[13:41:57.048] <TB3> INFO: *** Welcome to pxar ***
[13:41:57.048] <TB3> INFO: *** Today: 2016/10/26
[13:41:57.055] <TB3> INFO: *** Version: c8ba-dirty
[13:41:57.055] <TB3> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C15.dat
[13:41:57.055] <TB3> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[13:41:57.055] <TB3> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//defaultMaskFile.dat
[13:41:57.055] <TB3> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters_C15.dat
[13:41:57.112] <TB3> INFO: clk: 4
[13:41:57.112] <TB3> INFO: ctr: 4
[13:41:57.112] <TB3> INFO: sda: 19
[13:41:57.112] <TB3> INFO: tin: 9
[13:41:57.112] <TB3> INFO: level: 15
[13:41:57.112] <TB3> INFO: triggerdelay: 0
[13:41:57.112] <TB3> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[13:41:57.112] <TB3> INFO: Log level: INFO
[13:41:57.121] <TB3> INFO: Found DTB DTB_WZ4I6J
[13:41:57.129] <TB3> QUIET: Connection to board DTB_WZ4I6J opened.
[13:41:57.131] <TB3> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 170
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WZ4I6J
MAC address: 40D8551180AA
Hostname: pixelDTB170
Comment:
------------------------------------------------------
[13:41:57.133] <TB3> INFO: RPC call hashes of host and DTB match: 486171790
[13:41:58.654] <TB3> INFO: DUT info:
[13:41:58.654] <TB3> INFO: The DUT currently contains the following objects:
[13:41:58.654] <TB3> INFO: 4 TBM Cores tbm10c (4 ON)
[13:41:58.654] <TB3> INFO: TBM Core alpha (0): 7 registers set
[13:41:58.654] <TB3> INFO: TBM Core beta (1): 7 registers set
[13:41:58.654] <TB3> INFO: TBM Core alpha (2): 7 registers set
[13:41:58.654] <TB3> INFO: TBM Core beta (3): 7 registers set
[13:41:58.654] <TB3> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[13:41:58.654] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:58.654] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:58.654] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:58.654] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:58.654] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:58.654] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:58.654] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:58.654] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:58.654] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:58.654] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:58.654] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:58.654] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:58.654] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:58.655] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:58.655] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:58.655] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:59.055] <TB3> INFO: enter 'restricted' command line mode
[13:41:59.055] <TB3> INFO: enter test to run
[13:41:59.055] <TB3> INFO: test: pretest no parameter change
[13:41:59.056] <TB3> INFO: running: pretest
[13:41:59.664] <TB3> INFO: ######################################################################
[13:41:59.664] <TB3> INFO: PixTestPretest::doTest()
[13:41:59.664] <TB3> INFO: ######################################################################
[13:41:59.665] <TB3> INFO: ----------------------------------------------------------------------
[13:41:59.666] <TB3> INFO: PixTestPretest::programROC()
[13:41:59.666] <TB3> INFO: ----------------------------------------------------------------------
[13:42:17.679] <TB3> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[13:42:17.679] <TB3> INFO: IA differences per ROC: 18.5 17.7 18.5 16.9 17.7 19.3 20.9 17.7 20.1 20.9 17.7 19.3 20.9 19.3 21.7 18.5
[13:42:17.713] <TB3> INFO: ----------------------------------------------------------------------
[13:42:17.714] <TB3> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[13:42:17.714] <TB3> INFO: ----------------------------------------------------------------------
[13:42:24.593] <TB3> INFO: PixTestPretest::setVana() done, Module Ia 389.1 mA = 24.3188 mA/ROC
[13:42:24.593] <TB3> INFO: i(loss) [mA/ROC]: 20.1 19.3 19.3 19.3 20.1 19.3 20.1 19.3 19.3 19.3 19.3 20.1 19.3 19.3 19.3 20.1
[13:42:24.622] <TB3> INFO: ----------------------------------------------------------------------
[13:42:24.622] <TB3> INFO: PixTestPretest::findTiming()
[13:42:24.622] <TB3> INFO: ----------------------------------------------------------------------
[13:42:24.622] <TB3> INFO: PixTestCmd::init()

[13:42:55.947] <TB3> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[13:42:55.947] <TB3> INFO: (success/tries = 100/100), width = 4
[13:42:57.447] <TB3> INFO: ----------------------------------------------------------------------
[13:42:57.447] <TB3> INFO: PixTestPretest::findWorkingPixel()
[13:42:57.447] <TB3> INFO: ----------------------------------------------------------------------
[13:42:57.538] <TB3> INFO: Expecting 231680 events.
[13:43:07.149] <TB3> INFO: 231680 events read in total (9019ms).
[13:43:07.156] <TB3> INFO: Test took 9707ms.
[13:43:07.401] <TB3> INFO: Found working pixel in all ROCs: col/row = 12/22
[13:43:07.432] <TB3> INFO: ----------------------------------------------------------------------
[13:43:07.432] <TB3> INFO: PixTestPretest::setVthrCompCalDel()
[13:43:07.432] <TB3> INFO: ----------------------------------------------------------------------
[13:43:07.524] <TB3> INFO: Expecting 231680 events.
[13:43:17.190] <TB3> INFO: 231680 events read in total (9074ms).
[13:43:17.200] <TB3> INFO: Test took 9764ms.
[13:43:17.458] <TB3> INFO: PixTestPretest::setVthrCompCalDel() done
[13:43:17.458] <TB3> INFO: CalDel: 80 78 81 92 81 82 92 78 93 88 86 109 100 91 92 84
[13:43:17.458] <TB3> INFO: VthrComp: 52 53 51 51 51 51 51 51 56 56 51 51 51 51 53 51
[13:43:17.461] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C0.dat
[13:43:17.461] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C1.dat
[13:43:17.461] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C2.dat
[13:43:17.461] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C3.dat
[13:43:17.461] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C4.dat
[13:43:17.461] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C5.dat
[13:43:17.461] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C6.dat
[13:43:17.462] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C7.dat
[13:43:17.462] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C8.dat
[13:43:17.462] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C9.dat
[13:43:17.462] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C10.dat
[13:43:17.462] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C11.dat
[13:43:17.462] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C12.dat
[13:43:17.462] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C13.dat
[13:43:17.462] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C14.dat
[13:43:17.462] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C15.dat
[13:43:17.463] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[13:43:17.463] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[13:43:17.463] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[13:43:17.463] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[13:43:17.463] <TB3> INFO: PixTestPretest::doTest() done, duration: 78 seconds
[13:43:17.594] <TB3> INFO: enter test to run
[13:43:17.595] <TB3> INFO: test: fulltest no parameter change
[13:43:17.595] <TB3> INFO: running: fulltest
[13:43:17.595] <TB3> INFO: ######################################################################
[13:43:17.595] <TB3> INFO: PixTestFullTest::doTest()
[13:43:17.595] <TB3> INFO: ######################################################################
[13:43:17.596] <TB3> INFO: ######################################################################
[13:43:17.596] <TB3> INFO: PixTestAlive::doTest()
[13:43:17.596] <TB3> INFO: ######################################################################
[13:43:17.597] <TB3> INFO: ----------------------------------------------------------------------
[13:43:17.597] <TB3> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:43:17.597] <TB3> INFO: ----------------------------------------------------------------------
[13:43:17.830] <TB3> INFO: Expecting 41600 events.
[13:43:21.391] <TB3> INFO: 41600 events read in total (2969ms).
[13:43:21.392] <TB3> INFO: Test took 3794ms.
[13:43:21.618] <TB3> INFO: PixTestAlive::aliveTest() done
[13:43:21.618] <TB3> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
[13:43:21.619] <TB3> INFO: ----------------------------------------------------------------------
[13:43:21.619] <TB3> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:43:21.619] <TB3> INFO: ----------------------------------------------------------------------
[13:43:21.852] <TB3> INFO: Expecting 41600 events.
[13:43:24.776] <TB3> INFO: 41600 events read in total (2333ms).
[13:43:24.776] <TB3> INFO: Test took 3156ms.
[13:43:24.776] <TB3> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[13:43:25.016] <TB3> INFO: PixTestAlive::maskTest() done
[13:43:25.016] <TB3> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:43:25.018] <TB3> INFO: ----------------------------------------------------------------------
[13:43:25.018] <TB3> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:43:25.018] <TB3> INFO: ----------------------------------------------------------------------
[13:43:25.250] <TB3> INFO: Expecting 41600 events.
[13:43:28.722] <TB3> INFO: 41600 events read in total (2880ms).
[13:43:28.723] <TB3> INFO: Test took 3704ms.
[13:43:28.952] <TB3> INFO: PixTestAlive::addressDecodingTest() done
[13:43:28.952] <TB3> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:43:28.952] <TB3> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[13:43:28.952] <TB3> INFO: Decoding statistics:
[13:43:28.952] <TB3> INFO: General information:
[13:43:28.952] <TB3> INFO: 16bit words read: 0
[13:43:28.952] <TB3> INFO: valid events total: 0
[13:43:28.952] <TB3> INFO: empty events: 0
[13:43:28.952] <TB3> INFO: valid events with pixels: 0
[13:43:28.952] <TB3> INFO: valid pixel hits: 0
[13:43:28.952] <TB3> INFO: Event errors: 0
[13:43:28.952] <TB3> INFO: start marker: 0
[13:43:28.952] <TB3> INFO: stop marker: 0
[13:43:28.952] <TB3> INFO: overflow: 0
[13:43:28.952] <TB3> INFO: invalid 5bit words: 0
[13:43:28.952] <TB3> INFO: invalid XOR eye diagram: 0
[13:43:28.952] <TB3> INFO: frame (failed synchr.): 0
[13:43:28.952] <TB3> INFO: idle data (no TBM trl): 0
[13:43:28.952] <TB3> INFO: no data (only TBM hdr): 0
[13:43:28.952] <TB3> INFO: TBM errors: 0
[13:43:28.952] <TB3> INFO: flawed TBM headers: 0
[13:43:28.952] <TB3> INFO: flawed TBM trailers: 0
[13:43:28.952] <TB3> INFO: event ID mismatches: 0
[13:43:28.952] <TB3> INFO: ROC errors: 0
[13:43:28.952] <TB3> INFO: missing ROC header(s): 0
[13:43:28.952] <TB3> INFO: misplaced readback start: 0
[13:43:28.952] <TB3> INFO: Pixel decoding errors: 0
[13:43:28.952] <TB3> INFO: pixel data incomplete: 0
[13:43:28.952] <TB3> INFO: pixel address: 0
[13:43:28.952] <TB3> INFO: pulse height fill bit: 0
[13:43:28.952] <TB3> INFO: buffer corruption: 0
[13:43:28.959] <TB3> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:43:28.960] <TB3> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[13:43:28.960] <TB3> INFO: ######################################################################
[13:43:28.960] <TB3> INFO: PixTestReadback::doTest()
[13:43:28.960] <TB3> INFO: ######################################################################
[13:43:28.960] <TB3> INFO: ----------------------------------------------------------------------
[13:43:28.960] <TB3> INFO: PixTestReadback::CalibrateVd()
[13:43:28.960] <TB3> INFO: ----------------------------------------------------------------------
[13:43:38.929] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C0.dat
[13:43:38.929] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C1.dat
[13:43:38.929] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C2.dat
[13:43:38.929] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C3.dat
[13:43:38.929] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C4.dat
[13:43:38.929] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C5.dat
[13:43:38.929] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C6.dat
[13:43:38.929] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C7.dat
[13:43:38.929] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C8.dat
[13:43:38.929] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C9.dat
[13:43:38.929] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C10.dat
[13:43:38.930] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C11.dat
[13:43:38.930] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C12.dat
[13:43:38.930] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C13.dat
[13:43:38.930] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C14.dat
[13:43:38.930] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:43:38.958] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[13:43:38.958] <TB3> INFO: ----------------------------------------------------------------------
[13:43:38.958] <TB3> INFO: PixTestReadback::CalibrateVa()
[13:43:38.958] <TB3> INFO: ----------------------------------------------------------------------
[13:43:48.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C0.dat
[13:43:48.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C1.dat
[13:43:48.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C2.dat
[13:43:48.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C3.dat
[13:43:48.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C4.dat
[13:43:48.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C5.dat
[13:43:48.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C6.dat
[13:43:48.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C7.dat
[13:43:48.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C8.dat
[13:43:48.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C9.dat
[13:43:48.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C10.dat
[13:43:48.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C11.dat
[13:43:48.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C12.dat
[13:43:48.848] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C13.dat
[13:43:48.849] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C14.dat
[13:43:48.849] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:43:48.877] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[13:43:48.877] <TB3> INFO: ----------------------------------------------------------------------
[13:43:48.877] <TB3> INFO: PixTestReadback::readbackVbg()
[13:43:48.877] <TB3> INFO: ----------------------------------------------------------------------
[13:43:56.518] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[13:43:56.518] <TB3> INFO: ----------------------------------------------------------------------
[13:43:56.518] <TB3> INFO: PixTestReadback::getCalibratedVbg()
[13:43:56.518] <TB3> INFO: ----------------------------------------------------------------------
[13:43:56.518] <TB3> INFO: Vbg will be calibrated using Vd calibration
[13:43:56.518] <TB3> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 154.7calibrated Vbg = 1.17559 :::*/*/*/*/
[13:43:56.518] <TB3> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 150.9calibrated Vbg = 1.17505 :::*/*/*/*/
[13:43:56.518] <TB3> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 155.2calibrated Vbg = 1.1698 :::*/*/*/*/
[13:43:56.518] <TB3> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 155calibrated Vbg = 1.16289 :::*/*/*/*/
[13:43:56.518] <TB3> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 153.1calibrated Vbg = 1.16741 :::*/*/*/*/
[13:43:56.518] <TB3> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 158.1calibrated Vbg = 1.17185 :::*/*/*/*/
[13:43:56.518] <TB3> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 157.9calibrated Vbg = 1.17064 :::*/*/*/*/
[13:43:56.518] <TB3> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 155.1calibrated Vbg = 1.17253 :::*/*/*/*/
[13:43:56.518] <TB3> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 160calibrated Vbg = 1.17136 :::*/*/*/*/
[13:43:56.518] <TB3> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 154.6calibrated Vbg = 1.17105 :::*/*/*/*/
[13:43:56.518] <TB3> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 148.6calibrated Vbg = 1.15447 :::*/*/*/*/
[13:43:56.518] <TB3> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 149.4calibrated Vbg = 1.16776 :::*/*/*/*/
[13:43:56.518] <TB3> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 160.6calibrated Vbg = 1.17146 :::*/*/*/*/
[13:43:56.518] <TB3> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 152.4calibrated Vbg = 1.17225 :::*/*/*/*/
[13:43:56.518] <TB3> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 163calibrated Vbg = 1.17372 :::*/*/*/*/
[13:43:56.518] <TB3> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 159.5calibrated Vbg = 1.16441 :::*/*/*/*/
[13:43:56.520] <TB3> INFO: ----------------------------------------------------------------------
[13:43:56.520] <TB3> INFO: PixTestReadback::CalibrateIa()
[13:43:56.520] <TB3> INFO: ----------------------------------------------------------------------
[13:46:36.837] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C0.dat
[13:46:36.837] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C1.dat
[13:46:36.837] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C2.dat
[13:46:36.837] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C3.dat
[13:46:36.837] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C4.dat
[13:46:36.837] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C5.dat
[13:46:36.838] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C6.dat
[13:46:36.838] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C7.dat
[13:46:36.838] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C8.dat
[13:46:36.838] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C9.dat
[13:46:36.838] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C10.dat
[13:46:36.838] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C11.dat
[13:46:36.838] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C12.dat
[13:46:36.838] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C13.dat
[13:46:36.838] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C14.dat
[13:46:36.838] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:46:36.865] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[13:46:36.866] <TB3> INFO: PixTestReadback::doTest() done
[13:46:36.867] <TB3> INFO: Decoding statistics:
[13:46:36.867] <TB3> INFO: General information:
[13:46:36.867] <TB3> INFO: 16bit words read: 1536
[13:46:36.867] <TB3> INFO: valid events total: 256
[13:46:36.867] <TB3> INFO: empty events: 256
[13:46:36.867] <TB3> INFO: valid events with pixels: 0
[13:46:36.867] <TB3> INFO: valid pixel hits: 0
[13:46:36.867] <TB3> INFO: Event errors: 0
[13:46:36.867] <TB3> INFO: start marker: 0
[13:46:36.867] <TB3> INFO: stop marker: 0
[13:46:36.867] <TB3> INFO: overflow: 0
[13:46:36.867] <TB3> INFO: invalid 5bit words: 0
[13:46:36.867] <TB3> INFO: invalid XOR eye diagram: 0
[13:46:36.867] <TB3> INFO: frame (failed synchr.): 0
[13:46:36.867] <TB3> INFO: idle data (no TBM trl): 0
[13:46:36.867] <TB3> INFO: no data (only TBM hdr): 0
[13:46:36.867] <TB3> INFO: TBM errors: 0
[13:46:36.867] <TB3> INFO: flawed TBM headers: 0
[13:46:36.867] <TB3> INFO: flawed TBM trailers: 0
[13:46:36.867] <TB3> INFO: event ID mismatches: 0
[13:46:36.867] <TB3> INFO: ROC errors: 0
[13:46:36.867] <TB3> INFO: missing ROC header(s): 0
[13:46:36.867] <TB3> INFO: misplaced readback start: 0
[13:46:36.867] <TB3> INFO: Pixel decoding errors: 0
[13:46:36.867] <TB3> INFO: pixel data incomplete: 0
[13:46:36.867] <TB3> INFO: pixel address: 0
[13:46:36.867] <TB3> INFO: pulse height fill bit: 0
[13:46:36.867] <TB3> INFO: buffer corruption: 0
[13:46:36.901] <TB3> INFO: ######################################################################
[13:46:36.901] <TB3> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[13:46:36.901] <TB3> INFO: ######################################################################
[13:46:36.903] <TB3> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[13:46:36.915] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[13:46:36.915] <TB3> INFO: run 1 of 1
[13:46:37.147] <TB3> INFO: Expecting 3120000 events.
[13:47:07.342] <TB3> INFO: 668170 events read in total (29604ms).











[13:47:36.603] <TB3> INFO: 1333040 events read in total (58865ms).











[13:48:06.148] <TB3> INFO: 1993700 events read in total (88410ms).











[13:48:35.803] <TB3> INFO: 2652620 events read in total (118065ms).











[13:48:57.445] <TB3> INFO: 3120000 events read in total (139707ms).
[13:48:57.513] <TB3> INFO: Test took 140599ms.
[13:49:24.447] <TB3> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 167 seconds
[13:49:24.447] <TB3> INFO: number of dead bumps (per ROC): 1 0 0 0 0 0 0 9 3 0 0 0 0 1 0 0
[13:49:24.447] <TB3> INFO: separation cut (per ROC): 107 106 105 106 105 105 111 102 110 108 101 108 104 106 113 108
[13:49:24.447] <TB3> INFO: Decoding statistics:
[13:49:24.447] <TB3> INFO: General information:
[13:49:24.447] <TB3> INFO: 16bit words read: 0
[13:49:24.447] <TB3> INFO: valid events total: 0
[13:49:24.447] <TB3> INFO: empty events: 0
[13:49:24.447] <TB3> INFO: valid events with pixels: 0
[13:49:24.447] <TB3> INFO: valid pixel hits: 0
[13:49:24.447] <TB3> INFO: Event errors: 0
[13:49:24.447] <TB3> INFO: start marker: 0
[13:49:24.447] <TB3> INFO: stop marker: 0
[13:49:24.447] <TB3> INFO: overflow: 0
[13:49:24.447] <TB3> INFO: invalid 5bit words: 0
[13:49:24.447] <TB3> INFO: invalid XOR eye diagram: 0
[13:49:24.447] <TB3> INFO: frame (failed synchr.): 0
[13:49:24.447] <TB3> INFO: idle data (no TBM trl): 0
[13:49:24.447] <TB3> INFO: no data (only TBM hdr): 0
[13:49:24.447] <TB3> INFO: TBM errors: 0
[13:49:24.447] <TB3> INFO: flawed TBM headers: 0
[13:49:24.447] <TB3> INFO: flawed TBM trailers: 0
[13:49:24.447] <TB3> INFO: event ID mismatches: 0
[13:49:24.447] <TB3> INFO: ROC errors: 0
[13:49:24.447] <TB3> INFO: missing ROC header(s): 0
[13:49:24.447] <TB3> INFO: misplaced readback start: 0
[13:49:24.447] <TB3> INFO: Pixel decoding errors: 0
[13:49:24.447] <TB3> INFO: pixel data incomplete: 0
[13:49:24.447] <TB3> INFO: pixel address: 0
[13:49:24.447] <TB3> INFO: pulse height fill bit: 0
[13:49:24.447] <TB3> INFO: buffer corruption: 0
[13:49:24.497] <TB3> INFO: ######################################################################
[13:49:24.497] <TB3> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:49:24.498] <TB3> INFO: ######################################################################
[13:49:24.498] <TB3> INFO: ----------------------------------------------------------------------
[13:49:24.498] <TB3> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:49:24.498] <TB3> INFO: ----------------------------------------------------------------------
[13:49:24.498] <TB3> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[13:49:24.509] <TB3> INFO: dacScan split into 1 runs with ntrig = 50
[13:49:24.509] <TB3> INFO: run 1 of 1
[13:49:24.783] <TB3> INFO: Expecting 36608000 events.
[13:49:47.885] <TB3> INFO: 695900 events read in total (22511ms).
[13:50:10.380] <TB3> INFO: 1377750 events read in total (45006ms).
[13:50:32.745] <TB3> INFO: 2058900 events read in total (67371ms).
[13:50:55.420] <TB3> INFO: 2740600 events read in total (90046ms).
[13:51:17.643] <TB3> INFO: 3420100 events read in total (112269ms).
[13:51:40.224] <TB3> INFO: 4097750 events read in total (134850ms).
[13:52:02.483] <TB3> INFO: 4777300 events read in total (157109ms).
[13:52:24.811] <TB3> INFO: 5455500 events read in total (179437ms).
[13:52:47.480] <TB3> INFO: 6134150 events read in total (202106ms).
[13:53:10.202] <TB3> INFO: 6812300 events read in total (224828ms).
[13:53:32.892] <TB3> INFO: 7491050 events read in total (247518ms).
[13:53:55.302] <TB3> INFO: 8168200 events read in total (269928ms).
[13:54:17.704] <TB3> INFO: 8845600 events read in total (292330ms).
[13:54:40.009] <TB3> INFO: 9522100 events read in total (314635ms).
[13:55:02.412] <TB3> INFO: 10198450 events read in total (337038ms).
[13:55:24.830] <TB3> INFO: 10874350 events read in total (359456ms).
[13:55:47.466] <TB3> INFO: 11550550 events read in total (382092ms).
[13:56:09.828] <TB3> INFO: 12224750 events read in total (404454ms).
[13:56:32.341] <TB3> INFO: 12899700 events read in total (426967ms).
[13:56:54.831] <TB3> INFO: 13576500 events read in total (449457ms).
[13:57:17.236] <TB3> INFO: 14251750 events read in total (471862ms).
[13:57:39.862] <TB3> INFO: 14924250 events read in total (494488ms).
[13:58:02.505] <TB3> INFO: 15599200 events read in total (517131ms).
[13:58:24.740] <TB3> INFO: 16272300 events read in total (539366ms).
[13:58:47.224] <TB3> INFO: 16946300 events read in total (561850ms).
[13:59:09.672] <TB3> INFO: 17621050 events read in total (584298ms).
[13:59:32.139] <TB3> INFO: 18293000 events read in total (606765ms).
[13:59:54.534] <TB3> INFO: 18963500 events read in total (629160ms).
[14:00:16.707] <TB3> INFO: 19635150 events read in total (651333ms).
[14:00:39.386] <TB3> INFO: 20306650 events read in total (674012ms).
[14:01:01.785] <TB3> INFO: 20976800 events read in total (696411ms).
[14:01:24.208] <TB3> INFO: 21647850 events read in total (718834ms).
[14:01:46.636] <TB3> INFO: 22318300 events read in total (741262ms).
[14:02:09.089] <TB3> INFO: 22990100 events read in total (763715ms).
[14:02:31.541] <TB3> INFO: 23660650 events read in total (786167ms).
[14:02:54.093] <TB3> INFO: 24330850 events read in total (808719ms).
[14:03:16.897] <TB3> INFO: 25000800 events read in total (831523ms).
[14:03:38.935] <TB3> INFO: 25670900 events read in total (853561ms).
[14:04:01.268] <TB3> INFO: 26341150 events read in total (875894ms).
[14:04:23.898] <TB3> INFO: 27010950 events read in total (898524ms).
[14:04:46.075] <TB3> INFO: 27678300 events read in total (920701ms).
[14:05:08.374] <TB3> INFO: 28345900 events read in total (943000ms).
[14:05:30.693] <TB3> INFO: 29014900 events read in total (965319ms).
[14:05:53.252] <TB3> INFO: 29681850 events read in total (987878ms).
[14:06:15.685] <TB3> INFO: 30350350 events read in total (1010311ms).
[14:06:38.169] <TB3> INFO: 31019250 events read in total (1032795ms).
[14:07:00.538] <TB3> INFO: 31687550 events read in total (1055164ms).
[14:07:22.944] <TB3> INFO: 32356950 events read in total (1077570ms).
[14:07:45.696] <TB3> INFO: 33027200 events read in total (1100322ms).
[14:08:08.322] <TB3> INFO: 33699450 events read in total (1122948ms).
[14:08:30.877] <TB3> INFO: 34370300 events read in total (1145503ms).
[14:08:53.218] <TB3> INFO: 35040150 events read in total (1167844ms).
[14:09:15.853] <TB3> INFO: 35712400 events read in total (1190479ms).
[14:09:39.152] <TB3> INFO: 36394250 events read in total (1213778ms).
[14:09:46.744] <TB3> INFO: 36608000 events read in total (1221370ms).
[14:09:46.800] <TB3> INFO: Test took 1222292ms.
[14:09:47.390] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:09:49.363] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:09:51.546] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:09:53.677] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:09:55.467] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:09:57.803] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:09:59.958] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:10:01.910] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:10:03.846] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:10:06.050] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:10:07.982] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:10:10.024] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:10:11.833] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:10:13.504] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:10:15.525] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:10:17.587] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[14:10:19.098] <TB3> INFO: PixTestScurves::scurves() done
[14:10:19.098] <TB3> INFO: Vcal mean: 127.73 133.10 119.10 132.10 119.26 122.01 125.14 110.12 131.44 130.07 110.73 124.25 125.94 124.88 133.38 125.24
[14:10:19.098] <TB3> INFO: Vcal RMS: 6.49 6.98 6.09 6.06 6.88 6.54 6.11 5.19 8.27 7.36 4.92 6.38 6.22 5.67 7.83 6.57
[14:10:19.098] <TB3> INFO: PixTestScurves::fullTest() done, duration: 1254 seconds
[14:10:19.098] <TB3> INFO: Decoding statistics:
[14:10:19.098] <TB3> INFO: General information:
[14:10:19.098] <TB3> INFO: 16bit words read: 0
[14:10:19.098] <TB3> INFO: valid events total: 0
[14:10:19.098] <TB3> INFO: empty events: 0
[14:10:19.098] <TB3> INFO: valid events with pixels: 0
[14:10:19.098] <TB3> INFO: valid pixel hits: 0
[14:10:19.098] <TB3> INFO: Event errors: 0
[14:10:19.098] <TB3> INFO: start marker: 0
[14:10:19.098] <TB3> INFO: stop marker: 0
[14:10:19.098] <TB3> INFO: overflow: 0
[14:10:19.098] <TB3> INFO: invalid 5bit words: 0
[14:10:19.098] <TB3> INFO: invalid XOR eye diagram: 0
[14:10:19.098] <TB3> INFO: frame (failed synchr.): 0
[14:10:19.098] <TB3> INFO: idle data (no TBM trl): 0
[14:10:19.098] <TB3> INFO: no data (only TBM hdr): 0
[14:10:19.098] <TB3> INFO: TBM errors: 0
[14:10:19.098] <TB3> INFO: flawed TBM headers: 0
[14:10:19.098] <TB3> INFO: flawed TBM trailers: 0
[14:10:19.098] <TB3> INFO: event ID mismatches: 0
[14:10:19.098] <TB3> INFO: ROC errors: 0
[14:10:19.099] <TB3> INFO: missing ROC header(s): 0
[14:10:19.099] <TB3> INFO: misplaced readback start: 0
[14:10:19.099] <TB3> INFO: Pixel decoding errors: 0
[14:10:19.099] <TB3> INFO: pixel data incomplete: 0
[14:10:19.099] <TB3> INFO: pixel address: 0
[14:10:19.099] <TB3> INFO: pulse height fill bit: 0
[14:10:19.099] <TB3> INFO: buffer corruption: 0
[14:10:19.163] <TB3> INFO: ######################################################################
[14:10:19.163] <TB3> INFO: PixTestTrim::doTest()
[14:10:19.163] <TB3> INFO: ######################################################################
[14:10:19.164] <TB3> INFO: ----------------------------------------------------------------------
[14:10:19.164] <TB3> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[14:10:19.164] <TB3> INFO: ----------------------------------------------------------------------
[14:10:19.221] <TB3> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:10:19.221] <TB3> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:10:19.232] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[14:10:19.232] <TB3> INFO: run 1 of 1
[14:10:19.502] <TB3> INFO: Expecting 5025280 events.
[14:10:49.716] <TB3> INFO: 831016 events read in total (29622ms).
[14:11:19.422] <TB3> INFO: 1659648 events read in total (59328ms).
[14:11:48.865] <TB3> INFO: 2486304 events read in total (88772ms).
[14:12:18.542] <TB3> INFO: 3309728 events read in total (118448ms).
[14:12:47.928] <TB3> INFO: 4129208 events read in total (147834ms).
[14:13:18.241] <TB3> INFO: 4947784 events read in total (178147ms).
[14:13:21.562] <TB3> INFO: 5025280 events read in total (181468ms).
[14:13:21.606] <TB3> INFO: Test took 182374ms.
[14:13:38.127] <TB3> INFO: ROC 0 VthrComp = 131
[14:13:38.127] <TB3> INFO: ROC 1 VthrComp = 129
[14:13:38.127] <TB3> INFO: ROC 2 VthrComp = 124
[14:13:38.127] <TB3> INFO: ROC 3 VthrComp = 132
[14:13:38.127] <TB3> INFO: ROC 4 VthrComp = 120
[14:13:38.127] <TB3> INFO: ROC 5 VthrComp = 119
[14:13:38.127] <TB3> INFO: ROC 6 VthrComp = 132
[14:13:38.127] <TB3> INFO: ROC 7 VthrComp = 109
[14:13:38.127] <TB3> INFO: ROC 8 VthrComp = 126
[14:13:38.127] <TB3> INFO: ROC 9 VthrComp = 132
[14:13:38.128] <TB3> INFO: ROC 10 VthrComp = 108
[14:13:38.128] <TB3> INFO: ROC 11 VthrComp = 124
[14:13:38.128] <TB3> INFO: ROC 12 VthrComp = 127
[14:13:38.128] <TB3> INFO: ROC 13 VthrComp = 124
[14:13:38.128] <TB3> INFO: ROC 14 VthrComp = 132
[14:13:38.128] <TB3> INFO: ROC 15 VthrComp = 126
[14:13:38.398] <TB3> INFO: Expecting 41600 events.
[14:13:42.023] <TB3> INFO: 41600 events read in total (3034ms).
[14:13:42.024] <TB3> INFO: Test took 3894ms.
[14:13:42.032] <TB3> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:13:42.032] <TB3> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:13:42.042] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[14:13:42.042] <TB3> INFO: run 1 of 1
[14:13:42.320] <TB3> INFO: Expecting 5025280 events.
[14:14:08.424] <TB3> INFO: 590464 events read in total (25513ms).
[14:14:33.808] <TB3> INFO: 1179024 events read in total (50897ms).
[14:14:59.297] <TB3> INFO: 1768336 events read in total (76386ms).
[14:15:24.551] <TB3> INFO: 2357072 events read in total (101640ms).
[14:15:49.943] <TB3> INFO: 2943768 events read in total (127032ms).
[14:16:15.104] <TB3> INFO: 3529616 events read in total (152193ms).
[14:16:40.384] <TB3> INFO: 4115624 events read in total (177473ms).
[14:17:05.967] <TB3> INFO: 4701184 events read in total (203056ms).
[14:17:21.006] <TB3> INFO: 5025280 events read in total (218095ms).
[14:17:21.085] <TB3> INFO: Test took 219043ms.
[14:17:48.075] <TB3> INFO: roc 0 with ID = 0 has maximal Vcal 61.331 for pixel 4/8 mean/min/max = 46.5216/31.6102/61.433
[14:17:48.075] <TB3> INFO: roc 1 with ID = 1 has maximal Vcal 64.2222 for pixel 24/17 mean/min/max = 48.2846/32.2664/64.3028
[14:17:48.075] <TB3> INFO: roc 2 with ID = 2 has maximal Vcal 59.0392 for pixel 4/1 mean/min/max = 45.8001/32.4662/59.134
[14:17:48.076] <TB3> INFO: roc 3 with ID = 3 has maximal Vcal 62.0916 for pixel 0/76 mean/min/max = 46.92/31.575/62.2651
[14:17:48.076] <TB3> INFO: roc 4 with ID = 4 has maximal Vcal 61.014 for pixel 0/0 mean/min/max = 46.5071/31.9354/61.0788
[14:17:48.076] <TB3> INFO: roc 5 with ID = 5 has maximal Vcal 61.3178 for pixel 7/10 mean/min/max = 46.5051/31.5163/61.4939
[14:17:48.077] <TB3> INFO: roc 6 with ID = 6 has maximal Vcal 58.229 for pixel 50/6 mean/min/max = 44.9766/31.6769/58.2764
[14:17:48.077] <TB3> INFO: roc 7 with ID = 7 has maximal Vcal 62.3093 for pixel 6/79 mean/min/max = 48.2927/34.2535/62.3318
[14:17:48.077] <TB3> INFO: roc 8 with ID = 8 has maximal Vcal 64.6029 for pixel 10/71 mean/min/max = 48.0084/31.2823/64.7346
[14:17:48.077] <TB3> INFO: roc 9 with ID = 9 has maximal Vcal 62.3786 for pixel 2/25 mean/min/max = 46.7862/31.1088/62.4637
[14:17:48.078] <TB3> INFO: roc 10 with ID = 10 has maximal Vcal 63.4247 for pixel 4/76 mean/min/max = 49.6466/35.8435/63.4497
[14:17:48.078] <TB3> INFO: roc 11 with ID = 11 has maximal Vcal 60.5643 for pixel 24/21 mean/min/max = 47.0099/33.4002/60.6196
[14:17:48.078] <TB3> INFO: roc 12 with ID = 12 has maximal Vcal 59.3015 for pixel 0/43 mean/min/max = 45.1675/30.9363/59.3988
[14:17:48.079] <TB3> INFO: roc 13 with ID = 13 has maximal Vcal 59.1775 for pixel 32/4 mean/min/max = 45.8336/32.4651/59.202
[14:17:48.079] <TB3> INFO: roc 14 with ID = 14 has maximal Vcal 64.6642 for pixel 31/33 mean/min/max = 50.462/35.7186/65.2054
[14:17:48.079] <TB3> INFO: roc 15 with ID = 15 has maximal Vcal 59.934 for pixel 9/16 mean/min/max = 45.894/31.5181/60.2698
[14:17:48.080] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:17:48.168] <TB3> INFO: Expecting 411648 events.
[14:17:57.401] <TB3> INFO: 411648 events read in total (8641ms).
[14:17:57.407] <TB3> INFO: Expecting 411648 events.
[14:18:06.501] <TB3> INFO: 411648 events read in total (8691ms).
[14:18:06.511] <TB3> INFO: Expecting 411648 events.
[14:18:15.556] <TB3> INFO: 411648 events read in total (8642ms).
[14:18:15.567] <TB3> INFO: Expecting 411648 events.
[14:18:24.658] <TB3> INFO: 411648 events read in total (8688ms).
[14:18:24.676] <TB3> INFO: Expecting 411648 events.
[14:18:33.679] <TB3> INFO: 411648 events read in total (8600ms).
[14:18:33.694] <TB3> INFO: Expecting 411648 events.
[14:18:42.798] <TB3> INFO: 411648 events read in total (8701ms).
[14:18:42.823] <TB3> INFO: Expecting 411648 events.
[14:18:51.927] <TB3> INFO: 411648 events read in total (8701ms).
[14:18:51.956] <TB3> INFO: Expecting 411648 events.
[14:19:01.054] <TB3> INFO: 411648 events read in total (8695ms).
[14:19:01.085] <TB3> INFO: Expecting 411648 events.
[14:19:10.105] <TB3> INFO: 411648 events read in total (8617ms).
[14:19:10.131] <TB3> INFO: Expecting 411648 events.
[14:19:19.140] <TB3> INFO: 411648 events read in total (8606ms).
[14:19:19.171] <TB3> INFO: Expecting 411648 events.
[14:19:28.225] <TB3> INFO: 411648 events read in total (8651ms).
[14:19:28.256] <TB3> INFO: Expecting 411648 events.
[14:19:37.305] <TB3> INFO: 411648 events read in total (8646ms).
[14:19:37.340] <TB3> INFO: Expecting 411648 events.
[14:19:46.395] <TB3> INFO: 411648 events read in total (8652ms).
[14:19:46.430] <TB3> INFO: Expecting 411648 events.
[14:19:55.476] <TB3> INFO: 411648 events read in total (8643ms).
[14:19:55.516] <TB3> INFO: Expecting 411648 events.
[14:20:04.610] <TB3> INFO: 411648 events read in total (8691ms).
[14:20:04.651] <TB3> INFO: Expecting 411648 events.
[14:20:13.753] <TB3> INFO: 411648 events read in total (8699ms).
[14:20:13.798] <TB3> INFO: Test took 145718ms.
[14:20:14.482] <TB3> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:20:14.491] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[14:20:14.491] <TB3> INFO: run 1 of 1
[14:20:14.724] <TB3> INFO: Expecting 5025280 events.
[14:20:40.783] <TB3> INFO: 591312 events read in total (25467ms).
[14:21:06.434] <TB3> INFO: 1182400 events read in total (51118ms).
[14:21:32.120] <TB3> INFO: 1770304 events read in total (76804ms).
[14:21:57.733] <TB3> INFO: 2356264 events read in total (102417ms).
[14:22:23.270] <TB3> INFO: 2942192 events read in total (127955ms).
[14:22:48.931] <TB3> INFO: 3530712 events read in total (153615ms).
[14:23:14.339] <TB3> INFO: 4119208 events read in total (179023ms).
[14:23:40.374] <TB3> INFO: 4707680 events read in total (205058ms).
[14:23:54.876] <TB3> INFO: 5025280 events read in total (219560ms).
[14:23:54.987] <TB3> INFO: Test took 220497ms.
[14:24:19.587] <TB3> INFO: ---> TrimStepCorr4 extremal thresholds: 1.842413 .. 146.680931
[14:24:19.822] <TB3> INFO: Expecting 208000 events.
[14:24:29.206] <TB3> INFO: 208000 events read in total (8792ms).
[14:24:29.207] <TB3> INFO: Test took 9618ms.
[14:24:29.253] <TB3> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 1 .. 156 (-1/-1) hits flags = 528 (plus default)
[14:24:29.261] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[14:24:29.261] <TB3> INFO: run 1 of 1
[14:24:29.539] <TB3> INFO: Expecting 5191680 events.
[14:24:55.197] <TB3> INFO: 584568 events read in total (25066ms).
[14:25:20.747] <TB3> INFO: 1168864 events read in total (50616ms).
[14:25:46.272] <TB3> INFO: 1753280 events read in total (76141ms).
[14:26:11.732] <TB3> INFO: 2338104 events read in total (101602ms).
[14:26:37.279] <TB3> INFO: 2922720 events read in total (127148ms).
[14:27:02.565] <TB3> INFO: 3506176 events read in total (152434ms).
[14:27:28.014] <TB3> INFO: 4090072 events read in total (177883ms).
[14:27:53.758] <TB3> INFO: 4673040 events read in total (203627ms).
[14:28:17.369] <TB3> INFO: 5191680 events read in total (227238ms).
[14:28:17.489] <TB3> INFO: Test took 228228ms.
[14:28:43.788] <TB3> INFO: ---> TrimStepCorr2 extremal thresholds: 26.671035 .. 47.467274
[14:28:44.021] <TB3> INFO: Expecting 208000 events.
[14:28:53.591] <TB3> INFO: 208000 events read in total (8978ms).
[14:28:53.592] <TB3> INFO: Test took 9802ms.
[14:28:53.640] <TB3> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 57 (-1/-1) hits flags = 528 (plus default)
[14:28:53.649] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[14:28:53.649] <TB3> INFO: run 1 of 1
[14:28:53.927] <TB3> INFO: Expecting 1397760 events.
[14:29:21.647] <TB3> INFO: 657048 events read in total (27128ms).
[14:29:49.262] <TB3> INFO: 1312760 events read in total (54744ms).
[14:29:53.085] <TB3> INFO: 1397760 events read in total (58566ms).
[14:29:53.111] <TB3> INFO: Test took 59463ms.
[14:30:06.337] <TB3> INFO: ---> TrimStepCorr1a extremal thresholds: 28.201457 .. 49.954131
[14:30:06.584] <TB3> INFO: Expecting 208000 events.
[14:30:16.432] <TB3> INFO: 208000 events read in total (9257ms).
[14:30:16.433] <TB3> INFO: Test took 10095ms.
[14:30:16.498] <TB3> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 18 .. 59 (-1/-1) hits flags = 528 (plus default)
[14:30:16.509] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[14:30:16.509] <TB3> INFO: run 1 of 1
[14:30:16.787] <TB3> INFO: Expecting 1397760 events.
[14:30:44.321] <TB3> INFO: 642320 events read in total (26942ms).
[14:31:11.990] <TB3> INFO: 1282856 events read in total (54611ms).
[14:31:16.977] <TB3> INFO: 1397760 events read in total (59598ms).
[14:31:17.004] <TB3> INFO: Test took 60496ms.
[14:31:29.824] <TB3> INFO: ---> TrimStepCorr1b extremal thresholds: 26.689879 .. 51.292665
[14:31:30.062] <TB3> INFO: Expecting 208000 events.
[14:31:39.811] <TB3> INFO: 208000 events read in total (9158ms).
[14:31:39.812] <TB3> INFO: Test took 9987ms.
[14:31:39.879] <TB3> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 61 (-1/-1) hits flags = 528 (plus default)
[14:31:39.890] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[14:31:39.891] <TB3> INFO: run 1 of 1
[14:31:40.168] <TB3> INFO: Expecting 1530880 events.
[14:32:07.258] <TB3> INFO: 643136 events read in total (26498ms).
[14:32:34.771] <TB3> INFO: 1285912 events read in total (54011ms).
[14:32:45.181] <TB3> INFO: 1530880 events read in total (64421ms).
[14:32:45.209] <TB3> INFO: Test took 65319ms.
[14:32:59.889] <TB3> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:32:59.889] <TB3> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:32:59.901] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[14:32:59.901] <TB3> INFO: run 1 of 1
[14:33:00.135] <TB3> INFO: Expecting 1364480 events.
[14:33:28.092] <TB3> INFO: 668712 events read in total (27365ms).
[14:33:56.213] <TB3> INFO: 1336760 events read in total (55486ms).
[14:33:57.790] <TB3> INFO: 1364480 events read in total (57064ms).
[14:33:57.821] <TB3> INFO: Test took 57920ms.
[14:34:11.496] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C0.dat
[14:34:11.496] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C1.dat
[14:34:11.496] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C2.dat
[14:34:11.496] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C3.dat
[14:34:11.496] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C4.dat
[14:34:11.496] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C5.dat
[14:34:11.496] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C6.dat
[14:34:11.496] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C7.dat
[14:34:11.497] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C8.dat
[14:34:11.497] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C9.dat
[14:34:11.497] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C10.dat
[14:34:11.497] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C11.dat
[14:34:11.497] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C12.dat
[14:34:11.497] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C13.dat
[14:34:11.497] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C14.dat
[14:34:11.497] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C15.dat
[14:34:11.497] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C0.dat
[14:34:11.503] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C1.dat
[14:34:11.508] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C2.dat
[14:34:11.514] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C3.dat
[14:34:11.519] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C4.dat
[14:34:11.524] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C5.dat
[14:34:11.530] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C6.dat
[14:34:11.536] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C7.dat
[14:34:11.541] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C8.dat
[14:34:11.547] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C9.dat
[14:34:11.552] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C10.dat
[14:34:11.558] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C11.dat
[14:34:11.563] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C12.dat
[14:34:11.569] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C13.dat
[14:34:11.574] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C14.dat
[14:34:11.580] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C15.dat
[14:34:11.585] <TB3> INFO: PixTestTrim::trimTest() done
[14:34:11.585] <TB3> INFO: vtrim: 142 160 113 126 111 132 145 132 125 132 135 147 112 110 178 128
[14:34:11.585] <TB3> INFO: vthrcomp: 131 129 124 132 120 119 132 109 126 132 108 124 127 124 132 126
[14:34:11.585] <TB3> INFO: vcal mean: 34.95 36.32 34.94 35.31 35.02 35.45 34.92 35.20 35.06 35.56 35.10 35.12 34.98 34.97 35.28 34.99
[14:34:11.585] <TB3> INFO: vcal RMS: 1.11 2.40 1.03 1.51 1.08 1.55 1.17 1.14 1.27 1.94 1.14 1.19 1.25 1.07 1.40 1.16
[14:34:11.585] <TB3> INFO: bits mean: 9.57 10.44 9.58 9.14 8.55 10.23 10.20 8.91 9.51 9.84 8.58 10.05 9.94 9.53 9.74 10.14
[14:34:11.585] <TB3> INFO: bits RMS: 2.69 2.32 2.63 3.01 3.10 2.50 2.52 2.53 2.66 2.72 2.37 2.24 2.73 2.63 1.89 2.51
[14:34:11.593] <TB3> INFO: ----------------------------------------------------------------------
[14:34:11.593] <TB3> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:34:11.593] <TB3> INFO: ----------------------------------------------------------------------
[14:34:11.595] <TB3> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:34:11.604] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[14:34:11.604] <TB3> INFO: run 1 of 1
[14:34:11.836] <TB3> INFO: Expecting 4160000 events.
[14:34:44.156] <TB3> INFO: 769080 events read in total (31728ms).
[14:35:15.505] <TB3> INFO: 1530095 events read in total (63077ms).
[14:35:46.824] <TB3> INFO: 2285090 events read in total (94396ms).
[14:36:18.280] <TB3> INFO: 3037210 events read in total (125852ms).
[14:36:49.916] <TB3> INFO: 3787170 events read in total (157488ms).
[14:37:06.210] <TB3> INFO: 4160000 events read in total (173782ms).
[14:37:06.257] <TB3> INFO: Test took 174653ms.
[14:37:33.354] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 223 (-1/-1) hits flags = 528 (plus default)
[14:37:33.365] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[14:37:33.365] <TB3> INFO: run 1 of 1
[14:37:33.598] <TB3> INFO: Expecting 4659200 events.
[14:38:04.507] <TB3> INFO: 713465 events read in total (30317ms).
[14:38:34.609] <TB3> INFO: 1422055 events read in total (60419ms).
[14:39:04.877] <TB3> INFO: 2127215 events read in total (90687ms).
[14:39:34.807] <TB3> INFO: 2829885 events read in total (120617ms).
[14:40:04.963] <TB3> INFO: 3530845 events read in total (150773ms).
[14:40:34.878] <TB3> INFO: 4230770 events read in total (180688ms).
[14:40:53.425] <TB3> INFO: 4659200 events read in total (199235ms).
[14:40:53.487] <TB3> INFO: Test took 200122ms.
[14:41:24.742] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 216 (-1/-1) hits flags = 528 (plus default)
[14:41:24.752] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[14:41:24.752] <TB3> INFO: run 1 of 1
[14:41:24.985] <TB3> INFO: Expecting 4513600 events.
[14:41:56.003] <TB3> INFO: 721475 events read in total (31423ms).
[14:42:27.632] <TB3> INFO: 1437735 events read in total (62052ms).
[14:42:58.188] <TB3> INFO: 2150895 events read in total (92608ms).
[14:43:28.814] <TB3> INFO: 2860915 events read in total (123235ms).
[14:43:59.298] <TB3> INFO: 3569090 events read in total (153718ms).
[14:44:29.702] <TB3> INFO: 4277080 events read in total (184122ms).
[14:44:40.316] <TB3> INFO: 4513600 events read in total (194736ms).
[14:44:40.391] <TB3> INFO: Test took 195639ms.
[14:45:11.363] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 213 (-1/-1) hits flags = 528 (plus default)
[14:45:11.372] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[14:45:11.372] <TB3> INFO: run 1 of 1
[14:45:11.644] <TB3> INFO: Expecting 4451200 events.
[14:45:43.395] <TB3> INFO: 725110 events read in total (31159ms).
[14:46:13.857] <TB3> INFO: 1445025 events read in total (61621ms).
[14:46:44.404] <TB3> INFO: 2161715 events read in total (92168ms).
[14:47:14.751] <TB3> INFO: 2874950 events read in total (122515ms).
[14:47:45.323] <TB3> INFO: 3586310 events read in total (153087ms).
[14:48:15.891] <TB3> INFO: 4298545 events read in total (183655ms).
[14:48:22.730] <TB3> INFO: 4451200 events read in total (190494ms).
[14:48:22.786] <TB3> INFO: Test took 191414ms.
[14:48:53.500] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 218 (-1/-1) hits flags = 528 (plus default)
[14:48:53.509] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[14:48:53.509] <TB3> INFO: run 1 of 1
[14:48:53.775] <TB3> INFO: Expecting 4555200 events.
[14:49:24.662] <TB3> INFO: 719375 events read in total (30296ms).
[14:49:54.962] <TB3> INFO: 1434080 events read in total (60596ms).
[14:50:25.122] <TB3> INFO: 2145210 events read in total (90756ms).
[14:50:55.329] <TB3> INFO: 2853530 events read in total (120963ms).
[14:51:25.666] <TB3> INFO: 3559860 events read in total (151300ms).
[14:51:55.591] <TB3> INFO: 4265915 events read in total (181225ms).
[14:52:08.647] <TB3> INFO: 4555200 events read in total (194281ms).
[14:52:08.709] <TB3> INFO: Test took 195200ms.
[14:52:37.758] <TB3> INFO: PixTestTrim::trimBitTest() done
[14:52:37.759] <TB3> INFO: PixTestTrim::doTest() done, duration: 2538 seconds
[14:52:37.759] <TB3> INFO: Decoding statistics:
[14:52:37.759] <TB3> INFO: General information:
[14:52:37.759] <TB3> INFO: 16bit words read: 0
[14:52:37.759] <TB3> INFO: valid events total: 0
[14:52:37.759] <TB3> INFO: empty events: 0
[14:52:37.759] <TB3> INFO: valid events with pixels: 0
[14:52:37.759] <TB3> INFO: valid pixel hits: 0
[14:52:37.759] <TB3> INFO: Event errors: 0
[14:52:37.759] <TB3> INFO: start marker: 0
[14:52:37.759] <TB3> INFO: stop marker: 0
[14:52:37.759] <TB3> INFO: overflow: 0
[14:52:37.759] <TB3> INFO: invalid 5bit words: 0
[14:52:37.759] <TB3> INFO: invalid XOR eye diagram: 0
[14:52:37.759] <TB3> INFO: frame (failed synchr.): 0
[14:52:37.759] <TB3> INFO: idle data (no TBM trl): 0
[14:52:37.759] <TB3> INFO: no data (only TBM hdr): 0
[14:52:37.759] <TB3> INFO: TBM errors: 0
[14:52:37.759] <TB3> INFO: flawed TBM headers: 0
[14:52:37.759] <TB3> INFO: flawed TBM trailers: 0
[14:52:37.759] <TB3> INFO: event ID mismatches: 0
[14:52:37.759] <TB3> INFO: ROC errors: 0
[14:52:37.759] <TB3> INFO: missing ROC header(s): 0
[14:52:37.759] <TB3> INFO: misplaced readback start: 0
[14:52:37.759] <TB3> INFO: Pixel decoding errors: 0
[14:52:37.759] <TB3> INFO: pixel data incomplete: 0
[14:52:37.759] <TB3> INFO: pixel address: 0
[14:52:37.759] <TB3> INFO: pulse height fill bit: 0
[14:52:37.759] <TB3> INFO: buffer corruption: 0
[14:52:38.496] <TB3> INFO: ######################################################################
[14:52:38.496] <TB3> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[14:52:38.496] <TB3> INFO: ######################################################################
[14:52:38.768] <TB3> INFO: Expecting 41600 events.
[14:52:42.189] <TB3> INFO: 41600 events read in total (2830ms).
[14:52:42.190] <TB3> INFO: Test took 3693ms.
[14:52:42.628] <TB3> INFO: Expecting 41600 events.
[14:52:46.070] <TB3> INFO: 41600 events read in total (2850ms).
[14:52:46.070] <TB3> INFO: Test took 3678ms.
[14:52:46.373] <TB3> INFO: Expecting 41600 events.
[14:52:49.883] <TB3> INFO: 41600 events read in total (2919ms).
[14:52:49.884] <TB3> INFO: Test took 3790ms.
[14:52:50.172] <TB3> INFO: Expecting 41600 events.
[14:52:53.620] <TB3> INFO: 41600 events read in total (2856ms).
[14:52:53.621] <TB3> INFO: Test took 3713ms.
[14:52:53.909] <TB3> INFO: Expecting 41600 events.
[14:52:57.483] <TB3> INFO: 41600 events read in total (2982ms).
[14:52:57.484] <TB3> INFO: Test took 3839ms.
[14:52:57.781] <TB3> INFO: Expecting 41600 events.
[14:53:01.247] <TB3> INFO: 41600 events read in total (2874ms).
[14:53:01.248] <TB3> INFO: Test took 3739ms.
[14:53:01.536] <TB3> INFO: Expecting 41600 events.
[14:53:05.035] <TB3> INFO: 41600 events read in total (2907ms).
[14:53:05.036] <TB3> INFO: Test took 3765ms.
[14:53:05.326] <TB3> INFO: Expecting 41600 events.
[14:53:08.884] <TB3> INFO: 41600 events read in total (2967ms).
[14:53:08.885] <TB3> INFO: Test took 3824ms.
[14:53:09.188] <TB3> INFO: Expecting 41600 events.
[14:53:12.705] <TB3> INFO: 41600 events read in total (2925ms).
[14:53:12.706] <TB3> INFO: Test took 3798ms.
[14:53:12.994] <TB3> INFO: Expecting 41600 events.
[14:53:16.510] <TB3> INFO: 41600 events read in total (2925ms).
[14:53:16.511] <TB3> INFO: Test took 3782ms.
[14:53:16.800] <TB3> INFO: Expecting 41600 events.
[14:53:20.279] <TB3> INFO: 41600 events read in total (2888ms).
[14:53:20.280] <TB3> INFO: Test took 3745ms.
[14:53:20.568] <TB3> INFO: Expecting 41600 events.
[14:53:24.041] <TB3> INFO: 41600 events read in total (2882ms).
[14:53:24.042] <TB3> INFO: Test took 3739ms.
[14:53:24.330] <TB3> INFO: Expecting 41600 events.
[14:53:27.843] <TB3> INFO: 41600 events read in total (2922ms).
[14:53:27.844] <TB3> INFO: Test took 3779ms.
[14:53:28.135] <TB3> INFO: Expecting 41600 events.
[14:53:31.626] <TB3> INFO: 41600 events read in total (2899ms).
[14:53:31.627] <TB3> INFO: Test took 3756ms.
[14:53:31.915] <TB3> INFO: Expecting 41600 events.
[14:53:35.361] <TB3> INFO: 41600 events read in total (2855ms).
[14:53:35.361] <TB3> INFO: Test took 3711ms.
[14:53:35.650] <TB3> INFO: Expecting 41600 events.
[14:53:39.173] <TB3> INFO: 41600 events read in total (2932ms).
[14:53:39.174] <TB3> INFO: Test took 3789ms.
[14:53:39.465] <TB3> INFO: Expecting 41600 events.
[14:53:42.992] <TB3> INFO: 41600 events read in total (2936ms).
[14:53:42.993] <TB3> INFO: Test took 3793ms.
[14:53:43.281] <TB3> INFO: Expecting 41600 events.
[14:53:46.837] <TB3> INFO: 41600 events read in total (2964ms).
[14:53:46.838] <TB3> INFO: Test took 3821ms.
[14:53:47.126] <TB3> INFO: Expecting 41600 events.
[14:53:50.607] <TB3> INFO: 41600 events read in total (2890ms).
[14:53:50.608] <TB3> INFO: Test took 3747ms.
[14:53:50.898] <TB3> INFO: Expecting 41600 events.
[14:53:54.368] <TB3> INFO: 41600 events read in total (2878ms).
[14:53:54.368] <TB3> INFO: Test took 3734ms.
[14:53:54.659] <TB3> INFO: Expecting 41600 events.
[14:53:58.206] <TB3> INFO: 41600 events read in total (2956ms).
[14:53:58.207] <TB3> INFO: Test took 3813ms.
[14:53:58.497] <TB3> INFO: Expecting 41600 events.
[14:54:02.011] <TB3> INFO: 41600 events read in total (2922ms).
[14:54:02.012] <TB3> INFO: Test took 3780ms.
[14:54:02.303] <TB3> INFO: Expecting 41600 events.
[14:54:05.863] <TB3> INFO: 41600 events read in total (2968ms).
[14:54:05.864] <TB3> INFO: Test took 3828ms.
[14:54:06.152] <TB3> INFO: Expecting 41600 events.
[14:54:09.761] <TB3> INFO: 41600 events read in total (3017ms).
[14:54:09.762] <TB3> INFO: Test took 3874ms.
[14:54:10.052] <TB3> INFO: Expecting 41600 events.
[14:54:13.506] <TB3> INFO: 41600 events read in total (2863ms).
[14:54:13.507] <TB3> INFO: Test took 3720ms.
[14:54:13.795] <TB3> INFO: Expecting 41600 events.
[14:54:17.260] <TB3> INFO: 41600 events read in total (2874ms).
[14:54:17.261] <TB3> INFO: Test took 3731ms.
[14:54:17.550] <TB3> INFO: Expecting 41600 events.
[14:54:21.181] <TB3> INFO: 41600 events read in total (3040ms).
[14:54:21.181] <TB3> INFO: Test took 3896ms.
[14:54:21.470] <TB3> INFO: Expecting 2560 events.
[14:54:22.353] <TB3> INFO: 2560 events read in total (291ms).
[14:54:22.353] <TB3> INFO: Test took 1160ms.
[14:54:22.661] <TB3> INFO: Expecting 2560 events.
[14:54:23.542] <TB3> INFO: 2560 events read in total (290ms).
[14:54:23.542] <TB3> INFO: Test took 1188ms.
[14:54:23.850] <TB3> INFO: Expecting 2560 events.
[14:54:24.735] <TB3> INFO: 2560 events read in total (293ms).
[14:54:24.735] <TB3> INFO: Test took 1192ms.
[14:54:25.043] <TB3> INFO: Expecting 2560 events.
[14:54:25.926] <TB3> INFO: 2560 events read in total (291ms).
[14:54:25.927] <TB3> INFO: Test took 1192ms.
[14:54:26.234] <TB3> INFO: Expecting 2560 events.
[14:54:27.115] <TB3> INFO: 2560 events read in total (289ms).
[14:54:27.115] <TB3> INFO: Test took 1188ms.
[14:54:27.423] <TB3> INFO: Expecting 2560 events.
[14:54:28.302] <TB3> INFO: 2560 events read in total (287ms).
[14:54:28.302] <TB3> INFO: Test took 1187ms.
[14:54:28.610] <TB3> INFO: Expecting 2560 events.
[14:54:29.487] <TB3> INFO: 2560 events read in total (286ms).
[14:54:29.488] <TB3> INFO: Test took 1186ms.
[14:54:29.796] <TB3> INFO: Expecting 2560 events.
[14:54:30.676] <TB3> INFO: 2560 events read in total (289ms).
[14:54:30.676] <TB3> INFO: Test took 1188ms.
[14:54:30.984] <TB3> INFO: Expecting 2560 events.
[14:54:31.865] <TB3> INFO: 2560 events read in total (289ms).
[14:54:31.865] <TB3> INFO: Test took 1189ms.
[14:54:32.173] <TB3> INFO: Expecting 2560 events.
[14:54:33.051] <TB3> INFO: 2560 events read in total (286ms).
[14:54:33.051] <TB3> INFO: Test took 1186ms.
[14:54:33.359] <TB3> INFO: Expecting 2560 events.
[14:54:34.237] <TB3> INFO: 2560 events read in total (286ms).
[14:54:34.237] <TB3> INFO: Test took 1186ms.
[14:54:34.546] <TB3> INFO: Expecting 2560 events.
[14:54:35.424] <TB3> INFO: 2560 events read in total (287ms).
[14:54:35.424] <TB3> INFO: Test took 1186ms.
[14:54:35.732] <TB3> INFO: Expecting 2560 events.
[14:54:36.614] <TB3> INFO: 2560 events read in total (291ms).
[14:54:36.614] <TB3> INFO: Test took 1189ms.
[14:54:36.922] <TB3> INFO: Expecting 2560 events.
[14:54:37.804] <TB3> INFO: 2560 events read in total (290ms).
[14:54:37.805] <TB3> INFO: Test took 1190ms.
[14:54:38.112] <TB3> INFO: Expecting 2560 events.
[14:54:38.995] <TB3> INFO: 2560 events read in total (291ms).
[14:54:38.995] <TB3> INFO: Test took 1190ms.
[14:54:39.303] <TB3> INFO: Expecting 2560 events.
[14:54:40.187] <TB3> INFO: 2560 events read in total (292ms).
[14:54:40.188] <TB3> INFO: Test took 1192ms.
[14:54:40.191] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:54:40.496] <TB3> INFO: Expecting 655360 events.
[14:54:54.726] <TB3> INFO: 655360 events read in total (13639ms).
[14:54:54.736] <TB3> INFO: Expecting 655360 events.
[14:55:08.912] <TB3> INFO: 655360 events read in total (13773ms).
[14:55:08.931] <TB3> INFO: Expecting 655360 events.
[14:55:23.116] <TB3> INFO: 655360 events read in total (13782ms).
[14:55:23.135] <TB3> INFO: Expecting 655360 events.
[14:55:37.256] <TB3> INFO: 655360 events read in total (13718ms).
[14:55:37.278] <TB3> INFO: Expecting 655360 events.
[14:55:51.383] <TB3> INFO: 655360 events read in total (13702ms).
[14:55:51.411] <TB3> INFO: Expecting 655360 events.
[14:56:05.395] <TB3> INFO: 655360 events read in total (13581ms).
[14:56:05.425] <TB3> INFO: Expecting 655360 events.
[14:56:19.504] <TB3> INFO: 655360 events read in total (13676ms).
[14:56:19.539] <TB3> INFO: Expecting 655360 events.
[14:56:33.598] <TB3> INFO: 655360 events read in total (13656ms).
[14:56:33.651] <TB3> INFO: Expecting 655360 events.
[14:56:47.736] <TB3> INFO: 655360 events read in total (13682ms).
[14:56:47.779] <TB3> INFO: Expecting 655360 events.
[14:57:01.863] <TB3> INFO: 655360 events read in total (13681ms).
[14:57:01.913] <TB3> INFO: Expecting 655360 events.
[14:57:15.878] <TB3> INFO: 655360 events read in total (13563ms).
[14:57:15.928] <TB3> INFO: Expecting 655360 events.
[14:57:29.937] <TB3> INFO: 655360 events read in total (13606ms).
[14:57:29.994] <TB3> INFO: Expecting 655360 events.
[14:57:44.183] <TB3> INFO: 655360 events read in total (13786ms).
[14:57:44.244] <TB3> INFO: Expecting 655360 events.
[14:57:58.385] <TB3> INFO: 655360 events read in total (13738ms).
[14:57:58.452] <TB3> INFO: Expecting 655360 events.
[14:58:12.568] <TB3> INFO: 655360 events read in total (13713ms).
[14:58:12.639] <TB3> INFO: Expecting 655360 events.
[14:58:26.732] <TB3> INFO: 655360 events read in total (13690ms).
[14:58:26.833] <TB3> INFO: Test took 226642ms.
[14:58:26.930] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:58:27.195] <TB3> INFO: Expecting 655360 events.
[14:58:41.368] <TB3> INFO: 655360 events read in total (13581ms).
[14:58:41.382] <TB3> INFO: Expecting 655360 events.
[14:58:55.361] <TB3> INFO: 655360 events read in total (13576ms).
[14:58:55.379] <TB3> INFO: Expecting 655360 events.
[14:59:09.474] <TB3> INFO: 655360 events read in total (13692ms).
[14:59:09.491] <TB3> INFO: Expecting 655360 events.
[14:59:23.454] <TB3> INFO: 655360 events read in total (13560ms).
[14:59:23.476] <TB3> INFO: Expecting 655360 events.
[14:59:37.296] <TB3> INFO: 655360 events read in total (13417ms).
[14:59:37.324] <TB3> INFO: Expecting 655360 events.
[14:59:51.040] <TB3> INFO: 655360 events read in total (13313ms).
[14:59:51.071] <TB3> INFO: Expecting 655360 events.
[15:00:04.881] <TB3> INFO: 655360 events read in total (13407ms).
[15:00:04.916] <TB3> INFO: Expecting 655360 events.
[15:00:18.793] <TB3> INFO: 655360 events read in total (13474ms).
[15:00:18.831] <TB3> INFO: Expecting 655360 events.
[15:00:32.807] <TB3> INFO: 655360 events read in total (13573ms).
[15:00:32.849] <TB3> INFO: Expecting 655360 events.
[15:00:46.817] <TB3> INFO: 655360 events read in total (13565ms).
[15:00:46.869] <TB3> INFO: Expecting 655360 events.
[15:01:00.801] <TB3> INFO: 655360 events read in total (13529ms).
[15:01:00.866] <TB3> INFO: Expecting 655360 events.
[15:01:14.898] <TB3> INFO: 655360 events read in total (13629ms).
[15:01:14.963] <TB3> INFO: Expecting 655360 events.
[15:01:28.000] <TB3> INFO: 655360 events read in total (13632ms).
[15:01:29.061] <TB3> INFO: Expecting 655360 events.
[15:01:43.132] <TB3> INFO: 655360 events read in total (13668ms).
[15:01:43.206] <TB3> INFO: Expecting 655360 events.
[15:01:57.313] <TB3> INFO: 655360 events read in total (13704ms).
[15:01:57.383] <TB3> INFO: Expecting 655360 events.
[15:02:11.304] <TB3> INFO: 655360 events read in total (13518ms).
[15:02:11.380] <TB3> INFO: Test took 224450ms.
[15:02:11.573] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:02:11.578] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[15:02:11.583] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[15:02:11.588] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[15:02:11.592] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[15:02:11.597] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[15:02:11.602] <TB3> INFO: safety margin for low PH: adding 6, margin is now 26
[15:02:11.608] <TB3> INFO: safety margin for low PH: adding 7, margin is now 27
[15:02:11.614] <TB3> INFO: safety margin for low PH: adding 8, margin is now 28
[15:02:11.620] <TB3> INFO: safety margin for low PH: adding 9, margin is now 29
[15:02:11.625] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:02:11.631] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[15:02:11.637] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[15:02:11.643] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[15:02:11.649] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[15:02:11.654] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[15:02:11.660] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:02:11.665] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:02:11.670] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:02:11.675] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:02:11.680] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:02:11.685] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:02:11.690] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:02:11.695] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[15:02:11.700] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[15:02:11.705] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[15:02:11.710] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[15:02:11.715] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[15:02:11.720] <TB3> INFO: safety margin for low PH: adding 6, margin is now 26
[15:02:11.724] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:02:11.729] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:02:11.734] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:02:11.739] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[15:02:11.744] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:02:11.750] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:02:11.755] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[15:02:11.760] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[15:02:11.765] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[15:02:11.770] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[15:02:11.776] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[15:02:11.782] <TB3> INFO: safety margin for low PH: adding 6, margin is now 26
[15:02:11.789] <TB3> INFO: safety margin for low PH: adding 7, margin is now 27
[15:02:11.795] <TB3> INFO: safety margin for low PH: adding 8, margin is now 28
[15:02:11.801] <TB3> INFO: safety margin for low PH: adding 9, margin is now 29
[15:02:11.806] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:02:11.811] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[15:02:11.816] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[15:02:11.820] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[15:02:11.825] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[15:02:11.830] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[15:02:11.836] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[15:02:11.873] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C0.dat
[15:02:11.873] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C1.dat
[15:02:11.873] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C2.dat
[15:02:11.873] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C3.dat
[15:02:11.873] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C4.dat
[15:02:11.873] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C5.dat
[15:02:11.873] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C6.dat
[15:02:11.874] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C7.dat
[15:02:11.874] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C8.dat
[15:02:11.874] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C9.dat
[15:02:11.874] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C10.dat
[15:02:11.874] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C11.dat
[15:02:11.874] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C12.dat
[15:02:11.874] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C13.dat
[15:02:11.874] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C14.dat
[15:02:11.874] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C15.dat
[15:02:12.145] <TB3> INFO: Expecting 41600 events.
[15:02:15.235] <TB3> INFO: 41600 events read in total (2499ms).
[15:02:15.236] <TB3> INFO: Test took 3359ms.
[15:02:15.680] <TB3> INFO: Expecting 41600 events.
[15:02:18.682] <TB3> INFO: 41600 events read in total (2410ms).
[15:02:18.682] <TB3> INFO: Test took 3236ms.
[15:02:19.124] <TB3> INFO: Expecting 41600 events.
[15:02:22.218] <TB3> INFO: 41600 events read in total (2502ms).
[15:02:22.218] <TB3> INFO: Test took 3325ms.
[15:02:22.436] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:22.525] <TB3> INFO: Expecting 2560 events.
[15:02:23.409] <TB3> INFO: 2560 events read in total (293ms).
[15:02:23.409] <TB3> INFO: Test took 973ms.
[15:02:23.411] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:23.717] <TB3> INFO: Expecting 2560 events.
[15:02:24.604] <TB3> INFO: 2560 events read in total (295ms).
[15:02:24.604] <TB3> INFO: Test took 1193ms.
[15:02:24.605] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:24.912] <TB3> INFO: Expecting 2560 events.
[15:02:25.795] <TB3> INFO: 2560 events read in total (292ms).
[15:02:25.795] <TB3> INFO: Test took 1190ms.
[15:02:25.797] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:26.103] <TB3> INFO: Expecting 2560 events.
[15:02:26.990] <TB3> INFO: 2560 events read in total (295ms).
[15:02:26.990] <TB3> INFO: Test took 1193ms.
[15:02:26.992] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:27.299] <TB3> INFO: Expecting 2560 events.
[15:02:28.182] <TB3> INFO: 2560 events read in total (292ms).
[15:02:28.182] <TB3> INFO: Test took 1190ms.
[15:02:28.184] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:28.490] <TB3> INFO: Expecting 2560 events.
[15:02:29.373] <TB3> INFO: 2560 events read in total (291ms).
[15:02:29.374] <TB3> INFO: Test took 1190ms.
[15:02:29.375] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:29.682] <TB3> INFO: Expecting 2560 events.
[15:02:30.565] <TB3> INFO: 2560 events read in total (291ms).
[15:02:30.566] <TB3> INFO: Test took 1191ms.
[15:02:30.567] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:30.882] <TB3> INFO: Expecting 2560 events.
[15:02:31.766] <TB3> INFO: 2560 events read in total (293ms).
[15:02:31.767] <TB3> INFO: Test took 1200ms.
[15:02:31.769] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:32.075] <TB3> INFO: Expecting 2560 events.
[15:02:32.954] <TB3> INFO: 2560 events read in total (287ms).
[15:02:32.954] <TB3> INFO: Test took 1187ms.
[15:02:32.957] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:33.262] <TB3> INFO: Expecting 2560 events.
[15:02:34.146] <TB3> INFO: 2560 events read in total (292ms).
[15:02:34.146] <TB3> INFO: Test took 1190ms.
[15:02:34.148] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:34.454] <TB3> INFO: Expecting 2560 events.
[15:02:35.332] <TB3> INFO: 2560 events read in total (286ms).
[15:02:35.332] <TB3> INFO: Test took 1184ms.
[15:02:35.334] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:35.641] <TB3> INFO: Expecting 2560 events.
[15:02:36.520] <TB3> INFO: 2560 events read in total (288ms).
[15:02:36.521] <TB3> INFO: Test took 1187ms.
[15:02:36.522] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:36.829] <TB3> INFO: Expecting 2560 events.
[15:02:37.708] <TB3> INFO: 2560 events read in total (287ms).
[15:02:37.708] <TB3> INFO: Test took 1186ms.
[15:02:37.710] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:38.017] <TB3> INFO: Expecting 2560 events.
[15:02:38.894] <TB3> INFO: 2560 events read in total (286ms).
[15:02:38.895] <TB3> INFO: Test took 1185ms.
[15:02:38.897] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:39.203] <TB3> INFO: Expecting 2560 events.
[15:02:40.082] <TB3> INFO: 2560 events read in total (287ms).
[15:02:40.082] <TB3> INFO: Test took 1186ms.
[15:02:40.084] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:40.390] <TB3> INFO: Expecting 2560 events.
[15:02:41.269] <TB3> INFO: 2560 events read in total (287ms).
[15:02:41.269] <TB3> INFO: Test took 1185ms.
[15:02:41.271] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:41.578] <TB3> INFO: Expecting 2560 events.
[15:02:42.457] <TB3> INFO: 2560 events read in total (288ms).
[15:02:42.457] <TB3> INFO: Test took 1186ms.
[15:02:42.460] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:42.765] <TB3> INFO: Expecting 2560 events.
[15:02:43.644] <TB3> INFO: 2560 events read in total (287ms).
[15:02:43.645] <TB3> INFO: Test took 1185ms.
[15:02:43.646] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:43.953] <TB3> INFO: Expecting 2560 events.
[15:02:44.830] <TB3> INFO: 2560 events read in total (285ms).
[15:02:44.831] <TB3> INFO: Test took 1185ms.
[15:02:44.833] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:45.139] <TB3> INFO: Expecting 2560 events.
[15:02:46.019] <TB3> INFO: 2560 events read in total (288ms).
[15:02:46.020] <TB3> INFO: Test took 1187ms.
[15:02:46.021] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:46.328] <TB3> INFO: Expecting 2560 events.
[15:02:47.217] <TB3> INFO: 2560 events read in total (297ms).
[15:02:47.217] <TB3> INFO: Test took 1196ms.
[15:02:47.219] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:47.525] <TB3> INFO: Expecting 2560 events.
[15:02:48.407] <TB3> INFO: 2560 events read in total (291ms).
[15:02:48.407] <TB3> INFO: Test took 1188ms.
[15:02:48.409] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:48.715] <TB3> INFO: Expecting 2560 events.
[15:02:49.595] <TB3> INFO: 2560 events read in total (288ms).
[15:02:49.595] <TB3> INFO: Test took 1186ms.
[15:02:49.597] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:49.903] <TB3> INFO: Expecting 2560 events.
[15:02:50.786] <TB3> INFO: 2560 events read in total (291ms).
[15:02:50.786] <TB3> INFO: Test took 1189ms.
[15:02:50.788] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:51.095] <TB3> INFO: Expecting 2560 events.
[15:02:51.980] <TB3> INFO: 2560 events read in total (294ms).
[15:02:51.981] <TB3> INFO: Test took 1193ms.
[15:02:51.983] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:52.289] <TB3> INFO: Expecting 2560 events.
[15:02:53.173] <TB3> INFO: 2560 events read in total (292ms).
[15:02:53.173] <TB3> INFO: Test took 1191ms.
[15:02:53.175] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:53.481] <TB3> INFO: Expecting 2560 events.
[15:02:54.364] <TB3> INFO: 2560 events read in total (291ms).
[15:02:54.364] <TB3> INFO: Test took 1189ms.
[15:02:54.366] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:54.673] <TB3> INFO: Expecting 2560 events.
[15:02:55.555] <TB3> INFO: 2560 events read in total (291ms).
[15:02:55.555] <TB3> INFO: Test took 1189ms.
[15:02:55.557] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:55.863] <TB3> INFO: Expecting 2560 events.
[15:02:56.747] <TB3> INFO: 2560 events read in total (292ms).
[15:02:56.747] <TB3> INFO: Test took 1190ms.
[15:02:56.749] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:57.055] <TB3> INFO: Expecting 2560 events.
[15:02:57.939] <TB3> INFO: 2560 events read in total (292ms).
[15:02:57.939] <TB3> INFO: Test took 1190ms.
[15:02:57.940] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:58.247] <TB3> INFO: Expecting 2560 events.
[15:02:59.129] <TB3> INFO: 2560 events read in total (290ms).
[15:02:59.129] <TB3> INFO: Test took 1189ms.
[15:02:59.131] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:02:59.438] <TB3> INFO: Expecting 2560 events.
[15:03:00.323] <TB3> INFO: 2560 events read in total (294ms).
[15:03:00.323] <TB3> INFO: Test took 1192ms.
[15:03:00.787] <TB3> INFO: PixTestPhOptimization::doTest() done, duration: 622 seconds
[15:03:00.787] <TB3> INFO: PH scale (per ROC): 68 46 36 58 33 58 47 32 31 30 44 43 41 31 43 31
[15:03:00.787] <TB3> INFO: PH offset (per ROC): 112 102 105 122 100 124 96 102 93 89 109 98 110 102 110 81
[15:03:00.792] <TB3> INFO: Decoding statistics:
[15:03:00.792] <TB3> INFO: General information:
[15:03:00.792] <TB3> INFO: 16bit words read: 127880
[15:03:00.792] <TB3> INFO: valid events total: 20480
[15:03:00.792] <TB3> INFO: empty events: 17980
[15:03:00.792] <TB3> INFO: valid events with pixels: 2500
[15:03:00.792] <TB3> INFO: valid pixel hits: 2500
[15:03:00.792] <TB3> INFO: Event errors: 0
[15:03:00.792] <TB3> INFO: start marker: 0
[15:03:00.792] <TB3> INFO: stop marker: 0
[15:03:00.792] <TB3> INFO: overflow: 0
[15:03:00.792] <TB3> INFO: invalid 5bit words: 0
[15:03:00.792] <TB3> INFO: invalid XOR eye diagram: 0
[15:03:00.792] <TB3> INFO: frame (failed synchr.): 0
[15:03:00.792] <TB3> INFO: idle data (no TBM trl): 0
[15:03:00.792] <TB3> INFO: no data (only TBM hdr): 0
[15:03:00.792] <TB3> INFO: TBM errors: 0
[15:03:00.792] <TB3> INFO: flawed TBM headers: 0
[15:03:00.792] <TB3> INFO: flawed TBM trailers: 0
[15:03:00.792] <TB3> INFO: event ID mismatches: 0
[15:03:00.792] <TB3> INFO: ROC errors: 0
[15:03:00.792] <TB3> INFO: missing ROC header(s): 0
[15:03:00.792] <TB3> INFO: misplaced readback start: 0
[15:03:00.792] <TB3> INFO: Pixel decoding errors: 0
[15:03:00.792] <TB3> INFO: pixel data incomplete: 0
[15:03:00.792] <TB3> INFO: pixel address: 0
[15:03:00.792] <TB3> INFO: pulse height fill bit: 0
[15:03:00.792] <TB3> INFO: buffer corruption: 0
[15:03:01.059] <TB3> INFO: ######################################################################
[15:03:01.059] <TB3> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[15:03:01.059] <TB3> INFO: ######################################################################
[15:03:01.071] <TB3> INFO: scanning low vcal = 10
[15:03:01.302] <TB3> INFO: Expecting 41600 events.
[15:03:04.872] <TB3> INFO: 41600 events read in total (2978ms).
[15:03:04.873] <TB3> INFO: Test took 3802ms.
[15:03:04.874] <TB3> INFO: scanning low vcal = 20
[15:03:05.174] <TB3> INFO: Expecting 41600 events.
[15:03:08.726] <TB3> INFO: 41600 events read in total (2961ms).
[15:03:08.727] <TB3> INFO: Test took 3853ms.
[15:03:08.729] <TB3> INFO: scanning low vcal = 30
[15:03:09.027] <TB3> INFO: Expecting 41600 events.
[15:03:12.638] <TB3> INFO: 41600 events read in total (3019ms).
[15:03:12.639] <TB3> INFO: Test took 3910ms.
[15:03:12.642] <TB3> INFO: scanning low vcal = 40
[15:03:12.922] <TB3> INFO: Expecting 41600 events.
[15:03:16.834] <TB3> INFO: 41600 events read in total (3320ms).
[15:03:16.835] <TB3> INFO: Test took 4193ms.
[15:03:16.838] <TB3> INFO: scanning low vcal = 50
[15:03:17.114] <TB3> INFO: Expecting 41600 events.
[15:03:21.054] <TB3> INFO: 41600 events read in total (3348ms).
[15:03:21.054] <TB3> INFO: Test took 4216ms.
[15:03:21.057] <TB3> INFO: scanning low vcal = 60
[15:03:21.334] <TB3> INFO: Expecting 41600 events.
[15:03:25.276] <TB3> INFO: 41600 events read in total (3351ms).
[15:03:25.277] <TB3> INFO: Test took 4220ms.
[15:03:25.280] <TB3> INFO: scanning low vcal = 70
[15:03:25.557] <TB3> INFO: Expecting 41600 events.
[15:03:29.491] <TB3> INFO: 41600 events read in total (3343ms).
[15:03:29.491] <TB3> INFO: Test took 4211ms.
[15:03:29.494] <TB3> INFO: scanning low vcal = 80
[15:03:29.771] <TB3> INFO: Expecting 41600 events.
[15:03:33.712] <TB3> INFO: 41600 events read in total (3350ms).
[15:03:33.713] <TB3> INFO: Test took 4219ms.
[15:03:33.716] <TB3> INFO: scanning low vcal = 90
[15:03:33.992] <TB3> INFO: Expecting 41600 events.
[15:03:37.926] <TB3> INFO: 41600 events read in total (3342ms).
[15:03:37.927] <TB3> INFO: Test took 4211ms.
[15:03:37.929] <TB3> INFO: scanning low vcal = 100
[15:03:38.206] <TB3> INFO: Expecting 41600 events.
[15:03:42.169] <TB3> INFO: 41600 events read in total (3371ms).
[15:03:42.170] <TB3> INFO: Test took 4240ms.
[15:03:42.172] <TB3> INFO: scanning low vcal = 110
[15:03:42.449] <TB3> INFO: Expecting 41600 events.
[15:03:46.380] <TB3> INFO: 41600 events read in total (3340ms).
[15:03:46.380] <TB3> INFO: Test took 4208ms.
[15:03:46.383] <TB3> INFO: scanning low vcal = 120
[15:03:46.660] <TB3> INFO: Expecting 41600 events.
[15:03:50.606] <TB3> INFO: 41600 events read in total (3355ms).
[15:03:50.607] <TB3> INFO: Test took 4224ms.
[15:03:50.610] <TB3> INFO: scanning low vcal = 130
[15:03:50.887] <TB3> INFO: Expecting 41600 events.
[15:03:54.806] <TB3> INFO: 41600 events read in total (3328ms).
[15:03:54.806] <TB3> INFO: Test took 4196ms.
[15:03:54.809] <TB3> INFO: scanning low vcal = 140
[15:03:55.086] <TB3> INFO: Expecting 41600 events.
[15:03:59.006] <TB3> INFO: 41600 events read in total (3329ms).
[15:03:59.007] <TB3> INFO: Test took 4198ms.
[15:03:59.010] <TB3> INFO: scanning low vcal = 150
[15:03:59.287] <TB3> INFO: Expecting 41600 events.
[15:04:03.212] <TB3> INFO: 41600 events read in total (3334ms).
[15:04:03.213] <TB3> INFO: Test took 4203ms.
[15:04:03.215] <TB3> INFO: scanning low vcal = 160
[15:04:03.492] <TB3> INFO: Expecting 41600 events.
[15:04:07.433] <TB3> INFO: 41600 events read in total (3349ms).
[15:04:07.434] <TB3> INFO: Test took 4219ms.
[15:04:07.437] <TB3> INFO: scanning low vcal = 170
[15:04:07.713] <TB3> INFO: Expecting 41600 events.
[15:04:11.652] <TB3> INFO: 41600 events read in total (3347ms).
[15:04:11.653] <TB3> INFO: Test took 4216ms.
[15:04:11.656] <TB3> INFO: scanning low vcal = 180
[15:04:11.932] <TB3> INFO: Expecting 41600 events.
[15:04:15.850] <TB3> INFO: 41600 events read in total (3326ms).
[15:04:15.851] <TB3> INFO: Test took 4195ms.
[15:04:15.853] <TB3> INFO: scanning low vcal = 190
[15:04:16.130] <TB3> INFO: Expecting 41600 events.
[15:04:20.072] <TB3> INFO: 41600 events read in total (3351ms).
[15:04:20.073] <TB3> INFO: Test took 4220ms.
[15:04:20.075] <TB3> INFO: scanning low vcal = 200
[15:04:20.352] <TB3> INFO: Expecting 41600 events.
[15:04:24.271] <TB3> INFO: 41600 events read in total (3327ms).
[15:04:24.272] <TB3> INFO: Test took 4196ms.
[15:04:24.275] <TB3> INFO: scanning low vcal = 210
[15:04:24.551] <TB3> INFO: Expecting 41600 events.
[15:04:28.505] <TB3> INFO: 41600 events read in total (3362ms).
[15:04:28.506] <TB3> INFO: Test took 4231ms.
[15:04:28.508] <TB3> INFO: scanning low vcal = 220
[15:04:28.785] <TB3> INFO: Expecting 41600 events.
[15:04:32.733] <TB3> INFO: 41600 events read in total (3356ms).
[15:04:32.734] <TB3> INFO: Test took 4225ms.
[15:04:32.737] <TB3> INFO: scanning low vcal = 230
[15:04:33.013] <TB3> INFO: Expecting 41600 events.
[15:04:36.948] <TB3> INFO: 41600 events read in total (3343ms).
[15:04:36.949] <TB3> INFO: Test took 4212ms.
[15:04:36.951] <TB3> INFO: scanning low vcal = 240
[15:04:37.229] <TB3> INFO: Expecting 41600 events.
[15:04:41.183] <TB3> INFO: 41600 events read in total (3363ms).
[15:04:41.184] <TB3> INFO: Test took 4233ms.
[15:04:41.186] <TB3> INFO: scanning low vcal = 250
[15:04:41.463] <TB3> INFO: Expecting 41600 events.
[15:04:45.407] <TB3> INFO: 41600 events read in total (3336ms).
[15:04:45.408] <TB3> INFO: Test took 4222ms.
[15:04:45.412] <TB3> INFO: scanning high vcal = 30 (= 210 in low range)
[15:04:45.687] <TB3> INFO: Expecting 41600 events.
[15:04:49.619] <TB3> INFO: 41600 events read in total (3340ms).
[15:04:49.619] <TB3> INFO: Test took 4207ms.
[15:04:49.622] <TB3> INFO: scanning high vcal = 50 (= 350 in low range)
[15:04:49.899] <TB3> INFO: Expecting 41600 events.
[15:04:53.872] <TB3> INFO: 41600 events read in total (3382ms).
[15:04:53.873] <TB3> INFO: Test took 4251ms.
[15:04:53.876] <TB3> INFO: scanning high vcal = 70 (= 490 in low range)
[15:04:54.152] <TB3> INFO: Expecting 41600 events.
[15:04:58.068] <TB3> INFO: 41600 events read in total (3324ms).
[15:04:58.069] <TB3> INFO: Test took 4193ms.
[15:04:58.072] <TB3> INFO: scanning high vcal = 90 (= 630 in low range)
[15:04:58.348] <TB3> INFO: Expecting 41600 events.
[15:05:02.302] <TB3> INFO: 41600 events read in total (3362ms).
[15:05:02.303] <TB3> INFO: Test took 4231ms.
[15:05:02.305] <TB3> INFO: scanning high vcal = 200 (= 1400 in low range)
[15:05:02.582] <TB3> INFO: Expecting 41600 events.
[15:05:06.534] <TB3> INFO: 41600 events read in total (3360ms).
[15:05:06.535] <TB3> INFO: Test took 4229ms.
[15:05:07.099] <TB3> INFO: PixTestGainPedestal::measure() done
[15:05:44.020] <TB3> INFO: PixTestGainPedestal::fit() done
[15:05:44.020] <TB3> INFO: non-linearity mean: 0.989 0.957 0.917 0.985 0.940 0.985 0.951 0.954 0.936 1.006 0.952 0.927 0.935 0.937 0.919 1.025
[15:05:44.020] <TB3> INFO: non-linearity RMS: 0.002 0.047 0.098 0.003 0.142 0.003 0.063 0.209 0.141 0.187 0.045 0.083 0.087 0.184 0.100 0.157
[15:05:44.020] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[15:05:44.034] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[15:05:44.048] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[15:05:44.062] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[15:05:44.076] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[15:05:44.090] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[15:05:44.104] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[15:05:44.118] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[15:05:44.132] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[15:05:44.147] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[15:05:44.161] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[15:05:44.175] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[15:05:44.193] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[15:05:44.215] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[15:05:44.237] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[15:05:44.259] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[15:05:44.277] <TB3> INFO: PixTestGainPedestal::fullTest() done, duration: 163 seconds
[15:05:44.277] <TB3> INFO: Decoding statistics:
[15:05:44.277] <TB3> INFO: General information:
[15:05:44.277] <TB3> INFO: 16bit words read: 3259630
[15:05:44.277] <TB3> INFO: valid events total: 332800
[15:05:44.278] <TB3> INFO: empty events: 746
[15:05:44.278] <TB3> INFO: valid events with pixels: 332054
[15:05:44.278] <TB3> INFO: valid pixel hits: 631415
[15:05:44.278] <TB3> INFO: Event errors: 0
[15:05:44.278] <TB3> INFO: start marker: 0
[15:05:44.278] <TB3> INFO: stop marker: 0
[15:05:44.278] <TB3> INFO: overflow: 0
[15:05:44.278] <TB3> INFO: invalid 5bit words: 0
[15:05:44.278] <TB3> INFO: invalid XOR eye diagram: 0
[15:05:44.278] <TB3> INFO: frame (failed synchr.): 0
[15:05:44.278] <TB3> INFO: idle data (no TBM trl): 0
[15:05:44.278] <TB3> INFO: no data (only TBM hdr): 0
[15:05:44.278] <TB3> INFO: TBM errors: 0
[15:05:44.278] <TB3> INFO: flawed TBM headers: 0
[15:05:44.278] <TB3> INFO: flawed TBM trailers: 0
[15:05:44.278] <TB3> INFO: event ID mismatches: 0
[15:05:44.278] <TB3> INFO: ROC errors: 0
[15:05:44.278] <TB3> INFO: missing ROC header(s): 0
[15:05:44.278] <TB3> INFO: misplaced readback start: 0
[15:05:44.278] <TB3> INFO: Pixel decoding errors: 0
[15:05:44.278] <TB3> INFO: pixel data incomplete: 0
[15:05:44.278] <TB3> INFO: pixel address: 0
[15:05:44.278] <TB3> INFO: pulse height fill bit: 0
[15:05:44.278] <TB3> INFO: buffer corruption: 0
[15:05:44.292] <TB3> INFO: Decoding statistics:
[15:05:44.292] <TB3> INFO: General information:
[15:05:44.292] <TB3> INFO: 16bit words read: 3389046
[15:05:44.292] <TB3> INFO: valid events total: 353536
[15:05:44.292] <TB3> INFO: empty events: 18982
[15:05:44.292] <TB3> INFO: valid events with pixels: 334554
[15:05:44.292] <TB3> INFO: valid pixel hits: 633915
[15:05:44.292] <TB3> INFO: Event errors: 0
[15:05:44.292] <TB3> INFO: start marker: 0
[15:05:44.292] <TB3> INFO: stop marker: 0
[15:05:44.292] <TB3> INFO: overflow: 0
[15:05:44.292] <TB3> INFO: invalid 5bit words: 0
[15:05:44.292] <TB3> INFO: invalid XOR eye diagram: 0
[15:05:44.292] <TB3> INFO: frame (failed synchr.): 0
[15:05:44.292] <TB3> INFO: idle data (no TBM trl): 0
[15:05:44.292] <TB3> INFO: no data (only TBM hdr): 0
[15:05:44.292] <TB3> INFO: TBM errors: 0
[15:05:44.292] <TB3> INFO: flawed TBM headers: 0
[15:05:44.292] <TB3> INFO: flawed TBM trailers: 0
[15:05:44.292] <TB3> INFO: event ID mismatches: 0
[15:05:44.293] <TB3> INFO: ROC errors: 0
[15:05:44.293] <TB3> INFO: missing ROC header(s): 0
[15:05:44.293] <TB3> INFO: misplaced readback start: 0
[15:05:44.293] <TB3> INFO: Pixel decoding errors: 0
[15:05:44.293] <TB3> INFO: pixel data incomplete: 0
[15:05:44.293] <TB3> INFO: pixel address: 0
[15:05:44.293] <TB3> INFO: pulse height fill bit: 0
[15:05:44.293] <TB3> INFO: buffer corruption: 0
[15:05:44.293] <TB3> INFO: enter test to run
[15:05:44.293] <TB3> INFO: test: Trim80 no parameter change
[15:05:44.293] <TB3> INFO: running: trim80
[15:05:44.311] <TB3> INFO: ######################################################################
[15:05:44.311] <TB3> INFO: PixTestTrim80::doTest()
[15:05:44.311] <TB3> INFO: ######################################################################
[15:05:44.312] <TB3> INFO: ----------------------------------------------------------------------
[15:05:44.312] <TB3> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[15:05:44.312] <TB3> INFO: ----------------------------------------------------------------------
[15:05:44.352] <TB3> INFO: ---> VthrComp thr map (minimal VthrComp)
[15:05:44.353] <TB3> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[15:05:44.362] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[15:05:44.362] <TB3> INFO: run 1 of 1
[15:05:44.595] <TB3> INFO: Expecting 5025280 events.
[15:06:12.222] <TB3> INFO: 688184 events read in total (27035ms).
[15:06:39.353] <TB3> INFO: 1370120 events read in total (54166ms).
[15:07:06.770] <TB3> INFO: 2048680 events read in total (81583ms).
[15:07:34.190] <TB3> INFO: 2725608 events read in total (109003ms).
[15:08:01.190] <TB3> INFO: 3401984 events read in total (136003ms).
[15:08:28.368] <TB3> INFO: 4077496 events read in total (163181ms).
[15:08:55.575] <TB3> INFO: 4753432 events read in total (190388ms).
[15:09:06.615] <TB3> INFO: 5025280 events read in total (201428ms).
[15:09:06.685] <TB3> INFO: Test took 202323ms.
[15:09:28.375] <TB3> INFO: ROC 0 VthrComp = 79
[15:09:28.375] <TB3> INFO: ROC 1 VthrComp = 81
[15:09:28.375] <TB3> INFO: ROC 2 VthrComp = 73
[15:09:28.375] <TB3> INFO: ROC 3 VthrComp = 82
[15:09:28.375] <TB3> INFO: ROC 4 VthrComp = 73
[15:09:28.376] <TB3> INFO: ROC 5 VthrComp = 74
[15:09:28.376] <TB3> INFO: ROC 6 VthrComp = 77
[15:09:28.376] <TB3> INFO: ROC 7 VthrComp = 66
[15:09:28.376] <TB3> INFO: ROC 8 VthrComp = 80
[15:09:28.376] <TB3> INFO: ROC 9 VthrComp = 81
[15:09:28.376] <TB3> INFO: ROC 10 VthrComp = 67
[15:09:28.376] <TB3> INFO: ROC 11 VthrComp = 76
[15:09:28.376] <TB3> INFO: ROC 12 VthrComp = 76
[15:09:28.377] <TB3> INFO: ROC 13 VthrComp = 76
[15:09:28.377] <TB3> INFO: ROC 14 VthrComp = 85
[15:09:28.377] <TB3> INFO: ROC 15 VthrComp = 76
[15:09:28.650] <TB3> INFO: Expecting 41600 events.
[15:09:32.134] <TB3> INFO: 41600 events read in total (2893ms).
[15:09:32.134] <TB3> INFO: Test took 3756ms.
[15:09:32.143] <TB3> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[15:09:32.143] <TB3> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[15:09:32.153] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[15:09:32.153] <TB3> INFO: run 1 of 1
[15:09:32.431] <TB3> INFO: Expecting 5025280 events.
[15:10:00.264] <TB3> INFO: 689040 events read in total (27240ms).
[15:10:28.075] <TB3> INFO: 1374072 events read in total (55051ms).
[15:10:55.337] <TB3> INFO: 2056424 events read in total (82313ms).
[15:11:22.216] <TB3> INFO: 2736336 events read in total (109192ms).
[15:11:49.024] <TB3> INFO: 3413808 events read in total (136000ms).
[15:12:16.346] <TB3> INFO: 4089048 events read in total (163323ms).
[15:12:43.497] <TB3> INFO: 4763944 events read in total (190473ms).
[15:12:54.429] <TB3> INFO: 5025280 events read in total (201405ms).
[15:12:54.478] <TB3> INFO: Test took 202325ms.
[15:13:18.850] <TB3> INFO: roc 0 with ID = 0 has maximal Vcal 112.238 for pixel 0/68 mean/min/max = 94.7255/77.206/112.245
[15:13:18.851] <TB3> INFO: roc 1 with ID = 1 has maximal Vcal 109.675 for pixel 8/17 mean/min/max = 92.6411/75.5728/109.709
[15:13:18.851] <TB3> INFO: roc 2 with ID = 2 has maximal Vcal 110.078 for pixel 10/12 mean/min/max = 93.7141/77.2914/110.137
[15:13:18.852] <TB3> INFO: roc 3 with ID = 3 has maximal Vcal 108.073 for pixel 0/8 mean/min/max = 91.416/74.7342/108.098
[15:13:18.852] <TB3> INFO: roc 4 with ID = 4 has maximal Vcal 113.044 for pixel 0/7 mean/min/max = 94.4058/75.64/113.172
[15:13:18.852] <TB3> INFO: roc 5 with ID = 5 has maximal Vcal 111.954 for pixel 5/75 mean/min/max = 95.1402/78.234/112.046
[15:13:18.853] <TB3> INFO: roc 6 with ID = 6 has maximal Vcal 110.07 for pixel 17/2 mean/min/max = 93.7042/77.3357/110.073
[15:13:18.853] <TB3> INFO: roc 7 with ID = 7 has maximal Vcal 106.665 for pixel 51/74 mean/min/max = 90.5226/74.1805/106.865
[15:13:18.853] <TB3> INFO: roc 8 with ID = 8 has maximal Vcal 114.645 for pixel 24/79 mean/min/max = 93.9849/73.242/114.728
[15:13:18.854] <TB3> INFO: roc 9 with ID = 9 has maximal Vcal 112.497 for pixel 0/74 mean/min/max = 93.495/74.4863/112.504
[15:13:18.854] <TB3> INFO: roc 10 with ID = 10 has maximal Vcal 106.152 for pixel 1/74 mean/min/max = 90.2776/74.4018/106.153
[15:13:18.855] <TB3> INFO: roc 11 with ID = 11 has maximal Vcal 109.62 for pixel 17/72 mean/min/max = 93.6107/77.5311/109.69
[15:13:18.855] <TB3> INFO: roc 12 with ID = 12 has maximal Vcal 109.597 for pixel 0/55 mean/min/max = 94.1071/78.4596/109.755
[15:13:18.855] <TB3> INFO: roc 13 with ID = 13 has maximal Vcal 109.104 for pixel 26/79 mean/min/max = 94.5084/79.8294/109.187
[15:13:18.855] <TB3> INFO: roc 14 with ID = 14 has maximal Vcal 111.231 for pixel 1/75 mean/min/max = 92.0634/72.7032/111.424
[15:13:18.856] <TB3> INFO: roc 15 with ID = 15 has maximal Vcal 113.491 for pixel 14/11 mean/min/max = 95.8107/78.0924/113.529
[15:13:18.856] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:13:18.946] <TB3> INFO: Expecting 411648 events.
[15:13:28.223] <TB3> INFO: 411648 events read in total (8685ms).
[15:13:28.230] <TB3> INFO: Expecting 411648 events.
[15:13:37.400] <TB3> INFO: 411648 events read in total (8767ms).
[15:13:37.412] <TB3> INFO: Expecting 411648 events.
[15:13:46.476] <TB3> INFO: 411648 events read in total (8661ms).
[15:13:46.495] <TB3> INFO: Expecting 411648 events.
[15:13:55.799] <TB3> INFO: 411648 events read in total (8901ms).
[15:13:55.817] <TB3> INFO: Expecting 411648 events.
[15:14:04.906] <TB3> INFO: 411648 events read in total (8686ms).
[15:14:04.930] <TB3> INFO: Expecting 411648 events.
[15:14:14.048] <TB3> INFO: 411648 events read in total (8715ms).
[15:14:14.075] <TB3> INFO: Expecting 411648 events.
[15:14:23.120] <TB3> INFO: 411648 events read in total (8642ms).
[15:14:23.149] <TB3> INFO: Expecting 411648 events.
[15:14:32.305] <TB3> INFO: 411648 events read in total (8753ms).
[15:14:32.330] <TB3> INFO: Expecting 411648 events.
[15:14:41.553] <TB3> INFO: 411648 events read in total (8820ms).
[15:14:41.590] <TB3> INFO: Expecting 411648 events.
[15:14:50.714] <TB3> INFO: 411648 events read in total (8721ms).
[15:14:50.745] <TB3> INFO: Expecting 411648 events.
[15:14:59.840] <TB3> INFO: 411648 events read in total (8692ms).
[15:14:59.890] <TB3> INFO: Expecting 411648 events.
[15:15:08.930] <TB3> INFO: 411648 events read in total (8637ms).
[15:15:08.969] <TB3> INFO: Expecting 411648 events.
[15:15:18.040] <TB3> INFO: 411648 events read in total (8669ms).
[15:15:18.080] <TB3> INFO: Expecting 411648 events.
[15:15:27.240] <TB3> INFO: 411648 events read in total (8757ms).
[15:15:27.283] <TB3> INFO: Expecting 411648 events.
[15:15:36.332] <TB3> INFO: 411648 events read in total (8646ms).
[15:15:36.377] <TB3> INFO: Expecting 411648 events.
[15:15:45.443] <TB3> INFO: 411648 events read in total (8663ms).
[15:15:45.490] <TB3> INFO: Test took 146634ms.
[15:15:47.052] <TB3> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[15:15:47.061] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[15:15:47.061] <TB3> INFO: run 1 of 1
[15:15:47.295] <TB3> INFO: Expecting 5025280 events.
[15:16:14.781] <TB3> INFO: 668016 events read in total (26894ms).
[15:16:41.508] <TB3> INFO: 1331040 events read in total (53621ms).
[15:17:08.403] <TB3> INFO: 1991936 events read in total (80516ms).
[15:17:34.985] <TB3> INFO: 2650592 events read in total (107098ms).
[15:18:01.346] <TB3> INFO: 3304120 events read in total (133459ms).
[15:18:27.717] <TB3> INFO: 3954704 events read in total (159830ms).
[15:18:54.157] <TB3> INFO: 4603128 events read in total (186270ms).
[15:19:11.104] <TB3> INFO: 5025280 events read in total (203217ms).
[15:19:11.159] <TB3> INFO: Test took 204099ms.
[15:19:34.268] <TB3> INFO: ---> TrimStepCorr4 extremal thresholds: 48.420716 .. 104.537279
[15:19:34.510] <TB3> INFO: Expecting 208000 events.
[15:19:44.280] <TB3> INFO: 208000 events read in total (9178ms).
[15:19:44.281] <TB3> INFO: Test took 10011ms.
[15:19:44.345] <TB3> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 38 .. 114 (-1/-1) hits flags = 528 (plus default)
[15:19:44.355] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[15:19:44.355] <TB3> INFO: run 1 of 1
[15:19:44.633] <TB3> INFO: Expecting 2562560 events.
[15:20:12.856] <TB3> INFO: 690984 events read in total (27631ms).
[15:20:40.173] <TB3> INFO: 1380904 events read in total (54948ms).
[15:21:08.299] <TB3> INFO: 2059456 events read in total (83074ms).
[15:21:28.743] <TB3> INFO: 2562560 events read in total (103518ms).
[15:21:28.780] <TB3> INFO: Test took 104424ms.
[15:21:48.188] <TB3> INFO: ---> TrimStepCorr2 extremal thresholds: 60.207325 .. 95.416950
[15:21:48.424] <TB3> INFO: Expecting 208000 events.
[15:21:58.209] <TB3> INFO: 208000 events read in total (9193ms).
[15:21:58.210] <TB3> INFO: Test took 10021ms.
[15:21:58.314] <TB3> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 50 .. 105 (-1/-1) hits flags = 528 (plus default)
[15:21:58.325] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[15:21:58.325] <TB3> INFO: run 1 of 1
[15:21:58.608] <TB3> INFO: Expecting 1863680 events.
[15:22:28.157] <TB3> INFO: 683688 events read in total (28956ms).
[15:22:55.688] <TB3> INFO: 1367080 events read in total (56488ms).
[15:23:15.740] <TB3> INFO: 1863680 events read in total (76539ms).
[15:23:15.768] <TB3> INFO: Test took 77443ms.
[15:23:34.737] <TB3> INFO: ---> TrimStepCorr1a extremal thresholds: 64.604540 .. 97.720695
[15:23:34.995] <TB3> INFO: Expecting 208000 events.
[15:23:44.998] <TB3> INFO: 208000 events read in total (9411ms).
[15:23:44.998] <TB3> INFO: Test took 10261ms.
[15:23:45.045] <TB3> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 54 .. 107 (-1/-1) hits flags = 528 (plus default)
[15:23:45.053] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[15:23:45.053] <TB3> INFO: run 1 of 1
[15:23:45.331] <TB3> INFO: Expecting 1797120 events.
[15:24:13.033] <TB3> INFO: 665264 events read in total (27111ms).
[15:24:40.327] <TB3> INFO: 1329800 events read in total (54405ms).
[15:24:59.489] <TB3> INFO: 1797120 events read in total (73567ms).
[15:24:59.516] <TB3> INFO: Test took 74463ms.
[15:25:17.597] <TB3> INFO: ---> TrimStepCorr1b extremal thresholds: 67.346117 .. 95.200549
[15:25:17.832] <TB3> INFO: Expecting 208000 events.
[15:25:27.669] <TB3> INFO: 208000 events read in total (9245ms).
[15:25:27.671] <TB3> INFO: Test took 10072ms.
[15:25:27.718] <TB3> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 57 .. 105 (-1/-1) hits flags = 528 (plus default)
[15:25:27.727] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[15:25:27.727] <TB3> INFO: run 1 of 1
[15:25:28.005] <TB3> INFO: Expecting 1630720 events.
[15:25:55.466] <TB3> INFO: 663096 events read in total (26870ms).
[15:26:22.834] <TB3> INFO: 1326056 events read in total (54237ms).
[15:26:35.687] <TB3> INFO: 1630720 events read in total (67090ms).
[15:26:35.721] <TB3> INFO: Test took 67994ms.
[15:26:53.983] <TB3> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[15:26:53.983] <TB3> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[15:26:53.992] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[15:26:53.992] <TB3> INFO: run 1 of 1
[15:26:54.242] <TB3> INFO: Expecting 1364480 events.
[15:27:22.047] <TB3> INFO: 668080 events read in total (27214ms).
[15:27:49.480] <TB3> INFO: 1335816 events read in total (54647ms).
[15:27:51.122] <TB3> INFO: 1364480 events read in total (56289ms).
[15:27:51.143] <TB3> INFO: Test took 57151ms.
[15:28:08.976] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C0.dat
[15:28:08.976] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C1.dat
[15:28:08.976] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C2.dat
[15:28:08.976] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C3.dat
[15:28:08.976] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C4.dat
[15:28:08.976] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C5.dat
[15:28:08.976] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C6.dat
[15:28:08.976] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C7.dat
[15:28:08.976] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C8.dat
[15:28:08.976] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C9.dat
[15:28:08.977] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C10.dat
[15:28:08.977] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C11.dat
[15:28:08.977] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C12.dat
[15:28:08.977] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C13.dat
[15:28:08.977] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C14.dat
[15:28:08.977] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C15.dat
[15:28:08.977] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C0.dat
[15:28:08.982] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C1.dat
[15:28:08.988] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C2.dat
[15:28:08.994] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C3.dat
[15:28:08.999] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C4.dat
[15:28:09.005] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C5.dat
[15:28:09.010] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C6.dat
[15:28:09.016] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C7.dat
[15:28:09.022] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C8.dat
[15:28:09.027] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C9.dat
[15:28:09.033] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C10.dat
[15:28:09.038] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C11.dat
[15:28:09.044] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C12.dat
[15:28:09.050] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C13.dat
[15:28:09.055] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C14.dat
[15:28:09.061] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1085_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C15.dat
[15:28:09.066] <TB3> INFO: PixTestTrim80::trimTest() done
[15:28:09.066] <TB3> INFO: vtrim: 120 116 95 114 113 107 116 95 116 126 78 111 99 95 107 126
[15:28:09.066] <TB3> INFO: vthrcomp: 79 81 73 82 73 74 77 66 80 81 67 76 76 76 85 76
[15:28:09.066] <TB3> INFO: vcal mean: 79.98 79.95 79.94 79.95 79.88 79.98 79.91 79.91 79.88 79.96 79.90 79.94 79.96 79.99 79.90 79.93
[15:28:09.066] <TB3> INFO: vcal RMS: 0.88 0.90 0.72 0.79 0.75 0.77 1.43 0.80 0.85 0.83 0.73 0.79 0.74 0.76 0.80 0.81
[15:28:09.066] <TB3> INFO: bits mean: 9.60 10.22 9.59 10.58 9.90 9.34 9.65 10.42 10.52 10.54 9.66 9.94 9.40 9.21 10.22 10.16
[15:28:09.066] <TB3> INFO: bits RMS: 2.19 2.21 2.21 2.19 2.18 2.16 2.14 2.32 2.19 2.08 2.75 2.03 2.18 2.09 2.48 1.84
[15:28:09.073] <TB3> INFO: ----------------------------------------------------------------------
[15:28:09.073] <TB3> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[15:28:09.073] <TB3> INFO: ----------------------------------------------------------------------
[15:28:09.075] <TB3> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[15:28:09.084] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[15:28:09.084] <TB3> INFO: run 1 of 1
[15:28:09.318] <TB3> INFO: Expecting 4160000 events.
[15:28:41.378] <TB3> INFO: 769175 events read in total (31468ms).
[15:29:12.664] <TB3> INFO: 1530375 events read in total (62754ms).
[15:29:43.970] <TB3> INFO: 2285675 events read in total (94060ms).
[15:30:15.858] <TB3> INFO: 3038085 events read in total (125949ms).
[15:30:47.209] <TB3> INFO: 3788065 events read in total (157299ms).
[15:31:02.905] <TB3> INFO: 4160000 events read in total (172995ms).
[15:31:02.960] <TB3> INFO: Test took 173876ms.
[15:31:30.132] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 221 (-1/-1) hits flags = 528 (plus default)
[15:31:30.142] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[15:31:30.142] <TB3> INFO: run 1 of 1
[15:31:30.387] <TB3> INFO: Expecting 4617600 events.
[15:32:01.405] <TB3> INFO: 715835 events read in total (30426ms).
[15:32:31.547] <TB3> INFO: 1426560 events read in total (60568ms).
[15:33:01.971] <TB3> INFO: 2134055 events read in total (90993ms).
[15:33:32.203] <TB3> INFO: 2838680 events read in total (121224ms).
[15:34:02.144] <TB3> INFO: 3541415 events read in total (151165ms).
[15:34:32.161] <TB3> INFO: 4243465 events read in total (181182ms).
[15:34:48.745] <TB3> INFO: 4617600 events read in total (197766ms).
[15:34:48.809] <TB3> INFO: Test took 198667ms.
[15:35:19.284] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[15:35:19.295] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[15:35:19.295] <TB3> INFO: run 1 of 1
[15:35:19.537] <TB3> INFO: Expecting 4472000 events.
[15:35:50.805] <TB3> INFO: 724070 events read in total (30676ms).
[15:36:21.581] <TB3> INFO: 1442525 events read in total (61452ms).
[15:36:52.020] <TB3> INFO: 2158085 events read in total (91891ms).
[15:37:22.331] <TB3> INFO: 2870105 events read in total (122202ms).
[15:37:52.378] <TB3> INFO: 3580055 events read in total (152249ms).
[15:38:22.694] <TB3> INFO: 4290750 events read in total (182565ms).
[15:38:30.860] <TB3> INFO: 4472000 events read in total (190731ms).
[15:38:30.920] <TB3> INFO: Test took 191624ms.
[15:39:01.316] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[15:39:01.328] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[15:39:01.328] <TB3> INFO: run 1 of 1
[15:39:01.587] <TB3> INFO: Expecting 4472000 events.
[15:39:32.838] <TB3> INFO: 723640 events read in total (30660ms).
[15:40:03.375] <TB3> INFO: 1442400 events read in total (61197ms).
[15:40:34.336] <TB3> INFO: 2158085 events read in total (92158ms).
[15:41:04.782] <TB3> INFO: 2870155 events read in total (122604ms).
[15:41:35.182] <TB3> INFO: 3580550 events read in total (153004ms).
[15:42:05.794] <TB3> INFO: 4291510 events read in total (183616ms).
[15:42:13.883] <TB3> INFO: 4472000 events read in total (191705ms).
[15:42:13.939] <TB3> INFO: Test took 192611ms.
[15:42:42.856] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 211 (-1/-1) hits flags = 528 (plus default)
[15:42:42.865] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[15:42:42.865] <TB3> INFO: run 1 of 1
[15:42:43.126] <TB3> INFO: Expecting 4409600 events.
[15:43:14.551] <TB3> INFO: 727560 events read in total (30833ms).
[15:43:44.894] <TB3> INFO: 1450185 events read in total (61176ms).
[15:44:15.206] <TB3> INFO: 2169090 events read in total (91488ms).
[15:44:45.779] <TB3> INFO: 2885125 events read in total (122061ms).
[15:45:16.337] <TB3> INFO: 3598510 events read in total (152619ms).
[15:45:46.813] <TB3> INFO: 4313560 events read in total (183096ms).
[15:45:51.245] <TB3> INFO: 4409600 events read in total (187527ms).
[15:45:51.306] <TB3> INFO: Test took 188440ms.
[15:46:19.643] <TB3> INFO: PixTestTrim80::trimBitTest() done
[15:46:19.644] <TB3> INFO: PixTestTrim80::doTest() done, duration: 2435 seconds
[15:46:20.397] <TB3> INFO: enter test to run
[15:46:20.397] <TB3> INFO: test: exit no parameter change
[15:46:20.515] <TB3> QUIET: Connection to board 170 closed.
[15:46:20.516] <TB3> INFO: pXar: this is the end, my friend