[11:58:25.848] <TB2> INFO: *** Welcome to pxar ***
[11:58:25.848] <TB2> INFO: *** Today: 2016/10/26
[11:58:25.854] <TB2> INFO: *** Version: c8ba-dirty
[11:58:25.854] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C15.dat
[11:58:25.855] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//tbmParameters_C1b.dat
[11:58:25.855] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//defaultMaskFile.dat
[11:58:25.855] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters_C15.dat
[11:58:25.912] <TB2> INFO: clk: 4
[11:58:25.912] <TB2> INFO: ctr: 4
[11:58:25.912] <TB2> INFO: sda: 19
[11:58:25.912] <TB2> INFO: tin: 9
[11:58:25.912] <TB2> INFO: level: 15
[11:58:25.912] <TB2> INFO: triggerdelay: 0
[11:58:25.912] <TB2> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[11:58:25.912] <TB2> INFO: Log level: INFO
[11:58:25.920] <TB2> INFO: Found DTB DTB_WXC55Z
[11:58:25.931] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[11:58:25.933] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[11:58:25.935] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[11:58:27.489] <TB2> INFO: DUT info:
[11:58:27.489] <TB2> INFO: The DUT currently contains the following objects:
[11:58:27.489] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[11:58:27.489] <TB2> INFO: TBM Core alpha (0): 7 registers set
[11:58:27.489] <TB2> INFO: TBM Core beta (1): 7 registers set
[11:58:27.489] <TB2> INFO: TBM Core alpha (2): 7 registers set
[11:58:27.489] <TB2> INFO: TBM Core beta (3): 7 registers set
[11:58:27.489] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:58:27.489] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:27.489] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:27.489] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:27.489] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:27.489] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:27.489] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:27.489] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:27.489] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:27.489] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:27.489] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:27.489] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:27.489] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:27.489] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:27.489] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:27.489] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:27.489] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:58:27.890] <TB2> INFO: enter 'restricted' command line mode
[11:58:27.890] <TB2> INFO: enter test to run
[11:58:27.890] <TB2> INFO: test: pretest no parameter change
[11:58:27.890] <TB2> INFO: running: pretest
[11:58:28.809] <TB2> INFO: ######################################################################
[11:58:28.809] <TB2> INFO: PixTestPretest::doTest()
[11:58:28.809] <TB2> INFO: ######################################################################
[11:58:28.810] <TB2> INFO: ----------------------------------------------------------------------
[11:58:28.810] <TB2> INFO: PixTestPretest::programROC()
[11:58:28.810] <TB2> INFO: ----------------------------------------------------------------------
[11:58:46.823] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:58:46.823] <TB2> INFO: IA differences per ROC: 20.1 20.1 17.7 20.1 17.7 21.7 20.1 18.5 20.1 22.5 20.1 18.5 18.5 21.7 21.7 21.7
[11:58:46.859] <TB2> INFO: ----------------------------------------------------------------------
[11:58:46.859] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:58:46.859] <TB2> INFO: ----------------------------------------------------------------------
[11:58:53.235] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 388.3 mA = 24.2687 mA/ROC
[11:58:53.236] <TB2> INFO: i(loss) [mA/ROC]: 19.3 19.3 19.3 18.5 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3 18.5 19.3 18.5
[11:58:53.265] <TB2> INFO: ----------------------------------------------------------------------
[11:58:53.265] <TB2> INFO: PixTestPretest::findTiming()
[11:58:53.265] <TB2> INFO: ----------------------------------------------------------------------
[11:58:53.265] <TB2> INFO: PixTestCmd::init()

[11:59:24.523] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[11:59:24.523] <TB2> INFO: (success/tries = 100/100), width = 3
[11:59:26.023] <TB2> INFO: ----------------------------------------------------------------------
[11:59:26.023] <TB2> INFO: PixTestPretest::findWorkingPixel()
[11:59:26.023] <TB2> INFO: ----------------------------------------------------------------------
[11:59:26.114] <TB2> INFO: Expecting 231680 events.
[11:59:35.832] <TB2> INFO: 231680 events read in total (9126ms).
[11:59:35.838] <TB2> INFO: Test took 9813ms.
[11:59:36.089] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:59:36.117] <TB2> INFO: ----------------------------------------------------------------------
[11:59:36.117] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[11:59:36.117] <TB2> INFO: ----------------------------------------------------------------------
[11:59:36.209] <TB2> INFO: Expecting 231680 events.
[11:59:45.963] <TB2> INFO: 231680 events read in total (9162ms).
[11:59:45.972] <TB2> INFO: Test took 9852ms.
[11:59:46.234] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[11:59:46.234] <TB2> INFO: CalDel: 84 99 101 101 98 104 84 90 89 108 101 103 110 98 94 96
[11:59:46.234] <TB2> INFO: VthrComp: 51 54 51 54 51 51 53 51 55 51 51 51 52 52 51 51
[11:59:46.236] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C0.dat
[11:59:46.236] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C1.dat
[11:59:46.236] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C2.dat
[11:59:46.237] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C3.dat
[11:59:46.237] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C4.dat
[11:59:46.237] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C5.dat
[11:59:46.237] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C6.dat
[11:59:46.237] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C7.dat
[11:59:46.237] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C8.dat
[11:59:46.237] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C9.dat
[11:59:46.237] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C10.dat
[11:59:46.237] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C11.dat
[11:59:46.237] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C12.dat
[11:59:46.238] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C13.dat
[11:59:46.238] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C14.dat
[11:59:46.238] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters_C15.dat
[11:59:46.238] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//tbmParameters_C0a.dat
[11:59:46.238] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//tbmParameters_C0b.dat
[11:59:46.238] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//tbmParameters_C1a.dat
[11:59:46.238] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//tbmParameters_C1b.dat
[11:59:46.238] <TB2> INFO: PixTestPretest::doTest() done, duration: 78 seconds
[11:59:46.368] <TB2> INFO: enter test to run
[11:59:46.368] <TB2> INFO: test: FullTest no parameter change
[11:59:46.368] <TB2> INFO: running: fulltest
[11:59:46.369] <TB2> INFO: ######################################################################
[11:59:46.369] <TB2> INFO: PixTestFullTest::doTest()
[11:59:46.369] <TB2> INFO: ######################################################################
[11:59:46.370] <TB2> INFO: ######################################################################
[11:59:46.370] <TB2> INFO: PixTestAlive::doTest()
[11:59:46.370] <TB2> INFO: ######################################################################
[11:59:46.371] <TB2> INFO: ----------------------------------------------------------------------
[11:59:46.371] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:59:46.371] <TB2> INFO: ----------------------------------------------------------------------
[11:59:46.606] <TB2> INFO: Expecting 41600 events.
[11:59:50.126] <TB2> INFO: 41600 events read in total (2929ms).
[11:59:50.127] <TB2> INFO: Test took 3754ms.
[11:59:50.352] <TB2> INFO: PixTestAlive::aliveTest() done
[11:59:50.352] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:59:50.353] <TB2> INFO: ----------------------------------------------------------------------
[11:59:50.353] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:59:50.353] <TB2> INFO: ----------------------------------------------------------------------
[11:59:50.585] <TB2> INFO: Expecting 41600 events.
[11:59:53.711] <TB2> INFO: 41600 events read in total (2534ms).
[11:59:53.711] <TB2> INFO: Test took 3356ms.
[11:59:53.712] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:59:53.952] <TB2> INFO: PixTestAlive::maskTest() done
[11:59:53.952] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:59:53.954] <TB2> INFO: ----------------------------------------------------------------------
[11:59:53.954] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:59:53.954] <TB2> INFO: ----------------------------------------------------------------------
[11:59:54.191] <TB2> INFO: Expecting 41600 events.
[11:59:57.642] <TB2> INFO: 41600 events read in total (2860ms).
[11:59:57.642] <TB2> INFO: Test took 3686ms.
[11:59:57.868] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[11:59:57.869] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:59:57.869] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:59:57.869] <TB2> INFO: Decoding statistics:
[11:59:57.869] <TB2> INFO: General information:
[11:59:57.869] <TB2> INFO: 16bit words read: 0
[11:59:57.869] <TB2> INFO: valid events total: 0
[11:59:57.869] <TB2> INFO: empty events: 0
[11:59:57.869] <TB2> INFO: valid events with pixels: 0
[11:59:57.869] <TB2> INFO: valid pixel hits: 0
[11:59:57.869] <TB2> INFO: Event errors: 0
[11:59:57.869] <TB2> INFO: start marker: 0
[11:59:57.869] <TB2> INFO: stop marker: 0
[11:59:57.869] <TB2> INFO: overflow: 0
[11:59:57.869] <TB2> INFO: invalid 5bit words: 0
[11:59:57.869] <TB2> INFO: invalid XOR eye diagram: 0
[11:59:57.869] <TB2> INFO: frame (failed synchr.): 0
[11:59:57.869] <TB2> INFO: idle data (no TBM trl): 0
[11:59:57.869] <TB2> INFO: no data (only TBM hdr): 0
[11:59:57.869] <TB2> INFO: TBM errors: 0
[11:59:57.869] <TB2> INFO: flawed TBM headers: 0
[11:59:57.869] <TB2> INFO: flawed TBM trailers: 0
[11:59:57.869] <TB2> INFO: event ID mismatches: 0
[11:59:57.869] <TB2> INFO: ROC errors: 0
[11:59:57.869] <TB2> INFO: missing ROC header(s): 0
[11:59:57.869] <TB2> INFO: misplaced readback start: 0
[11:59:57.869] <TB2> INFO: Pixel decoding errors: 0
[11:59:57.869] <TB2> INFO: pixel data incomplete: 0
[11:59:57.869] <TB2> INFO: pixel address: 0
[11:59:57.869] <TB2> INFO: pulse height fill bit: 0
[11:59:57.869] <TB2> INFO: buffer corruption: 0
[11:59:57.876] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C15.dat
[11:59:57.876] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[11:59:57.876] <TB2> INFO: ######################################################################
[11:59:57.876] <TB2> INFO: PixTestReadback::doTest()
[11:59:57.876] <TB2> INFO: ######################################################################
[11:59:57.877] <TB2> INFO: ----------------------------------------------------------------------
[11:59:57.877] <TB2> INFO: PixTestReadback::CalibrateVd()
[11:59:57.877] <TB2> INFO: ----------------------------------------------------------------------
[12:00:07.855] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C0.dat
[12:00:07.856] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C1.dat
[12:00:07.856] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C2.dat
[12:00:07.856] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C3.dat
[12:00:07.856] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C4.dat
[12:00:07.856] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C5.dat
[12:00:07.856] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C6.dat
[12:00:07.856] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C7.dat
[12:00:07.856] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C8.dat
[12:00:07.856] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C9.dat
[12:00:07.856] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C10.dat
[12:00:07.856] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C11.dat
[12:00:07.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C12.dat
[12:00:07.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C13.dat
[12:00:07.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C14.dat
[12:00:07.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C15.dat
[12:00:07.885] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:00:07.885] <TB2> INFO: ----------------------------------------------------------------------
[12:00:07.885] <TB2> INFO: PixTestReadback::CalibrateVa()
[12:00:07.885] <TB2> INFO: ----------------------------------------------------------------------
[12:00:17.778] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C0.dat
[12:00:17.778] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C1.dat
[12:00:17.779] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C2.dat
[12:00:17.779] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C3.dat
[12:00:17.779] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C4.dat
[12:00:17.779] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C5.dat
[12:00:17.779] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C6.dat
[12:00:17.779] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C7.dat
[12:00:17.779] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C8.dat
[12:00:17.779] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C9.dat
[12:00:17.779] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C10.dat
[12:00:17.779] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C11.dat
[12:00:17.779] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C12.dat
[12:00:17.779] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C13.dat
[12:00:17.780] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C14.dat
[12:00:17.780] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C15.dat
[12:00:17.809] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:00:17.809] <TB2> INFO: ----------------------------------------------------------------------
[12:00:17.809] <TB2> INFO: PixTestReadback::readbackVbg()
[12:00:17.809] <TB2> INFO: ----------------------------------------------------------------------
[12:00:25.448] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:00:25.448] <TB2> INFO: ----------------------------------------------------------------------
[12:00:25.448] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[12:00:25.448] <TB2> INFO: ----------------------------------------------------------------------
[12:00:25.448] <TB2> INFO: Vbg will be calibrated using Vd calibration
[12:00:25.448] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 156.9calibrated Vbg = 1.15335 :::*/*/*/*/
[12:00:25.448] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 164.2calibrated Vbg = 1.15776 :::*/*/*/*/
[12:00:25.448] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 151.5calibrated Vbg = 1.15199 :::*/*/*/*/
[12:00:25.448] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 155.6calibrated Vbg = 1.15118 :::*/*/*/*/
[12:00:25.448] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 155.2calibrated Vbg = 1.15256 :::*/*/*/*/
[12:00:25.448] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 149.7calibrated Vbg = 1.1581 :::*/*/*/*/
[12:00:25.448] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 150.5calibrated Vbg = 1.16256 :::*/*/*/*/
[12:00:25.448] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 159.7calibrated Vbg = 1.15454 :::*/*/*/*/
[12:00:25.448] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 161.6calibrated Vbg = 1.15184 :::*/*/*/*/
[12:00:25.448] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 153.4calibrated Vbg = 1.14621 :::*/*/*/*/
[12:00:25.448] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 157.1calibrated Vbg = 1.14435 :::*/*/*/*/
[12:00:25.448] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 156calibrated Vbg = 1.1409 :::*/*/*/*/
[12:00:25.448] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 165.8calibrated Vbg = 1.15086 :::*/*/*/*/
[12:00:25.448] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 154calibrated Vbg = 1.15351 :::*/*/*/*/
[12:00:25.448] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 154.4calibrated Vbg = 1.15539 :::*/*/*/*/
[12:00:25.448] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 147.9calibrated Vbg = 1.14858 :::*/*/*/*/
[12:00:25.450] <TB2> INFO: ----------------------------------------------------------------------
[12:00:25.450] <TB2> INFO: PixTestReadback::CalibrateIa()
[12:00:25.450] <TB2> INFO: ----------------------------------------------------------------------
[12:03:05.726] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C0.dat
[12:03:05.726] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C1.dat
[12:03:05.727] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C2.dat
[12:03:05.727] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C3.dat
[12:03:05.727] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C4.dat
[12:03:05.727] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C5.dat
[12:03:05.727] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C6.dat
[12:03:05.727] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C7.dat
[12:03:05.727] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C8.dat
[12:03:05.727] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C9.dat
[12:03:05.727] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C10.dat
[12:03:05.727] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C11.dat
[12:03:05.727] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C12.dat
[12:03:05.728] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C13.dat
[12:03:05.728] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C14.dat
[12:03:05.728] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//readbackCal_C15.dat
[12:03:05.758] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:03:05.759] <TB2> INFO: PixTestReadback::doTest() done
[12:03:05.760] <TB2> INFO: Decoding statistics:
[12:03:05.760] <TB2> INFO: General information:
[12:03:05.760] <TB2> INFO: 16bit words read: 1536
[12:03:05.760] <TB2> INFO: valid events total: 256
[12:03:05.760] <TB2> INFO: empty events: 256
[12:03:05.760] <TB2> INFO: valid events with pixels: 0
[12:03:05.760] <TB2> INFO: valid pixel hits: 0
[12:03:05.760] <TB2> INFO: Event errors: 0
[12:03:05.760] <TB2> INFO: start marker: 0
[12:03:05.760] <TB2> INFO: stop marker: 0
[12:03:05.760] <TB2> INFO: overflow: 0
[12:03:05.760] <TB2> INFO: invalid 5bit words: 0
[12:03:05.760] <TB2> INFO: invalid XOR eye diagram: 0
[12:03:05.760] <TB2> INFO: frame (failed synchr.): 0
[12:03:05.760] <TB2> INFO: idle data (no TBM trl): 0
[12:03:05.760] <TB2> INFO: no data (only TBM hdr): 0
[12:03:05.760] <TB2> INFO: TBM errors: 0
[12:03:05.760] <TB2> INFO: flawed TBM headers: 0
[12:03:05.760] <TB2> INFO: flawed TBM trailers: 0
[12:03:05.760] <TB2> INFO: event ID mismatches: 0
[12:03:05.760] <TB2> INFO: ROC errors: 0
[12:03:05.760] <TB2> INFO: missing ROC header(s): 0
[12:03:05.760] <TB2> INFO: misplaced readback start: 0
[12:03:05.760] <TB2> INFO: Pixel decoding errors: 0
[12:03:05.760] <TB2> INFO: pixel data incomplete: 0
[12:03:05.760] <TB2> INFO: pixel address: 0
[12:03:05.760] <TB2> INFO: pulse height fill bit: 0
[12:03:05.760] <TB2> INFO: buffer corruption: 0
[12:03:05.793] <TB2> INFO: ######################################################################
[12:03:05.793] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:03:05.793] <TB2> INFO: ######################################################################
[12:03:05.796] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:03:05.807] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:03:05.807] <TB2> INFO: run 1 of 1
[12:03:06.045] <TB2> INFO: Expecting 3120000 events.
[12:03:36.614] <TB2> INFO: 656690 events read in total (29977ms).











[12:04:06.985] <TB2> INFO: 1313095 events read in total (60348ms).











[12:04:37.395] <TB2> INFO: 1966745 events read in total (90758ms).











[12:05:07.984] <TB2> INFO: 2621725 events read in total (121347ms).











[12:05:30.800] <TB2> INFO: 3120000 events read in total (144163ms).
[12:05:30.874] <TB2> INFO: Test took 145067ms.
[12:05:54.664] <TB2> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 168 seconds
[12:05:54.664] <TB2> INFO: number of dead bumps (per ROC): 1 0 1 2 0 0 0 0 0 2 1 2 2 2 0 0
[12:05:54.664] <TB2> INFO: separation cut (per ROC): 103 106 102 107 88 107 111 108 108 110 116 106 105 106 108 106
[12:05:54.664] <TB2> INFO: Decoding statistics:
[12:05:54.664] <TB2> INFO: General information:
[12:05:54.664] <TB2> INFO: 16bit words read: 0
[12:05:54.664] <TB2> INFO: valid events total: 0
[12:05:54.664] <TB2> INFO: empty events: 0
[12:05:54.664] <TB2> INFO: valid events with pixels: 0
[12:05:54.664] <TB2> INFO: valid pixel hits: 0
[12:05:54.664] <TB2> INFO: Event errors: 0
[12:05:54.664] <TB2> INFO: start marker: 0
[12:05:54.664] <TB2> INFO: stop marker: 0
[12:05:54.664] <TB2> INFO: overflow: 0
[12:05:54.664] <TB2> INFO: invalid 5bit words: 0
[12:05:54.664] <TB2> INFO: invalid XOR eye diagram: 0
[12:05:54.664] <TB2> INFO: frame (failed synchr.): 0
[12:05:54.664] <TB2> INFO: idle data (no TBM trl): 0
[12:05:54.664] <TB2> INFO: no data (only TBM hdr): 0
[12:05:54.664] <TB2> INFO: TBM errors: 0
[12:05:54.664] <TB2> INFO: flawed TBM headers: 0
[12:05:54.664] <TB2> INFO: flawed TBM trailers: 0
[12:05:54.664] <TB2> INFO: event ID mismatches: 0
[12:05:54.664] <TB2> INFO: ROC errors: 0
[12:05:54.664] <TB2> INFO: missing ROC header(s): 0
[12:05:54.664] <TB2> INFO: misplaced readback start: 0
[12:05:54.664] <TB2> INFO: Pixel decoding errors: 0
[12:05:54.664] <TB2> INFO: pixel data incomplete: 0
[12:05:54.665] <TB2> INFO: pixel address: 0
[12:05:54.665] <TB2> INFO: pulse height fill bit: 0
[12:05:54.665] <TB2> INFO: buffer corruption: 0
[12:05:54.711] <TB2> INFO: ######################################################################
[12:05:54.711] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:05:54.711] <TB2> INFO: ######################################################################
[12:05:54.712] <TB2> INFO: ----------------------------------------------------------------------
[12:05:54.712] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:05:54.712] <TB2> INFO: ----------------------------------------------------------------------
[12:05:54.712] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:05:54.723] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[12:05:54.723] <TB2> INFO: run 1 of 1
[12:05:54.957] <TB2> INFO: Expecting 36608000 events.
[12:06:18.393] <TB2> INFO: 668950 events read in total (22844ms).
[12:06:40.809] <TB2> INFO: 1327450 events read in total (45260ms).
[12:07:03.764] <TB2> INFO: 1984550 events read in total (68215ms).
[12:07:26.592] <TB2> INFO: 2639450 events read in total (91043ms).
[12:07:49.676] <TB2> INFO: 3295250 events read in total (114127ms).
[12:08:12.629] <TB2> INFO: 3949600 events read in total (137080ms).
[12:08:35.524] <TB2> INFO: 4604650 events read in total (159975ms).
[12:08:58.436] <TB2> INFO: 5258800 events read in total (182887ms).
[12:09:21.312] <TB2> INFO: 5913700 events read in total (205763ms).
[12:09:43.999] <TB2> INFO: 6571350 events read in total (228450ms).
[12:10:06.857] <TB2> INFO: 7228450 events read in total (251308ms).
[12:10:29.783] <TB2> INFO: 7881200 events read in total (274234ms).
[12:10:52.704] <TB2> INFO: 8534250 events read in total (297155ms).
[12:11:15.346] <TB2> INFO: 9189750 events read in total (319797ms).
[12:11:37.938] <TB2> INFO: 9845550 events read in total (342389ms).
[12:12:01.230] <TB2> INFO: 10498400 events read in total (365681ms).
[12:12:23.791] <TB2> INFO: 11150950 events read in total (388242ms).
[12:12:46.494] <TB2> INFO: 11805450 events read in total (410945ms).
[12:13:09.360] <TB2> INFO: 12458650 events read in total (433811ms).
[12:13:32.150] <TB2> INFO: 13110300 events read in total (456601ms).
[12:13:54.996] <TB2> INFO: 13762150 events read in total (479447ms).
[12:14:17.506] <TB2> INFO: 14414050 events read in total (501957ms).
[12:14:40.119] <TB2> INFO: 15066550 events read in total (524570ms).
[12:15:02.617] <TB2> INFO: 15719300 events read in total (547068ms).
[12:15:25.428] <TB2> INFO: 16371950 events read in total (569879ms).
[12:15:48.467] <TB2> INFO: 17024450 events read in total (592918ms).
[12:16:11.060] <TB2> INFO: 17675500 events read in total (615511ms).
[12:16:33.739] <TB2> INFO: 18326700 events read in total (638190ms).
[12:16:56.016] <TB2> INFO: 18975900 events read in total (660467ms).
[12:17:19.102] <TB2> INFO: 19623550 events read in total (683553ms).
[12:17:41.699] <TB2> INFO: 20272800 events read in total (706150ms).
[12:18:04.578] <TB2> INFO: 20921200 events read in total (729029ms).
[12:18:27.451] <TB2> INFO: 21569350 events read in total (751903ms).
[12:18:50.209] <TB2> INFO: 22218650 events read in total (774660ms).
[12:19:12.814] <TB2> INFO: 22868500 events read in total (797265ms).
[12:19:35.541] <TB2> INFO: 23518200 events read in total (819992ms).
[12:19:58.521] <TB2> INFO: 24167750 events read in total (842972ms).
[12:20:21.272] <TB2> INFO: 24817900 events read in total (865723ms).
[12:20:44.290] <TB2> INFO: 25467200 events read in total (888741ms).
[12:21:07.281] <TB2> INFO: 26116850 events read in total (911732ms).
[12:21:30.198] <TB2> INFO: 26767300 events read in total (934649ms).
[12:21:52.736] <TB2> INFO: 27416900 events read in total (957187ms).
[12:22:15.665] <TB2> INFO: 28066300 events read in total (980116ms).
[12:22:38.378] <TB2> INFO: 28713750 events read in total (1002829ms).
[12:23:00.773] <TB2> INFO: 29363400 events read in total (1025224ms).
[12:23:23.370] <TB2> INFO: 30012450 events read in total (1047821ms).
[12:23:46.061] <TB2> INFO: 30662450 events read in total (1070512ms).
[12:24:09.029] <TB2> INFO: 31311900 events read in total (1093480ms).
[12:24:31.447] <TB2> INFO: 31961850 events read in total (1115898ms).
[12:24:54.224] <TB2> INFO: 32611950 events read in total (1138675ms).
[12:25:16.697] <TB2> INFO: 33263600 events read in total (1161148ms).
[12:25:39.465] <TB2> INFO: 33915550 events read in total (1183916ms).
[12:26:02.277] <TB2> INFO: 34566200 events read in total (1206728ms).
[12:26:25.335] <TB2> INFO: 35216500 events read in total (1229786ms).
[12:26:47.595] <TB2> INFO: 35867350 events read in total (1252046ms).
[12:27:10.347] <TB2> INFO: 36528700 events read in total (1274798ms).
[12:27:13.412] <TB2> INFO: 36608000 events read in total (1277863ms).
[12:27:13.464] <TB2> INFO: Test took 1278742ms.
[12:27:13.943] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:27:16.293] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:27:17.978] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:27:19.602] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:27:21.550] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:27:23.445] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:27:25.519] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:27:27.694] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:27:29.750] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:27:31.832] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:27:33.597] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:27:35.160] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:27:37.467] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:27:39.446] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:27:41.762] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:27:43.849] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:27:45.666] <TB2> INFO: PixTestScurves::scurves() done
[12:27:45.666] <TB2> INFO: Vcal mean: 109.97 128.02 120.77 117.60 96.95 114.41 120.37 123.46 128.87 112.50 127.01 114.84 118.24 115.27 111.99 117.11
[12:27:45.666] <TB2> INFO: Vcal RMS: 4.86 6.60 6.95 6.39 5.34 4.96 6.54 5.93 7.16 5.03 7.27 5.71 6.03 5.58 5.65 5.95
[12:27:45.666] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1310 seconds
[12:27:45.667] <TB2> INFO: Decoding statistics:
[12:27:45.667] <TB2> INFO: General information:
[12:27:45.667] <TB2> INFO: 16bit words read: 0
[12:27:45.667] <TB2> INFO: valid events total: 0
[12:27:45.667] <TB2> INFO: empty events: 0
[12:27:45.667] <TB2> INFO: valid events with pixels: 0
[12:27:45.667] <TB2> INFO: valid pixel hits: 0
[12:27:45.667] <TB2> INFO: Event errors: 0
[12:27:45.667] <TB2> INFO: start marker: 0
[12:27:45.667] <TB2> INFO: stop marker: 0
[12:27:45.667] <TB2> INFO: overflow: 0
[12:27:45.667] <TB2> INFO: invalid 5bit words: 0
[12:27:45.667] <TB2> INFO: invalid XOR eye diagram: 0
[12:27:45.667] <TB2> INFO: frame (failed synchr.): 0
[12:27:45.667] <TB2> INFO: idle data (no TBM trl): 0
[12:27:45.667] <TB2> INFO: no data (only TBM hdr): 0
[12:27:45.667] <TB2> INFO: TBM errors: 0
[12:27:45.667] <TB2> INFO: flawed TBM headers: 0
[12:27:45.667] <TB2> INFO: flawed TBM trailers: 0
[12:27:45.667] <TB2> INFO: event ID mismatches: 0
[12:27:45.667] <TB2> INFO: ROC errors: 0
[12:27:45.667] <TB2> INFO: missing ROC header(s): 0
[12:27:45.667] <TB2> INFO: misplaced readback start: 0
[12:27:45.667] <TB2> INFO: Pixel decoding errors: 0
[12:27:45.667] <TB2> INFO: pixel data incomplete: 0
[12:27:45.667] <TB2> INFO: pixel address: 0
[12:27:45.667] <TB2> INFO: pulse height fill bit: 0
[12:27:45.667] <TB2> INFO: buffer corruption: 0
[12:27:45.734] <TB2> INFO: ######################################################################
[12:27:45.734] <TB2> INFO: PixTestTrim::doTest()
[12:27:45.734] <TB2> INFO: ######################################################################
[12:27:45.735] <TB2> INFO: ----------------------------------------------------------------------
[12:27:45.735] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:27:45.735] <TB2> INFO: ----------------------------------------------------------------------
[12:27:45.775] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:27:45.775] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:27:45.784] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:27:45.784] <TB2> INFO: run 1 of 1
[12:27:46.019] <TB2> INFO: Expecting 5025280 events.
[12:28:17.138] <TB2> INFO: 822176 events read in total (30524ms).
[12:28:47.909] <TB2> INFO: 1642544 events read in total (61295ms).
[12:29:18.111] <TB2> INFO: 2460488 events read in total (91497ms).
[12:29:48.860] <TB2> INFO: 3274880 events read in total (122246ms).
[12:30:18.773] <TB2> INFO: 4087872 events read in total (152159ms).
[12:30:48.798] <TB2> INFO: 4900144 events read in total (182184ms).
[12:30:53.846] <TB2> INFO: 5025280 events read in total (187232ms).
[12:30:53.905] <TB2> INFO: Test took 188120ms.
[12:31:11.368] <TB2> INFO: ROC 0 VthrComp = 120
[12:31:11.368] <TB2> INFO: ROC 1 VthrComp = 130
[12:31:11.368] <TB2> INFO: ROC 2 VthrComp = 115
[12:31:11.368] <TB2> INFO: ROC 3 VthrComp = 122
[12:31:11.368] <TB2> INFO: ROC 4 VthrComp = 103
[12:31:11.368] <TB2> INFO: ROC 5 VthrComp = 126
[12:31:11.368] <TB2> INFO: ROC 6 VthrComp = 130
[12:31:11.368] <TB2> INFO: ROC 7 VthrComp = 129
[12:31:11.369] <TB2> INFO: ROC 8 VthrComp = 131
[12:31:11.369] <TB2> INFO: ROC 9 VthrComp = 122
[12:31:11.369] <TB2> INFO: ROC 10 VthrComp = 132
[12:31:11.369] <TB2> INFO: ROC 11 VthrComp = 114
[12:31:11.369] <TB2> INFO: ROC 12 VthrComp = 121
[12:31:11.369] <TB2> INFO: ROC 13 VthrComp = 122
[12:31:11.369] <TB2> INFO: ROC 14 VthrComp = 115
[12:31:11.369] <TB2> INFO: ROC 15 VthrComp = 118
[12:31:11.608] <TB2> INFO: Expecting 41600 events.
[12:31:15.156] <TB2> INFO: 41600 events read in total (2956ms).
[12:31:15.157] <TB2> INFO: Test took 3786ms.
[12:31:15.165] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:31:15.165] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:31:15.174] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:31:15.174] <TB2> INFO: run 1 of 1
[12:31:15.452] <TB2> INFO: Expecting 5025280 events.
[12:31:41.697] <TB2> INFO: 589312 events read in total (25654ms).
[12:32:07.737] <TB2> INFO: 1177512 events read in total (51694ms).
[12:32:33.990] <TB2> INFO: 1765776 events read in total (77947ms).
[12:32:59.696] <TB2> INFO: 2353360 events read in total (103653ms).
[12:33:25.240] <TB2> INFO: 2938952 events read in total (129197ms).
[12:33:51.615] <TB2> INFO: 3524416 events read in total (155572ms).
[12:34:17.490] <TB2> INFO: 4109416 events read in total (181447ms).
[12:34:43.737] <TB2> INFO: 4694424 events read in total (207694ms).
[12:34:58.788] <TB2> INFO: 5025280 events read in total (222745ms).
[12:34:58.854] <TB2> INFO: Test took 223680ms.
[12:35:23.707] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 59.0416 for pixel 0/17 mean/min/max = 45.5665/32.0576/59.0754
[12:35:23.708] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 62.9807 for pixel 0/71 mean/min/max = 46.6997/30.0686/63.3309
[12:35:23.708] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 64.3963 for pixel 5/0 mean/min/max = 47.9296/31.3493/64.5098
[12:35:23.708] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 62.0856 for pixel 12/79 mean/min/max = 46.6221/30.8311/62.4131
[12:35:23.709] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 59.1234 for pixel 36/79 mean/min/max = 46.1398/33.1555/59.1241
[12:35:23.709] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 55.5778 for pixel 8/74 mean/min/max = 43.7635/31.2215/56.3056
[12:35:23.709] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 60.4828 for pixel 51/62 mean/min/max = 45.9429/31.3903/60.4955
[12:35:23.710] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 60.5728 for pixel 13/20 mean/min/max = 46.0594/31.2322/60.8867
[12:35:23.710] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 63.3624 for pixel 0/53 mean/min/max = 47.7324/31.9444/63.5205
[12:35:23.710] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 57.7534 for pixel 3/4 mean/min/max = 45.2359/32.7034/57.7685
[12:35:23.711] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 62.3012 for pixel 23/70 mean/min/max = 47.0917/31.8245/62.3589
[12:35:23.711] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 61.6969 for pixel 4/74 mean/min/max = 46.7973/31.8239/61.7707
[12:35:23.711] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 61.1472 for pixel 0/4 mean/min/max = 46.0654/30.8669/61.2639
[12:35:23.712] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 59.0342 for pixel 10/11 mean/min/max = 45.3231/31.5287/59.1175
[12:35:23.712] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 59.637 for pixel 0/73 mean/min/max = 45.8117/31.6383/59.9851
[12:35:23.712] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 61.8708 for pixel 5/46 mean/min/max = 46.3079/30.7326/61.8832
[12:35:23.712] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:35:23.801] <TB2> INFO: Expecting 411648 events.
[12:35:33.280] <TB2> INFO: 411648 events read in total (8887ms).
[12:35:33.286] <TB2> INFO: Expecting 411648 events.
[12:35:42.569] <TB2> INFO: 411648 events read in total (8880ms).
[12:35:42.577] <TB2> INFO: Expecting 411648 events.
[12:35:51.928] <TB2> INFO: 411648 events read in total (8948ms).
[12:35:51.944] <TB2> INFO: Expecting 411648 events.
[12:36:01.184] <TB2> INFO: 411648 events read in total (8837ms).
[12:36:01.198] <TB2> INFO: Expecting 411648 events.
[12:36:10.633] <TB2> INFO: 411648 events read in total (9032ms).
[12:36:10.650] <TB2> INFO: Expecting 411648 events.
[12:36:20.054] <TB2> INFO: 411648 events read in total (9001ms).
[12:36:20.081] <TB2> INFO: Expecting 411648 events.
[12:36:29.352] <TB2> INFO: 411648 events read in total (8868ms).
[12:36:29.372] <TB2> INFO: Expecting 411648 events.
[12:36:38.838] <TB2> INFO: 411648 events read in total (9063ms).
[12:36:38.872] <TB2> INFO: Expecting 411648 events.
[12:36:47.995] <TB2> INFO: 411648 events read in total (8720ms).
[12:36:48.023] <TB2> INFO: Expecting 411648 events.
[12:36:57.332] <TB2> INFO: 411648 events read in total (8906ms).
[12:36:57.361] <TB2> INFO: Expecting 411648 events.
[12:37:06.689] <TB2> INFO: 411648 events read in total (8925ms).
[12:37:06.736] <TB2> INFO: Expecting 411648 events.
[12:37:16.077] <TB2> INFO: 411648 events read in total (8938ms).
[12:37:16.126] <TB2> INFO: Expecting 411648 events.
[12:37:25.437] <TB2> INFO: 411648 events read in total (8909ms).
[12:37:25.492] <TB2> INFO: Expecting 411648 events.
[12:37:34.900] <TB2> INFO: 411648 events read in total (9005ms).
[12:37:34.942] <TB2> INFO: Expecting 411648 events.
[12:37:44.264] <TB2> INFO: 411648 events read in total (8919ms).
[12:37:44.309] <TB2> INFO: Expecting 411648 events.
[12:37:53.671] <TB2> INFO: 411648 events read in total (8959ms).
[12:37:53.738] <TB2> INFO: Test took 150026ms.
[12:37:54.470] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:37:54.482] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:37:54.482] <TB2> INFO: run 1 of 1
[12:37:54.772] <TB2> INFO: Expecting 5025280 events.
[12:38:21.560] <TB2> INFO: 587768 events read in total (26196ms).
[12:38:47.560] <TB2> INFO: 1173608 events read in total (52196ms).
[12:39:13.474] <TB2> INFO: 1757856 events read in total (78110ms).
[12:39:39.936] <TB2> INFO: 2342848 events read in total (104572ms).
[12:40:06.070] <TB2> INFO: 2927184 events read in total (130707ms).
[12:40:31.910] <TB2> INFO: 3512672 events read in total (156546ms).
[12:40:57.838] <TB2> INFO: 4096192 events read in total (182474ms).
[12:41:23.574] <TB2> INFO: 4679128 events read in total (208210ms).
[12:41:39.083] <TB2> INFO: 5025280 events read in total (223719ms).
[12:41:39.203] <TB2> INFO: Test took 224722ms.
[12:42:02.889] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 2.500000 .. 147.808359
[12:42:03.123] <TB2> INFO: Expecting 208000 events.
[12:42:13.072] <TB2> INFO: 208000 events read in total (9357ms).
[12:42:13.073] <TB2> INFO: Test took 10183ms.
[12:42:13.119] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 157 (-1/-1) hits flags = 528 (plus default)
[12:42:13.128] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:42:13.128] <TB2> INFO: run 1 of 1
[12:42:13.406] <TB2> INFO: Expecting 5191680 events.
[12:42:39.901] <TB2> INFO: 582408 events read in total (25903ms).
[12:43:06.020] <TB2> INFO: 1164760 events read in total (52022ms).
[12:43:31.987] <TB2> INFO: 1746768 events read in total (77989ms).
[12:43:58.318] <TB2> INFO: 2329400 events read in total (104320ms).
[12:44:24.192] <TB2> INFO: 2911800 events read in total (130194ms).
[12:44:50.283] <TB2> INFO: 3493240 events read in total (156285ms).
[12:45:16.475] <TB2> INFO: 4074680 events read in total (182477ms).
[12:45:42.066] <TB2> INFO: 4655640 events read in total (208068ms).
[12:46:06.189] <TB2> INFO: 5191680 events read in total (232191ms).
[12:46:06.261] <TB2> INFO: Test took 233134ms.
[12:46:30.731] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.981198 .. 46.086967
[12:46:30.981] <TB2> INFO: Expecting 208000 events.
[12:46:40.946] <TB2> INFO: 208000 events read in total (9374ms).
[12:46:40.947] <TB2> INFO: Test took 10215ms.
[12:46:40.993] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[12:46:40.002] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:46:40.002] <TB2> INFO: run 1 of 1
[12:46:41.280] <TB2> INFO: Expecting 1331200 events.
[12:47:09.700] <TB2> INFO: 654632 events read in total (27829ms).
[12:47:37.363] <TB2> INFO: 1307768 events read in total (55493ms).
[12:47:38.725] <TB2> INFO: 1331200 events read in total (56855ms).
[12:47:38.749] <TB2> INFO: Test took 57748ms.
[12:47:52.443] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 26.460274 .. 47.804849
[12:47:52.676] <TB2> INFO: Expecting 208000 events.
[12:48:02.363] <TB2> INFO: 208000 events read in total (9096ms).
[12:48:02.364] <TB2> INFO: Test took 9920ms.
[12:48:02.433] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 57 (-1/-1) hits flags = 528 (plus default)
[12:48:02.441] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:48:02.441] <TB2> INFO: run 1 of 1
[12:48:02.719] <TB2> INFO: Expecting 1397760 events.
[12:48:31.121] <TB2> INFO: 655688 events read in total (27810ms).
[12:48:58.700] <TB2> INFO: 1310656 events read in total (55389ms).
[12:49:02.764] <TB2> INFO: 1397760 events read in total (59453ms).
[12:49:02.788] <TB2> INFO: Test took 60348ms.
[12:49:15.650] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 23.943581 .. 49.743217
[12:49:15.926] <TB2> INFO: Expecting 208000 events.
[12:49:25.906] <TB2> INFO: 208000 events read in total (9388ms).
[12:49:25.908] <TB2> INFO: Test took 10256ms.
[12:49:25.954] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 13 .. 59 (-1/-1) hits flags = 528 (plus default)
[12:49:25.963] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:49:25.963] <TB2> INFO: run 1 of 1
[12:49:26.241] <TB2> INFO: Expecting 1564160 events.
[12:49:54.955] <TB2> INFO: 660104 events read in total (28123ms).
[12:50:22.426] <TB2> INFO: 1319592 events read in total (55594ms).
[12:50:33.278] <TB2> INFO: 1564160 events read in total (66446ms).
[12:50:33.312] <TB2> INFO: Test took 67350ms.
[12:50:46.857] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:50:46.857] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:50:46.866] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:50:46.866] <TB2> INFO: run 1 of 1
[12:50:47.160] <TB2> INFO: Expecting 1364480 events.
[12:51:15.446] <TB2> INFO: 667264 events read in total (27694ms).
[12:51:44.304] <TB2> INFO: 1333920 events read in total (56552ms).
[12:51:46.099] <TB2> INFO: 1364480 events read in total (58347ms).
[12:51:46.130] <TB2> INFO: Test took 59265ms.
[12:51:58.217] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C0.dat
[12:51:58.217] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C1.dat
[12:51:58.217] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C2.dat
[12:51:58.217] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C3.dat
[12:51:58.217] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C4.dat
[12:51:58.217] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C5.dat
[12:51:58.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C6.dat
[12:51:58.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C7.dat
[12:51:58.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C8.dat
[12:51:58.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C9.dat
[12:51:58.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C10.dat
[12:51:58.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C11.dat
[12:51:58.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C12.dat
[12:51:58.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C13.dat
[12:51:58.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C14.dat
[12:51:58.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C15.dat
[12:51:58.218] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C0.dat
[12:51:58.226] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C1.dat
[12:51:58.234] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C2.dat
[12:51:58.242] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C3.dat
[12:51:58.250] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C4.dat
[12:51:58.257] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C5.dat
[12:51:58.265] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C6.dat
[12:51:58.272] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C7.dat
[12:51:58.280] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C8.dat
[12:51:58.286] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C9.dat
[12:51:58.292] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C10.dat
[12:51:58.297] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C11.dat
[12:51:58.303] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C12.dat
[12:51:58.308] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C13.dat
[12:51:58.313] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C14.dat
[12:51:58.319] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//trimParameters35_C15.dat
[12:51:58.324] <TB2> INFO: PixTestTrim::trimTest() done
[12:51:58.324] <TB2> INFO: vtrim: 144 122 147 120 131 115 117 144 145 134 148 127 137 155 116 142
[12:51:58.324] <TB2> INFO: vthrcomp: 120 130 115 122 103 126 130 129 131 122 132 114 121 122 115 118
[12:51:58.324] <TB2> INFO: vcal mean: 34.97 34.93 34.99 34.98 34.95 34.89 34.97 34.92 35.16 34.94 34.98 34.98 34.98 34.95 34.94 34.99
[12:51:58.324] <TB2> INFO: vcal RMS: 1.07 1.31 1.35 1.19 0.99 1.08 1.15 1.23 1.40 1.07 1.19 1.25 1.09 1.09 1.06 1.24
[12:51:58.324] <TB2> INFO: bits mean: 10.13 9.23 9.84 9.41 9.26 10.27 9.67 10.18 9.43 10.00 9.88 9.74 9.44 10.08 9.25 10.36
[12:51:58.324] <TB2> INFO: bits RMS: 2.40 3.02 2.55 2.82 2.64 2.60 2.66 2.46 2.69 2.42 2.44 2.55 2.83 2.53 2.85 2.43
[12:51:58.331] <TB2> INFO: ----------------------------------------------------------------------
[12:51:58.331] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:51:58.331] <TB2> INFO: ----------------------------------------------------------------------
[12:51:58.334] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:51:58.345] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:51:58.346] <TB2> INFO: run 1 of 1
[12:51:58.577] <TB2> INFO: Expecting 4160000 events.
[12:52:30.823] <TB2> INFO: 736450 events read in total (31655ms).
[12:53:02.351] <TB2> INFO: 1467880 events read in total (63183ms).
[12:53:33.411] <TB2> INFO: 2194935 events read in total (94243ms).
[12:54:04.847] <TB2> INFO: 2919335 events read in total (125679ms).
[12:54:35.942] <TB2> INFO: 3643800 events read in total (156774ms).
[12:54:58.372] <TB2> INFO: 4160000 events read in total (179204ms).
[12:54:58.442] <TB2> INFO: Test took 180097ms.
[12:55:22.734] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 222 (-1/-1) hits flags = 528 (plus default)
[12:55:22.743] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:55:22.744] <TB2> INFO: run 1 of 1
[12:55:22.978] <TB2> INFO: Expecting 4638400 events.
[12:55:54.011] <TB2> INFO: 688995 events read in total (30441ms).
[12:56:24.251] <TB2> INFO: 1375785 events read in total (60681ms).
[12:56:54.828] <TB2> INFO: 2059670 events read in total (91258ms).
[12:57:25.265] <TB2> INFO: 2741015 events read in total (121695ms).
[12:57:55.683] <TB2> INFO: 3422510 events read in total (152113ms).
[12:58:25.922] <TB2> INFO: 4103790 events read in total (182352ms).
[12:58:49.470] <TB2> INFO: 4638400 events read in total (205900ms).
[12:58:49.561] <TB2> INFO: Test took 206817ms.
[12:59:17.967] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[12:59:17.978] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:59:17.978] <TB2> INFO: run 1 of 1
[12:59:18.210] <TB2> INFO: Expecting 4139200 events.
[12:59:50.020] <TB2> INFO: 715030 events read in total (31219ms).
[13:00:20.739] <TB2> INFO: 1426125 events read in total (61938ms).
[13:00:51.645] <TB2> INFO: 2133885 events read in total (92844ms).
[13:01:22.278] <TB2> INFO: 2838685 events read in total (123477ms).
[13:01:53.365] <TB2> INFO: 3544270 events read in total (154564ms).
[13:02:19.606] <TB2> INFO: 4139200 events read in total (180805ms).
[13:02:19.661] <TB2> INFO: Test took 181682ms.
[13:02:45.125] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:02:45.134] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:02:45.134] <TB2> INFO: run 1 of 1
[13:02:45.367] <TB2> INFO: Expecting 4160000 events.
[13:03:16.915] <TB2> INFO: 713890 events read in total (30956ms).
[13:03:48.114] <TB2> INFO: 1423990 events read in total (62155ms).
[13:04:18.769] <TB2> INFO: 2130700 events read in total (92810ms).
[13:04:49.719] <TB2> INFO: 2834600 events read in total (123760ms).
[13:05:21.088] <TB2> INFO: 3538905 events read in total (155129ms).
[13:05:48.275] <TB2> INFO: 4160000 events read in total (182316ms).
[13:05:48.356] <TB2> INFO: Test took 183221ms.
[13:06:13.459] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[13:06:13.471] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:06:13.471] <TB2> INFO: run 1 of 1
[13:06:13.757] <TB2> INFO: Expecting 4139200 events.
[13:06:45.350] <TB2> INFO: 715345 events read in total (31001ms).
[13:07:16.324] <TB2> INFO: 1426665 events read in total (61975ms).
[13:07:47.670] <TB2> INFO: 2134485 events read in total (93321ms).
[13:08:18.637] <TB2> INFO: 2839470 events read in total (124288ms).
[13:08:49.791] <TB2> INFO: 3545085 events read in total (155442ms).
[13:09:15.689] <TB2> INFO: 4139200 events read in total (181340ms).
[13:09:15.745] <TB2> INFO: Test took 182273ms.
[13:09:40.434] <TB2> INFO: PixTestTrim::trimBitTest() done
[13:09:40.435] <TB2> INFO: PixTestTrim::doTest() done, duration: 2514 seconds
[13:09:40.435] <TB2> INFO: Decoding statistics:
[13:09:40.435] <TB2> INFO: General information:
[13:09:40.435] <TB2> INFO: 16bit words read: 0
[13:09:40.435] <TB2> INFO: valid events total: 0
[13:09:40.435] <TB2> INFO: empty events: 0
[13:09:40.435] <TB2> INFO: valid events with pixels: 0
[13:09:40.435] <TB2> INFO: valid pixel hits: 0
[13:09:40.435] <TB2> INFO: Event errors: 0
[13:09:40.435] <TB2> INFO: start marker: 0
[13:09:40.435] <TB2> INFO: stop marker: 0
[13:09:40.435] <TB2> INFO: overflow: 0
[13:09:40.435] <TB2> INFO: invalid 5bit words: 0
[13:09:40.435] <TB2> INFO: invalid XOR eye diagram: 0
[13:09:40.435] <TB2> INFO: frame (failed synchr.): 0
[13:09:40.435] <TB2> INFO: idle data (no TBM trl): 0
[13:09:40.435] <TB2> INFO: no data (only TBM hdr): 0
[13:09:40.435] <TB2> INFO: TBM errors: 0
[13:09:40.435] <TB2> INFO: flawed TBM headers: 0
[13:09:40.435] <TB2> INFO: flawed TBM trailers: 0
[13:09:40.435] <TB2> INFO: event ID mismatches: 0
[13:09:40.435] <TB2> INFO: ROC errors: 0
[13:09:40.435] <TB2> INFO: missing ROC header(s): 0
[13:09:40.435] <TB2> INFO: misplaced readback start: 0
[13:09:40.435] <TB2> INFO: Pixel decoding errors: 0
[13:09:40.435] <TB2> INFO: pixel data incomplete: 0
[13:09:40.435] <TB2> INFO: pixel address: 0
[13:09:40.435] <TB2> INFO: pulse height fill bit: 0
[13:09:40.435] <TB2> INFO: buffer corruption: 0
[13:09:41.061] <TB2> INFO: ######################################################################
[13:09:41.061] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:09:41.061] <TB2> INFO: ######################################################################
[13:09:41.333] <TB2> INFO: Expecting 41600 events.
[13:09:44.884] <TB2> INFO: 41600 events read in total (2959ms).
[13:09:44.885] <TB2> INFO: Test took 3823ms.
[13:09:45.320] <TB2> INFO: Expecting 41600 events.
[13:09:48.866] <TB2> INFO: 41600 events read in total (2954ms).
[13:09:48.867] <TB2> INFO: Test took 3779ms.
[13:09:49.155] <TB2> INFO: Expecting 41600 events.
[13:09:52.628] <TB2> INFO: 41600 events read in total (2882ms).
[13:09:52.628] <TB2> INFO: Test took 3738ms.
[13:09:52.916] <TB2> INFO: Expecting 41600 events.
[13:09:56.418] <TB2> INFO: 41600 events read in total (2910ms).
[13:09:56.419] <TB2> INFO: Test took 3767ms.
[13:09:56.707] <TB2> INFO: Expecting 41600 events.
[13:10:00.433] <TB2> INFO: 41600 events read in total (3135ms).
[13:10:00.434] <TB2> INFO: Test took 3992ms.
[13:10:00.783] <TB2> INFO: Expecting 41600 events.
[13:10:04.519] <TB2> INFO: 41600 events read in total (3144ms).
[13:10:04.520] <TB2> INFO: Test took 4058ms.
[13:10:04.812] <TB2> INFO: Expecting 41600 events.
[13:10:08.284] <TB2> INFO: 41600 events read in total (2881ms).
[13:10:08.285] <TB2> INFO: Test took 3742ms.
[13:10:08.599] <TB2> INFO: Expecting 41600 events.
[13:10:12.239] <TB2> INFO: 41600 events read in total (3049ms).
[13:10:12.240] <TB2> INFO: Test took 3932ms.
[13:10:12.528] <TB2> INFO: Expecting 41600 events.
[13:10:16.120] <TB2> INFO: 41600 events read in total (3000ms).
[13:10:16.120] <TB2> INFO: Test took 3856ms.
[13:10:16.408] <TB2> INFO: Expecting 41600 events.
[13:10:19.966] <TB2> INFO: 41600 events read in total (2966ms).
[13:10:19.967] <TB2> INFO: Test took 3823ms.
[13:10:20.255] <TB2> INFO: Expecting 41600 events.
[13:10:23.958] <TB2> INFO: 41600 events read in total (3112ms).
[13:10:23.960] <TB2> INFO: Test took 3970ms.
[13:10:24.251] <TB2> INFO: Expecting 41600 events.
[13:10:27.727] <TB2> INFO: 41600 events read in total (2884ms).
[13:10:27.728] <TB2> INFO: Test took 3741ms.
[13:10:28.016] <TB2> INFO: Expecting 41600 events.
[13:10:31.583] <TB2> INFO: 41600 events read in total (2975ms).
[13:10:31.583] <TB2> INFO: Test took 3832ms.
[13:10:31.885] <TB2> INFO: Expecting 41600 events.
[13:10:35.360] <TB2> INFO: 41600 events read in total (2883ms).
[13:10:35.361] <TB2> INFO: Test took 3751ms.
[13:10:35.649] <TB2> INFO: Expecting 41600 events.
[13:10:39.169] <TB2> INFO: 41600 events read in total (2928ms).
[13:10:39.170] <TB2> INFO: Test took 3786ms.
[13:10:39.461] <TB2> INFO: Expecting 41600 events.
[13:10:43.048] <TB2> INFO: 41600 events read in total (2995ms).
[13:10:43.048] <TB2> INFO: Test took 3851ms.
[13:10:43.363] <TB2> INFO: Expecting 41600 events.
[13:10:46.930] <TB2> INFO: 41600 events read in total (2975ms).
[13:10:46.931] <TB2> INFO: Test took 3856ms.
[13:10:47.219] <TB2> INFO: Expecting 41600 events.
[13:10:50.820] <TB2> INFO: 41600 events read in total (3010ms).
[13:10:50.820] <TB2> INFO: Test took 3866ms.
[13:10:51.108] <TB2> INFO: Expecting 41600 events.
[13:10:54.746] <TB2> INFO: 41600 events read in total (3046ms).
[13:10:54.747] <TB2> INFO: Test took 3903ms.
[13:10:55.069] <TB2> INFO: Expecting 41600 events.
[13:10:58.581] <TB2> INFO: 41600 events read in total (2920ms).
[13:10:58.582] <TB2> INFO: Test took 3808ms.
[13:10:58.874] <TB2> INFO: Expecting 41600 events.
[13:11:02.464] <TB2> INFO: 41600 events read in total (2999ms).
[13:11:02.465] <TB2> INFO: Test took 3856ms.
[13:11:02.785] <TB2> INFO: Expecting 41600 events.
[13:11:06.304] <TB2> INFO: 41600 events read in total (2928ms).
[13:11:06.305] <TB2> INFO: Test took 3817ms.
[13:11:06.593] <TB2> INFO: Expecting 41600 events.
[13:11:10.201] <TB2> INFO: 41600 events read in total (3016ms).
[13:11:10.201] <TB2> INFO: Test took 3872ms.
[13:11:10.489] <TB2> INFO: Expecting 41600 events.
[13:11:14.338] <TB2> INFO: 41600 events read in total (3257ms).
[13:11:14.339] <TB2> INFO: Test took 4114ms.
[13:11:14.631] <TB2> INFO: Expecting 41600 events.
[13:11:18.222] <TB2> INFO: 41600 events read in total (3000ms).
[13:11:18.223] <TB2> INFO: Test took 3857ms.
[13:11:18.511] <TB2> INFO: Expecting 41600 events.
[13:11:22.076] <TB2> INFO: 41600 events read in total (2974ms).
[13:11:22.077] <TB2> INFO: Test took 3831ms.
[13:11:22.369] <TB2> INFO: Expecting 41600 events.
[13:11:25.949] <TB2> INFO: 41600 events read in total (2989ms).
[13:11:25.949] <TB2> INFO: Test took 3845ms.
[13:11:26.237] <TB2> INFO: Expecting 41600 events.
[13:11:29.834] <TB2> INFO: 41600 events read in total (3005ms).
[13:11:29.834] <TB2> INFO: Test took 3861ms.
[13:11:30.128] <TB2> INFO: Expecting 41600 events.
[13:11:33.718] <TB2> INFO: 41600 events read in total (2998ms).
[13:11:33.718] <TB2> INFO: Test took 3855ms.
[13:11:34.007] <TB2> INFO: Expecting 2560 events.
[13:11:34.898] <TB2> INFO: 2560 events read in total (299ms).
[13:11:34.898] <TB2> INFO: Test took 1167ms.
[13:11:35.206] <TB2> INFO: Expecting 2560 events.
[13:11:36.088] <TB2> INFO: 2560 events read in total (291ms).
[13:11:36.088] <TB2> INFO: Test took 1190ms.
[13:11:36.396] <TB2> INFO: Expecting 2560 events.
[13:11:37.282] <TB2> INFO: 2560 events read in total (295ms).
[13:11:37.282] <TB2> INFO: Test took 1194ms.
[13:11:37.590] <TB2> INFO: Expecting 2560 events.
[13:11:38.474] <TB2> INFO: 2560 events read in total (292ms).
[13:11:38.474] <TB2> INFO: Test took 1191ms.
[13:11:38.782] <TB2> INFO: Expecting 2560 events.
[13:11:39.660] <TB2> INFO: 2560 events read in total (287ms).
[13:11:39.660] <TB2> INFO: Test took 1186ms.
[13:11:39.968] <TB2> INFO: Expecting 2560 events.
[13:11:40.848] <TB2> INFO: 2560 events read in total (288ms).
[13:11:40.848] <TB2> INFO: Test took 1187ms.
[13:11:41.156] <TB2> INFO: Expecting 2560 events.
[13:11:42.035] <TB2> INFO: 2560 events read in total (288ms).
[13:11:42.035] <TB2> INFO: Test took 1186ms.
[13:11:42.343] <TB2> INFO: Expecting 2560 events.
[13:11:43.221] <TB2> INFO: 2560 events read in total (286ms).
[13:11:43.221] <TB2> INFO: Test took 1185ms.
[13:11:43.529] <TB2> INFO: Expecting 2560 events.
[13:11:44.408] <TB2> INFO: 2560 events read in total (288ms).
[13:11:44.409] <TB2> INFO: Test took 1188ms.
[13:11:44.716] <TB2> INFO: Expecting 2560 events.
[13:11:45.598] <TB2> INFO: 2560 events read in total (290ms).
[13:11:45.599] <TB2> INFO: Test took 1190ms.
[13:11:45.907] <TB2> INFO: Expecting 2560 events.
[13:11:46.787] <TB2> INFO: 2560 events read in total (288ms).
[13:11:46.787] <TB2> INFO: Test took 1188ms.
[13:11:47.095] <TB2> INFO: Expecting 2560 events.
[13:11:47.978] <TB2> INFO: 2560 events read in total (291ms).
[13:11:47.978] <TB2> INFO: Test took 1190ms.
[13:11:48.286] <TB2> INFO: Expecting 2560 events.
[13:11:49.170] <TB2> INFO: 2560 events read in total (292ms).
[13:11:49.170] <TB2> INFO: Test took 1191ms.
[13:11:49.478] <TB2> INFO: Expecting 2560 events.
[13:11:50.362] <TB2> INFO: 2560 events read in total (292ms).
[13:11:50.363] <TB2> INFO: Test took 1192ms.
[13:11:50.671] <TB2> INFO: Expecting 2560 events.
[13:11:51.557] <TB2> INFO: 2560 events read in total (295ms).
[13:11:51.557] <TB2> INFO: Test took 1194ms.
[13:11:51.865] <TB2> INFO: Expecting 2560 events.
[13:11:52.753] <TB2> INFO: 2560 events read in total (296ms).
[13:11:52.753] <TB2> INFO: Test took 1195ms.
[13:11:52.756] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:11:53.061] <TB2> INFO: Expecting 655360 events.
[13:12:07.835] <TB2> INFO: 655360 events read in total (14182ms).
[13:12:07.845] <TB2> INFO: Expecting 655360 events.
[13:12:22.334] <TB2> INFO: 655360 events read in total (14086ms).
[13:12:22.348] <TB2> INFO: Expecting 655360 events.
[13:12:36.822] <TB2> INFO: 655360 events read in total (14071ms).
[13:12:36.851] <TB2> INFO: Expecting 655360 events.
[13:12:51.247] <TB2> INFO: 655360 events read in total (13994ms).
[13:12:51.280] <TB2> INFO: Expecting 655360 events.
[13:13:05.841] <TB2> INFO: 655360 events read in total (14158ms).
[13:13:05.884] <TB2> INFO: Expecting 655360 events.
[13:13:20.313] <TB2> INFO: 655360 events read in total (14026ms).
[13:13:20.346] <TB2> INFO: Expecting 655360 events.
[13:13:34.822] <TB2> INFO: 655360 events read in total (14073ms).
[13:13:34.879] <TB2> INFO: Expecting 655360 events.
[13:13:49.347] <TB2> INFO: 655360 events read in total (14065ms).
[13:13:49.385] <TB2> INFO: Expecting 655360 events.
[13:14:03.850] <TB2> INFO: 655360 events read in total (14062ms).
[13:14:03.893] <TB2> INFO: Expecting 655360 events.
[13:14:18.337] <TB2> INFO: 655360 events read in total (14041ms).
[13:14:18.382] <TB2> INFO: Expecting 655360 events.
[13:14:32.817] <TB2> INFO: 655360 events read in total (14032ms).
[13:14:32.868] <TB2> INFO: Expecting 655360 events.
[13:14:47.404] <TB2> INFO: 655360 events read in total (14133ms).
[13:14:47.461] <TB2> INFO: Expecting 655360 events.
[13:15:01.824] <TB2> INFO: 655360 events read in total (13960ms).
[13:15:01.882] <TB2> INFO: Expecting 655360 events.
[13:15:16.469] <TB2> INFO: 655360 events read in total (14184ms).
[13:15:16.564] <TB2> INFO: Expecting 655360 events.
[13:15:31.137] <TB2> INFO: 655360 events read in total (14170ms).
[13:15:31.240] <TB2> INFO: Expecting 655360 events.
[13:15:45.614] <TB2> INFO: 655360 events read in total (13971ms).
[13:15:45.688] <TB2> INFO: Test took 232932ms.
[13:15:45.767] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:15:46.032] <TB2> INFO: Expecting 655360 events.
[13:16:00.557] <TB2> INFO: 655360 events read in total (13933ms).
[13:16:00.567] <TB2> INFO: Expecting 655360 events.
[13:16:14.857] <TB2> INFO: 655360 events read in total (13887ms).
[13:16:14.877] <TB2> INFO: Expecting 655360 events.
[13:16:29.347] <TB2> INFO: 655360 events read in total (14067ms).
[13:16:29.365] <TB2> INFO: Expecting 655360 events.
[13:16:43.613] <TB2> INFO: 655360 events read in total (13845ms).
[13:16:43.645] <TB2> INFO: Expecting 655360 events.
[13:16:58.078] <TB2> INFO: 655360 events read in total (14030ms).
[13:16:58.105] <TB2> INFO: Expecting 655360 events.
[13:17:12.532] <TB2> INFO: 655360 events read in total (14024ms).
[13:17:12.562] <TB2> INFO: Expecting 655360 events.
[13:17:26.873] <TB2> INFO: 655360 events read in total (13908ms).
[13:17:26.913] <TB2> INFO: Expecting 655360 events.
[13:17:41.207] <TB2> INFO: 655360 events read in total (13891ms).
[13:17:41.263] <TB2> INFO: Expecting 655360 events.
[13:17:55.551] <TB2> INFO: 655360 events read in total (13885ms).
[13:17:55.594] <TB2> INFO: Expecting 655360 events.
[13:18:09.740] <TB2> INFO: 655360 events read in total (13743ms).
[13:18:09.785] <TB2> INFO: Expecting 655360 events.
[13:18:24.062] <TB2> INFO: 655360 events read in total (13874ms).
[13:18:24.140] <TB2> INFO: Expecting 655360 events.
[13:18:38.237] <TB2> INFO: 655360 events read in total (13694ms).
[13:18:38.293] <TB2> INFO: Expecting 655360 events.
[13:18:52.631] <TB2> INFO: 655360 events read in total (13935ms).
[13:18:52.689] <TB2> INFO: Expecting 655360 events.
[13:19:07.052] <TB2> INFO: 655360 events read in total (13960ms).
[13:19:07.117] <TB2> INFO: Expecting 655360 events.
[13:19:21.337] <TB2> INFO: 655360 events read in total (13817ms).
[13:19:21.406] <TB2> INFO: Expecting 655360 events.
[13:19:35.908] <TB2> INFO: 655360 events read in total (14099ms).
[13:19:35.983] <TB2> INFO: Test took 230216ms.
[13:19:36.137] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:19:36.142] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:19:36.146] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:19:36.151] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:19:36.155] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:19:36.160] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:19:36.165] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:19:36.170] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:19:36.175] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:19:36.180] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:19:36.185] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[13:19:36.190] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:19:36.195] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:19:36.200] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:19:36.206] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:19:36.214] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:19:36.221] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[13:19:36.228] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[13:19:36.234] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[13:19:36.241] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[13:19:36.249] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[13:19:36.256] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[13:19:36.263] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:19:36.270] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:19:36.277] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:19:36.285] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:19:36.292] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:19:36.299] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:19:36.306] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:19:36.313] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:19:36.320] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:19:36.328] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:19:36.335] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:19:36.342] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:19:36.349] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:19:36.357] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:19:36.364] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:19:36.371] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[13:19:36.378] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[13:19:36.385] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[13:19:36.393] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[13:19:36.400] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[13:19:36.405] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:19:36.410] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:19:36.444] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C0.dat
[13:19:36.445] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C1.dat
[13:19:36.445] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C2.dat
[13:19:36.445] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C3.dat
[13:19:36.445] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C4.dat
[13:19:36.445] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C5.dat
[13:19:36.445] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C6.dat
[13:19:36.445] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C7.dat
[13:19:36.445] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C8.dat
[13:19:36.445] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C9.dat
[13:19:36.445] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C10.dat
[13:19:36.445] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C11.dat
[13:19:36.446] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C12.dat
[13:19:36.446] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C13.dat
[13:19:36.446] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C14.dat
[13:19:36.446] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//dacParameters35_C15.dat
[13:19:36.680] <TB2> INFO: Expecting 41600 events.
[13:19:39.806] <TB2> INFO: 41600 events read in total (2534ms).
[13:19:39.807] <TB2> INFO: Test took 3359ms.
[13:19:40.249] <TB2> INFO: Expecting 41600 events.
[13:19:43.315] <TB2> INFO: 41600 events read in total (2475ms).
[13:19:43.316] <TB2> INFO: Test took 3299ms.
[13:19:43.762] <TB2> INFO: Expecting 41600 events.
[13:19:46.930] <TB2> INFO: 41600 events read in total (2577ms).
[13:19:46.930] <TB2> INFO: Test took 3400ms.
[13:19:47.150] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:19:47.239] <TB2> INFO: Expecting 2560 events.
[13:19:48.123] <TB2> INFO: 2560 events read in total (292ms).
[13:19:48.124] <TB2> INFO: Test took 974ms.
[13:19:48.125] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:19:48.432] <TB2> INFO: Expecting 2560 events.
[13:19:49.320] <TB2> INFO: 2560 events read in total (296ms).
[13:19:49.320] <TB2> INFO: Test took 1195ms.
[13:19:49.322] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:19:49.628] <TB2> INFO: Expecting 2560 events.
[13:19:50.515] <TB2> INFO: 2560 events read in total (295ms).
[13:19:50.515] <TB2> INFO: Test took 1193ms.
[13:19:50.517] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:19:50.823] <TB2> INFO: Expecting 2560 events.
[13:19:51.707] <TB2> INFO: 2560 events read in total (292ms).
[13:19:51.707] <TB2> INFO: Test took 1190ms.
[13:19:51.709] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:19:52.016] <TB2> INFO: Expecting 2560 events.
[13:19:52.900] <TB2> INFO: 2560 events read in total (293ms).
[13:19:52.900] <TB2> INFO: Test took 1191ms.
[13:19:52.901] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:19:53.208] <TB2> INFO: Expecting 2560 events.
[13:19:54.092] <TB2> INFO: 2560 events read in total (292ms).
[13:19:54.093] <TB2> INFO: Test took 1192ms.
[13:19:54.094] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:19:54.401] <TB2> INFO: Expecting 2560 events.
[13:19:55.285] <TB2> INFO: 2560 events read in total (293ms).
[13:19:55.285] <TB2> INFO: Test took 1191ms.
[13:19:55.287] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:19:55.593] <TB2> INFO: Expecting 2560 events.
[13:19:56.477] <TB2> INFO: 2560 events read in total (292ms).
[13:19:56.477] <TB2> INFO: Test took 1190ms.
[13:19:56.479] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:19:56.786] <TB2> INFO: Expecting 2560 events.
[13:19:57.669] <TB2> INFO: 2560 events read in total (291ms).
[13:19:57.670] <TB2> INFO: Test took 1191ms.
[13:19:57.671] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:19:57.978] <TB2> INFO: Expecting 2560 events.
[13:19:58.858] <TB2> INFO: 2560 events read in total (288ms).
[13:19:58.858] <TB2> INFO: Test took 1187ms.
[13:19:58.860] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:19:59.166] <TB2> INFO: Expecting 2560 events.
[13:20:00.047] <TB2> INFO: 2560 events read in total (289ms).
[13:20:00.048] <TB2> INFO: Test took 1188ms.
[13:20:00.049] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:00.356] <TB2> INFO: Expecting 2560 events.
[13:20:01.239] <TB2> INFO: 2560 events read in total (292ms).
[13:20:01.239] <TB2> INFO: Test took 1190ms.
[13:20:01.241] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:01.547] <TB2> INFO: Expecting 2560 events.
[13:20:02.427] <TB2> INFO: 2560 events read in total (288ms).
[13:20:02.427] <TB2> INFO: Test took 1186ms.
[13:20:02.429] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:02.735] <TB2> INFO: Expecting 2560 events.
[13:20:03.617] <TB2> INFO: 2560 events read in total (290ms).
[13:20:03.617] <TB2> INFO: Test took 1189ms.
[13:20:03.619] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:03.925] <TB2> INFO: Expecting 2560 events.
[13:20:04.805] <TB2> INFO: 2560 events read in total (288ms).
[13:20:04.805] <TB2> INFO: Test took 1186ms.
[13:20:04.807] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:05.114] <TB2> INFO: Expecting 2560 events.
[13:20:05.993] <TB2> INFO: 2560 events read in total (288ms).
[13:20:05.993] <TB2> INFO: Test took 1186ms.
[13:20:05.995] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:06.301] <TB2> INFO: Expecting 2560 events.
[13:20:07.180] <TB2> INFO: 2560 events read in total (287ms).
[13:20:07.180] <TB2> INFO: Test took 1185ms.
[13:20:07.182] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:07.489] <TB2> INFO: Expecting 2560 events.
[13:20:08.369] <TB2> INFO: 2560 events read in total (288ms).
[13:20:08.370] <TB2> INFO: Test took 1188ms.
[13:20:08.371] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:08.678] <TB2> INFO: Expecting 2560 events.
[13:20:09.562] <TB2> INFO: 2560 events read in total (293ms).
[13:20:09.562] <TB2> INFO: Test took 1191ms.
[13:20:09.564] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:09.870] <TB2> INFO: Expecting 2560 events.
[13:20:10.753] <TB2> INFO: 2560 events read in total (292ms).
[13:20:10.753] <TB2> INFO: Test took 1190ms.
[13:20:10.755] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:11.061] <TB2> INFO: Expecting 2560 events.
[13:20:11.946] <TB2> INFO: 2560 events read in total (293ms).
[13:20:11.946] <TB2> INFO: Test took 1191ms.
[13:20:11.948] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:12.254] <TB2> INFO: Expecting 2560 events.
[13:20:13.137] <TB2> INFO: 2560 events read in total (291ms).
[13:20:13.137] <TB2> INFO: Test took 1189ms.
[13:20:13.139] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:13.445] <TB2> INFO: Expecting 2560 events.
[13:20:14.324] <TB2> INFO: 2560 events read in total (287ms).
[13:20:14.324] <TB2> INFO: Test took 1185ms.
[13:20:14.326] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:14.633] <TB2> INFO: Expecting 2560 events.
[13:20:15.512] <TB2> INFO: 2560 events read in total (287ms).
[13:20:15.512] <TB2> INFO: Test took 1186ms.
[13:20:15.514] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:15.821] <TB2> INFO: Expecting 2560 events.
[13:20:16.709] <TB2> INFO: 2560 events read in total (296ms).
[13:20:16.709] <TB2> INFO: Test took 1195ms.
[13:20:16.711] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:17.018] <TB2> INFO: Expecting 2560 events.
[13:20:17.906] <TB2> INFO: 2560 events read in total (297ms).
[13:20:17.906] <TB2> INFO: Test took 1195ms.
[13:20:17.908] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:18.215] <TB2> INFO: Expecting 2560 events.
[13:20:19.103] <TB2> INFO: 2560 events read in total (297ms).
[13:20:19.103] <TB2> INFO: Test took 1195ms.
[13:20:19.105] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:19.412] <TB2> INFO: Expecting 2560 events.
[13:20:20.295] <TB2> INFO: 2560 events read in total (292ms).
[13:20:20.296] <TB2> INFO: Test took 1191ms.
[13:20:20.298] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:20.604] <TB2> INFO: Expecting 2560 events.
[13:20:21.488] <TB2> INFO: 2560 events read in total (292ms).
[13:20:21.488] <TB2> INFO: Test took 1190ms.
[13:20:21.490] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:21.797] <TB2> INFO: Expecting 2560 events.
[13:20:22.685] <TB2> INFO: 2560 events read in total (297ms).
[13:20:22.685] <TB2> INFO: Test took 1195ms.
[13:20:22.687] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:22.993] <TB2> INFO: Expecting 2560 events.
[13:20:23.880] <TB2> INFO: 2560 events read in total (295ms).
[13:20:23.880] <TB2> INFO: Test took 1193ms.
[13:20:23.882] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:20:24.189] <TB2> INFO: Expecting 2560 events.
[13:20:25.076] <TB2> INFO: 2560 events read in total (296ms).
[13:20:25.076] <TB2> INFO: Test took 1194ms.
[13:20:25.540] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 644 seconds
[13:20:25.540] <TB2> INFO: PH scale (per ROC): 52 54 47 61 42 54 48 63 62 59 44 60 39 48 47 44
[13:20:25.540] <TB2> INFO: PH offset (per ROC): 97 118 101 129 105 144 105 123 119 125 99 129 110 113 111 97
[13:20:25.544] <TB2> INFO: Decoding statistics:
[13:20:25.544] <TB2> INFO: General information:
[13:20:25.544] <TB2> INFO: 16bit words read: 127886
[13:20:25.544] <TB2> INFO: valid events total: 20480
[13:20:25.544] <TB2> INFO: empty events: 17977
[13:20:25.544] <TB2> INFO: valid events with pixels: 2503
[13:20:25.544] <TB2> INFO: valid pixel hits: 2503
[13:20:25.544] <TB2> INFO: Event errors: 0
[13:20:25.544] <TB2> INFO: start marker: 0
[13:20:25.544] <TB2> INFO: stop marker: 0
[13:20:25.544] <TB2> INFO: overflow: 0
[13:20:25.544] <TB2> INFO: invalid 5bit words: 0
[13:20:25.544] <TB2> INFO: invalid XOR eye diagram: 0
[13:20:25.544] <TB2> INFO: frame (failed synchr.): 0
[13:20:25.544] <TB2> INFO: idle data (no TBM trl): 0
[13:20:25.544] <TB2> INFO: no data (only TBM hdr): 0
[13:20:25.544] <TB2> INFO: TBM errors: 0
[13:20:25.544] <TB2> INFO: flawed TBM headers: 0
[13:20:25.544] <TB2> INFO: flawed TBM trailers: 0
[13:20:25.544] <TB2> INFO: event ID mismatches: 0
[13:20:25.544] <TB2> INFO: ROC errors: 0
[13:20:25.544] <TB2> INFO: missing ROC header(s): 0
[13:20:25.544] <TB2> INFO: misplaced readback start: 0
[13:20:25.544] <TB2> INFO: Pixel decoding errors: 0
[13:20:25.544] <TB2> INFO: pixel data incomplete: 0
[13:20:25.544] <TB2> INFO: pixel address: 0
[13:20:25.544] <TB2> INFO: pulse height fill bit: 0
[13:20:25.544] <TB2> INFO: buffer corruption: 0
[13:20:25.810] <TB2> INFO: ######################################################################
[13:20:25.810] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:20:25.810] <TB2> INFO: ######################################################################
[13:20:25.820] <TB2> INFO: scanning low vcal = 10
[13:20:26.051] <TB2> INFO: Expecting 41600 events.
[13:20:29.650] <TB2> INFO: 41600 events read in total (3007ms).
[13:20:29.650] <TB2> INFO: Test took 3830ms.
[13:20:29.651] <TB2> INFO: scanning low vcal = 20
[13:20:29.951] <TB2> INFO: Expecting 41600 events.
[13:20:33.516] <TB2> INFO: 41600 events read in total (2973ms).
[13:20:33.516] <TB2> INFO: Test took 3864ms.
[13:20:33.518] <TB2> INFO: scanning low vcal = 30
[13:20:33.817] <TB2> INFO: Expecting 41600 events.
[13:20:37.503] <TB2> INFO: 41600 events read in total (3095ms).
[13:20:37.504] <TB2> INFO: Test took 3986ms.
[13:20:37.506] <TB2> INFO: scanning low vcal = 40
[13:20:37.798] <TB2> INFO: Expecting 41600 events.
[13:20:41.736] <TB2> INFO: 41600 events read in total (3347ms).
[13:20:41.738] <TB2> INFO: Test took 4232ms.
[13:20:41.741] <TB2> INFO: scanning low vcal = 50
[13:20:42.018] <TB2> INFO: Expecting 41600 events.
[13:20:45.003] <TB2> INFO: 41600 events read in total (3394ms).
[13:20:46.003] <TB2> INFO: Test took 4262ms.
[13:20:46.006] <TB2> INFO: scanning low vcal = 60
[13:20:46.283] <TB2> INFO: Expecting 41600 events.
[13:20:50.294] <TB2> INFO: 41600 events read in total (3419ms).
[13:20:50.295] <TB2> INFO: Test took 4289ms.
[13:20:50.298] <TB2> INFO: scanning low vcal = 70
[13:20:50.574] <TB2> INFO: Expecting 41600 events.
[13:20:54.516] <TB2> INFO: 41600 events read in total (3350ms).
[13:20:54.517] <TB2> INFO: Test took 4219ms.
[13:20:54.519] <TB2> INFO: scanning low vcal = 80
[13:20:54.816] <TB2> INFO: Expecting 41600 events.
[13:20:58.811] <TB2> INFO: 41600 events read in total (3403ms).
[13:20:58.811] <TB2> INFO: Test took 4292ms.
[13:20:58.814] <TB2> INFO: scanning low vcal = 90
[13:20:59.090] <TB2> INFO: Expecting 41600 events.
[13:21:03.039] <TB2> INFO: 41600 events read in total (3357ms).
[13:21:03.040] <TB2> INFO: Test took 4226ms.
[13:21:03.043] <TB2> INFO: scanning low vcal = 100
[13:21:03.320] <TB2> INFO: Expecting 41600 events.
[13:21:07.317] <TB2> INFO: 41600 events read in total (3406ms).
[13:21:07.318] <TB2> INFO: Test took 4275ms.
[13:21:07.321] <TB2> INFO: scanning low vcal = 110
[13:21:07.612] <TB2> INFO: Expecting 41600 events.
[13:21:11.622] <TB2> INFO: 41600 events read in total (3418ms).
[13:21:11.623] <TB2> INFO: Test took 4302ms.
[13:21:11.626] <TB2> INFO: scanning low vcal = 120
[13:21:11.902] <TB2> INFO: Expecting 41600 events.
[13:21:15.891] <TB2> INFO: 41600 events read in total (3397ms).
[13:21:15.891] <TB2> INFO: Test took 4265ms.
[13:21:15.894] <TB2> INFO: scanning low vcal = 130
[13:21:16.171] <TB2> INFO: Expecting 41600 events.
[13:21:20.183] <TB2> INFO: 41600 events read in total (3420ms).
[13:21:20.184] <TB2> INFO: Test took 4290ms.
[13:21:20.187] <TB2> INFO: scanning low vcal = 140
[13:21:20.463] <TB2> INFO: Expecting 41600 events.
[13:21:24.449] <TB2> INFO: 41600 events read in total (3394ms).
[13:21:24.450] <TB2> INFO: Test took 4263ms.
[13:21:24.452] <TB2> INFO: scanning low vcal = 150
[13:21:24.729] <TB2> INFO: Expecting 41600 events.
[13:21:28.795] <TB2> INFO: 41600 events read in total (3474ms).
[13:21:28.796] <TB2> INFO: Test took 4343ms.
[13:21:28.798] <TB2> INFO: scanning low vcal = 160
[13:21:29.075] <TB2> INFO: Expecting 41600 events.
[13:21:33.074] <TB2> INFO: 41600 events read in total (3407ms).
[13:21:33.074] <TB2> INFO: Test took 4275ms.
[13:21:33.077] <TB2> INFO: scanning low vcal = 170
[13:21:33.353] <TB2> INFO: Expecting 41600 events.
[13:21:37.304] <TB2> INFO: 41600 events read in total (3359ms).
[13:21:37.305] <TB2> INFO: Test took 4228ms.
[13:21:37.307] <TB2> INFO: scanning low vcal = 180
[13:21:37.584] <TB2> INFO: Expecting 41600 events.
[13:21:41.629] <TB2> INFO: 41600 events read in total (3454ms).
[13:21:41.630] <TB2> INFO: Test took 4323ms.
[13:21:41.633] <TB2> INFO: scanning low vcal = 190
[13:21:41.925] <TB2> INFO: Expecting 41600 events.
[13:21:45.912] <TB2> INFO: 41600 events read in total (3395ms).
[13:21:45.913] <TB2> INFO: Test took 4280ms.
[13:21:45.915] <TB2> INFO: scanning low vcal = 200
[13:21:46.192] <TB2> INFO: Expecting 41600 events.
[13:21:50.163] <TB2> INFO: 41600 events read in total (3379ms).
[13:21:50.164] <TB2> INFO: Test took 4249ms.
[13:21:50.166] <TB2> INFO: scanning low vcal = 210
[13:21:50.459] <TB2> INFO: Expecting 41600 events.
[13:21:54.465] <TB2> INFO: 41600 events read in total (3414ms).
[13:21:54.465] <TB2> INFO: Test took 4299ms.
[13:21:54.468] <TB2> INFO: scanning low vcal = 220
[13:21:54.761] <TB2> INFO: Expecting 41600 events.
[13:21:58.718] <TB2> INFO: 41600 events read in total (3365ms).
[13:21:58.719] <TB2> INFO: Test took 4251ms.
[13:21:58.721] <TB2> INFO: scanning low vcal = 230
[13:21:58.998] <TB2> INFO: Expecting 41600 events.
[13:22:02.951] <TB2> INFO: 41600 events read in total (3361ms).
[13:22:02.952] <TB2> INFO: Test took 4230ms.
[13:22:02.955] <TB2> INFO: scanning low vcal = 240
[13:22:03.231] <TB2> INFO: Expecting 41600 events.
[13:22:07.250] <TB2> INFO: 41600 events read in total (3427ms).
[13:22:07.251] <TB2> INFO: Test took 4296ms.
[13:22:07.253] <TB2> INFO: scanning low vcal = 250
[13:22:07.530] <TB2> INFO: Expecting 41600 events.
[13:22:11.512] <TB2> INFO: 41600 events read in total (3390ms).
[13:22:11.513] <TB2> INFO: Test took 4260ms.
[13:22:11.517] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[13:22:11.792] <TB2> INFO: Expecting 41600 events.
[13:22:15.783] <TB2> INFO: 41600 events read in total (3399ms).
[13:22:15.783] <TB2> INFO: Test took 4266ms.
[13:22:15.786] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[13:22:16.063] <TB2> INFO: Expecting 41600 events.
[13:22:20.058] <TB2> INFO: 41600 events read in total (3404ms).
[13:22:20.059] <TB2> INFO: Test took 4273ms.
[13:22:20.062] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[13:22:20.338] <TB2> INFO: Expecting 41600 events.
[13:22:24.360] <TB2> INFO: 41600 events read in total (3430ms).
[13:22:24.361] <TB2> INFO: Test took 4299ms.
[13:22:24.364] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[13:22:24.656] <TB2> INFO: Expecting 41600 events.
[13:22:28.694] <TB2> INFO: 41600 events read in total (3446ms).
[13:22:28.695] <TB2> INFO: Test took 4331ms.
[13:22:28.698] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:22:29.008] <TB2> INFO: Expecting 41600 events.
[13:22:33.090] <TB2> INFO: 41600 events read in total (3490ms).
[13:22:33.090] <TB2> INFO: Test took 4392ms.
[13:22:33.496] <TB2> INFO: PixTestGainPedestal::measure() done
[13:23:06.721] <TB2> INFO: PixTestGainPedestal::fit() done
[13:23:06.721] <TB2> INFO: non-linearity mean: 0.950 0.984 0.939 0.979 0.966 0.981 0.941 0.980 0.984 0.981 0.923 0.981 0.973 0.948 0.935 0.969
[13:23:06.721] <TB2> INFO: non-linearity RMS: 0.053 0.003 0.134 0.003 0.178 0.004 0.051 0.003 0.003 0.003 0.160 0.004 0.179 0.060 0.058 0.166
[13:23:06.721] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[13:23:06.735] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[13:23:06.748] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[13:23:06.762] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[13:23:06.775] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[13:23:06.789] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[13:23:06.802] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[13:23:06.816] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[13:23:06.829] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[13:23:06.842] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[13:23:06.856] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[13:23:06.869] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[13:23:06.883] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[13:23:06.896] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[13:23:06.910] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[13:23:06.923] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[13:23:06.937] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 161 seconds
[13:23:06.937] <TB2> INFO: Decoding statistics:
[13:23:06.937] <TB2> INFO: General information:
[13:23:06.937] <TB2> INFO: 16bit words read: 3327694
[13:23:06.937] <TB2> INFO: valid events total: 332800
[13:23:06.937] <TB2> INFO: empty events: 0
[13:23:06.937] <TB2> INFO: valid events with pixels: 332800
[13:23:06.937] <TB2> INFO: valid pixel hits: 665447
[13:23:06.937] <TB2> INFO: Event errors: 0
[13:23:06.937] <TB2> INFO: start marker: 0
[13:23:06.937] <TB2> INFO: stop marker: 0
[13:23:06.937] <TB2> INFO: overflow: 0
[13:23:06.937] <TB2> INFO: invalid 5bit words: 0
[13:23:06.937] <TB2> INFO: invalid XOR eye diagram: 0
[13:23:06.937] <TB2> INFO: frame (failed synchr.): 0
[13:23:06.937] <TB2> INFO: idle data (no TBM trl): 0
[13:23:06.937] <TB2> INFO: no data (only TBM hdr): 0
[13:23:06.937] <TB2> INFO: TBM errors: 0
[13:23:06.937] <TB2> INFO: flawed TBM headers: 0
[13:23:06.937] <TB2> INFO: flawed TBM trailers: 0
[13:23:06.937] <TB2> INFO: event ID mismatches: 0
[13:23:06.937] <TB2> INFO: ROC errors: 0
[13:23:06.937] <TB2> INFO: missing ROC header(s): 0
[13:23:06.937] <TB2> INFO: misplaced readback start: 0
[13:23:06.937] <TB2> INFO: Pixel decoding errors: 0
[13:23:06.937] <TB2> INFO: pixel data incomplete: 0
[13:23:06.937] <TB2> INFO: pixel address: 0
[13:23:06.937] <TB2> INFO: pulse height fill bit: 0
[13:23:06.937] <TB2> INFO: buffer corruption: 0
[13:23:06.952] <TB2> INFO: Decoding statistics:
[13:23:06.952] <TB2> INFO: General information:
[13:23:06.952] <TB2> INFO: 16bit words read: 3457116
[13:23:06.952] <TB2> INFO: valid events total: 353536
[13:23:06.952] <TB2> INFO: empty events: 18233
[13:23:06.952] <TB2> INFO: valid events with pixels: 335303
[13:23:06.952] <TB2> INFO: valid pixel hits: 667950
[13:23:06.952] <TB2> INFO: Event errors: 0
[13:23:06.952] <TB2> INFO: start marker: 0
[13:23:06.952] <TB2> INFO: stop marker: 0
[13:23:06.952] <TB2> INFO: overflow: 0
[13:23:06.952] <TB2> INFO: invalid 5bit words: 0
[13:23:06.952] <TB2> INFO: invalid XOR eye diagram: 0
[13:23:06.952] <TB2> INFO: frame (failed synchr.): 0
[13:23:06.952] <TB2> INFO: idle data (no TBM trl): 0
[13:23:06.952] <TB2> INFO: no data (only TBM hdr): 0
[13:23:06.952] <TB2> INFO: TBM errors: 0
[13:23:06.952] <TB2> INFO: flawed TBM headers: 0
[13:23:06.952] <TB2> INFO: flawed TBM trailers: 0
[13:23:06.952] <TB2> INFO: event ID mismatches: 0
[13:23:06.952] <TB2> INFO: ROC errors: 0
[13:23:06.952] <TB2> INFO: missing ROC header(s): 0
[13:23:06.952] <TB2> INFO: misplaced readback start: 0
[13:23:06.952] <TB2> INFO: Pixel decoding errors: 0
[13:23:06.952] <TB2> INFO: pixel data incomplete: 0
[13:23:06.952] <TB2> INFO: pixel address: 0
[13:23:06.952] <TB2> INFO: pulse height fill bit: 0
[13:23:06.952] <TB2> INFO: buffer corruption: 0
[13:23:06.952] <TB2> INFO: enter test to run
[13:23:06.952] <TB2> INFO: test: exit no parameter change
[13:23:06.991] <TB2> QUIET: Connection to board 156 closed.
[13:23:06.992] <TB2> INFO: pXar: this is the end, my friend