[13:41:47.006] <TB2> INFO: *** Welcome to pxar ***
[13:41:47.006] <TB2> INFO: *** Today: 2016/10/26
[13:41:47.012] <TB2> INFO: *** Version: c8ba-dirty
[13:41:47.012] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C15.dat
[13:41:47.013] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[13:41:47.013] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//defaultMaskFile.dat
[13:41:47.013] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters_C15.dat
[13:41:47.103] <TB2> INFO: clk: 4
[13:41:47.103] <TB2> INFO: ctr: 4
[13:41:47.103] <TB2> INFO: sda: 19
[13:41:47.103] <TB2> INFO: tin: 9
[13:41:47.103] <TB2> INFO: level: 15
[13:41:47.103] <TB2> INFO: triggerdelay: 0
[13:41:47.103] <TB2> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[13:41:47.103] <TB2> INFO: Log level: INFO
[13:41:47.114] <TB2> INFO: Found DTB DTB_WXC55Z
[13:41:47.125] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[13:41:47.127] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[13:41:47.129] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[13:41:48.616] <TB2> INFO: DUT info:
[13:41:48.617] <TB2> INFO: The DUT currently contains the following objects:
[13:41:48.617] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[13:41:48.617] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:41:48.617] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:41:48.617] <TB2> INFO: TBM Core alpha (2): 7 registers set
[13:41:48.617] <TB2> INFO: TBM Core beta (3): 7 registers set
[13:41:48.617] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[13:41:48.617] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:48.617] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:48.617] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:48.617] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:48.617] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:48.617] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:48.617] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:48.617] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:48.617] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:48.617] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:48.617] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:48.617] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:48.617] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:48.617] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:48.617] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:48.617] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:49.018] <TB2> INFO: enter 'restricted' command line mode
[13:41:49.018] <TB2> INFO: enter test to run
[13:41:49.018] <TB2> INFO: test: pretest no parameter change
[13:41:49.018] <TB2> INFO: running: pretest
[13:41:49.905] <TB2> INFO: ######################################################################
[13:41:49.905] <TB2> INFO: PixTestPretest::doTest()
[13:41:49.905] <TB2> INFO: ######################################################################
[13:41:49.906] <TB2> INFO: ----------------------------------------------------------------------
[13:41:49.906] <TB2> INFO: PixTestPretest::programROC()
[13:41:49.906] <TB2> INFO: ----------------------------------------------------------------------
[13:42:07.919] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[13:42:07.919] <TB2> INFO: IA differences per ROC: 19.3 18.5 17.7 19.3 17.7 20.9 19.3 17.7 19.3 21.7 19.3 17.7 17.7 20.9 20.9 20.9
[13:42:07.956] <TB2> INFO: ----------------------------------------------------------------------
[13:42:07.956] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[13:42:07.956] <TB2> INFO: ----------------------------------------------------------------------
[13:42:15.039] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 385.9 mA = 24.1188 mA/ROC
[13:42:15.039] <TB2> INFO: i(loss) [mA/ROC]: 19.3 19.3 19.3 18.5 18.5 19.3 18.5 19.3 18.5 18.5 18.5 18.5 18.5 18.5 18.5 19.3
[13:42:15.069] <TB2> INFO: ----------------------------------------------------------------------
[13:42:15.070] <TB2> INFO: PixTestPretest::findTiming()
[13:42:15.070] <TB2> INFO: ----------------------------------------------------------------------
[13:42:15.070] <TB2> INFO: PixTestCmd::init()

[13:42:46.251] <TB2> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[13:42:46.251] <TB2> INFO: (success/tries = 100/100), width = 3
[13:42:47.753] <TB2> INFO: ----------------------------------------------------------------------
[13:42:47.753] <TB2> INFO: PixTestPretest::findWorkingPixel()
[13:42:47.753] <TB2> INFO: ----------------------------------------------------------------------
[13:42:47.845] <TB2> INFO: Expecting 231680 events.
[13:42:57.529] <TB2> INFO: 231680 events read in total (9093ms).
[13:42:57.535] <TB2> INFO: Test took 9779ms.
[13:42:57.783] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[13:42:57.811] <TB2> INFO: ----------------------------------------------------------------------
[13:42:57.812] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[13:42:57.812] <TB2> INFO: ----------------------------------------------------------------------
[13:42:57.904] <TB2> INFO: Expecting 231680 events.
[13:43:07.552] <TB2> INFO: 231680 events read in total (9057ms).
[13:43:07.561] <TB2> INFO: Test took 9746ms.
[13:43:07.818] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[13:43:07.818] <TB2> INFO: CalDel: 76 87 87 90 88 94 78 80 81 96 90 91 98 88 82 85
[13:43:07.818] <TB2> INFO: VthrComp: 51 55 51 55 51 52 54 52 57 51 53 51 52 53 51 54
[13:43:07.821] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C0.dat
[13:43:07.821] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C1.dat
[13:43:07.821] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C2.dat
[13:43:07.821] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C3.dat
[13:43:07.821] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C4.dat
[13:43:07.821] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C5.dat
[13:43:07.821] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C6.dat
[13:43:07.821] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C7.dat
[13:43:07.822] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C8.dat
[13:43:07.822] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C9.dat
[13:43:07.822] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C10.dat
[13:43:07.822] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C11.dat
[13:43:07.822] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C12.dat
[13:43:07.822] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C13.dat
[13:43:07.822] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C14.dat
[13:43:07.822] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C15.dat
[13:43:07.822] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[13:43:07.822] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[13:43:07.822] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[13:43:07.823] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[13:43:07.823] <TB2> INFO: PixTestPretest::doTest() done, duration: 78 seconds
[13:43:07.953] <TB2> INFO: enter test to run
[13:43:07.953] <TB2> INFO: test: fulltest no parameter change
[13:43:07.953] <TB2> INFO: running: fulltest
[13:43:07.953] <TB2> INFO: ######################################################################
[13:43:07.953] <TB2> INFO: PixTestFullTest::doTest()
[13:43:07.953] <TB2> INFO: ######################################################################
[13:43:07.954] <TB2> INFO: ######################################################################
[13:43:07.954] <TB2> INFO: PixTestAlive::doTest()
[13:43:07.954] <TB2> INFO: ######################################################################
[13:43:07.955] <TB2> INFO: ----------------------------------------------------------------------
[13:43:07.955] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:43:07.955] <TB2> INFO: ----------------------------------------------------------------------
[13:43:08.189] <TB2> INFO: Expecting 41600 events.
[13:43:11.613] <TB2> INFO: 41600 events read in total (2832ms).
[13:43:11.614] <TB2> INFO: Test took 3657ms.
[13:43:11.841] <TB2> INFO: PixTestAlive::aliveTest() done
[13:43:11.841] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:43:11.842] <TB2> INFO: ----------------------------------------------------------------------
[13:43:11.842] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:43:11.842] <TB2> INFO: ----------------------------------------------------------------------
[13:43:12.078] <TB2> INFO: Expecting 41600 events.
[13:43:15.037] <TB2> INFO: 41600 events read in total (2367ms).
[13:43:15.037] <TB2> INFO: Test took 3193ms.
[13:43:15.038] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[13:43:15.276] <TB2> INFO: PixTestAlive::maskTest() done
[13:43:15.276] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:43:15.278] <TB2> INFO: ----------------------------------------------------------------------
[13:43:15.278] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:43:15.278] <TB2> INFO: ----------------------------------------------------------------------
[13:43:15.510] <TB2> INFO: Expecting 41600 events.
[13:43:19.100] <TB2> INFO: 41600 events read in total (2998ms).
[13:43:19.101] <TB2> INFO: Test took 3822ms.
[13:43:19.329] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[13:43:19.329] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:43:19.329] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[13:43:19.329] <TB2> INFO: Decoding statistics:
[13:43:19.329] <TB2> INFO: General information:
[13:43:19.329] <TB2> INFO: 16bit words read: 0
[13:43:19.329] <TB2> INFO: valid events total: 0
[13:43:19.329] <TB2> INFO: empty events: 0
[13:43:19.329] <TB2> INFO: valid events with pixels: 0
[13:43:19.329] <TB2> INFO: valid pixel hits: 0
[13:43:19.329] <TB2> INFO: Event errors: 0
[13:43:19.329] <TB2> INFO: start marker: 0
[13:43:19.329] <TB2> INFO: stop marker: 0
[13:43:19.329] <TB2> INFO: overflow: 0
[13:43:19.329] <TB2> INFO: invalid 5bit words: 0
[13:43:19.329] <TB2> INFO: invalid XOR eye diagram: 0
[13:43:19.329] <TB2> INFO: frame (failed synchr.): 0
[13:43:19.329] <TB2> INFO: idle data (no TBM trl): 0
[13:43:19.329] <TB2> INFO: no data (only TBM hdr): 0
[13:43:19.329] <TB2> INFO: TBM errors: 0
[13:43:19.329] <TB2> INFO: flawed TBM headers: 0
[13:43:19.329] <TB2> INFO: flawed TBM trailers: 0
[13:43:19.329] <TB2> INFO: event ID mismatches: 0
[13:43:19.329] <TB2> INFO: ROC errors: 0
[13:43:19.329] <TB2> INFO: missing ROC header(s): 0
[13:43:19.329] <TB2> INFO: misplaced readback start: 0
[13:43:19.329] <TB2> INFO: Pixel decoding errors: 0
[13:43:19.329] <TB2> INFO: pixel data incomplete: 0
[13:43:19.329] <TB2> INFO: pixel address: 0
[13:43:19.329] <TB2> INFO: pulse height fill bit: 0
[13:43:19.329] <TB2> INFO: buffer corruption: 0
[13:43:19.336] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:43:19.336] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[13:43:19.336] <TB2> INFO: ######################################################################
[13:43:19.336] <TB2> INFO: PixTestReadback::doTest()
[13:43:19.336] <TB2> INFO: ######################################################################
[13:43:19.336] <TB2> INFO: ----------------------------------------------------------------------
[13:43:19.336] <TB2> INFO: PixTestReadback::CalibrateVd()
[13:43:19.336] <TB2> INFO: ----------------------------------------------------------------------
[13:43:29.311] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C0.dat
[13:43:29.311] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C1.dat
[13:43:29.311] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C2.dat
[13:43:29.311] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C3.dat
[13:43:29.311] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C4.dat
[13:43:29.311] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C5.dat
[13:43:29.312] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C6.dat
[13:43:29.312] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C7.dat
[13:43:29.312] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C8.dat
[13:43:29.312] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C9.dat
[13:43:29.312] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C10.dat
[13:43:29.312] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C11.dat
[13:43:29.312] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C12.dat
[13:43:29.312] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C13.dat
[13:43:29.312] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C14.dat
[13:43:29.312] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:43:29.340] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:43:29.340] <TB2> INFO: ----------------------------------------------------------------------
[13:43:29.340] <TB2> INFO: PixTestReadback::CalibrateVa()
[13:43:29.340] <TB2> INFO: ----------------------------------------------------------------------
[13:43:39.235] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C0.dat
[13:43:39.235] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C1.dat
[13:43:39.235] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C2.dat
[13:43:39.235] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C3.dat
[13:43:39.235] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C4.dat
[13:43:39.235] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C5.dat
[13:43:39.235] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C6.dat
[13:43:39.235] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C7.dat
[13:43:39.235] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C8.dat
[13:43:39.235] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C9.dat
[13:43:39.235] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C10.dat
[13:43:39.235] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C11.dat
[13:43:39.235] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C12.dat
[13:43:39.235] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C13.dat
[13:43:39.235] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C14.dat
[13:43:39.235] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:43:39.265] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:43:39.265] <TB2> INFO: ----------------------------------------------------------------------
[13:43:39.265] <TB2> INFO: PixTestReadback::readbackVbg()
[13:43:39.265] <TB2> INFO: ----------------------------------------------------------------------
[13:43:46.904] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:43:46.904] <TB2> INFO: ----------------------------------------------------------------------
[13:43:46.904] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[13:43:46.904] <TB2> INFO: ----------------------------------------------------------------------
[13:43:46.904] <TB2> INFO: Vbg will be calibrated using Vd calibration
[13:43:46.904] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 157.2calibrated Vbg = 1.17133 :::*/*/*/*/
[13:43:46.904] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 164.2calibrated Vbg = 1.17785 :::*/*/*/*/
[13:43:46.905] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 153.6calibrated Vbg = 1.1705 :::*/*/*/*/
[13:43:46.905] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 156.8calibrated Vbg = 1.17639 :::*/*/*/*/
[13:43:46.905] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 156.5calibrated Vbg = 1.17249 :::*/*/*/*/
[13:43:46.905] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 151calibrated Vbg = 1.17621 :::*/*/*/*/
[13:43:46.905] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 151.5calibrated Vbg = 1.17573 :::*/*/*/*/
[13:43:46.905] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 160calibrated Vbg = 1.17163 :::*/*/*/*/
[13:43:46.905] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 161.5calibrated Vbg = 1.17174 :::*/*/*/*/
[13:43:46.905] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 154calibrated Vbg = 1.15948 :::*/*/*/*/
[13:43:46.905] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 157.2calibrated Vbg = 1.16309 :::*/*/*/*/
[13:43:46.905] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 157calibrated Vbg = 1.1578 :::*/*/*/*/
[13:43:46.905] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 165.5calibrated Vbg = 1.16548 :::*/*/*/*/
[13:43:46.905] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 155.6calibrated Vbg = 1.17093 :::*/*/*/*/
[13:43:46.905] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 155calibrated Vbg = 1.17906 :::*/*/*/*/
[13:43:46.905] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 149.5calibrated Vbg = 1.1684 :::*/*/*/*/
[13:43:46.907] <TB2> INFO: ----------------------------------------------------------------------
[13:43:46.907] <TB2> INFO: PixTestReadback::CalibrateIa()
[13:43:46.907] <TB2> INFO: ----------------------------------------------------------------------
[13:46:27.218] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C0.dat
[13:46:27.218] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C1.dat
[13:46:27.218] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C2.dat
[13:46:27.219] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C3.dat
[13:46:27.219] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C4.dat
[13:46:27.219] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C5.dat
[13:46:27.219] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C6.dat
[13:46:27.219] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C7.dat
[13:46:27.219] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C8.dat
[13:46:27.219] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C9.dat
[13:46:27.219] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C10.dat
[13:46:27.219] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C11.dat
[13:46:27.219] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C12.dat
[13:46:27.219] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C13.dat
[13:46:27.219] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C14.dat
[13:46:27.219] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:46:27.248] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:46:27.250] <TB2> INFO: PixTestReadback::doTest() done
[13:46:27.250] <TB2> INFO: Decoding statistics:
[13:46:27.250] <TB2> INFO: General information:
[13:46:27.250] <TB2> INFO: 16bit words read: 1536
[13:46:27.250] <TB2> INFO: valid events total: 256
[13:46:27.250] <TB2> INFO: empty events: 256
[13:46:27.250] <TB2> INFO: valid events with pixels: 0
[13:46:27.250] <TB2> INFO: valid pixel hits: 0
[13:46:27.250] <TB2> INFO: Event errors: 0
[13:46:27.250] <TB2> INFO: start marker: 0
[13:46:27.250] <TB2> INFO: stop marker: 0
[13:46:27.250] <TB2> INFO: overflow: 0
[13:46:27.250] <TB2> INFO: invalid 5bit words: 0
[13:46:27.250] <TB2> INFO: invalid XOR eye diagram: 0
[13:46:27.250] <TB2> INFO: frame (failed synchr.): 0
[13:46:27.250] <TB2> INFO: idle data (no TBM trl): 0
[13:46:27.250] <TB2> INFO: no data (only TBM hdr): 0
[13:46:27.250] <TB2> INFO: TBM errors: 0
[13:46:27.250] <TB2> INFO: flawed TBM headers: 0
[13:46:27.250] <TB2> INFO: flawed TBM trailers: 0
[13:46:27.250] <TB2> INFO: event ID mismatches: 0
[13:46:27.250] <TB2> INFO: ROC errors: 0
[13:46:27.250] <TB2> INFO: missing ROC header(s): 0
[13:46:27.250] <TB2> INFO: misplaced readback start: 0
[13:46:27.250] <TB2> INFO: Pixel decoding errors: 0
[13:46:27.251] <TB2> INFO: pixel data incomplete: 0
[13:46:27.251] <TB2> INFO: pixel address: 0
[13:46:27.251] <TB2> INFO: pulse height fill bit: 0
[13:46:27.251] <TB2> INFO: buffer corruption: 0
[13:46:27.292] <TB2> INFO: ######################################################################
[13:46:27.293] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[13:46:27.293] <TB2> INFO: ######################################################################
[13:46:27.295] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[13:46:27.306] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:46:27.306] <TB2> INFO: run 1 of 1
[13:46:27.538] <TB2> INFO: Expecting 3120000 events.
[13:46:58.100] <TB2> INFO: 668055 events read in total (29970ms).
[13:47:27.643] <TB2> INFO: 1335700 events read in total (59513ms).











[13:47:57.346] <TB2> INFO: 2000275 events read in total (89216ms).











[13:48:27.106] <TB2> INFO: 2664840 events read in total (118976ms).











[13:48:47.407] <TB2> INFO: 3120000 events read in total (139277ms).
[13:48:47.461] <TB2> INFO: Test took 140155ms.
[13:49:15.188] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 167 seconds
[13:49:15.188] <TB2> INFO: number of dead bumps (per ROC): 1 0 1 2 1 0 0 0 0 2 1 2 2 2 0 0
[13:49:15.188] <TB2> INFO: separation cut (per ROC): 105 106 105 105 92 108 111 109 116 108 120 110 102 106 109 112
[13:49:15.188] <TB2> INFO: Decoding statistics:
[13:49:15.188] <TB2> INFO: General information:
[13:49:15.188] <TB2> INFO: 16bit words read: 0
[13:49:15.188] <TB2> INFO: valid events total: 0
[13:49:15.188] <TB2> INFO: empty events: 0
[13:49:15.188] <TB2> INFO: valid events with pixels: 0
[13:49:15.188] <TB2> INFO: valid pixel hits: 0
[13:49:15.188] <TB2> INFO: Event errors: 0
[13:49:15.188] <TB2> INFO: start marker: 0
[13:49:15.188] <TB2> INFO: stop marker: 0
[13:49:15.188] <TB2> INFO: overflow: 0
[13:49:15.188] <TB2> INFO: invalid 5bit words: 0
[13:49:15.188] <TB2> INFO: invalid XOR eye diagram: 0
[13:49:15.188] <TB2> INFO: frame (failed synchr.): 0
[13:49:15.188] <TB2> INFO: idle data (no TBM trl): 0
[13:49:15.188] <TB2> INFO: no data (only TBM hdr): 0
[13:49:15.188] <TB2> INFO: TBM errors: 0
[13:49:15.188] <TB2> INFO: flawed TBM headers: 0
[13:49:15.188] <TB2> INFO: flawed TBM trailers: 0
[13:49:15.188] <TB2> INFO: event ID mismatches: 0
[13:49:15.188] <TB2> INFO: ROC errors: 0
[13:49:15.188] <TB2> INFO: missing ROC header(s): 0
[13:49:15.188] <TB2> INFO: misplaced readback start: 0
[13:49:15.188] <TB2> INFO: Pixel decoding errors: 0
[13:49:15.188] <TB2> INFO: pixel data incomplete: 0
[13:49:15.188] <TB2> INFO: pixel address: 0
[13:49:15.188] <TB2> INFO: pulse height fill bit: 0
[13:49:15.188] <TB2> INFO: buffer corruption: 0
[13:49:15.237] <TB2> INFO: ######################################################################
[13:49:15.237] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:49:15.237] <TB2> INFO: ######################################################################
[13:49:15.238] <TB2> INFO: ----------------------------------------------------------------------
[13:49:15.238] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:49:15.238] <TB2> INFO: ----------------------------------------------------------------------
[13:49:15.238] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[13:49:15.250] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[13:49:15.250] <TB2> INFO: run 1 of 1
[13:49:15.486] <TB2> INFO: Expecting 36608000 events.
[13:49:38.802] <TB2> INFO: 695000 events read in total (22724ms).
[13:50:01.338] <TB2> INFO: 1377150 events read in total (45260ms).
[13:50:23.755] <TB2> INFO: 2056700 events read in total (67677ms).
[13:50:46.340] <TB2> INFO: 2734700 events read in total (90262ms).
[13:51:08.747] <TB2> INFO: 3412400 events read in total (112669ms).
[13:51:30.884] <TB2> INFO: 4090000 events read in total (134806ms).
[13:51:53.272] <TB2> INFO: 4767150 events read in total (157194ms).
[13:52:15.745] <TB2> INFO: 5443400 events read in total (179667ms).
[13:52:38.165] <TB2> INFO: 6121850 events read in total (202087ms).
[13:53:00.610] <TB2> INFO: 6801200 events read in total (224532ms).
[13:53:23.074] <TB2> INFO: 7478850 events read in total (246996ms).
[13:53:45.584] <TB2> INFO: 8155500 events read in total (269506ms).
[13:54:07.787] <TB2> INFO: 8832400 events read in total (291709ms).
[13:54:30.268] <TB2> INFO: 9510800 events read in total (314190ms).
[13:54:52.554] <TB2> INFO: 10188150 events read in total (336476ms).
[13:55:14.931] <TB2> INFO: 10863950 events read in total (358853ms).
[13:55:37.260] <TB2> INFO: 11540200 events read in total (381183ms).
[13:55:59.719] <TB2> INFO: 12214000 events read in total (403641ms).
[13:56:22.046] <TB2> INFO: 12889100 events read in total (425968ms).
[13:56:44.412] <TB2> INFO: 13561200 events read in total (448334ms).
[13:57:06.693] <TB2> INFO: 14235700 events read in total (470615ms).
[13:57:29.148] <TB2> INFO: 14908200 events read in total (493070ms).
[13:57:51.572] <TB2> INFO: 15582750 events read in total (515494ms).
[13:58:13.703] <TB2> INFO: 16257150 events read in total (537625ms).
[13:58:36.084] <TB2> INFO: 16930950 events read in total (560006ms).
[13:58:58.436] <TB2> INFO: 17604550 events read in total (582358ms).
[13:59:20.941] <TB2> INFO: 18275350 events read in total (604863ms).
[13:59:43.325] <TB2> INFO: 18944950 events read in total (627247ms).
[14:00:05.690] <TB2> INFO: 19613750 events read in total (649612ms).
[14:00:28.188] <TB2> INFO: 20283000 events read in total (672110ms).
[14:00:50.619] <TB2> INFO: 20951600 events read in total (694541ms).
[14:01:13.341] <TB2> INFO: 21620300 events read in total (717263ms).
[14:01:35.673] <TB2> INFO: 22289900 events read in total (739595ms).
[14:01:57.830] <TB2> INFO: 22959450 events read in total (761752ms).
[14:02:20.092] <TB2> INFO: 23629400 events read in total (784014ms).
[14:02:42.694] <TB2> INFO: 24300150 events read in total (806616ms).
[14:03:05.156] <TB2> INFO: 24971100 events read in total (829078ms).
[14:03:27.561] <TB2> INFO: 25641000 events read in total (851483ms).
[14:03:49.670] <TB2> INFO: 26310750 events read in total (873592ms).
[14:04:12.306] <TB2> INFO: 26980650 events read in total (896228ms).
[14:04:34.634] <TB2> INFO: 27650300 events read in total (918556ms).
[14:04:57.262] <TB2> INFO: 28319850 events read in total (941185ms).
[14:05:19.801] <TB2> INFO: 28988200 events read in total (963723ms).
[14:05:42.185] <TB2> INFO: 29656550 events read in total (986107ms).
[14:06:04.288] <TB2> INFO: 30324050 events read in total (1008210ms).
[14:06:26.595] <TB2> INFO: 30993350 events read in total (1030517ms).
[14:06:49.193] <TB2> INFO: 31663150 events read in total (1053115ms).
[14:07:11.533] <TB2> INFO: 32332350 events read in total (1075455ms).
[14:07:33.684] <TB2> INFO: 33003600 events read in total (1097606ms).
[14:07:56.040] <TB2> INFO: 33675550 events read in total (1119962ms).
[14:08:18.298] <TB2> INFO: 34345800 events read in total (1142220ms).
[14:08:40.729] <TB2> INFO: 35016650 events read in total (1164651ms).
[14:09:02.868] <TB2> INFO: 35687300 events read in total (1186790ms).
[14:09:25.631] <TB2> INFO: 36367450 events read in total (1209554ms).
[14:09:34.039] <TB2> INFO: 36608000 events read in total (1217961ms).
[14:09:34.091] <TB2> INFO: Test took 1218841ms.
[14:09:34.521] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:09:36.483] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:09:38.433] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:09:40.501] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:09:42.416] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:09:44.891] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:09:47.210] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:09:49.322] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:09:51.489] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:09:53.419] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:09:55.283] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:09:57.627] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:09:59.886] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:10:01.858] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:10:03.785] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:10:05.834] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:10:07.718] <TB2> INFO: PixTestScurves::scurves() done
[14:10:07.718] <TB2> INFO: Vcal mean: 119.79 135.72 134.12 125.47 107.73 126.20 129.15 133.79 139.33 122.19 134.61 128.24 127.80 124.32 122.35 128.68
[14:10:07.718] <TB2> INFO: Vcal RMS: 5.78 6.58 7.11 6.91 4.96 6.17 6.75 6.02 6.47 6.27 6.89 6.67 6.35 6.46 6.76 6.47
[14:10:07.718] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1252 seconds
[14:10:07.718] <TB2> INFO: Decoding statistics:
[14:10:07.718] <TB2> INFO: General information:
[14:10:07.718] <TB2> INFO: 16bit words read: 0
[14:10:07.718] <TB2> INFO: valid events total: 0
[14:10:07.718] <TB2> INFO: empty events: 0
[14:10:07.718] <TB2> INFO: valid events with pixels: 0
[14:10:07.718] <TB2> INFO: valid pixel hits: 0
[14:10:07.718] <TB2> INFO: Event errors: 0
[14:10:07.718] <TB2> INFO: start marker: 0
[14:10:07.718] <TB2> INFO: stop marker: 0
[14:10:07.718] <TB2> INFO: overflow: 0
[14:10:07.718] <TB2> INFO: invalid 5bit words: 0
[14:10:07.718] <TB2> INFO: invalid XOR eye diagram: 0
[14:10:07.718] <TB2> INFO: frame (failed synchr.): 0
[14:10:07.718] <TB2> INFO: idle data (no TBM trl): 0
[14:10:07.718] <TB2> INFO: no data (only TBM hdr): 0
[14:10:07.718] <TB2> INFO: TBM errors: 0
[14:10:07.718] <TB2> INFO: flawed TBM headers: 0
[14:10:07.718] <TB2> INFO: flawed TBM trailers: 0
[14:10:07.718] <TB2> INFO: event ID mismatches: 0
[14:10:07.718] <TB2> INFO: ROC errors: 0
[14:10:07.719] <TB2> INFO: missing ROC header(s): 0
[14:10:07.719] <TB2> INFO: misplaced readback start: 0
[14:10:07.719] <TB2> INFO: Pixel decoding errors: 0
[14:10:07.719] <TB2> INFO: pixel data incomplete: 0
[14:10:07.719] <TB2> INFO: pixel address: 0
[14:10:07.719] <TB2> INFO: pulse height fill bit: 0
[14:10:07.719] <TB2> INFO: buffer corruption: 0
[14:10:07.784] <TB2> INFO: ######################################################################
[14:10:07.784] <TB2> INFO: PixTestTrim::doTest()
[14:10:07.784] <TB2> INFO: ######################################################################
[14:10:07.786] <TB2> INFO: ----------------------------------------------------------------------
[14:10:07.786] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[14:10:07.786] <TB2> INFO: ----------------------------------------------------------------------
[14:10:07.827] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:10:07.827] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:10:07.837] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:10:07.837] <TB2> INFO: run 1 of 1
[14:10:08.093] <TB2> INFO: Expecting 5025280 events.
[14:10:38.285] <TB2> INFO: 834200 events read in total (29598ms).
[14:11:07.926] <TB2> INFO: 1666576 events read in total (59239ms).
[14:11:37.935] <TB2> INFO: 2496096 events read in total (89248ms).
[14:12:07.718] <TB2> INFO: 3321784 events read in total (119031ms).
[14:12:37.551] <TB2> INFO: 4144640 events read in total (148864ms).
[14:13:07.334] <TB2> INFO: 4967512 events read in total (178647ms).
[14:13:09.806] <TB2> INFO: 5025280 events read in total (181119ms).
[14:13:09.864] <TB2> INFO: Test took 182028ms.
[14:13:26.431] <TB2> INFO: ROC 0 VthrComp = 127
[14:13:26.431] <TB2> INFO: ROC 1 VthrComp = 130
[14:13:26.431] <TB2> INFO: ROC 2 VthrComp = 122
[14:13:26.431] <TB2> INFO: ROC 3 VthrComp = 126
[14:13:26.431] <TB2> INFO: ROC 4 VthrComp = 108
[14:13:26.432] <TB2> INFO: ROC 5 VthrComp = 132
[14:13:26.432] <TB2> INFO: ROC 6 VthrComp = 132
[14:13:26.433] <TB2> INFO: ROC 7 VthrComp = 133
[14:13:26.433] <TB2> INFO: ROC 8 VthrComp = 135
[14:13:26.433] <TB2> INFO: ROC 9 VthrComp = 126
[14:13:26.433] <TB2> INFO: ROC 10 VthrComp = 132
[14:13:26.433] <TB2> INFO: ROC 11 VthrComp = 122
[14:13:26.434] <TB2> INFO: ROC 12 VthrComp = 122
[14:13:26.434] <TB2> INFO: ROC 13 VthrComp = 128
[14:13:26.434] <TB2> INFO: ROC 14 VthrComp = 122
[14:13:26.434] <TB2> INFO: ROC 15 VthrComp = 130
[14:13:26.742] <TB2> INFO: Expecting 41600 events.
[14:13:30.354] <TB2> INFO: 41600 events read in total (3019ms).
[14:13:30.355] <TB2> INFO: Test took 3919ms.
[14:13:30.364] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:13:30.364] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:13:30.373] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:13:30.373] <TB2> INFO: run 1 of 1
[14:13:30.652] <TB2> INFO: Expecting 5025280 events.
[14:13:56.856] <TB2> INFO: 593352 events read in total (25613ms).
[14:14:22.391] <TB2> INFO: 1185744 events read in total (51148ms).
[14:14:47.738] <TB2> INFO: 1777888 events read in total (76495ms).
[14:15:13.506] <TB2> INFO: 2369224 events read in total (102263ms).
[14:15:38.628] <TB2> INFO: 2957624 events read in total (127385ms).
[14:16:04.102] <TB2> INFO: 3544240 events read in total (152859ms).
[14:16:29.892] <TB2> INFO: 4129424 events read in total (178649ms).
[14:16:54.996] <TB2> INFO: 4714704 events read in total (203753ms).
[14:17:08.960] <TB2> INFO: 5025280 events read in total (217717ms).
[14:17:09.019] <TB2> INFO: Test took 218646ms.
[14:17:36.300] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 59.0939 for pixel 18/3 mean/min/max = 45.3437/31.5791/59.1083
[14:17:36.300] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 66.7143 for pixel 16/79 mean/min/max = 50.3845/33.6991/67.0698
[14:17:36.301] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 65.7627 for pixel 19/2 mean/min/max = 49.0001/32.2182/65.782
[14:17:36.301] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 63.2804 for pixel 12/21 mean/min/max = 47.3141/31.2729/63.3554
[14:17:36.301] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 61.7452 for pixel 0/18 mean/min/max = 48.5193/35.2597/61.7789
[14:17:36.302] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 57.5347 for pixel 0/3 mean/min/max = 45.2242/32.9056/57.5428
[14:17:36.302] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 63.2745 for pixel 18/77 mean/min/max = 48.3681/33.42/63.3162
[14:17:36.302] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 62.6694 for pixel 5/78 mean/min/max = 47.9682/33.1134/62.8229
[14:17:36.302] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 64.481 for pixel 8/77 mean/min/max = 48.5745/32.5185/64.6304
[14:17:36.303] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 58.001 for pixel 11/26 mean/min/max = 45.4774/32.8952/58.0595
[14:17:36.303] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 66.5542 for pixel 10/11 mean/min/max = 51.2582/35.5956/66.9208
[14:17:36.303] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 62.3578 for pixel 0/77 mean/min/max = 47.8641/33.1514/62.5767
[14:17:36.304] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 62.548 for pixel 3/2 mean/min/max = 47.4294/32.2487/62.6101
[14:17:36.304] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 59.6055 for pixel 16/10 mean/min/max = 45.5093/31.4013/59.6172
[14:17:36.304] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 60.1193 for pixel 49/2 mean/min/max = 45.746/31.3666/60.1254
[14:17:36.305] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 62.7986 for pixel 6/5 mean/min/max = 47.2189/31.4776/62.9602
[14:17:36.305] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:17:36.393] <TB2> INFO: Expecting 411648 events.
[14:17:46.353] <TB2> INFO: 411648 events read in total (9368ms).
[14:17:46.363] <TB2> INFO: Expecting 411648 events.
[14:17:55.350] <TB2> INFO: 411648 events read in total (8584ms).
[14:17:55.360] <TB2> INFO: Expecting 411648 events.
[14:18:04.373] <TB2> INFO: 411648 events read in total (8610ms).
[14:18:04.386] <TB2> INFO: Expecting 411648 events.
[14:18:13.409] <TB2> INFO: 411648 events read in total (8620ms).
[14:18:13.428] <TB2> INFO: Expecting 411648 events.
[14:18:22.457] <TB2> INFO: 411648 events read in total (8626ms).
[14:18:22.474] <TB2> INFO: Expecting 411648 events.
[14:18:31.469] <TB2> INFO: 411648 events read in total (8592ms).
[14:18:31.488] <TB2> INFO: Expecting 411648 events.
[14:18:40.570] <TB2> INFO: 411648 events read in total (8679ms).
[14:18:40.599] <TB2> INFO: Expecting 411648 events.
[14:18:49.638] <TB2> INFO: 411648 events read in total (8636ms).
[14:18:49.661] <TB2> INFO: Expecting 411648 events.
[14:18:58.679] <TB2> INFO: 411648 events read in total (8615ms).
[14:18:58.716] <TB2> INFO: Expecting 411648 events.
[14:19:07.689] <TB2> INFO: 411648 events read in total (8570ms).
[14:19:07.718] <TB2> INFO: Expecting 411648 events.
[14:19:16.762] <TB2> INFO: 411648 events read in total (8641ms).
[14:19:16.797] <TB2> INFO: Expecting 411648 events.
[14:19:25.742] <TB2> INFO: 411648 events read in total (8542ms).
[14:19:25.778] <TB2> INFO: Expecting 411648 events.
[14:19:34.853] <TB2> INFO: 411648 events read in total (8672ms).
[14:19:34.893] <TB2> INFO: Expecting 411648 events.
[14:19:43.950] <TB2> INFO: 411648 events read in total (8654ms).
[14:19:43.991] <TB2> INFO: Expecting 411648 events.
[14:19:53.044] <TB2> INFO: 411648 events read in total (8649ms).
[14:19:53.089] <TB2> INFO: Expecting 411648 events.
[14:20:02.166] <TB2> INFO: 411648 events read in total (8674ms).
[14:20:02.229] <TB2> INFO: Test took 145924ms.
[14:20:02.958] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:20:02.967] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:20:02.967] <TB2> INFO: run 1 of 1
[14:20:03.210] <TB2> INFO: Expecting 5025280 events.
[14:20:29.309] <TB2> INFO: 589872 events read in total (25508ms).
[14:20:54.676] <TB2> INFO: 1177280 events read in total (50875ms).
[14:21:20.410] <TB2> INFO: 1764080 events read in total (76610ms).
[14:21:45.954] <TB2> INFO: 2350768 events read in total (102153ms).
[14:22:11.475] <TB2> INFO: 2937400 events read in total (127674ms).
[14:22:36.655] <TB2> INFO: 3524728 events read in total (152854ms).
[14:23:01.846] <TB2> INFO: 4110456 events read in total (178045ms).
[14:23:27.275] <TB2> INFO: 4695584 events read in total (203474ms).
[14:23:42.022] <TB2> INFO: 5025280 events read in total (218221ms).
[14:23:42.144] <TB2> INFO: Test took 219178ms.
[14:24:06.113] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 3.500000 .. 147.395769
[14:24:06.348] <TB2> INFO: Expecting 208000 events.
[14:24:16.012] <TB2> INFO: 208000 events read in total (9073ms).
[14:24:16.013] <TB2> INFO: Test took 9897ms.
[14:24:16.059] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 3 .. 157 (-1/-1) hits flags = 528 (plus default)
[14:24:16.069] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:24:16.069] <TB2> INFO: run 1 of 1
[14:24:16.348] <TB2> INFO: Expecting 5158400 events.
[14:24:42.282] <TB2> INFO: 581200 events read in total (25343ms).
[14:25:07.613] <TB2> INFO: 1162312 events read in total (50675ms).
[14:25:32.819] <TB2> INFO: 1743328 events read in total (75880ms).
[14:25:58.291] <TB2> INFO: 2324664 events read in total (101353ms).
[14:26:23.881] <TB2> INFO: 2906272 events read in total (126942ms).
[14:26:49.315] <TB2> INFO: 3487680 events read in total (152376ms).
[14:27:14.722] <TB2> INFO: 4068744 events read in total (177783ms).
[14:27:39.946] <TB2> INFO: 4649184 events read in total (203007ms).
[14:28:02.472] <TB2> INFO: 5158400 events read in total (225533ms).
[14:28:02.611] <TB2> INFO: Test took 226542ms.
[14:28:30.487] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.266569 .. 45.641813
[14:28:30.722] <TB2> INFO: Expecting 208000 events.
[14:28:40.464] <TB2> INFO: 208000 events read in total (9149ms).
[14:28:40.465] <TB2> INFO: Test took 9977ms.
[14:28:40.517] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:28:40.526] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:28:40.526] <TB2> INFO: run 1 of 1
[14:28:40.804] <TB2> INFO: Expecting 1297920 events.
[14:29:08.545] <TB2> INFO: 661080 events read in total (27150ms).
[14:29:34.991] <TB2> INFO: 1297920 events read in total (53597ms).
[14:29:35.030] <TB2> INFO: Test took 54505ms.
[14:29:48.808] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 26.914365 .. 49.706931
[14:29:49.041] <TB2> INFO: Expecting 208000 events.
[14:29:58.765] <TB2> INFO: 208000 events read in total (9132ms).
[14:29:58.766] <TB2> INFO: Test took 9957ms.
[14:29:58.822] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 59 (-1/-1) hits flags = 528 (plus default)
[14:29:58.831] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:29:58.831] <TB2> INFO: run 1 of 1
[14:29:59.110] <TB2> INFO: Expecting 1464320 events.
[14:30:26.643] <TB2> INFO: 650584 events read in total (26941ms).
[14:30:53.962] <TB2> INFO: 1300256 events read in total (54260ms).
[14:31:01.397] <TB2> INFO: 1464320 events read in total (61696ms).
[14:31:01.433] <TB2> INFO: Test took 62602ms.
[14:31:15.718] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 27.539864 .. 54.120438
[14:31:15.993] <TB2> INFO: Expecting 208000 events.
[14:31:25.632] <TB2> INFO: 208000 events read in total (9047ms).
[14:31:25.633] <TB2> INFO: Test took 9914ms.
[14:31:25.678] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 17 .. 64 (-1/-1) hits flags = 528 (plus default)
[14:31:25.687] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:31:25.687] <TB2> INFO: run 1 of 1
[14:31:25.965] <TB2> INFO: Expecting 1597440 events.
[14:31:53.314] <TB2> INFO: 631776 events read in total (26758ms).
[14:32:20.081] <TB2> INFO: 1263320 events read in total (53525ms).
[14:32:34.386] <TB2> INFO: 1597440 events read in total (67830ms).
[14:32:34.415] <TB2> INFO: Test took 68728ms.
[14:32:48.973] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:32:48.973] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:32:48.985] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:32:48.985] <TB2> INFO: run 1 of 1
[14:32:49.305] <TB2> INFO: Expecting 1364480 events.
[14:33:17.102] <TB2> INFO: 668616 events read in total (27206ms).
[14:33:44.519] <TB2> INFO: 1336672 events read in total (54623ms).
[14:33:46.133] <TB2> INFO: 1364480 events read in total (56237ms).
[14:33:46.157] <TB2> INFO: Test took 57172ms.
[14:33:59.584] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C0.dat
[14:33:59.584] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C1.dat
[14:33:59.584] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C2.dat
[14:33:59.585] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C3.dat
[14:33:59.585] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C4.dat
[14:33:59.585] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C5.dat
[14:33:59.585] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C6.dat
[14:33:59.585] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C7.dat
[14:33:59.585] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C8.dat
[14:33:59.585] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C9.dat
[14:33:59.585] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C10.dat
[14:33:59.585] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C11.dat
[14:33:59.585] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C12.dat
[14:33:59.585] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C13.dat
[14:33:59.585] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C14.dat
[14:33:59.585] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C15.dat
[14:33:59.585] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C0.dat
[14:33:59.591] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C1.dat
[14:33:59.596] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C2.dat
[14:33:59.602] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C3.dat
[14:33:59.607] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C4.dat
[14:33:59.613] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C5.dat
[14:33:59.618] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C6.dat
[14:33:59.624] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C7.dat
[14:33:59.629] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C8.dat
[14:33:59.634] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C9.dat
[14:33:59.640] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C10.dat
[14:33:59.645] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C11.dat
[14:33:59.651] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C12.dat
[14:33:59.656] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C13.dat
[14:33:59.661] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C14.dat
[14:33:59.667] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C15.dat
[14:33:59.675] <TB2> INFO: PixTestTrim::trimTest() done
[14:33:59.675] <TB2> INFO: vtrim: 138 137 151 145 130 122 132 145 147 130 167 120 136 147 126 136
[14:33:59.675] <TB2> INFO: vthrcomp: 127 130 122 126 108 132 132 133 135 126 132 122 122 128 122 130
[14:33:59.675] <TB2> INFO: vcal mean: 35.26 35.62 35.95 35.48 34.97 34.96 35.17 35.24 35.72 34.99 35.99 35.22 34.92 34.98 34.95 35.21
[14:33:59.675] <TB2> INFO: vcal RMS: 1.63 1.76 2.15 1.81 1.04 1.03 1.29 1.35 2.00 1.10 2.29 1.38 1.19 1.13 1.08 1.37
[14:33:59.675] <TB2> INFO: bits mean: 10.21 8.55 9.93 10.43 8.08 9.81 9.25 9.52 9.64 10.00 9.26 9.12 9.23 10.03 9.83 9.72
[14:33:59.675] <TB2> INFO: bits RMS: 2.53 2.84 2.52 2.32 2.68 2.54 2.50 2.48 2.63 2.40 2.29 2.74 2.71 2.57 2.64 2.67
[14:33:59.682] <TB2> INFO: ----------------------------------------------------------------------
[14:33:59.682] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:33:59.682] <TB2> INFO: ----------------------------------------------------------------------
[14:33:59.685] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:33:59.696] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:33:59.696] <TB2> INFO: run 1 of 1
[14:33:59.927] <TB2> INFO: Expecting 4160000 events.
[14:34:31.783] <TB2> INFO: 768550 events read in total (31264ms).
[14:35:03.137] <TB2> INFO: 1530955 events read in total (62618ms).
[14:35:34.084] <TB2> INFO: 2287880 events read in total (93565ms).
[14:36:05.430] <TB2> INFO: 3041855 events read in total (124911ms).
[14:36:36.576] <TB2> INFO: 3795155 events read in total (156057ms).
[14:36:52.074] <TB2> INFO: 4160000 events read in total (171555ms).
[14:36:52.132] <TB2> INFO: Test took 172436ms.
[14:37:18.689] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[14:37:18.698] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:37:18.698] <TB2> INFO: run 1 of 1
[14:37:18.930] <TB2> INFO: Expecting 5324800 events.
[14:37:49.173] <TB2> INFO: 683465 events read in total (29652ms).
[14:38:18.653] <TB2> INFO: 1364245 events read in total (59132ms).
[14:38:47.978] <TB2> INFO: 2042575 events read in total (88457ms).
[14:39:17.284] <TB2> INFO: 2719080 events read in total (117763ms).
[14:39:46.880] <TB2> INFO: 3393085 events read in total (147359ms).
[14:40:16.345] <TB2> INFO: 4067355 events read in total (176824ms).
[14:40:45.907] <TB2> INFO: 4740885 events read in total (206386ms).
[14:41:12.213] <TB2> INFO: 5324800 events read in total (232692ms).
[14:41:12.321] <TB2> INFO: Test took 233623ms.
[14:41:47.577] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 251 (-1/-1) hits flags = 528 (plus default)
[14:41:47.586] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:41:47.586] <TB2> INFO: run 1 of 1
[14:41:47.831] <TB2> INFO: Expecting 5241600 events.
[14:42:18.400] <TB2> INFO: 687035 events read in total (29978ms).
[14:42:48.489] <TB2> INFO: 1370990 events read in total (60067ms).
[14:43:18.274] <TB2> INFO: 2052400 events read in total (89852ms).
[14:43:48.109] <TB2> INFO: 2732280 events read in total (119687ms).
[14:44:17.689] <TB2> INFO: 3409115 events read in total (149267ms).
[14:44:48.216] <TB2> INFO: 4086420 events read in total (179794ms).
[14:45:17.630] <TB2> INFO: 4763510 events read in total (209208ms).
[14:45:38.539] <TB2> INFO: 5241600 events read in total (230117ms).
[14:45:38.613] <TB2> INFO: Test took 231027ms.
[14:46:14.429] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 250 (-1/-1) hits flags = 528 (plus default)
[14:46:14.439] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:46:14.439] <TB2> INFO: run 1 of 1
[14:46:14.678] <TB2> INFO: Expecting 5220800 events.
[14:46:45.132] <TB2> INFO: 688110 events read in total (29862ms).
[14:47:14.726] <TB2> INFO: 1372980 events read in total (59456ms).
[14:47:44.392] <TB2> INFO: 2055365 events read in total (89122ms).
[14:48:14.257] <TB2> INFO: 2735970 events read in total (118987ms).
[14:48:43.511] <TB2> INFO: 3414125 events read in total (148241ms).
[14:49:12.854] <TB2> INFO: 4092110 events read in total (177584ms).
[14:49:42.193] <TB2> INFO: 4769960 events read in total (206923ms).
[14:50:01.923] <TB2> INFO: 5220800 events read in total (226653ms).
[14:50:02.016] <TB2> INFO: Test took 227577ms.
[14:50:35.701] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[14:50:35.710] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:50:35.710] <TB2> INFO: run 1 of 1
[14:50:35.945] <TB2> INFO: Expecting 4430400 events.
[14:51:07.107] <TB2> INFO: 725600 events read in total (30571ms).
[14:51:37.595] <TB2> INFO: 1447390 events read in total (61059ms).
[14:52:08.428] <TB2> INFO: 2164785 events read in total (91892ms).
[14:52:38.727] <TB2> INFO: 2878215 events read in total (122191ms).
[14:53:09.252] <TB2> INFO: 3591815 events read in total (152716ms).
[14:53:39.665] <TB2> INFO: 4305210 events read in total (183129ms).
[14:53:45.325] <TB2> INFO: 4430400 events read in total (188789ms).
[14:53:45.380] <TB2> INFO: Test took 189671ms.
[14:54:11.362] <TB2> INFO: PixTestTrim::trimBitTest() done
[14:54:11.364] <TB2> INFO: PixTestTrim::doTest() done, duration: 2643 seconds
[14:54:11.364] <TB2> INFO: Decoding statistics:
[14:54:11.364] <TB2> INFO: General information:
[14:54:11.364] <TB2> INFO: 16bit words read: 0
[14:54:11.364] <TB2> INFO: valid events total: 0
[14:54:11.364] <TB2> INFO: empty events: 0
[14:54:11.364] <TB2> INFO: valid events with pixels: 0
[14:54:11.364] <TB2> INFO: valid pixel hits: 0
[14:54:11.364] <TB2> INFO: Event errors: 0
[14:54:11.364] <TB2> INFO: start marker: 0
[14:54:11.364] <TB2> INFO: stop marker: 0
[14:54:11.364] <TB2> INFO: overflow: 0
[14:54:11.364] <TB2> INFO: invalid 5bit words: 0
[14:54:11.364] <TB2> INFO: invalid XOR eye diagram: 0
[14:54:11.364] <TB2> INFO: frame (failed synchr.): 0
[14:54:11.364] <TB2> INFO: idle data (no TBM trl): 0
[14:54:11.364] <TB2> INFO: no data (only TBM hdr): 0
[14:54:11.364] <TB2> INFO: TBM errors: 0
[14:54:11.364] <TB2> INFO: flawed TBM headers: 0
[14:54:11.364] <TB2> INFO: flawed TBM trailers: 0
[14:54:11.364] <TB2> INFO: event ID mismatches: 0
[14:54:11.364] <TB2> INFO: ROC errors: 0
[14:54:11.364] <TB2> INFO: missing ROC header(s): 0
[14:54:11.364] <TB2> INFO: misplaced readback start: 0
[14:54:11.364] <TB2> INFO: Pixel decoding errors: 0
[14:54:11.364] <TB2> INFO: pixel data incomplete: 0
[14:54:11.364] <TB2> INFO: pixel address: 0
[14:54:11.364] <TB2> INFO: pulse height fill bit: 0
[14:54:11.364] <TB2> INFO: buffer corruption: 0
[14:54:11.979] <TB2> INFO: ######################################################################
[14:54:11.979] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[14:54:11.979] <TB2> INFO: ######################################################################
[14:54:12.213] <TB2> INFO: Expecting 41600 events.
[14:54:15.676] <TB2> INFO: 41600 events read in total (2871ms).
[14:54:15.677] <TB2> INFO: Test took 3697ms.
[14:54:16.136] <TB2> INFO: Expecting 41600 events.
[14:54:19.650] <TB2> INFO: 41600 events read in total (2922ms).
[14:54:19.651] <TB2> INFO: Test took 3771ms.
[14:54:19.939] <TB2> INFO: Expecting 41600 events.
[14:54:23.460] <TB2> INFO: 41600 events read in total (2929ms).
[14:54:23.461] <TB2> INFO: Test took 3787ms.
[14:54:23.749] <TB2> INFO: Expecting 41600 events.
[14:54:27.214] <TB2> INFO: 41600 events read in total (2874ms).
[14:54:27.215] <TB2> INFO: Test took 3731ms.
[14:54:27.505] <TB2> INFO: Expecting 41600 events.
[14:54:31.025] <TB2> INFO: 41600 events read in total (2928ms).
[14:54:31.027] <TB2> INFO: Test took 3786ms.
[14:54:31.317] <TB2> INFO: Expecting 41600 events.
[14:54:34.771] <TB2> INFO: 41600 events read in total (2862ms).
[14:54:34.772] <TB2> INFO: Test took 3719ms.
[14:54:35.060] <TB2> INFO: Expecting 41600 events.
[14:54:38.546] <TB2> INFO: 41600 events read in total (2895ms).
[14:54:38.547] <TB2> INFO: Test took 3752ms.
[14:54:38.835] <TB2> INFO: Expecting 41600 events.
[14:54:42.268] <TB2> INFO: 41600 events read in total (2841ms).
[14:54:42.269] <TB2> INFO: Test took 3698ms.
[14:54:42.557] <TB2> INFO: Expecting 41600 events.
[14:54:45.988] <TB2> INFO: 41600 events read in total (2840ms).
[14:54:45.989] <TB2> INFO: Test took 3697ms.
[14:54:46.277] <TB2> INFO: Expecting 41600 events.
[14:54:49.801] <TB2> INFO: 41600 events read in total (2933ms).
[14:54:49.802] <TB2> INFO: Test took 3790ms.
[14:54:50.090] <TB2> INFO: Expecting 41600 events.
[14:54:53.637] <TB2> INFO: 41600 events read in total (2955ms).
[14:54:53.638] <TB2> INFO: Test took 3813ms.
[14:54:53.941] <TB2> INFO: Expecting 41600 events.
[14:54:57.457] <TB2> INFO: 41600 events read in total (2924ms).
[14:54:57.458] <TB2> INFO: Test took 3795ms.
[14:54:57.746] <TB2> INFO: Expecting 41600 events.
[14:55:01.198] <TB2> INFO: 41600 events read in total (2860ms).
[14:55:01.199] <TB2> INFO: Test took 3718ms.
[14:55:01.488] <TB2> INFO: Expecting 41600 events.
[14:55:05.021] <TB2> INFO: 41600 events read in total (2942ms).
[14:55:05.022] <TB2> INFO: Test took 3799ms.
[14:55:05.314] <TB2> INFO: Expecting 41600 events.
[14:55:08.814] <TB2> INFO: 41600 events read in total (2908ms).
[14:55:08.816] <TB2> INFO: Test took 3767ms.
[14:55:09.104] <TB2> INFO: Expecting 41600 events.
[14:55:12.579] <TB2> INFO: 41600 events read in total (2883ms).
[14:55:12.580] <TB2> INFO: Test took 3741ms.
[14:55:12.870] <TB2> INFO: Expecting 41600 events.
[14:55:16.407] <TB2> INFO: 41600 events read in total (2945ms).
[14:55:16.408] <TB2> INFO: Test took 3802ms.
[14:55:16.699] <TB2> INFO: Expecting 41600 events.
[14:55:20.152] <TB2> INFO: 41600 events read in total (2862ms).
[14:55:20.153] <TB2> INFO: Test took 3719ms.
[14:55:20.441] <TB2> INFO: Expecting 41600 events.
[14:55:23.902] <TB2> INFO: 41600 events read in total (2869ms).
[14:55:23.903] <TB2> INFO: Test took 3727ms.
[14:55:24.190] <TB2> INFO: Expecting 41600 events.
[14:55:27.713] <TB2> INFO: 41600 events read in total (2931ms).
[14:55:27.714] <TB2> INFO: Test took 3788ms.
[14:55:28.005] <TB2> INFO: Expecting 41600 events.
[14:55:31.447] <TB2> INFO: 41600 events read in total (2851ms).
[14:55:31.448] <TB2> INFO: Test took 3708ms.
[14:55:31.736] <TB2> INFO: Expecting 41600 events.
[14:55:35.178] <TB2> INFO: 41600 events read in total (2850ms).
[14:55:35.179] <TB2> INFO: Test took 3707ms.
[14:55:35.467] <TB2> INFO: Expecting 41600 events.
[14:55:38.917] <TB2> INFO: 41600 events read in total (2854ms).
[14:55:38.918] <TB2> INFO: Test took 3716ms.
[14:55:39.209] <TB2> INFO: Expecting 41600 events.
[14:55:42.725] <TB2> INFO: 41600 events read in total (2925ms).
[14:55:42.726] <TB2> INFO: Test took 3782ms.
[14:55:43.014] <TB2> INFO: Expecting 41600 events.
[14:55:46.544] <TB2> INFO: 41600 events read in total (2938ms).
[14:55:46.545] <TB2> INFO: Test took 3795ms.
[14:55:46.833] <TB2> INFO: Expecting 41600 events.
[14:55:50.256] <TB2> INFO: 41600 events read in total (2832ms).
[14:55:50.257] <TB2> INFO: Test took 3689ms.
[14:55:50.546] <TB2> INFO: Expecting 41600 events.
[14:55:54.038] <TB2> INFO: 41600 events read in total (2900ms).
[14:55:54.039] <TB2> INFO: Test took 3757ms.
[14:55:54.331] <TB2> INFO: Expecting 2560 events.
[14:55:55.214] <TB2> INFO: 2560 events read in total (292ms).
[14:55:55.214] <TB2> INFO: Test took 1160ms.
[14:55:55.522] <TB2> INFO: Expecting 2560 events.
[14:55:56.405] <TB2> INFO: 2560 events read in total (291ms).
[14:55:56.405] <TB2> INFO: Test took 1191ms.
[14:55:56.713] <TB2> INFO: Expecting 2560 events.
[14:55:57.595] <TB2> INFO: 2560 events read in total (291ms).
[14:55:57.596] <TB2> INFO: Test took 1191ms.
[14:55:57.904] <TB2> INFO: Expecting 2560 events.
[14:55:58.789] <TB2> INFO: 2560 events read in total (290ms).
[14:55:58.789] <TB2> INFO: Test took 1193ms.
[14:55:59.097] <TB2> INFO: Expecting 2560 events.
[14:55:59.976] <TB2> INFO: 2560 events read in total (287ms).
[14:55:59.976] <TB2> INFO: Test took 1186ms.
[14:56:00.286] <TB2> INFO: Expecting 2560 events.
[14:56:01.163] <TB2> INFO: 2560 events read in total (286ms).
[14:56:01.163] <TB2> INFO: Test took 1187ms.
[14:56:01.471] <TB2> INFO: Expecting 2560 events.
[14:56:02.350] <TB2> INFO: 2560 events read in total (288ms).
[14:56:02.350] <TB2> INFO: Test took 1187ms.
[14:56:02.658] <TB2> INFO: Expecting 2560 events.
[14:56:03.538] <TB2> INFO: 2560 events read in total (289ms).
[14:56:03.538] <TB2> INFO: Test took 1188ms.
[14:56:03.846] <TB2> INFO: Expecting 2560 events.
[14:56:04.725] <TB2> INFO: 2560 events read in total (287ms).
[14:56:04.725] <TB2> INFO: Test took 1186ms.
[14:56:05.033] <TB2> INFO: Expecting 2560 events.
[14:56:05.912] <TB2> INFO: 2560 events read in total (288ms).
[14:56:05.912] <TB2> INFO: Test took 1186ms.
[14:56:06.220] <TB2> INFO: Expecting 2560 events.
[14:56:07.102] <TB2> INFO: 2560 events read in total (290ms).
[14:56:07.102] <TB2> INFO: Test took 1189ms.
[14:56:07.410] <TB2> INFO: Expecting 2560 events.
[14:56:08.288] <TB2> INFO: 2560 events read in total (287ms).
[14:56:08.288] <TB2> INFO: Test took 1186ms.
[14:56:08.596] <TB2> INFO: Expecting 2560 events.
[14:56:09.480] <TB2> INFO: 2560 events read in total (292ms).
[14:56:09.480] <TB2> INFO: Test took 1191ms.
[14:56:09.788] <TB2> INFO: Expecting 2560 events.
[14:56:10.670] <TB2> INFO: 2560 events read in total (290ms).
[14:56:10.670] <TB2> INFO: Test took 1190ms.
[14:56:10.978] <TB2> INFO: Expecting 2560 events.
[14:56:11.860] <TB2> INFO: 2560 events read in total (290ms).
[14:56:11.860] <TB2> INFO: Test took 1189ms.
[14:56:12.168] <TB2> INFO: Expecting 2560 events.
[14:56:13.052] <TB2> INFO: 2560 events read in total (292ms).
[14:56:13.052] <TB2> INFO: Test took 1191ms.
[14:56:13.055] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:56:13.361] <TB2> INFO: Expecting 655360 events.
[14:56:27.697] <TB2> INFO: 655360 events read in total (13745ms).
[14:56:27.708] <TB2> INFO: Expecting 655360 events.
[14:56:41.708] <TB2> INFO: 655360 events read in total (13588ms).
[14:56:41.728] <TB2> INFO: Expecting 655360 events.
[14:56:55.784] <TB2> INFO: 655360 events read in total (13653ms).
[14:56:55.805] <TB2> INFO: Expecting 655360 events.
[14:57:09.922] <TB2> INFO: 655360 events read in total (13714ms).
[14:57:09.953] <TB2> INFO: Expecting 655360 events.
[14:57:24.013] <TB2> INFO: 655360 events read in total (13657ms).
[14:57:24.040] <TB2> INFO: Expecting 655360 events.
[14:57:38.156] <TB2> INFO: 655360 events read in total (13713ms).
[14:57:38.188] <TB2> INFO: Expecting 655360 events.
[14:57:52.226] <TB2> INFO: 655360 events read in total (13635ms).
[14:57:52.263] <TB2> INFO: Expecting 655360 events.
[14:58:06.460] <TB2> INFO: 655360 events read in total (13794ms).
[14:58:06.518] <TB2> INFO: Expecting 655360 events.
[14:58:20.556] <TB2> INFO: 655360 events read in total (13635ms).
[14:58:20.617] <TB2> INFO: Expecting 655360 events.
[14:58:34.725] <TB2> INFO: 655360 events read in total (13705ms).
[14:58:34.799] <TB2> INFO: Expecting 655360 events.
[14:58:48.938] <TB2> INFO: 655360 events read in total (13736ms).
[14:58:48.999] <TB2> INFO: Expecting 655360 events.
[14:59:03.067] <TB2> INFO: 655360 events read in total (13665ms).
[14:59:03.124] <TB2> INFO: Expecting 655360 events.
[14:59:17.242] <TB2> INFO: 655360 events read in total (13715ms).
[14:59:17.302] <TB2> INFO: Expecting 655360 events.
[14:59:31.407] <TB2> INFO: 655360 events read in total (13702ms).
[14:59:31.496] <TB2> INFO: Expecting 655360 events.
[14:59:45.597] <TB2> INFO: 655360 events read in total (13698ms).
[14:59:45.694] <TB2> INFO: Expecting 655360 events.
[14:59:59.845] <TB2> INFO: 655360 events read in total (13748ms).
[14:59:59.921] <TB2> INFO: Test took 226866ms.
[14:59:59.001] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:00:00.266] <TB2> INFO: Expecting 655360 events.
[15:00:14.351] <TB2> INFO: 655360 events read in total (13493ms).
[15:00:14.361] <TB2> INFO: Expecting 655360 events.
[15:00:28.113] <TB2> INFO: 655360 events read in total (13349ms).
[15:00:28.127] <TB2> INFO: Expecting 655360 events.
[15:00:42.159] <TB2> INFO: 655360 events read in total (13629ms).
[15:00:42.183] <TB2> INFO: Expecting 655360 events.
[15:00:56.115] <TB2> INFO: 655360 events read in total (13530ms).
[15:00:56.138] <TB2> INFO: Expecting 655360 events.
[15:01:10.050] <TB2> INFO: 655360 events read in total (13509ms).
[15:01:10.077] <TB2> INFO: Expecting 655360 events.
[15:01:24.029] <TB2> INFO: 655360 events read in total (13549ms).
[15:01:24.063] <TB2> INFO: Expecting 655360 events.
[15:01:37.690] <TB2> INFO: 655360 events read in total (13224ms).
[15:01:37.724] <TB2> INFO: Expecting 655360 events.
[15:01:51.737] <TB2> INFO: 655360 events read in total (13610ms).
[15:01:51.776] <TB2> INFO: Expecting 655360 events.
[15:02:05.520] <TB2> INFO: 655360 events read in total (13341ms).
[15:02:05.562] <TB2> INFO: Expecting 655360 events.
[15:02:19.592] <TB2> INFO: 655360 events read in total (13627ms).
[15:02:19.641] <TB2> INFO: Expecting 655360 events.
[15:02:33.469] <TB2> INFO: 655360 events read in total (13425ms).
[15:02:33.518] <TB2> INFO: Expecting 655360 events.
[15:02:47.356] <TB2> INFO: 655360 events read in total (13435ms).
[15:02:47.413] <TB2> INFO: Expecting 655360 events.
[15:03:01.475] <TB2> INFO: 655360 events read in total (13659ms).
[15:03:01.532] <TB2> INFO: Expecting 655360 events.
[15:03:15.645] <TB2> INFO: 655360 events read in total (13710ms).
[15:03:15.710] <TB2> INFO: Expecting 655360 events.
[15:03:29.762] <TB2> INFO: 655360 events read in total (13649ms).
[15:03:29.833] <TB2> INFO: Expecting 655360 events.
[15:03:43.841] <TB2> INFO: 655360 events read in total (13605ms).
[15:03:43.914] <TB2> INFO: Test took 223913ms.
[15:03:44.074] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:44.079] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:03:44.083] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:44.088] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:03:44.092] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:03:44.097] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:03:44.101] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:03:44.106] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[15:03:44.110] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:44.115] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:44.119] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:03:44.124] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:03:44.128] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:03:44.133] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:44.137] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:03:44.142] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:03:44.147] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:03:44.152] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:03:44.157] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[15:03:44.162] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:44.167] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:44.171] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:03:44.175] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:03:44.180] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:03:44.185] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:44.190] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:44.194] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:44.199] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:03:44.203] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:03:44.208] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:03:44.212] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:03:44.217] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[15:03:44.221] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[15:03:44.226] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[15:03:44.231] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[15:03:44.235] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[15:03:44.240] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[15:03:44.244] <TB2> INFO: safety margin for low PH: adding 11, margin is now 31
[15:03:44.249] <TB2> INFO: safety margin for low PH: adding 12, margin is now 32
[15:03:44.253] <TB2> INFO: safety margin for low PH: adding 13, margin is now 33
[15:03:44.258] <TB2> INFO: safety margin for low PH: adding 14, margin is now 34
[15:03:44.263] <TB2> INFO: safety margin for low PH: adding 15, margin is now 35
[15:03:44.267] <TB2> INFO: safety margin for low PH: adding 16, margin is now 36
[15:03:44.272] <TB2> INFO: safety margin for low PH: adding 17, margin is now 37
[15:03:44.276] <TB2> INFO: safety margin for low PH: adding 18, margin is now 38
[15:03:44.281] <TB2> INFO: safety margin for low PH: adding 19, margin is now 39
[15:03:44.286] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:44.290] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:03:44.295] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:44.300] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:44.304] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:03:44.309] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:03:44.313] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:03:44.318] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:03:44.323] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:44.327] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:03:44.332] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:03:44.336] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:03:44.341] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:03:44.345] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[15:03:44.350] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[15:03:44.355] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:44.359] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:44.364] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:03:44.369] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:03:44.373] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:03:44.378] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:03:44.411] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C0.dat
[15:03:44.411] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C1.dat
[15:03:44.411] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C2.dat
[15:03:44.412] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C3.dat
[15:03:44.412] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C4.dat
[15:03:44.412] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C5.dat
[15:03:44.412] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C6.dat
[15:03:44.412] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C7.dat
[15:03:44.412] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C8.dat
[15:03:44.412] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C9.dat
[15:03:44.412] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C10.dat
[15:03:44.412] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C11.dat
[15:03:44.413] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C12.dat
[15:03:44.413] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C13.dat
[15:03:44.413] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C14.dat
[15:03:44.413] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C15.dat
[15:03:44.685] <TB2> INFO: Expecting 41600 events.
[15:03:47.827] <TB2> INFO: 41600 events read in total (2550ms).
[15:03:47.827] <TB2> INFO: Test took 3410ms.
[15:03:48.272] <TB2> INFO: Expecting 41600 events.
[15:03:51.298] <TB2> INFO: 41600 events read in total (2435ms).
[15:03:51.299] <TB2> INFO: Test took 3259ms.
[15:03:51.742] <TB2> INFO: Expecting 41600 events.
[15:03:54.831] <TB2> INFO: 41600 events read in total (2497ms).
[15:03:54.832] <TB2> INFO: Test took 3321ms.
[15:03:55.047] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:55.135] <TB2> INFO: Expecting 2560 events.
[15:03:56.018] <TB2> INFO: 2560 events read in total (291ms).
[15:03:56.018] <TB2> INFO: Test took 971ms.
[15:03:56.020] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:56.327] <TB2> INFO: Expecting 2560 events.
[15:03:57.209] <TB2> INFO: 2560 events read in total (291ms).
[15:03:57.210] <TB2> INFO: Test took 1190ms.
[15:03:57.211] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:57.518] <TB2> INFO: Expecting 2560 events.
[15:03:58.405] <TB2> INFO: 2560 events read in total (295ms).
[15:03:58.405] <TB2> INFO: Test took 1194ms.
[15:03:58.407] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:58.713] <TB2> INFO: Expecting 2560 events.
[15:03:59.595] <TB2> INFO: 2560 events read in total (290ms).
[15:03:59.596] <TB2> INFO: Test took 1189ms.
[15:03:59.597] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:59.904] <TB2> INFO: Expecting 2560 events.
[15:04:00.791] <TB2> INFO: 2560 events read in total (295ms).
[15:04:00.791] <TB2> INFO: Test took 1194ms.
[15:04:00.793] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:01.100] <TB2> INFO: Expecting 2560 events.
[15:04:01.983] <TB2> INFO: 2560 events read in total (292ms).
[15:04:01.983] <TB2> INFO: Test took 1190ms.
[15:04:01.985] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:02.292] <TB2> INFO: Expecting 2560 events.
[15:04:03.178] <TB2> INFO: 2560 events read in total (294ms).
[15:04:03.178] <TB2> INFO: Test took 1193ms.
[15:04:03.180] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:03.486] <TB2> INFO: Expecting 2560 events.
[15:04:04.372] <TB2> INFO: 2560 events read in total (294ms).
[15:04:04.372] <TB2> INFO: Test took 1192ms.
[15:04:04.374] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:04.681] <TB2> INFO: Expecting 2560 events.
[15:04:05.564] <TB2> INFO: 2560 events read in total (291ms).
[15:04:05.564] <TB2> INFO: Test took 1190ms.
[15:04:05.566] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:05.872] <TB2> INFO: Expecting 2560 events.
[15:04:06.753] <TB2> INFO: 2560 events read in total (289ms).
[15:04:06.754] <TB2> INFO: Test took 1188ms.
[15:04:06.755] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:07.064] <TB2> INFO: Expecting 2560 events.
[15:04:07.943] <TB2> INFO: 2560 events read in total (288ms).
[15:04:07.943] <TB2> INFO: Test took 1188ms.
[15:04:07.945] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:08.251] <TB2> INFO: Expecting 2560 events.
[15:04:09.130] <TB2> INFO: 2560 events read in total (287ms).
[15:04:09.131] <TB2> INFO: Test took 1186ms.
[15:04:09.132] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:09.439] <TB2> INFO: Expecting 2560 events.
[15:04:10.320] <TB2> INFO: 2560 events read in total (289ms).
[15:04:10.321] <TB2> INFO: Test took 1189ms.
[15:04:10.322] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:10.629] <TB2> INFO: Expecting 2560 events.
[15:04:11.507] <TB2> INFO: 2560 events read in total (286ms).
[15:04:11.508] <TB2> INFO: Test took 1186ms.
[15:04:11.510] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:11.816] <TB2> INFO: Expecting 2560 events.
[15:04:12.696] <TB2> INFO: 2560 events read in total (288ms).
[15:04:12.696] <TB2> INFO: Test took 1186ms.
[15:04:12.698] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:13.004] <TB2> INFO: Expecting 2560 events.
[15:04:13.884] <TB2> INFO: 2560 events read in total (288ms).
[15:04:13.885] <TB2> INFO: Test took 1187ms.
[15:04:13.886] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:14.193] <TB2> INFO: Expecting 2560 events.
[15:04:15.070] <TB2> INFO: 2560 events read in total (286ms).
[15:04:15.071] <TB2> INFO: Test took 1185ms.
[15:04:15.072] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:15.379] <TB2> INFO: Expecting 2560 events.
[15:04:16.258] <TB2> INFO: 2560 events read in total (287ms).
[15:04:16.258] <TB2> INFO: Test took 1186ms.
[15:04:16.260] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:16.566] <TB2> INFO: Expecting 2560 events.
[15:04:17.446] <TB2> INFO: 2560 events read in total (288ms).
[15:04:17.446] <TB2> INFO: Test took 1186ms.
[15:04:17.448] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:17.754] <TB2> INFO: Expecting 2560 events.
[15:04:18.633] <TB2> INFO: 2560 events read in total (287ms).
[15:04:18.633] <TB2> INFO: Test took 1186ms.
[15:04:18.635] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:18.942] <TB2> INFO: Expecting 2560 events.
[15:04:19.821] <TB2> INFO: 2560 events read in total (288ms).
[15:04:19.821] <TB2> INFO: Test took 1186ms.
[15:04:19.823] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:20.130] <TB2> INFO: Expecting 2560 events.
[15:04:21.009] <TB2> INFO: 2560 events read in total (288ms).
[15:04:21.009] <TB2> INFO: Test took 1186ms.
[15:04:21.011] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:21.317] <TB2> INFO: Expecting 2560 events.
[15:04:22.199] <TB2> INFO: 2560 events read in total (290ms).
[15:04:22.199] <TB2> INFO: Test took 1188ms.
[15:04:22.201] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:22.507] <TB2> INFO: Expecting 2560 events.
[15:04:23.385] <TB2> INFO: 2560 events read in total (286ms).
[15:04:23.385] <TB2> INFO: Test took 1185ms.
[15:04:23.387] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:23.694] <TB2> INFO: Expecting 2560 events.
[15:04:24.578] <TB2> INFO: 2560 events read in total (292ms).
[15:04:24.579] <TB2> INFO: Test took 1192ms.
[15:04:24.581] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:24.887] <TB2> INFO: Expecting 2560 events.
[15:04:25.772] <TB2> INFO: 2560 events read in total (294ms).
[15:04:25.772] <TB2> INFO: Test took 1191ms.
[15:04:25.774] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:26.081] <TB2> INFO: Expecting 2560 events.
[15:04:26.964] <TB2> INFO: 2560 events read in total (292ms).
[15:04:26.965] <TB2> INFO: Test took 1191ms.
[15:04:26.966] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:27.273] <TB2> INFO: Expecting 2560 events.
[15:04:28.156] <TB2> INFO: 2560 events read in total (292ms).
[15:04:28.157] <TB2> INFO: Test took 1191ms.
[15:04:28.158] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:28.465] <TB2> INFO: Expecting 2560 events.
[15:04:29.349] <TB2> INFO: 2560 events read in total (292ms).
[15:04:29.349] <TB2> INFO: Test took 1191ms.
[15:04:29.351] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:29.658] <TB2> INFO: Expecting 2560 events.
[15:04:30.541] <TB2> INFO: 2560 events read in total (291ms).
[15:04:30.542] <TB2> INFO: Test took 1191ms.
[15:04:30.543] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:30.850] <TB2> INFO: Expecting 2560 events.
[15:04:31.734] <TB2> INFO: 2560 events read in total (293ms).
[15:04:31.734] <TB2> INFO: Test took 1191ms.
[15:04:31.736] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:04:32.043] <TB2> INFO: Expecting 2560 events.
[15:04:32.927] <TB2> INFO: 2560 events read in total (293ms).
[15:04:32.927] <TB2> INFO: Test took 1191ms.
[15:04:33.391] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 621 seconds
[15:04:33.391] <TB2> INFO: PH scale (per ROC): 45 48 37 44 38 48 39 32 41 40 37 55 34 39 38 35
[15:04:33.391] <TB2> INFO: PH offset (per ROC): 94 113 95 114 97 138 102 99 108 112 95 122 102 111 105 93
[15:04:33.396] <TB2> INFO: Decoding statistics:
[15:04:33.396] <TB2> INFO: General information:
[15:04:33.396] <TB2> INFO: 16bit words read: 127720
[15:04:33.396] <TB2> INFO: valid events total: 20480
[15:04:33.396] <TB2> INFO: empty events: 18060
[15:04:33.396] <TB2> INFO: valid events with pixels: 2420
[15:04:33.396] <TB2> INFO: valid pixel hits: 2420
[15:04:33.396] <TB2> INFO: Event errors: 0
[15:04:33.396] <TB2> INFO: start marker: 0
[15:04:33.396] <TB2> INFO: stop marker: 0
[15:04:33.396] <TB2> INFO: overflow: 0
[15:04:33.396] <TB2> INFO: invalid 5bit words: 0
[15:04:33.396] <TB2> INFO: invalid XOR eye diagram: 0
[15:04:33.396] <TB2> INFO: frame (failed synchr.): 0
[15:04:33.396] <TB2> INFO: idle data (no TBM trl): 0
[15:04:33.396] <TB2> INFO: no data (only TBM hdr): 0
[15:04:33.396] <TB2> INFO: TBM errors: 0
[15:04:33.396] <TB2> INFO: flawed TBM headers: 0
[15:04:33.396] <TB2> INFO: flawed TBM trailers: 0
[15:04:33.396] <TB2> INFO: event ID mismatches: 0
[15:04:33.396] <TB2> INFO: ROC errors: 0
[15:04:33.396] <TB2> INFO: missing ROC header(s): 0
[15:04:33.396] <TB2> INFO: misplaced readback start: 0
[15:04:33.396] <TB2> INFO: Pixel decoding errors: 0
[15:04:33.396] <TB2> INFO: pixel data incomplete: 0
[15:04:33.396] <TB2> INFO: pixel address: 0
[15:04:33.396] <TB2> INFO: pulse height fill bit: 0
[15:04:33.396] <TB2> INFO: buffer corruption: 0
[15:04:33.675] <TB2> INFO: ######################################################################
[15:04:33.675] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[15:04:33.675] <TB2> INFO: ######################################################################
[15:04:33.685] <TB2> INFO: scanning low vcal = 10
[15:04:33.916] <TB2> INFO: Expecting 41600 events.
[15:04:37.478] <TB2> INFO: 41600 events read in total (2970ms).
[15:04:37.479] <TB2> INFO: Test took 3794ms.
[15:04:37.481] <TB2> INFO: scanning low vcal = 20
[15:04:37.777] <TB2> INFO: Expecting 41600 events.
[15:04:41.367] <TB2> INFO: 41600 events read in total (2999ms).
[15:04:41.368] <TB2> INFO: Test took 3887ms.
[15:04:41.369] <TB2> INFO: scanning low vcal = 30
[15:04:41.667] <TB2> INFO: Expecting 41600 events.
[15:04:45.283] <TB2> INFO: 41600 events read in total (3025ms).
[15:04:45.283] <TB2> INFO: Test took 3914ms.
[15:04:45.286] <TB2> INFO: scanning low vcal = 40
[15:04:45.565] <TB2> INFO: Expecting 41600 events.
[15:04:49.476] <TB2> INFO: 41600 events read in total (3320ms).
[15:04:49.477] <TB2> INFO: Test took 4191ms.
[15:04:49.480] <TB2> INFO: scanning low vcal = 50
[15:04:49.757] <TB2> INFO: Expecting 41600 events.
[15:04:53.684] <TB2> INFO: 41600 events read in total (3336ms).
[15:04:53.685] <TB2> INFO: Test took 4205ms.
[15:04:53.687] <TB2> INFO: scanning low vcal = 60
[15:04:53.964] <TB2> INFO: Expecting 41600 events.
[15:04:57.891] <TB2> INFO: 41600 events read in total (3335ms).
[15:04:57.892] <TB2> INFO: Test took 4204ms.
[15:04:57.894] <TB2> INFO: scanning low vcal = 70
[15:04:58.171] <TB2> INFO: Expecting 41600 events.
[15:05:02.116] <TB2> INFO: 41600 events read in total (3353ms).
[15:05:02.117] <TB2> INFO: Test took 4223ms.
[15:05:02.119] <TB2> INFO: scanning low vcal = 80
[15:05:02.396] <TB2> INFO: Expecting 41600 events.
[15:05:06.359] <TB2> INFO: 41600 events read in total (3371ms).
[15:05:06.360] <TB2> INFO: Test took 4241ms.
[15:05:06.363] <TB2> INFO: scanning low vcal = 90
[15:05:06.645] <TB2> INFO: Expecting 41600 events.
[15:05:10.628] <TB2> INFO: 41600 events read in total (3391ms).
[15:05:10.629] <TB2> INFO: Test took 4266ms.
[15:05:10.632] <TB2> INFO: scanning low vcal = 100
[15:05:10.909] <TB2> INFO: Expecting 41600 events.
[15:05:14.908] <TB2> INFO: 41600 events read in total (3407ms).
[15:05:14.909] <TB2> INFO: Test took 4277ms.
[15:05:14.912] <TB2> INFO: scanning low vcal = 110
[15:05:15.189] <TB2> INFO: Expecting 41600 events.
[15:05:19.141] <TB2> INFO: 41600 events read in total (3360ms).
[15:05:19.142] <TB2> INFO: Test took 4229ms.
[15:05:19.145] <TB2> INFO: scanning low vcal = 120
[15:05:19.421] <TB2> INFO: Expecting 41600 events.
[15:05:23.364] <TB2> INFO: 41600 events read in total (3351ms).
[15:05:23.368] <TB2> INFO: Test took 4223ms.
[15:05:23.370] <TB2> INFO: scanning low vcal = 130
[15:05:23.647] <TB2> INFO: Expecting 41600 events.
[15:05:27.577] <TB2> INFO: 41600 events read in total (3339ms).
[15:05:27.578] <TB2> INFO: Test took 4208ms.
[15:05:27.581] <TB2> INFO: scanning low vcal = 140
[15:05:27.860] <TB2> INFO: Expecting 41600 events.
[15:05:31.814] <TB2> INFO: 41600 events read in total (3362ms).
[15:05:31.815] <TB2> INFO: Test took 4234ms.
[15:05:31.817] <TB2> INFO: scanning low vcal = 150
[15:05:32.094] <TB2> INFO: Expecting 41600 events.
[15:05:36.046] <TB2> INFO: 41600 events read in total (3360ms).
[15:05:36.046] <TB2> INFO: Test took 4229ms.
[15:05:36.049] <TB2> INFO: scanning low vcal = 160
[15:05:36.326] <TB2> INFO: Expecting 41600 events.
[15:05:40.264] <TB2> INFO: 41600 events read in total (3347ms).
[15:05:40.265] <TB2> INFO: Test took 4216ms.
[15:05:40.267] <TB2> INFO: scanning low vcal = 170
[15:05:40.544] <TB2> INFO: Expecting 41600 events.
[15:05:44.549] <TB2> INFO: 41600 events read in total (3413ms).
[15:05:44.551] <TB2> INFO: Test took 4284ms.
[15:05:44.553] <TB2> INFO: scanning low vcal = 180
[15:05:44.830] <TB2> INFO: Expecting 41600 events.
[15:05:48.779] <TB2> INFO: 41600 events read in total (3358ms).
[15:05:48.780] <TB2> INFO: Test took 4227ms.
[15:05:48.782] <TB2> INFO: scanning low vcal = 190
[15:05:49.059] <TB2> INFO: Expecting 41600 events.
[15:05:52.986] <TB2> INFO: 41600 events read in total (3336ms).
[15:05:52.986] <TB2> INFO: Test took 4204ms.
[15:05:52.989] <TB2> INFO: scanning low vcal = 200
[15:05:53.266] <TB2> INFO: Expecting 41600 events.
[15:05:57.193] <TB2> INFO: 41600 events read in total (3336ms).
[15:05:57.193] <TB2> INFO: Test took 4204ms.
[15:05:57.196] <TB2> INFO: scanning low vcal = 210
[15:05:57.473] <TB2> INFO: Expecting 41600 events.
[15:06:01.432] <TB2> INFO: 41600 events read in total (3368ms).
[15:06:01.432] <TB2> INFO: Test took 4235ms.
[15:06:01.435] <TB2> INFO: scanning low vcal = 220
[15:06:01.714] <TB2> INFO: Expecting 41600 events.
[15:06:05.712] <TB2> INFO: 41600 events read in total (3406ms).
[15:06:05.713] <TB2> INFO: Test took 4278ms.
[15:06:05.716] <TB2> INFO: scanning low vcal = 230
[15:06:05.993] <TB2> INFO: Expecting 41600 events.
[15:06:10.014] <TB2> INFO: 41600 events read in total (3429ms).
[15:06:10.015] <TB2> INFO: Test took 4299ms.
[15:06:10.017] <TB2> INFO: scanning low vcal = 240
[15:06:10.294] <TB2> INFO: Expecting 41600 events.
[15:06:14.238] <TB2> INFO: 41600 events read in total (3352ms).
[15:06:14.239] <TB2> INFO: Test took 4221ms.
[15:06:14.241] <TB2> INFO: scanning low vcal = 250
[15:06:14.518] <TB2> INFO: Expecting 41600 events.
[15:06:18.453] <TB2> INFO: 41600 events read in total (3344ms).
[15:06:18.454] <TB2> INFO: Test took 4212ms.
[15:06:18.457] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[15:06:18.733] <TB2> INFO: Expecting 41600 events.
[15:06:22.739] <TB2> INFO: 41600 events read in total (3412ms).
[15:06:22.740] <TB2> INFO: Test took 4283ms.
[15:06:22.742] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[15:06:23.019] <TB2> INFO: Expecting 41600 events.
[15:06:26.997] <TB2> INFO: 41600 events read in total (3386ms).
[15:06:26.998] <TB2> INFO: Test took 4255ms.
[15:06:26.001] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[15:06:27.281] <TB2> INFO: Expecting 41600 events.
[15:06:31.236] <TB2> INFO: 41600 events read in total (3363ms).
[15:06:31.237] <TB2> INFO: Test took 4236ms.
[15:06:31.240] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[15:06:31.534] <TB2> INFO: Expecting 41600 events.
[15:06:35.477] <TB2> INFO: 41600 events read in total (3351ms).
[15:06:35.478] <TB2> INFO: Test took 4238ms.
[15:06:35.481] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[15:06:35.757] <TB2> INFO: Expecting 41600 events.
[15:06:39.714] <TB2> INFO: 41600 events read in total (3365ms).
[15:06:39.714] <TB2> INFO: Test took 4233ms.
[15:06:40.185] <TB2> INFO: PixTestGainPedestal::measure() done
[15:07:18.858] <TB2> INFO: PixTestGainPedestal::fit() done
[15:07:18.858] <TB2> INFO: non-linearity mean: 0.947 0.985 0.948 0.956 0.962 0.980 0.936 0.979 0.932 0.945 0.933 0.985 0.983 0.946 0.930 0.976
[15:07:18.858] <TB2> INFO: non-linearity RMS: 0.058 0.003 0.139 0.037 0.167 0.005 0.054 0.193 0.088 0.072 0.155 0.002 0.165 0.065 0.067 0.170
[15:07:18.858] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[15:07:18.873] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[15:07:18.886] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[15:07:18.900] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[15:07:18.914] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[15:07:18.927] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[15:07:18.941] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[15:07:18.959] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[15:07:18.973] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[15:07:18.987] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[15:07:18.001] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[15:07:19.014] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[15:07:19.028] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[15:07:19.042] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[15:07:19.062] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[15:07:19.085] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[15:07:19.109] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 165 seconds
[15:07:19.109] <TB2> INFO: Decoding statistics:
[15:07:19.109] <TB2> INFO: General information:
[15:07:19.109] <TB2> INFO: 16bit words read: 3259804
[15:07:19.109] <TB2> INFO: valid events total: 332800
[15:07:19.109] <TB2> INFO: empty events: 2550
[15:07:19.109] <TB2> INFO: valid events with pixels: 330250
[15:07:19.109] <TB2> INFO: valid pixel hits: 631502
[15:07:19.109] <TB2> INFO: Event errors: 0
[15:07:19.109] <TB2> INFO: start marker: 0
[15:07:19.109] <TB2> INFO: stop marker: 0
[15:07:19.109] <TB2> INFO: overflow: 0
[15:07:19.109] <TB2> INFO: invalid 5bit words: 0
[15:07:19.109] <TB2> INFO: invalid XOR eye diagram: 0
[15:07:19.109] <TB2> INFO: frame (failed synchr.): 0
[15:07:19.109] <TB2> INFO: idle data (no TBM trl): 0
[15:07:19.109] <TB2> INFO: no data (only TBM hdr): 0
[15:07:19.109] <TB2> INFO: TBM errors: 0
[15:07:19.109] <TB2> INFO: flawed TBM headers: 0
[15:07:19.109] <TB2> INFO: flawed TBM trailers: 0
[15:07:19.109] <TB2> INFO: event ID mismatches: 0
[15:07:19.109] <TB2> INFO: ROC errors: 0
[15:07:19.109] <TB2> INFO: missing ROC header(s): 0
[15:07:19.109] <TB2> INFO: misplaced readback start: 0
[15:07:19.109] <TB2> INFO: Pixel decoding errors: 0
[15:07:19.109] <TB2> INFO: pixel data incomplete: 0
[15:07:19.109] <TB2> INFO: pixel address: 0
[15:07:19.109] <TB2> INFO: pulse height fill bit: 0
[15:07:19.109] <TB2> INFO: buffer corruption: 0
[15:07:19.130] <TB2> INFO: Decoding statistics:
[15:07:19.130] <TB2> INFO: General information:
[15:07:19.130] <TB2> INFO: 16bit words read: 3389060
[15:07:19.130] <TB2> INFO: valid events total: 353536
[15:07:19.130] <TB2> INFO: empty events: 20866
[15:07:19.130] <TB2> INFO: valid events with pixels: 332670
[15:07:19.130] <TB2> INFO: valid pixel hits: 633922
[15:07:19.130] <TB2> INFO: Event errors: 0
[15:07:19.130] <TB2> INFO: start marker: 0
[15:07:19.131] <TB2> INFO: stop marker: 0
[15:07:19.131] <TB2> INFO: overflow: 0
[15:07:19.131] <TB2> INFO: invalid 5bit words: 0
[15:07:19.131] <TB2> INFO: invalid XOR eye diagram: 0
[15:07:19.131] <TB2> INFO: frame (failed synchr.): 0
[15:07:19.131] <TB2> INFO: idle data (no TBM trl): 0
[15:07:19.131] <TB2> INFO: no data (only TBM hdr): 0
[15:07:19.131] <TB2> INFO: TBM errors: 0
[15:07:19.131] <TB2> INFO: flawed TBM headers: 0
[15:07:19.131] <TB2> INFO: flawed TBM trailers: 0
[15:07:19.131] <TB2> INFO: event ID mismatches: 0
[15:07:19.131] <TB2> INFO: ROC errors: 0
[15:07:19.131] <TB2> INFO: missing ROC header(s): 0
[15:07:19.131] <TB2> INFO: misplaced readback start: 0
[15:07:19.131] <TB2> INFO: Pixel decoding errors: 0
[15:07:19.131] <TB2> INFO: pixel data incomplete: 0
[15:07:19.131] <TB2> INFO: pixel address: 0
[15:07:19.131] <TB2> INFO: pulse height fill bit: 0
[15:07:19.131] <TB2> INFO: buffer corruption: 0
[15:07:19.131] <TB2> INFO: enter test to run
[15:07:19.131] <TB2> INFO: test: Trim80 no parameter change
[15:07:19.131] <TB2> INFO: running: trim80
[15:07:19.153] <TB2> INFO: ######################################################################
[15:07:19.153] <TB2> INFO: PixTestTrim80::doTest()
[15:07:19.153] <TB2> INFO: ######################################################################
[15:07:19.154] <TB2> INFO: ----------------------------------------------------------------------
[15:07:19.154] <TB2> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[15:07:19.154] <TB2> INFO: ----------------------------------------------------------------------
[15:07:19.194] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[15:07:19.194] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[15:07:19.206] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:07:19.206] <TB2> INFO: run 1 of 1
[15:07:19.458] <TB2> INFO: Expecting 5025280 events.
[15:07:47.193] <TB2> INFO: 684752 events read in total (27143ms).
[15:08:14.200] <TB2> INFO: 1366576 events read in total (54150ms).
[15:08:41.314] <TB2> INFO: 2046192 events read in total (81264ms).
[15:09:08.470] <TB2> INFO: 2725032 events read in total (108420ms).
[15:09:35.846] <TB2> INFO: 3403400 events read in total (135796ms).
[15:10:02.829] <TB2> INFO: 4080408 events read in total (162779ms).
[15:10:30.202] <TB2> INFO: 4757592 events read in total (190152ms).
[15:10:41.107] <TB2> INFO: 5025280 events read in total (201057ms).
[15:10:41.177] <TB2> INFO: Test took 201971ms.
[15:11:05.057] <TB2> INFO: ROC 0 VthrComp = 75
[15:11:05.057] <TB2> INFO: ROC 1 VthrComp = 86
[15:11:05.057] <TB2> INFO: ROC 2 VthrComp = 78
[15:11:05.057] <TB2> INFO: ROC 3 VthrComp = 79
[15:11:05.057] <TB2> INFO: ROC 4 VthrComp = 64
[15:11:05.057] <TB2> INFO: ROC 5 VthrComp = 79
[15:11:05.057] <TB2> INFO: ROC 6 VthrComp = 83
[15:11:05.058] <TB2> INFO: ROC 7 VthrComp = 84
[15:11:05.058] <TB2> INFO: ROC 8 VthrComp = 90
[15:11:05.058] <TB2> INFO: ROC 9 VthrComp = 75
[15:11:05.058] <TB2> INFO: ROC 10 VthrComp = 86
[15:11:05.058] <TB2> INFO: ROC 11 VthrComp = 76
[15:11:05.058] <TB2> INFO: ROC 12 VthrComp = 77
[15:11:05.058] <TB2> INFO: ROC 13 VthrComp = 76
[15:11:05.059] <TB2> INFO: ROC 14 VthrComp = 74
[15:11:05.059] <TB2> INFO: ROC 15 VthrComp = 81
[15:11:05.292] <TB2> INFO: Expecting 41600 events.
[15:11:08.746] <TB2> INFO: 41600 events read in total (2862ms).
[15:11:08.747] <TB2> INFO: Test took 3686ms.
[15:11:08.756] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[15:11:08.756] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[15:11:08.765] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:11:08.765] <TB2> INFO: run 1 of 1
[15:11:09.043] <TB2> INFO: Expecting 5025280 events.
[15:11:36.664] <TB2> INFO: 688968 events read in total (27030ms).
[15:12:03.607] <TB2> INFO: 1373760 events read in total (53973ms).
[15:12:30.594] <TB2> INFO: 2056136 events read in total (80960ms).
[15:12:57.378] <TB2> INFO: 2735808 events read in total (107744ms).
[15:13:23.974] <TB2> INFO: 3412184 events read in total (134340ms).
[15:13:50.905] <TB2> INFO: 4086664 events read in total (161271ms).
[15:14:17.232] <TB2> INFO: 4762136 events read in total (187598ms).
[15:14:27.625] <TB2> INFO: 5025280 events read in total (197991ms).
[15:14:27.670] <TB2> INFO: Test took 198905ms.
[15:14:48.889] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 108.853 for pixel 0/17 mean/min/max = 93.3745/77.8681/108.881
[15:14:48.890] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 110.255 for pixel 25/39 mean/min/max = 92.565/74.7294/110.401
[15:14:48.890] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 114.741 for pixel 14/8 mean/min/max = 96.1553/77.5654/114.745
[15:14:48.891] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 113.521 for pixel 0/53 mean/min/max = 95.4591/77.2241/113.694
[15:14:48.891] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 107.265 for pixel 2/61 mean/min/max = 91.2574/75.1806/107.334
[15:14:48.892] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 108.108 for pixel 28/52 mean/min/max = 92.9121/77.5915/108.233
[15:14:48.892] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 109.916 for pixel 4/73 mean/min/max = 92.3373/74.4907/110.184
[15:14:48.892] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 108.065 for pixel 51/14 mean/min/max = 91.5253/74.84/108.211
[15:14:48.893] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 111.309 for pixel 48/63 mean/min/max = 93.2354/74.9656/111.505
[15:14:48.893] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 110.292 for pixel 17/77 mean/min/max = 94.2499/78.1102/110.39
[15:14:48.893] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 109.177 for pixel 0/68 mean/min/max = 91.5324/73.7954/109.269
[15:14:48.894] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 112.12 for pixel 5/2 mean/min/max = 95.0796/77.8372/112.322
[15:14:48.894] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 112.918 for pixel 51/73 mean/min/max = 95.8131/78.6666/112.96
[15:14:48.894] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 111.726 for pixel 2/1 mean/min/max = 95.3309/78.7636/111.898
[15:14:48.895] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 111.404 for pixel 0/5 mean/min/max = 94.041/76.646/111.436
[15:14:48.895] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 110.369 for pixel 0/25 mean/min/max = 92.7511/74.8092/110.693
[15:14:48.895] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:48.984] <TB2> INFO: Expecting 411648 events.
[15:14:58.155] <TB2> INFO: 411648 events read in total (8579ms).
[15:14:58.163] <TB2> INFO: Expecting 411648 events.
[15:15:07.226] <TB2> INFO: 411648 events read in total (8660ms).
[15:15:07.235] <TB2> INFO: Expecting 411648 events.
[15:15:16.286] <TB2> INFO: 411648 events read in total (8648ms).
[15:15:16.298] <TB2> INFO: Expecting 411648 events.
[15:15:25.354] <TB2> INFO: 411648 events read in total (8653ms).
[15:15:25.369] <TB2> INFO: Expecting 411648 events.
[15:15:34.438] <TB2> INFO: 411648 events read in total (8666ms).
[15:15:34.460] <TB2> INFO: Expecting 411648 events.
[15:15:43.490] <TB2> INFO: 411648 events read in total (8627ms).
[15:15:43.515] <TB2> INFO: Expecting 411648 events.
[15:15:52.550] <TB2> INFO: 411648 events read in total (8632ms).
[15:15:52.572] <TB2> INFO: Expecting 411648 events.
[15:16:01.719] <TB2> INFO: 411648 events read in total (8744ms).
[15:16:01.744] <TB2> INFO: Expecting 411648 events.
[15:16:10.841] <TB2> INFO: 411648 events read in total (8694ms).
[15:16:10.868] <TB2> INFO: Expecting 411648 events.
[15:16:19.937] <TB2> INFO: 411648 events read in total (8666ms).
[15:16:19.966] <TB2> INFO: Expecting 411648 events.
[15:16:29.052] <TB2> INFO: 411648 events read in total (8683ms).
[15:16:29.086] <TB2> INFO: Expecting 411648 events.
[15:16:38.220] <TB2> INFO: 411648 events read in total (8730ms).
[15:16:38.258] <TB2> INFO: Expecting 411648 events.
[15:16:47.350] <TB2> INFO: 411648 events read in total (8689ms).
[15:16:47.387] <TB2> INFO: Expecting 411648 events.
[15:16:56.590] <TB2> INFO: 411648 events read in total (8800ms).
[15:16:56.648] <TB2> INFO: Expecting 411648 events.
[15:17:05.864] <TB2> INFO: 411648 events read in total (8813ms).
[15:17:05.919] <TB2> INFO: Expecting 411648 events.
[15:17:15.067] <TB2> INFO: 411648 events read in total (8745ms).
[15:17:15.131] <TB2> INFO: Test took 146236ms.
[15:17:16.791] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[15:17:16.801] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:17:16.801] <TB2> INFO: run 1 of 1
[15:17:17.032] <TB2> INFO: Expecting 5025280 events.
[15:17:44.588] <TB2> INFO: 665560 events read in total (26964ms).
[15:18:11.618] <TB2> INFO: 1329328 events read in total (53994ms).
[15:18:38.534] <TB2> INFO: 1992384 events read in total (80910ms).
[15:19:05.741] <TB2> INFO: 2653584 events read in total (108117ms).
[15:19:32.175] <TB2> INFO: 3310776 events read in total (134551ms).
[15:19:58.741] <TB2> INFO: 3967024 events read in total (161117ms).
[15:20:25.650] <TB2> INFO: 4622280 events read in total (188026ms).
[15:20:42.153] <TB2> INFO: 5025280 events read in total (204529ms).
[15:20:42.219] <TB2> INFO: Test took 205418ms.
[15:21:07.559] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 50.290590 .. 119.052363
[15:21:07.831] <TB2> INFO: Expecting 208000 events.
[15:21:17.323] <TB2> INFO: 208000 events read in total (8901ms).
[15:21:17.324] <TB2> INFO: Test took 9764ms.
[15:21:17.376] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 40 .. 129 (-1/-1) hits flags = 528 (plus default)
[15:21:17.387] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:21:17.387] <TB2> INFO: run 1 of 1
[15:21:17.665] <TB2> INFO: Expecting 2995200 events.
[15:21:45.171] <TB2> INFO: 654952 events read in total (26915ms).
[15:22:12.612] <TB2> INFO: 1308712 events read in total (54357ms).
[15:22:39.579] <TB2> INFO: 1958864 events read in total (81323ms).
[15:23:06.207] <TB2> INFO: 2606048 events read in total (107951ms).
[15:23:21.918] <TB2> INFO: 2995200 events read in total (123662ms).
[15:23:21.961] <TB2> INFO: Test took 124575ms.
[15:23:44.918] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 60.574551 .. 105.303494
[15:23:45.153] <TB2> INFO: Expecting 208000 events.
[15:23:54.702] <TB2> INFO: 208000 events read in total (8958ms).
[15:23:54.703] <TB2> INFO: Test took 9783ms.
[15:23:54.766] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 50 .. 115 (-1/-1) hits flags = 528 (plus default)
[15:23:54.776] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:23:54.776] <TB2> INFO: run 1 of 1
[15:23:55.054] <TB2> INFO: Expecting 2196480 events.
[15:24:22.568] <TB2> INFO: 654792 events read in total (26922ms).
[15:24:49.243] <TB2> INFO: 1309744 events read in total (53597ms).
[15:25:16.385] <TB2> INFO: 1963992 events read in total (80739ms).
[15:25:26.350] <TB2> INFO: 2196480 events read in total (90704ms).
[15:25:26.389] <TB2> INFO: Test took 91613ms.
[15:25:46.308] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 65.941606 .. 98.232115
[15:25:46.630] <TB2> INFO: Expecting 208000 events.
[15:25:56.740] <TB2> INFO: 208000 events read in total (9518ms).
[15:25:56.740] <TB2> INFO: Test took 10430ms.
[15:25:56.786] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 55 .. 108 (-1/-1) hits flags = 528 (plus default)
[15:25:56.797] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:25:56.797] <TB2> INFO: run 1 of 1
[15:25:57.074] <TB2> INFO: Expecting 1797120 events.
[15:26:24.893] <TB2> INFO: 659032 events read in total (27227ms).
[15:26:52.188] <TB2> INFO: 1317464 events read in total (54523ms).
[15:27:12.019] <TB2> INFO: 1797120 events read in total (74353ms).
[15:27:12.046] <TB2> INFO: Test took 75249ms.
[15:27:29.505] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 68.147702 .. 97.914987
[15:27:29.738] <TB2> INFO: Expecting 208000 events.
[15:27:39.666] <TB2> INFO: 208000 events read in total (9336ms).
[15:27:39.667] <TB2> INFO: Test took 10161ms.
[15:27:39.732] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 58 .. 107 (-1/-1) hits flags = 528 (plus default)
[15:27:39.742] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:27:39.742] <TB2> INFO: run 1 of 1
[15:27:40.021] <TB2> INFO: Expecting 1664000 events.
[15:28:07.755] <TB2> INFO: 652728 events read in total (27143ms).
[15:28:34.560] <TB2> INFO: 1305096 events read in total (53949ms).
[15:28:49.914] <TB2> INFO: 1664000 events read in total (69302ms).
[15:28:49.950] <TB2> INFO: Test took 70208ms.
[15:29:07.439] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[15:29:07.439] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[15:29:07.447] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:29:07.447] <TB2> INFO: run 1 of 1
[15:29:07.707] <TB2> INFO: Expecting 1364480 events.
[15:29:35.332] <TB2> INFO: 668136 events read in total (27033ms).
[15:30:03.117] <TB2> INFO: 1335872 events read in total (54819ms).
[15:30:04.694] <TB2> INFO: 1364480 events read in total (56395ms).
[15:30:04.718] <TB2> INFO: Test took 57270ms.
[15:30:22.924] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C0.dat
[15:30:22.924] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C1.dat
[15:30:22.924] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C2.dat
[15:30:22.924] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C3.dat
[15:30:22.924] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C4.dat
[15:30:22.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C5.dat
[15:30:22.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C6.dat
[15:30:22.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C7.dat
[15:30:22.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C8.dat
[15:30:22.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C9.dat
[15:30:22.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C10.dat
[15:30:22.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C11.dat
[15:30:22.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C12.dat
[15:30:22.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C13.dat
[15:30:22.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C14.dat
[15:30:22.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C15.dat
[15:30:22.925] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C0.dat
[15:30:22.931] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C1.dat
[15:30:22.936] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C2.dat
[15:30:22.942] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C3.dat
[15:30:22.948] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C4.dat
[15:30:22.955] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C5.dat
[15:30:22.964] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C6.dat
[15:30:22.971] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C7.dat
[15:30:22.977] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C8.dat
[15:30:22.984] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C9.dat
[15:30:22.989] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C10.dat
[15:30:22.995] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C11.dat
[15:30:23.003] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C12.dat
[15:30:23.010] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C13.dat
[15:30:23.017] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C14.dat
[15:30:23.024] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1084_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C15.dat
[15:30:23.032] <TB2> INFO: PixTestTrim80::trimTest() done
[15:30:23.032] <TB2> INFO: vtrim: 111 123 124 115 105 111 94 109 129 117 103 110 121 131 110 110
[15:30:23.032] <TB2> INFO: vthrcomp: 75 86 78 79 64 79 83 84 90 75 86 76 77 76 74 81
[15:30:23.032] <TB2> INFO: vcal mean: 79.97 79.97 79.95 79.97 79.98 79.95 79.94 79.97 79.99 79.92 79.92 79.98 79.89 79.99 79.96 79.93
[15:30:23.032] <TB2> INFO: vcal RMS: 0.75 0.89 0.84 0.82 0.72 0.71 0.79 0.80 0.80 0.73 0.81 0.78 0.78 0.77 0.77 0.81
[15:30:23.032] <TB2> INFO: bits mean: 9.81 10.63 9.67 9.75 10.29 10.22 9.93 10.28 10.41 10.00 10.09 9.67 9.18 9.51 9.73 10.18
[15:30:23.032] <TB2> INFO: bits RMS: 2.10 2.08 2.08 2.11 2.23 1.94 2.40 2.26 2.11 1.93 2.48 2.09 2.19 2.06 2.24 2.32
[15:30:23.053] <TB2> INFO: ----------------------------------------------------------------------
[15:30:23.053] <TB2> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[15:30:23.053] <TB2> INFO: ----------------------------------------------------------------------
[15:30:23.056] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[15:30:23.068] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:30:23.068] <TB2> INFO: run 1 of 1
[15:30:23.389] <TB2> INFO: Expecting 4160000 events.
[15:30:55.811] <TB2> INFO: 768450 events read in total (31830ms).
[15:31:27.317] <TB2> INFO: 1530895 events read in total (63336ms).
[15:31:58.808] <TB2> INFO: 2287775 events read in total (94827ms).
[15:32:30.240] <TB2> INFO: 3041765 events read in total (126259ms).
[15:33:02.107] <TB2> INFO: 3794860 events read in total (158126ms).
[15:33:17.423] <TB2> INFO: 4160000 events read in total (173442ms).
[15:33:17.484] <TB2> INFO: Test took 174417ms.
[15:33:44.556] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 220 (-1/-1) hits flags = 528 (plus default)
[15:33:44.565] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:33:44.565] <TB2> INFO: run 1 of 1
[15:33:44.797] <TB2> INFO: Expecting 4596800 events.
[15:34:15.909] <TB2> INFO: 715510 events read in total (30520ms).
[15:34:47.619] <TB2> INFO: 1427365 events read in total (62230ms).
[15:35:18.784] <TB2> INFO: 2135455 events read in total (93395ms).
[15:35:49.042] <TB2> INFO: 2839785 events read in total (123653ms).
[15:36:19.277] <TB2> INFO: 3543970 events read in total (153888ms).
[15:36:49.497] <TB2> INFO: 4247720 events read in total (184108ms).
[15:37:04.643] <TB2> INFO: 4596800 events read in total (199254ms).
[15:37:04.702] <TB2> INFO: Test took 200137ms.
[15:37:34.757] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[15:37:34.765] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:37:34.765] <TB2> INFO: run 1 of 1
[15:37:34.999] <TB2> INFO: Expecting 4430400 events.
[15:38:06.241] <TB2> INFO: 725040 events read in total (30651ms).
[15:38:37.413] <TB2> INFO: 1446175 events read in total (61823ms).
[15:39:08.318] <TB2> INFO: 2162995 events read in total (92728ms).
[15:39:39.051] <TB2> INFO: 2875920 events read in total (123461ms).
[15:40:09.767] <TB2> INFO: 3589145 events read in total (154177ms).
[15:40:40.698] <TB2> INFO: 4302455 events read in total (185108ms).
[15:40:46.494] <TB2> INFO: 4430400 events read in total (190904ms).
[15:40:46.561] <TB2> INFO: Test took 191796ms.
[15:41:18.725] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 213 (-1/-1) hits flags = 528 (plus default)
[15:41:18.736] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:41:18.736] <TB2> INFO: run 1 of 1
[15:41:19.012] <TB2> INFO: Expecting 4451200 events.
[15:41:50.453] <TB2> INFO: 724210 events read in total (30849ms).
[15:42:21.056] <TB2> INFO: 1444550 events read in total (61452ms).
[15:42:51.805] <TB2> INFO: 2160975 events read in total (92201ms).
[15:43:22.840] <TB2> INFO: 2873070 events read in total (123236ms).
[15:43:53.343] <TB2> INFO: 3585490 events read in total (153739ms).
[15:44:23.864] <TB2> INFO: 4297945 events read in total (184260ms).
[15:44:30.643] <TB2> INFO: 4451200 events read in total (191039ms).
[15:44:30.716] <TB2> INFO: Test took 191980ms.
[15:45:01.275] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 213 (-1/-1) hits flags = 528 (plus default)
[15:45:01.283] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:45:01.284] <TB2> INFO: run 1 of 1
[15:45:01.519] <TB2> INFO: Expecting 4451200 events.
[15:45:32.798] <TB2> INFO: 724380 events read in total (30687ms).
[15:46:03.921] <TB2> INFO: 1445095 events read in total (61810ms).
[15:46:36.093] <TB2> INFO: 2161425 events read in total (93982ms).
[15:47:08.211] <TB2> INFO: 2873855 events read in total (126100ms).
[15:47:38.268] <TB2> INFO: 3586375 events read in total (156157ms).
[15:48:08.718] <TB2> INFO: 4298925 events read in total (186607ms).
[15:48:15.371] <TB2> INFO: 4451200 events read in total (193260ms).
[15:48:15.428] <TB2> INFO: Test took 194144ms.
[15:48:40.415] <TB2> INFO: PixTestTrim80::trimBitTest() done
[15:48:40.417] <TB2> INFO: PixTestTrim80::doTest() done, duration: 2481 seconds
[15:48:41.059] <TB2> INFO: enter test to run
[15:48:41.059] <TB2> INFO: test: exit no parameter change
[15:48:41.158] <TB2> QUIET: Connection to board 156 closed.
[15:48:41.159] <TB2> INFO: pXar: this is the end, my friend