[13:41:36.997] <TB1> INFO: *** Welcome to pxar ***
[13:41:36.997] <TB1> INFO: *** Today: 2016/10/26
[13:41:36.002] <TB1> INFO: *** Version: c8ba-dirty
[13:41:36.003] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C15.dat
[13:41:37.003] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[13:41:37.003] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//defaultMaskFile.dat
[13:41:37.003] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters_C15.dat
[13:41:37.062] <TB1> INFO: clk: 4
[13:41:37.062] <TB1> INFO: ctr: 4
[13:41:37.062] <TB1> INFO: sda: 19
[13:41:37.062] <TB1> INFO: tin: 9
[13:41:37.062] <TB1> INFO: level: 15
[13:41:37.062] <TB1> INFO: triggerdelay: 0
[13:41:37.062] <TB1> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[13:41:37.062] <TB1> INFO: Log level: INFO
[13:41:37.071] <TB1> INFO: Found DTB DTB_WXBYFL
[13:41:37.081] <TB1> QUIET: Connection to board DTB_WXBYFL opened.
[13:41:37.083] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 153
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXBYFL
MAC address: 40D855118099
Hostname: pixelDTB153
Comment:
------------------------------------------------------
[13:41:37.084] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[13:41:38.640] <TB1> INFO: DUT info:
[13:41:38.640] <TB1> INFO: The DUT currently contains the following objects:
[13:41:38.640] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[13:41:38.640] <TB1> INFO: TBM Core alpha (0): 7 registers set
[13:41:38.640] <TB1> INFO: TBM Core beta (1): 7 registers set
[13:41:38.640] <TB1> INFO: TBM Core alpha (2): 7 registers set
[13:41:38.640] <TB1> INFO: TBM Core beta (3): 7 registers set
[13:41:38.640] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[13:41:38.640] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:38.640] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:38.640] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:38.640] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:38.640] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:38.640] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:38.640] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:38.640] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:38.640] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:38.640] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:38.640] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:38.640] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:38.640] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:38.640] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:38.640] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:38.640] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[13:41:39.041] <TB1> INFO: enter 'restricted' command line mode
[13:41:39.041] <TB1> INFO: enter test to run
[13:41:39.041] <TB1> INFO: test: pretest no parameter change
[13:41:39.041] <TB1> INFO: running: pretest
[13:41:39.970] <TB1> INFO: ######################################################################
[13:41:39.970] <TB1> INFO: PixTestPretest::doTest()
[13:41:39.970] <TB1> INFO: ######################################################################
[13:41:39.971] <TB1> INFO: ----------------------------------------------------------------------
[13:41:39.971] <TB1> INFO: PixTestPretest::programROC()
[13:41:39.971] <TB1> INFO: ----------------------------------------------------------------------
[13:41:57.984] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[13:41:57.984] <TB1> INFO: IA differences per ROC: 19.3 20.1 17.7 19.3 17.7 18.5 17.7 20.9 16.1 19.3 17.7 16.9 20.1 19.3 19.3 17.7
[13:41:58.019] <TB1> INFO: ----------------------------------------------------------------------
[13:41:58.019] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[13:41:58.019] <TB1> INFO: ----------------------------------------------------------------------
[13:42:19.264] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 391.5 mA = 24.4688 mA/ROC
[13:42:19.264] <TB1> INFO: i(loss) [mA/ROC]: 19.3 19.3 18.5 19.3 19.3 20.1 18.5 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3 18.5
[13:42:19.294] <TB1> INFO: ----------------------------------------------------------------------
[13:42:19.294] <TB1> INFO: PixTestPretest::findTiming()
[13:42:19.294] <TB1> INFO: ----------------------------------------------------------------------
[13:42:19.294] <TB1> INFO: PixTestCmd::init()

[13:42:50.618] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[13:42:50.618] <TB1> INFO: (success/tries = 100/100), width = 3
[13:42:52.121] <TB1> INFO: ----------------------------------------------------------------------
[13:42:52.121] <TB1> INFO: PixTestPretest::findWorkingPixel()
[13:42:52.121] <TB1> INFO: ----------------------------------------------------------------------
[13:42:52.212] <TB1> INFO: Expecting 231680 events.
[13:43:01.783] <TB1> INFO: 231680 events read in total (8979ms).
[13:43:01.791] <TB1> INFO: Test took 9668ms.
[13:43:02.042] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[13:43:02.071] <TB1> INFO: ----------------------------------------------------------------------
[13:43:02.071] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[13:43:02.071] <TB1> INFO: ----------------------------------------------------------------------
[13:43:02.163] <TB1> INFO: Expecting 231680 events.
[13:43:11.803] <TB1> INFO: 231680 events read in total (9048ms).
[13:43:11.814] <TB1> INFO: Test took 9739ms.
[13:43:12.074] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[13:43:12.074] <TB1> INFO: CalDel: 88 91 82 93 98 105 95 93 100 75 76 93 87 96 99 77
[13:43:12.074] <TB1> INFO: VthrComp: 51 51 51 51 51 52 51 51 51 54 53 52 61 54 51 54
[13:43:12.077] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C0.dat
[13:43:12.077] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C1.dat
[13:43:12.077] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C2.dat
[13:43:12.077] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C3.dat
[13:43:12.077] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C4.dat
[13:43:12.077] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C5.dat
[13:43:12.077] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C6.dat
[13:43:12.077] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C7.dat
[13:43:12.078] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C8.dat
[13:43:12.078] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C9.dat
[13:43:12.078] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C10.dat
[13:43:12.078] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C11.dat
[13:43:12.078] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C12.dat
[13:43:12.078] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C13.dat
[13:43:12.078] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C14.dat
[13:43:12.078] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters_C15.dat
[13:43:12.078] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[13:43:12.078] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[13:43:12.079] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[13:43:12.079] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[13:43:12.079] <TB1> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[13:43:12.175] <TB1> INFO: enter test to run
[13:43:12.175] <TB1> INFO: test: fulltest no parameter change
[13:43:12.175] <TB1> INFO: running: fulltest
[13:43:12.175] <TB1> INFO: ######################################################################
[13:43:12.175] <TB1> INFO: PixTestFullTest::doTest()
[13:43:12.175] <TB1> INFO: ######################################################################
[13:43:12.176] <TB1> INFO: ######################################################################
[13:43:12.176] <TB1> INFO: PixTestAlive::doTest()
[13:43:12.176] <TB1> INFO: ######################################################################
[13:43:12.177] <TB1> INFO: ----------------------------------------------------------------------
[13:43:12.177] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:43:12.177] <TB1> INFO: ----------------------------------------------------------------------
[13:43:12.411] <TB1> INFO: Expecting 41600 events.
[13:43:15.916] <TB1> INFO: 41600 events read in total (2913ms).
[13:43:15.916] <TB1> INFO: Test took 3737ms.
[13:43:16.141] <TB1> INFO: PixTestAlive::aliveTest() done
[13:43:16.141] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:43:16.142] <TB1> INFO: ----------------------------------------------------------------------
[13:43:16.142] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:43:16.142] <TB1> INFO: ----------------------------------------------------------------------
[13:43:16.374] <TB1> INFO: Expecting 41600 events.
[13:43:19.319] <TB1> INFO: 41600 events read in total (2353ms).
[13:43:19.319] <TB1> INFO: Test took 3176ms.
[13:43:19.319] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[13:43:19.557] <TB1> INFO: PixTestAlive::maskTest() done
[13:43:19.557] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:43:19.558] <TB1> INFO: ----------------------------------------------------------------------
[13:43:19.558] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:43:19.558] <TB1> INFO: ----------------------------------------------------------------------
[13:43:19.792] <TB1> INFO: Expecting 41600 events.
[13:43:23.242] <TB1> INFO: 41600 events read in total (2858ms).
[13:43:23.242] <TB1> INFO: Test took 3683ms.
[13:43:23.469] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[13:43:23.469] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:43:23.469] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[13:43:23.469] <TB1> INFO: Decoding statistics:
[13:43:23.469] <TB1> INFO: General information:
[13:43:23.469] <TB1> INFO: 16bit words read: 0
[13:43:23.469] <TB1> INFO: valid events total: 0
[13:43:23.469] <TB1> INFO: empty events: 0
[13:43:23.469] <TB1> INFO: valid events with pixels: 0
[13:43:23.469] <TB1> INFO: valid pixel hits: 0
[13:43:23.469] <TB1> INFO: Event errors: 0
[13:43:23.469] <TB1> INFO: start marker: 0
[13:43:23.469] <TB1> INFO: stop marker: 0
[13:43:23.469] <TB1> INFO: overflow: 0
[13:43:23.469] <TB1> INFO: invalid 5bit words: 0
[13:43:23.469] <TB1> INFO: invalid XOR eye diagram: 0
[13:43:23.469] <TB1> INFO: frame (failed synchr.): 0
[13:43:23.469] <TB1> INFO: idle data (no TBM trl): 0
[13:43:23.469] <TB1> INFO: no data (only TBM hdr): 0
[13:43:23.469] <TB1> INFO: TBM errors: 0
[13:43:23.469] <TB1> INFO: flawed TBM headers: 0
[13:43:23.469] <TB1> INFO: flawed TBM trailers: 0
[13:43:23.469] <TB1> INFO: event ID mismatches: 0
[13:43:23.469] <TB1> INFO: ROC errors: 0
[13:43:23.469] <TB1> INFO: missing ROC header(s): 0
[13:43:23.469] <TB1> INFO: misplaced readback start: 0
[13:43:23.469] <TB1> INFO: Pixel decoding errors: 0
[13:43:23.469] <TB1> INFO: pixel data incomplete: 0
[13:43:23.469] <TB1> INFO: pixel address: 0
[13:43:23.469] <TB1> INFO: pulse height fill bit: 0
[13:43:23.469] <TB1> INFO: buffer corruption: 0
[13:43:23.476] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:43:23.476] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[13:43:23.476] <TB1> INFO: ######################################################################
[13:43:23.476] <TB1> INFO: PixTestReadback::doTest()
[13:43:23.476] <TB1> INFO: ######################################################################
[13:43:23.476] <TB1> INFO: ----------------------------------------------------------------------
[13:43:23.476] <TB1> INFO: PixTestReadback::CalibrateVd()
[13:43:23.476] <TB1> INFO: ----------------------------------------------------------------------
[13:43:33.447] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C0.dat
[13:43:33.447] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C1.dat
[13:43:33.447] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C2.dat
[13:43:33.447] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C3.dat
[13:43:33.447] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C4.dat
[13:43:33.447] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C5.dat
[13:43:33.447] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C6.dat
[13:43:33.447] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C7.dat
[13:43:33.447] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C8.dat
[13:43:33.447] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C9.dat
[13:43:33.448] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C10.dat
[13:43:33.448] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C11.dat
[13:43:33.448] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C12.dat
[13:43:33.448] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C13.dat
[13:43:33.448] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C14.dat
[13:43:33.448] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:43:33.475] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[13:43:33.475] <TB1> INFO: ----------------------------------------------------------------------
[13:43:33.475] <TB1> INFO: PixTestReadback::CalibrateVa()
[13:43:33.475] <TB1> INFO: ----------------------------------------------------------------------
[13:43:43.375] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C0.dat
[13:43:43.376] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C1.dat
[13:43:43.376] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C2.dat
[13:43:43.376] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C3.dat
[13:43:43.376] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C4.dat
[13:43:43.376] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C5.dat
[13:43:43.376] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C6.dat
[13:43:43.376] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C7.dat
[13:43:43.376] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C8.dat
[13:43:43.376] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C9.dat
[13:43:43.376] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C10.dat
[13:43:43.376] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C11.dat
[13:43:43.376] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C12.dat
[13:43:43.376] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C13.dat
[13:43:43.376] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C14.dat
[13:43:43.376] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:43:43.404] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[13:43:43.404] <TB1> INFO: ----------------------------------------------------------------------
[13:43:43.404] <TB1> INFO: PixTestReadback::readbackVbg()
[13:43:43.404] <TB1> INFO: ----------------------------------------------------------------------
[13:43:51.046] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[13:43:51.046] <TB1> INFO: ----------------------------------------------------------------------
[13:43:51.046] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[13:43:51.046] <TB1> INFO: ----------------------------------------------------------------------
[13:43:51.046] <TB1> INFO: Vbg will be calibrated using Vd calibration
[13:43:51.046] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 165.9calibrated Vbg = 1.16232 :::*/*/*/*/
[13:43:51.046] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 150.8calibrated Vbg = 1.15461 :::*/*/*/*/
[13:43:51.046] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 150.2calibrated Vbg = 1.14966 :::*/*/*/*/
[13:43:51.046] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 157.9calibrated Vbg = 1.15715 :::*/*/*/*/
[13:43:51.046] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 152.9calibrated Vbg = 1.1541 :::*/*/*/*/
[13:43:51.046] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 150.7calibrated Vbg = 1.16155 :::*/*/*/*/
[13:43:51.046] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 154.4calibrated Vbg = 1.1537 :::*/*/*/*/
[13:43:51.046] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 153calibrated Vbg = 1.16143 :::*/*/*/*/
[13:43:51.046] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 164.9calibrated Vbg = 1.15381 :::*/*/*/*/
[13:43:51.046] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 160.2calibrated Vbg = 1.14984 :::*/*/*/*/
[13:43:51.046] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 160calibrated Vbg = 1.15137 :::*/*/*/*/
[13:43:51.046] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 148.1calibrated Vbg = 1.14248 :::*/*/*/*/
[13:43:51.046] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 163calibrated Vbg = 1.15649 :::*/*/*/*/
[13:43:51.046] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 152.5calibrated Vbg = 1.16344 :::*/*/*/*/
[13:43:51.046] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 154.1calibrated Vbg = 1.15446 :::*/*/*/*/
[13:43:51.046] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 162.7calibrated Vbg = 1.15799 :::*/*/*/*/
[13:43:51.048] <TB1> INFO: ----------------------------------------------------------------------
[13:43:51.048] <TB1> INFO: PixTestReadback::CalibrateIa()
[13:43:51.048] <TB1> INFO: ----------------------------------------------------------------------
[13:46:31.359] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C0.dat
[13:46:31.360] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C1.dat
[13:46:31.360] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C2.dat
[13:46:31.360] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C3.dat
[13:46:31.360] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C4.dat
[13:46:31.360] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C5.dat
[13:46:31.360] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C6.dat
[13:46:31.360] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C7.dat
[13:46:31.360] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C8.dat
[13:46:31.360] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C9.dat
[13:46:31.360] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C10.dat
[13:46:31.360] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C11.dat
[13:46:31.360] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C12.dat
[13:46:31.361] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C13.dat
[13:46:31.361] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C14.dat
[13:46:31.361] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//readbackCal_C15.dat
[13:46:31.388] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[13:46:31.389] <TB1> INFO: PixTestReadback::doTest() done
[13:46:31.390] <TB1> INFO: Decoding statistics:
[13:46:31.390] <TB1> INFO: General information:
[13:46:31.390] <TB1> INFO: 16bit words read: 1536
[13:46:31.390] <TB1> INFO: valid events total: 256
[13:46:31.390] <TB1> INFO: empty events: 256
[13:46:31.390] <TB1> INFO: valid events with pixels: 0
[13:46:31.390] <TB1> INFO: valid pixel hits: 0
[13:46:31.390] <TB1> INFO: Event errors: 0
[13:46:31.390] <TB1> INFO: start marker: 0
[13:46:31.390] <TB1> INFO: stop marker: 0
[13:46:31.390] <TB1> INFO: overflow: 0
[13:46:31.390] <TB1> INFO: invalid 5bit words: 0
[13:46:31.390] <TB1> INFO: invalid XOR eye diagram: 0
[13:46:31.390] <TB1> INFO: frame (failed synchr.): 0
[13:46:31.390] <TB1> INFO: idle data (no TBM trl): 0
[13:46:31.390] <TB1> INFO: no data (only TBM hdr): 0
[13:46:31.390] <TB1> INFO: TBM errors: 0
[13:46:31.390] <TB1> INFO: flawed TBM headers: 0
[13:46:31.390] <TB1> INFO: flawed TBM trailers: 0
[13:46:31.390] <TB1> INFO: event ID mismatches: 0
[13:46:31.390] <TB1> INFO: ROC errors: 0
[13:46:31.390] <TB1> INFO: missing ROC header(s): 0
[13:46:31.390] <TB1> INFO: misplaced readback start: 0
[13:46:31.390] <TB1> INFO: Pixel decoding errors: 0
[13:46:31.390] <TB1> INFO: pixel data incomplete: 0
[13:46:31.390] <TB1> INFO: pixel address: 0
[13:46:31.390] <TB1> INFO: pulse height fill bit: 0
[13:46:31.390] <TB1> INFO: buffer corruption: 0
[13:46:31.425] <TB1> INFO: ######################################################################
[13:46:31.425] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[13:46:31.425] <TB1> INFO: ######################################################################
[13:46:31.428] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[13:46:31.439] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:46:31.439] <TB1> INFO: run 1 of 1
[13:46:31.718] <TB1> INFO: Expecting 3120000 events.
[13:47:02.402] <TB1> INFO: 679865 events read in total (30092ms).











[13:47:32.739] <TB1> INFO: 1355065 events read in total (60429ms).
[13:48:02.713] <TB1> INFO: 2027310 events read in total (90403ms).











[13:48:32.527] <TB1> INFO: 2699350 events read in total (120217ms).











[13:48:51.760] <TB1> INFO: 3120000 events read in total (139451ms).
[13:48:51.828] <TB1> INFO: Test took 140389ms.
[13:49:18.365] <TB1> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 166 seconds
[13:49:18.365] <TB1> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 0 0 7 0 0 0 0 1 0 0
[13:49:18.365] <TB1> INFO: separation cut (per ROC): 105 114 105 104 112 114 102 112 106 111 123 108 105 105 106 106
[13:49:18.366] <TB1> INFO: Decoding statistics:
[13:49:18.366] <TB1> INFO: General information:
[13:49:18.366] <TB1> INFO: 16bit words read: 0
[13:49:18.366] <TB1> INFO: valid events total: 0
[13:49:18.366] <TB1> INFO: empty events: 0
[13:49:18.366] <TB1> INFO: valid events with pixels: 0
[13:49:18.366] <TB1> INFO: valid pixel hits: 0
[13:49:18.366] <TB1> INFO: Event errors: 0
[13:49:18.366] <TB1> INFO: start marker: 0
[13:49:18.366] <TB1> INFO: stop marker: 0
[13:49:18.366] <TB1> INFO: overflow: 0
[13:49:18.366] <TB1> INFO: invalid 5bit words: 0
[13:49:18.366] <TB1> INFO: invalid XOR eye diagram: 0
[13:49:18.366] <TB1> INFO: frame (failed synchr.): 0
[13:49:18.366] <TB1> INFO: idle data (no TBM trl): 0
[13:49:18.366] <TB1> INFO: no data (only TBM hdr): 0
[13:49:18.366] <TB1> INFO: TBM errors: 0
[13:49:18.366] <TB1> INFO: flawed TBM headers: 0
[13:49:18.366] <TB1> INFO: flawed TBM trailers: 0
[13:49:18.366] <TB1> INFO: event ID mismatches: 0
[13:49:18.366] <TB1> INFO: ROC errors: 0
[13:49:18.366] <TB1> INFO: missing ROC header(s): 0
[13:49:18.366] <TB1> INFO: misplaced readback start: 0
[13:49:18.366] <TB1> INFO: Pixel decoding errors: 0
[13:49:18.366] <TB1> INFO: pixel data incomplete: 0
[13:49:18.366] <TB1> INFO: pixel address: 0
[13:49:18.366] <TB1> INFO: pulse height fill bit: 0
[13:49:18.366] <TB1> INFO: buffer corruption: 0
[13:49:18.405] <TB1> INFO: ######################################################################
[13:49:18.405] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:49:18.405] <TB1> INFO: ######################################################################
[13:49:18.406] <TB1> INFO: ----------------------------------------------------------------------
[13:49:18.406] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:49:18.406] <TB1> INFO: ----------------------------------------------------------------------
[13:49:18.406] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[13:49:18.415] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[13:49:18.415] <TB1> INFO: run 1 of 1
[13:49:18.651] <TB1> INFO: Expecting 36608000 events.
[13:49:41.953] <TB1> INFO: 700350 events read in total (22710ms).
[13:50:04.552] <TB1> INFO: 1387150 events read in total (45309ms).
[13:50:27.182] <TB1> INFO: 2070650 events read in total (67939ms).
[13:50:49.858] <TB1> INFO: 2755700 events read in total (90615ms).
[13:51:12.373] <TB1> INFO: 3438250 events read in total (113130ms).
[13:51:34.983] <TB1> INFO: 4121450 events read in total (135740ms).
[13:51:57.667] <TB1> INFO: 4800450 events read in total (158424ms).
[13:52:20.203] <TB1> INFO: 5481200 events read in total (180960ms).
[13:52:42.711] <TB1> INFO: 6161950 events read in total (203468ms).
[13:53:05.356] <TB1> INFO: 6845650 events read in total (226113ms).
[13:53:27.914] <TB1> INFO: 7524250 events read in total (248671ms).
[13:53:50.498] <TB1> INFO: 8205000 events read in total (271255ms).
[13:54:13.085] <TB1> INFO: 8884950 events read in total (293842ms).
[13:54:35.850] <TB1> INFO: 9565400 events read in total (316607ms).
[13:54:58.512] <TB1> INFO: 10245550 events read in total (339269ms).
[13:55:20.952] <TB1> INFO: 10924400 events read in total (361709ms).
[13:55:43.501] <TB1> INFO: 11603300 events read in total (384258ms).
[13:56:05.847] <TB1> INFO: 12282850 events read in total (406604ms).
[13:56:28.308] <TB1> INFO: 12961300 events read in total (429065ms).
[13:56:50.916] <TB1> INFO: 13638600 events read in total (451673ms).
[13:57:13.230] <TB1> INFO: 14316400 events read in total (473987ms).
[13:57:35.383] <TB1> INFO: 14993400 events read in total (496140ms).
[13:57:58.025] <TB1> INFO: 15670950 events read in total (518782ms).
[13:58:20.294] <TB1> INFO: 16346850 events read in total (541051ms).
[13:58:42.630] <TB1> INFO: 17024450 events read in total (563387ms).
[13:59:05.190] <TB1> INFO: 17698250 events read in total (585947ms).
[13:59:27.679] <TB1> INFO: 18374700 events read in total (608436ms).
[13:59:49.871] <TB1> INFO: 19048900 events read in total (630628ms).
[14:00:12.384] <TB1> INFO: 19723100 events read in total (653141ms).
[14:00:34.571] <TB1> INFO: 20394150 events read in total (675328ms).
[14:00:57.211] <TB1> INFO: 21066500 events read in total (697968ms).
[14:01:19.515] <TB1> INFO: 21738050 events read in total (720272ms).
[14:01:41.741] <TB1> INFO: 22411450 events read in total (742498ms).
[14:02:04.143] <TB1> INFO: 23080300 events read in total (764900ms).
[14:02:26.558] <TB1> INFO: 23750650 events read in total (787315ms).
[14:02:48.877] <TB1> INFO: 24419750 events read in total (809634ms).
[14:03:11.257] <TB1> INFO: 25092400 events read in total (832014ms).
[14:03:33.618] <TB1> INFO: 25763400 events read in total (854375ms).
[14:03:55.896] <TB1> INFO: 26433900 events read in total (876653ms).
[14:04:18.178] <TB1> INFO: 27103050 events read in total (898935ms).
[14:04:40.424] <TB1> INFO: 27771500 events read in total (921181ms).
[14:05:02.904] <TB1> INFO: 28440500 events read in total (943661ms).
[14:05:25.181] <TB1> INFO: 29108200 events read in total (965938ms).
[14:05:47.507] <TB1> INFO: 29777200 events read in total (988264ms).
[14:06:09.837] <TB1> INFO: 30445100 events read in total (1010594ms).
[14:06:32.326] <TB1> INFO: 31114550 events read in total (1033083ms).
[14:06:54.582] <TB1> INFO: 31781850 events read in total (1055339ms).
[14:07:16.970] <TB1> INFO: 32451950 events read in total (1077727ms).
[14:07:39.347] <TB1> INFO: 33119800 events read in total (1100104ms).
[14:08:01.673] <TB1> INFO: 33791650 events read in total (1122430ms).
[14:08:24.020] <TB1> INFO: 34460000 events read in total (1144777ms).
[14:08:46.341] <TB1> INFO: 35132900 events read in total (1167098ms).
[14:09:08.542] <TB1> INFO: 35802650 events read in total (1189299ms).
[14:09:31.414] <TB1> INFO: 36486950 events read in total (1212171ms).
[14:09:35.877] <TB1> INFO: 36608000 events read in total (1216634ms).
[14:09:35.930] <TB1> INFO: Test took 1217515ms.
[14:09:36.356] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:09:38.123] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:09:39.855] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:09:41.878] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:09:43.944] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:09:45.969] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:09:47.940] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:09:49.859] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:09:51.619] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:09:53.732] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:09:55.772] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:09:57.581] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:09:59.545] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:10:01.159] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:10:02.946] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:10:04.577] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:10:06.543] <TB1> INFO: PixTestScurves::scurves() done
[14:10:06.543] <TB1> INFO: Vcal mean: 130.80 125.12 116.43 119.69 133.33 129.02 122.18 123.33 126.89 134.84 122.56 127.05 133.93 132.09 124.94 125.32
[14:10:06.543] <TB1> INFO: Vcal RMS: 6.35 5.96 5.64 6.02 6.24 6.74 6.26 6.30 6.87 6.42 5.96 6.26 7.59 6.91 6.26 6.30
[14:10:06.543] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1248 seconds
[14:10:06.543] <TB1> INFO: Decoding statistics:
[14:10:06.543] <TB1> INFO: General information:
[14:10:06.543] <TB1> INFO: 16bit words read: 0
[14:10:06.543] <TB1> INFO: valid events total: 0
[14:10:06.543] <TB1> INFO: empty events: 0
[14:10:06.543] <TB1> INFO: valid events with pixels: 0
[14:10:06.543] <TB1> INFO: valid pixel hits: 0
[14:10:06.543] <TB1> INFO: Event errors: 0
[14:10:06.543] <TB1> INFO: start marker: 0
[14:10:06.543] <TB1> INFO: stop marker: 0
[14:10:06.543] <TB1> INFO: overflow: 0
[14:10:06.543] <TB1> INFO: invalid 5bit words: 0
[14:10:06.543] <TB1> INFO: invalid XOR eye diagram: 0
[14:10:06.543] <TB1> INFO: frame (failed synchr.): 0
[14:10:06.543] <TB1> INFO: idle data (no TBM trl): 0
[14:10:06.543] <TB1> INFO: no data (only TBM hdr): 0
[14:10:06.543] <TB1> INFO: TBM errors: 0
[14:10:06.543] <TB1> INFO: flawed TBM headers: 0
[14:10:06.543] <TB1> INFO: flawed TBM trailers: 0
[14:10:06.543] <TB1> INFO: event ID mismatches: 0
[14:10:06.543] <TB1> INFO: ROC errors: 0
[14:10:06.543] <TB1> INFO: missing ROC header(s): 0
[14:10:06.543] <TB1> INFO: misplaced readback start: 0
[14:10:06.543] <TB1> INFO: Pixel decoding errors: 0
[14:10:06.543] <TB1> INFO: pixel data incomplete: 0
[14:10:06.543] <TB1> INFO: pixel address: 0
[14:10:06.543] <TB1> INFO: pulse height fill bit: 0
[14:10:06.543] <TB1> INFO: buffer corruption: 0
[14:10:06.613] <TB1> INFO: ######################################################################
[14:10:06.613] <TB1> INFO: PixTestTrim::doTest()
[14:10:06.613] <TB1> INFO: ######################################################################
[14:10:06.614] <TB1> INFO: ----------------------------------------------------------------------
[14:10:06.614] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[14:10:06.614] <TB1> INFO: ----------------------------------------------------------------------
[14:10:06.682] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:10:06.682] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:10:06.694] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:10:06.694] <TB1> INFO: run 1 of 1
[14:10:07.016] <TB1> INFO: Expecting 5025280 events.
[14:10:37.391] <TB1> INFO: 832808 events read in total (29782ms).
[14:11:07.014] <TB1> INFO: 1663392 events read in total (59405ms).
[14:11:36.559] <TB1> INFO: 2491400 events read in total (88950ms).
[14:12:06.664] <TB1> INFO: 3315032 events read in total (119055ms).
[14:12:36.024] <TB1> INFO: 4135168 events read in total (148416ms).
[14:13:05.775] <TB1> INFO: 4953648 events read in total (178166ms).
[14:13:08.898] <TB1> INFO: 5025280 events read in total (181289ms).
[14:13:08.941] <TB1> INFO: Test took 182247ms.
[14:13:26.773] <TB1> INFO: ROC 0 VthrComp = 129
[14:13:26.773] <TB1> INFO: ROC 1 VthrComp = 133
[14:13:26.774] <TB1> INFO: ROC 2 VthrComp = 118
[14:13:26.774] <TB1> INFO: ROC 3 VthrComp = 121
[14:13:26.774] <TB1> INFO: ROC 4 VthrComp = 130
[14:13:26.774] <TB1> INFO: ROC 5 VthrComp = 129
[14:13:26.774] <TB1> INFO: ROC 6 VthrComp = 124
[14:13:26.774] <TB1> INFO: ROC 7 VthrComp = 131
[14:13:26.774] <TB1> INFO: ROC 8 VthrComp = 114
[14:13:26.774] <TB1> INFO: ROC 9 VthrComp = 130
[14:13:26.775] <TB1> INFO: ROC 10 VthrComp = 132
[14:13:26.775] <TB1> INFO: ROC 11 VthrComp = 129
[14:13:26.775] <TB1> INFO: ROC 12 VthrComp = 132
[14:13:26.775] <TB1> INFO: ROC 13 VthrComp = 124
[14:13:26.775] <TB1> INFO: ROC 14 VthrComp = 127
[14:13:26.779] <TB1> INFO: ROC 15 VthrComp = 129
[14:13:27.014] <TB1> INFO: Expecting 41600 events.
[14:13:30.621] <TB1> INFO: 41600 events read in total (3015ms).
[14:13:30.622] <TB1> INFO: Test took 3842ms.
[14:13:30.632] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:13:30.632] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:13:30.642] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:13:30.642] <TB1> INFO: run 1 of 1
[14:13:30.920] <TB1> INFO: Expecting 5025280 events.
[14:13:56.811] <TB1> INFO: 591408 events read in total (25299ms).
[14:14:22.190] <TB1> INFO: 1181040 events read in total (50678ms).
[14:14:47.475] <TB1> INFO: 1770432 events read in total (75963ms).
[14:15:13.166] <TB1> INFO: 2359448 events read in total (101654ms).
[14:15:38.438] <TB1> INFO: 2946192 events read in total (126926ms).
[14:16:03.617] <TB1> INFO: 3531944 events read in total (152105ms).
[14:16:28.577] <TB1> INFO: 4117000 events read in total (177065ms).
[14:16:53.770] <TB1> INFO: 4701168 events read in total (202258ms).
[14:17:08.038] <TB1> INFO: 5025280 events read in total (216526ms).
[14:17:08.094] <TB1> INFO: Test took 217452ms.
[14:17:35.101] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 59.923 for pixel 13/10 mean/min/max = 45.8687/31.5996/60.1378
[14:17:35.102] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 58.7474 for pixel 5/44 mean/min/max = 45.891/33.0286/58.7534
[14:17:35.102] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 59.9814 for pixel 0/0 mean/min/max = 46.0066/31.9836/60.0295
[14:17:35.103] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 60.7581 for pixel 33/5 mean/min/max = 46.858/32.924/60.7921
[14:17:35.103] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 62.501 for pixel 0/44 mean/min/max = 47.6606/32.7287/62.5925
[14:17:35.103] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 59.6712 for pixel 0/27 mean/min/max = 45.801/31.8391/59.763
[14:17:35.104] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 57.5892 for pixel 5/4 mean/min/max = 45.4028/33.1306/57.6749
[14:17:35.104] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 58.3511 for pixel 1/72 mean/min/max = 45.4354/32.3294/58.5414
[14:17:35.105] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 65.858 for pixel 3/8 mean/min/max = 48.8571/31.8268/65.8874
[14:17:35.105] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 64.517 for pixel 4/3 mean/min/max = 49.1854/33.7955/64.5752
[14:17:35.105] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 57.8608 for pixel 3/2 mean/min/max = 45.0415/32.1315/57.9515
[14:17:35.106] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 62.1631 for pixel 12/12 mean/min/max = 47.6371/32.7078/62.5664
[14:17:35.106] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 70.2008 for pixel 13/11 mean/min/max = 52.4779/34.4713/70.4844
[14:17:35.106] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 62.79 for pixel 0/18 mean/min/max = 48.151/33.4043/62.8978
[14:17:35.107] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 60.3112 for pixel 16/1 mean/min/max = 46.1865/32.0437/60.3294
[14:17:35.107] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 61.2633 for pixel 37/4 mean/min/max = 46.6172/31.6281/61.6063
[14:17:35.108] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:17:35.196] <TB1> INFO: Expecting 411648 events.
[14:17:44.513] <TB1> INFO: 411648 events read in total (8725ms).
[14:17:44.520] <TB1> INFO: Expecting 411648 events.
[14:17:53.638] <TB1> INFO: 411648 events read in total (8715ms).
[14:17:53.649] <TB1> INFO: Expecting 411648 events.
[14:18:02.650] <TB1> INFO: 411648 events read in total (8598ms).
[14:18:02.661] <TB1> INFO: Expecting 411648 events.
[14:18:11.700] <TB1> INFO: 411648 events read in total (8636ms).
[14:18:11.716] <TB1> INFO: Expecting 411648 events.
[14:18:20.732] <TB1> INFO: 411648 events read in total (8613ms).
[14:18:20.747] <TB1> INFO: Expecting 411648 events.
[14:18:29.822] <TB1> INFO: 411648 events read in total (8672ms).
[14:18:29.840] <TB1> INFO: Expecting 411648 events.
[14:18:38.879] <TB1> INFO: 411648 events read in total (8636ms).
[14:18:38.899] <TB1> INFO: Expecting 411648 events.
[14:18:47.874] <TB1> INFO: 411648 events read in total (8572ms).
[14:18:47.905] <TB1> INFO: Expecting 411648 events.
[14:18:56.933] <TB1> INFO: 411648 events read in total (8625ms).
[14:18:56.959] <TB1> INFO: Expecting 411648 events.
[14:19:05.966] <TB1> INFO: 411648 events read in total (8604ms).
[14:19:05.001] <TB1> INFO: Expecting 411648 events.
[14:19:15.066] <TB1> INFO: 411648 events read in total (8662ms).
[14:19:15.098] <TB1> INFO: Expecting 411648 events.
[14:19:24.174] <TB1> INFO: 411648 events read in total (8673ms).
[14:19:24.208] <TB1> INFO: Expecting 411648 events.
[14:19:33.289] <TB1> INFO: 411648 events read in total (8678ms).
[14:19:33.326] <TB1> INFO: Expecting 411648 events.
[14:19:42.380] <TB1> INFO: 411648 events read in total (8651ms).
[14:19:42.419] <TB1> INFO: Expecting 411648 events.
[14:19:51.538] <TB1> INFO: 411648 events read in total (8717ms).
[14:19:51.584] <TB1> INFO: Expecting 411648 events.
[14:20:00.697] <TB1> INFO: 411648 events read in total (8710ms).
[14:20:00.742] <TB1> INFO: Test took 145634ms.
[14:20:01.395] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:20:01.407] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:20:01.407] <TB1> INFO: run 1 of 1
[14:20:01.647] <TB1> INFO: Expecting 5025280 events.
[14:20:27.551] <TB1> INFO: 590184 events read in total (25312ms).
[14:20:52.977] <TB1> INFO: 1179768 events read in total (50738ms).
[14:21:18.638] <TB1> INFO: 1768152 events read in total (76399ms).
[14:21:44.236] <TB1> INFO: 2356296 events read in total (101997ms).
[14:22:09.851] <TB1> INFO: 2944208 events read in total (127613ms).
[14:22:35.563] <TB1> INFO: 3536120 events read in total (153324ms).
[14:23:01.120] <TB1> INFO: 4125736 events read in total (178881ms).
[14:23:26.988] <TB1> INFO: 4715176 events read in total (204749ms).
[14:23:40.864] <TB1> INFO: 5025280 events read in total (218625ms).
[14:23:40.996] <TB1> INFO: Test took 219589ms.
[14:24:04.172] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 5.468981 .. 146.976342
[14:24:04.409] <TB1> INFO: Expecting 208000 events.
[14:24:13.883] <TB1> INFO: 208000 events read in total (8883ms).
[14:24:13.885] <TB1> INFO: Test took 9712ms.
[14:24:13.944] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 5 .. 156 (-1/-1) hits flags = 528 (plus default)
[14:24:13.956] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:24:13.956] <TB1> INFO: run 1 of 1
[14:24:14.245] <TB1> INFO: Expecting 5058560 events.
[14:24:40.163] <TB1> INFO: 579816 events read in total (25326ms).
[14:25:05.292] <TB1> INFO: 1159632 events read in total (50456ms).
[14:25:30.814] <TB1> INFO: 1739216 events read in total (75978ms).
[14:25:56.158] <TB1> INFO: 2318888 events read in total (101321ms).
[14:26:21.798] <TB1> INFO: 2898224 events read in total (126961ms).
[14:26:47.235] <TB1> INFO: 3476872 events read in total (152399ms).
[14:27:12.151] <TB1> INFO: 4055032 events read in total (177314ms).
[14:27:37.470] <TB1> INFO: 4633072 events read in total (202633ms).
[14:27:56.166] <TB1> INFO: 5058560 events read in total (221329ms).
[14:27:56.244] <TB1> INFO: Test took 222288ms.
[14:28:24.501] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 26.711624 .. 46.927136
[14:28:24.738] <TB1> INFO: Expecting 208000 events.
[14:28:34.428] <TB1> INFO: 208000 events read in total (9098ms).
[14:28:34.430] <TB1> INFO: Test took 9927ms.
[14:28:34.484] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 56 (-1/-1) hits flags = 528 (plus default)
[14:28:34.492] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:28:34.492] <TB1> INFO: run 1 of 1
[14:28:34.770] <TB1> INFO: Expecting 1364480 events.
[14:29:02.331] <TB1> INFO: 661856 events read in total (26969ms).
[14:29:29.533] <TB1> INFO: 1321440 events read in total (54172ms).
[14:29:31.739] <TB1> INFO: 1364480 events read in total (56377ms).
[14:29:31.774] <TB1> INFO: Test took 57282ms.
[14:29:46.367] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 27.782623 .. 49.258879
[14:29:46.601] <TB1> INFO: Expecting 208000 events.
[14:29:56.171] <TB1> INFO: 208000 events read in total (8978ms).
[14:29:56.172] <TB1> INFO: Test took 9803ms.
[14:29:56.221] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 59 (-1/-1) hits flags = 528 (plus default)
[14:29:56.231] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:29:56.231] <TB1> INFO: run 1 of 1
[14:29:56.509] <TB1> INFO: Expecting 1431040 events.
[14:30:24.061] <TB1> INFO: 646368 events read in total (26961ms).
[14:30:51.128] <TB1> INFO: 1290968 events read in total (54028ms).
[14:30:58.074] <TB1> INFO: 1431040 events read in total (60975ms).
[14:30:58.102] <TB1> INFO: Test took 61872ms.
[14:31:12.982] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 25.394834 .. 52.639577
[14:31:13.243] <TB1> INFO: Expecting 208000 events.
[14:31:23.076] <TB1> INFO: 208000 events read in total (9242ms).
[14:31:23.077] <TB1> INFO: Test took 10093ms.
[14:31:23.124] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 62 (-1/-1) hits flags = 528 (plus default)
[14:31:23.132] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:31:23.132] <TB1> INFO: run 1 of 1
[14:31:23.414] <TB1> INFO: Expecting 1597440 events.
[14:31:50.837] <TB1> INFO: 643808 events read in total (26831ms).
[14:32:17.691] <TB1> INFO: 1287776 events read in total (53685ms).
[14:32:31.335] <TB1> INFO: 1597440 events read in total (67329ms).
[14:32:31.370] <TB1> INFO: Test took 68239ms.
[14:32:46.366] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:32:46.366] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:32:46.377] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:32:46.377] <TB1> INFO: run 1 of 1
[14:32:46.652] <TB1> INFO: Expecting 1364480 events.
[14:33:14.515] <TB1> INFO: 668856 events read in total (27272ms).
[14:33:42.363] <TB1> INFO: 1336656 events read in total (55120ms).
[14:33:43.982] <TB1> INFO: 1364480 events read in total (56740ms).
[14:33:44.014] <TB1> INFO: Test took 57636ms.
[14:33:56.831] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C0.dat
[14:33:56.831] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C1.dat
[14:33:56.831] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C2.dat
[14:33:56.831] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C3.dat
[14:33:56.831] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C4.dat
[14:33:56.832] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C5.dat
[14:33:56.832] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C6.dat
[14:33:56.832] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C7.dat
[14:33:56.832] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C8.dat
[14:33:56.832] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C9.dat
[14:33:56.832] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C10.dat
[14:33:56.832] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C11.dat
[14:33:56.832] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C12.dat
[14:33:56.832] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C13.dat
[14:33:56.832] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C14.dat
[14:33:56.832] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C15.dat
[14:33:56.832] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C0.dat
[14:33:56.839] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C1.dat
[14:33:56.845] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C2.dat
[14:33:56.850] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C3.dat
[14:33:56.856] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C4.dat
[14:33:56.862] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C5.dat
[14:33:56.868] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C6.dat
[14:33:56.874] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C7.dat
[14:33:56.880] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C8.dat
[14:33:56.886] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C9.dat
[14:33:56.892] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C10.dat
[14:33:56.897] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C11.dat
[14:33:56.903] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C12.dat
[14:33:56.909] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C13.dat
[14:33:56.915] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C14.dat
[14:33:56.920] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters35_C15.dat
[14:33:56.926] <TB1> INFO: PixTestTrim::trimTest() done
[14:33:56.926] <TB1> INFO: vtrim: 129 130 127 132 142 137 121 141 123 149 125 128 171 141 143 156
[14:33:56.926] <TB1> INFO: vthrcomp: 129 133 118 121 130 129 124 131 114 130 132 129 132 124 127 129
[14:33:56.926] <TB1> INFO: vcal mean: 35.07 34.96 35.06 34.97 35.24 34.93 35.00 34.99 35.88 36.13 34.96 35.44 35.37 35.30 35.04 35.26
[14:33:56.926] <TB1> INFO: vcal RMS: 1.36 1.04 1.18 1.10 1.38 1.17 1.07 1.03 2.15 2.35 1.01 1.57 1.64 1.39 1.16 1.43
[14:33:56.926] <TB1> INFO: bits mean: 10.05 9.68 10.16 9.73 9.59 9.85 9.94 10.02 9.56 9.73 9.98 9.23 8.91 9.64 10.06 10.59
[14:33:56.926] <TB1> INFO: bits RMS: 2.57 2.54 2.42 2.44 2.54 2.59 2.45 2.45 2.72 2.47 2.51 2.76 2.40 2.41 2.44 2.27
[14:33:56.933] <TB1> INFO: ----------------------------------------------------------------------
[14:33:56.933] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:33:56.933] <TB1> INFO: ----------------------------------------------------------------------
[14:33:56.935] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:33:56.948] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:33:56.948] <TB1> INFO: run 1 of 1
[14:33:57.207] <TB1> INFO: Expecting 4160000 events.
[14:34:29.338] <TB1> INFO: 773640 events read in total (31539ms).
[14:35:00.704] <TB1> INFO: 1539895 events read in total (62905ms).
[14:35:31.873] <TB1> INFO: 2300970 events read in total (94074ms).
[14:36:02.972] <TB1> INFO: 3056780 events read in total (125173ms).
[14:36:34.020] <TB1> INFO: 3808995 events read in total (156221ms).
[14:36:48.941] <TB1> INFO: 4160000 events read in total (171142ms).
[14:36:48.988] <TB1> INFO: Test took 172040ms.
[14:37:17.580] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[14:37:17.592] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:37:17.592] <TB1> INFO: run 1 of 1
[14:37:17.880] <TB1> INFO: Expecting 5324800 events.
[14:37:47.002] <TB1> INFO: 686525 events read in total (29530ms).
[14:38:17.706] <TB1> INFO: 1369525 events read in total (59234ms).
[14:38:47.531] <TB1> INFO: 2051170 events read in total (89059ms).
[14:39:17.267] <TB1> INFO: 2730210 events read in total (118795ms).
[14:39:46.901] <TB1> INFO: 3406925 events read in total (148429ms).
[14:40:16.379] <TB1> INFO: 4081885 events read in total (177907ms).
[14:40:46.238] <TB1> INFO: 4755655 events read in total (207766ms).
[14:41:12.395] <TB1> INFO: 5324800 events read in total (233923ms).
[14:41:12.505] <TB1> INFO: Test took 234913ms.
[14:41:49.710] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 230 (-1/-1) hits flags = 528 (plus default)
[14:41:49.720] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:41:49.720] <TB1> INFO: run 1 of 1
[14:41:49.951] <TB1> INFO: Expecting 4804800 events.
[14:42:20.720] <TB1> INFO: 708610 events read in total (30177ms).
[14:42:50.762] <TB1> INFO: 1413260 events read in total (60219ms).
[14:43:21.269] <TB1> INFO: 2115285 events read in total (90726ms).
[14:43:51.550] <TB1> INFO: 2814480 events read in total (121007ms).
[14:44:21.579] <TB1> INFO: 3510890 events read in total (151036ms).
[14:44:52.232] <TB1> INFO: 4204550 events read in total (181689ms).
[14:45:18.395] <TB1> INFO: 4804800 events read in total (207852ms).
[14:45:18.480] <TB1> INFO: Test took 208761ms.
[14:45:49.253] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 220 (-1/-1) hits flags = 528 (plus default)
[14:45:49.262] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:45:49.262] <TB1> INFO: run 1 of 1
[14:45:49.507] <TB1> INFO: Expecting 4596800 events.
[14:46:20.718] <TB1> INFO: 719345 events read in total (30619ms).
[14:46:51.046] <TB1> INFO: 1434510 events read in total (60947ms).
[14:47:21.305] <TB1> INFO: 2146790 events read in total (91206ms).
[14:47:51.562] <TB1> INFO: 2855410 events read in total (121464ms).
[14:48:22.199] <TB1> INFO: 3560675 events read in total (152100ms).
[14:48:52.235] <TB1> INFO: 4264920 events read in total (182136ms).
[14:49:06.558] <TB1> INFO: 4596800 events read in total (196459ms).
[14:49:06.633] <TB1> INFO: Test took 197371ms.
[14:49:38.662] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 219 (-1/-1) hits flags = 528 (plus default)
[14:49:38.672] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:49:38.672] <TB1> INFO: run 1 of 1
[14:49:38.912] <TB1> INFO: Expecting 4576000 events.
[14:50:10.168] <TB1> INFO: 720490 events read in total (30665ms).
[14:50:40.716] <TB1> INFO: 1436650 events read in total (61213ms).
[14:51:11.056] <TB1> INFO: 2150235 events read in total (91553ms).
[14:51:41.445] <TB1> INFO: 2859770 events read in total (121942ms).
[14:52:12.303] <TB1> INFO: 3565995 events read in total (152800ms).
[14:52:43.118] <TB1> INFO: 4271360 events read in total (183615ms).
[14:52:56.312] <TB1> INFO: 4576000 events read in total (196809ms).
[14:52:56.370] <TB1> INFO: Test took 197698ms.
[14:53:26.334] <TB1> INFO: PixTestTrim::trimBitTest() done
[14:53:26.336] <TB1> INFO: PixTestTrim::doTest() done, duration: 2599 seconds
[14:53:26.336] <TB1> INFO: Decoding statistics:
[14:53:26.336] <TB1> INFO: General information:
[14:53:26.336] <TB1> INFO: 16bit words read: 0
[14:53:26.336] <TB1> INFO: valid events total: 0
[14:53:26.336] <TB1> INFO: empty events: 0
[14:53:26.336] <TB1> INFO: valid events with pixels: 0
[14:53:26.336] <TB1> INFO: valid pixel hits: 0
[14:53:26.336] <TB1> INFO: Event errors: 0
[14:53:26.336] <TB1> INFO: start marker: 0
[14:53:26.336] <TB1> INFO: stop marker: 0
[14:53:26.336] <TB1> INFO: overflow: 0
[14:53:26.336] <TB1> INFO: invalid 5bit words: 0
[14:53:26.336] <TB1> INFO: invalid XOR eye diagram: 0
[14:53:26.336] <TB1> INFO: frame (failed synchr.): 0
[14:53:26.336] <TB1> INFO: idle data (no TBM trl): 0
[14:53:26.336] <TB1> INFO: no data (only TBM hdr): 0
[14:53:26.336] <TB1> INFO: TBM errors: 0
[14:53:26.336] <TB1> INFO: flawed TBM headers: 0
[14:53:26.336] <TB1> INFO: flawed TBM trailers: 0
[14:53:26.336] <TB1> INFO: event ID mismatches: 0
[14:53:26.336] <TB1> INFO: ROC errors: 0
[14:53:26.336] <TB1> INFO: missing ROC header(s): 0
[14:53:26.336] <TB1> INFO: misplaced readback start: 0
[14:53:26.336] <TB1> INFO: Pixel decoding errors: 0
[14:53:26.336] <TB1> INFO: pixel data incomplete: 0
[14:53:26.336] <TB1> INFO: pixel address: 0
[14:53:26.336] <TB1> INFO: pulse height fill bit: 0
[14:53:26.336] <TB1> INFO: buffer corruption: 0
[14:53:26.997] <TB1> INFO: ######################################################################
[14:53:26.997] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[14:53:26.997] <TB1> INFO: ######################################################################
[14:53:27.268] <TB1> INFO: Expecting 41600 events.
[14:53:30.751] <TB1> INFO: 41600 events read in total (2891ms).
[14:53:30.752] <TB1> INFO: Test took 3753ms.
[14:53:31.188] <TB1> INFO: Expecting 41600 events.
[14:53:34.658] <TB1> INFO: 41600 events read in total (2878ms).
[14:53:34.659] <TB1> INFO: Test took 3703ms.
[14:53:34.957] <TB1> INFO: Expecting 41600 events.
[14:53:38.531] <TB1> INFO: 41600 events read in total (2983ms).
[14:53:38.532] <TB1> INFO: Test took 3849ms.
[14:53:38.822] <TB1> INFO: Expecting 41600 events.
[14:53:42.394] <TB1> INFO: 41600 events read in total (2980ms).
[14:53:42.394] <TB1> INFO: Test took 3837ms.
[14:53:42.687] <TB1> INFO: Expecting 41600 events.
[14:53:46.247] <TB1> INFO: 41600 events read in total (2968ms).
[14:53:46.248] <TB1> INFO: Test took 3826ms.
[14:53:46.536] <TB1> INFO: Expecting 41600 events.
[14:53:50.118] <TB1> INFO: 41600 events read in total (2990ms).
[14:53:50.119] <TB1> INFO: Test took 3847ms.
[14:53:50.409] <TB1> INFO: Expecting 41600 events.
[14:53:53.906] <TB1> INFO: 41600 events read in total (2906ms).
[14:53:53.908] <TB1> INFO: Test took 3764ms.
[14:53:54.196] <TB1> INFO: Expecting 41600 events.
[14:53:57.685] <TB1> INFO: 41600 events read in total (2898ms).
[14:53:57.686] <TB1> INFO: Test took 3755ms.
[14:53:57.975] <TB1> INFO: Expecting 41600 events.
[14:54:01.543] <TB1> INFO: 41600 events read in total (2976ms).
[14:54:01.545] <TB1> INFO: Test took 3835ms.
[14:54:01.834] <TB1> INFO: Expecting 41600 events.
[14:54:05.405] <TB1> INFO: 41600 events read in total (2979ms).
[14:54:05.406] <TB1> INFO: Test took 3836ms.
[14:54:05.694] <TB1> INFO: Expecting 41600 events.
[14:54:09.259] <TB1> INFO: 41600 events read in total (2973ms).
[14:54:09.260] <TB1> INFO: Test took 3831ms.
[14:54:09.554] <TB1> INFO: Expecting 41600 events.
[14:54:13.039] <TB1> INFO: 41600 events read in total (2893ms).
[14:54:13.040] <TB1> INFO: Test took 3754ms.
[14:54:13.328] <TB1> INFO: Expecting 41600 events.
[14:54:16.807] <TB1> INFO: 41600 events read in total (2887ms).
[14:54:16.808] <TB1> INFO: Test took 3745ms.
[14:54:17.098] <TB1> INFO: Expecting 41600 events.
[14:54:20.595] <TB1> INFO: 41600 events read in total (2905ms).
[14:54:20.596] <TB1> INFO: Test took 3762ms.
[14:54:20.885] <TB1> INFO: Expecting 41600 events.
[14:54:24.337] <TB1> INFO: 41600 events read in total (2861ms).
[14:54:24.337] <TB1> INFO: Test took 3717ms.
[14:54:24.625] <TB1> INFO: Expecting 41600 events.
[14:54:28.094] <TB1> INFO: 41600 events read in total (2877ms).
[14:54:28.095] <TB1> INFO: Test took 3734ms.
[14:54:28.383] <TB1> INFO: Expecting 41600 events.
[14:54:31.853] <TB1> INFO: 41600 events read in total (2878ms).
[14:54:31.853] <TB1> INFO: Test took 3735ms.
[14:54:32.141] <TB1> INFO: Expecting 41600 events.
[14:54:35.658] <TB1> INFO: 41600 events read in total (2925ms).
[14:54:35.659] <TB1> INFO: Test took 3782ms.
[14:54:35.947] <TB1> INFO: Expecting 41600 events.
[14:54:39.443] <TB1> INFO: 41600 events read in total (2904ms).
[14:54:39.444] <TB1> INFO: Test took 3761ms.
[14:54:39.732] <TB1> INFO: Expecting 41600 events.
[14:54:43.252] <TB1> INFO: 41600 events read in total (2929ms).
[14:54:43.253] <TB1> INFO: Test took 3786ms.
[14:54:43.541] <TB1> INFO: Expecting 41600 events.
[14:54:47.013] <TB1> INFO: 41600 events read in total (2880ms).
[14:54:47.014] <TB1> INFO: Test took 3738ms.
[14:54:47.304] <TB1> INFO: Expecting 41600 events.
[14:54:50.820] <TB1> INFO: 41600 events read in total (2924ms).
[14:54:50.821] <TB1> INFO: Test took 3781ms.
[14:54:51.109] <TB1> INFO: Expecting 41600 events.
[14:54:54.622] <TB1> INFO: 41600 events read in total (2921ms).
[14:54:54.623] <TB1> INFO: Test took 3779ms.
[14:54:54.914] <TB1> INFO: Expecting 41600 events.
[14:54:58.615] <TB1> INFO: 41600 events read in total (3109ms).
[14:54:58.616] <TB1> INFO: Test took 3966ms.
[14:54:58.907] <TB1> INFO: Expecting 41600 events.
[14:55:02.543] <TB1> INFO: 41600 events read in total (3044ms).
[14:55:02.544] <TB1> INFO: Test took 3905ms.
[14:55:02.837] <TB1> INFO: Expecting 41600 events.
[14:55:06.294] <TB1> INFO: 41600 events read in total (2866ms).
[14:55:06.295] <TB1> INFO: Test took 3725ms.
[14:55:06.586] <TB1> INFO: Expecting 41600 events.
[14:55:10.093] <TB1> INFO: 41600 events read in total (2916ms).
[14:55:10.094] <TB1> INFO: Test took 3773ms.
[14:55:10.396] <TB1> INFO: Expecting 41600 events.
[14:55:13.873] <TB1> INFO: 41600 events read in total (2886ms).
[14:55:13.874] <TB1> INFO: Test took 3755ms.
[14:55:14.166] <TB1> INFO: Expecting 2560 events.
[14:55:15.048] <TB1> INFO: 2560 events read in total (291ms).
[14:55:15.048] <TB1> INFO: Test took 1159ms.
[14:55:15.356] <TB1> INFO: Expecting 2560 events.
[14:55:16.247] <TB1> INFO: 2560 events read in total (299ms).
[14:55:16.247] <TB1> INFO: Test took 1198ms.
[14:55:16.555] <TB1> INFO: Expecting 2560 events.
[14:55:17.441] <TB1> INFO: 2560 events read in total (294ms).
[14:55:17.441] <TB1> INFO: Test took 1193ms.
[14:55:17.749] <TB1> INFO: Expecting 2560 events.
[14:55:18.632] <TB1> INFO: 2560 events read in total (291ms).
[14:55:18.632] <TB1> INFO: Test took 1190ms.
[14:55:18.940] <TB1> INFO: Expecting 2560 events.
[14:55:19.826] <TB1> INFO: 2560 events read in total (289ms).
[14:55:19.826] <TB1> INFO: Test took 1193ms.
[14:55:20.135] <TB1> INFO: Expecting 2560 events.
[14:55:21.013] <TB1> INFO: 2560 events read in total (287ms).
[14:55:21.013] <TB1> INFO: Test took 1186ms.
[14:55:21.321] <TB1> INFO: Expecting 2560 events.
[14:55:22.201] <TB1> INFO: 2560 events read in total (288ms).
[14:55:22.201] <TB1> INFO: Test took 1187ms.
[14:55:22.509] <TB1> INFO: Expecting 2560 events.
[14:55:23.389] <TB1> INFO: 2560 events read in total (288ms).
[14:55:23.389] <TB1> INFO: Test took 1187ms.
[14:55:23.697] <TB1> INFO: Expecting 2560 events.
[14:55:24.576] <TB1> INFO: 2560 events read in total (287ms).
[14:55:24.577] <TB1> INFO: Test took 1187ms.
[14:55:24.884] <TB1> INFO: Expecting 2560 events.
[14:55:25.763] <TB1> INFO: 2560 events read in total (287ms).
[14:55:25.763] <TB1> INFO: Test took 1186ms.
[14:55:26.071] <TB1> INFO: Expecting 2560 events.
[14:55:26.948] <TB1> INFO: 2560 events read in total (286ms).
[14:55:26.949] <TB1> INFO: Test took 1186ms.
[14:55:27.257] <TB1> INFO: Expecting 2560 events.
[14:55:28.135] <TB1> INFO: 2560 events read in total (287ms).
[14:55:28.136] <TB1> INFO: Test took 1187ms.
[14:55:28.444] <TB1> INFO: Expecting 2560 events.
[14:55:29.326] <TB1> INFO: 2560 events read in total (291ms).
[14:55:29.327] <TB1> INFO: Test took 1191ms.
[14:55:29.635] <TB1> INFO: Expecting 2560 events.
[14:55:30.521] <TB1> INFO: 2560 events read in total (295ms).
[14:55:30.521] <TB1> INFO: Test took 1194ms.
[14:55:30.829] <TB1> INFO: Expecting 2560 events.
[14:55:31.715] <TB1> INFO: 2560 events read in total (295ms).
[14:55:31.716] <TB1> INFO: Test took 1194ms.
[14:55:32.023] <TB1> INFO: Expecting 2560 events.
[14:55:32.909] <TB1> INFO: 2560 events read in total (294ms).
[14:55:32.909] <TB1> INFO: Test took 1193ms.
[14:55:32.912] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:55:33.218] <TB1> INFO: Expecting 655360 events.
[14:55:47.650] <TB1> INFO: 655360 events read in total (13841ms).
[14:55:47.661] <TB1> INFO: Expecting 655360 events.
[14:56:01.727] <TB1> INFO: 655360 events read in total (13663ms).
[14:56:01.742] <TB1> INFO: Expecting 655360 events.
[14:56:15.739] <TB1> INFO: 655360 events read in total (13594ms).
[14:56:15.764] <TB1> INFO: Expecting 655360 events.
[14:56:29.759] <TB1> INFO: 655360 events read in total (13592ms).
[14:56:29.783] <TB1> INFO: Expecting 655360 events.
[14:56:43.928] <TB1> INFO: 655360 events read in total (13743ms).
[14:56:43.963] <TB1> INFO: Expecting 655360 events.
[14:56:57.978] <TB1> INFO: 655360 events read in total (13612ms).
[14:56:58.022] <TB1> INFO: Expecting 655360 events.
[14:57:12.018] <TB1> INFO: 655360 events read in total (13593ms).
[14:57:12.052] <TB1> INFO: Expecting 655360 events.
[14:57:26.088] <TB1> INFO: 655360 events read in total (13633ms).
[14:57:26.129] <TB1> INFO: Expecting 655360 events.
[14:57:40.236] <TB1> INFO: 655360 events read in total (13704ms).
[14:57:40.279] <TB1> INFO: Expecting 655360 events.
[14:57:54.382] <TB1> INFO: 655360 events read in total (13693ms).
[14:57:54.432] <TB1> INFO: Expecting 655360 events.
[14:58:08.456] <TB1> INFO: 655360 events read in total (13621ms).
[14:58:08.506] <TB1> INFO: Expecting 655360 events.
[14:58:22.520] <TB1> INFO: 655360 events read in total (13611ms).
[14:58:22.597] <TB1> INFO: Expecting 655360 events.
[14:58:36.643] <TB1> INFO: 655360 events read in total (13643ms).
[14:58:36.725] <TB1> INFO: Expecting 655360 events.
[14:58:50.768] <TB1> INFO: 655360 events read in total (13640ms).
[14:58:50.838] <TB1> INFO: Expecting 655360 events.
[14:59:04.916] <TB1> INFO: 655360 events read in total (13676ms).
[14:59:04.988] <TB1> INFO: Expecting 655360 events.
[14:59:19.064] <TB1> INFO: 655360 events read in total (13673ms).
[14:59:19.163] <TB1> INFO: Test took 226251ms.
[14:59:19.247] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:59:19.512] <TB1> INFO: Expecting 655360 events.
[14:59:33.515] <TB1> INFO: 655360 events read in total (13412ms).
[14:59:33.525] <TB1> INFO: Expecting 655360 events.
[14:59:47.210] <TB1> INFO: 655360 events read in total (13282ms).
[14:59:47.229] <TB1> INFO: Expecting 655360 events.
[15:00:01.270] <TB1> INFO: 655360 events read in total (13638ms).
[15:00:01.288] <TB1> INFO: Expecting 655360 events.
[15:00:14.982] <TB1> INFO: 655360 events read in total (13291ms).
[15:00:15.006] <TB1> INFO: Expecting 655360 events.
[15:00:28.921] <TB1> INFO: 655360 events read in total (13512ms).
[15:00:28.947] <TB1> INFO: Expecting 655360 events.
[15:00:42.844] <TB1> INFO: 655360 events read in total (13494ms).
[15:00:42.884] <TB1> INFO: Expecting 655360 events.
[15:00:56.616] <TB1> INFO: 655360 events read in total (13329ms).
[15:00:56.662] <TB1> INFO: Expecting 655360 events.
[15:01:10.426] <TB1> INFO: 655360 events read in total (13361ms).
[15:01:10.486] <TB1> INFO: Expecting 655360 events.
[15:01:24.229] <TB1> INFO: 655360 events read in total (13340ms).
[15:01:24.271] <TB1> INFO: Expecting 655360 events.
[15:01:38.014] <TB1> INFO: 655360 events read in total (13340ms).
[15:01:38.062] <TB1> INFO: Expecting 655360 events.
[15:01:51.999] <TB1> INFO: 655360 events read in total (13534ms).
[15:01:52.065] <TB1> INFO: Expecting 655360 events.
[15:02:06.090] <TB1> INFO: 655360 events read in total (13622ms).
[15:02:06.149] <TB1> INFO: Expecting 655360 events.
[15:02:20.216] <TB1> INFO: 655360 events read in total (13664ms).
[15:02:20.277] <TB1> INFO: Expecting 655360 events.
[15:02:34.253] <TB1> INFO: 655360 events read in total (13573ms).
[15:02:34.342] <TB1> INFO: Expecting 655360 events.
[15:02:48.405] <TB1> INFO: 655360 events read in total (13660ms).
[15:02:48.501] <TB1> INFO: Expecting 655360 events.
[15:03:02.111] <TB1> INFO: 655360 events read in total (13207ms).
[15:03:02.181] <TB1> INFO: Test took 222934ms.
[15:03:02.338] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:02.342] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:02.347] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:03:02.352] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:03:02.356] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[15:03:02.361] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[15:03:02.365] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[15:03:02.370] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[15:03:02.375] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[15:03:02.379] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[15:03:02.384] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[15:03:02.389] <TB1> INFO: safety margin for low PH: adding 10, margin is now 30
[15:03:02.394] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:02.399] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:02.404] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:02.408] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:03:02.413] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:03:02.419] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[15:03:02.423] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[15:03:02.428] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[15:03:02.433] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[15:03:02.438] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[15:03:02.443] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:02.448] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:02.453] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:02.458] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:03:02.463] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:03:02.468] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[15:03:02.473] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[15:03:02.477] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[15:03:02.483] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[15:03:02.489] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[15:03:02.494] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[15:03:02.499] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:02.504] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:02.509] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:02.514] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:03:02.519] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:03:02.524] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:02.529] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:02.534] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:03:02.540] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:03:02.545] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[15:03:02.550] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[15:03:02.556] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[15:03:02.562] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[15:03:02.568] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[15:03:02.573] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[15:03:02.578] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[15:03:02.583] <TB1> INFO: safety margin for low PH: adding 10, margin is now 30
[15:03:02.588] <TB1> INFO: safety margin for low PH: adding 11, margin is now 31
[15:03:02.593] <TB1> INFO: safety margin for low PH: adding 12, margin is now 32
[15:03:02.598] <TB1> INFO: safety margin for low PH: adding 13, margin is now 33
[15:03:02.603] <TB1> INFO: safety margin for low PH: adding 14, margin is now 34
[15:03:02.607] <TB1> INFO: safety margin for low PH: adding 15, margin is now 35
[15:03:02.612] <TB1> INFO: safety margin for low PH: adding 16, margin is now 36
[15:03:02.617] <TB1> INFO: safety margin for low PH: adding 17, margin is now 37
[15:03:02.622] <TB1> INFO: safety margin for low PH: adding 18, margin is now 38
[15:03:02.628] <TB1> INFO: safety margin for low PH: adding 19, margin is now 39
[15:03:02.633] <TB1> INFO: safety margin for low PH: adding 20, margin is now 40
[15:03:02.637] <TB1> INFO: safety margin for low PH: adding 21, margin is now 41
[15:03:02.642] <TB1> INFO: safety margin for low PH: adding 22, margin is now 42
[15:03:02.647] <TB1> INFO: safety margin for low PH: adding 23, margin is now 43
[15:03:02.652] <TB1> INFO: safety margin for low PH: adding 24, margin is now 44
[15:03:02.657] <TB1> INFO: safety margin for low PH: adding 25, margin is now 45
[15:03:02.662] <TB1> INFO: safety margin for low PH: adding 26, margin is now 46
[15:03:02.666] <TB1> INFO: safety margin for low PH: adding 27, margin is now 47
[15:03:02.671] <TB1> INFO: safety margin for low PH: adding 28, margin is now 48
[15:03:02.675] <TB1> INFO: safety margin for low PH: adding 29, margin is now 49
[15:03:02.680] <TB1> INFO: safety margin for low PH: adding 30, margin is now 50
[15:03:02.685] <TB1> INFO: safety margin for low PH: adding 31, margin is now 51
[15:03:02.691] <TB1> INFO: safety margin for low PH: adding 32, margin is now 52
[15:03:02.698] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:02.704] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:03:02.710] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:03:02.716] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[15:03:02.723] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[15:03:02.729] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[15:03:02.735] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[15:03:02.742] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[15:03:02.748] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[15:03:02.754] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[15:03:02.761] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:02.767] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:03:02.773] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:03:02.780] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[15:03:02.786] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[15:03:02.792] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[15:03:02.799] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[15:03:02.805] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[15:03:02.811] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[15:03:02.817] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:03:02.852] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C0.dat
[15:03:02.852] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C1.dat
[15:03:02.852] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C2.dat
[15:03:02.852] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C3.dat
[15:03:02.852] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C4.dat
[15:03:02.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C5.dat
[15:03:02.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C6.dat
[15:03:02.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C7.dat
[15:03:02.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C8.dat
[15:03:02.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C9.dat
[15:03:02.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C10.dat
[15:03:02.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C11.dat
[15:03:02.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C12.dat
[15:03:02.853] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C13.dat
[15:03:02.854] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C14.dat
[15:03:02.854] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters35_C15.dat
[15:03:03.131] <TB1> INFO: Expecting 41600 events.
[15:03:06.259] <TB1> INFO: 41600 events read in total (2536ms).
[15:03:06.260] <TB1> INFO: Test took 3404ms.
[15:03:06.705] <TB1> INFO: Expecting 41600 events.
[15:03:09.685] <TB1> INFO: 41600 events read in total (2389ms).
[15:03:09.686] <TB1> INFO: Test took 3213ms.
[15:03:10.130] <TB1> INFO: Expecting 41600 events.
[15:03:13.216] <TB1> INFO: 41600 events read in total (2494ms).
[15:03:13.217] <TB1> INFO: Test took 3321ms.
[15:03:13.431] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:13.520] <TB1> INFO: Expecting 2560 events.
[15:03:14.402] <TB1> INFO: 2560 events read in total (291ms).
[15:03:14.403] <TB1> INFO: Test took 972ms.
[15:03:14.404] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:14.711] <TB1> INFO: Expecting 2560 events.
[15:03:15.595] <TB1> INFO: 2560 events read in total (292ms).
[15:03:15.595] <TB1> INFO: Test took 1191ms.
[15:03:15.597] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:15.903] <TB1> INFO: Expecting 2560 events.
[15:03:16.786] <TB1> INFO: 2560 events read in total (291ms).
[15:03:16.786] <TB1> INFO: Test took 1189ms.
[15:03:16.788] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:17.094] <TB1> INFO: Expecting 2560 events.
[15:03:17.977] <TB1> INFO: 2560 events read in total (291ms).
[15:03:17.978] <TB1> INFO: Test took 1190ms.
[15:03:17.979] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:18.286] <TB1> INFO: Expecting 2560 events.
[15:03:19.169] <TB1> INFO: 2560 events read in total (291ms).
[15:03:19.169] <TB1> INFO: Test took 1190ms.
[15:03:19.171] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:19.478] <TB1> INFO: Expecting 2560 events.
[15:03:20.360] <TB1> INFO: 2560 events read in total (290ms).
[15:03:20.361] <TB1> INFO: Test took 1190ms.
[15:03:20.362] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:20.669] <TB1> INFO: Expecting 2560 events.
[15:03:21.552] <TB1> INFO: 2560 events read in total (291ms).
[15:03:21.553] <TB1> INFO: Test took 1191ms.
[15:03:21.555] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:21.861] <TB1> INFO: Expecting 2560 events.
[15:03:22.744] <TB1> INFO: 2560 events read in total (291ms).
[15:03:22.744] <TB1> INFO: Test took 1190ms.
[15:03:22.746] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:23.052] <TB1> INFO: Expecting 2560 events.
[15:03:23.931] <TB1> INFO: 2560 events read in total (287ms).
[15:03:23.931] <TB1> INFO: Test took 1185ms.
[15:03:23.933] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:24.239] <TB1> INFO: Expecting 2560 events.
[15:03:25.118] <TB1> INFO: 2560 events read in total (287ms).
[15:03:25.119] <TB1> INFO: Test took 1186ms.
[15:03:25.120] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:25.427] <TB1> INFO: Expecting 2560 events.
[15:03:26.308] <TB1> INFO: 2560 events read in total (289ms).
[15:03:26.309] <TB1> INFO: Test took 1189ms.
[15:03:26.310] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:26.617] <TB1> INFO: Expecting 2560 events.
[15:03:27.498] <TB1> INFO: 2560 events read in total (289ms).
[15:03:27.499] <TB1> INFO: Test took 1189ms.
[15:03:27.500] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:27.807] <TB1> INFO: Expecting 2560 events.
[15:03:28.687] <TB1> INFO: 2560 events read in total (289ms).
[15:03:28.687] <TB1> INFO: Test took 1187ms.
[15:03:28.689] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:28.995] <TB1> INFO: Expecting 2560 events.
[15:03:29.878] <TB1> INFO: 2560 events read in total (291ms).
[15:03:29.878] <TB1> INFO: Test took 1189ms.
[15:03:29.879] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:30.186] <TB1> INFO: Expecting 2560 events.
[15:03:31.066] <TB1> INFO: 2560 events read in total (288ms).
[15:03:31.066] <TB1> INFO: Test took 1187ms.
[15:03:31.068] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:31.374] <TB1> INFO: Expecting 2560 events.
[15:03:32.254] <TB1> INFO: 2560 events read in total (288ms).
[15:03:32.255] <TB1> INFO: Test took 1188ms.
[15:03:32.256] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:32.563] <TB1> INFO: Expecting 2560 events.
[15:03:33.440] <TB1> INFO: 2560 events read in total (285ms).
[15:03:33.441] <TB1> INFO: Test took 1185ms.
[15:03:33.442] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:33.749] <TB1> INFO: Expecting 2560 events.
[15:03:34.631] <TB1> INFO: 2560 events read in total (290ms).
[15:03:34.631] <TB1> INFO: Test took 1189ms.
[15:03:34.633] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:34.939] <TB1> INFO: Expecting 2560 events.
[15:03:35.819] <TB1> INFO: 2560 events read in total (288ms).
[15:03:35.820] <TB1> INFO: Test took 1187ms.
[15:03:35.822] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:36.128] <TB1> INFO: Expecting 2560 events.
[15:03:37.006] <TB1> INFO: 2560 events read in total (286ms).
[15:03:37.007] <TB1> INFO: Test took 1186ms.
[15:03:37.008] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:37.315] <TB1> INFO: Expecting 2560 events.
[15:03:38.195] <TB1> INFO: 2560 events read in total (288ms).
[15:03:38.195] <TB1> INFO: Test took 1187ms.
[15:03:38.198] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:38.503] <TB1> INFO: Expecting 2560 events.
[15:03:39.385] <TB1> INFO: 2560 events read in total (290ms).
[15:03:39.386] <TB1> INFO: Test took 1188ms.
[15:03:39.388] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:39.694] <TB1> INFO: Expecting 2560 events.
[15:03:40.572] <TB1> INFO: 2560 events read in total (286ms).
[15:03:40.572] <TB1> INFO: Test took 1184ms.
[15:03:40.574] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:40.881] <TB1> INFO: Expecting 2560 events.
[15:03:41.761] <TB1> INFO: 2560 events read in total (288ms).
[15:03:41.762] <TB1> INFO: Test took 1188ms.
[15:03:41.763] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:42.070] <TB1> INFO: Expecting 2560 events.
[15:03:42.953] <TB1> INFO: 2560 events read in total (292ms).
[15:03:42.953] <TB1> INFO: Test took 1190ms.
[15:03:42.955] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:43.261] <TB1> INFO: Expecting 2560 events.
[15:03:44.148] <TB1> INFO: 2560 events read in total (295ms).
[15:03:44.148] <TB1> INFO: Test took 1193ms.
[15:03:44.150] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:44.456] <TB1> INFO: Expecting 2560 events.
[15:03:45.340] <TB1> INFO: 2560 events read in total (292ms).
[15:03:45.340] <TB1> INFO: Test took 1190ms.
[15:03:45.342] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:45.649] <TB1> INFO: Expecting 2560 events.
[15:03:46.532] <TB1> INFO: 2560 events read in total (292ms).
[15:03:46.533] <TB1> INFO: Test took 1191ms.
[15:03:46.534] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:46.841] <TB1> INFO: Expecting 2560 events.
[15:03:47.724] <TB1> INFO: 2560 events read in total (292ms).
[15:03:47.724] <TB1> INFO: Test took 1190ms.
[15:03:47.726] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:48.033] <TB1> INFO: Expecting 2560 events.
[15:03:48.918] <TB1> INFO: 2560 events read in total (294ms).
[15:03:48.919] <TB1> INFO: Test took 1193ms.
[15:03:48.921] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:49.227] <TB1> INFO: Expecting 2560 events.
[15:03:50.110] <TB1> INFO: 2560 events read in total (292ms).
[15:03:50.110] <TB1> INFO: Test took 1189ms.
[15:03:50.112] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:50.419] <TB1> INFO: Expecting 2560 events.
[15:03:51.304] <TB1> INFO: 2560 events read in total (294ms).
[15:03:51.304] <TB1> INFO: Test took 1192ms.
[15:03:51.766] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 624 seconds
[15:03:51.766] <TB1> INFO: PH scale (per ROC): 47 33 42 53 33 37 59 35 36 35 45 52 28 40 40 41
[15:03:51.766] <TB1> INFO: PH offset (per ROC): 89 86 107 123 109 102 123 114 103 104 83 118 80 112 112 83
[15:03:51.771] <TB1> INFO: Decoding statistics:
[15:03:51.771] <TB1> INFO: General information:
[15:03:51.771] <TB1> INFO: 16bit words read: 127884
[15:03:51.771] <TB1> INFO: valid events total: 20480
[15:03:51.771] <TB1> INFO: empty events: 17978
[15:03:51.772] <TB1> INFO: valid events with pixels: 2502
[15:03:51.772] <TB1> INFO: valid pixel hits: 2502
[15:03:51.772] <TB1> INFO: Event errors: 0
[15:03:51.772] <TB1> INFO: start marker: 0
[15:03:51.772] <TB1> INFO: stop marker: 0
[15:03:51.772] <TB1> INFO: overflow: 0
[15:03:51.772] <TB1> INFO: invalid 5bit words: 0
[15:03:51.772] <TB1> INFO: invalid XOR eye diagram: 0
[15:03:51.772] <TB1> INFO: frame (failed synchr.): 0
[15:03:51.772] <TB1> INFO: idle data (no TBM trl): 0
[15:03:51.772] <TB1> INFO: no data (only TBM hdr): 0
[15:03:51.772] <TB1> INFO: TBM errors: 0
[15:03:51.772] <TB1> INFO: flawed TBM headers: 0
[15:03:51.772] <TB1> INFO: flawed TBM trailers: 0
[15:03:51.772] <TB1> INFO: event ID mismatches: 0
[15:03:51.772] <TB1> INFO: ROC errors: 0
[15:03:51.772] <TB1> INFO: missing ROC header(s): 0
[15:03:51.772] <TB1> INFO: misplaced readback start: 0
[15:03:51.772] <TB1> INFO: Pixel decoding errors: 0
[15:03:51.772] <TB1> INFO: pixel data incomplete: 0
[15:03:51.772] <TB1> INFO: pixel address: 0
[15:03:51.772] <TB1> INFO: pulse height fill bit: 0
[15:03:51.772] <TB1> INFO: buffer corruption: 0
[15:03:52.044] <TB1> INFO: ######################################################################
[15:03:52.044] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[15:03:52.044] <TB1> INFO: ######################################################################
[15:03:52.055] <TB1> INFO: scanning low vcal = 10
[15:03:52.288] <TB1> INFO: Expecting 41600 events.
[15:03:55.849] <TB1> INFO: 41600 events read in total (2969ms).
[15:03:55.849] <TB1> INFO: Test took 3793ms.
[15:03:55.850] <TB1> INFO: scanning low vcal = 20
[15:03:56.148] <TB1> INFO: Expecting 41600 events.
[15:03:59.714] <TB1> INFO: 41600 events read in total (2975ms).
[15:03:59.715] <TB1> INFO: Test took 3864ms.
[15:03:59.716] <TB1> INFO: scanning low vcal = 30
[15:04:00.012] <TB1> INFO: Expecting 41600 events.
[15:04:03.671] <TB1> INFO: 41600 events read in total (3067ms).
[15:04:03.672] <TB1> INFO: Test took 3956ms.
[15:04:03.674] <TB1> INFO: scanning low vcal = 40
[15:04:03.952] <TB1> INFO: Expecting 41600 events.
[15:04:07.900] <TB1> INFO: 41600 events read in total (3356ms).
[15:04:07.901] <TB1> INFO: Test took 4227ms.
[15:04:07.904] <TB1> INFO: scanning low vcal = 50
[15:04:08.180] <TB1> INFO: Expecting 41600 events.
[15:04:12.117] <TB1> INFO: 41600 events read in total (3345ms).
[15:04:12.117] <TB1> INFO: Test took 4213ms.
[15:04:12.120] <TB1> INFO: scanning low vcal = 60
[15:04:12.397] <TB1> INFO: Expecting 41600 events.
[15:04:16.353] <TB1> INFO: 41600 events read in total (3365ms).
[15:04:16.354] <TB1> INFO: Test took 4234ms.
[15:04:16.357] <TB1> INFO: scanning low vcal = 70
[15:04:16.634] <TB1> INFO: Expecting 41600 events.
[15:04:20.564] <TB1> INFO: 41600 events read in total (3339ms).
[15:04:20.565] <TB1> INFO: Test took 4208ms.
[15:04:20.568] <TB1> INFO: scanning low vcal = 80
[15:04:20.844] <TB1> INFO: Expecting 41600 events.
[15:04:24.801] <TB1> INFO: 41600 events read in total (3365ms).
[15:04:24.802] <TB1> INFO: Test took 4234ms.
[15:04:24.804] <TB1> INFO: scanning low vcal = 90
[15:04:25.081] <TB1> INFO: Expecting 41600 events.
[15:04:29.027] <TB1> INFO: 41600 events read in total (3355ms).
[15:04:29.028] <TB1> INFO: Test took 4224ms.
[15:04:29.031] <TB1> INFO: scanning low vcal = 100
[15:04:29.307] <TB1> INFO: Expecting 41600 events.
[15:04:33.270] <TB1> INFO: 41600 events read in total (3371ms).
[15:04:33.271] <TB1> INFO: Test took 4240ms.
[15:04:33.273] <TB1> INFO: scanning low vcal = 110
[15:04:33.550] <TB1> INFO: Expecting 41600 events.
[15:04:37.493] <TB1> INFO: 41600 events read in total (3352ms).
[15:04:37.494] <TB1> INFO: Test took 4221ms.
[15:04:37.497] <TB1> INFO: scanning low vcal = 120
[15:04:37.777] <TB1> INFO: Expecting 41600 events.
[15:04:41.792] <TB1> INFO: 41600 events read in total (3423ms).
[15:04:41.793] <TB1> INFO: Test took 4296ms.
[15:04:41.796] <TB1> INFO: scanning low vcal = 130
[15:04:42.072] <TB1> INFO: Expecting 41600 events.
[15:04:46.030] <TB1> INFO: 41600 events read in total (3366ms).
[15:04:46.030] <TB1> INFO: Test took 4234ms.
[15:04:46.033] <TB1> INFO: scanning low vcal = 140
[15:04:46.310] <TB1> INFO: Expecting 41600 events.
[15:04:50.268] <TB1> INFO: 41600 events read in total (3367ms).
[15:04:50.269] <TB1> INFO: Test took 4236ms.
[15:04:50.272] <TB1> INFO: scanning low vcal = 150
[15:04:50.548] <TB1> INFO: Expecting 41600 events.
[15:04:54.486] <TB1> INFO: 41600 events read in total (3346ms).
[15:04:54.487] <TB1> INFO: Test took 4215ms.
[15:04:54.490] <TB1> INFO: scanning low vcal = 160
[15:04:54.766] <TB1> INFO: Expecting 41600 events.
[15:04:58.743] <TB1> INFO: 41600 events read in total (3385ms).
[15:04:58.744] <TB1> INFO: Test took 4254ms.
[15:04:58.747] <TB1> INFO: scanning low vcal = 170
[15:04:59.023] <TB1> INFO: Expecting 41600 events.
[15:05:02.975] <TB1> INFO: 41600 events read in total (3360ms).
[15:05:02.976] <TB1> INFO: Test took 4229ms.
[15:05:02.979] <TB1> INFO: scanning low vcal = 180
[15:05:03.255] <TB1> INFO: Expecting 41600 events.
[15:05:07.243] <TB1> INFO: 41600 events read in total (3396ms).
[15:05:07.244] <TB1> INFO: Test took 4265ms.
[15:05:07.246] <TB1> INFO: scanning low vcal = 190
[15:05:07.543] <TB1> INFO: Expecting 41600 events.
[15:05:11.536] <TB1> INFO: 41600 events read in total (3402ms).
[15:05:11.536] <TB1> INFO: Test took 4289ms.
[15:05:11.539] <TB1> INFO: scanning low vcal = 200
[15:05:11.816] <TB1> INFO: Expecting 41600 events.
[15:05:15.812] <TB1> INFO: 41600 events read in total (3405ms).
[15:05:15.813] <TB1> INFO: Test took 4274ms.
[15:05:15.816] <TB1> INFO: scanning low vcal = 210
[15:05:16.093] <TB1> INFO: Expecting 41600 events.
[15:05:20.040] <TB1> INFO: 41600 events read in total (3356ms).
[15:05:20.040] <TB1> INFO: Test took 4224ms.
[15:05:20.043] <TB1> INFO: scanning low vcal = 220
[15:05:20.319] <TB1> INFO: Expecting 41600 events.
[15:05:24.283] <TB1> INFO: 41600 events read in total (3372ms).
[15:05:24.284] <TB1> INFO: Test took 4241ms.
[15:05:24.286] <TB1> INFO: scanning low vcal = 230
[15:05:24.563] <TB1> INFO: Expecting 41600 events.
[15:05:28.525] <TB1> INFO: 41600 events read in total (3370ms).
[15:05:28.525] <TB1> INFO: Test took 4239ms.
[15:05:28.528] <TB1> INFO: scanning low vcal = 240
[15:05:28.805] <TB1> INFO: Expecting 41600 events.
[15:05:32.779] <TB1> INFO: 41600 events read in total (3383ms).
[15:05:32.779] <TB1> INFO: Test took 4251ms.
[15:05:32.782] <TB1> INFO: scanning low vcal = 250
[15:05:33.058] <TB1> INFO: Expecting 41600 events.
[15:05:37.008] <TB1> INFO: 41600 events read in total (3358ms).
[15:05:37.008] <TB1> INFO: Test took 4226ms.
[15:05:37.012] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[15:05:37.288] <TB1> INFO: Expecting 41600 events.
[15:05:41.233] <TB1> INFO: 41600 events read in total (3355ms).
[15:05:41.234] <TB1> INFO: Test took 4222ms.
[15:05:41.237] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[15:05:41.513] <TB1> INFO: Expecting 41600 events.
[15:05:45.487] <TB1> INFO: 41600 events read in total (3382ms).
[15:05:45.487] <TB1> INFO: Test took 4250ms.
[15:05:45.490] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[15:05:45.767] <TB1> INFO: Expecting 41600 events.
[15:05:49.715] <TB1> INFO: 41600 events read in total (3357ms).
[15:05:49.715] <TB1> INFO: Test took 4225ms.
[15:05:49.718] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[15:05:49.995] <TB1> INFO: Expecting 41600 events.
[15:05:53.940] <TB1> INFO: 41600 events read in total (3354ms).
[15:05:53.941] <TB1> INFO: Test took 4223ms.
[15:05:53.944] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[15:05:54.220] <TB1> INFO: Expecting 41600 events.
[15:05:58.162] <TB1> INFO: 41600 events read in total (3350ms).
[15:05:58.163] <TB1> INFO: Test took 4219ms.
[15:05:58.738] <TB1> INFO: PixTestGainPedestal::measure() done
[15:06:37.163] <TB1> INFO: PixTestGainPedestal::fit() done
[15:06:37.163] <TB1> INFO: non-linearity mean: 0.954 0.979 0.942 0.984 0.967 0.919 0.986 0.916 0.947 0.923 0.932 0.977 1.062 0.958 0.935 0.936
[15:06:37.163] <TB1> INFO: non-linearity RMS: 0.060 0.187 0.159 0.002 0.196 0.134 0.003 0.116 0.067 0.121 0.160 0.010 0.097 0.051 0.095 0.152
[15:06:37.163] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[15:06:37.184] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[15:06:37.200] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[15:06:37.219] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[15:06:37.240] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[15:06:37.260] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[15:06:37.282] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[15:06:37.300] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[15:06:37.314] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[15:06:37.334] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[15:06:37.348] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[15:06:37.368] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[15:06:37.389] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[15:06:37.410] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[15:06:37.434] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[15:06:37.453] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[15:06:37.467] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 165 seconds
[15:06:37.467] <TB1> INFO: Decoding statistics:
[15:06:37.467] <TB1> INFO: General information:
[15:06:37.467] <TB1> INFO: 16bit words read: 3293918
[15:06:37.467] <TB1> INFO: valid events total: 332800
[15:06:37.467] <TB1> INFO: empty events: 683
[15:06:37.467] <TB1> INFO: valid events with pixels: 332117
[15:06:37.468] <TB1> INFO: valid pixel hits: 648559
[15:06:37.468] <TB1> INFO: Event errors: 0
[15:06:37.468] <TB1> INFO: start marker: 0
[15:06:37.468] <TB1> INFO: stop marker: 0
[15:06:37.468] <TB1> INFO: overflow: 0
[15:06:37.468] <TB1> INFO: invalid 5bit words: 0
[15:06:37.468] <TB1> INFO: invalid XOR eye diagram: 0
[15:06:37.468] <TB1> INFO: frame (failed synchr.): 0
[15:06:37.468] <TB1> INFO: idle data (no TBM trl): 0
[15:06:37.468] <TB1> INFO: no data (only TBM hdr): 0
[15:06:37.468] <TB1> INFO: TBM errors: 0
[15:06:37.468] <TB1> INFO: flawed TBM headers: 0
[15:06:37.468] <TB1> INFO: flawed TBM trailers: 0
[15:06:37.468] <TB1> INFO: event ID mismatches: 0
[15:06:37.468] <TB1> INFO: ROC errors: 0
[15:06:37.468] <TB1> INFO: missing ROC header(s): 0
[15:06:37.468] <TB1> INFO: misplaced readback start: 0
[15:06:37.468] <TB1> INFO: Pixel decoding errors: 0
[15:06:37.468] <TB1> INFO: pixel data incomplete: 0
[15:06:37.468] <TB1> INFO: pixel address: 0
[15:06:37.468] <TB1> INFO: pulse height fill bit: 0
[15:06:37.468] <TB1> INFO: buffer corruption: 0
[15:06:37.483] <TB1> INFO: Decoding statistics:
[15:06:37.483] <TB1> INFO: General information:
[15:06:37.483] <TB1> INFO: 16bit words read: 3423338
[15:06:37.483] <TB1> INFO: valid events total: 353536
[15:06:37.483] <TB1> INFO: empty events: 18917
[15:06:37.483] <TB1> INFO: valid events with pixels: 334619
[15:06:37.483] <TB1> INFO: valid pixel hits: 651061
[15:06:37.483] <TB1> INFO: Event errors: 0
[15:06:37.483] <TB1> INFO: start marker: 0
[15:06:37.483] <TB1> INFO: stop marker: 0
[15:06:37.483] <TB1> INFO: overflow: 0
[15:06:37.483] <TB1> INFO: invalid 5bit words: 0
[15:06:37.483] <TB1> INFO: invalid XOR eye diagram: 0
[15:06:37.483] <TB1> INFO: frame (failed synchr.): 0
[15:06:37.483] <TB1> INFO: idle data (no TBM trl): 0
[15:06:37.483] <TB1> INFO: no data (only TBM hdr): 0
[15:06:37.483] <TB1> INFO: TBM errors: 0
[15:06:37.483] <TB1> INFO: flawed TBM headers: 0
[15:06:37.483] <TB1> INFO: flawed TBM trailers: 0
[15:06:37.483] <TB1> INFO: event ID mismatches: 0
[15:06:37.483] <TB1> INFO: ROC errors: 0
[15:06:37.483] <TB1> INFO: missing ROC header(s): 0
[15:06:37.483] <TB1> INFO: misplaced readback start: 0
[15:06:37.483] <TB1> INFO: Pixel decoding errors: 0
[15:06:37.483] <TB1> INFO: pixel data incomplete: 0
[15:06:37.483] <TB1> INFO: pixel address: 0
[15:06:37.484] <TB1> INFO: pulse height fill bit: 0
[15:06:37.484] <TB1> INFO: buffer corruption: 0
[15:06:37.484] <TB1> INFO: enter test to run
[15:06:37.484] <TB1> INFO: test: Trim80 no parameter change
[15:06:37.484] <TB1> INFO: running: trim80
[15:06:37.499] <TB1> INFO: ######################################################################
[15:06:37.499] <TB1> INFO: PixTestTrim80::doTest()
[15:06:37.499] <TB1> INFO: ######################################################################
[15:06:37.500] <TB1> INFO: ----------------------------------------------------------------------
[15:06:37.500] <TB1> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[15:06:37.500] <TB1> INFO: ----------------------------------------------------------------------
[15:06:37.547] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[15:06:37.547] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[15:06:37.558] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[15:06:37.558] <TB1> INFO: run 1 of 1
[15:06:37.833] <TB1> INFO: Expecting 5025280 events.
[15:07:05.995] <TB1> INFO: 685712 events read in total (27570ms).
[15:07:33.248] <TB1> INFO: 1367024 events read in total (54823ms).
[15:08:00.443] <TB1> INFO: 2046248 events read in total (82018ms).
[15:08:27.589] <TB1> INFO: 2723768 events read in total (109164ms).
[15:08:54.656] <TB1> INFO: 3399264 events read in total (136231ms).
[15:09:21.566] <TB1> INFO: 4073136 events read in total (163141ms).
[15:09:48.555] <TB1> INFO: 4746368 events read in total (190130ms).
[15:09:59.926] <TB1> INFO: 5025280 events read in total (201501ms).
[15:09:59.989] <TB1> INFO: Test took 202431ms.
[15:10:23.308] <TB1> INFO: ROC 0 VthrComp = 80
[15:10:23.308] <TB1> INFO: ROC 1 VthrComp = 79
[15:10:23.308] <TB1> INFO: ROC 2 VthrComp = 72
[15:10:23.308] <TB1> INFO: ROC 3 VthrComp = 73
[15:10:23.308] <TB1> INFO: ROC 4 VthrComp = 82
[15:10:23.309] <TB1> INFO: ROC 5 VthrComp = 79
[15:10:23.309] <TB1> INFO: ROC 6 VthrComp = 75
[15:10:23.309] <TB1> INFO: ROC 7 VthrComp = 77
[15:10:23.309] <TB1> INFO: ROC 8 VthrComp = 74
[15:10:23.309] <TB1> INFO: ROC 9 VthrComp = 85
[15:10:23.309] <TB1> INFO: ROC 10 VthrComp = 78
[15:10:23.309] <TB1> INFO: ROC 11 VthrComp = 79
[15:10:23.309] <TB1> INFO: ROC 12 VthrComp = 91
[15:10:23.309] <TB1> INFO: ROC 13 VthrComp = 82
[15:10:23.309] <TB1> INFO: ROC 14 VthrComp = 76
[15:10:23.309] <TB1> INFO: ROC 15 VthrComp = 79
[15:10:23.578] <TB1> INFO: Expecting 41600 events.
[15:10:27.128] <TB1> INFO: 41600 events read in total (2955ms).
[15:10:27.130] <TB1> INFO: Test took 3818ms.
[15:10:27.141] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[15:10:27.141] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[15:10:27.150] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[15:10:27.150] <TB1> INFO: run 1 of 1
[15:10:27.428] <TB1> INFO: Expecting 5025280 events.
[15:10:56.009] <TB1> INFO: 689568 events read in total (27989ms).
[15:11:23.365] <TB1> INFO: 1376024 events read in total (55346ms).
[15:11:50.681] <TB1> INFO: 2060864 events read in total (82661ms).
[15:12:18.012] <TB1> INFO: 2741864 events read in total (109992ms).
[15:12:45.088] <TB1> INFO: 3418552 events read in total (137068ms).
[15:13:11.726] <TB1> INFO: 4094672 events read in total (163706ms).
[15:13:38.145] <TB1> INFO: 4769688 events read in total (190125ms).
[15:13:48.389] <TB1> INFO: 5025280 events read in total (200369ms).
[15:13:48.451] <TB1> INFO: Test took 201300ms.
[15:14:11.637] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 109.268 for pixel 0/48 mean/min/max = 91.8695/74.4486/109.29
[15:14:11.637] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 108.339 for pixel 13/42 mean/min/max = 93.0678/77.7757/108.36
[15:14:11.637] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 108.95 for pixel 0/59 mean/min/max = 92.9541/76.9024/109.006
[15:14:11.638] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 109.418 for pixel 5/57 mean/min/max = 93.3981/77.363/109.433
[15:14:11.638] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 108.451 for pixel 7/79 mean/min/max = 91.3359/74.1599/108.512
[15:14:11.638] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 111.235 for pixel 0/69 mean/min/max = 94.0338/76.5313/111.536
[15:14:11.638] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 108.186 for pixel 51/40 mean/min/max = 93.1131/77.8425/108.384
[15:14:11.639] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 110.575 for pixel 1/72 mean/min/max = 93.9741/77.2108/110.737
[15:14:11.639] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 114.925 for pixel 0/29 mean/min/max = 96.4128/77.4204/115.405
[15:14:11.639] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 109.245 for pixel 0/57 mean/min/max = 91.5611/73.8489/109.273
[15:14:11.640] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 107.96 for pixel 29/3 mean/min/max = 92.8886/77.7918/107.985
[15:14:11.640] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 111.749 for pixel 0/22 mean/min/max = 94.7666/77.483/112.05
[15:14:11.640] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 112.234 for pixel 0/67 mean/min/max = 93.546/73.9326/113.159
[15:14:11.641] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 107.426 for pixel 47/79 mean/min/max = 91.2967/74.8251/107.768
[15:14:11.641] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 110.917 for pixel 1/13 mean/min/max = 94.769/78.4387/111.099
[15:14:11.641] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 110.586 for pixel 0/12 mean/min/max = 94.256/77.7831/110.729
[15:14:11.641] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:14:11.730] <TB1> INFO: Expecting 411648 events.
[15:14:20.976] <TB1> INFO: 411648 events read in total (8655ms).
[15:14:20.982] <TB1> INFO: Expecting 411648 events.
[15:14:30.110] <TB1> INFO: 411648 events read in total (8722ms).
[15:14:30.122] <TB1> INFO: Expecting 411648 events.
[15:14:39.345] <TB1> INFO: 411648 events read in total (8820ms).
[15:14:39.357] <TB1> INFO: Expecting 411648 events.
[15:14:48.525] <TB1> INFO: 411648 events read in total (8765ms).
[15:14:48.544] <TB1> INFO: Expecting 411648 events.
[15:14:57.553] <TB1> INFO: 411648 events read in total (8606ms).
[15:14:57.576] <TB1> INFO: Expecting 411648 events.
[15:15:06.531] <TB1> INFO: 411648 events read in total (8552ms).
[15:15:06.550] <TB1> INFO: Expecting 411648 events.
[15:15:15.572] <TB1> INFO: 411648 events read in total (8619ms).
[15:15:15.602] <TB1> INFO: Expecting 411648 events.
[15:15:24.682] <TB1> INFO: 411648 events read in total (8677ms).
[15:15:24.715] <TB1> INFO: Expecting 411648 events.
[15:15:33.760] <TB1> INFO: 411648 events read in total (8642ms).
[15:15:33.790] <TB1> INFO: Expecting 411648 events.
[15:15:42.891] <TB1> INFO: 411648 events read in total (8698ms).
[15:15:42.927] <TB1> INFO: Expecting 411648 events.
[15:15:52.028] <TB1> INFO: 411648 events read in total (8698ms).
[15:15:52.061] <TB1> INFO: Expecting 411648 events.
[15:16:01.169] <TB1> INFO: 411648 events read in total (8705ms).
[15:16:01.217] <TB1> INFO: Expecting 411648 events.
[15:16:10.385] <TB1> INFO: 411648 events read in total (8765ms).
[15:16:10.432] <TB1> INFO: Expecting 411648 events.
[15:16:19.545] <TB1> INFO: 411648 events read in total (8710ms).
[15:16:19.598] <TB1> INFO: Expecting 411648 events.
[15:16:28.648] <TB1> INFO: 411648 events read in total (8647ms).
[15:16:28.694] <TB1> INFO: Expecting 411648 events.
[15:16:37.929] <TB1> INFO: 411648 events read in total (8832ms).
[15:16:37.976] <TB1> INFO: Test took 146335ms.
[15:16:39.621] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[15:16:39.632] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[15:16:39.632] <TB1> INFO: run 1 of 1
[15:16:39.865] <TB1> INFO: Expecting 5025280 events.
[15:17:07.273] <TB1> INFO: 668856 events read in total (26816ms).
[15:17:34.457] <TB1> INFO: 1334776 events read in total (54000ms).
[15:18:01.059] <TB1> INFO: 1999792 events read in total (80602ms).
[15:18:27.723] <TB1> INFO: 2662144 events read in total (107266ms).
[15:18:54.437] <TB1> INFO: 3320184 events read in total (133980ms).
[15:19:21.218] <TB1> INFO: 3977480 events read in total (160761ms).
[15:19:48.216] <TB1> INFO: 4633592 events read in total (187759ms).
[15:20:04.057] <TB1> INFO: 5025280 events read in total (203600ms).
[15:20:04.113] <TB1> INFO: Test took 204481ms.
[15:20:27.619] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 51.317866 .. 98.939239
[15:20:27.894] <TB1> INFO: Expecting 208000 events.
[15:20:37.764] <TB1> INFO: 208000 events read in total (9278ms).
[15:20:37.764] <TB1> INFO: Test took 10143ms.
[15:20:37.811] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 41 .. 108 (-1/-1) hits flags = 528 (plus default)
[15:20:37.821] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[15:20:37.822] <TB1> INFO: run 1 of 1
[15:20:38.101] <TB1> INFO: Expecting 2263040 events.
[15:21:07.046] <TB1> INFO: 701208 events read in total (28353ms).
[15:21:35.305] <TB1> INFO: 1399560 events read in total (56612ms).
[15:22:03.755] <TB1> INFO: 2090472 events read in total (85062ms).
[15:22:11.092] <TB1> INFO: 2263040 events read in total (92399ms).
[15:22:11.128] <TB1> INFO: Test took 93306ms.
[15:22:31.351] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 61.883261 .. 89.311511
[15:22:31.588] <TB1> INFO: Expecting 208000 events.
[15:22:41.317] <TB1> INFO: 208000 events read in total (9138ms).
[15:22:41.318] <TB1> INFO: Test took 9965ms.
[15:22:41.398] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 51 .. 99 (-1/-1) hits flags = 528 (plus default)
[15:22:41.410] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[15:22:41.410] <TB1> INFO: run 1 of 1
[15:22:41.688] <TB1> INFO: Expecting 1630720 events.
[15:23:10.376] <TB1> INFO: 704736 events read in total (28096ms).
[15:23:38.418] <TB1> INFO: 1408872 events read in total (56138ms).
[15:23:47.569] <TB1> INFO: 1630720 events read in total (65289ms).
[15:23:47.604] <TB1> INFO: Test took 66195ms.
[15:24:05.792] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 66.806403 .. 84.275298
[15:24:06.059] <TB1> INFO: Expecting 208000 events.
[15:24:15.986] <TB1> INFO: 208000 events read in total (9335ms).
[15:24:15.987] <TB1> INFO: Test took 10194ms.
[15:24:16.034] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 56 .. 94 (-1/-1) hits flags = 528 (plus default)
[15:24:16.042] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[15:24:16.042] <TB1> INFO: run 1 of 1
[15:24:16.320] <TB1> INFO: Expecting 1297920 events.
[15:24:45.360] <TB1> INFO: 715632 events read in total (28448ms).
[15:25:09.309] <TB1> INFO: 1297920 events read in total (52397ms).
[15:25:09.334] <TB1> INFO: Test took 53293ms.
[15:25:27.191] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 70.278356 .. 83.493630
[15:25:27.432] <TB1> INFO: Expecting 208000 events.
[15:25:37.275] <TB1> INFO: 208000 events read in total (9240ms).
[15:25:37.276] <TB1> INFO: Test took 10083ms.
[15:25:37.322] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 60 .. 93 (-1/-1) hits flags = 528 (plus default)
[15:25:37.331] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[15:25:37.331] <TB1> INFO: run 1 of 1
[15:25:37.609] <TB1> INFO: Expecting 1131520 events.
[15:26:06.072] <TB1> INFO: 708232 events read in total (27872ms).
[15:26:23.305] <TB1> INFO: 1131520 events read in total (45105ms).
[15:26:23.329] <TB1> INFO: Test took 45999ms.
[15:26:38.862] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[15:26:38.862] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[15:26:38.874] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[15:26:38.874] <TB1> INFO: run 1 of 1
[15:26:39.179] <TB1> INFO: Expecting 1364480 events.
[15:27:07.959] <TB1> INFO: 668248 events read in total (28188ms).
[15:27:35.432] <TB1> INFO: 1336096 events read in total (55661ms).
[15:27:37.104] <TB1> INFO: 1364480 events read in total (57333ms).
[15:27:37.126] <TB1> INFO: Test took 58252ms.
[15:27:55.064] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C0.dat
[15:27:55.064] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C1.dat
[15:27:55.064] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C2.dat
[15:27:55.064] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C3.dat
[15:27:55.064] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C4.dat
[15:27:55.065] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C5.dat
[15:27:55.065] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C6.dat
[15:27:55.065] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C7.dat
[15:27:55.065] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C8.dat
[15:27:55.065] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C9.dat
[15:27:55.065] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C10.dat
[15:27:55.065] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C11.dat
[15:27:55.065] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C12.dat
[15:27:55.065] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C13.dat
[15:27:55.065] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C14.dat
[15:27:55.066] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//dacParameters80_C15.dat
[15:27:55.066] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C0.dat
[15:27:55.072] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C1.dat
[15:27:55.077] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C2.dat
[15:27:55.083] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C3.dat
[15:27:55.089] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C4.dat
[15:27:55.094] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C5.dat
[15:27:55.100] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C6.dat
[15:27:55.106] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C7.dat
[15:27:55.112] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C8.dat
[15:27:55.117] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C9.dat
[15:27:55.123] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C10.dat
[15:27:55.128] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C11.dat
[15:27:55.134] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C12.dat
[15:27:55.140] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C13.dat
[15:27:55.145] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C14.dat
[15:27:55.151] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1083_FullQualification_2016-10-26_11h02m_1477472544//003_FulltestTrim80_p17//trimParameters80_C15.dat
[15:27:55.156] <TB1> INFO: PixTestTrim80::trimTest() done
[15:27:55.156] <TB1> INFO: vtrim: 102 101 98 95 102 113 108 117 105 117 100 122 119 99 114 114
[15:27:55.157] <TB1> INFO: vthrcomp: 80 79 72 73 82 79 75 77 74 85 78 79 91 82 76 79
[15:27:55.157] <TB1> INFO: vcal mean: 79.91 79.96 79.95 79.95 79.93 79.98 79.99 79.96 79.95 79.97 79.96 79.95 80.00 79.94 79.97 79.95
[15:27:55.157] <TB1> INFO: vcal RMS: 0.76 0.71 0.76 0.76 0.80 0.75 0.75 0.74 0.88 0.90 0.72 0.82 0.91 0.82 0.79 0.82
[15:27:55.157] <TB1> INFO: bits mean: 10.24 9.48 9.93 9.50 10.24 9.74 10.09 9.80 9.21 10.74 9.81 10.12 10.03 10.06 9.56 9.76
[15:27:55.157] <TB1> INFO: bits RMS: 2.28 2.23 2.17 2.27 2.38 2.17 1.95 2.11 2.27 2.10 2.10 1.94 2.46 2.43 2.08 2.10
[15:27:55.163] <TB1> INFO: ----------------------------------------------------------------------
[15:27:55.163] <TB1> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[15:27:55.163] <TB1> INFO: ----------------------------------------------------------------------
[15:27:55.166] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[15:27:55.177] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:27:55.177] <TB1> INFO: run 1 of 1
[15:27:55.412] <TB1> INFO: Expecting 4160000 events.
[15:28:27.495] <TB1> INFO: 773590 events read in total (31492ms).
[15:28:59.103] <TB1> INFO: 1539670 events read in total (63101ms).
[15:29:30.267] <TB1> INFO: 2300580 events read in total (94264ms).
[15:30:01.557] <TB1> INFO: 3056190 events read in total (125554ms).
[15:30:32.518] <TB1> INFO: 3808310 events read in total (156515ms).
[15:30:47.404] <TB1> INFO: 4160000 events read in total (171401ms).
[15:30:47.463] <TB1> INFO: Test took 172286ms.
[15:31:13.057] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[15:31:13.068] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:31:13.068] <TB1> INFO: run 1 of 1
[15:31:13.339] <TB1> INFO: Expecting 5324800 events.
[15:31:43.903] <TB1> INFO: 686480 events read in total (29972ms).
[15:32:13.757] <TB1> INFO: 1369460 events read in total (59826ms).
[15:32:43.414] <TB1> INFO: 2050990 events read in total (89483ms).
[15:33:13.360] <TB1> INFO: 2730060 events read in total (119429ms).
[15:33:42.936] <TB1> INFO: 3406800 events read in total (149005ms).
[15:34:12.229] <TB1> INFO: 4081725 events read in total (178298ms).
[15:34:41.763] <TB1> INFO: 4755360 events read in total (207832ms).
[15:35:07.254] <TB1> INFO: 5324800 events read in total (233323ms).
[15:35:07.346] <TB1> INFO: Test took 234277ms.
[15:35:40.332] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 230 (-1/-1) hits flags = 528 (plus default)
[15:35:40.343] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:35:40.343] <TB1> INFO: run 1 of 1
[15:35:40.578] <TB1> INFO: Expecting 4804800 events.
[15:36:11.399] <TB1> INFO: 708365 events read in total (30229ms).
[15:36:41.244] <TB1> INFO: 1412945 events read in total (60074ms).
[15:37:11.449] <TB1> INFO: 2114995 events read in total (90279ms).
[15:37:41.449] <TB1> INFO: 2814210 events read in total (120279ms).
[15:38:11.456] <TB1> INFO: 3510325 events read in total (150286ms).
[15:38:41.784] <TB1> INFO: 4203990 events read in total (180614ms).
[15:39:08.193] <TB1> INFO: 4804800 events read in total (207023ms).
[15:39:08.302] <TB1> INFO: Test took 207960ms.
[15:39:39.501] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 220 (-1/-1) hits flags = 528 (plus default)
[15:39:39.511] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:39:39.511] <TB1> INFO: run 1 of 1
[15:39:39.745] <TB1> INFO: Expecting 4596800 events.
[15:40:11.077] <TB1> INFO: 719160 events read in total (30740ms).
[15:40:41.951] <TB1> INFO: 1434045 events read in total (61614ms).
[15:41:12.525] <TB1> INFO: 2146025 events read in total (92188ms).
[15:41:42.810] <TB1> INFO: 2854705 events read in total (122473ms).
[15:42:13.192] <TB1> INFO: 3559870 events read in total (152855ms).
[15:42:43.577] <TB1> INFO: 4263915 events read in total (183240ms).
[15:42:57.815] <TB1> INFO: 4596800 events read in total (197478ms).
[15:42:57.873] <TB1> INFO: Test took 198362ms.
[15:43:27.903] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 220 (-1/-1) hits flags = 528 (plus default)
[15:43:27.911] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:43:27.911] <TB1> INFO: run 1 of 1
[15:43:28.183] <TB1> INFO: Expecting 4596800 events.
[15:43:59.108] <TB1> INFO: 719255 events read in total (30333ms).
[15:44:29.684] <TB1> INFO: 1434220 events read in total (60909ms).
[15:44:59.969] <TB1> INFO: 2146630 events read in total (91195ms).
[15:45:30.533] <TB1> INFO: 2855195 events read in total (121758ms).
[15:46:01.661] <TB1> INFO: 3560365 events read in total (152886ms).
[15:46:32.776] <TB1> INFO: 4264835 events read in total (184001ms).
[15:46:47.848] <TB1> INFO: 4596800 events read in total (199073ms).
[15:46:47.906] <TB1> INFO: Test took 199994ms.
[15:47:13.359] <TB1> INFO: PixTestTrim80::trimBitTest() done
[15:47:13.360] <TB1> INFO: PixTestTrim80::doTest() done, duration: 2435 seconds
[15:47:13.992] <TB1> INFO: enter test to run
[15:47:13.992] <TB1> INFO: test: exit no parameter change
[15:47:14.096] <TB1> QUIET: Connection to board 153 closed.
[15:47:14.096] <TB1> INFO: pXar: this is the end, my friend