[06:39:54.801] <TB1> INFO: *** Welcome to pxar ***
[06:39:54.801] <TB1> INFO: *** Today: 2016/11/04
[06:39:54.809] <TB1> INFO: *** Version: c8ba-dirty
[06:39:54.809] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C15.dat
[06:39:54.810] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[06:39:54.810] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//defaultMaskFile.dat
[06:39:54.810] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters_C15.dat
[06:39:54.874] <TB1> INFO: clk: 4
[06:39:54.874] <TB1> INFO: ctr: 4
[06:39:54.874] <TB1> INFO: sda: 19
[06:39:54.874] <TB1> INFO: tin: 9
[06:39:54.874] <TB1> INFO: level: 15
[06:39:54.874] <TB1> INFO: triggerdelay: 0
[06:39:54.874] <TB1> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[06:39:54.874] <TB1> INFO: Log level: INFO
[06:39:54.882] <TB1> INFO: Found DTB DTB_WXC03A
[06:39:54.893] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[06:39:54.895] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
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[06:39:54.897] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[06:39:56.387] <TB1> INFO: DUT info:
[06:39:56.387] <TB1> INFO: The DUT currently contains the following objects:
[06:39:56.387] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[06:39:56.387] <TB1> INFO: TBM Core alpha (0): 7 registers set
[06:39:56.387] <TB1> INFO: TBM Core beta (1): 7 registers set
[06:39:56.387] <TB1> INFO: TBM Core alpha (2): 7 registers set
[06:39:56.387] <TB1> INFO: TBM Core beta (3): 7 registers set
[06:39:56.387] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[06:39:56.387] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[06:39:56.387] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[06:39:56.387] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[06:39:56.387] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[06:39:56.388] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[06:39:56.388] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[06:39:56.388] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[06:39:56.388] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[06:39:56.388] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[06:39:56.388] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[06:39:56.388] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[06:39:56.388] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[06:39:56.388] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[06:39:56.388] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[06:39:56.388] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[06:39:56.388] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[06:39:56.788] <TB1> INFO: enter 'restricted' command line mode
[06:39:56.789] <TB1> INFO: enter test to run
[06:39:56.789] <TB1> INFO: test: pretest no parameter change
[06:39:56.789] <TB1> INFO: running: pretest
[06:39:56.793] <TB1> INFO: ######################################################################
[06:39:56.793] <TB1> INFO: PixTestPretest::doTest()
[06:39:56.793] <TB1> INFO: ######################################################################
[06:39:56.795] <TB1> INFO: ----------------------------------------------------------------------
[06:39:56.795] <TB1> INFO: PixTestPretest::programROC()
[06:39:56.795] <TB1> INFO: ----------------------------------------------------------------------
[06:40:14.808] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[06:40:14.808] <TB1> INFO: IA differences per ROC: 16.1 17.7 17.7 19.3 16.9 20.1 18.5 17.7 17.7 16.9 16.1 18.5 17.7 17.7 18.5 17.7
[06:40:14.866] <TB1> INFO: ----------------------------------------------------------------------
[06:40:14.867] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[06:40:14.867] <TB1> INFO: ----------------------------------------------------------------------
[06:40:22.973] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 393.9 mA = 24.6187 mA/ROC
[06:40:22.973] <TB1> INFO: i(loss) [mA/ROC]: 20.1 20.1 19.3 20.1 19.3 20.1 20.1 19.3 20.1 19.3 19.3 20.9 19.3 19.3 20.1 20.1
[06:40:23.009] <TB1> INFO: ----------------------------------------------------------------------
[06:40:23.009] <TB1> INFO: PixTestPretest::findTiming()
[06:40:23.009] <TB1> INFO: ----------------------------------------------------------------------
[06:40:23.009] <TB1> INFO: PixTestCmd::init()

[06:40:55.338] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[06:40:55.338] <TB1> INFO: (success/tries = 100/100), width = 3
[06:40:56.853] <TB1> INFO: ----------------------------------------------------------------------
[06:40:56.853] <TB1> INFO: PixTestPretest::findWorkingPixel()
[06:40:56.853] <TB1> INFO: ----------------------------------------------------------------------
[06:40:56.947] <TB1> INFO: Expecting 231680 events.
[06:41:06.907] <TB1> INFO: 231680 events read in total (9368ms).
[06:41:06.917] <TB1> INFO: Test took 10060ms.
[06:41:07.158] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[06:41:07.189] <TB1> INFO: ----------------------------------------------------------------------
[06:41:07.189] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[06:41:07.189] <TB1> INFO: ----------------------------------------------------------------------
[06:41:07.283] <TB1> INFO: Expecting 231680 events.
[06:41:17.239] <TB1> INFO: 231680 events read in total (9364ms).
[06:41:17.253] <TB1> INFO: Test took 10059ms.
[06:41:17.518] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[06:41:17.518] <TB1> INFO: CalDel: 92 90 85 99 81 95 98 81 97 94 86 77 96 98 107 83
[06:41:17.518] <TB1> INFO: VthrComp: 51 51 54 51 51 51 51 53 57 51 54 51 51 51 51 63
[06:41:17.522] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C0.dat
[06:41:17.522] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C1.dat
[06:41:17.523] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C2.dat
[06:41:17.523] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C3.dat
[06:41:17.523] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C4.dat
[06:41:17.523] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C5.dat
[06:41:17.524] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C6.dat
[06:41:17.524] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C7.dat
[06:41:17.524] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C8.dat
[06:41:17.524] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C9.dat
[06:41:17.524] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C10.dat
[06:41:17.524] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C11.dat
[06:41:17.525] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C12.dat
[06:41:17.525] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C13.dat
[06:41:17.525] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C14.dat
[06:41:17.525] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters_C15.dat
[06:41:17.525] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[06:41:17.526] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[06:41:17.526] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[06:41:17.526] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[06:41:17.526] <TB1> INFO: PixTestPretest::doTest() done, duration: 80 seconds
[06:41:17.581] <TB1> INFO: enter test to run
[06:41:17.581] <TB1> INFO: test: fulltest no parameter change
[06:41:17.581] <TB1> INFO: running: fulltest
[06:41:17.581] <TB1> INFO: ######################################################################
[06:41:17.581] <TB1> INFO: PixTestFullTest::doTest()
[06:41:17.581] <TB1> INFO: ######################################################################
[06:41:17.582] <TB1> INFO: ######################################################################
[06:41:17.582] <TB1> INFO: PixTestAlive::doTest()
[06:41:17.582] <TB1> INFO: ######################################################################
[06:41:17.583] <TB1> INFO: ----------------------------------------------------------------------
[06:41:17.583] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[06:41:17.583] <TB1> INFO: ----------------------------------------------------------------------
[06:41:17.822] <TB1> INFO: Expecting 41600 events.
[06:41:21.433] <TB1> INFO: 41600 events read in total (3019ms).
[06:41:21.433] <TB1> INFO: Test took 3849ms.
[06:41:21.663] <TB1> INFO: PixTestAlive::aliveTest() done
[06:41:21.663] <TB1> INFO: number of dead pixels (per ROC): 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[06:41:21.665] <TB1> INFO: ----------------------------------------------------------------------
[06:41:21.665] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[06:41:21.665] <TB1> INFO: ----------------------------------------------------------------------
[06:41:21.910] <TB1> INFO: Expecting 41600 events.
[06:41:24.856] <TB1> INFO: 41600 events read in total (2354ms).
[06:41:24.857] <TB1> INFO: Test took 3191ms.
[06:41:24.857] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[06:41:25.095] <TB1> INFO: PixTestAlive::maskTest() done
[06:41:25.095] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[06:41:25.096] <TB1> INFO: ----------------------------------------------------------------------
[06:41:25.096] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[06:41:25.096] <TB1> INFO: ----------------------------------------------------------------------
[06:41:25.334] <TB1> INFO: Expecting 41600 events.
[06:41:28.900] <TB1> INFO: 41600 events read in total (2974ms).
[06:41:28.900] <TB1> INFO: Test took 3802ms.
[06:41:29.128] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[06:41:29.128] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[06:41:29.128] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[06:41:29.128] <TB1> INFO: Decoding statistics:
[06:41:29.128] <TB1> INFO: General information:
[06:41:29.128] <TB1> INFO: 16bit words read: 0
[06:41:29.128] <TB1> INFO: valid events total: 0
[06:41:29.128] <TB1> INFO: empty events: 0
[06:41:29.129] <TB1> INFO: valid events with pixels: 0
[06:41:29.129] <TB1> INFO: valid pixel hits: 0
[06:41:29.129] <TB1> INFO: Event errors: 0
[06:41:29.129] <TB1> INFO: start marker: 0
[06:41:29.129] <TB1> INFO: stop marker: 0
[06:41:29.129] <TB1> INFO: overflow: 0
[06:41:29.129] <TB1> INFO: invalid 5bit words: 0
[06:41:29.129] <TB1> INFO: invalid XOR eye diagram: 0
[06:41:29.129] <TB1> INFO: frame (failed synchr.): 0
[06:41:29.129] <TB1> INFO: idle data (no TBM trl): 0
[06:41:29.129] <TB1> INFO: no data (only TBM hdr): 0
[06:41:29.129] <TB1> INFO: TBM errors: 0
[06:41:29.129] <TB1> INFO: flawed TBM headers: 0
[06:41:29.129] <TB1> INFO: flawed TBM trailers: 0
[06:41:29.129] <TB1> INFO: event ID mismatches: 0
[06:41:29.129] <TB1> INFO: ROC errors: 0
[06:41:29.129] <TB1> INFO: missing ROC header(s): 0
[06:41:29.129] <TB1> INFO: misplaced readback start: 0
[06:41:29.129] <TB1> INFO: Pixel decoding errors: 0
[06:41:29.129] <TB1> INFO: pixel data incomplete: 0
[06:41:29.129] <TB1> INFO: pixel address: 0
[06:41:29.129] <TB1> INFO: pulse height fill bit: 0
[06:41:29.129] <TB1> INFO: buffer corruption: 0
[06:41:29.134] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C15.dat
[06:41:29.135] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[06:41:29.135] <TB1> INFO: ######################################################################
[06:41:29.135] <TB1> INFO: PixTestReadback::doTest()
[06:41:29.135] <TB1> INFO: ######################################################################
[06:41:29.135] <TB1> INFO: ----------------------------------------------------------------------
[06:41:29.135] <TB1> INFO: PixTestReadback::CalibrateVd()
[06:41:29.135] <TB1> INFO: ----------------------------------------------------------------------
[06:41:39.097] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C0.dat
[06:41:39.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C1.dat
[06:41:39.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C2.dat
[06:41:39.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C3.dat
[06:41:39.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C4.dat
[06:41:39.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C5.dat
[06:41:39.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C6.dat
[06:41:39.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C7.dat
[06:41:39.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C8.dat
[06:41:39.099] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C9.dat
[06:41:39.099] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C10.dat
[06:41:39.099] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C11.dat
[06:41:39.099] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C12.dat
[06:41:39.099] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C13.dat
[06:41:39.099] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C14.dat
[06:41:39.099] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C15.dat
[06:41:39.131] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[06:41:39.132] <TB1> INFO: ----------------------------------------------------------------------
[06:41:39.132] <TB1> INFO: PixTestReadback::CalibrateVa()
[06:41:39.132] <TB1> INFO: ----------------------------------------------------------------------
[06:41:49.067] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C0.dat
[06:41:49.067] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C1.dat
[06:41:49.067] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C2.dat
[06:41:49.067] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C3.dat
[06:41:49.067] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C4.dat
[06:41:49.067] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C5.dat
[06:41:49.067] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C6.dat
[06:41:49.067] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C7.dat
[06:41:49.068] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C8.dat
[06:41:49.068] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C9.dat
[06:41:49.068] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C10.dat
[06:41:49.068] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C11.dat
[06:41:49.068] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C12.dat
[06:41:49.068] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C13.dat
[06:41:49.068] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C14.dat
[06:41:49.068] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C15.dat
[06:41:49.097] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[06:41:49.097] <TB1> INFO: ----------------------------------------------------------------------
[06:41:49.097] <TB1> INFO: PixTestReadback::readbackVbg()
[06:41:49.097] <TB1> INFO: ----------------------------------------------------------------------
[06:41:56.769] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[06:41:56.769] <TB1> INFO: ----------------------------------------------------------------------
[06:41:56.769] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[06:41:56.769] <TB1> INFO: ----------------------------------------------------------------------
[06:41:56.770] <TB1> INFO: Vbg will be calibrated using Vd calibration
[06:41:56.770] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 154.1calibrated Vbg = 1.20582 :::*/*/*/*/
[06:41:56.770] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 146.3calibrated Vbg = 1.19843 :::*/*/*/*/
[06:41:56.770] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 156.1calibrated Vbg = 1.19611 :::*/*/*/*/
[06:41:56.770] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 157.9calibrated Vbg = 1.20072 :::*/*/*/*/
[06:41:56.770] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 159.6calibrated Vbg = 1.19859 :::*/*/*/*/
[06:41:56.770] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 150.6calibrated Vbg = 1.20326 :::*/*/*/*/
[06:41:56.770] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 161.4calibrated Vbg = 1.19956 :::*/*/*/*/
[06:41:56.770] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 158.5calibrated Vbg = 1.20076 :::*/*/*/*/
[06:41:56.770] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 160.4calibrated Vbg = 1.19082 :::*/*/*/*/
[06:41:56.770] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 150.4calibrated Vbg = 1.19299 :::*/*/*/*/
[06:41:56.770] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 153.6calibrated Vbg = 1.18922 :::*/*/*/*/
[06:41:56.770] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 157.7calibrated Vbg = 1.18433 :::*/*/*/*/
[06:41:56.770] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 156.5calibrated Vbg = 1.1938 :::*/*/*/*/
[06:41:56.770] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 155.5calibrated Vbg = 1.20169 :::*/*/*/*/
[06:41:56.770] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 155.6calibrated Vbg = 1.20517 :::*/*/*/*/
[06:41:56.770] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 156calibrated Vbg = 1.19555 :::*/*/*/*/
[06:41:56.772] <TB1> INFO: ----------------------------------------------------------------------
[06:41:56.772] <TB1> INFO: PixTestReadback::CalibrateIa()
[06:41:56.772] <TB1> INFO: ----------------------------------------------------------------------
[06:44:37.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C0.dat
[06:44:37.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C1.dat
[06:44:37.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C2.dat
[06:44:37.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C3.dat
[06:44:37.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C4.dat
[06:44:37.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C5.dat
[06:44:37.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C6.dat
[06:44:37.612] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C7.dat
[06:44:37.613] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C8.dat
[06:44:37.613] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C9.dat
[06:44:37.613] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C10.dat
[06:44:37.613] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C11.dat
[06:44:37.613] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C12.dat
[06:44:37.613] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C13.dat
[06:44:37.613] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C14.dat
[06:44:37.613] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//readbackCal_C15.dat
[06:44:37.644] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[06:44:37.647] <TB1> INFO: PixTestReadback::doTest() done
[06:44:37.647] <TB1> INFO: Decoding statistics:
[06:44:37.647] <TB1> INFO: General information:
[06:44:37.647] <TB1> INFO: 16bit words read: 1536
[06:44:37.647] <TB1> INFO: valid events total: 256
[06:44:37.647] <TB1> INFO: empty events: 256
[06:44:37.647] <TB1> INFO: valid events with pixels: 0
[06:44:37.647] <TB1> INFO: valid pixel hits: 0
[06:44:37.647] <TB1> INFO: Event errors: 0
[06:44:37.647] <TB1> INFO: start marker: 0
[06:44:37.647] <TB1> INFO: stop marker: 0
[06:44:37.648] <TB1> INFO: overflow: 0
[06:44:37.648] <TB1> INFO: invalid 5bit words: 0
[06:44:37.648] <TB1> INFO: invalid XOR eye diagram: 0
[06:44:37.648] <TB1> INFO: frame (failed synchr.): 0
[06:44:37.648] <TB1> INFO: idle data (no TBM trl): 0
[06:44:37.648] <TB1> INFO: no data (only TBM hdr): 0
[06:44:37.648] <TB1> INFO: TBM errors: 0
[06:44:37.648] <TB1> INFO: flawed TBM headers: 0
[06:44:37.648] <TB1> INFO: flawed TBM trailers: 0
[06:44:37.648] <TB1> INFO: event ID mismatches: 0
[06:44:37.648] <TB1> INFO: ROC errors: 0
[06:44:37.648] <TB1> INFO: missing ROC header(s): 0
[06:44:37.648] <TB1> INFO: misplaced readback start: 0
[06:44:37.648] <TB1> INFO: Pixel decoding errors: 0
[06:44:37.648] <TB1> INFO: pixel data incomplete: 0
[06:44:37.648] <TB1> INFO: pixel address: 0
[06:44:37.648] <TB1> INFO: pulse height fill bit: 0
[06:44:37.648] <TB1> INFO: buffer corruption: 0
[06:44:37.716] <TB1> INFO: ######################################################################
[06:44:37.716] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[06:44:37.716] <TB1> INFO: ######################################################################
[06:44:37.719] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[06:44:37.806] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[06:44:37.806] <TB1> INFO: run 1 of 1
[06:44:38.045] <TB1> INFO: Expecting 3120000 events.
[06:45:08.871] <TB1> INFO: 666975 events read in total (30234ms).











[06:45:38.676] <TB1> INFO: 1328735 events read in total (60039ms).











[06:46:08.829] <TB1> INFO: 1986005 events read in total (90192ms).











[06:46:38.605] <TB1> INFO: 2644145 events read in total (119968ms).











[06:47:00.203] <TB1> INFO: 3120000 events read in total (141566ms).
[06:47:00.304] <TB1> INFO: Test took 142499ms.
[06:47:25.322] <TB1> INFO: PixTestBBMap::doTest() done with 1 decoding errors: , duration: 167 seconds
[06:47:25.322] <TB1> INFO: number of dead bumps (per ROC): 6 22 0 2 0 0 0 0 0 0 0 1 0 0 0 0
[06:47:25.322] <TB1> INFO: separation cut (per ROC): 107 99 108 104 105 114 105 107 126 121 126 116 104 107 119 140
[06:47:25.322] <TB1> INFO: Decoding statistics:
[06:47:25.322] <TB1> INFO: General information:
[06:47:25.322] <TB1> INFO: 16bit words read: 0
[06:47:25.322] <TB1> INFO: valid events total: 0
[06:47:25.322] <TB1> INFO: empty events: 0
[06:47:25.322] <TB1> INFO: valid events with pixels: 0
[06:47:25.322] <TB1> INFO: valid pixel hits: 0
[06:47:25.322] <TB1> INFO: Event errors: 0
[06:47:25.322] <TB1> INFO: start marker: 0
[06:47:25.322] <TB1> INFO: stop marker: 0
[06:47:25.322] <TB1> INFO: overflow: 0
[06:47:25.322] <TB1> INFO: invalid 5bit words: 0
[06:47:25.322] <TB1> INFO: invalid XOR eye diagram: 0
[06:47:25.322] <TB1> INFO: frame (failed synchr.): 0
[06:47:25.322] <TB1> INFO: idle data (no TBM trl): 0
[06:47:25.322] <TB1> INFO: no data (only TBM hdr): 0
[06:47:25.322] <TB1> INFO: TBM errors: 0
[06:47:25.322] <TB1> INFO: flawed TBM headers: 0
[06:47:25.322] <TB1> INFO: flawed TBM trailers: 0
[06:47:25.322] <TB1> INFO: event ID mismatches: 0
[06:47:25.322] <TB1> INFO: ROC errors: 0
[06:47:25.322] <TB1> INFO: missing ROC header(s): 0
[06:47:25.322] <TB1> INFO: misplaced readback start: 0
[06:47:25.323] <TB1> INFO: Pixel decoding errors: 0
[06:47:25.323] <TB1> INFO: pixel data incomplete: 0
[06:47:25.323] <TB1> INFO: pixel address: 0
[06:47:25.323] <TB1> INFO: pulse height fill bit: 0
[06:47:25.323] <TB1> INFO: buffer corruption: 0
[06:47:25.363] <TB1> INFO: ######################################################################
[06:47:25.363] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[06:47:25.363] <TB1> INFO: ######################################################################
[06:47:25.363] <TB1> INFO: ----------------------------------------------------------------------
[06:47:25.364] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[06:47:25.364] <TB1> INFO: ----------------------------------------------------------------------
[06:47:25.364] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[06:47:25.379] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[06:47:25.379] <TB1> INFO: run 1 of 1
[06:47:25.637] <TB1> INFO: Expecting 36608000 events.
[06:47:49.212] <TB1> INFO: 699450 events read in total (22983ms).
[06:48:12.143] <TB1> INFO: 1382250 events read in total (45914ms).
[06:48:35.219] <TB1> INFO: 2066800 events read in total (68990ms).
[06:48:58.322] <TB1> INFO: 2750600 events read in total (92093ms).
[06:49:21.426] <TB1> INFO: 3433300 events read in total (115197ms).
[06:49:44.574] <TB1> INFO: 4114650 events read in total (138345ms).
[06:50:07.652] <TB1> INFO: 4797250 events read in total (161423ms).
[06:50:30.573] <TB1> INFO: 5479200 events read in total (184344ms).
[06:50:53.576] <TB1> INFO: 6160750 events read in total (207347ms).
[06:51:16.759] <TB1> INFO: 6843450 events read in total (230530ms).
[06:51:39.896] <TB1> INFO: 7525600 events read in total (253667ms).
[06:52:03.148] <TB1> INFO: 8207400 events read in total (276919ms).
[06:52:25.920] <TB1> INFO: 8888600 events read in total (299691ms).
[06:52:48.917] <TB1> INFO: 9572150 events read in total (322688ms).
[06:53:12.203] <TB1> INFO: 10254800 events read in total (345974ms).
[06:53:35.058] <TB1> INFO: 10936300 events read in total (368829ms).
[06:53:58.195] <TB1> INFO: 11616700 events read in total (391966ms).
[06:54:21.405] <TB1> INFO: 12298250 events read in total (415176ms).
[06:54:44.450] <TB1> INFO: 12978800 events read in total (438221ms).
[06:55:07.475] <TB1> INFO: 13660550 events read in total (461246ms).
[06:55:30.500] <TB1> INFO: 14341000 events read in total (484271ms).
[06:55:53.329] <TB1> INFO: 15019650 events read in total (507100ms).
[06:56:16.432] <TB1> INFO: 15697750 events read in total (530203ms).
[06:56:39.466] <TB1> INFO: 16375600 events read in total (553237ms).
[06:57:02.417] <TB1> INFO: 17054250 events read in total (576188ms).
[06:57:25.202] <TB1> INFO: 17730650 events read in total (598973ms).
[06:57:48.029] <TB1> INFO: 18406550 events read in total (621800ms).
[06:58:11.046] <TB1> INFO: 19083950 events read in total (644817ms).
[06:58:33.948] <TB1> INFO: 19758700 events read in total (667719ms).
[06:58:56.753] <TB1> INFO: 20430750 events read in total (690524ms).
[06:59:19.434] <TB1> INFO: 21102450 events read in total (713205ms).
[06:59:42.345] <TB1> INFO: 21778500 events read in total (736116ms).
[07:00:05.483] <TB1> INFO: 22452100 events read in total (759254ms).
[07:00:28.131] <TB1> INFO: 23125700 events read in total (781902ms).
[07:00:50.848] <TB1> INFO: 23800750 events read in total (804619ms).
[07:01:13.539] <TB1> INFO: 24475000 events read in total (827310ms).
[07:01:36.462] <TB1> INFO: 25149100 events read in total (850233ms).
[07:01:59.514] <TB1> INFO: 25823700 events read in total (873285ms).
[07:02:22.360] <TB1> INFO: 26495800 events read in total (896131ms).
[07:02:45.214] <TB1> INFO: 27171700 events read in total (918985ms).
[07:03:08.621] <TB1> INFO: 27845400 events read in total (942392ms).
[07:03:31.601] <TB1> INFO: 28518900 events read in total (965372ms).
[07:03:54.459] <TB1> INFO: 29192400 events read in total (988230ms).
[07:04:17.536] <TB1> INFO: 29865400 events read in total (1011307ms).
[07:04:40.324] <TB1> INFO: 30538650 events read in total (1034095ms).
[07:05:03.311] <TB1> INFO: 31210700 events read in total (1057082ms).
[07:05:26.251] <TB1> INFO: 31883600 events read in total (1080022ms).
[07:05:49.044] <TB1> INFO: 32556700 events read in total (1102815ms).
[07:06:11.775] <TB1> INFO: 33229200 events read in total (1125546ms).
[07:06:34.663] <TB1> INFO: 33902750 events read in total (1148434ms).
[07:06:57.615] <TB1> INFO: 34577100 events read in total (1171386ms).
[07:07:20.907] <TB1> INFO: 35251650 events read in total (1194678ms).
[07:07:43.527] <TB1> INFO: 35929700 events read in total (1217298ms).
[07:08:06.448] <TB1> INFO: 36608000 events read in total (1240219ms).
[07:08:06.547] <TB1> INFO: Test took 1241168ms.
[07:08:06.928] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[07:08:08.756] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[07:08:10.629] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[07:08:12.512] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[07:08:14.486] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[07:08:16.200] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[07:08:18.042] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[07:08:20.054] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[07:08:22.016] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[07:08:23.895] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[07:08:25.721] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[07:08:27.661] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[07:08:29.740] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[07:08:31.748] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[07:08:33.597] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[07:08:35.526] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[07:08:37.574] <TB1> INFO: PixTestScurves::scurves() done
[07:08:37.574] <TB1> INFO: Vcal mean: 127.48 112.60 120.01 118.99 123.30 128.10 128.93 126.95 137.67 135.56 131.34 124.78 122.25 122.44 128.88 134.10
[07:08:37.574] <TB1> INFO: Vcal RMS: 6.28 4.90 6.16 5.53 5.86 5.46 6.19 6.36 5.87 6.13 6.31 6.09 6.17 5.81 6.76 5.67
[07:08:37.574] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1272 seconds
[07:08:37.574] <TB1> INFO: Decoding statistics:
[07:08:37.574] <TB1> INFO: General information:
[07:08:37.574] <TB1> INFO: 16bit words read: 0
[07:08:37.574] <TB1> INFO: valid events total: 0
[07:08:37.574] <TB1> INFO: empty events: 0
[07:08:37.574] <TB1> INFO: valid events with pixels: 0
[07:08:37.574] <TB1> INFO: valid pixel hits: 0
[07:08:37.574] <TB1> INFO: Event errors: 0
[07:08:37.574] <TB1> INFO: start marker: 0
[07:08:37.574] <TB1> INFO: stop marker: 0
[07:08:37.574] <TB1> INFO: overflow: 0
[07:08:37.574] <TB1> INFO: invalid 5bit words: 0
[07:08:37.574] <TB1> INFO: invalid XOR eye diagram: 0
[07:08:37.574] <TB1> INFO: frame (failed synchr.): 0
[07:08:37.574] <TB1> INFO: idle data (no TBM trl): 0
[07:08:37.575] <TB1> INFO: no data (only TBM hdr): 0
[07:08:37.575] <TB1> INFO: TBM errors: 0
[07:08:37.575] <TB1> INFO: flawed TBM headers: 0
[07:08:37.575] <TB1> INFO: flawed TBM trailers: 0
[07:08:37.575] <TB1> INFO: event ID mismatches: 0
[07:08:37.575] <TB1> INFO: ROC errors: 0
[07:08:37.575] <TB1> INFO: missing ROC header(s): 0
[07:08:37.575] <TB1> INFO: misplaced readback start: 0
[07:08:37.575] <TB1> INFO: Pixel decoding errors: 0
[07:08:37.575] <TB1> INFO: pixel data incomplete: 0
[07:08:37.575] <TB1> INFO: pixel address: 0
[07:08:37.575] <TB1> INFO: pulse height fill bit: 0
[07:08:37.575] <TB1> INFO: buffer corruption: 0
[07:08:37.652] <TB1> INFO: ######################################################################
[07:08:37.652] <TB1> INFO: PixTestTrim::doTest()
[07:08:37.652] <TB1> INFO: ######################################################################
[07:08:37.653] <TB1> INFO: ----------------------------------------------------------------------
[07:08:37.653] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[07:08:37.653] <TB1> INFO: ----------------------------------------------------------------------
[07:08:37.700] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[07:08:37.701] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[07:08:37.714] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[07:08:37.714] <TB1> INFO: run 1 of 1
[07:08:37.954] <TB1> INFO: Expecting 5025280 events.
[07:09:09.677] <TB1> INFO: 833128 events read in total (31123ms).
[07:09:40.500] <TB1> INFO: 1663968 events read in total (61947ms).
[07:10:10.892] <TB1> INFO: 2491656 events read in total (92338ms).
[07:10:41.863] <TB1> INFO: 3314568 events read in total (123309ms).
[07:11:12.183] <TB1> INFO: 4133368 events read in total (153629ms).
[07:11:42.314] <TB1> INFO: 4950720 events read in total (183760ms).
[07:11:45.654] <TB1> INFO: 5025280 events read in total (187100ms).
[07:11:45.706] <TB1> INFO: Test took 187993ms.
[07:12:03.157] <TB1> INFO: ROC 0 VthrComp = 130
[07:12:03.158] <TB1> INFO: ROC 1 VthrComp = 115
[07:12:03.158] <TB1> INFO: ROC 2 VthrComp = 124
[07:12:03.158] <TB1> INFO: ROC 3 VthrComp = 122
[07:12:03.158] <TB1> INFO: ROC 4 VthrComp = 130
[07:12:03.158] <TB1> INFO: ROC 5 VthrComp = 131
[07:12:03.158] <TB1> INFO: ROC 6 VthrComp = 128
[07:12:03.158] <TB1> INFO: ROC 7 VthrComp = 130
[07:12:03.158] <TB1> INFO: ROC 8 VthrComp = 133
[07:12:03.158] <TB1> INFO: ROC 9 VthrComp = 132
[07:12:03.158] <TB1> INFO: ROC 10 VthrComp = 134
[07:12:03.158] <TB1> INFO: ROC 11 VthrComp = 132
[07:12:03.159] <TB1> INFO: ROC 12 VthrComp = 122
[07:12:03.159] <TB1> INFO: ROC 13 VthrComp = 126
[07:12:03.159] <TB1> INFO: ROC 14 VthrComp = 130
[07:12:03.159] <TB1> INFO: ROC 15 VthrComp = 139
[07:12:03.408] <TB1> INFO: Expecting 41600 events.
[07:12:07.066] <TB1> INFO: 41600 events read in total (3066ms).
[07:12:07.067] <TB1> INFO: Test took 3907ms.
[07:12:07.076] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[07:12:07.076] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[07:12:07.088] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[07:12:07.088] <TB1> INFO: run 1 of 1
[07:12:07.366] <TB1> INFO: Expecting 5025280 events.
[07:12:33.953] <TB1> INFO: 592424 events read in total (25996ms).
[07:12:59.786] <TB1> INFO: 1184152 events read in total (51829ms).
[07:13:25.481] <TB1> INFO: 1775576 events read in total (77524ms).
[07:13:51.744] <TB1> INFO: 2366352 events read in total (103787ms).
[07:14:17.786] <TB1> INFO: 2954608 events read in total (129829ms).
[07:14:43.486] <TB1> INFO: 3541584 events read in total (155529ms).
[07:15:09.483] <TB1> INFO: 4128328 events read in total (181526ms).
[07:15:35.494] <TB1> INFO: 4714856 events read in total (207537ms).
[07:15:50.119] <TB1> INFO: 5025280 events read in total (222162ms).
[07:15:50.205] <TB1> INFO: Test took 223118ms.
[07:16:18.581] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 61.8634 for pixel 0/16 mean/min/max = 47.023/32.0258/62.0202
[07:16:18.581] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 59.9358 for pixel 17/75 mean/min/max = 46.3992/32.7773/60.0211
[07:16:18.582] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 62.9901 for pixel 20/24 mean/min/max = 46.9083/30.8005/63.016
[07:16:18.582] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 61.6902 for pixel 21/12 mean/min/max = 46.9031/32.0294/61.7767
[07:16:18.583] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 58.9563 for pixel 14/14 mean/min/max = 46.0589/33.14/58.9777
[07:16:18.583] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 60.8292 for pixel 23/7 mean/min/max = 47.6127/34.3166/60.9088
[07:16:18.584] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 61.939 for pixel 16/5 mean/min/max = 47.2277/32.1275/62.3279
[07:16:18.584] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 62.5278 for pixel 0/9 mean/min/max = 47.0609/31.5276/62.5942
[07:16:18.585] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 69.6327 for pixel 2/14 mean/min/max = 53.5756/37.0064/70.1448
[07:16:18.585] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 61.7107 for pixel 6/75 mean/min/max = 46.8188/31.8727/61.7648
[07:16:18.585] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 63.8228 for pixel 11/1 mean/min/max = 48.291/32.7157/63.8663
[07:16:18.586] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 60.2915 for pixel 51/9 mean/min/max = 46.9471/33.5557/60.3386
[07:16:18.586] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 60.6479 for pixel 6/4 mean/min/max = 46.8685/32.8934/60.8435
[07:16:18.587] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 59.8132 for pixel 4/3 mean/min/max = 46.0382/32.2552/59.8212
[07:16:18.587] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 60.469 for pixel 2/4 mean/min/max = 46.5087/32.4395/60.578
[07:16:18.588] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 73.1873 for pixel 10/7 mean/min/max = 57.4346/41.5019/73.3673
[07:16:18.589] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[07:16:18.677] <TB1> INFO: Expecting 411648 events.
[07:16:28.173] <TB1> INFO: 411648 events read in total (8904ms).
[07:16:28.180] <TB1> INFO: Expecting 411648 events.
[07:16:37.269] <TB1> INFO: 411648 events read in total (8686ms).
[07:16:37.284] <TB1> INFO: Expecting 411648 events.
[07:16:46.646] <TB1> INFO: 411648 events read in total (8958ms).
[07:16:46.664] <TB1> INFO: Expecting 411648 events.
[07:16:56.104] <TB1> INFO: 411648 events read in total (9037ms).
[07:16:56.125] <TB1> INFO: Expecting 411648 events.
[07:17:05.512] <TB1> INFO: 411648 events read in total (8984ms).
[07:17:05.532] <TB1> INFO: Expecting 411648 events.
[07:17:14.939] <TB1> INFO: 411648 events read in total (9004ms).
[07:17:14.968] <TB1> INFO: Expecting 411648 events.
[07:17:24.368] <TB1> INFO: 411648 events read in total (8997ms).
[07:17:24.393] <TB1> INFO: Expecting 411648 events.
[07:17:33.736] <TB1> INFO: 411648 events read in total (8939ms).
[07:17:33.773] <TB1> INFO: Expecting 411648 events.
[07:17:43.171] <TB1> INFO: 411648 events read in total (8995ms).
[07:17:43.202] <TB1> INFO: Expecting 411648 events.
[07:17:52.572] <TB1> INFO: 411648 events read in total (8967ms).
[07:17:52.607] <TB1> INFO: Expecting 411648 events.
[07:18:02.014] <TB1> INFO: 411648 events read in total (9004ms).
[07:18:02.072] <TB1> INFO: Expecting 411648 events.
[07:18:11.431] <TB1> INFO: 411648 events read in total (8956ms).
[07:18:11.482] <TB1> INFO: Expecting 411648 events.
[07:18:20.857] <TB1> INFO: 411648 events read in total (8972ms).
[07:18:20.908] <TB1> INFO: Expecting 411648 events.
[07:18:30.294] <TB1> INFO: 411648 events read in total (8982ms).
[07:18:30.355] <TB1> INFO: Expecting 411648 events.
[07:18:39.716] <TB1> INFO: 411648 events read in total (8958ms).
[07:18:39.763] <TB1> INFO: Expecting 411648 events.
[07:18:49.014] <TB1> INFO: 411648 events read in total (8848ms).
[07:18:49.077] <TB1> INFO: Test took 150488ms.
[07:18:49.845] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[07:18:49.859] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[07:18:49.859] <TB1> INFO: run 1 of 1
[07:18:50.135] <TB1> INFO: Expecting 5025280 events.
[07:19:16.862] <TB1> INFO: 587864 events read in total (26135ms).
[07:19:42.677] <TB1> INFO: 1174456 events read in total (51950ms).
[07:20:08.737] <TB1> INFO: 1760936 events read in total (78010ms).
[07:20:34.491] <TB1> INFO: 2345384 events read in total (103764ms).
[07:21:00.430] <TB1> INFO: 2929072 events read in total (129703ms).
[07:21:26.560] <TB1> INFO: 3514464 events read in total (155833ms).
[07:21:52.754] <TB1> INFO: 4098104 events read in total (182027ms).
[07:22:18.485] <TB1> INFO: 4680808 events read in total (207758ms).
[07:22:35.614] <TB1> INFO: 5025280 events read in total (224887ms).
[07:22:35.726] <TB1> INFO: Test took 225869ms.
[07:23:01.337] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 8.774545 .. 142.232007
[07:23:01.591] <TB1> INFO: Expecting 208000 events.
[07:23:11.290] <TB1> INFO: 208000 events read in total (9107ms).
[07:23:11.291] <TB1> INFO: Test took 9953ms.
[07:23:11.358] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 8 .. 152 (-1/-1) hits flags = 528 (plus default)
[07:23:11.373] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[07:23:11.373] <TB1> INFO: run 1 of 1
[07:23:11.651] <TB1> INFO: Expecting 4825600 events.
[07:23:37.712] <TB1> INFO: 576208 events read in total (25470ms).
[07:24:03.124] <TB1> INFO: 1152656 events read in total (50883ms).
[07:24:28.483] <TB1> INFO: 1728856 events read in total (76242ms).
[07:24:54.138] <TB1> INFO: 2304904 events read in total (101896ms).
[07:25:19.866] <TB1> INFO: 2880960 events read in total (127624ms).
[07:25:45.653] <TB1> INFO: 3456776 events read in total (153411ms).
[07:26:11.292] <TB1> INFO: 4032440 events read in total (179050ms).
[07:26:36.921] <TB1> INFO: 4607480 events read in total (204679ms).
[07:26:47.019] <TB1> INFO: 4825600 events read in total (214777ms).
[07:26:47.143] <TB1> INFO: Test took 215771ms.
[07:27:13.467] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.053236 .. 46.662105
[07:27:13.705] <TB1> INFO: Expecting 208000 events.
[07:27:23.781] <TB1> INFO: 208000 events read in total (9484ms).
[07:27:23.782] <TB1> INFO: Test took 10314ms.
[07:27:23.829] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[07:27:23.843] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[07:27:23.843] <TB1> INFO: run 1 of 1
[07:27:24.121] <TB1> INFO: Expecting 1331200 events.
[07:27:53.228] <TB1> INFO: 656536 events read in total (28515ms).
[07:28:21.097] <TB1> INFO: 1312000 events read in total (56385ms).
[07:28:22.331] <TB1> INFO: 1331200 events read in total (57619ms).
[07:28:22.369] <TB1> INFO: Test took 58526ms.
[07:28:37.801] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 26.274362 .. 50.056028
[07:28:38.072] <TB1> INFO: Expecting 208000 events.
[07:28:48.025] <TB1> INFO: 208000 events read in total (9361ms).
[07:28:48.025] <TB1> INFO: Test took 10223ms.
[07:28:48.073] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 60 (-1/-1) hits flags = 528 (plus default)
[07:28:48.087] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[07:28:48.087] <TB1> INFO: run 1 of 1
[07:28:48.365] <TB1> INFO: Expecting 1497600 events.
[07:29:16.445] <TB1> INFO: 647000 events read in total (27488ms).
[07:29:44.248] <TB1> INFO: 1292728 events read in total (55292ms).
[07:29:53.336] <TB1> INFO: 1497600 events read in total (64379ms).
[07:29:53.372] <TB1> INFO: Test took 65286ms.
[07:30:06.590] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 24.940686 .. 54.911955
[07:30:06.831] <TB1> INFO: Expecting 208000 events.
[07:30:16.640] <TB1> INFO: 208000 events read in total (9218ms).
[07:30:16.641] <TB1> INFO: Test took 10049ms.
[07:30:16.690] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 64 (-1/-1) hits flags = 528 (plus default)
[07:30:16.704] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[07:30:16.704] <TB1> INFO: run 1 of 1
[07:30:16.982] <TB1> INFO: Expecting 1697280 events.
[07:30:44.566] <TB1> INFO: 642440 events read in total (26992ms).
[07:31:11.804] <TB1> INFO: 1284728 events read in total (54230ms).
[07:31:29.175] <TB1> INFO: 1697280 events read in total (71601ms).
[07:31:29.229] <TB1> INFO: Test took 72526ms.
[07:31:44.783] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[07:31:44.784] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[07:31:44.797] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[07:31:44.797] <TB1> INFO: run 1 of 1
[07:31:45.035] <TB1> INFO: Expecting 1364480 events.
[07:32:13.783] <TB1> INFO: 668376 events read in total (28156ms).
[07:32:41.848] <TB1> INFO: 1336872 events read in total (56221ms).
[07:32:43.397] <TB1> INFO: 1364480 events read in total (57770ms).
[07:32:43.431] <TB1> INFO: Test took 58635ms.
[07:32:57.746] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C0.dat
[07:32:57.746] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C1.dat
[07:32:57.746] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C2.dat
[07:32:57.746] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C3.dat
[07:32:57.747] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C4.dat
[07:32:57.747] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C5.dat
[07:32:57.747] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C6.dat
[07:32:57.747] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C7.dat
[07:32:57.747] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C8.dat
[07:32:57.747] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C9.dat
[07:32:57.747] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C10.dat
[07:32:57.747] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C11.dat
[07:32:57.747] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C12.dat
[07:32:57.748] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C13.dat
[07:32:57.748] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C14.dat
[07:32:57.748] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C15.dat
[07:32:57.748] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters35_C0.dat
[07:32:57.755] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters35_C1.dat
[07:32:57.761] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters35_C2.dat
[07:32:57.768] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters35_C3.dat
[07:32:57.774] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters35_C4.dat
[07:32:57.781] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters35_C5.dat
[07:32:57.787] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters35_C6.dat
[07:32:57.793] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters35_C7.dat
[07:32:57.799] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters35_C8.dat
[07:32:57.806] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters35_C9.dat
[07:32:57.813] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters35_C10.dat
[07:32:57.819] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters35_C11.dat
[07:32:57.825] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters35_C12.dat
[07:32:57.832] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters35_C13.dat
[07:32:57.838] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters35_C14.dat
[07:32:57.845] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters35_C15.dat
[07:32:57.851] <TB1> INFO: PixTestTrim::trimTest() done
[07:32:57.851] <TB1> INFO: vtrim: 119 131 142 147 126 143 144 131 175 136 134 125 138 119 122 199
[07:32:57.851] <TB1> INFO: vthrcomp: 130 115 124 122 130 131 128 130 133 132 134 132 122 126 130 139
[07:32:57.851] <TB1> INFO: vcal mean: 35.24 35.04 34.99 35.00 35.01 34.96 35.75 35.13 35.86 35.10 35.13 35.08 35.06 35.06 35.06 35.46
[07:32:57.851] <TB1> INFO: vcal RMS: 1.23 1.12 1.06 1.01 1.01 0.98 1.96 1.14 2.13 1.08 1.24 0.98 1.11 1.06 1.00 1.79
[07:32:57.851] <TB1> INFO: bits mean: 9.15 9.28 9.94 9.59 9.24 9.00 9.84 8.84 8.29 9.42 9.03 8.40 9.29 9.33 8.96 7.27
[07:32:57.851] <TB1> INFO: bits RMS: 2.87 2.72 2.52 2.62 2.72 2.55 2.62 3.05 2.43 2.69 2.70 2.87 2.67 2.80 2.83 2.15
[07:32:57.861] <TB1> INFO: ----------------------------------------------------------------------
[07:32:57.861] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[07:32:57.861] <TB1> INFO: ----------------------------------------------------------------------
[07:32:57.864] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[07:32:57.878] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[07:32:57.878] <TB1> INFO: run 1 of 1
[07:32:58.115] <TB1> INFO: Expecting 4160000 events.
[07:33:31.536] <TB1> INFO: 768835 events read in total (32830ms).
[07:34:03.877] <TB1> INFO: 1534000 events read in total (65171ms).
[07:34:36.421] <TB1> INFO: 2295970 events read in total (97715ms).
[07:35:08.779] <TB1> INFO: 3054790 events read in total (130073ms).
[07:35:40.993] <TB1> INFO: 3809640 events read in total (162287ms).
[07:35:55.764] <TB1> INFO: 4160000 events read in total (177058ms).
[07:35:55.835] <TB1> INFO: Test took 177957ms.
[07:36:20.751] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 242 (-1/-1) hits flags = 528 (plus default)
[07:36:20.764] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[07:36:20.764] <TB1> INFO: run 1 of 1
[07:36:21.047] <TB1> INFO: Expecting 5054400 events.
[07:36:52.447] <TB1> INFO: 694760 events read in total (30808ms).
[07:37:23.555] <TB1> INFO: 1387520 events read in total (61916ms).
[07:37:54.750] <TB1> INFO: 2078920 events read in total (93111ms).
[07:38:25.922] <TB1> INFO: 2768830 events read in total (124283ms).
[07:38:56.805] <TB1> INFO: 3457330 events read in total (155166ms).
[07:39:27.994] <TB1> INFO: 4143135 events read in total (186355ms).
[07:39:57.878] <TB1> INFO: 4829520 events read in total (216239ms).
[07:40:08.238] <TB1> INFO: 5054400 events read in total (226599ms).
[07:40:08.389] <TB1> INFO: Test took 227624ms.
[07:40:41.085] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[07:40:41.099] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[07:40:41.100] <TB1> INFO: run 1 of 1
[07:40:41.364] <TB1> INFO: Expecting 4430400 events.
[07:41:13.254] <TB1> INFO: 725625 events read in total (31299ms).
[07:41:44.381] <TB1> INFO: 1448865 events read in total (62426ms).
[07:42:15.597] <TB1> INFO: 2170070 events read in total (93642ms).
[07:42:46.769] <TB1> INFO: 2888685 events read in total (124814ms).
[07:43:18.224] <TB1> INFO: 3604365 events read in total (156269ms).
[07:43:49.729] <TB1> INFO: 4320560 events read in total (187774ms).
[07:43:54.889] <TB1> INFO: 4430400 events read in total (192934ms).
[07:43:54.969] <TB1> INFO: Test took 193869ms.
[07:44:20.691] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[07:44:20.704] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[07:44:20.704] <TB1> INFO: run 1 of 1
[07:44:20.948] <TB1> INFO: Expecting 4430400 events.
[07:44:52.521] <TB1> INFO: 725445 events read in total (30982ms).
[07:45:23.645] <TB1> INFO: 1449080 events read in total (62106ms).
[07:45:55.086] <TB1> INFO: 2170335 events read in total (93548ms).
[07:46:25.944] <TB1> INFO: 2889455 events read in total (124405ms).
[07:46:56.906] <TB1> INFO: 3605695 events read in total (155367ms).
[07:47:27.431] <TB1> INFO: 4321960 events read in total (185892ms).
[07:47:32.291] <TB1> INFO: 4430400 events read in total (190752ms).
[07:47:32.408] <TB1> INFO: Test took 191703ms.
[07:47:57.279] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[07:47:57.293] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[07:47:57.293] <TB1> INFO: run 1 of 1
[07:47:57.535] <TB1> INFO: Expecting 4430400 events.
[07:48:29.199] <TB1> INFO: 725250 events read in total (31072ms).
[07:49:00.042] <TB1> INFO: 1448480 events read in total (61915ms).
[07:49:31.348] <TB1> INFO: 2169385 events read in total (93222ms).
[07:50:02.490] <TB1> INFO: 2888070 events read in total (124363ms).
[07:50:33.768] <TB1> INFO: 3603745 events read in total (155641ms).
[07:51:04.357] <TB1> INFO: 4319650 events read in total (186230ms).
[07:51:09.342] <TB1> INFO: 4430400 events read in total (191216ms).
[07:51:09.419] <TB1> INFO: Test took 192126ms.
[07:51:32.997] <TB1> INFO: PixTestTrim::trimBitTest() done
[07:51:32.999] <TB1> INFO: PixTestTrim::doTest() done, duration: 2575 seconds
[07:51:32.999] <TB1> INFO: Decoding statistics:
[07:51:32.999] <TB1> INFO: General information:
[07:51:32.999] <TB1> INFO: 16bit words read: 0
[07:51:32.999] <TB1> INFO: valid events total: 0
[07:51:32.999] <TB1> INFO: empty events: 0
[07:51:32.999] <TB1> INFO: valid events with pixels: 0
[07:51:32.999] <TB1> INFO: valid pixel hits: 0
[07:51:32.999] <TB1> INFO: Event errors: 0
[07:51:32.999] <TB1> INFO: start marker: 0
[07:51:32.999] <TB1> INFO: stop marker: 0
[07:51:32.999] <TB1> INFO: overflow: 0
[07:51:32.999] <TB1> INFO: invalid 5bit words: 0
[07:51:32.999] <TB1> INFO: invalid XOR eye diagram: 0
[07:51:32.999] <TB1> INFO: frame (failed synchr.): 0
[07:51:32.999] <TB1> INFO: idle data (no TBM trl): 0
[07:51:32.999] <TB1> INFO: no data (only TBM hdr): 0
[07:51:32.999] <TB1> INFO: TBM errors: 0
[07:51:32.999] <TB1> INFO: flawed TBM headers: 0
[07:51:32.999] <TB1> INFO: flawed TBM trailers: 0
[07:51:32.999] <TB1> INFO: event ID mismatches: 0
[07:51:32.999] <TB1> INFO: ROC errors: 0
[07:51:32.999] <TB1> INFO: missing ROC header(s): 0
[07:51:32.999] <TB1> INFO: misplaced readback start: 0
[07:51:32.999] <TB1> INFO: Pixel decoding errors: 0
[07:51:32.999] <TB1> INFO: pixel data incomplete: 0
[07:51:32.999] <TB1> INFO: pixel address: 0
[07:51:32.999] <TB1> INFO: pulse height fill bit: 0
[07:51:32.999] <TB1> INFO: buffer corruption: 0
[07:51:33.635] <TB1> INFO: ######################################################################
[07:51:33.635] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[07:51:33.635] <TB1> INFO: ######################################################################
[07:51:33.916] <TB1> INFO: Expecting 41600 events.
[07:51:37.437] <TB1> INFO: 41600 events read in total (2930ms).
[07:51:37.437] <TB1> INFO: Test took 3800ms.
[07:51:37.878] <TB1> INFO: Expecting 41600 events.
[07:51:41.462] <TB1> INFO: 41600 events read in total (2992ms).
[07:51:41.463] <TB1> INFO: Test took 3823ms.
[07:51:41.755] <TB1> INFO: Expecting 41600 events.
[07:51:45.333] <TB1> INFO: 41600 events read in total (2987ms).
[07:51:45.334] <TB1> INFO: Test took 3844ms.
[07:51:45.626] <TB1> INFO: Expecting 41600 events.
[07:51:49.131] <TB1> INFO: 41600 events read in total (2914ms).
[07:51:49.132] <TB1> INFO: Test took 3771ms.
[07:51:49.425] <TB1> INFO: Expecting 41600 events.
[07:51:53.005] <TB1> INFO: 41600 events read in total (2988ms).
[07:51:53.006] <TB1> INFO: Test took 3846ms.
[07:51:53.297] <TB1> INFO: Expecting 41600 events.
[07:51:56.997] <TB1> INFO: 41600 events read in total (3108ms).
[07:51:56.998] <TB1> INFO: Test took 3966ms.
[07:51:57.287] <TB1> INFO: Expecting 41600 events.
[07:52:00.947] <TB1> INFO: 41600 events read in total (3068ms).
[07:52:00.948] <TB1> INFO: Test took 3926ms.
[07:52:01.240] <TB1> INFO: Expecting 41600 events.
[07:52:04.723] <TB1> INFO: 41600 events read in total (2891ms).
[07:52:04.724] <TB1> INFO: Test took 3749ms.
[07:52:05.014] <TB1> INFO: Expecting 41600 events.
[07:52:08.539] <TB1> INFO: 41600 events read in total (2933ms).
[07:52:08.540] <TB1> INFO: Test took 3792ms.
[07:52:08.828] <TB1> INFO: Expecting 41600 events.
[07:52:12.403] <TB1> INFO: 41600 events read in total (2983ms).
[07:52:12.404] <TB1> INFO: Test took 3840ms.
[07:52:12.693] <TB1> INFO: Expecting 41600 events.
[07:52:16.154] <TB1> INFO: 41600 events read in total (2870ms).
[07:52:16.155] <TB1> INFO: Test took 3727ms.
[07:52:16.444] <TB1> INFO: Expecting 41600 events.
[07:52:20.408] <TB1> INFO: 41600 events read in total (3372ms).
[07:52:20.409] <TB1> INFO: Test took 4229ms.
[07:52:20.764] <TB1> INFO: Expecting 41600 events.
[07:52:24.310] <TB1> INFO: 41600 events read in total (2955ms).
[07:52:24.311] <TB1> INFO: Test took 3873ms.
[07:52:24.601] <TB1> INFO: Expecting 41600 events.
[07:52:28.078] <TB1> INFO: 41600 events read in total (2886ms).
[07:52:28.079] <TB1> INFO: Test took 3744ms.
[07:52:28.368] <TB1> INFO: Expecting 41600 events.
[07:52:31.880] <TB1> INFO: 41600 events read in total (2921ms).
[07:52:31.881] <TB1> INFO: Test took 3778ms.
[07:52:32.170] <TB1> INFO: Expecting 41600 events.
[07:52:35.676] <TB1> INFO: 41600 events read in total (2914ms).
[07:52:35.677] <TB1> INFO: Test took 3772ms.
[07:52:35.967] <TB1> INFO: Expecting 41600 events.
[07:52:39.485] <TB1> INFO: 41600 events read in total (2927ms).
[07:52:39.486] <TB1> INFO: Test took 3784ms.
[07:52:39.777] <TB1> INFO: Expecting 41600 events.
[07:52:43.261] <TB1> INFO: 41600 events read in total (2892ms).
[07:52:43.262] <TB1> INFO: Test took 3750ms.
[07:52:43.550] <TB1> INFO: Expecting 41600 events.
[07:52:47.047] <TB1> INFO: 41600 events read in total (2905ms).
[07:52:47.048] <TB1> INFO: Test took 3762ms.
[07:52:47.349] <TB1> INFO: Expecting 41600 events.
[07:52:50.844] <TB1> INFO: 41600 events read in total (2904ms).
[07:52:50.845] <TB1> INFO: Test took 3773ms.
[07:52:51.134] <TB1> INFO: Expecting 41600 events.
[07:52:54.727] <TB1> INFO: 41600 events read in total (3001ms).
[07:52:54.728] <TB1> INFO: Test took 3859ms.
[07:52:55.017] <TB1> INFO: Expecting 41600 events.
[07:52:58.665] <TB1> INFO: 41600 events read in total (3056ms).
[07:52:58.666] <TB1> INFO: Test took 3914ms.
[07:52:59.017] <TB1> INFO: Expecting 41600 events.
[07:53:02.516] <TB1> INFO: 41600 events read in total (2907ms).
[07:53:02.517] <TB1> INFO: Test took 3823ms.
[07:53:02.833] <TB1> INFO: Expecting 41600 events.
[07:53:06.349] <TB1> INFO: 41600 events read in total (2924ms).
[07:53:06.350] <TB1> INFO: Test took 3805ms.
[07:53:06.678] <TB1> INFO: Expecting 41600 events.
[07:53:10.338] <TB1> INFO: 41600 events read in total (3068ms).
[07:53:10.338] <TB1> INFO: Test took 3962ms.
[07:53:10.627] <TB1> INFO: Expecting 41600 events.
[07:53:14.206] <TB1> INFO: 41600 events read in total (2987ms).
[07:53:14.207] <TB1> INFO: Test took 3845ms.
[07:53:14.496] <TB1> INFO: Expecting 41600 events.
[07:53:18.061] <TB1> INFO: 41600 events read in total (2973ms).
[07:53:18.063] <TB1> INFO: Test took 3832ms.
[07:53:18.355] <TB1> INFO: Expecting 41600 events.
[07:53:21.880] <TB1> INFO: 41600 events read in total (2933ms).
[07:53:21.881] <TB1> INFO: Test took 3791ms.
[07:53:22.172] <TB1> INFO: Expecting 41600 events.
[07:53:25.772] <TB1> INFO: 41600 events read in total (3009ms).
[07:53:25.773] <TB1> INFO: Test took 3867ms.
[07:53:26.063] <TB1> INFO: Expecting 41600 events.
[07:53:29.590] <TB1> INFO: 41600 events read in total (2936ms).
[07:53:29.591] <TB1> INFO: Test took 3793ms.
[07:53:29.921] <TB1> INFO: Expecting 41600 events.
[07:53:33.500] <TB1> INFO: 41600 events read in total (2987ms).
[07:53:33.501] <TB1> INFO: Test took 3884ms.
[07:53:33.793] <TB1> INFO: Expecting 2560 events.
[07:53:34.685] <TB1> INFO: 2560 events read in total (300ms).
[07:53:34.686] <TB1> INFO: Test took 1171ms.
[07:53:34.994] <TB1> INFO: Expecting 2560 events.
[07:53:35.891] <TB1> INFO: 2560 events read in total (305ms).
[07:53:35.891] <TB1> INFO: Test took 1205ms.
[07:53:36.199] <TB1> INFO: Expecting 2560 events.
[07:53:37.090] <TB1> INFO: 2560 events read in total (300ms).
[07:53:37.090] <TB1> INFO: Test took 1198ms.
[07:53:37.398] <TB1> INFO: Expecting 2560 events.
[07:53:38.289] <TB1> INFO: 2560 events read in total (299ms).
[07:53:38.290] <TB1> INFO: Test took 1199ms.
[07:53:38.597] <TB1> INFO: Expecting 2560 events.
[07:53:39.490] <TB1> INFO: 2560 events read in total (301ms).
[07:53:39.490] <TB1> INFO: Test took 1200ms.
[07:53:39.799] <TB1> INFO: Expecting 2560 events.
[07:53:40.679] <TB1> INFO: 2560 events read in total (288ms).
[07:53:40.680] <TB1> INFO: Test took 1189ms.
[07:53:40.986] <TB1> INFO: Expecting 2560 events.
[07:53:41.867] <TB1> INFO: 2560 events read in total (289ms).
[07:53:41.867] <TB1> INFO: Test took 1186ms.
[07:53:42.175] <TB1> INFO: Expecting 2560 events.
[07:53:43.064] <TB1> INFO: 2560 events read in total (298ms).
[07:53:43.064] <TB1> INFO: Test took 1196ms.
[07:53:43.372] <TB1> INFO: Expecting 2560 events.
[07:53:44.260] <TB1> INFO: 2560 events read in total (296ms).
[07:53:44.260] <TB1> INFO: Test took 1195ms.
[07:53:44.569] <TB1> INFO: Expecting 2560 events.
[07:53:45.454] <TB1> INFO: 2560 events read in total (294ms).
[07:53:45.454] <TB1> INFO: Test took 1193ms.
[07:53:45.762] <TB1> INFO: Expecting 2560 events.
[07:53:46.649] <TB1> INFO: 2560 events read in total (295ms).
[07:53:46.650] <TB1> INFO: Test took 1195ms.
[07:53:46.956] <TB1> INFO: Expecting 2560 events.
[07:53:47.836] <TB1> INFO: 2560 events read in total (289ms).
[07:53:47.836] <TB1> INFO: Test took 1186ms.
[07:53:48.144] <TB1> INFO: Expecting 2560 events.
[07:53:49.035] <TB1> INFO: 2560 events read in total (299ms).
[07:53:49.036] <TB1> INFO: Test took 1199ms.
[07:53:49.344] <TB1> INFO: Expecting 2560 events.
[07:53:50.227] <TB1> INFO: 2560 events read in total (292ms).
[07:53:50.227] <TB1> INFO: Test took 1191ms.
[07:53:50.535] <TB1> INFO: Expecting 2560 events.
[07:53:51.430] <TB1> INFO: 2560 events read in total (303ms).
[07:53:51.430] <TB1> INFO: Test took 1202ms.
[07:53:51.737] <TB1> INFO: Expecting 2560 events.
[07:53:52.624] <TB1> INFO: 2560 events read in total (295ms).
[07:53:52.625] <TB1> INFO: Test took 1194ms.
[07:53:52.628] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[07:53:52.933] <TB1> INFO: Expecting 655360 events.
[07:54:07.833] <TB1> INFO: 655360 events read in total (14308ms).
[07:54:07.846] <TB1> INFO: Expecting 655360 events.
[07:54:22.428] <TB1> INFO: 655360 events read in total (14179ms).
[07:54:22.451] <TB1> INFO: Expecting 655360 events.
[07:54:37.167] <TB1> INFO: 655360 events read in total (14313ms).
[07:54:37.191] <TB1> INFO: Expecting 655360 events.
[07:54:52.053] <TB1> INFO: 655360 events read in total (14459ms).
[07:54:52.079] <TB1> INFO: Expecting 655360 events.
[07:55:06.525] <TB1> INFO: 655360 events read in total (14043ms).
[07:55:06.554] <TB1> INFO: Expecting 655360 events.
[07:55:20.952] <TB1> INFO: 655360 events read in total (13995ms).
[07:55:20.988] <TB1> INFO: Expecting 655360 events.
[07:55:35.507] <TB1> INFO: 655360 events read in total (14116ms).
[07:55:35.545] <TB1> INFO: Expecting 655360 events.
[07:55:50.072] <TB1> INFO: 655360 events read in total (14123ms).
[07:55:50.126] <TB1> INFO: Expecting 655360 events.
[07:56:04.609] <TB1> INFO: 655360 events read in total (14080ms).
[07:56:04.663] <TB1> INFO: Expecting 655360 events.
[07:56:19.212] <TB1> INFO: 655360 events read in total (14146ms).
[07:56:19.311] <TB1> INFO: Expecting 655360 events.
[07:56:33.827] <TB1> INFO: 655360 events read in total (14113ms).
[07:56:33.886] <TB1> INFO: Expecting 655360 events.
[07:56:48.396] <TB1> INFO: 655360 events read in total (14107ms).
[07:56:48.545] <TB1> INFO: Expecting 655360 events.
[07:57:03.030] <TB1> INFO: 655360 events read in total (14082ms).
[07:57:03.109] <TB1> INFO: Expecting 655360 events.
[07:57:17.555] <TB1> INFO: 655360 events read in total (14043ms).
[07:57:17.676] <TB1> INFO: Expecting 655360 events.
[07:57:32.189] <TB1> INFO: 655360 events read in total (14110ms).
[07:57:32.328] <TB1> INFO: Expecting 655360 events.
[07:57:46.889] <TB1> INFO: 655360 events read in total (14158ms).
[07:57:47.053] <TB1> INFO: Test took 234425ms.
[07:57:47.150] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[07:57:47.406] <TB1> INFO: Expecting 655360 events.
[07:58:02.011] <TB1> INFO: 655360 events read in total (14013ms).
[07:58:02.024] <TB1> INFO: Expecting 655360 events.
[07:58:16.454] <TB1> INFO: 655360 events read in total (14027ms).
[07:58:16.475] <TB1> INFO: Expecting 655360 events.
[07:58:30.859] <TB1> INFO: 655360 events read in total (13981ms).
[07:58:30.883] <TB1> INFO: Expecting 655360 events.
[07:58:45.176] <TB1> INFO: 655360 events read in total (13890ms).
[07:58:45.203] <TB1> INFO: Expecting 655360 events.
[07:58:59.607] <TB1> INFO: 655360 events read in total (14001ms).
[07:58:59.646] <TB1> INFO: Expecting 655360 events.
[07:59:14.238] <TB1> INFO: 655360 events read in total (14189ms).
[07:59:14.274] <TB1> INFO: Expecting 655360 events.
[07:59:28.474] <TB1> INFO: 655360 events read in total (13797ms).
[07:59:28.512] <TB1> INFO: Expecting 655360 events.
[07:59:43.053] <TB1> INFO: 655360 events read in total (14138ms).
[07:59:43.105] <TB1> INFO: Expecting 655360 events.
[07:59:57.365] <TB1> INFO: 655360 events read in total (13857ms).
[07:59:57.414] <TB1> INFO: Expecting 655360 events.
[08:00:12.046] <TB1> INFO: 655360 events read in total (14229ms).
[08:00:12.118] <TB1> INFO: Expecting 655360 events.
[08:00:26.467] <TB1> INFO: 655360 events read in total (13946ms).
[08:00:26.530] <TB1> INFO: Expecting 655360 events.
[08:00:40.917] <TB1> INFO: 655360 events read in total (13984ms).
[08:00:40.998] <TB1> INFO: Expecting 655360 events.
[08:00:55.306] <TB1> INFO: 655360 events read in total (13904ms).
[08:00:55.405] <TB1> INFO: Expecting 655360 events.
[08:01:10.030] <TB1> INFO: 655360 events read in total (14222ms).
[08:01:10.181] <TB1> INFO: Expecting 655360 events.
[08:01:24.718] <TB1> INFO: 655360 events read in total (14134ms).
[08:01:24.812] <TB1> INFO: Expecting 655360 events.
[08:01:39.348] <TB1> INFO: 655360 events read in total (14133ms).
[08:01:39.491] <TB1> INFO: Test took 232341ms.
[08:01:39.739] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[08:01:39.747] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[08:01:39.755] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[08:01:39.763] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[08:01:39.771] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[08:01:39.779] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[08:01:39.787] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[08:01:39.795] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[08:01:39.802] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[08:01:39.810] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[08:01:39.818] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[08:01:39.826] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[08:01:39.834] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[08:01:39.842] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[08:01:39.850] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[08:01:39.858] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[08:01:39.866] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[08:01:39.874] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[08:01:39.882] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[08:01:39.889] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[08:01:39.897] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[08:01:39.905] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[08:01:39.913] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[08:01:39.921] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[08:01:39.929] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[08:01:39.937] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[08:01:39.945] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[08:01:39.953] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[08:01:39.961] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[08:01:39.969] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[08:01:39.977] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[08:01:39.985] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[08:01:39.993] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[08:01:39.001] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[08:01:40.009] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[08:01:40.017] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[08:01:40.025] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[08:01:40.033] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[08:01:40.041] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[08:01:40.049] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[08:01:40.057] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[08:01:40.098] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C0.dat
[08:01:40.098] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C1.dat
[08:01:40.099] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C2.dat
[08:01:40.099] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C3.dat
[08:01:40.099] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C4.dat
[08:01:40.099] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C5.dat
[08:01:40.099] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C6.dat
[08:01:40.100] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C7.dat
[08:01:40.100] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C8.dat
[08:01:40.100] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C9.dat
[08:01:40.100] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C10.dat
[08:01:40.100] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C11.dat
[08:01:40.101] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C12.dat
[08:01:40.101] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C13.dat
[08:01:40.101] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C14.dat
[08:01:40.101] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters35_C15.dat
[08:01:40.366] <TB1> INFO: Expecting 41600 events.
[08:01:43.568] <TB1> INFO: 41600 events read in total (2610ms).
[08:01:43.569] <TB1> INFO: Test took 3464ms.
[08:01:44.028] <TB1> INFO: Expecting 41600 events.
[08:01:47.099] <TB1> INFO: 41600 events read in total (2480ms).
[08:01:47.099] <TB1> INFO: Test took 3314ms.
[08:01:47.554] <TB1> INFO: Expecting 41600 events.
[08:01:50.708] <TB1> INFO: 41600 events read in total (2562ms).
[08:01:50.709] <TB1> INFO: Test took 3396ms.
[08:01:50.925] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:01:51.013] <TB1> INFO: Expecting 2560 events.
[08:01:51.899] <TB1> INFO: 2560 events read in total (294ms).
[08:01:51.900] <TB1> INFO: Test took 975ms.
[08:01:51.903] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:01:52.209] <TB1> INFO: Expecting 2560 events.
[08:01:53.094] <TB1> INFO: 2560 events read in total (293ms).
[08:01:53.094] <TB1> INFO: Test took 1191ms.
[08:01:53.097] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:01:53.402] <TB1> INFO: Expecting 2560 events.
[08:01:54.296] <TB1> INFO: 2560 events read in total (302ms).
[08:01:54.297] <TB1> INFO: Test took 1200ms.
[08:01:54.300] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:01:54.604] <TB1> INFO: Expecting 2560 events.
[08:01:55.502] <TB1> INFO: 2560 events read in total (306ms).
[08:01:55.502] <TB1> INFO: Test took 1202ms.
[08:01:55.505] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:01:55.810] <TB1> INFO: Expecting 2560 events.
[08:01:56.704] <TB1> INFO: 2560 events read in total (302ms).
[08:01:56.705] <TB1> INFO: Test took 1200ms.
[08:01:56.708] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:01:57.013] <TB1> INFO: Expecting 2560 events.
[08:01:57.901] <TB1> INFO: 2560 events read in total (297ms).
[08:01:57.902] <TB1> INFO: Test took 1194ms.
[08:01:57.904] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:01:58.210] <TB1> INFO: Expecting 2560 events.
[08:01:59.097] <TB1> INFO: 2560 events read in total (295ms).
[08:01:59.098] <TB1> INFO: Test took 1194ms.
[08:01:59.101] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:01:59.406] <TB1> INFO: Expecting 2560 events.
[08:02:00.291] <TB1> INFO: 2560 events read in total (292ms).
[08:02:00.291] <TB1> INFO: Test took 1190ms.
[08:02:00.294] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:00.600] <TB1> INFO: Expecting 2560 events.
[08:02:01.490] <TB1> INFO: 2560 events read in total (298ms).
[08:02:01.490] <TB1> INFO: Test took 1196ms.
[08:02:01.493] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:01.798] <TB1> INFO: Expecting 2560 events.
[08:02:02.691] <TB1> INFO: 2560 events read in total (301ms).
[08:02:02.692] <TB1> INFO: Test took 1199ms.
[08:02:02.695] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:02.999] <TB1> INFO: Expecting 2560 events.
[08:02:03.889] <TB1> INFO: 2560 events read in total (298ms).
[08:02:03.889] <TB1> INFO: Test took 1195ms.
[08:02:03.893] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:04.197] <TB1> INFO: Expecting 2560 events.
[08:02:05.084] <TB1> INFO: 2560 events read in total (295ms).
[08:02:05.085] <TB1> INFO: Test took 1192ms.
[08:02:05.088] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:05.393] <TB1> INFO: Expecting 2560 events.
[08:02:06.279] <TB1> INFO: 2560 events read in total (295ms).
[08:02:06.279] <TB1> INFO: Test took 1192ms.
[08:02:06.281] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:06.588] <TB1> INFO: Expecting 2560 events.
[08:02:07.471] <TB1> INFO: 2560 events read in total (291ms).
[08:02:07.472] <TB1> INFO: Test took 1191ms.
[08:02:07.474] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:07.781] <TB1> INFO: Expecting 2560 events.
[08:02:08.670] <TB1> INFO: 2560 events read in total (298ms).
[08:02:08.670] <TB1> INFO: Test took 1197ms.
[08:02:08.672] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:08.979] <TB1> INFO: Expecting 2560 events.
[08:02:09.862] <TB1> INFO: 2560 events read in total (291ms).
[08:02:09.863] <TB1> INFO: Test took 1191ms.
[08:02:09.865] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:10.171] <TB1> INFO: Expecting 2560 events.
[08:02:11.055] <TB1> INFO: 2560 events read in total (292ms).
[08:02:11.055] <TB1> INFO: Test took 1190ms.
[08:02:11.057] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:11.364] <TB1> INFO: Expecting 2560 events.
[08:02:13.201] <TB1> INFO: 2560 events read in total (295ms).
[08:02:13.202] <TB1> INFO: Test took 2145ms.
[08:02:13.204] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:13.514] <TB1> INFO: Expecting 2560 events.
[08:02:14.401] <TB1> INFO: 2560 events read in total (295ms).
[08:02:14.401] <TB1> INFO: Test took 1197ms.
[08:02:14.404] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:14.709] <TB1> INFO: Expecting 2560 events.
[08:02:15.600] <TB1> INFO: 2560 events read in total (298ms).
[08:02:15.600] <TB1> INFO: Test took 1197ms.
[08:02:15.602] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:15.909] <TB1> INFO: Expecting 2560 events.
[08:02:16.796] <TB1> INFO: 2560 events read in total (295ms).
[08:02:16.796] <TB1> INFO: Test took 1194ms.
[08:02:16.799] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:17.105] <TB1> INFO: Expecting 2560 events.
[08:02:17.992] <TB1> INFO: 2560 events read in total (295ms).
[08:02:17.992] <TB1> INFO: Test took 1193ms.
[08:02:17.996] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:18.301] <TB1> INFO: Expecting 2560 events.
[08:02:19.184] <TB1> INFO: 2560 events read in total (291ms).
[08:02:19.184] <TB1> INFO: Test took 1188ms.
[08:02:19.187] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:19.494] <TB1> INFO: Expecting 2560 events.
[08:02:20.380] <TB1> INFO: 2560 events read in total (294ms).
[08:02:20.381] <TB1> INFO: Test took 1195ms.
[08:02:20.384] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:20.688] <TB1> INFO: Expecting 2560 events.
[08:02:21.573] <TB1> INFO: 2560 events read in total (294ms).
[08:02:21.574] <TB1> INFO: Test took 1191ms.
[08:02:21.577] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:21.881] <TB1> INFO: Expecting 2560 events.
[08:02:22.776] <TB1> INFO: 2560 events read in total (303ms).
[08:02:22.777] <TB1> INFO: Test took 1200ms.
[08:02:22.779] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:23.085] <TB1> INFO: Expecting 2560 events.
[08:02:23.980] <TB1> INFO: 2560 events read in total (303ms).
[08:02:23.980] <TB1> INFO: Test took 1202ms.
[08:02:23.984] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:24.288] <TB1> INFO: Expecting 2560 events.
[08:02:25.181] <TB1> INFO: 2560 events read in total (302ms).
[08:02:25.181] <TB1> INFO: Test took 1197ms.
[08:02:25.185] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:25.489] <TB1> INFO: Expecting 2560 events.
[08:02:26.382] <TB1> INFO: 2560 events read in total (301ms).
[08:02:26.383] <TB1> INFO: Test took 1198ms.
[08:02:26.386] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:26.692] <TB1> INFO: Expecting 2560 events.
[08:02:27.580] <TB1> INFO: 2560 events read in total (297ms).
[08:02:27.581] <TB1> INFO: Test took 1195ms.
[08:02:27.584] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:27.889] <TB1> INFO: Expecting 2560 events.
[08:02:28.781] <TB1> INFO: 2560 events read in total (301ms).
[08:02:28.782] <TB1> INFO: Test took 1199ms.
[08:02:28.785] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:02:29.090] <TB1> INFO: Expecting 2560 events.
[08:02:29.977] <TB1> INFO: 2560 events read in total (296ms).
[08:02:29.977] <TB1> INFO: Test took 1192ms.
[08:02:30.460] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 656 seconds
[08:02:30.460] <TB1> INFO: PH scale (per ROC): 35 37 31 47 52 47 44 48 47 34 42 40 43 48 36 44
[08:02:30.460] <TB1> INFO: PH offset (per ROC): 108 83 92 103 118 109 92 89 103 84 88 97 110 116 98 99
[08:02:30.469] <TB1> INFO: Decoding statistics:
[08:02:30.469] <TB1> INFO: General information:
[08:02:30.469] <TB1> INFO: 16bit words read: 127880
[08:02:30.469] <TB1> INFO: valid events total: 20480
[08:02:30.469] <TB1> INFO: empty events: 17980
[08:02:30.469] <TB1> INFO: valid events with pixels: 2500
[08:02:30.469] <TB1> INFO: valid pixel hits: 2500
[08:02:30.469] <TB1> INFO: Event errors: 0
[08:02:30.469] <TB1> INFO: start marker: 0
[08:02:30.469] <TB1> INFO: stop marker: 0
[08:02:30.469] <TB1> INFO: overflow: 0
[08:02:30.469] <TB1> INFO: invalid 5bit words: 0
[08:02:30.469] <TB1> INFO: invalid XOR eye diagram: 0
[08:02:30.469] <TB1> INFO: frame (failed synchr.): 0
[08:02:30.469] <TB1> INFO: idle data (no TBM trl): 0
[08:02:30.469] <TB1> INFO: no data (only TBM hdr): 0
[08:02:30.469] <TB1> INFO: TBM errors: 0
[08:02:30.469] <TB1> INFO: flawed TBM headers: 0
[08:02:30.469] <TB1> INFO: flawed TBM trailers: 0
[08:02:30.469] <TB1> INFO: event ID mismatches: 0
[08:02:30.469] <TB1> INFO: ROC errors: 0
[08:02:30.469] <TB1> INFO: missing ROC header(s): 0
[08:02:30.469] <TB1> INFO: misplaced readback start: 0
[08:02:30.469] <TB1> INFO: Pixel decoding errors: 0
[08:02:30.469] <TB1> INFO: pixel data incomplete: 0
[08:02:30.469] <TB1> INFO: pixel address: 0
[08:02:30.469] <TB1> INFO: pulse height fill bit: 0
[08:02:30.469] <TB1> INFO: buffer corruption: 0
[08:02:30.634] <TB1> INFO: ######################################################################
[08:02:30.634] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[08:02:30.634] <TB1> INFO: ######################################################################
[08:02:30.650] <TB1> INFO: scanning low vcal = 10
[08:02:30.887] <TB1> INFO: Expecting 41600 events.
[08:02:34.477] <TB1> INFO: 41600 events read in total (2998ms).
[08:02:34.477] <TB1> INFO: Test took 3827ms.
[08:02:34.478] <TB1> INFO: scanning low vcal = 20
[08:02:34.775] <TB1> INFO: Expecting 41600 events.
[08:02:38.373] <TB1> INFO: 41600 events read in total (3006ms).
[08:02:38.373] <TB1> INFO: Test took 3895ms.
[08:02:38.375] <TB1> INFO: scanning low vcal = 30
[08:02:38.673] <TB1> INFO: Expecting 41600 events.
[08:02:42.342] <TB1> INFO: 41600 events read in total (3077ms).
[08:02:42.343] <TB1> INFO: Test took 3967ms.
[08:02:42.345] <TB1> INFO: scanning low vcal = 40
[08:02:42.623] <TB1> INFO: Expecting 41600 events.
[08:02:46.643] <TB1> INFO: 41600 events read in total (3429ms).
[08:02:46.645] <TB1> INFO: Test took 4300ms.
[08:02:46.648] <TB1> INFO: scanning low vcal = 50
[08:02:46.932] <TB1> INFO: Expecting 41600 events.
[08:02:50.963] <TB1> INFO: 41600 events read in total (3439ms).
[08:02:50.963] <TB1> INFO: Test took 4315ms.
[08:02:50.967] <TB1> INFO: scanning low vcal = 60
[08:02:51.244] <TB1> INFO: Expecting 41600 events.
[08:02:55.312] <TB1> INFO: 41600 events read in total (3476ms).
[08:02:55.313] <TB1> INFO: Test took 4346ms.
[08:02:55.316] <TB1> INFO: scanning low vcal = 70
[08:02:55.594] <TB1> INFO: Expecting 41600 events.
[08:02:59.633] <TB1> INFO: 41600 events read in total (3447ms).
[08:02:59.634] <TB1> INFO: Test took 4318ms.
[08:02:59.637] <TB1> INFO: scanning low vcal = 80
[08:02:59.914] <TB1> INFO: Expecting 41600 events.
[08:03:03.953] <TB1> INFO: 41600 events read in total (3447ms).
[08:03:03.954] <TB1> INFO: Test took 4317ms.
[08:03:03.957] <TB1> INFO: scanning low vcal = 90
[08:03:04.235] <TB1> INFO: Expecting 41600 events.
[08:03:08.322] <TB1> INFO: 41600 events read in total (3495ms).
[08:03:08.323] <TB1> INFO: Test took 4366ms.
[08:03:08.327] <TB1> INFO: scanning low vcal = 100
[08:03:08.604] <TB1> INFO: Expecting 41600 events.
[08:03:12.653] <TB1> INFO: 41600 events read in total (3458ms).
[08:03:12.654] <TB1> INFO: Test took 4327ms.
[08:03:12.657] <TB1> INFO: scanning low vcal = 110
[08:03:12.938] <TB1> INFO: Expecting 41600 events.
[08:03:17.020] <TB1> INFO: 41600 events read in total (3490ms).
[08:03:17.021] <TB1> INFO: Test took 4364ms.
[08:03:17.024] <TB1> INFO: scanning low vcal = 120
[08:03:17.301] <TB1> INFO: Expecting 41600 events.
[08:03:21.349] <TB1> INFO: 41600 events read in total (3456ms).
[08:03:21.349] <TB1> INFO: Test took 4325ms.
[08:03:21.352] <TB1> INFO: scanning low vcal = 130
[08:03:21.629] <TB1> INFO: Expecting 41600 events.
[08:03:25.669] <TB1> INFO: 41600 events read in total (3448ms).
[08:03:25.670] <TB1> INFO: Test took 4318ms.
[08:03:25.673] <TB1> INFO: scanning low vcal = 140
[08:03:25.950] <TB1> INFO: Expecting 41600 events.
[08:03:29.987] <TB1> INFO: 41600 events read in total (3445ms).
[08:03:29.987] <TB1> INFO: Test took 4314ms.
[08:03:29.991] <TB1> INFO: scanning low vcal = 150
[08:03:30.269] <TB1> INFO: Expecting 41600 events.
[08:03:34.348] <TB1> INFO: 41600 events read in total (3488ms).
[08:03:34.349] <TB1> INFO: Test took 4358ms.
[08:03:34.352] <TB1> INFO: scanning low vcal = 160
[08:03:34.629] <TB1> INFO: Expecting 41600 events.
[08:03:38.692] <TB1> INFO: 41600 events read in total (3471ms).
[08:03:38.693] <TB1> INFO: Test took 4341ms.
[08:03:38.696] <TB1> INFO: scanning low vcal = 170
[08:03:38.973] <TB1> INFO: Expecting 41600 events.
[08:03:43.035] <TB1> INFO: 41600 events read in total (3470ms).
[08:03:43.036] <TB1> INFO: Test took 4340ms.
[08:03:43.042] <TB1> INFO: scanning low vcal = 180
[08:03:43.317] <TB1> INFO: Expecting 41600 events.
[08:03:47.400] <TB1> INFO: 41600 events read in total (3492ms).
[08:03:47.401] <TB1> INFO: Test took 4359ms.
[08:03:47.405] <TB1> INFO: scanning low vcal = 190
[08:03:47.681] <TB1> INFO: Expecting 41600 events.
[08:03:51.710] <TB1> INFO: 41600 events read in total (3437ms).
[08:03:51.711] <TB1> INFO: Test took 4306ms.
[08:03:51.714] <TB1> INFO: scanning low vcal = 200
[08:03:51.991] <TB1> INFO: Expecting 41600 events.
[08:03:56.033] <TB1> INFO: 41600 events read in total (3450ms).
[08:03:56.034] <TB1> INFO: Test took 4320ms.
[08:03:56.038] <TB1> INFO: scanning low vcal = 210
[08:03:56.315] <TB1> INFO: Expecting 41600 events.
[08:04:00.376] <TB1> INFO: 41600 events read in total (3470ms).
[08:04:00.376] <TB1> INFO: Test took 4338ms.
[08:04:00.380] <TB1> INFO: scanning low vcal = 220
[08:04:00.657] <TB1> INFO: Expecting 41600 events.
[08:04:04.610] <TB1> INFO: 41600 events read in total (3362ms).
[08:04:04.610] <TB1> INFO: Test took 4230ms.
[08:04:04.615] <TB1> INFO: scanning low vcal = 230
[08:04:04.890] <TB1> INFO: Expecting 41600 events.
[08:04:08.845] <TB1> INFO: 41600 events read in total (3361ms).
[08:04:08.846] <TB1> INFO: Test took 4231ms.
[08:04:08.849] <TB1> INFO: scanning low vcal = 240
[08:04:09.125] <TB1> INFO: Expecting 41600 events.
[08:04:13.066] <TB1> INFO: 41600 events read in total (3349ms).
[08:04:13.067] <TB1> INFO: Test took 4218ms.
[08:04:13.070] <TB1> INFO: scanning low vcal = 250
[08:04:13.347] <TB1> INFO: Expecting 41600 events.
[08:04:17.306] <TB1> INFO: 41600 events read in total (3367ms).
[08:04:17.307] <TB1> INFO: Test took 4237ms.
[08:04:17.311] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[08:04:17.587] <TB1> INFO: Expecting 41600 events.
[08:04:21.547] <TB1> INFO: 41600 events read in total (3368ms).
[08:04:21.548] <TB1> INFO: Test took 4237ms.
[08:04:21.552] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[08:04:21.828] <TB1> INFO: Expecting 41600 events.
[08:04:25.795] <TB1> INFO: 41600 events read in total (3372ms).
[08:04:25.796] <TB1> INFO: Test took 4244ms.
[08:04:25.799] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[08:04:26.075] <TB1> INFO: Expecting 41600 events.
[08:04:30.031] <TB1> INFO: 41600 events read in total (3364ms).
[08:04:30.032] <TB1> INFO: Test took 4233ms.
[08:04:30.037] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[08:04:30.312] <TB1> INFO: Expecting 41600 events.
[08:04:34.351] <TB1> INFO: 41600 events read in total (3446ms).
[08:04:34.352] <TB1> INFO: Test took 4315ms.
[08:04:34.355] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[08:04:34.632] <TB1> INFO: Expecting 41600 events.
[08:04:38.671] <TB1> INFO: 41600 events read in total (3447ms).
[08:04:38.672] <TB1> INFO: Test took 4317ms.
[08:04:39.273] <TB1> INFO: PixTestGainPedestal::measure() done
[08:05:15.594] <TB1> INFO: PixTestGainPedestal::fit() done
[08:05:15.594] <TB1> INFO: non-linearity mean: 0.924 1.025 1.026 0.964 0.978 0.938 0.944 0.960 0.970 0.977 0.915 0.926 0.948 0.980 0.936 0.949
[08:05:15.594] <TB1> INFO: non-linearity RMS: 0.085 0.141 0.191 0.037 0.004 0.088 0.078 0.046 0.017 0.217 0.115 0.162 0.046 0.004 0.161 0.045
[08:05:15.594] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[08:05:15.608] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[08:05:15.622] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[08:05:15.636] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[08:05:15.649] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[08:05:15.662] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[08:05:15.675] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[08:05:15.689] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[08:05:15.702] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[08:05:15.715] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[08:05:15.728] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[08:05:15.741] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[08:05:15.754] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[08:05:15.767] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[08:05:15.780] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[08:05:15.794] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[08:05:15.807] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 165 seconds
[08:05:15.807] <TB1> INFO: Decoding statistics:
[08:05:15.807] <TB1> INFO: General information:
[08:05:15.807] <TB1> INFO: 16bit words read: 3273320
[08:05:15.807] <TB1> INFO: valid events total: 332800
[08:05:15.807] <TB1> INFO: empty events: 1284
[08:05:15.807] <TB1> INFO: valid events with pixels: 331516
[08:05:15.807] <TB1> INFO: valid pixel hits: 638260
[08:05:15.807] <TB1> INFO: Event errors: 0
[08:05:15.807] <TB1> INFO: start marker: 0
[08:05:15.807] <TB1> INFO: stop marker: 0
[08:05:15.807] <TB1> INFO: overflow: 0
[08:05:15.807] <TB1> INFO: invalid 5bit words: 0
[08:05:15.807] <TB1> INFO: invalid XOR eye diagram: 0
[08:05:15.807] <TB1> INFO: frame (failed synchr.): 0
[08:05:15.807] <TB1> INFO: idle data (no TBM trl): 0
[08:05:15.807] <TB1> INFO: no data (only TBM hdr): 0
[08:05:15.807] <TB1> INFO: TBM errors: 0
[08:05:15.807] <TB1> INFO: flawed TBM headers: 0
[08:05:15.807] <TB1> INFO: flawed TBM trailers: 0
[08:05:15.807] <TB1> INFO: event ID mismatches: 0
[08:05:15.807] <TB1> INFO: ROC errors: 0
[08:05:15.807] <TB1> INFO: missing ROC header(s): 0
[08:05:15.807] <TB1> INFO: misplaced readback start: 0
[08:05:15.807] <TB1> INFO: Pixel decoding errors: 0
[08:05:15.807] <TB1> INFO: pixel data incomplete: 0
[08:05:15.807] <TB1> INFO: pixel address: 0
[08:05:15.807] <TB1> INFO: pulse height fill bit: 0
[08:05:15.807] <TB1> INFO: buffer corruption: 0
[08:05:15.825] <TB1> INFO: Decoding statistics:
[08:05:15.825] <TB1> INFO: General information:
[08:05:15.825] <TB1> INFO: 16bit words read: 3402736
[08:05:15.825] <TB1> INFO: valid events total: 353536
[08:05:15.825] <TB1> INFO: empty events: 19520
[08:05:15.825] <TB1> INFO: valid events with pixels: 334016
[08:05:15.825] <TB1> INFO: valid pixel hits: 640760
[08:05:15.825] <TB1> INFO: Event errors: 0
[08:05:15.825] <TB1> INFO: start marker: 0
[08:05:15.825] <TB1> INFO: stop marker: 0
[08:05:15.825] <TB1> INFO: overflow: 0
[08:05:15.825] <TB1> INFO: invalid 5bit words: 0
[08:05:15.825] <TB1> INFO: invalid XOR eye diagram: 0
[08:05:15.825] <TB1> INFO: frame (failed synchr.): 0
[08:05:15.825] <TB1> INFO: idle data (no TBM trl): 0
[08:05:15.825] <TB1> INFO: no data (only TBM hdr): 0
[08:05:15.825] <TB1> INFO: TBM errors: 0
[08:05:15.825] <TB1> INFO: flawed TBM headers: 0
[08:05:15.825] <TB1> INFO: flawed TBM trailers: 0
[08:05:15.825] <TB1> INFO: event ID mismatches: 0
[08:05:15.825] <TB1> INFO: ROC errors: 0
[08:05:15.825] <TB1> INFO: missing ROC header(s): 0
[08:05:15.825] <TB1> INFO: misplaced readback start: 0
[08:05:15.825] <TB1> INFO: Pixel decoding errors: 0
[08:05:15.825] <TB1> INFO: pixel data incomplete: 0
[08:05:15.825] <TB1> INFO: pixel address: 0
[08:05:15.825] <TB1> INFO: pulse height fill bit: 0
[08:05:15.825] <TB1> INFO: buffer corruption: 0
[08:05:15.825] <TB1> INFO: enter test to run
[08:05:15.825] <TB1> INFO: test: trim80 no parameter change
[08:05:15.825] <TB1> INFO: running: trim80
[08:05:15.826] <TB1> INFO: ######################################################################
[08:05:15.826] <TB1> INFO: PixTestTrim80::doTest()
[08:05:15.826] <TB1> INFO: ######################################################################
[08:05:15.828] <TB1> INFO: ----------------------------------------------------------------------
[08:05:15.828] <TB1> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[08:05:15.828] <TB1> INFO: ----------------------------------------------------------------------
[08:05:15.869] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[08:05:15.869] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[08:05:15.883] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[08:05:15.883] <TB1> INFO: run 1 of 1
[08:05:16.119] <TB1> INFO: Expecting 5025280 events.
[08:05:43.882] <TB1> INFO: 682920 events read in total (27172ms).
[08:06:11.669] <TB1> INFO: 1362440 events read in total (54959ms).
[08:06:39.377] <TB1> INFO: 2040440 events read in total (82667ms).
[08:07:06.839] <TB1> INFO: 2716432 events read in total (110129ms).
[08:07:34.285] <TB1> INFO: 3390032 events read in total (137575ms).
[08:08:02.042] <TB1> INFO: 4062496 events read in total (165332ms).
[08:08:29.401] <TB1> INFO: 4736488 events read in total (192691ms).
[08:08:41.335] <TB1> INFO: 5025280 events read in total (204625ms).
[08:08:41.431] <TB1> INFO: Test took 205549ms.
[08:09:05.659] <TB1> INFO: ROC 0 VthrComp = 78
[08:09:05.659] <TB1> INFO: ROC 1 VthrComp = 70
[08:09:05.659] <TB1> INFO: ROC 2 VthrComp = 75
[08:09:05.659] <TB1> INFO: ROC 3 VthrComp = 73
[08:09:05.659] <TB1> INFO: ROC 4 VthrComp = 76
[08:09:05.659] <TB1> INFO: ROC 5 VthrComp = 80
[08:09:05.660] <TB1> INFO: ROC 6 VthrComp = 79
[08:09:05.660] <TB1> INFO: ROC 7 VthrComp = 80
[08:09:05.660] <TB1> INFO: ROC 8 VthrComp = 91
[08:09:05.660] <TB1> INFO: ROC 9 VthrComp = 83
[08:09:05.660] <TB1> INFO: ROC 10 VthrComp = 86
[08:09:05.660] <TB1> INFO: ROC 11 VthrComp = 77
[08:09:05.660] <TB1> INFO: ROC 12 VthrComp = 75
[08:09:05.660] <TB1> INFO: ROC 13 VthrComp = 75
[08:09:05.660] <TB1> INFO: ROC 14 VthrComp = 79
[08:09:05.661] <TB1> INFO: ROC 15 VthrComp = 98
[08:09:05.940] <TB1> INFO: Expecting 41600 events.
[08:09:09.384] <TB1> INFO: 41600 events read in total (2852ms).
[08:09:09.386] <TB1> INFO: Test took 3724ms.
[08:09:09.397] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[08:09:09.397] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[08:09:09.414] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[08:09:09.414] <TB1> INFO: run 1 of 1
[08:09:09.692] <TB1> INFO: Expecting 5025280 events.
[08:09:37.843] <TB1> INFO: 686008 events read in total (27559ms).
[08:10:06.602] <TB1> INFO: 1370216 events read in total (56318ms).
[08:10:34.370] <TB1> INFO: 2053488 events read in total (84086ms).
[08:11:01.929] <TB1> INFO: 2733920 events read in total (111645ms).
[08:11:29.041] <TB1> INFO: 3410624 events read in total (138757ms).
[08:11:57.228] <TB1> INFO: 4085304 events read in total (166944ms).
[08:12:24.535] <TB1> INFO: 4759936 events read in total (194251ms).
[08:12:35.291] <TB1> INFO: 5025280 events read in total (205007ms).
[08:12:35.356] <TB1> INFO: Test took 205941ms.
[08:12:56.515] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 110 for pixel 0/70 mean/min/max = 94.0481/77.9722/110.124
[08:12:56.515] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 104.337 for pixel 51/73 mean/min/max = 89.2567/73.9431/104.57
[08:12:56.516] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 111.786 for pixel 0/2 mean/min/max = 94.7876/77.6906/111.885
[08:12:56.517] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 109.843 for pixel 51/8 mean/min/max = 94.2578/78.5518/109.964
[08:12:56.517] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 109.436 for pixel 15/1 mean/min/max = 94.5438/79.6166/109.471
[08:12:56.518] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 106.488 for pixel 6/2 mean/min/max = 91.4614/76.1497/106.773
[08:12:56.519] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 110.534 for pixel 51/68 mean/min/max = 94.1267/77.4589/110.795
[08:12:56.519] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 109.354 for pixel 0/43 mean/min/max = 91.9916/74.5506/109.433
[08:12:56.520] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 109.302 for pixel 19/69 mean/min/max = 92.579/75.5729/109.585
[08:12:56.521] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 107.272 for pixel 2/70 mean/min/max = 91.2022/74.8532/107.551
[08:12:56.521] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 108.274 for pixel 3/12 mean/min/max = 91.3482/74.2293/108.467
[08:12:56.522] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 111.36 for pixel 0/65 mean/min/max = 94.3945/77.4212/111.368
[08:12:56.522] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 108.886 for pixel 46/79 mean/min/max = 93.1941/77.4971/108.891
[08:12:56.523] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 110.362 for pixel 0/10 mean/min/max = 94.2834/77.9802/110.586
[08:12:56.523] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 111.926 for pixel 5/62 mean/min/max = 94.41/76.788/112.032
[08:12:56.524] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 106.688 for pixel 12/7 mean/min/max = 90.8625/74.9726/106.752
[08:12:56.524] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:12:56.613] <TB1> INFO: Expecting 411648 events.
[08:13:05.954] <TB1> INFO: 411648 events read in total (8749ms).
[08:13:05.964] <TB1> INFO: Expecting 411648 events.
[08:13:15.257] <TB1> INFO: 411648 events read in total (8890ms).
[08:13:15.272] <TB1> INFO: Expecting 411648 events.
[08:13:24.574] <TB1> INFO: 411648 events read in total (8899ms).
[08:13:24.588] <TB1> INFO: Expecting 411648 events.
[08:13:33.885] <TB1> INFO: 411648 events read in total (8894ms).
[08:13:33.902] <TB1> INFO: Expecting 411648 events.
[08:13:43.055] <TB1> INFO: 411648 events read in total (8750ms).
[08:13:43.075] <TB1> INFO: Expecting 411648 events.
[08:13:52.208] <TB1> INFO: 411648 events read in total (8723ms).
[08:13:52.237] <TB1> INFO: Expecting 411648 events.
[08:14:01.665] <TB1> INFO: 411648 events read in total (9025ms).
[08:14:01.697] <TB1> INFO: Expecting 411648 events.
[08:14:11.099] <TB1> INFO: 411648 events read in total (8999ms).
[08:14:11.127] <TB1> INFO: Expecting 411648 events.
[08:14:20.531] <TB1> INFO: 411648 events read in total (9001ms).
[08:14:20.586] <TB1> INFO: Expecting 411648 events.
[08:14:30.081] <TB1> INFO: 411648 events read in total (9092ms).
[08:14:30.126] <TB1> INFO: Expecting 411648 events.
[08:14:39.564] <TB1> INFO: 411648 events read in total (9035ms).
[08:14:39.607] <TB1> INFO: Expecting 411648 events.
[08:14:48.968] <TB1> INFO: 411648 events read in total (8958ms).
[08:14:49.010] <TB1> INFO: Expecting 411648 events.
[08:14:58.270] <TB1> INFO: 411648 events read in total (8857ms).
[08:14:58.320] <TB1> INFO: Expecting 411648 events.
[08:15:07.831] <TB1> INFO: 411648 events read in total (9108ms).
[08:15:07.878] <TB1> INFO: Expecting 411648 events.
[08:15:17.090] <TB1> INFO: 411648 events read in total (8809ms).
[08:15:17.180] <TB1> INFO: Expecting 411648 events.
[08:15:26.374] <TB1> INFO: 411648 events read in total (8791ms).
[08:15:26.438] <TB1> INFO: Test took 149914ms.
[08:15:27.883] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[08:15:27.897] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[08:15:27.897] <TB1> INFO: run 1 of 1
[08:15:28.149] <TB1> INFO: Expecting 5025280 events.
[08:15:56.229] <TB1> INFO: 669544 events read in total (27488ms).
[08:16:23.578] <TB1> INFO: 1336712 events read in total (54837ms).
[08:16:51.072] <TB1> INFO: 2003784 events read in total (82331ms).
[08:17:18.700] <TB1> INFO: 2668928 events read in total (109959ms).
[08:17:46.064] <TB1> INFO: 3329656 events read in total (137323ms).
[08:18:13.315] <TB1> INFO: 3989240 events read in total (164574ms).
[08:18:40.240] <TB1> INFO: 4647848 events read in total (191499ms).
[08:18:55.548] <TB1> INFO: 5025280 events read in total (206807ms).
[08:18:55.617] <TB1> INFO: Test took 207720ms.
[08:19:17.422] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 53.049460 .. 106.060761
[08:19:17.665] <TB1> INFO: Expecting 208000 events.
[08:19:27.487] <TB1> INFO: 208000 events read in total (9230ms).
[08:19:27.488] <TB1> INFO: Test took 10065ms.
[08:19:27.550] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 43 .. 116 (-1/-1) hits flags = 528 (plus default)
[08:19:27.564] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[08:19:27.564] <TB1> INFO: run 1 of 1
[08:19:27.847] <TB1> INFO: Expecting 2462720 events.
[08:19:56.293] <TB1> INFO: 672368 events read in total (27854ms).
[08:20:24.542] <TB1> INFO: 1345616 events read in total (56103ms).
[08:20:51.959] <TB1> INFO: 2013776 events read in total (83520ms).
[08:21:10.324] <TB1> INFO: 2462720 events read in total (101885ms).
[08:21:10.378] <TB1> INFO: Test took 102815ms.
[08:21:29.850] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 59.891901 .. 94.070872
[08:21:30.130] <TB1> INFO: Expecting 208000 events.
[08:21:39.886] <TB1> INFO: 208000 events read in total (9164ms).
[08:21:39.888] <TB1> INFO: Test took 10036ms.
[08:21:39.948] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 49 .. 104 (-1/-1) hits flags = 528 (plus default)
[08:21:39.963] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[08:21:39.963] <TB1> INFO: run 1 of 1
[08:21:40.242] <TB1> INFO: Expecting 1863680 events.
[08:22:08.753] <TB1> INFO: 689808 events read in total (27919ms).
[08:22:36.496] <TB1> INFO: 1378968 events read in total (55663ms).
[08:22:55.989] <TB1> INFO: 1863680 events read in total (75155ms).
[08:22:56.027] <TB1> INFO: Test took 76064ms.
[08:23:14.643] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 64.813881 .. 90.706673
[08:23:14.881] <TB1> INFO: Expecting 208000 events.
[08:23:24.917] <TB1> INFO: 208000 events read in total (9445ms).
[08:23:24.918] <TB1> INFO: Test took 10273ms.
[08:23:24.975] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 54 .. 100 (-1/-1) hits flags = 528 (plus default)
[08:23:24.989] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[08:23:24.989] <TB1> INFO: run 1 of 1
[08:23:25.267] <TB1> INFO: Expecting 1564160 events.
[08:23:54.087] <TB1> INFO: 690928 events read in total (28228ms).
[08:24:22.082] <TB1> INFO: 1380784 events read in total (56223ms).
[08:24:30.136] <TB1> INFO: 1564160 events read in total (64277ms).
[08:24:30.169] <TB1> INFO: Test took 65180ms.
[08:24:48.515] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 66.697051 .. 90.372839
[08:24:48.766] <TB1> INFO: Expecting 208000 events.
[08:24:59.137] <TB1> INFO: 208000 events read in total (9779ms).
[08:24:59.138] <TB1> INFO: Test took 10620ms.
[08:24:59.192] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 56 .. 100 (-1/-1) hits flags = 528 (plus default)
[08:24:59.206] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[08:24:59.206] <TB1> INFO: run 1 of 1
[08:24:59.484] <TB1> INFO: Expecting 1497600 events.
[08:25:28.171] <TB1> INFO: 684328 events read in total (28095ms).
[08:25:55.950] <TB1> INFO: 1368664 events read in total (55875ms).
[08:26:01.632] <TB1> INFO: 1497600 events read in total (61556ms).
[08:26:01.670] <TB1> INFO: Test took 62465ms.
[08:26:19.976] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[08:26:19.976] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[08:26:19.991] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[08:26:19.991] <TB1> INFO: run 1 of 1
[08:26:20.230] <TB1> INFO: Expecting 1364480 events.
[08:26:48.878] <TB1> INFO: 667920 events read in total (28056ms).
[08:27:16.624] <TB1> INFO: 1335792 events read in total (55803ms).
[08:27:18.237] <TB1> INFO: 1364480 events read in total (57415ms).
[08:27:18.269] <TB1> INFO: Test took 58279ms.
[08:27:36.613] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters80_C0.dat
[08:27:36.614] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters80_C1.dat
[08:27:36.614] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters80_C2.dat
[08:27:36.614] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters80_C3.dat
[08:27:36.614] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters80_C4.dat
[08:27:36.614] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters80_C5.dat
[08:27:36.614] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters80_C6.dat
[08:27:36.614] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters80_C7.dat
[08:27:36.614] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters80_C8.dat
[08:27:36.615] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters80_C9.dat
[08:27:36.615] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters80_C10.dat
[08:27:36.615] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters80_C11.dat
[08:27:36.615] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters80_C12.dat
[08:27:36.615] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters80_C13.dat
[08:27:36.615] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters80_C14.dat
[08:27:36.615] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//dacParameters80_C15.dat
[08:27:36.615] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters80_C0.dat
[08:27:36.621] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters80_C1.dat
[08:27:36.626] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters80_C2.dat
[08:27:36.630] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters80_C3.dat
[08:27:36.635] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters80_C4.dat
[08:27:36.640] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters80_C5.dat
[08:27:36.645] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters80_C6.dat
[08:27:36.650] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters80_C7.dat
[08:27:36.655] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters80_C8.dat
[08:27:36.661] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters80_C9.dat
[08:27:36.666] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters80_C10.dat
[08:27:36.671] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters80_C11.dat
[08:27:36.677] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters80_C12.dat
[08:27:36.682] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters80_C13.dat
[08:27:36.687] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters80_C14.dat
[08:27:36.692] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1081_FullQualification_2016-11-03_14h08m_1478178483//003_FulltestTrim80_p17//trimParameters80_C15.dat
[08:27:36.697] <TB1> INFO: PixTestTrim80::trimTest() done
[08:27:36.697] <TB1> INFO: vtrim: 94 84 104 99 104 101 113 110 115 96 95 103 109 96 115 113
[08:27:36.697] <TB1> INFO: vthrcomp: 78 70 75 73 76 80 79 80 91 83 86 77 75 75 79 98
[08:27:36.697] <TB1> INFO: vcal mean: 79.98 79.93 79.95 79.98 79.95 79.98 79.99 79.95 79.93 80.01 79.98 79.97 79.95 79.89 79.94 79.97
[08:27:36.697] <TB1> INFO: vcal RMS: 0.72 1.45 0.81 0.72 0.70 0.71 0.80 0.75 0.78 0.76 0.77 0.72 0.71 0.68 0.73 0.82
[08:27:36.697] <TB1> INFO: bits mean: 8.92 10.17 9.18 8.61 9.03 9.82 9.40 9.98 9.99 9.77 9.90 8.89 9.45 8.92 9.63 10.24
[08:27:36.697] <TB1> INFO: bits RMS: 2.42 2.59 2.37 2.49 2.17 2.35 2.30 2.45 2.29 2.58 2.57 2.41 2.30 2.34 2.24 2.30
[08:27:36.704] <TB1> INFO: ----------------------------------------------------------------------
[08:27:36.704] <TB1> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[08:27:36.704] <TB1> INFO: ----------------------------------------------------------------------
[08:27:36.706] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[08:27:36.720] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[08:27:36.720] <TB1> INFO: run 1 of 1
[08:27:36.957] <TB1> INFO: Expecting 4160000 events.
[08:28:09.525] <TB1> INFO: 767570 events read in total (31976ms).
[08:28:41.585] <TB1> INFO: 1532145 events read in total (64036ms).
[08:29:13.512] <TB1> INFO: 2293695 events read in total (95963ms).
[08:29:45.338] <TB1> INFO: 3051835 events read in total (127789ms).
[08:30:17.169] <TB1> INFO: 3806160 events read in total (159620ms).
[08:30:32.333] <TB1> INFO: 4160000 events read in total (174784ms).
[08:30:32.415] <TB1> INFO: Test took 175695ms.
[08:30:59.072] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[08:30:59.085] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[08:30:59.085] <TB1> INFO: run 1 of 1
[08:30:59.323] <TB1> INFO: Expecting 5324800 events.
[08:31:30.127] <TB1> INFO: 683555 events read in total (30212ms).
[08:32:00.048] <TB1> INFO: 1365500 events read in total (60133ms).
[08:32:30.315] <TB1> INFO: 2046005 events read in total (90400ms).
[08:33:00.315] <TB1> INFO: 2725890 events read in total (120400ms).
[08:33:29.799] <TB1> INFO: 3404055 events read in total (149884ms).
[08:33:59.891] <TB1> INFO: 4080445 events read in total (179976ms).
[08:34:30.098] <TB1> INFO: 4755860 events read in total (210183ms).
[08:34:55.684] <TB1> INFO: 5324800 events read in total (235769ms).
[08:34:55.844] <TB1> INFO: Test took 236758ms.
[08:35:26.686] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 210 (-1/-1) hits flags = 528 (plus default)
[08:35:26.700] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[08:35:26.700] <TB1> INFO: run 1 of 1
[08:35:26.938] <TB1> INFO: Expecting 4388800 events.
[08:35:58.791] <TB1> INFO: 727775 events read in total (31262ms).
[08:36:31.302] <TB1> INFO: 1453465 events read in total (63773ms).
[08:37:03.134] <TB1> INFO: 2176665 events read in total (95605ms).
[08:37:34.823] <TB1> INFO: 2897285 events read in total (127294ms).
[08:38:05.811] <TB1> INFO: 3615120 events read in total (158282ms).
[08:38:37.369] <TB1> INFO: 4334640 events read in total (189840ms).
[08:38:40.102] <TB1> INFO: 4388800 events read in total (192573ms).
[08:38:40.209] <TB1> INFO: Test took 193509ms.
[08:39:05.512] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 213 (-1/-1) hits flags = 528 (plus default)
[08:39:05.526] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[08:39:05.526] <TB1> INFO: run 1 of 1
[08:39:05.763] <TB1> INFO: Expecting 4451200 events.
[08:39:36.865] <TB1> INFO: 723960 events read in total (30510ms).
[08:40:08.456] <TB1> INFO: 1445680 events read in total (62101ms).
[08:40:38.934] <TB1> INFO: 2165555 events read in total (92579ms).
[08:41:10.182] <TB1> INFO: 2882635 events read in total (123827ms).
[08:41:41.179] <TB1> INFO: 3597370 events read in total (154824ms).
[08:42:12.484] <TB1> INFO: 4312450 events read in total (186129ms).
[08:42:18.768] <TB1> INFO: 4451200 events read in total (192413ms).
[08:42:18.856] <TB1> INFO: Test took 193330ms.
[08:42:43.471] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 213 (-1/-1) hits flags = 528 (plus default)
[08:42:43.485] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[08:42:43.485] <TB1> INFO: run 1 of 1
[08:42:43.734] <TB1> INFO: Expecting 4451200 events.
[08:43:15.577] <TB1> INFO: 724200 events read in total (31251ms).
[08:43:47.627] <TB1> INFO: 1445945 events read in total (63301ms).
[08:44:19.433] <TB1> INFO: 2165675 events read in total (95107ms).
[08:44:51.270] <TB1> INFO: 2882975 events read in total (126944ms).
[08:45:23.165] <TB1> INFO: 3597960 events read in total (158839ms).
[08:45:55.952] <TB1> INFO: 4313445 events read in total (191626ms).
[08:46:02.705] <TB1> INFO: 4451200 events read in total (198379ms).
[08:46:02.822] <TB1> INFO: Test took 199337ms.
[08:46:26.212] <TB1> INFO: PixTestTrim80::trimBitTest() done
[08:46:26.213] <TB1> INFO: PixTestTrim80::doTest() done, duration: 2470 seconds
[08:46:26.873] <TB1> INFO: enter test to run
[08:46:26.873] <TB1> INFO: test: exit no parameter change
[08:46:27.066] <TB1> QUIET: Connection to board 154 closed.
[08:46:27.068] <TB1> INFO: pXar: this is the end, my friend