[16:34:50.599] <TB2> INFO: *** Welcome to pxar ***
[16:34:50.599] <TB2> INFO: *** Today: 2016/10/25
[16:34:50.605] <TB2> INFO: *** Version: c8ba-dirty
[16:34:50.605] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C15.dat
[16:34:50.606] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//tbmParameters_C1b.dat
[16:34:50.606] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//defaultMaskFile.dat
[16:34:50.606] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters_C15.dat
[16:34:50.661] <TB2> INFO: clk: 4
[16:34:50.661] <TB2> INFO: ctr: 4
[16:34:50.661] <TB2> INFO: sda: 19
[16:34:50.661] <TB2> INFO: tin: 9
[16:34:50.661] <TB2> INFO: level: 15
[16:34:50.661] <TB2> INFO: triggerdelay: 0
[16:34:50.661] <TB2> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[16:34:50.661] <TB2> INFO: Log level: INFO
[16:34:50.670] <TB2> INFO: Found DTB DTB_WXC55Z
[16:34:50.681] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[16:34:50.683] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[16:34:50.684] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[16:34:52.167] <TB2> INFO: DUT info:
[16:34:52.167] <TB2> INFO: The DUT currently contains the following objects:
[16:34:52.167] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[16:34:52.167] <TB2> INFO: TBM Core alpha (0): 7 registers set
[16:34:52.167] <TB2> INFO: TBM Core beta (1): 7 registers set
[16:34:52.167] <TB2> INFO: TBM Core alpha (2): 7 registers set
[16:34:52.167] <TB2> INFO: TBM Core beta (3): 7 registers set
[16:34:52.167] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[16:34:52.167] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:52.167] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:52.167] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:52.167] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:52.167] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:52.167] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:52.167] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:52.167] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:52.167] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:52.167] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:52.167] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:52.167] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:52.167] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:52.167] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:52.168] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:52.168] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:52.568] <TB2> INFO: enter 'restricted' command line mode
[16:34:52.568] <TB2> INFO: enter test to run
[16:34:52.568] <TB2> INFO: test: pretest no parameter change
[16:34:52.568] <TB2> INFO: running: pretest
[16:34:53.148] <TB2> INFO: ######################################################################
[16:34:53.148] <TB2> INFO: PixTestPretest::doTest()
[16:34:53.148] <TB2> INFO: ######################################################################
[16:34:53.149] <TB2> INFO: ----------------------------------------------------------------------
[16:34:53.149] <TB2> INFO: PixTestPretest::programROC()
[16:34:53.149] <TB2> INFO: ----------------------------------------------------------------------
[16:35:11.162] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[16:35:11.162] <TB2> INFO: IA differences per ROC: 18.5 17.7 16.9 17.7 19.3 19.3 16.9 18.5 18.5 20.9 18.5 16.9 20.1 16.1 18.5 20.1
[16:35:11.197] <TB2> INFO: ----------------------------------------------------------------------
[16:35:11.197] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[16:35:11.198] <TB2> INFO: ----------------------------------------------------------------------
[16:35:18.379] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 384.3 mA = 24.0187 mA/ROC
[16:35:18.379] <TB2> INFO: i(loss) [mA/ROC]: 20.1 20.1 19.3 20.1 20.1 19.3 20.1 20.1 20.1 20.1 19.3 20.1 20.1 19.3 19.3 19.3
[16:35:18.407] <TB2> INFO: ----------------------------------------------------------------------
[16:35:18.407] <TB2> INFO: PixTestPretest::findTiming()
[16:35:18.407] <TB2> INFO: ----------------------------------------------------------------------
[16:35:18.407] <TB2> INFO: PixTestCmd::init()

[16:35:49.654] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[16:35:49.654] <TB2> INFO: (success/tries = 100/100), width = 3
[16:35:51.162] <TB2> INFO: ----------------------------------------------------------------------
[16:35:51.162] <TB2> INFO: PixTestPretest::findWorkingPixel()
[16:35:51.162] <TB2> INFO: ----------------------------------------------------------------------
[16:35:51.253] <TB2> INFO: Expecting 231680 events.
[16:36:00.829] <TB2> INFO: 231680 events read in total (8984ms).
[16:36:00.837] <TB2> INFO: Test took 9673ms.
[16:36:01.083] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[16:36:01.113] <TB2> INFO: ----------------------------------------------------------------------
[16:36:01.113] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[16:36:01.113] <TB2> INFO: ----------------------------------------------------------------------
[16:36:01.205] <TB2> INFO: Expecting 231680 events.
[16:36:10.860] <TB2> INFO: 231680 events read in total (9063ms).
[16:36:10.866] <TB2> INFO: Test took 9749ms.
[16:36:11.125] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[16:36:11.125] <TB2> INFO: CalDel: 82 94 95 109 120 105 108 118 106 115 81 98 137 104 110 102
[16:36:11.125] <TB2> INFO: VthrComp: 54 51 51 51 51 51 51 51 51 51 51 56 51 51 57 51
[16:36:11.128] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C0.dat
[16:36:11.128] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C1.dat
[16:36:11.128] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C2.dat
[16:36:11.128] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C3.dat
[16:36:11.128] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C4.dat
[16:36:11.128] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C5.dat
[16:36:11.128] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C6.dat
[16:36:11.128] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C7.dat
[16:36:11.128] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C8.dat
[16:36:11.128] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C9.dat
[16:36:11.129] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C10.dat
[16:36:11.129] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C11.dat
[16:36:11.129] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C12.dat
[16:36:11.129] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C13.dat
[16:36:11.129] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C14.dat
[16:36:11.129] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C15.dat
[16:36:11.129] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//tbmParameters_C0a.dat
[16:36:11.129] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//tbmParameters_C0b.dat
[16:36:11.129] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//tbmParameters_C1a.dat
[16:36:11.129] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//tbmParameters_C1b.dat
[16:36:11.130] <TB2> INFO: PixTestPretest::doTest() done, duration: 78 seconds
[16:36:11.226] <TB2> INFO: enter test to run
[16:36:11.226] <TB2> INFO: test: FullTest no parameter change
[16:36:11.226] <TB2> INFO: running: fulltest
[16:36:11.226] <TB2> INFO: ######################################################################
[16:36:11.226] <TB2> INFO: PixTestFullTest::doTest()
[16:36:11.226] <TB2> INFO: ######################################################################
[16:36:11.227] <TB2> INFO: ######################################################################
[16:36:11.227] <TB2> INFO: PixTestAlive::doTest()
[16:36:11.227] <TB2> INFO: ######################################################################
[16:36:11.228] <TB2> INFO: ----------------------------------------------------------------------
[16:36:11.228] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:36:11.228] <TB2> INFO: ----------------------------------------------------------------------
[16:36:11.461] <TB2> INFO: Expecting 41600 events.
[16:36:14.916] <TB2> INFO: 41600 events read in total (2863ms).
[16:36:14.917] <TB2> INFO: Test took 3688ms.
[16:36:15.144] <TB2> INFO: PixTestAlive::aliveTest() done
[16:36:15.144] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[16:36:15.146] <TB2> INFO: ----------------------------------------------------------------------
[16:36:15.146] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:36:15.146] <TB2> INFO: ----------------------------------------------------------------------
[16:36:15.380] <TB2> INFO: Expecting 41600 events.
[16:36:18.302] <TB2> INFO: 41600 events read in total (2330ms).
[16:36:18.302] <TB2> INFO: Test took 3155ms.
[16:36:18.303] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[16:36:18.542] <TB2> INFO: PixTestAlive::maskTest() done
[16:36:18.542] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[16:36:18.544] <TB2> INFO: ----------------------------------------------------------------------
[16:36:18.544] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:36:18.544] <TB2> INFO: ----------------------------------------------------------------------
[16:36:18.777] <TB2> INFO: Expecting 41600 events.
[16:36:22.183] <TB2> INFO: 41600 events read in total (2815ms).
[16:36:22.183] <TB2> INFO: Test took 3638ms.
[16:36:22.411] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[16:36:22.411] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[16:36:22.411] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[16:36:22.411] <TB2> INFO: Decoding statistics:
[16:36:22.411] <TB2> INFO: General information:
[16:36:22.411] <TB2> INFO: 16bit words read: 0
[16:36:22.411] <TB2> INFO: valid events total: 0
[16:36:22.411] <TB2> INFO: empty events: 0
[16:36:22.411] <TB2> INFO: valid events with pixels: 0
[16:36:22.411] <TB2> INFO: valid pixel hits: 0
[16:36:22.411] <TB2> INFO: Event errors: 0
[16:36:22.411] <TB2> INFO: start marker: 0
[16:36:22.411] <TB2> INFO: stop marker: 0
[16:36:22.411] <TB2> INFO: overflow: 0
[16:36:22.411] <TB2> INFO: invalid 5bit words: 0
[16:36:22.411] <TB2> INFO: invalid XOR eye diagram: 0
[16:36:22.411] <TB2> INFO: frame (failed synchr.): 0
[16:36:22.411] <TB2> INFO: idle data (no TBM trl): 0
[16:36:22.411] <TB2> INFO: no data (only TBM hdr): 0
[16:36:22.411] <TB2> INFO: TBM errors: 0
[16:36:22.411] <TB2> INFO: flawed TBM headers: 0
[16:36:22.411] <TB2> INFO: flawed TBM trailers: 0
[16:36:22.411] <TB2> INFO: event ID mismatches: 0
[16:36:22.411] <TB2> INFO: ROC errors: 0
[16:36:22.411] <TB2> INFO: missing ROC header(s): 0
[16:36:22.411] <TB2> INFO: misplaced readback start: 0
[16:36:22.411] <TB2> INFO: Pixel decoding errors: 0
[16:36:22.411] <TB2> INFO: pixel data incomplete: 0
[16:36:22.411] <TB2> INFO: pixel address: 0
[16:36:22.411] <TB2> INFO: pulse height fill bit: 0
[16:36:22.411] <TB2> INFO: buffer corruption: 0
[16:36:22.418] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C15.dat
[16:36:22.418] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[16:36:22.418] <TB2> INFO: ######################################################################
[16:36:22.418] <TB2> INFO: PixTestReadback::doTest()
[16:36:22.418] <TB2> INFO: ######################################################################
[16:36:22.418] <TB2> INFO: ----------------------------------------------------------------------
[16:36:22.418] <TB2> INFO: PixTestReadback::CalibrateVd()
[16:36:22.418] <TB2> INFO: ----------------------------------------------------------------------
[16:36:32.392] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C0.dat
[16:36:32.392] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C1.dat
[16:36:32.392] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C2.dat
[16:36:32.392] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C3.dat
[16:36:32.392] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C4.dat
[16:36:32.392] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C5.dat
[16:36:32.393] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C6.dat
[16:36:32.393] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C7.dat
[16:36:32.393] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C8.dat
[16:36:32.393] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C9.dat
[16:36:32.393] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C10.dat
[16:36:32.393] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C11.dat
[16:36:32.393] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C12.dat
[16:36:32.393] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C13.dat
[16:36:32.393] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C14.dat
[16:36:32.393] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C15.dat
[16:36:32.421] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:36:32.421] <TB2> INFO: ----------------------------------------------------------------------
[16:36:32.421] <TB2> INFO: PixTestReadback::CalibrateVa()
[16:36:32.421] <TB2> INFO: ----------------------------------------------------------------------
[16:36:42.312] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C0.dat
[16:36:42.312] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C1.dat
[16:36:42.312] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C2.dat
[16:36:42.312] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C3.dat
[16:36:42.313] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C4.dat
[16:36:42.313] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C5.dat
[16:36:42.313] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C6.dat
[16:36:42.313] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C7.dat
[16:36:42.313] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C8.dat
[16:36:42.313] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C9.dat
[16:36:42.313] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C10.dat
[16:36:42.313] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C11.dat
[16:36:42.313] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C12.dat
[16:36:42.313] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C13.dat
[16:36:42.313] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C14.dat
[16:36:42.313] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C15.dat
[16:36:42.341] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:36:42.341] <TB2> INFO: ----------------------------------------------------------------------
[16:36:42.341] <TB2> INFO: PixTestReadback::readbackVbg()
[16:36:42.341] <TB2> INFO: ----------------------------------------------------------------------
[16:36:49.984] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:36:49.984] <TB2> INFO: ----------------------------------------------------------------------
[16:36:49.984] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[16:36:49.984] <TB2> INFO: ----------------------------------------------------------------------
[16:36:49.984] <TB2> INFO: Vbg will be calibrated using Vd calibration
[16:36:49.984] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 156.2calibrated Vbg = 1.15902 :::*/*/*/*/
[16:36:49.984] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 160.6calibrated Vbg = 1.15612 :::*/*/*/*/
[16:36:49.984] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 157.6calibrated Vbg = 1.15577 :::*/*/*/*/
[16:36:49.984] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 162.2calibrated Vbg = 1.15286 :::*/*/*/*/
[16:36:49.984] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 146.3calibrated Vbg = 1.15363 :::*/*/*/*/
[16:36:49.984] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 151.2calibrated Vbg = 1.15855 :::*/*/*/*/
[16:36:49.984] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 164.7calibrated Vbg = 1.16591 :::*/*/*/*/
[16:36:49.984] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 159.6calibrated Vbg = 1.17017 :::*/*/*/*/
[16:36:49.984] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 157.9calibrated Vbg = 1.15748 :::*/*/*/*/
[16:36:49.984] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 151.1calibrated Vbg = 1.15376 :::*/*/*/*/
[16:36:49.984] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 152.5calibrated Vbg = 1.14938 :::*/*/*/*/
[16:36:49.984] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 161.2calibrated Vbg = 1.14367 :::*/*/*/*/
[16:36:49.984] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 159calibrated Vbg = 1.15974 :::*/*/*/*/
[16:36:49.984] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 151.7calibrated Vbg = 1.15612 :::*/*/*/*/
[16:36:49.984] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 150.9calibrated Vbg = 1.15992 :::*/*/*/*/
[16:36:49.984] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 158.6calibrated Vbg = 1.16337 :::*/*/*/*/
[16:36:49.986] <TB2> INFO: ----------------------------------------------------------------------
[16:36:49.986] <TB2> INFO: PixTestReadback::CalibrateIa()
[16:36:49.986] <TB2> INFO: ----------------------------------------------------------------------
[16:39:30.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C0.dat
[16:39:30.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C1.dat
[16:39:30.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C2.dat
[16:39:30.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C3.dat
[16:39:30.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C4.dat
[16:39:30.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C5.dat
[16:39:30.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C6.dat
[16:39:30.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C7.dat
[16:39:30.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C8.dat
[16:39:30.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C9.dat
[16:39:30.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C10.dat
[16:39:30.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C11.dat
[16:39:30.302] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C12.dat
[16:39:30.302] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C13.dat
[16:39:30.302] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C14.dat
[16:39:30.302] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C15.dat
[16:39:30.329] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:39:30.331] <TB2> INFO: PixTestReadback::doTest() done
[16:39:30.331] <TB2> INFO: Decoding statistics:
[16:39:30.331] <TB2> INFO: General information:
[16:39:30.331] <TB2> INFO: 16bit words read: 1536
[16:39:30.331] <TB2> INFO: valid events total: 256
[16:39:30.331] <TB2> INFO: empty events: 256
[16:39:30.331] <TB2> INFO: valid events with pixels: 0
[16:39:30.331] <TB2> INFO: valid pixel hits: 0
[16:39:30.331] <TB2> INFO: Event errors: 0
[16:39:30.331] <TB2> INFO: start marker: 0
[16:39:30.331] <TB2> INFO: stop marker: 0
[16:39:30.331] <TB2> INFO: overflow: 0
[16:39:30.331] <TB2> INFO: invalid 5bit words: 0
[16:39:30.331] <TB2> INFO: invalid XOR eye diagram: 0
[16:39:30.331] <TB2> INFO: frame (failed synchr.): 0
[16:39:30.331] <TB2> INFO: idle data (no TBM trl): 0
[16:39:30.331] <TB2> INFO: no data (only TBM hdr): 0
[16:39:30.331] <TB2> INFO: TBM errors: 0
[16:39:30.331] <TB2> INFO: flawed TBM headers: 0
[16:39:30.331] <TB2> INFO: flawed TBM trailers: 0
[16:39:30.331] <TB2> INFO: event ID mismatches: 0
[16:39:30.331] <TB2> INFO: ROC errors: 0
[16:39:30.331] <TB2> INFO: missing ROC header(s): 0
[16:39:30.331] <TB2> INFO: misplaced readback start: 0
[16:39:30.331] <TB2> INFO: Pixel decoding errors: 0
[16:39:30.331] <TB2> INFO: pixel data incomplete: 0
[16:39:30.331] <TB2> INFO: pixel address: 0
[16:39:30.331] <TB2> INFO: pulse height fill bit: 0
[16:39:30.331] <TB2> INFO: buffer corruption: 0
[16:39:30.379] <TB2> INFO: ######################################################################
[16:39:30.379] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[16:39:30.379] <TB2> INFO: ######################################################################
[16:39:30.382] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[16:39:30.396] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:39:30.396] <TB2> INFO: run 1 of 1
[16:39:30.640] <TB2> INFO: Expecting 3120000 events.
[16:40:00.941] <TB2> INFO: 671845 events read in total (29709ms).











[16:40:30.681] <TB2> INFO: 1341725 events read in total (59449ms).











[16:41:00.468] <TB2> INFO: 2011260 events read in total (89236ms).











[16:41:30.582] <TB2> INFO: 2680380 events read in total (119350ms).











[16:41:50.550] <TB2> INFO: 3120000 events read in total (139318ms).
[16:41:50.616] <TB2> INFO: Test took 140221ms.
[16:42:15.665] <TB2> INFO: PixTestBBMap::doTest() done with 4 decoding errors: , duration: 165 seconds
[16:42:15.665] <TB2> INFO: number of dead bumps (per ROC): 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[16:42:15.665] <TB2> INFO: separation cut (per ROC): 112 106 103 105 106 103 106 102 101 104 109 118 105 105 107 104
[16:42:15.665] <TB2> INFO: Decoding statistics:
[16:42:15.665] <TB2> INFO: General information:
[16:42:15.665] <TB2> INFO: 16bit words read: 0
[16:42:15.665] <TB2> INFO: valid events total: 0
[16:42:15.665] <TB2> INFO: empty events: 0
[16:42:15.665] <TB2> INFO: valid events with pixels: 0
[16:42:15.665] <TB2> INFO: valid pixel hits: 0
[16:42:15.665] <TB2> INFO: Event errors: 0
[16:42:15.665] <TB2> INFO: start marker: 0
[16:42:15.665] <TB2> INFO: stop marker: 0
[16:42:15.665] <TB2> INFO: overflow: 0
[16:42:15.666] <TB2> INFO: invalid 5bit words: 0
[16:42:15.666] <TB2> INFO: invalid XOR eye diagram: 0
[16:42:15.666] <TB2> INFO: frame (failed synchr.): 0
[16:42:15.666] <TB2> INFO: idle data (no TBM trl): 0
[16:42:15.666] <TB2> INFO: no data (only TBM hdr): 0
[16:42:15.666] <TB2> INFO: TBM errors: 0
[16:42:15.666] <TB2> INFO: flawed TBM headers: 0
[16:42:15.666] <TB2> INFO: flawed TBM trailers: 0
[16:42:15.666] <TB2> INFO: event ID mismatches: 0
[16:42:15.666] <TB2> INFO: ROC errors: 0
[16:42:15.666] <TB2> INFO: missing ROC header(s): 0
[16:42:15.666] <TB2> INFO: misplaced readback start: 0
[16:42:15.666] <TB2> INFO: Pixel decoding errors: 0
[16:42:15.666] <TB2> INFO: pixel data incomplete: 0
[16:42:15.666] <TB2> INFO: pixel address: 0
[16:42:15.666] <TB2> INFO: pulse height fill bit: 0
[16:42:15.666] <TB2> INFO: buffer corruption: 0
[16:42:15.703] <TB2> INFO: ######################################################################
[16:42:15.703] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:42:15.703] <TB2> INFO: ######################################################################
[16:42:15.703] <TB2> INFO: ----------------------------------------------------------------------
[16:42:15.703] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:42:15.703] <TB2> INFO: ----------------------------------------------------------------------
[16:42:15.703] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[16:42:15.714] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[16:42:15.714] <TB2> INFO: run 1 of 1
[16:42:15.980] <TB2> INFO: Expecting 36608000 events.
[16:42:39.164] <TB2> INFO: 670700 events read in total (22592ms).
[16:43:01.896] <TB2> INFO: 1332800 events read in total (45324ms).
[16:43:24.247] <TB2> INFO: 1991050 events read in total (67675ms).
[16:43:46.654] <TB2> INFO: 2648350 events read in total (90082ms).
[16:44:09.191] <TB2> INFO: 3308400 events read in total (112619ms).
[16:44:31.800] <TB2> INFO: 3968750 events read in total (135228ms).
[16:44:54.234] <TB2> INFO: 4627950 events read in total (157662ms).
[16:45:16.582] <TB2> INFO: 5286350 events read in total (180010ms).
[16:45:38.879] <TB2> INFO: 5945400 events read in total (202307ms).
[16:46:01.397] <TB2> INFO: 6602750 events read in total (224825ms).
[16:46:23.856] <TB2> INFO: 7259250 events read in total (247284ms).
[16:46:46.276] <TB2> INFO: 7918000 events read in total (269704ms).
[16:47:08.857] <TB2> INFO: 8577250 events read in total (292285ms).
[16:47:31.380] <TB2> INFO: 9236650 events read in total (314808ms).
[16:47:54.034] <TB2> INFO: 9895950 events read in total (337462ms).
[16:48:16.551] <TB2> INFO: 10554000 events read in total (359979ms).
[16:48:38.728] <TB2> INFO: 11210450 events read in total (382156ms).
[16:49:00.798] <TB2> INFO: 11867750 events read in total (404226ms).
[16:49:23.206] <TB2> INFO: 12521400 events read in total (426634ms).
[16:49:45.909] <TB2> INFO: 13178600 events read in total (449337ms).
[16:50:08.430] <TB2> INFO: 13835350 events read in total (471858ms).
[16:50:30.769] <TB2> INFO: 14492450 events read in total (494197ms).
[16:50:53.252] <TB2> INFO: 15149850 events read in total (516680ms).
[16:51:15.801] <TB2> INFO: 15806200 events read in total (539229ms).
[16:51:38.469] <TB2> INFO: 16462000 events read in total (561897ms).
[16:52:01.049] <TB2> INFO: 17115450 events read in total (584477ms).
[16:52:23.655] <TB2> INFO: 17769150 events read in total (607083ms).
[16:52:45.942] <TB2> INFO: 18422900 events read in total (629371ms).
[16:53:08.414] <TB2> INFO: 19076250 events read in total (651842ms).
[16:53:30.972] <TB2> INFO: 19728850 events read in total (674400ms).
[16:53:53.554] <TB2> INFO: 20380300 events read in total (696982ms).
[16:54:16.161] <TB2> INFO: 21031300 events read in total (719589ms).
[16:54:38.388] <TB2> INFO: 21682100 events read in total (741816ms).
[16:55:00.988] <TB2> INFO: 22333100 events read in total (764416ms).
[16:55:23.285] <TB2> INFO: 22984750 events read in total (786713ms).
[16:55:45.678] <TB2> INFO: 23637200 events read in total (809106ms).
[16:56:07.898] <TB2> INFO: 24287900 events read in total (831326ms).
[16:56:30.174] <TB2> INFO: 24940050 events read in total (853602ms).
[16:56:52.326] <TB2> INFO: 25591950 events read in total (875754ms).
[16:57:14.642] <TB2> INFO: 26244450 events read in total (898070ms).
[16:57:36.864] <TB2> INFO: 26893550 events read in total (920292ms).
[16:57:59.209] <TB2> INFO: 27544700 events read in total (942637ms).
[16:58:21.434] <TB2> INFO: 28195300 events read in total (964862ms).
[16:58:43.864] <TB2> INFO: 28845250 events read in total (987292ms).
[16:59:06.280] <TB2> INFO: 29495100 events read in total (1009708ms).
[16:59:28.747] <TB2> INFO: 30145900 events read in total (1032175ms).
[16:59:51.148] <TB2> INFO: 30795200 events read in total (1054576ms).
[17:00:13.260] <TB2> INFO: 31446150 events read in total (1076688ms).
[17:00:35.617] <TB2> INFO: 32096550 events read in total (1099045ms).
[17:00:57.908] <TB2> INFO: 32748100 events read in total (1121336ms).
[17:01:20.038] <TB2> INFO: 33401100 events read in total (1143466ms).
[17:01:42.272] <TB2> INFO: 34052950 events read in total (1165700ms).
[17:02:04.452] <TB2> INFO: 34704000 events read in total (1187880ms).
[17:02:26.874] <TB2> INFO: 35355450 events read in total (1210302ms).
[17:02:49.063] <TB2> INFO: 36008400 events read in total (1232491ms).
[17:03:09.426] <TB2> INFO: 36608000 events read in total (1252854ms).
[17:03:09.497] <TB2> INFO: Test took 1253783ms.
[17:03:09.941] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:03:11.760] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:03:13.876] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:03:15.831] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:03:17.791] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:03:19.838] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:03:21.711] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:03:23.655] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:03:25.615] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:03:27.745] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:03:29.823] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:03:31.801] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:03:33.852] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:03:35.883] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:03:38.080] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:03:39.975] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:03:42.038] <TB2> INFO: PixTestScurves::scurves() done
[17:03:42.038] <TB2> INFO: Vcal mean: 118.81 118.98 109.60 108.23 109.89 104.26 114.11 109.75 106.67 110.15 119.66 119.52 112.53 109.92 115.15 112.00
[17:03:42.038] <TB2> INFO: Vcal RMS: 6.21 5.97 5.33 5.00 4.73 5.31 5.37 4.98 5.24 4.97 6.03 5.98 5.26 5.19 7.15 5.17
[17:03:42.038] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1286 seconds
[17:03:42.038] <TB2> INFO: Decoding statistics:
[17:03:42.038] <TB2> INFO: General information:
[17:03:42.038] <TB2> INFO: 16bit words read: 0
[17:03:42.038] <TB2> INFO: valid events total: 0
[17:03:42.038] <TB2> INFO: empty events: 0
[17:03:42.038] <TB2> INFO: valid events with pixels: 0
[17:03:42.038] <TB2> INFO: valid pixel hits: 0
[17:03:42.038] <TB2> INFO: Event errors: 0
[17:03:42.038] <TB2> INFO: start marker: 0
[17:03:42.038] <TB2> INFO: stop marker: 0
[17:03:42.038] <TB2> INFO: overflow: 0
[17:03:42.038] <TB2> INFO: invalid 5bit words: 0
[17:03:42.038] <TB2> INFO: invalid XOR eye diagram: 0
[17:03:42.038] <TB2> INFO: frame (failed synchr.): 0
[17:03:42.038] <TB2> INFO: idle data (no TBM trl): 0
[17:03:42.038] <TB2> INFO: no data (only TBM hdr): 0
[17:03:42.038] <TB2> INFO: TBM errors: 0
[17:03:42.038] <TB2> INFO: flawed TBM headers: 0
[17:03:42.038] <TB2> INFO: flawed TBM trailers: 0
[17:03:42.038] <TB2> INFO: event ID mismatches: 0
[17:03:42.038] <TB2> INFO: ROC errors: 0
[17:03:42.038] <TB2> INFO: missing ROC header(s): 0
[17:03:42.038] <TB2> INFO: misplaced readback start: 0
[17:03:42.038] <TB2> INFO: Pixel decoding errors: 0
[17:03:42.038] <TB2> INFO: pixel data incomplete: 0
[17:03:42.038] <TB2> INFO: pixel address: 0
[17:03:42.038] <TB2> INFO: pulse height fill bit: 0
[17:03:42.038] <TB2> INFO: buffer corruption: 0
[17:03:42.126] <TB2> INFO: ######################################################################
[17:03:42.126] <TB2> INFO: PixTestTrim::doTest()
[17:03:42.126] <TB2> INFO: ######################################################################
[17:03:42.127] <TB2> INFO: ----------------------------------------------------------------------
[17:03:42.127] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[17:03:42.127] <TB2> INFO: ----------------------------------------------------------------------
[17:03:42.170] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[17:03:42.170] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:03:42.180] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:03:42.180] <TB2> INFO: run 1 of 1
[17:03:42.428] <TB2> INFO: Expecting 5025280 events.
[17:04:12.610] <TB2> INFO: 822984 events read in total (29588ms).
[17:04:42.167] <TB2> INFO: 1643864 events read in total (59145ms).
[17:05:11.845] <TB2> INFO: 2460904 events read in total (88823ms).
[17:05:41.452] <TB2> INFO: 3275272 events read in total (118430ms).
[17:06:10.933] <TB2> INFO: 4086432 events read in total (147912ms).
[17:06:40.905] <TB2> INFO: 4894688 events read in total (177883ms).
[17:06:45.986] <TB2> INFO: 5025280 events read in total (182964ms).
[17:06:46.055] <TB2> INFO: Test took 183875ms.
[17:07:05.171] <TB2> INFO: ROC 0 VthrComp = 128
[17:07:05.172] <TB2> INFO: ROC 1 VthrComp = 125
[17:07:05.172] <TB2> INFO: ROC 2 VthrComp = 111
[17:07:05.172] <TB2> INFO: ROC 3 VthrComp = 114
[17:07:05.172] <TB2> INFO: ROC 4 VthrComp = 114
[17:07:05.172] <TB2> INFO: ROC 5 VthrComp = 108
[17:07:05.172] <TB2> INFO: ROC 6 VthrComp = 118
[17:07:05.173] <TB2> INFO: ROC 7 VthrComp = 110
[17:07:05.173] <TB2> INFO: ROC 8 VthrComp = 112
[17:07:05.173] <TB2> INFO: ROC 9 VthrComp = 116
[17:07:05.173] <TB2> INFO: ROC 10 VthrComp = 119
[17:07:05.173] <TB2> INFO: ROC 11 VthrComp = 130
[17:07:05.173] <TB2> INFO: ROC 12 VthrComp = 109
[17:07:05.174] <TB2> INFO: ROC 13 VthrComp = 106
[17:07:05.174] <TB2> INFO: ROC 14 VthrComp = 117
[17:07:05.174] <TB2> INFO: ROC 15 VthrComp = 115
[17:07:05.502] <TB2> INFO: Expecting 41600 events.
[17:07:09.076] <TB2> INFO: 41600 events read in total (2982ms).
[17:07:09.077] <TB2> INFO: Test took 3901ms.
[17:07:09.089] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[17:07:09.089] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:07:09.100] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:07:09.100] <TB2> INFO: run 1 of 1
[17:07:09.378] <TB2> INFO: Expecting 5025280 events.
[17:07:35.503] <TB2> INFO: 592624 events read in total (25533ms).
[17:08:00.740] <TB2> INFO: 1183360 events read in total (50770ms).
[17:08:25.891] <TB2> INFO: 1774208 events read in total (75921ms).
[17:08:51.175] <TB2> INFO: 2363848 events read in total (101205ms).
[17:09:16.710] <TB2> INFO: 2951192 events read in total (126740ms).
[17:09:41.841] <TB2> INFO: 3537056 events read in total (151871ms).
[17:10:06.938] <TB2> INFO: 4122440 events read in total (176968ms).
[17:10:32.278] <TB2> INFO: 4707224 events read in total (202308ms).
[17:10:46.364] <TB2> INFO: 5025280 events read in total (216395ms).
[17:10:46.437] <TB2> INFO: Test took 217337ms.
[17:11:14.874] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 60.9686 for pixel 31/5 mean/min/max = 46.4945/31.8156/61.1734
[17:11:14.874] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 59.4096 for pixel 12/15 mean/min/max = 45.5158/31.0289/60.0028
[17:11:14.875] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 62.8525 for pixel 9/0 mean/min/max = 48.4121/33.8754/62.9487
[17:11:14.875] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 59.1672 for pixel 8/78 mean/min/max = 45.7017/32.0696/59.3339
[17:11:14.875] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 60.0245 for pixel 0/5 mean/min/max = 46.1483/32.2397/60.057
[17:11:14.876] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 59.866 for pixel 0/62 mean/min/max = 47.3823/34.8252/59.9395
[17:11:14.876] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 59.1921 for pixel 16/0 mean/min/max = 45.7285/32.1549/59.3021
[17:11:14.877] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 62.2924 for pixel 2/79 mean/min/max = 48.1432/33.9837/62.3027
[17:11:14.877] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 59.9312 for pixel 0/79 mean/min/max = 46.1935/32.1914/60.1957
[17:11:14.877] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 59.0817 for pixel 0/20 mean/min/max = 45.4159/31.6783/59.1534
[17:11:14.878] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 61.7838 for pixel 22/13 mean/min/max = 46.2719/30.6628/61.8811
[17:11:14.878] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 60.9694 for pixel 8/18 mean/min/max = 46.381/31.407/61.3551
[17:11:14.879] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 62.5706 for pixel 34/12 mean/min/max = 48.1724/33.6717/62.673
[17:11:14.879] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 65.4262 for pixel 1/0 mean/min/max = 49.8095/34.065/65.554
[17:11:14.879] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 63.6364 for pixel 4/49 mean/min/max = 47.4947/31.296/63.6934
[17:11:14.880] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 59.791 for pixel 11/69 mean/min/max = 46.0356/32.1648/59.9065
[17:11:14.880] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:11:14.969] <TB2> INFO: Expecting 411648 events.
[17:11:24.254] <TB2> INFO: 411648 events read in total (8693ms).
[17:11:24.261] <TB2> INFO: Expecting 411648 events.
[17:11:33.258] <TB2> INFO: 411648 events read in total (8595ms).
[17:11:33.267] <TB2> INFO: Expecting 411648 events.
[17:11:42.321] <TB2> INFO: 411648 events read in total (8652ms).
[17:11:42.333] <TB2> INFO: Expecting 411648 events.
[17:11:51.341] <TB2> INFO: 411648 events read in total (8605ms).
[17:11:51.355] <TB2> INFO: Expecting 411648 events.
[17:12:00.397] <TB2> INFO: 411648 events read in total (8639ms).
[17:12:00.418] <TB2> INFO: Expecting 411648 events.
[17:12:09.369] <TB2> INFO: 411648 events read in total (8548ms).
[17:12:09.395] <TB2> INFO: Expecting 411648 events.
[17:12:18.421] <TB2> INFO: 411648 events read in total (8624ms).
[17:12:18.443] <TB2> INFO: Expecting 411648 events.
[17:12:27.491] <TB2> INFO: 411648 events read in total (8645ms).
[17:12:27.515] <TB2> INFO: Expecting 411648 events.
[17:12:36.437] <TB2> INFO: 411648 events read in total (8519ms).
[17:12:36.464] <TB2> INFO: Expecting 411648 events.
[17:12:45.443] <TB2> INFO: 411648 events read in total (8576ms).
[17:12:45.470] <TB2> INFO: Expecting 411648 events.
[17:12:54.540] <TB2> INFO: 411648 events read in total (8667ms).
[17:12:54.582] <TB2> INFO: Expecting 411648 events.
[17:13:03.610] <TB2> INFO: 411648 events read in total (8625ms).
[17:13:03.646] <TB2> INFO: Expecting 411648 events.
[17:13:12.655] <TB2> INFO: 411648 events read in total (8606ms).
[17:13:12.693] <TB2> INFO: Expecting 411648 events.
[17:13:21.733] <TB2> INFO: 411648 events read in total (8637ms).
[17:13:21.787] <TB2> INFO: Expecting 411648 events.
[17:13:30.808] <TB2> INFO: 411648 events read in total (8618ms).
[17:13:30.849] <TB2> INFO: Expecting 411648 events.
[17:13:39.933] <TB2> INFO: 411648 events read in total (8681ms).
[17:13:39.994] <TB2> INFO: Test took 145114ms.
[17:13:40.686] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[17:13:40.694] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:13:40.695] <TB2> INFO: run 1 of 1
[17:13:40.947] <TB2> INFO: Expecting 5025280 events.
[17:14:07.101] <TB2> INFO: 587376 events read in total (25563ms).
[17:14:32.556] <TB2> INFO: 1175216 events read in total (51017ms).
[17:14:58.059] <TB2> INFO: 1761816 events read in total (76520ms).
[17:15:23.585] <TB2> INFO: 2347512 events read in total (102046ms).
[17:15:49.459] <TB2> INFO: 2933680 events read in total (127920ms).
[17:16:15.061] <TB2> INFO: 3520648 events read in total (153522ms).
[17:16:40.383] <TB2> INFO: 4106776 events read in total (178844ms).
[17:17:06.130] <TB2> INFO: 4691304 events read in total (204591ms).
[17:17:20.840] <TB2> INFO: 5025280 events read in total (219302ms).
[17:17:20.933] <TB2> INFO: Test took 220239ms.
[17:17:45.898] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 1.516668 .. 146.795000
[17:17:46.195] <TB2> INFO: Expecting 208000 events.
[17:17:55.774] <TB2> INFO: 208000 events read in total (8987ms).
[17:17:55.775] <TB2> INFO: Test took 9876ms.
[17:17:55.857] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 1 .. 156 (-1/-1) hits flags = 528 (plus default)
[17:17:55.869] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:17:55.869] <TB2> INFO: run 1 of 1
[17:17:56.147] <TB2> INFO: Expecting 5191680 events.
[17:18:22.203] <TB2> INFO: 583896 events read in total (25464ms).
[17:18:47.843] <TB2> INFO: 1168080 events read in total (51104ms).
[17:19:12.769] <TB2> INFO: 1752160 events read in total (76030ms).
[17:19:38.032] <TB2> INFO: 2336008 events read in total (101293ms).
[17:20:03.461] <TB2> INFO: 2919752 events read in total (126722ms).
[17:20:28.574] <TB2> INFO: 3502720 events read in total (151835ms).
[17:20:53.879] <TB2> INFO: 4086024 events read in total (177140ms).
[17:21:19.141] <TB2> INFO: 4668712 events read in total (202402ms).
[17:21:42.304] <TB2> INFO: 5191680 events read in total (225565ms).
[17:21:42.375] <TB2> INFO: Test took 226507ms.
[17:22:08.565] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.311657 .. 46.213638
[17:22:08.807] <TB2> INFO: Expecting 208000 events.
[17:22:18.705] <TB2> INFO: 208000 events read in total (9306ms).
[17:22:18.706] <TB2> INFO: Test took 10139ms.
[17:22:18.772] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[17:22:18.783] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:22:18.783] <TB2> INFO: run 1 of 1
[17:22:19.061] <TB2> INFO: Expecting 1331200 events.
[17:22:46.651] <TB2> INFO: 654760 events read in total (26998ms).
[17:23:13.709] <TB2> INFO: 1307944 events read in total (54056ms).
[17:23:15.138] <TB2> INFO: 1331200 events read in total (55486ms).
[17:23:15.163] <TB2> INFO: Test took 56380ms.
[17:23:28.940] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 26.722424 .. 46.511592
[17:23:29.190] <TB2> INFO: Expecting 208000 events.
[17:23:38.938] <TB2> INFO: 208000 events read in total (9156ms).
[17:23:38.938] <TB2> INFO: Test took 9996ms.
[17:23:38.985] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 56 (-1/-1) hits flags = 528 (plus default)
[17:23:38.995] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:23:38.995] <TB2> INFO: run 1 of 1
[17:23:39.273] <TB2> INFO: Expecting 1364480 events.
[17:24:07.453] <TB2> INFO: 659672 events read in total (27589ms).
[17:24:34.663] <TB2> INFO: 1317832 events read in total (54799ms).
[17:24:37.089] <TB2> INFO: 1364480 events read in total (57226ms).
[17:24:37.111] <TB2> INFO: Test took 58117ms.
[17:24:51.430] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 25.579844 .. 45.049257
[17:24:51.691] <TB2> INFO: Expecting 208000 events.
[17:25:01.643] <TB2> INFO: 208000 events read in total (9360ms).
[17:25:01.644] <TB2> INFO: Test took 10212ms.
[17:25:01.714] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[17:25:01.725] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:25:01.725] <TB2> INFO: run 1 of 1
[17:25:01.003] <TB2> INFO: Expecting 1364480 events.
[17:25:30.640] <TB2> INFO: 667216 events read in total (28045ms).
[17:25:57.838] <TB2> INFO: 1334296 events read in total (55243ms).
[17:25:59.477] <TB2> INFO: 1364480 events read in total (56882ms).
[17:25:59.511] <TB2> INFO: Test took 57786ms.
[17:26:13.689] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[17:26:13.689] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[17:26:13.700] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:26:13.700] <TB2> INFO: run 1 of 1
[17:26:13.942] <TB2> INFO: Expecting 1364480 events.
[17:26:42.201] <TB2> INFO: 667432 events read in total (27661ms).
[17:27:09.275] <TB2> INFO: 1333888 events read in total (54736ms).
[17:27:10.908] <TB2> INFO: 1364480 events read in total (56368ms).
[17:27:10.934] <TB2> INFO: Test took 57235ms.
[17:27:24.923] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C0.dat
[17:27:24.924] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C1.dat
[17:27:24.924] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C2.dat
[17:27:24.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C3.dat
[17:27:24.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C4.dat
[17:27:24.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C5.dat
[17:27:24.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C6.dat
[17:27:24.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C7.dat
[17:27:24.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C8.dat
[17:27:24.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C9.dat
[17:27:24.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C10.dat
[17:27:24.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C11.dat
[17:27:24.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C12.dat
[17:27:24.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C13.dat
[17:27:24.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C14.dat
[17:27:24.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C15.dat
[17:27:24.927] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C0.dat
[17:27:24.934] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C1.dat
[17:27:24.942] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C2.dat
[17:27:24.951] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C3.dat
[17:27:24.959] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C4.dat
[17:27:24.968] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C5.dat
[17:27:24.977] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C6.dat
[17:27:24.985] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C7.dat
[17:27:24.994] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C8.dat
[17:27:24.002] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C9.dat
[17:27:25.010] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C10.dat
[17:27:25.019] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C11.dat
[17:27:25.027] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C12.dat
[17:27:25.036] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C13.dat
[17:27:25.045] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C14.dat
[17:27:25.053] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C15.dat
[17:27:25.062] <TB2> INFO: PixTestTrim::trimTest() done
[17:27:25.062] <TB2> INFO: vtrim: 148 138 148 127 119 132 144 140 112 123 151 149 129 143 149 123
[17:27:25.062] <TB2> INFO: vthrcomp: 128 125 111 114 114 108 118 110 112 116 119 130 109 106 117 115
[17:27:25.062] <TB2> INFO: vcal mean: 34.95 34.98 34.95 34.95 34.88 34.96 34.94 34.97 35.03 34.98 34.98 34.93 34.98 35.06 35.02 35.00
[17:27:25.062] <TB2> INFO: vcal RMS: 1.15 1.18 1.09 1.01 1.07 0.97 1.06 1.04 0.98 1.00 1.21 1.26 1.10 1.23 1.23 1.07
[17:27:25.062] <TB2> INFO: bits mean: 10.09 10.06 9.04 9.45 9.43 8.96 10.39 9.13 8.72 9.46 10.04 10.15 9.18 9.12 9.67 9.92
[17:27:25.062] <TB2> INFO: bits RMS: 2.37 2.60 2.47 2.70 2.70 2.45 2.27 2.45 3.00 2.79 2.62 2.44 2.48 2.39 2.58 2.46
[17:27:25.069] <TB2> INFO: ----------------------------------------------------------------------
[17:27:25.070] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[17:27:25.070] <TB2> INFO: ----------------------------------------------------------------------
[17:27:25.072] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[17:27:25.081] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:27:25.081] <TB2> INFO: run 1 of 1
[17:27:25.365] <TB2> INFO: Expecting 4160000 events.
[17:27:57.777] <TB2> INFO: 741975 events read in total (31820ms).
[17:28:28.827] <TB2> INFO: 1479665 events read in total (62870ms).
[17:28:59.894] <TB2> INFO: 2212895 events read in total (93937ms).
[17:29:31.035] <TB2> INFO: 2941615 events read in total (125078ms).
[17:30:02.082] <TB2> INFO: 3668570 events read in total (156126ms).
[17:30:22.868] <TB2> INFO: 4160000 events read in total (176911ms).
[17:30:22.931] <TB2> INFO: Test took 177850ms.
[17:30:52.166] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 202 (-1/-1) hits flags = 528 (plus default)
[17:30:52.174] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:30:52.175] <TB2> INFO: run 1 of 1
[17:30:52.410] <TB2> INFO: Expecting 4222400 events.
[17:31:23.552] <TB2> INFO: 714355 events read in total (30550ms).
[17:31:54.092] <TB2> INFO: 1425010 events read in total (61090ms).
[17:32:24.893] <TB2> INFO: 2132200 events read in total (91891ms).
[17:32:55.273] <TB2> INFO: 2834485 events read in total (122271ms).
[17:33:25.837] <TB2> INFO: 3535340 events read in total (152835ms).
[17:33:55.823] <TB2> INFO: 4222400 events read in total (182821ms).
[17:33:55.891] <TB2> INFO: Test took 183717ms.
[17:34:27.395] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 197 (-1/-1) hits flags = 528 (plus default)
[17:34:27.407] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:34:27.407] <TB2> INFO: run 1 of 1
[17:34:27.681] <TB2> INFO: Expecting 4118400 events.
[17:34:58.832] <TB2> INFO: 720685 events read in total (30560ms).
[17:35:29.375] <TB2> INFO: 1437390 events read in total (61103ms).
[17:35:59.747] <TB2> INFO: 2150330 events read in total (91475ms).
[17:36:29.902] <TB2> INFO: 2858270 events read in total (121630ms).
[17:37:00.019] <TB2> INFO: 3564975 events read in total (151747ms).
[17:37:23.820] <TB2> INFO: 4118400 events read in total (175548ms).
[17:37:23.875] <TB2> INFO: Test took 176468ms.
[17:37:53.585] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[17:37:53.595] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:37:53.595] <TB2> INFO: run 1 of 1
[17:37:53.844] <TB2> INFO: Expecting 4139200 events.
[17:38:25.085] <TB2> INFO: 719525 events read in total (30649ms).
[17:38:55.764] <TB2> INFO: 1435015 events read in total (61328ms).
[17:39:26.184] <TB2> INFO: 2146940 events read in total (91748ms).
[17:39:56.835] <TB2> INFO: 2853610 events read in total (122399ms).
[17:40:27.172] <TB2> INFO: 3559185 events read in total (152736ms).
[17:40:52.031] <TB2> INFO: 4139200 events read in total (177595ms).
[17:40:52.101] <TB2> INFO: Test took 178506ms.
[17:41:23.512] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[17:41:23.521] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:41:23.521] <TB2> INFO: run 1 of 1
[17:41:23.754] <TB2> INFO: Expecting 4139200 events.
[17:41:54.901] <TB2> INFO: 719710 events read in total (30556ms).
[17:42:25.370] <TB2> INFO: 1435460 events read in total (61025ms).
[17:42:56.010] <TB2> INFO: 2147385 events read in total (91666ms).
[17:43:26.367] <TB2> INFO: 2854095 events read in total (122022ms).
[17:43:57.473] <TB2> INFO: 3559760 events read in total (153128ms).
[17:44:22.295] <TB2> INFO: 4139200 events read in total (177950ms).
[17:44:22.354] <TB2> INFO: Test took 178832ms.
[17:44:50.889] <TB2> INFO: PixTestTrim::trimBitTest() done
[17:44:50.890] <TB2> INFO: PixTestTrim::doTest() done, duration: 2468 seconds
[17:44:50.890] <TB2> INFO: Decoding statistics:
[17:44:50.890] <TB2> INFO: General information:
[17:44:50.890] <TB2> INFO: 16bit words read: 0
[17:44:50.890] <TB2> INFO: valid events total: 0
[17:44:50.890] <TB2> INFO: empty events: 0
[17:44:50.890] <TB2> INFO: valid events with pixels: 0
[17:44:50.890] <TB2> INFO: valid pixel hits: 0
[17:44:50.890] <TB2> INFO: Event errors: 0
[17:44:50.890] <TB2> INFO: start marker: 0
[17:44:50.890] <TB2> INFO: stop marker: 0
[17:44:50.890] <TB2> INFO: overflow: 0
[17:44:50.890] <TB2> INFO: invalid 5bit words: 0
[17:44:50.890] <TB2> INFO: invalid XOR eye diagram: 0
[17:44:50.890] <TB2> INFO: frame (failed synchr.): 0
[17:44:50.890] <TB2> INFO: idle data (no TBM trl): 0
[17:44:50.890] <TB2> INFO: no data (only TBM hdr): 0
[17:44:50.890] <TB2> INFO: TBM errors: 0
[17:44:50.890] <TB2> INFO: flawed TBM headers: 0
[17:44:50.890] <TB2> INFO: flawed TBM trailers: 0
[17:44:50.890] <TB2> INFO: event ID mismatches: 0
[17:44:50.890] <TB2> INFO: ROC errors: 0
[17:44:50.890] <TB2> INFO: missing ROC header(s): 0
[17:44:50.890] <TB2> INFO: misplaced readback start: 0
[17:44:50.890] <TB2> INFO: Pixel decoding errors: 0
[17:44:50.890] <TB2> INFO: pixel data incomplete: 0
[17:44:50.890] <TB2> INFO: pixel address: 0
[17:44:50.890] <TB2> INFO: pulse height fill bit: 0
[17:44:50.890] <TB2> INFO: buffer corruption: 0
[17:44:51.541] <TB2> INFO: ######################################################################
[17:44:51.541] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[17:44:51.541] <TB2> INFO: ######################################################################
[17:44:51.775] <TB2> INFO: Expecting 41600 events.
[17:44:55.295] <TB2> INFO: 41600 events read in total (2928ms).
[17:44:55.296] <TB2> INFO: Test took 3753ms.
[17:44:55.807] <TB2> INFO: Expecting 41600 events.
[17:44:59.255] <TB2> INFO: 41600 events read in total (2856ms).
[17:44:59.255] <TB2> INFO: Test took 3756ms.
[17:44:59.546] <TB2> INFO: Expecting 41600 events.
[17:45:03.008] <TB2> INFO: 41600 events read in total (2871ms).
[17:45:03.008] <TB2> INFO: Test took 3727ms.
[17:45:03.296] <TB2> INFO: Expecting 41600 events.
[17:45:06.832] <TB2> INFO: 41600 events read in total (2944ms).
[17:45:06.833] <TB2> INFO: Test took 3802ms.
[17:45:07.121] <TB2> INFO: Expecting 41600 events.
[17:45:10.656] <TB2> INFO: 41600 events read in total (2942ms).
[17:45:10.657] <TB2> INFO: Test took 3801ms.
[17:45:10.945] <TB2> INFO: Expecting 41600 events.
[17:45:14.395] <TB2> INFO: 41600 events read in total (2858ms).
[17:45:14.396] <TB2> INFO: Test took 3716ms.
[17:45:14.684] <TB2> INFO: Expecting 41600 events.
[17:45:18.187] <TB2> INFO: 41600 events read in total (2912ms).
[17:45:18.188] <TB2> INFO: Test took 3769ms.
[17:45:18.478] <TB2> INFO: Expecting 41600 events.
[17:45:21.927] <TB2> INFO: 41600 events read in total (2857ms).
[17:45:21.928] <TB2> INFO: Test took 3715ms.
[17:45:22.216] <TB2> INFO: Expecting 41600 events.
[17:45:25.766] <TB2> INFO: 41600 events read in total (2958ms).
[17:45:25.766] <TB2> INFO: Test took 3815ms.
[17:45:26.054] <TB2> INFO: Expecting 41600 events.
[17:45:29.611] <TB2> INFO: 41600 events read in total (2965ms).
[17:45:29.612] <TB2> INFO: Test took 3823ms.
[17:45:29.910] <TB2> INFO: Expecting 41600 events.
[17:45:33.347] <TB2> INFO: 41600 events read in total (2845ms).
[17:45:33.347] <TB2> INFO: Test took 3712ms.
[17:45:33.636] <TB2> INFO: Expecting 41600 events.
[17:45:37.188] <TB2> INFO: 41600 events read in total (2961ms).
[17:45:37.189] <TB2> INFO: Test took 3818ms.
[17:45:37.477] <TB2> INFO: Expecting 41600 events.
[17:45:40.932] <TB2> INFO: 41600 events read in total (2864ms).
[17:45:40.933] <TB2> INFO: Test took 3721ms.
[17:45:41.221] <TB2> INFO: Expecting 41600 events.
[17:45:44.684] <TB2> INFO: 41600 events read in total (2872ms).
[17:45:44.685] <TB2> INFO: Test took 3729ms.
[17:45:44.978] <TB2> INFO: Expecting 41600 events.
[17:45:48.446] <TB2> INFO: 41600 events read in total (2877ms).
[17:45:48.447] <TB2> INFO: Test took 3734ms.
[17:45:48.735] <TB2> INFO: Expecting 41600 events.
[17:45:52.201] <TB2> INFO: 41600 events read in total (2874ms).
[17:45:52.202] <TB2> INFO: Test took 3732ms.
[17:45:52.490] <TB2> INFO: Expecting 41600 events.
[17:45:55.955] <TB2> INFO: 41600 events read in total (2873ms).
[17:45:55.956] <TB2> INFO: Test took 3731ms.
[17:45:56.244] <TB2> INFO: Expecting 41600 events.
[17:45:59.823] <TB2> INFO: 41600 events read in total (2988ms).
[17:45:59.824] <TB2> INFO: Test took 3845ms.
[17:46:00.112] <TB2> INFO: Expecting 41600 events.
[17:46:03.601] <TB2> INFO: 41600 events read in total (2898ms).
[17:46:03.602] <TB2> INFO: Test took 3755ms.
[17:46:03.890] <TB2> INFO: Expecting 41600 events.
[17:46:07.410] <TB2> INFO: 41600 events read in total (2928ms).
[17:46:07.411] <TB2> INFO: Test took 3786ms.
[17:46:07.699] <TB2> INFO: Expecting 41600 events.
[17:46:11.177] <TB2> INFO: 41600 events read in total (2886ms).
[17:46:11.178] <TB2> INFO: Test took 3744ms.
[17:46:11.465] <TB2> INFO: Expecting 41600 events.
[17:46:14.931] <TB2> INFO: 41600 events read in total (2874ms).
[17:46:14.932] <TB2> INFO: Test took 3731ms.
[17:46:15.231] <TB2> INFO: Expecting 41600 events.
[17:46:18.736] <TB2> INFO: 41600 events read in total (2914ms).
[17:46:18.736] <TB2> INFO: Test took 3779ms.
[17:46:19.024] <TB2> INFO: Expecting 41600 events.
[17:46:22.658] <TB2> INFO: 41600 events read in total (3042ms).
[17:46:22.658] <TB2> INFO: Test took 3898ms.
[17:46:22.946] <TB2> INFO: Expecting 41600 events.
[17:46:26.464] <TB2> INFO: 41600 events read in total (2926ms).
[17:46:26.465] <TB2> INFO: Test took 3783ms.
[17:46:26.755] <TB2> INFO: Expecting 41600 events.
[17:46:30.195] <TB2> INFO: 41600 events read in total (2848ms).
[17:46:30.196] <TB2> INFO: Test took 3705ms.
[17:46:30.488] <TB2> INFO: Expecting 41600 events.
[17:46:34.037] <TB2> INFO: 41600 events read in total (2958ms).
[17:46:34.037] <TB2> INFO: Test took 3818ms.
[17:46:34.325] <TB2> INFO: Expecting 41600 events.
[17:46:37.896] <TB2> INFO: 41600 events read in total (2979ms).
[17:46:37.897] <TB2> INFO: Test took 3836ms.
[17:46:38.187] <TB2> INFO: Expecting 41600 events.
[17:46:41.789] <TB2> INFO: 41600 events read in total (3010ms).
[17:46:41.791] <TB2> INFO: Test took 3868ms.
[17:46:42.089] <TB2> INFO: Expecting 41600 events.
[17:46:45.626] <TB2> INFO: 41600 events read in total (2945ms).
[17:46:45.627] <TB2> INFO: Test took 3811ms.
[17:46:45.917] <TB2> INFO: Expecting 41600 events.
[17:46:49.381] <TB2> INFO: 41600 events read in total (2873ms).
[17:46:49.382] <TB2> INFO: Test took 3730ms.
[17:46:49.670] <TB2> INFO: Expecting 2560 events.
[17:46:50.554] <TB2> INFO: 2560 events read in total (292ms).
[17:46:50.554] <TB2> INFO: Test took 1160ms.
[17:46:50.862] <TB2> INFO: Expecting 2560 events.
[17:46:51.749] <TB2> INFO: 2560 events read in total (295ms).
[17:46:51.749] <TB2> INFO: Test took 1194ms.
[17:46:52.057] <TB2> INFO: Expecting 2560 events.
[17:46:52.940] <TB2> INFO: 2560 events read in total (292ms).
[17:46:52.940] <TB2> INFO: Test took 1191ms.
[17:46:53.248] <TB2> INFO: Expecting 2560 events.
[17:46:54.133] <TB2> INFO: 2560 events read in total (293ms).
[17:46:54.133] <TB2> INFO: Test took 1192ms.
[17:46:54.441] <TB2> INFO: Expecting 2560 events.
[17:46:55.319] <TB2> INFO: 2560 events read in total (286ms).
[17:46:55.320] <TB2> INFO: Test took 1186ms.
[17:46:55.627] <TB2> INFO: Expecting 2560 events.
[17:46:56.506] <TB2> INFO: 2560 events read in total (287ms).
[17:46:56.506] <TB2> INFO: Test took 1185ms.
[17:46:56.814] <TB2> INFO: Expecting 2560 events.
[17:46:57.692] <TB2> INFO: 2560 events read in total (286ms).
[17:46:57.693] <TB2> INFO: Test took 1186ms.
[17:46:57.000] <TB2> INFO: Expecting 2560 events.
[17:46:58.883] <TB2> INFO: 2560 events read in total (291ms).
[17:46:58.883] <TB2> INFO: Test took 1190ms.
[17:46:59.191] <TB2> INFO: Expecting 2560 events.
[17:47:00.074] <TB2> INFO: 2560 events read in total (291ms).
[17:47:00.074] <TB2> INFO: Test took 1190ms.
[17:47:00.382] <TB2> INFO: Expecting 2560 events.
[17:47:01.263] <TB2> INFO: 2560 events read in total (289ms).
[17:47:01.263] <TB2> INFO: Test took 1188ms.
[17:47:01.571] <TB2> INFO: Expecting 2560 events.
[17:47:02.451] <TB2> INFO: 2560 events read in total (288ms).
[17:47:02.451] <TB2> INFO: Test took 1188ms.
[17:47:02.759] <TB2> INFO: Expecting 2560 events.
[17:47:03.637] <TB2> INFO: 2560 events read in total (286ms).
[17:47:03.637] <TB2> INFO: Test took 1185ms.
[17:47:03.945] <TB2> INFO: Expecting 2560 events.
[17:47:04.830] <TB2> INFO: 2560 events read in total (293ms).
[17:47:04.830] <TB2> INFO: Test took 1192ms.
[17:47:05.138] <TB2> INFO: Expecting 2560 events.
[17:47:06.021] <TB2> INFO: 2560 events read in total (291ms).
[17:47:06.021] <TB2> INFO: Test took 1190ms.
[17:47:06.329] <TB2> INFO: Expecting 2560 events.
[17:47:07.215] <TB2> INFO: 2560 events read in total (294ms).
[17:47:07.215] <TB2> INFO: Test took 1193ms.
[17:47:07.523] <TB2> INFO: Expecting 2560 events.
[17:47:08.409] <TB2> INFO: 2560 events read in total (294ms).
[17:47:08.409] <TB2> INFO: Test took 1194ms.
[17:47:08.412] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:47:08.718] <TB2> INFO: Expecting 655360 events.
[17:47:23.138] <TB2> INFO: 655360 events read in total (13828ms).
[17:47:23.148] <TB2> INFO: Expecting 655360 events.
[17:47:37.318] <TB2> INFO: 655360 events read in total (13767ms).
[17:47:37.332] <TB2> INFO: Expecting 655360 events.
[17:47:51.511] <TB2> INFO: 655360 events read in total (13776ms).
[17:47:51.531] <TB2> INFO: Expecting 655360 events.
[17:48:05.698] <TB2> INFO: 655360 events read in total (13764ms).
[17:48:05.720] <TB2> INFO: Expecting 655360 events.
[17:48:19.756] <TB2> INFO: 655360 events read in total (13633ms).
[17:48:19.784] <TB2> INFO: Expecting 655360 events.
[17:48:33.819] <TB2> INFO: 655360 events read in total (13632ms).
[17:48:33.850] <TB2> INFO: Expecting 655360 events.
[17:48:47.847] <TB2> INFO: 655360 events read in total (13594ms).
[17:48:47.883] <TB2> INFO: Expecting 655360 events.
[17:49:01.823] <TB2> INFO: 655360 events read in total (13537ms).
[17:49:01.871] <TB2> INFO: Expecting 655360 events.
[17:49:15.961] <TB2> INFO: 655360 events read in total (13688ms).
[17:49:16.020] <TB2> INFO: Expecting 655360 events.
[17:49:30.069] <TB2> INFO: 655360 events read in total (13646ms).
[17:49:30.118] <TB2> INFO: Expecting 655360 events.
[17:49:44.149] <TB2> INFO: 655360 events read in total (13628ms).
[17:49:44.222] <TB2> INFO: Expecting 655360 events.
[17:49:58.238] <TB2> INFO: 655360 events read in total (13612ms).
[17:49:58.305] <TB2> INFO: Expecting 655360 events.
[17:50:12.416] <TB2> INFO: 655360 events read in total (13708ms).
[17:50:12.478] <TB2> INFO: Expecting 655360 events.
[17:50:26.404] <TB2> INFO: 655360 events read in total (13523ms).
[17:50:26.470] <TB2> INFO: Expecting 655360 events.
[17:50:40.497] <TB2> INFO: 655360 events read in total (13624ms).
[17:50:40.595] <TB2> INFO: Expecting 655360 events.
[17:50:54.652] <TB2> INFO: 655360 events read in total (13654ms).
[17:50:54.728] <TB2> INFO: Test took 226316ms.
[17:50:54.813] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:50:55.078] <TB2> INFO: Expecting 655360 events.
[17:51:09.272] <TB2> INFO: 655360 events read in total (13602ms).
[17:51:09.285] <TB2> INFO: Expecting 655360 events.
[17:51:23.192] <TB2> INFO: 655360 events read in total (13504ms).
[17:51:23.214] <TB2> INFO: Expecting 655360 events.
[17:51:37.113] <TB2> INFO: 655360 events read in total (13496ms).
[17:51:37.131] <TB2> INFO: Expecting 655360 events.
[17:51:51.184] <TB2> INFO: 655360 events read in total (13650ms).
[17:51:51.213] <TB2> INFO: Expecting 655360 events.
[17:52:05.138] <TB2> INFO: 655360 events read in total (13521ms).
[17:52:05.168] <TB2> INFO: Expecting 655360 events.
[17:52:19.067] <TB2> INFO: 655360 events read in total (13496ms).
[17:52:19.097] <TB2> INFO: Expecting 655360 events.
[17:52:33.095] <TB2> INFO: 655360 events read in total (13596ms).
[17:52:33.131] <TB2> INFO: Expecting 655360 events.
[17:52:47.131] <TB2> INFO: 655360 events read in total (13597ms).
[17:52:47.169] <TB2> INFO: Expecting 655360 events.
[17:53:01.052] <TB2> INFO: 655360 events read in total (13480ms).
[17:53:01.094] <TB2> INFO: Expecting 655360 events.
[17:53:14.847] <TB2> INFO: 655360 events read in total (13350ms).
[17:53:14.893] <TB2> INFO: Expecting 655360 events.
[17:53:28.900] <TB2> INFO: 655360 events read in total (13604ms).
[17:53:28.953] <TB2> INFO: Expecting 655360 events.
[17:53:42.779] <TB2> INFO: 655360 events read in total (13423ms).
[17:53:42.856] <TB2> INFO: Expecting 655360 events.
[17:53:56.517] <TB2> INFO: 655360 events read in total (13258ms).
[17:53:56.600] <TB2> INFO: Expecting 655360 events.
[17:54:10.414] <TB2> INFO: 655360 events read in total (13411ms).
[17:54:10.480] <TB2> INFO: Expecting 655360 events.
[17:54:24.331] <TB2> INFO: 655360 events read in total (13448ms).
[17:54:24.429] <TB2> INFO: Expecting 655360 events.
[17:54:38.501] <TB2> INFO: 655360 events read in total (13669ms).
[17:54:38.602] <TB2> INFO: Test took 223789ms.
[17:54:38.777] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:54:38.782] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:54:38.788] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:54:38.792] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[17:54:38.797] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[17:54:38.801] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[17:54:38.806] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[17:54:38.810] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[17:54:38.815] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[17:54:38.820] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[17:54:38.825] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[17:54:38.829] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[17:54:38.834] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:54:38.838] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:54:38.843] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:54:38.848] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:54:38.852] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:54:38.857] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:54:38.862] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:54:38.866] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:54:38.871] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:54:38.876] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:54:38.880] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:54:38.885] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:54:38.890] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:54:38.894] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:54:38.899] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:54:38.904] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:54:38.908] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:54:38.913] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[17:54:38.917] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[17:54:38.922] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:54:38.955] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C0.dat
[17:54:38.955] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C1.dat
[17:54:38.955] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C2.dat
[17:54:38.955] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C3.dat
[17:54:38.955] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C4.dat
[17:54:38.955] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C5.dat
[17:54:38.955] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C6.dat
[17:54:38.955] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C7.dat
[17:54:38.956] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C8.dat
[17:54:38.956] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C9.dat
[17:54:38.956] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C10.dat
[17:54:38.956] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C11.dat
[17:54:38.956] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C12.dat
[17:54:38.956] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C13.dat
[17:54:38.956] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C14.dat
[17:54:38.956] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C15.dat
[17:54:39.190] <TB2> INFO: Expecting 41600 events.
[17:54:42.297] <TB2> INFO: 41600 events read in total (2515ms).
[17:54:42.297] <TB2> INFO: Test took 3338ms.
[17:54:42.742] <TB2> INFO: Expecting 41600 events.
[17:54:45.745] <TB2> INFO: 41600 events read in total (2412ms).
[17:54:45.746] <TB2> INFO: Test took 3238ms.
[17:54:46.188] <TB2> INFO: Expecting 41600 events.
[17:54:49.274] <TB2> INFO: 41600 events read in total (2495ms).
[17:54:49.274] <TB2> INFO: Test took 3318ms.
[17:54:49.488] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:54:49.576] <TB2> INFO: Expecting 2560 events.
[17:54:50.462] <TB2> INFO: 2560 events read in total (294ms).
[17:54:50.463] <TB2> INFO: Test took 975ms.
[17:54:50.465] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:54:50.771] <TB2> INFO: Expecting 2560 events.
[17:54:51.653] <TB2> INFO: 2560 events read in total (290ms).
[17:54:51.654] <TB2> INFO: Test took 1189ms.
[17:54:51.656] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:54:51.962] <TB2> INFO: Expecting 2560 events.
[17:54:52.847] <TB2> INFO: 2560 events read in total (294ms).
[17:54:52.847] <TB2> INFO: Test took 1191ms.
[17:54:52.849] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:54:53.156] <TB2> INFO: Expecting 2560 events.
[17:54:54.038] <TB2> INFO: 2560 events read in total (291ms).
[17:54:54.038] <TB2> INFO: Test took 1189ms.
[17:54:54.040] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:54:54.347] <TB2> INFO: Expecting 2560 events.
[17:54:55.230] <TB2> INFO: 2560 events read in total (292ms).
[17:54:55.230] <TB2> INFO: Test took 1190ms.
[17:54:55.232] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:54:55.538] <TB2> INFO: Expecting 2560 events.
[17:54:56.422] <TB2> INFO: 2560 events read in total (292ms).
[17:54:56.422] <TB2> INFO: Test took 1190ms.
[17:54:56.424] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:54:56.730] <TB2> INFO: Expecting 2560 events.
[17:54:57.613] <TB2> INFO: 2560 events read in total (291ms).
[17:54:57.613] <TB2> INFO: Test took 1189ms.
[17:54:57.615] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:54:57.922] <TB2> INFO: Expecting 2560 events.
[17:54:58.806] <TB2> INFO: 2560 events read in total (293ms).
[17:54:58.807] <TB2> INFO: Test took 1192ms.
[17:54:58.808] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:54:59.115] <TB2> INFO: Expecting 2560 events.
[17:54:59.992] <TB2> INFO: 2560 events read in total (287ms).
[17:54:59.993] <TB2> INFO: Test took 1185ms.
[17:54:59.995] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:00.301] <TB2> INFO: Expecting 2560 events.
[17:55:01.179] <TB2> INFO: 2560 events read in total (286ms).
[17:55:01.180] <TB2> INFO: Test took 1185ms.
[17:55:01.181] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:01.488] <TB2> INFO: Expecting 2560 events.
[17:55:02.365] <TB2> INFO: 2560 events read in total (286ms).
[17:55:02.365] <TB2> INFO: Test took 1184ms.
[17:55:02.367] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:02.673] <TB2> INFO: Expecting 2560 events.
[17:55:03.552] <TB2> INFO: 2560 events read in total (287ms).
[17:55:03.552] <TB2> INFO: Test took 1185ms.
[17:55:03.554] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:03.860] <TB2> INFO: Expecting 2560 events.
[17:55:04.739] <TB2> INFO: 2560 events read in total (287ms).
[17:55:04.739] <TB2> INFO: Test took 1185ms.
[17:55:04.741] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:05.048] <TB2> INFO: Expecting 2560 events.
[17:55:05.927] <TB2> INFO: 2560 events read in total (287ms).
[17:55:05.928] <TB2> INFO: Test took 1187ms.
[17:55:05.929] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:06.236] <TB2> INFO: Expecting 2560 events.
[17:55:07.116] <TB2> INFO: 2560 events read in total (288ms).
[17:55:07.116] <TB2> INFO: Test took 1187ms.
[17:55:07.118] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:07.424] <TB2> INFO: Expecting 2560 events.
[17:55:08.303] <TB2> INFO: 2560 events read in total (287ms).
[17:55:08.303] <TB2> INFO: Test took 1185ms.
[17:55:08.305] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:08.612] <TB2> INFO: Expecting 2560 events.
[17:55:09.492] <TB2> INFO: 2560 events read in total (288ms).
[17:55:09.492] <TB2> INFO: Test took 1187ms.
[17:55:09.494] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:09.801] <TB2> INFO: Expecting 2560 events.
[17:55:10.687] <TB2> INFO: 2560 events read in total (294ms).
[17:55:10.687] <TB2> INFO: Test took 1193ms.
[17:55:10.689] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:10.995] <TB2> INFO: Expecting 2560 events.
[17:55:11.874] <TB2> INFO: 2560 events read in total (287ms).
[17:55:11.875] <TB2> INFO: Test took 1186ms.
[17:55:11.877] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:12.183] <TB2> INFO: Expecting 2560 events.
[17:55:13.061] <TB2> INFO: 2560 events read in total (287ms).
[17:55:13.062] <TB2> INFO: Test took 1186ms.
[17:55:13.064] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:13.370] <TB2> INFO: Expecting 2560 events.
[17:55:14.248] <TB2> INFO: 2560 events read in total (286ms).
[17:55:14.248] <TB2> INFO: Test took 1184ms.
[17:55:14.250] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:14.557] <TB2> INFO: Expecting 2560 events.
[17:55:15.436] <TB2> INFO: 2560 events read in total (288ms).
[17:55:15.436] <TB2> INFO: Test took 1186ms.
[17:55:15.438] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:15.744] <TB2> INFO: Expecting 2560 events.
[17:55:16.623] <TB2> INFO: 2560 events read in total (286ms).
[17:55:16.623] <TB2> INFO: Test took 1185ms.
[17:55:16.625] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:16.931] <TB2> INFO: Expecting 2560 events.
[17:55:17.809] <TB2> INFO: 2560 events read in total (286ms).
[17:55:17.809] <TB2> INFO: Test took 1184ms.
[17:55:17.811] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:18.118] <TB2> INFO: Expecting 2560 events.
[17:55:18.002] <TB2> INFO: 2560 events read in total (293ms).
[17:55:18.002] <TB2> INFO: Test took 1191ms.
[17:55:18.004] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:19.310] <TB2> INFO: Expecting 2560 events.
[17:55:20.193] <TB2> INFO: 2560 events read in total (291ms).
[17:55:20.193] <TB2> INFO: Test took 1190ms.
[17:55:20.196] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:20.502] <TB2> INFO: Expecting 2560 events.
[17:55:21.390] <TB2> INFO: 2560 events read in total (297ms).
[17:55:21.390] <TB2> INFO: Test took 1195ms.
[17:55:21.392] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:21.698] <TB2> INFO: Expecting 2560 events.
[17:55:22.581] <TB2> INFO: 2560 events read in total (291ms).
[17:55:22.581] <TB2> INFO: Test took 1189ms.
[17:55:22.583] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:22.889] <TB2> INFO: Expecting 2560 events.
[17:55:23.774] <TB2> INFO: 2560 events read in total (293ms).
[17:55:23.774] <TB2> INFO: Test took 1191ms.
[17:55:23.776] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:24.082] <TB2> INFO: Expecting 2560 events.
[17:55:24.965] <TB2> INFO: 2560 events read in total (291ms).
[17:55:24.965] <TB2> INFO: Test took 1189ms.
[17:55:24.967] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:25.274] <TB2> INFO: Expecting 2560 events.
[17:55:26.156] <TB2> INFO: 2560 events read in total (290ms).
[17:55:26.156] <TB2> INFO: Test took 1189ms.
[17:55:26.158] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:55:26.464] <TB2> INFO: Expecting 2560 events.
[17:55:27.350] <TB2> INFO: 2560 events read in total (294ms).
[17:55:27.350] <TB2> INFO: Test took 1192ms.
[17:55:27.813] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 636 seconds
[17:55:27.813] <TB2> INFO: PH scale (per ROC): 54 65 59 48 52 63 42 55 59 40 65 48 52 35 53 59
[17:55:27.813] <TB2> INFO: PH offset (per ROC): 130 112 130 94 133 115 92 135 123 112 125 102 130 99 115 128
[17:55:27.818] <TB2> INFO: Decoding statistics:
[17:55:27.818] <TB2> INFO: General information:
[17:55:27.818] <TB2> INFO: 16bit words read: 127878
[17:55:27.818] <TB2> INFO: valid events total: 20480
[17:55:27.818] <TB2> INFO: empty events: 17981
[17:55:27.818] <TB2> INFO: valid events with pixels: 2499
[17:55:27.818] <TB2> INFO: valid pixel hits: 2499
[17:55:27.818] <TB2> INFO: Event errors: 0
[17:55:27.818] <TB2> INFO: start marker: 0
[17:55:27.818] <TB2> INFO: stop marker: 0
[17:55:27.818] <TB2> INFO: overflow: 0
[17:55:27.818] <TB2> INFO: invalid 5bit words: 0
[17:55:27.818] <TB2> INFO: invalid XOR eye diagram: 0
[17:55:27.818] <TB2> INFO: frame (failed synchr.): 0
[17:55:27.818] <TB2> INFO: idle data (no TBM trl): 0
[17:55:27.818] <TB2> INFO: no data (only TBM hdr): 0
[17:55:27.818] <TB2> INFO: TBM errors: 0
[17:55:27.818] <TB2> INFO: flawed TBM headers: 0
[17:55:27.818] <TB2> INFO: flawed TBM trailers: 0
[17:55:27.818] <TB2> INFO: event ID mismatches: 0
[17:55:27.818] <TB2> INFO: ROC errors: 0
[17:55:27.818] <TB2> INFO: missing ROC header(s): 0
[17:55:27.818] <TB2> INFO: misplaced readback start: 0
[17:55:27.818] <TB2> INFO: Pixel decoding errors: 0
[17:55:27.818] <TB2> INFO: pixel data incomplete: 0
[17:55:27.818] <TB2> INFO: pixel address: 0
[17:55:27.818] <TB2> INFO: pulse height fill bit: 0
[17:55:27.818] <TB2> INFO: buffer corruption: 0
[17:55:28.129] <TB2> INFO: ######################################################################
[17:55:28.129] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[17:55:28.129] <TB2> INFO: ######################################################################
[17:55:28.139] <TB2> INFO: scanning low vcal = 10
[17:55:28.373] <TB2> INFO: Expecting 41600 events.
[17:55:31.937] <TB2> INFO: 41600 events read in total (2973ms).
[17:55:31.938] <TB2> INFO: Test took 3798ms.
[17:55:31.939] <TB2> INFO: scanning low vcal = 20
[17:55:32.239] <TB2> INFO: Expecting 41600 events.
[17:55:35.806] <TB2> INFO: 41600 events read in total (2975ms).
[17:55:35.807] <TB2> INFO: Test took 3868ms.
[17:55:35.809] <TB2> INFO: scanning low vcal = 30
[17:55:36.107] <TB2> INFO: Expecting 41600 events.
[17:55:39.755] <TB2> INFO: 41600 events read in total (3057ms).
[17:55:39.756] <TB2> INFO: Test took 3947ms.
[17:55:39.758] <TB2> INFO: scanning low vcal = 40
[17:55:40.039] <TB2> INFO: Expecting 41600 events.
[17:55:43.942] <TB2> INFO: 41600 events read in total (3309ms).
[17:55:43.943] <TB2> INFO: Test took 4184ms.
[17:55:43.946] <TB2> INFO: scanning low vcal = 50
[17:55:44.222] <TB2> INFO: Expecting 41600 events.
[17:55:48.186] <TB2> INFO: 41600 events read in total (3372ms).
[17:55:48.187] <TB2> INFO: Test took 4241ms.
[17:55:48.189] <TB2> INFO: scanning low vcal = 60
[17:55:48.466] <TB2> INFO: Expecting 41600 events.
[17:55:52.394] <TB2> INFO: 41600 events read in total (3336ms).
[17:55:52.395] <TB2> INFO: Test took 4206ms.
[17:55:52.398] <TB2> INFO: scanning low vcal = 70
[17:55:52.675] <TB2> INFO: Expecting 41600 events.
[17:55:56.600] <TB2> INFO: 41600 events read in total (3334ms).
[17:55:56.601] <TB2> INFO: Test took 4203ms.
[17:55:56.604] <TB2> INFO: scanning low vcal = 80
[17:55:56.880] <TB2> INFO: Expecting 41600 events.
[17:56:00.847] <TB2> INFO: 41600 events read in total (3375ms).
[17:56:00.848] <TB2> INFO: Test took 4244ms.
[17:56:00.851] <TB2> INFO: scanning low vcal = 90
[17:56:01.127] <TB2> INFO: Expecting 41600 events.
[17:56:05.048] <TB2> INFO: 41600 events read in total (3329ms).
[17:56:05.048] <TB2> INFO: Test took 4197ms.
[17:56:05.051] <TB2> INFO: scanning low vcal = 100
[17:56:05.328] <TB2> INFO: Expecting 41600 events.
[17:56:09.316] <TB2> INFO: 41600 events read in total (3396ms).
[17:56:09.316] <TB2> INFO: Test took 4265ms.
[17:56:09.319] <TB2> INFO: scanning low vcal = 110
[17:56:09.596] <TB2> INFO: Expecting 41600 events.
[17:56:13.529] <TB2> INFO: 41600 events read in total (3342ms).
[17:56:13.530] <TB2> INFO: Test took 4211ms.
[17:56:13.533] <TB2> INFO: scanning low vcal = 120
[17:56:13.809] <TB2> INFO: Expecting 41600 events.
[17:56:17.798] <TB2> INFO: 41600 events read in total (3397ms).
[17:56:17.799] <TB2> INFO: Test took 4266ms.
[17:56:17.801] <TB2> INFO: scanning low vcal = 130
[17:56:18.078] <TB2> INFO: Expecting 41600 events.
[17:56:22.016] <TB2> INFO: 41600 events read in total (3346ms).
[17:56:22.016] <TB2> INFO: Test took 4215ms.
[17:56:22.019] <TB2> INFO: scanning low vcal = 140
[17:56:22.296] <TB2> INFO: Expecting 41600 events.
[17:56:26.260] <TB2> INFO: 41600 events read in total (3373ms).
[17:56:26.260] <TB2> INFO: Test took 4241ms.
[17:56:26.264] <TB2> INFO: scanning low vcal = 150
[17:56:26.540] <TB2> INFO: Expecting 41600 events.
[17:56:30.520] <TB2> INFO: 41600 events read in total (3388ms).
[17:56:30.521] <TB2> INFO: Test took 4257ms.
[17:56:30.523] <TB2> INFO: scanning low vcal = 160
[17:56:30.800] <TB2> INFO: Expecting 41600 events.
[17:56:34.752] <TB2> INFO: 41600 events read in total (3360ms).
[17:56:34.753] <TB2> INFO: Test took 4229ms.
[17:56:34.756] <TB2> INFO: scanning low vcal = 170
[17:56:35.033] <TB2> INFO: Expecting 41600 events.
[17:56:38.006] <TB2> INFO: 41600 events read in total (3381ms).
[17:56:38.006] <TB2> INFO: Test took 4250ms.
[17:56:39.009] <TB2> INFO: scanning low vcal = 180
[17:56:39.286] <TB2> INFO: Expecting 41600 events.
[17:56:43.257] <TB2> INFO: 41600 events read in total (3380ms).
[17:56:43.258] <TB2> INFO: Test took 4249ms.
[17:56:43.261] <TB2> INFO: scanning low vcal = 190
[17:56:43.537] <TB2> INFO: Expecting 41600 events.
[17:56:47.506] <TB2> INFO: 41600 events read in total (3377ms).
[17:56:47.506] <TB2> INFO: Test took 4245ms.
[17:56:47.509] <TB2> INFO: scanning low vcal = 200
[17:56:47.786] <TB2> INFO: Expecting 41600 events.
[17:56:51.761] <TB2> INFO: 41600 events read in total (3384ms).
[17:56:51.762] <TB2> INFO: Test took 4253ms.
[17:56:51.764] <TB2> INFO: scanning low vcal = 210
[17:56:52.041] <TB2> INFO: Expecting 41600 events.
[17:56:55.978] <TB2> INFO: 41600 events read in total (3346ms).
[17:56:55.979] <TB2> INFO: Test took 4215ms.
[17:56:55.982] <TB2> INFO: scanning low vcal = 220
[17:56:56.259] <TB2> INFO: Expecting 41600 events.
[17:57:00.218] <TB2> INFO: 41600 events read in total (3367ms).
[17:57:00.219] <TB2> INFO: Test took 4237ms.
[17:57:00.222] <TB2> INFO: scanning low vcal = 230
[17:57:00.499] <TB2> INFO: Expecting 41600 events.
[17:57:04.443] <TB2> INFO: 41600 events read in total (3352ms).
[17:57:04.444] <TB2> INFO: Test took 4222ms.
[17:57:04.446] <TB2> INFO: scanning low vcal = 240
[17:57:04.723] <TB2> INFO: Expecting 41600 events.
[17:57:08.661] <TB2> INFO: 41600 events read in total (3347ms).
[17:57:08.661] <TB2> INFO: Test took 4214ms.
[17:57:08.664] <TB2> INFO: scanning low vcal = 250
[17:57:08.941] <TB2> INFO: Expecting 41600 events.
[17:57:12.865] <TB2> INFO: 41600 events read in total (3333ms).
[17:57:12.865] <TB2> INFO: Test took 4201ms.
[17:57:12.869] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[17:57:13.145] <TB2> INFO: Expecting 41600 events.
[17:57:17.106] <TB2> INFO: 41600 events read in total (3370ms).
[17:57:17.107] <TB2> INFO: Test took 4238ms.
[17:57:17.109] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[17:57:17.386] <TB2> INFO: Expecting 41600 events.
[17:57:21.327] <TB2> INFO: 41600 events read in total (3349ms).
[17:57:21.327] <TB2> INFO: Test took 4218ms.
[17:57:21.330] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[17:57:21.607] <TB2> INFO: Expecting 41600 events.
[17:57:25.541] <TB2> INFO: 41600 events read in total (3343ms).
[17:57:25.542] <TB2> INFO: Test took 4212ms.
[17:57:25.545] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[17:57:25.821] <TB2> INFO: Expecting 41600 events.
[17:57:29.771] <TB2> INFO: 41600 events read in total (3358ms).
[17:57:29.771] <TB2> INFO: Test took 4226ms.
[17:57:29.774] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[17:57:30.051] <TB2> INFO: Expecting 41600 events.
[17:57:33.002] <TB2> INFO: 41600 events read in total (3360ms).
[17:57:33.003] <TB2> INFO: Test took 4229ms.
[17:57:34.483] <TB2> INFO: PixTestGainPedestal::measure() done
[17:58:14.727] <TB2> INFO: PixTestGainPedestal::fit() done
[17:58:14.727] <TB2> INFO: non-linearity mean: 0.979 0.981 0.981 0.928 0.979 0.984 0.958 0.983 0.983 0.929 0.985 0.942 0.979 0.948 0.972 0.978
[17:58:14.727] <TB2> INFO: non-linearity RMS: 0.005 0.005 0.003 0.094 0.005 0.002 0.161 0.003 0.004 0.110 0.004 0.061 0.005 0.138 0.016 0.004
[17:58:14.727] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[17:58:14.741] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[17:58:14.755] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[17:58:14.769] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[17:58:14.782] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[17:58:14.796] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[17:58:14.810] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[17:58:14.824] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[17:58:14.838] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[17:58:14.851] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[17:58:14.865] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[17:58:14.880] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[17:58:14.898] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[17:58:14.917] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[17:58:14.935] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[17:58:14.955] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[17:58:14.974] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 166 seconds
[17:58:14.974] <TB2> INFO: Decoding statistics:
[17:58:14.974] <TB2> INFO: General information:
[17:58:14.974] <TB2> INFO: 16bit words read: 3327874
[17:58:14.974] <TB2> INFO: valid events total: 332800
[17:58:14.974] <TB2> INFO: empty events: 0
[17:58:14.974] <TB2> INFO: valid events with pixels: 332800
[17:58:14.974] <TB2> INFO: valid pixel hits: 665537
[17:58:14.974] <TB2> INFO: Event errors: 0
[17:58:14.974] <TB2> INFO: start marker: 0
[17:58:14.974] <TB2> INFO: stop marker: 0
[17:58:14.974] <TB2> INFO: overflow: 0
[17:58:14.974] <TB2> INFO: invalid 5bit words: 0
[17:58:14.974] <TB2> INFO: invalid XOR eye diagram: 0
[17:58:14.974] <TB2> INFO: frame (failed synchr.): 0
[17:58:14.974] <TB2> INFO: idle data (no TBM trl): 0
[17:58:14.974] <TB2> INFO: no data (only TBM hdr): 0
[17:58:14.974] <TB2> INFO: TBM errors: 0
[17:58:14.974] <TB2> INFO: flawed TBM headers: 0
[17:58:14.974] <TB2> INFO: flawed TBM trailers: 0
[17:58:14.974] <TB2> INFO: event ID mismatches: 0
[17:58:14.974] <TB2> INFO: ROC errors: 0
[17:58:14.974] <TB2> INFO: missing ROC header(s): 0
[17:58:14.974] <TB2> INFO: misplaced readback start: 0
[17:58:14.974] <TB2> INFO: Pixel decoding errors: 0
[17:58:14.974] <TB2> INFO: pixel data incomplete: 0
[17:58:14.974] <TB2> INFO: pixel address: 0
[17:58:14.974] <TB2> INFO: pulse height fill bit: 0
[17:58:14.974] <TB2> INFO: buffer corruption: 0
[17:58:14.994] <TB2> INFO: Decoding statistics:
[17:58:14.994] <TB2> INFO: General information:
[17:58:14.994] <TB2> INFO: 16bit words read: 3457288
[17:58:14.994] <TB2> INFO: valid events total: 353536
[17:58:14.994] <TB2> INFO: empty events: 18237
[17:58:14.994] <TB2> INFO: valid events with pixels: 335299
[17:58:14.994] <TB2> INFO: valid pixel hits: 668036
[17:58:14.994] <TB2> INFO: Event errors: 0
[17:58:14.994] <TB2> INFO: start marker: 0
[17:58:14.994] <TB2> INFO: stop marker: 0
[17:58:14.994] <TB2> INFO: overflow: 0
[17:58:14.994] <TB2> INFO: invalid 5bit words: 0
[17:58:14.994] <TB2> INFO: invalid XOR eye diagram: 0
[17:58:14.994] <TB2> INFO: frame (failed synchr.): 0
[17:58:14.994] <TB2> INFO: idle data (no TBM trl): 0
[17:58:14.994] <TB2> INFO: no data (only TBM hdr): 0
[17:58:14.994] <TB2> INFO: TBM errors: 0
[17:58:14.994] <TB2> INFO: flawed TBM headers: 0
[17:58:14.994] <TB2> INFO: flawed TBM trailers: 0
[17:58:14.994] <TB2> INFO: event ID mismatches: 0
[17:58:14.994] <TB2> INFO: ROC errors: 0
[17:58:14.994] <TB2> INFO: missing ROC header(s): 0
[17:58:14.994] <TB2> INFO: misplaced readback start: 0
[17:58:14.994] <TB2> INFO: Pixel decoding errors: 0
[17:58:14.994] <TB2> INFO: pixel data incomplete: 0
[17:58:14.994] <TB2> INFO: pixel address: 0
[17:58:14.994] <TB2> INFO: pulse height fill bit: 0
[17:58:14.994] <TB2> INFO: buffer corruption: 0
[17:58:14.994] <TB2> INFO: enter test to run
[17:58:14.994] <TB2> INFO: test: Trim80 no parameter change
[17:58:14.994] <TB2> INFO: running: trim80
[17:58:15.017] <TB2> INFO: ######################################################################
[17:58:15.017] <TB2> INFO: PixTestTrim80::doTest()
[17:58:15.017] <TB2> INFO: ######################################################################
[17:58:15.018] <TB2> INFO: ----------------------------------------------------------------------
[17:58:15.018] <TB2> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[17:58:15.018] <TB2> INFO: ----------------------------------------------------------------------
[17:58:15.063] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[17:58:15.063] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:58:15.072] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:58:15.072] <TB2> INFO: run 1 of 1
[17:58:15.306] <TB2> INFO: Expecting 5025280 events.
[17:58:42.452] <TB2> INFO: 673584 events read in total (26554ms).
[17:59:09.683] <TB2> INFO: 1344936 events read in total (53785ms).
[17:59:37.549] <TB2> INFO: 2013720 events read in total (81651ms).
[18:00:04.492] <TB2> INFO: 2682752 events read in total (108594ms).
[18:00:31.408] <TB2> INFO: 3351584 events read in total (135510ms).
[18:00:58.169] <TB2> INFO: 4018856 events read in total (162271ms).
[18:01:24.727] <TB2> INFO: 4685176 events read in total (188829ms).
[18:01:38.275] <TB2> INFO: 5025280 events read in total (202377ms).
[18:01:38.334] <TB2> INFO: Test took 203263ms.
[18:02:01.489] <TB2> INFO: ROC 0 VthrComp = 76
[18:02:01.489] <TB2> INFO: ROC 1 VthrComp = 73
[18:02:01.490] <TB2> INFO: ROC 2 VthrComp = 65
[18:02:01.490] <TB2> INFO: ROC 3 VthrComp = 66
[18:02:01.490] <TB2> INFO: ROC 4 VthrComp = 68
[18:02:01.490] <TB2> INFO: ROC 5 VthrComp = 61
[18:02:01.490] <TB2> INFO: ROC 6 VthrComp = 70
[18:02:01.490] <TB2> INFO: ROC 7 VthrComp = 67
[18:02:01.490] <TB2> INFO: ROC 8 VthrComp = 64
[18:02:01.490] <TB2> INFO: ROC 9 VthrComp = 67
[18:02:01.491] <TB2> INFO: ROC 10 VthrComp = 72
[18:02:01.491] <TB2> INFO: ROC 11 VthrComp = 76
[18:02:01.491] <TB2> INFO: ROC 12 VthrComp = 67
[18:02:01.491] <TB2> INFO: ROC 13 VthrComp = 65
[18:02:01.491] <TB2> INFO: ROC 14 VthrComp = 72
[18:02:01.491] <TB2> INFO: ROC 15 VthrComp = 68
[18:02:01.732] <TB2> INFO: Expecting 41600 events.
[18:02:05.220] <TB2> INFO: 41600 events read in total (2896ms).
[18:02:05.221] <TB2> INFO: Test took 3728ms.
[18:02:05.229] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[18:02:05.229] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[18:02:05.238] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:02:05.238] <TB2> INFO: run 1 of 1
[18:02:05.516] <TB2> INFO: Expecting 5025280 events.
[18:02:33.195] <TB2> INFO: 683360 events read in total (27087ms).
[18:03:00.218] <TB2> INFO: 1364320 events read in total (54111ms).
[18:03:27.966] <TB2> INFO: 2044528 events read in total (81858ms).
[18:03:54.583] <TB2> INFO: 2721336 events read in total (108475ms).
[18:04:21.376] <TB2> INFO: 3394424 events read in total (135268ms).
[18:04:47.973] <TB2> INFO: 4066792 events read in total (161865ms).
[18:05:14.861] <TB2> INFO: 4738848 events read in total (188753ms).
[18:05:26.480] <TB2> INFO: 5025280 events read in total (200372ms).
[18:05:26.545] <TB2> INFO: Test took 201307ms.
[18:05:50.644] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 110.731 for pixel 0/69 mean/min/max = 94.0217/77.0868/110.957
[18:05:50.644] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 110.016 for pixel 12/3 mean/min/max = 93.5535/77.0837/110.023
[18:05:50.645] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 108.493 for pixel 4/74 mean/min/max = 91.7691/74.6116/108.927
[18:05:50.645] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 106.123 for pixel 14/79 mean/min/max = 90.3048/74.2716/106.338
[18:05:50.645] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 105.893 for pixel 14/5 mean/min/max = 90.3898/74.7841/105.996
[18:05:50.646] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 107.678 for pixel 0/47 mean/min/max = 91.4394/75.1856/107.693
[18:05:50.646] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 107.473 for pixel 0/21 mean/min/max = 91.0584/74.4882/107.629
[18:05:50.646] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 106.175 for pixel 18/61 mean/min/max = 90.2067/73.9706/106.443
[18:05:50.647] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 108.575 for pixel 10/4 mean/min/max = 91.7408/74.8896/108.592
[18:05:50.647] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 106.49 for pixel 21/65 mean/min/max = 90.7644/74.5656/106.963
[18:05:50.648] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 110.709 for pixel 5/13 mean/min/max = 93.7746/76.4954/111.054
[18:05:50.648] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 112.973 for pixel 14/73 mean/min/max = 95.7147/78.1938/113.236
[18:05:50.648] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 108.162 for pixel 48/71 mean/min/max = 91.0553/73.9455/108.165
[18:05:50.649] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 109.227 for pixel 0/19 mean/min/max = 92.2619/75.178/109.346
[18:05:50.649] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 116.533 for pixel 13/67 mean/min/max = 95.9898/75.1783/116.801
[18:05:50.649] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 107.246 for pixel 17/77 mean/min/max = 90.7922/74.2568/107.328
[18:05:50.650] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:50.738] <TB2> INFO: Expecting 411648 events.
[18:06:00.101] <TB2> INFO: 411648 events read in total (8771ms).
[18:06:00.111] <TB2> INFO: Expecting 411648 events.
[18:06:09.333] <TB2> INFO: 411648 events read in total (8819ms).
[18:06:09.346] <TB2> INFO: Expecting 411648 events.
[18:06:18.522] <TB2> INFO: 411648 events read in total (8773ms).
[18:06:18.538] <TB2> INFO: Expecting 411648 events.
[18:06:27.660] <TB2> INFO: 411648 events read in total (8720ms).
[18:06:27.674] <TB2> INFO: Expecting 411648 events.
[18:06:36.818] <TB2> INFO: 411648 events read in total (8741ms).
[18:06:36.834] <TB2> INFO: Expecting 411648 events.
[18:06:45.944] <TB2> INFO: 411648 events read in total (8707ms).
[18:06:45.964] <TB2> INFO: Expecting 411648 events.
[18:06:55.084] <TB2> INFO: 411648 events read in total (8717ms).
[18:06:55.106] <TB2> INFO: Expecting 411648 events.
[18:07:04.325] <TB2> INFO: 411648 events read in total (8816ms).
[18:07:04.349] <TB2> INFO: Expecting 411648 events.
[18:07:13.544] <TB2> INFO: 411648 events read in total (8792ms).
[18:07:13.580] <TB2> INFO: Expecting 411648 events.
[18:07:22.666] <TB2> INFO: 411648 events read in total (8683ms).
[18:07:22.696] <TB2> INFO: Expecting 411648 events.
[18:07:31.721] <TB2> INFO: 411648 events read in total (8622ms).
[18:07:31.754] <TB2> INFO: Expecting 411648 events.
[18:07:40.769] <TB2> INFO: 411648 events read in total (8612ms).
[18:07:40.804] <TB2> INFO: Expecting 411648 events.
[18:07:49.913] <TB2> INFO: 411648 events read in total (8706ms).
[18:07:49.966] <TB2> INFO: Expecting 411648 events.
[18:07:59.084] <TB2> INFO: 411648 events read in total (8715ms).
[18:07:59.125] <TB2> INFO: Expecting 411648 events.
[18:08:08.173] <TB2> INFO: 411648 events read in total (8645ms).
[18:08:08.231] <TB2> INFO: Expecting 411648 events.
[18:08:17.261] <TB2> INFO: 411648 events read in total (8627ms).
[18:08:17.309] <TB2> INFO: Test took 146659ms.
[18:08:18.837] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[18:08:18.846] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:08:18.846] <TB2> INFO: run 1 of 1
[18:08:19.122] <TB2> INFO: Expecting 5025280 events.
[18:08:45.958] <TB2> INFO: 663064 events read in total (26244ms).
[18:09:12.444] <TB2> INFO: 1324608 events read in total (52730ms).
[18:09:38.780] <TB2> INFO: 1985560 events read in total (79066ms).
[18:10:05.368] <TB2> INFO: 2644848 events read in total (105654ms).
[18:10:31.844] <TB2> INFO: 3299360 events read in total (132130ms).
[18:10:58.297] <TB2> INFO: 3951024 events read in total (158583ms).
[18:11:24.577] <TB2> INFO: 4602192 events read in total (184863ms).
[18:11:41.656] <TB2> INFO: 5025280 events read in total (201942ms).
[18:11:41.719] <TB2> INFO: Test took 202873ms.
[18:12:05.248] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 49.473498 .. 102.497419
[18:12:05.493] <TB2> INFO: Expecting 208000 events.
[18:12:15.205] <TB2> INFO: 208000 events read in total (9120ms).
[18:12:15.206] <TB2> INFO: Test took 9957ms.
[18:12:15.251] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 39 .. 112 (-1/-1) hits flags = 528 (plus default)
[18:12:15.260] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:12:15.260] <TB2> INFO: run 1 of 1
[18:12:15.538] <TB2> INFO: Expecting 2462720 events.
[18:12:43.535] <TB2> INFO: 688552 events read in total (27406ms).
[18:13:10.912] <TB2> INFO: 1375968 events read in total (54783ms).
[18:13:38.949] <TB2> INFO: 2057104 events read in total (82820ms).
[18:13:55.253] <TB2> INFO: 2462720 events read in total (99124ms).
[18:13:55.288] <TB2> INFO: Test took 100029ms.
[18:14:14.248] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 60.873690 .. 91.980820
[18:14:14.525] <TB2> INFO: Expecting 208000 events.
[18:14:24.310] <TB2> INFO: 208000 events read in total (9194ms).
[18:14:24.311] <TB2> INFO: Test took 10062ms.
[18:14:24.361] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 50 .. 101 (-1/-1) hits flags = 528 (plus default)
[18:14:24.371] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:14:24.371] <TB2> INFO: run 1 of 1
[18:14:24.648] <TB2> INFO: Expecting 1730560 events.
[18:14:53.196] <TB2> INFO: 698808 events read in total (27956ms).
[18:15:20.912] <TB2> INFO: 1396928 events read in total (55672ms).
[18:15:34.646] <TB2> INFO: 1730560 events read in total (69406ms).
[18:15:34.683] <TB2> INFO: Test took 70313ms.
[18:15:52.504] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 66.504235 .. 86.580961
[18:15:52.737] <TB2> INFO: Expecting 208000 events.
[18:16:02.323] <TB2> INFO: 208000 events read in total (8994ms).
[18:16:02.324] <TB2> INFO: Test took 9819ms.
[18:16:02.390] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 56 .. 96 (-1/-1) hits flags = 528 (plus default)
[18:16:02.402] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:16:02.402] <TB2> INFO: run 1 of 1
[18:16:02.680] <TB2> INFO: Expecting 1364480 events.
[18:16:31.344] <TB2> INFO: 703248 events read in total (28072ms).
[18:16:57.946] <TB2> INFO: 1364480 events read in total (54674ms).
[18:16:57.976] <TB2> INFO: Test took 55575ms.
[18:17:15.247] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 67.937014 .. 84.484074
[18:17:15.482] <TB2> INFO: Expecting 208000 events.
[18:17:25.012] <TB2> INFO: 208000 events read in total (8938ms).
[18:17:25.013] <TB2> INFO: Test took 9764ms.
[18:17:25.061] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 57 .. 94 (-1/-1) hits flags = 528 (plus default)
[18:17:25.070] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:17:25.070] <TB2> INFO: run 1 of 1
[18:17:25.349] <TB2> INFO: Expecting 1264640 events.
[18:17:53.945] <TB2> INFO: 712824 events read in total (28005ms).
[18:18:15.750] <TB2> INFO: 1264640 events read in total (49810ms).
[18:18:15.772] <TB2> INFO: Test took 50703ms.
[18:18:32.668] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[18:18:32.668] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[18:18:32.677] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:18:32.677] <TB2> INFO: run 1 of 1
[18:18:32.933] <TB2> INFO: Expecting 1364480 events.
[18:19:01.066] <TB2> INFO: 667656 events read in total (27541ms).
[18:19:28.829] <TB2> INFO: 1335168 events read in total (55304ms).
[18:19:30.410] <TB2> INFO: 1364480 events read in total (56885ms).
[18:19:30.431] <TB2> INFO: Test took 57754ms.
[18:19:47.459] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C0.dat
[18:19:47.459] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C1.dat
[18:19:47.459] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C2.dat
[18:19:47.459] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C3.dat
[18:19:47.459] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C4.dat
[18:19:47.459] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C5.dat
[18:19:47.459] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C6.dat
[18:19:47.459] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C7.dat
[18:19:47.459] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C8.dat
[18:19:47.460] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C9.dat
[18:19:47.460] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C10.dat
[18:19:47.460] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C11.dat
[18:19:47.460] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C12.dat
[18:19:47.460] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C13.dat
[18:19:47.460] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C14.dat
[18:19:47.460] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C15.dat
[18:19:47.460] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C0.dat
[18:19:47.467] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C1.dat
[18:19:47.473] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C2.dat
[18:19:47.479] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C3.dat
[18:19:47.484] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C4.dat
[18:19:47.490] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C5.dat
[18:19:47.495] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C6.dat
[18:19:47.501] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C7.dat
[18:19:47.509] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C8.dat
[18:19:47.518] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C9.dat
[18:19:47.526] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C10.dat
[18:19:47.535] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C11.dat
[18:19:47.544] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C12.dat
[18:19:47.553] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C13.dat
[18:19:47.562] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C14.dat
[18:19:47.571] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1079_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C15.dat
[18:19:47.579] <TB2> INFO: PixTestTrim80::trimTest() done
[18:19:47.579] <TB2> INFO: vtrim: 109 111 104 90 93 108 98 93 91 110 116 123 98 90 147 93
[18:19:47.579] <TB2> INFO: vthrcomp: 76 73 65 66 68 61 70 67 64 67 72 76 67 65 72 68
[18:19:47.579] <TB2> INFO: vcal mean: 79.98 79.97 79.92 79.97 79.95 79.94 79.98 79.99 79.96 79.96 79.95 79.93 79.92 79.99 79.94 79.99
[18:19:47.579] <TB2> INFO: vcal RMS: 0.85 0.77 0.76 0.76 0.76 0.76 0.75 0.74 0.74 0.77 0.76 0.87 0.81 0.76 0.93 0.77
[18:19:47.579] <TB2> INFO: bits mean: 9.54 9.93 10.11 10.20 10.61 10.85 10.46 10.47 9.92 10.68 9.86 9.86 10.88 9.97 10.37 10.66
[18:19:47.579] <TB2> INFO: bits RMS: 2.28 2.08 2.37 2.46 2.19 1.96 2.24 2.40 2.43 2.15 2.19 1.94 2.10 2.40 2.03 2.18
[18:19:47.586] <TB2> INFO: ----------------------------------------------------------------------
[18:19:47.586] <TB2> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[18:19:47.586] <TB2> INFO: ----------------------------------------------------------------------
[18:19:47.589] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[18:19:47.601] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[18:19:47.601] <TB2> INFO: run 1 of 1
[18:19:47.900] <TB2> INFO: Expecting 4160000 events.
[18:20:19.453] <TB2> INFO: 742130 events read in total (30961ms).
[18:20:50.213] <TB2> INFO: 1479850 events read in total (61721ms).
[18:21:21.376] <TB2> INFO: 2213330 events read in total (92884ms).
[18:21:52.296] <TB2> INFO: 2941900 events read in total (123804ms).
[18:22:23.118] <TB2> INFO: 3668945 events read in total (154626ms).
[18:22:43.927] <TB2> INFO: 4160000 events read in total (175435ms).
[18:22:43.988] <TB2> INFO: Test took 176388ms.
[18:23:12.527] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[18:23:12.536] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[18:23:12.536] <TB2> INFO: run 1 of 1
[18:23:12.778] <TB2> INFO: Expecting 4472000 events.
[18:23:43.778] <TB2> INFO: 701490 events read in total (30407ms).
[18:24:13.896] <TB2> INFO: 1399590 events read in total (60525ms).
[18:24:44.567] <TB2> INFO: 2094560 events read in total (91196ms).
[18:25:14.824] <TB2> INFO: 2784895 events read in total (121453ms).
[18:25:44.877] <TB2> INFO: 3474285 events read in total (151506ms).
[18:26:15.201] <TB2> INFO: 4163745 events read in total (181830ms).
[18:26:28.585] <TB2> INFO: 4472000 events read in total (195214ms).
[18:26:28.645] <TB2> INFO: Test took 196110ms.
[18:26:59.058] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[18:26:59.069] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[18:26:59.069] <TB2> INFO: run 1 of 1
[18:26:59.301] <TB2> INFO: Expecting 4097600 events.
[18:27:30.644] <TB2> INFO: 722135 events read in total (30751ms).
[18:28:01.770] <TB2> INFO: 1440095 events read in total (61877ms).
[18:28:32.021] <TB2> INFO: 2154190 events read in total (92128ms).
[18:29:02.279] <TB2> INFO: 2863360 events read in total (122386ms).
[18:29:32.574] <TB2> INFO: 3571280 events read in total (152681ms).
[18:29:55.220] <TB2> INFO: 4097600 events read in total (175327ms).
[18:29:55.279] <TB2> INFO: Test took 176210ms.
[18:30:25.492] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[18:30:25.503] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[18:30:25.503] <TB2> INFO: run 1 of 1
[18:30:25.778] <TB2> INFO: Expecting 4097600 events.
[18:30:58.091] <TB2> INFO: 722120 events read in total (31722ms).
[18:31:28.428] <TB2> INFO: 1440095 events read in total (62059ms).
[18:31:58.616] <TB2> INFO: 2154065 events read in total (92247ms).
[18:32:28.856] <TB2> INFO: 2863200 events read in total (122487ms).
[18:32:59.107] <TB2> INFO: 3570970 events read in total (152738ms).
[18:33:21.671] <TB2> INFO: 4097600 events read in total (175302ms).
[18:33:21.730] <TB2> INFO: Test took 176226ms.
[18:33:49.705] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 195 (-1/-1) hits flags = 528 (plus default)
[18:33:49.715] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[18:33:49.715] <TB2> INFO: run 1 of 1
[18:33:49.947] <TB2> INFO: Expecting 4076800 events.
[18:34:21.687] <TB2> INFO: 723340 events read in total (31148ms).
[18:34:52.197] <TB2> INFO: 1442460 events read in total (61658ms).
[18:35:22.458] <TB2> INFO: 2157680 events read in total (91919ms).
[18:35:52.854] <TB2> INFO: 2868005 events read in total (122315ms).
[18:36:23.297] <TB2> INFO: 3576805 events read in total (152758ms).
[18:36:44.701] <TB2> INFO: 4076800 events read in total (174162ms).
[18:36:44.762] <TB2> INFO: Test took 175047ms.
[18:37:12.703] <TB2> INFO: PixTestTrim80::trimBitTest() done
[18:37:12.704] <TB2> INFO: PixTestTrim80::doTest() done, duration: 2337 seconds
[18:37:13.372] <TB2> INFO: enter test to run
[18:37:13.372] <TB2> INFO: test: exit no parameter change
[18:37:13.476] <TB2> QUIET: Connection to board 156 closed.
[18:37:13.478] <TB2> INFO: pXar: this is the end, my friend