[16:34:40.592] <TB1> INFO: *** Welcome to pxar ***
[16:34:40.592] <TB1> INFO: *** Today: 2016/10/25
[16:34:40.598] <TB1> INFO: *** Version: c8ba-dirty
[16:34:40.598] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C15.dat
[16:34:40.598] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//tbmParameters_C1b.dat
[16:34:40.598] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//defaultMaskFile.dat
[16:34:40.598] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters_C15.dat
[16:34:40.652] <TB1> INFO: clk: 4
[16:34:40.652] <TB1> INFO: ctr: 4
[16:34:40.652] <TB1> INFO: sda: 19
[16:34:40.652] <TB1> INFO: tin: 9
[16:34:40.652] <TB1> INFO: level: 15
[16:34:40.652] <TB1> INFO: triggerdelay: 0
[16:34:40.652] <TB1> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[16:34:40.652] <TB1> INFO: Log level: INFO
[16:34:40.661] <TB1> INFO: Found DTB DTB_WXBYFL
[16:34:40.671] <TB1> QUIET: Connection to board DTB_WXBYFL opened.
[16:34:40.673] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 153
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXBYFL
MAC address: 40D855118099
Hostname: pixelDTB153
Comment:
------------------------------------------------------
[16:34:40.674] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[16:34:42.228] <TB1> INFO: DUT info:
[16:34:42.228] <TB1> INFO: The DUT currently contains the following objects:
[16:34:42.228] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[16:34:42.228] <TB1> INFO: TBM Core alpha (0): 7 registers set
[16:34:42.228] <TB1> INFO: TBM Core beta (1): 7 registers set
[16:34:42.228] <TB1> INFO: TBM Core alpha (2): 7 registers set
[16:34:42.228] <TB1> INFO: TBM Core beta (3): 7 registers set
[16:34:42.228] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[16:34:42.228] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:42.228] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:42.228] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:42.228] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:42.228] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:42.228] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:42.228] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:42.228] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:42.229] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:42.229] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:42.229] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:42.229] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:42.229] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:42.229] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:42.229] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:42.229] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[16:34:42.629] <TB1> INFO: enter 'restricted' command line mode
[16:34:42.629] <TB1> INFO: enter test to run
[16:34:42.629] <TB1> INFO: test: pretest no parameter change
[16:34:42.630] <TB1> INFO: running: pretest
[16:34:43.194] <TB1> INFO: ######################################################################
[16:34:43.195] <TB1> INFO: PixTestPretest::doTest()
[16:34:43.195] <TB1> INFO: ######################################################################
[16:34:43.196] <TB1> INFO: ----------------------------------------------------------------------
[16:34:43.196] <TB1> INFO: PixTestPretest::programROC()
[16:34:43.196] <TB1> INFO: ----------------------------------------------------------------------
[16:35:01.209] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[16:35:01.209] <TB1> INFO: IA differences per ROC: 22.5 18.5 20.1 16.9 18.5 17.7 22.5 18.5 20.1 17.7 20.1 19.3 20.1 17.7 19.3 19.3
[16:35:01.243] <TB1> INFO: ----------------------------------------------------------------------
[16:35:01.243] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[16:35:01.243] <TB1> INFO: ----------------------------------------------------------------------
[16:35:22.488] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 384.3 mA = 24.0187 mA/ROC
[16:35:22.488] <TB1> INFO: i(loss) [mA/ROC]: 20.1 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3 20.1 19.3 19.3 19.3 20.1 19.3 19.3
[16:35:22.517] <TB1> INFO: ----------------------------------------------------------------------
[16:35:22.517] <TB1> INFO: PixTestPretest::findTiming()
[16:35:22.517] <TB1> INFO: ----------------------------------------------------------------------
[16:35:22.517] <TB1> INFO: PixTestCmd::init()

[16:35:53.427] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 3, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[16:35:53.427] <TB1> INFO: (success/tries = 100/100), width = 3
[16:35:54.924] <TB1> INFO: ----------------------------------------------------------------------
[16:35:54.924] <TB1> INFO: PixTestPretest::findWorkingPixel()
[16:35:54.925] <TB1> INFO: ----------------------------------------------------------------------
[16:35:55.016] <TB1> INFO: Expecting 231680 events.
[16:36:04.648] <TB1> INFO: 231680 events read in total (9041ms).
[16:36:04.656] <TB1> INFO: Test took 9729ms.
[16:36:04.902] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[16:36:04.931] <TB1> INFO: ----------------------------------------------------------------------
[16:36:04.931] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[16:36:04.931] <TB1> INFO: ----------------------------------------------------------------------
[16:36:05.023] <TB1> INFO: Expecting 231680 events.
[16:36:14.698] <TB1> INFO: 231680 events read in total (9084ms).
[16:36:14.705] <TB1> INFO: Test took 9770ms.
[16:36:14.966] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[16:36:14.966] <TB1> INFO: CalDel: 126 100 127 128 124 111 129 114 119 143 113 113 136 115 117 116
[16:36:14.966] <TB1> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 54 51 51 52 52 51 51
[16:36:14.969] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C0.dat
[16:36:14.969] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C1.dat
[16:36:14.969] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C2.dat
[16:36:14.969] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C3.dat
[16:36:14.969] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C4.dat
[16:36:14.969] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C5.dat
[16:36:14.969] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C6.dat
[16:36:14.969] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C7.dat
[16:36:14.969] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C8.dat
[16:36:14.970] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C9.dat
[16:36:14.970] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C10.dat
[16:36:14.970] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C11.dat
[16:36:14.970] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C12.dat
[16:36:14.970] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C13.dat
[16:36:14.970] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C14.dat
[16:36:14.970] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters_C15.dat
[16:36:14.970] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//tbmParameters_C0a.dat
[16:36:14.970] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//tbmParameters_C0b.dat
[16:36:14.970] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//tbmParameters_C1a.dat
[16:36:14.971] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//tbmParameters_C1b.dat
[16:36:14.971] <TB1> INFO: PixTestPretest::doTest() done, duration: 92 seconds
[16:36:15.066] <TB1> INFO: enter test to run
[16:36:15.066] <TB1> INFO: test: FullTest no parameter change
[16:36:15.066] <TB1> INFO: running: fulltest
[16:36:15.066] <TB1> INFO: ######################################################################
[16:36:15.066] <TB1> INFO: PixTestFullTest::doTest()
[16:36:15.066] <TB1> INFO: ######################################################################
[16:36:15.067] <TB1> INFO: ######################################################################
[16:36:15.067] <TB1> INFO: PixTestAlive::doTest()
[16:36:15.067] <TB1> INFO: ######################################################################
[16:36:15.068] <TB1> INFO: ----------------------------------------------------------------------
[16:36:15.068] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:36:15.068] <TB1> INFO: ----------------------------------------------------------------------
[16:36:15.305] <TB1> INFO: Expecting 41600 events.
[16:36:18.817] <TB1> INFO: 41600 events read in total (2920ms).
[16:36:18.817] <TB1> INFO: Test took 3747ms.
[16:36:19.044] <TB1> INFO: PixTestAlive::aliveTest() done
[16:36:19.044] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[16:36:19.045] <TB1> INFO: ----------------------------------------------------------------------
[16:36:19.045] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:36:19.045] <TB1> INFO: ----------------------------------------------------------------------
[16:36:19.277] <TB1> INFO: Expecting 41600 events.
[16:36:22.252] <TB1> INFO: 41600 events read in total (2383ms).
[16:36:22.253] <TB1> INFO: Test took 3207ms.
[16:36:22.253] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[16:36:22.492] <TB1> INFO: PixTestAlive::maskTest() done
[16:36:22.493] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[16:36:22.494] <TB1> INFO: ----------------------------------------------------------------------
[16:36:22.494] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:36:22.494] <TB1> INFO: ----------------------------------------------------------------------
[16:36:22.728] <TB1> INFO: Expecting 41600 events.
[16:36:26.270] <TB1> INFO: 41600 events read in total (2951ms).
[16:36:26.270] <TB1> INFO: Test took 3775ms.
[16:36:26.497] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[16:36:26.497] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[16:36:26.497] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[16:36:26.497] <TB1> INFO: Decoding statistics:
[16:36:26.497] <TB1> INFO: General information:
[16:36:26.497] <TB1> INFO: 16bit words read: 0
[16:36:26.497] <TB1> INFO: valid events total: 0
[16:36:26.497] <TB1> INFO: empty events: 0
[16:36:26.497] <TB1> INFO: valid events with pixels: 0
[16:36:26.497] <TB1> INFO: valid pixel hits: 0
[16:36:26.497] <TB1> INFO: Event errors: 0
[16:36:26.497] <TB1> INFO: start marker: 0
[16:36:26.497] <TB1> INFO: stop marker: 0
[16:36:26.497] <TB1> INFO: overflow: 0
[16:36:26.497] <TB1> INFO: invalid 5bit words: 0
[16:36:26.497] <TB1> INFO: invalid XOR eye diagram: 0
[16:36:26.497] <TB1> INFO: frame (failed synchr.): 0
[16:36:26.497] <TB1> INFO: idle data (no TBM trl): 0
[16:36:26.497] <TB1> INFO: no data (only TBM hdr): 0
[16:36:26.497] <TB1> INFO: TBM errors: 0
[16:36:26.497] <TB1> INFO: flawed TBM headers: 0
[16:36:26.497] <TB1> INFO: flawed TBM trailers: 0
[16:36:26.497] <TB1> INFO: event ID mismatches: 0
[16:36:26.497] <TB1> INFO: ROC errors: 0
[16:36:26.497] <TB1> INFO: missing ROC header(s): 0
[16:36:26.497] <TB1> INFO: misplaced readback start: 0
[16:36:26.497] <TB1> INFO: Pixel decoding errors: 0
[16:36:26.497] <TB1> INFO: pixel data incomplete: 0
[16:36:26.497] <TB1> INFO: pixel address: 0
[16:36:26.497] <TB1> INFO: pulse height fill bit: 0
[16:36:26.497] <TB1> INFO: buffer corruption: 0
[16:36:26.504] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C15.dat
[16:36:26.504] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[16:36:26.505] <TB1> INFO: ######################################################################
[16:36:26.505] <TB1> INFO: PixTestReadback::doTest()
[16:36:26.505] <TB1> INFO: ######################################################################
[16:36:26.505] <TB1> INFO: ----------------------------------------------------------------------
[16:36:26.505] <TB1> INFO: PixTestReadback::CalibrateVd()
[16:36:26.505] <TB1> INFO: ----------------------------------------------------------------------
[16:36:36.465] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C0.dat
[16:36:36.465] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C1.dat
[16:36:36.465] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C2.dat
[16:36:36.465] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C3.dat
[16:36:36.465] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C4.dat
[16:36:36.465] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C5.dat
[16:36:36.465] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C6.dat
[16:36:36.465] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C7.dat
[16:36:36.465] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C8.dat
[16:36:36.465] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C9.dat
[16:36:36.465] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C10.dat
[16:36:36.465] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C11.dat
[16:36:36.466] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C12.dat
[16:36:36.466] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C13.dat
[16:36:36.466] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C14.dat
[16:36:36.466] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C15.dat
[16:36:36.492] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[16:36:36.492] <TB1> INFO: ----------------------------------------------------------------------
[16:36:36.492] <TB1> INFO: PixTestReadback::CalibrateVa()
[16:36:36.492] <TB1> INFO: ----------------------------------------------------------------------
[16:36:46.382] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C0.dat
[16:36:46.382] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C1.dat
[16:36:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C2.dat
[16:36:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C3.dat
[16:36:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C4.dat
[16:36:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C5.dat
[16:36:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C6.dat
[16:36:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C7.dat
[16:36:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C8.dat
[16:36:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C9.dat
[16:36:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C10.dat
[16:36:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C11.dat
[16:36:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C12.dat
[16:36:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C13.dat
[16:36:46.383] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C14.dat
[16:36:46.384] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C15.dat
[16:36:46.411] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[16:36:46.411] <TB1> INFO: ----------------------------------------------------------------------
[16:36:46.411] <TB1> INFO: PixTestReadback::readbackVbg()
[16:36:46.411] <TB1> INFO: ----------------------------------------------------------------------
[16:36:54.055] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[16:36:54.055] <TB1> INFO: ----------------------------------------------------------------------
[16:36:54.055] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[16:36:54.055] <TB1> INFO: ----------------------------------------------------------------------
[16:36:54.055] <TB1> INFO: Vbg will be calibrated using Vd calibration
[16:36:54.055] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 146.6calibrated Vbg = 1.14272 :::*/*/*/*/
[16:36:54.055] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 158calibrated Vbg = 1.14796 :::*/*/*/*/
[16:36:54.055] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 156.8calibrated Vbg = 1.1402 :::*/*/*/*/
[16:36:54.055] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 157.3calibrated Vbg = 1.14476 :::*/*/*/*/
[16:36:54.055] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 156.2calibrated Vbg = 1.14557 :::*/*/*/*/
[16:36:54.055] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 152.4calibrated Vbg = 1.15535 :::*/*/*/*/
[16:36:54.055] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 159.2calibrated Vbg = 1.15354 :::*/*/*/*/
[16:36:54.055] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 159.6calibrated Vbg = 1.15258 :::*/*/*/*/
[16:36:54.055] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 147.9calibrated Vbg = 1.14539 :::*/*/*/*/
[16:36:54.055] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 160.5calibrated Vbg = 1.14792 :::*/*/*/*/
[16:36:54.055] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 148.8calibrated Vbg = 1.13945 :::*/*/*/*/
[16:36:54.055] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 151.8calibrated Vbg = 1.1421 :::*/*/*/*/
[16:36:54.055] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 151.6calibrated Vbg = 1.15197 :::*/*/*/*/
[16:36:54.055] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 159calibrated Vbg = 1.14756 :::*/*/*/*/
[16:36:54.055] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 145calibrated Vbg = 1.14766 :::*/*/*/*/
[16:36:54.055] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 151.6calibrated Vbg = 1.14323 :::*/*/*/*/
[16:36:54.057] <TB1> INFO: ----------------------------------------------------------------------
[16:36:54.057] <TB1> INFO: PixTestReadback::CalibrateIa()
[16:36:54.057] <TB1> INFO: ----------------------------------------------------------------------
[16:39:34.357] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C0.dat
[16:39:34.357] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C1.dat
[16:39:34.357] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C2.dat
[16:39:34.357] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C3.dat
[16:39:34.357] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C4.dat
[16:39:34.357] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C5.dat
[16:39:34.357] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C6.dat
[16:39:34.357] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C7.dat
[16:39:34.357] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C8.dat
[16:39:34.357] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C9.dat
[16:39:34.357] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C10.dat
[16:39:34.357] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C11.dat
[16:39:34.358] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C12.dat
[16:39:34.358] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C13.dat
[16:39:34.358] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C14.dat
[16:39:34.358] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//readbackCal_C15.dat
[16:39:34.385] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[16:39:34.386] <TB1> INFO: PixTestReadback::doTest() done
[16:39:34.386] <TB1> INFO: Decoding statistics:
[16:39:34.386] <TB1> INFO: General information:
[16:39:34.386] <TB1> INFO: 16bit words read: 1536
[16:39:34.386] <TB1> INFO: valid events total: 256
[16:39:34.386] <TB1> INFO: empty events: 256
[16:39:34.386] <TB1> INFO: valid events with pixels: 0
[16:39:34.386] <TB1> INFO: valid pixel hits: 0
[16:39:34.386] <TB1> INFO: Event errors: 0
[16:39:34.386] <TB1> INFO: start marker: 0
[16:39:34.386] <TB1> INFO: stop marker: 0
[16:39:34.386] <TB1> INFO: overflow: 0
[16:39:34.386] <TB1> INFO: invalid 5bit words: 0
[16:39:34.386] <TB1> INFO: invalid XOR eye diagram: 0
[16:39:34.386] <TB1> INFO: frame (failed synchr.): 0
[16:39:34.386] <TB1> INFO: idle data (no TBM trl): 0
[16:39:34.386] <TB1> INFO: no data (only TBM hdr): 0
[16:39:34.386] <TB1> INFO: TBM errors: 0
[16:39:34.386] <TB1> INFO: flawed TBM headers: 0
[16:39:34.386] <TB1> INFO: flawed TBM trailers: 0
[16:39:34.386] <TB1> INFO: event ID mismatches: 0
[16:39:34.386] <TB1> INFO: ROC errors: 0
[16:39:34.386] <TB1> INFO: missing ROC header(s): 0
[16:39:34.386] <TB1> INFO: misplaced readback start: 0
[16:39:34.386] <TB1> INFO: Pixel decoding errors: 0
[16:39:34.386] <TB1> INFO: pixel data incomplete: 0
[16:39:34.386] <TB1> INFO: pixel address: 0
[16:39:34.386] <TB1> INFO: pulse height fill bit: 0
[16:39:34.386] <TB1> INFO: buffer corruption: 0
[16:39:34.420] <TB1> INFO: ######################################################################
[16:39:34.420] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[16:39:34.420] <TB1> INFO: ######################################################################
[16:39:34.423] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[16:39:34.434] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[16:39:34.434] <TB1> INFO: run 1 of 1
[16:39:34.710] <TB1> INFO: Expecting 3120000 events.
[16:40:04.777] <TB1> INFO: 650035 events read in total (29475ms).
[16:40:34.125] <TB1> INFO: 1298635 events read in total (58823ms).











[16:41:03.409] <TB1> INFO: 1944455 events read in total (88107ms).











[16:41:32.646] <TB1> INFO: 2591580 events read in total (117344ms).











[16:41:57.049] <TB1> INFO: 3120000 events read in total (141747ms).
[16:41:57.136] <TB1> INFO: Test took 142703ms.
[16:42:22.673] <TB1> INFO: PixTestBBMap::doTest() done, duration: 168 seconds
[16:42:22.673] <TB1> INFO: number of dead bumps (per ROC): 0 0 0 0 2 0 0 0 0 0 0 1 2 0 0 0
[16:42:22.673] <TB1> INFO: separation cut (per ROC): 90 105 104 93 94 85 93 86 88 104 98 84 100 96 84 95
[16:42:22.673] <TB1> INFO: Decoding statistics:
[16:42:22.673] <TB1> INFO: General information:
[16:42:22.673] <TB1> INFO: 16bit words read: 0
[16:42:22.673] <TB1> INFO: valid events total: 0
[16:42:22.673] <TB1> INFO: empty events: 0
[16:42:22.673] <TB1> INFO: valid events with pixels: 0
[16:42:22.673] <TB1> INFO: valid pixel hits: 0
[16:42:22.673] <TB1> INFO: Event errors: 0
[16:42:22.673] <TB1> INFO: start marker: 0
[16:42:22.673] <TB1> INFO: stop marker: 0
[16:42:22.673] <TB1> INFO: overflow: 0
[16:42:22.673] <TB1> INFO: invalid 5bit words: 0
[16:42:22.673] <TB1> INFO: invalid XOR eye diagram: 0
[16:42:22.673] <TB1> INFO: frame (failed synchr.): 0
[16:42:22.673] <TB1> INFO: idle data (no TBM trl): 0
[16:42:22.673] <TB1> INFO: no data (only TBM hdr): 0
[16:42:22.673] <TB1> INFO: TBM errors: 0
[16:42:22.673] <TB1> INFO: flawed TBM headers: 0
[16:42:22.673] <TB1> INFO: flawed TBM trailers: 0
[16:42:22.673] <TB1> INFO: event ID mismatches: 0
[16:42:22.673] <TB1> INFO: ROC errors: 0
[16:42:22.673] <TB1> INFO: missing ROC header(s): 0
[16:42:22.673] <TB1> INFO: misplaced readback start: 0
[16:42:22.673] <TB1> INFO: Pixel decoding errors: 0
[16:42:22.673] <TB1> INFO: pixel data incomplete: 0
[16:42:22.673] <TB1> INFO: pixel address: 0
[16:42:22.673] <TB1> INFO: pulse height fill bit: 0
[16:42:22.673] <TB1> INFO: buffer corruption: 0
[16:42:22.717] <TB1> INFO: ######################################################################
[16:42:22.717] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:42:22.717] <TB1> INFO: ######################################################################
[16:42:22.717] <TB1> INFO: ----------------------------------------------------------------------
[16:42:22.717] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:42:22.717] <TB1> INFO: ----------------------------------------------------------------------
[16:42:22.717] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[16:42:22.727] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[16:42:22.727] <TB1> INFO: run 1 of 1
[16:42:22.993] <TB1> INFO: Expecting 36608000 events.
[16:42:46.114] <TB1> INFO: 675500 events read in total (22529ms).
[16:43:08.688] <TB1> INFO: 1335450 events read in total (45103ms).
[16:43:31.169] <TB1> INFO: 1996200 events read in total (67584ms).
[16:43:53.881] <TB1> INFO: 2655400 events read in total (90296ms).
[16:44:16.147] <TB1> INFO: 3314700 events read in total (112562ms).
[16:44:38.508] <TB1> INFO: 3971850 events read in total (134923ms).
[16:45:00.824] <TB1> INFO: 4630300 events read in total (157239ms).
[16:45:23.319] <TB1> INFO: 5288550 events read in total (179734ms).
[16:45:45.888] <TB1> INFO: 5946700 events read in total (202303ms).
[16:46:08.382] <TB1> INFO: 6605600 events read in total (224797ms).
[16:46:31.024] <TB1> INFO: 7263150 events read in total (247439ms).
[16:46:53.564] <TB1> INFO: 7921000 events read in total (269979ms).
[16:47:15.840] <TB1> INFO: 8579050 events read in total (292255ms).
[16:47:38.476] <TB1> INFO: 9238800 events read in total (314891ms).
[16:48:00.895] <TB1> INFO: 9896450 events read in total (337310ms).
[16:48:23.177] <TB1> INFO: 10552700 events read in total (359592ms).
[16:48:45.677] <TB1> INFO: 11208600 events read in total (382092ms).
[16:49:07.826] <TB1> INFO: 11865150 events read in total (404241ms).
[16:49:30.274] <TB1> INFO: 12521100 events read in total (426689ms).
[16:49:52.609] <TB1> INFO: 13178450 events read in total (449024ms).
[16:50:14.863] <TB1> INFO: 13833300 events read in total (471278ms).
[16:50:37.310] <TB1> INFO: 14489700 events read in total (493725ms).
[16:50:59.827] <TB1> INFO: 15143700 events read in total (516242ms).
[16:51:22.290] <TB1> INFO: 15797800 events read in total (538705ms).
[16:51:44.741] <TB1> INFO: 16453400 events read in total (561156ms).
[16:52:07.308] <TB1> INFO: 17108250 events read in total (583723ms).
[16:52:29.994] <TB1> INFO: 17764600 events read in total (606409ms).
[16:52:52.513] <TB1> INFO: 18418450 events read in total (628928ms).
[16:53:14.879] <TB1> INFO: 19070600 events read in total (651294ms).
[16:53:37.321] <TB1> INFO: 19721500 events read in total (673736ms).
[16:53:59.767] <TB1> INFO: 20372300 events read in total (696182ms).
[16:54:22.151] <TB1> INFO: 21022600 events read in total (718566ms).
[16:54:44.726] <TB1> INFO: 21674000 events read in total (741141ms).
[16:55:06.952] <TB1> INFO: 22323850 events read in total (763367ms).
[16:55:29.147] <TB1> INFO: 22973800 events read in total (785562ms).
[16:55:51.567] <TB1> INFO: 23624400 events read in total (807982ms).
[16:56:13.843] <TB1> INFO: 24273800 events read in total (830258ms).
[16:56:35.986] <TB1> INFO: 24922150 events read in total (852401ms).
[16:56:58.248] <TB1> INFO: 25570650 events read in total (874663ms).
[16:57:20.394] <TB1> INFO: 26218750 events read in total (896809ms).
[16:57:42.493] <TB1> INFO: 26865150 events read in total (918908ms).
[16:58:04.734] <TB1> INFO: 27514600 events read in total (941149ms).
[16:58:26.857] <TB1> INFO: 28162350 events read in total (963272ms).
[16:58:49.223] <TB1> INFO: 28810200 events read in total (985638ms).
[16:59:11.165] <TB1> INFO: 29457650 events read in total (1007580ms).
[16:59:33.233] <TB1> INFO: 30103600 events read in total (1029648ms).
[16:59:55.463] <TB1> INFO: 30751400 events read in total (1051878ms).
[17:00:17.492] <TB1> INFO: 31397850 events read in total (1073907ms).
[17:00:39.620] <TB1> INFO: 32046350 events read in total (1096035ms).
[17:01:01.908] <TB1> INFO: 32695750 events read in total (1118323ms).
[17:01:24.094] <TB1> INFO: 33345200 events read in total (1140509ms).
[17:01:46.286] <TB1> INFO: 33995150 events read in total (1162701ms).
[17:02:08.253] <TB1> INFO: 34645600 events read in total (1184668ms).
[17:02:30.517] <TB1> INFO: 35294900 events read in total (1206932ms).
[17:02:52.600] <TB1> INFO: 35946750 events read in total (1229015ms).
[17:03:15.390] <TB1> INFO: 36607300 events read in total (1251805ms).
[17:03:15.844] <TB1> INFO: 36608000 events read in total (1252259ms).
[17:03:15.899] <TB1> INFO: Test took 1253172ms.
[17:03:16.328] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:03:18.266] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:03:20.068] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:03:22.060] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:03:23.636] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:03:25.505] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:03:27.400] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:03:29.307] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:03:31.215] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:03:32.955] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:03:34.873] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:03:36.807] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:03:38.593] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:03:40.610] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:03:42.497] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:03:44.364] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:03:46.272] <TB1> INFO: PixTestScurves::scurves() done
[17:03:46.272] <TB1> INFO: Vcal mean: 118.45 123.59 125.04 114.59 110.67 106.78 117.73 112.02 110.49 123.88 110.82 102.01 117.52 116.78 113.64 111.33
[17:03:46.272] <TB1> INFO: Vcal RMS: 6.25 6.38 7.06 6.24 5.42 5.67 5.72 6.14 5.91 6.20 5.47 5.62 6.03 5.98 5.96 5.81
[17:03:46.272] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1283 seconds
[17:03:46.272] <TB1> INFO: Decoding statistics:
[17:03:46.272] <TB1> INFO: General information:
[17:03:46.272] <TB1> INFO: 16bit words read: 0
[17:03:46.272] <TB1> INFO: valid events total: 0
[17:03:46.272] <TB1> INFO: empty events: 0
[17:03:46.272] <TB1> INFO: valid events with pixels: 0
[17:03:46.272] <TB1> INFO: valid pixel hits: 0
[17:03:46.272] <TB1> INFO: Event errors: 0
[17:03:46.272] <TB1> INFO: start marker: 0
[17:03:46.272] <TB1> INFO: stop marker: 0
[17:03:46.272] <TB1> INFO: overflow: 0
[17:03:46.272] <TB1> INFO: invalid 5bit words: 0
[17:03:46.272] <TB1> INFO: invalid XOR eye diagram: 0
[17:03:46.272] <TB1> INFO: frame (failed synchr.): 0
[17:03:46.272] <TB1> INFO: idle data (no TBM trl): 0
[17:03:46.272] <TB1> INFO: no data (only TBM hdr): 0
[17:03:46.272] <TB1> INFO: TBM errors: 0
[17:03:46.272] <TB1> INFO: flawed TBM headers: 0
[17:03:46.272] <TB1> INFO: flawed TBM trailers: 0
[17:03:46.273] <TB1> INFO: event ID mismatches: 0
[17:03:46.273] <TB1> INFO: ROC errors: 0
[17:03:46.273] <TB1> INFO: missing ROC header(s): 0
[17:03:46.273] <TB1> INFO: misplaced readback start: 0
[17:03:46.273] <TB1> INFO: Pixel decoding errors: 0
[17:03:46.273] <TB1> INFO: pixel data incomplete: 0
[17:03:46.273] <TB1> INFO: pixel address: 0
[17:03:46.273] <TB1> INFO: pulse height fill bit: 0
[17:03:46.273] <TB1> INFO: buffer corruption: 0
[17:03:46.342] <TB1> INFO: ######################################################################
[17:03:46.342] <TB1> INFO: PixTestTrim::doTest()
[17:03:46.342] <TB1> INFO: ######################################################################
[17:03:46.343] <TB1> INFO: ----------------------------------------------------------------------
[17:03:46.343] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[17:03:46.343] <TB1> INFO: ----------------------------------------------------------------------
[17:03:46.384] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[17:03:46.384] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:03:46.393] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:03:46.393] <TB1> INFO: run 1 of 1
[17:03:46.632] <TB1> INFO: Expecting 5025280 events.
[17:04:17.185] <TB1> INFO: 827000 events read in total (29957ms).
[17:04:47.243] <TB1> INFO: 1651760 events read in total (60015ms).
[17:05:17.349] <TB1> INFO: 2473496 events read in total (90122ms).
[17:05:46.972] <TB1> INFO: 3292624 events read in total (119744ms).
[17:06:16.585] <TB1> INFO: 4107608 events read in total (149358ms).
[17:06:46.288] <TB1> INFO: 4920648 events read in total (179060ms).
[17:06:50.425] <TB1> INFO: 5025280 events read in total (183197ms).
[17:06:50.482] <TB1> INFO: Test took 184089ms.
[17:07:09.797] <TB1> INFO: ROC 0 VthrComp = 116
[17:07:09.797] <TB1> INFO: ROC 1 VthrComp = 124
[17:07:09.798] <TB1> INFO: ROC 2 VthrComp = 119
[17:07:09.798] <TB1> INFO: ROC 3 VthrComp = 106
[17:07:09.798] <TB1> INFO: ROC 4 VthrComp = 108
[17:07:09.799] <TB1> INFO: ROC 5 VthrComp = 105
[17:07:09.799] <TB1> INFO: ROC 6 VthrComp = 113
[17:07:09.799] <TB1> INFO: ROC 7 VthrComp = 102
[17:07:09.799] <TB1> INFO: ROC 8 VthrComp = 103
[17:07:09.800] <TB1> INFO: ROC 9 VthrComp = 120
[17:07:09.800] <TB1> INFO: ROC 10 VthrComp = 117
[17:07:09.800] <TB1> INFO: ROC 11 VthrComp = 101
[17:07:09.800] <TB1> INFO: ROC 12 VthrComp = 112
[17:07:09.800] <TB1> INFO: ROC 13 VthrComp = 110
[17:07:09.801] <TB1> INFO: ROC 14 VthrComp = 109
[17:07:09.801] <TB1> INFO: ROC 15 VthrComp = 110
[17:07:10.036] <TB1> INFO: Expecting 41600 events.
[17:07:13.498] <TB1> INFO: 41600 events read in total (2871ms).
[17:07:13.498] <TB1> INFO: Test took 3696ms.
[17:07:13.507] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[17:07:13.507] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:07:13.517] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:07:13.517] <TB1> INFO: run 1 of 1
[17:07:13.795] <TB1> INFO: Expecting 5025280 events.
[17:07:40.035] <TB1> INFO: 594208 events read in total (25649ms).
[17:08:05.643] <TB1> INFO: 1187224 events read in total (51257ms).
[17:08:30.953] <TB1> INFO: 1780392 events read in total (76567ms).
[17:08:56.225] <TB1> INFO: 2372664 events read in total (101839ms).
[17:09:21.837] <TB1> INFO: 2962600 events read in total (127451ms).
[17:09:47.225] <TB1> INFO: 3550632 events read in total (152839ms).
[17:10:12.782] <TB1> INFO: 4137184 events read in total (178396ms).
[17:10:38.584] <TB1> INFO: 4723928 events read in total (204198ms).
[17:10:51.565] <TB1> INFO: 5025280 events read in total (217179ms).
[17:10:51.623] <TB1> INFO: Test took 218107ms.
[17:11:16.175] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 65.4692 for pixel 14/10 mean/min/max = 48.0868/30.5488/65.6247
[17:11:16.175] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 62.1219 for pixel 0/79 mean/min/max = 46.2091/30.2765/62.1417
[17:11:16.175] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 64.6055 for pixel 14/8 mean/min/max = 47.1118/29.5273/64.6963
[17:11:16.176] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 70.4269 for pixel 0/12 mean/min/max = 51.9042/33.0996/70.7088
[17:11:16.176] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 65.901 for pixel 22/8 mean/min/max = 49.7925/33.6636/65.9214
[17:11:16.176] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 65.5668 for pixel 21/4 mean/min/max = 49.6805/32.994/66.367
[17:11:16.177] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 65.7778 for pixel 35/2 mean/min/max = 48.3857/30.9477/65.8238
[17:11:16.177] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 71.3812 for pixel 9/12 mean/min/max = 51.536/31.5914/71.4806
[17:11:16.177] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 64.9498 for pixel 6/33 mean/min/max = 48.6209/32.2657/64.9762
[17:11:16.177] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 67.0027 for pixel 28/8 mean/min/max = 49.2134/31.3051/67.1217
[17:11:16.178] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 60.0795 for pixel 5/8 mean/min/max = 45.9368/31.6741/60.1995
[17:11:16.178] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 63.0007 for pixel 1/10 mean/min/max = 47.9938/32.6995/63.288
[17:11:16.178] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 64.9107 for pixel 13/6 mean/min/max = 48.3523/31.5588/65.1457
[17:11:16.179] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 66.8219 for pixel 48/2 mean/min/max = 50.2048/32.918/67.4916
[17:11:16.179] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 65.4324 for pixel 43/15 mean/min/max = 49.6175/33.0163/66.2187
[17:11:16.179] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 63.1801 for pixel 11/10 mean/min/max = 48.3566/33.4214/63.2919
[17:11:16.180] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:11:16.269] <TB1> INFO: Expecting 411648 events.
[17:11:25.590] <TB1> INFO: 411648 events read in total (8730ms).
[17:11:25.598] <TB1> INFO: Expecting 411648 events.
[17:11:34.593] <TB1> INFO: 411648 events read in total (8592ms).
[17:11:34.601] <TB1> INFO: Expecting 411648 events.
[17:11:43.719] <TB1> INFO: 411648 events read in total (8715ms).
[17:11:43.734] <TB1> INFO: Expecting 411648 events.
[17:11:52.734] <TB1> INFO: 411648 events read in total (8596ms).
[17:11:52.747] <TB1> INFO: Expecting 411648 events.
[17:12:01.789] <TB1> INFO: 411648 events read in total (8639ms).
[17:12:01.811] <TB1> INFO: Expecting 411648 events.
[17:12:10.847] <TB1> INFO: 411648 events read in total (8633ms).
[17:12:10.866] <TB1> INFO: Expecting 411648 events.
[17:12:19.983] <TB1> INFO: 411648 events read in total (8715ms).
[17:12:20.012] <TB1> INFO: Expecting 411648 events.
[17:12:29.020] <TB1> INFO: 411648 events read in total (8605ms).
[17:12:29.044] <TB1> INFO: Expecting 411648 events.
[17:12:38.015] <TB1> INFO: 411648 events read in total (8568ms).
[17:12:38.042] <TB1> INFO: Expecting 411648 events.
[17:12:47.078] <TB1> INFO: 411648 events read in total (8633ms).
[17:12:47.108] <TB1> INFO: Expecting 411648 events.
[17:12:56.149] <TB1> INFO: 411648 events read in total (8638ms).
[17:12:56.183] <TB1> INFO: Expecting 411648 events.
[17:13:05.261] <TB1> INFO: 411648 events read in total (8675ms).
[17:13:05.295] <TB1> INFO: Expecting 411648 events.
[17:13:14.291] <TB1> INFO: 411648 events read in total (8593ms).
[17:13:14.342] <TB1> INFO: Expecting 411648 events.
[17:13:23.387] <TB1> INFO: 411648 events read in total (8642ms).
[17:13:23.425] <TB1> INFO: Expecting 411648 events.
[17:13:32.414] <TB1> INFO: 411648 events read in total (8586ms).
[17:13:32.463] <TB1> INFO: Expecting 411648 events.
[17:13:41.563] <TB1> INFO: 411648 events read in total (8697ms).
[17:13:41.611] <TB1> INFO: Test took 145431ms.
[17:13:42.289] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[17:13:42.297] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:13:42.297] <TB1> INFO: run 1 of 1
[17:13:42.529] <TB1> INFO: Expecting 5025280 events.
[17:14:08.337] <TB1> INFO: 591456 events read in total (25217ms).
[17:14:33.460] <TB1> INFO: 1181016 events read in total (50340ms).
[17:14:58.780] <TB1> INFO: 1770352 events read in total (75660ms).
[17:15:23.937] <TB1> INFO: 2360720 events read in total (100817ms).
[17:15:49.372] <TB1> INFO: 2950544 events read in total (126252ms).
[17:16:15.055] <TB1> INFO: 3544248 events read in total (151935ms).
[17:16:40.154] <TB1> INFO: 4135888 events read in total (177034ms).
[17:17:05.698] <TB1> INFO: 4725504 events read in total (202578ms).
[17:17:18.902] <TB1> INFO: 5025280 events read in total (215782ms).
[17:17:18.002] <TB1> INFO: Test took 216705ms.
[17:17:41.562] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 1.218710 .. 146.570590
[17:17:41.807] <TB1> INFO: Expecting 208000 events.
[17:17:51.354] <TB1> INFO: 208000 events read in total (8956ms).
[17:17:51.356] <TB1> INFO: Test took 9792ms.
[17:17:51.407] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 1 .. 156 (-1/-1) hits flags = 528 (plus default)
[17:17:51.418] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:17:51.418] <TB1> INFO: run 1 of 1
[17:17:51.695] <TB1> INFO: Expecting 5191680 events.
[17:18:17.541] <TB1> INFO: 584544 events read in total (25254ms).
[17:18:42.828] <TB1> INFO: 1169688 events read in total (50542ms).
[17:19:08.529] <TB1> INFO: 1754400 events read in total (76242ms).
[17:19:33.640] <TB1> INFO: 2338768 events read in total (101353ms).
[17:19:58.725] <TB1> INFO: 2922600 events read in total (126438ms).
[17:20:24.226] <TB1> INFO: 3506592 events read in total (151939ms).
[17:20:49.815] <TB1> INFO: 4089936 events read in total (177528ms).
[17:21:14.866] <TB1> INFO: 4672456 events read in total (202579ms).
[17:21:37.958] <TB1> INFO: 5191680 events read in total (225671ms).
[17:21:38.035] <TB1> INFO: Test took 226618ms.
[17:22:04.380] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 26.963527 .. 49.184096
[17:22:04.616] <TB1> INFO: Expecting 208000 events.
[17:22:14.383] <TB1> INFO: 208000 events read in total (9175ms).
[17:22:14.383] <TB1> INFO: Test took 10003ms.
[17:22:14.430] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 59 (-1/-1) hits flags = 528 (plus default)
[17:22:14.438] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:22:14.438] <TB1> INFO: run 1 of 1
[17:22:14.717] <TB1> INFO: Expecting 1464320 events.
[17:22:42.055] <TB1> INFO: 649072 events read in total (26746ms).
[17:23:09.157] <TB1> INFO: 1296728 events read in total (53848ms).
[17:23:16.575] <TB1> INFO: 1464320 events read in total (61266ms).
[17:23:16.605] <TB1> INFO: Test took 62168ms.
[17:23:31.311] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 26.509796 .. 48.968394
[17:23:31.549] <TB1> INFO: Expecting 208000 events.
[17:23:41.370] <TB1> INFO: 208000 events read in total (9229ms).
[17:23:41.370] <TB1> INFO: Test took 10058ms.
[17:23:41.418] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 58 (-1/-1) hits flags = 528 (plus default)
[17:23:41.427] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:23:41.427] <TB1> INFO: run 1 of 1
[17:23:41.705] <TB1> INFO: Expecting 1431040 events.
[17:24:09.198] <TB1> INFO: 652912 events read in total (26901ms).
[17:24:36.379] <TB1> INFO: 1304712 events read in total (54082ms).
[17:24:42.084] <TB1> INFO: 1431040 events read in total (59787ms).
[17:24:42.110] <TB1> INFO: Test took 60683ms.
[17:24:55.282] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 24.394802 .. 46.449643
[17:24:55.515] <TB1> INFO: Expecting 208000 events.
[17:25:05.289] <TB1> INFO: 208000 events read in total (9183ms).
[17:25:05.290] <TB1> INFO: Test took 10007ms.
[17:25:05.357] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 56 (-1/-1) hits flags = 528 (plus default)
[17:25:05.368] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:25:05.368] <TB1> INFO: run 1 of 1
[17:25:05.646] <TB1> INFO: Expecting 1431040 events.
[17:25:33.948] <TB1> INFO: 667216 events read in total (27710ms).
[17:26:01.199] <TB1> INFO: 1334336 events read in total (54961ms).
[17:26:05.641] <TB1> INFO: 1431040 events read in total (59403ms).
[17:26:05.671] <TB1> INFO: Test took 60304ms.
[17:26:19.424] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[17:26:19.424] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[17:26:19.432] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:26:19.432] <TB1> INFO: run 1 of 1
[17:26:19.664] <TB1> INFO: Expecting 1364480 events.
[17:26:48.087] <TB1> INFO: 668008 events read in total (27831ms).
[17:27:15.244] <TB1> INFO: 1335408 events read in total (54988ms).
[17:27:16.926] <TB1> INFO: 1364480 events read in total (56671ms).
[17:27:16.952] <TB1> INFO: Test took 57520ms.
[17:27:30.710] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C0.dat
[17:27:30.710] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C1.dat
[17:27:30.710] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C2.dat
[17:27:30.710] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C3.dat
[17:27:30.710] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C4.dat
[17:27:30.710] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C5.dat
[17:27:30.710] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C6.dat
[17:27:30.710] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C7.dat
[17:27:30.710] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C8.dat
[17:27:30.711] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C9.dat
[17:27:30.711] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C10.dat
[17:27:30.711] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C11.dat
[17:27:30.711] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C12.dat
[17:27:30.711] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C13.dat
[17:27:30.711] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C14.dat
[17:27:30.711] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C15.dat
[17:27:30.711] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C0.dat
[17:27:30.717] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C1.dat
[17:27:30.723] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C2.dat
[17:27:30.729] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C3.dat
[17:27:30.734] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C4.dat
[17:27:30.740] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C5.dat
[17:27:30.747] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C6.dat
[17:27:30.753] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C7.dat
[17:27:30.759] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C8.dat
[17:27:30.765] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C9.dat
[17:27:30.771] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C10.dat
[17:27:30.777] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C11.dat
[17:27:30.783] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C12.dat
[17:27:30.789] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C13.dat
[17:27:30.797] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C14.dat
[17:27:30.805] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters35_C15.dat
[17:27:30.811] <TB1> INFO: PixTestTrim::trimTest() done
[17:27:30.811] <TB1> INFO: vtrim: 141 125 154 144 156 140 160 157 132 165 126 127 129 142 147 129
[17:27:30.811] <TB1> INFO: vthrcomp: 116 124 119 106 108 105 113 102 103 120 117 101 112 110 109 110
[17:27:30.811] <TB1> INFO: vcal mean: 35.01 34.94 35.09 35.15 34.99 35.06 35.03 35.39 35.00 35.52 34.97 34.99 35.05 35.23 35.28 34.98
[17:27:30.811] <TB1> INFO: vcal RMS: 1.12 1.16 1.41 1.35 1.11 1.20 1.35 1.68 1.15 1.76 1.00 1.04 1.26 1.33 1.50 1.07
[17:27:30.811] <TB1> INFO: bits mean: 9.71 9.47 10.28 8.71 9.43 9.08 10.09 9.49 9.30 9.76 9.56 9.39 9.74 8.98 9.66 8.92
[17:27:30.811] <TB1> INFO: bits RMS: 2.63 2.87 2.51 2.63 2.27 2.54 2.43 2.56 2.55 2.65 2.68 2.52 2.54 2.64 2.31 2.57
[17:27:30.818] <TB1> INFO: ----------------------------------------------------------------------
[17:27:30.818] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[17:27:30.818] <TB1> INFO: ----------------------------------------------------------------------
[17:27:30.821] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[17:27:30.832] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[17:27:30.832] <TB1> INFO: run 1 of 1
[17:27:31.107] <TB1> INFO: Expecting 4160000 events.
[17:28:03.101] <TB1> INFO: 741970 events read in total (31402ms).
[17:28:34.328] <TB1> INFO: 1479035 events read in total (62629ms).
[17:29:05.324] <TB1> INFO: 2212055 events read in total (93625ms).
[17:29:36.253] <TB1> INFO: 2938745 events read in total (124554ms).
[17:30:07.247] <TB1> INFO: 3662235 events read in total (155548ms).
[17:30:28.336] <TB1> INFO: 4160000 events read in total (176637ms).
[17:30:28.390] <TB1> INFO: Test took 177558ms.
[17:30:57.047] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[17:30:57.056] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[17:30:57.056] <TB1> INFO: run 1 of 1
[17:30:57.295] <TB1> INFO: Expecting 4326400 events.
[17:31:28.400] <TB1> INFO: 706855 events read in total (30513ms).
[17:31:58.693] <TB1> INFO: 1409885 events read in total (60806ms).
[17:32:29.019] <TB1> INFO: 2109930 events read in total (91132ms).
[17:32:59.363] <TB1> INFO: 2805080 events read in total (121476ms).
[17:33:29.497] <TB1> INFO: 3497085 events read in total (151610ms).
[17:33:59.731] <TB1> INFO: 4189855 events read in total (181844ms).
[17:34:05.913] <TB1> INFO: 4326400 events read in total (188026ms).
[17:34:05.979] <TB1> INFO: Test took 188923ms.
[17:34:36.361] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 195 (-1/-1) hits flags = 528 (plus default)
[17:34:36.373] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[17:34:36.373] <TB1> INFO: run 1 of 1
[17:34:36.694] <TB1> INFO: Expecting 4076800 events.
[17:35:08.066] <TB1> INFO: 721670 events read in total (30781ms).
[17:35:38.645] <TB1> INFO: 1438750 events read in total (61360ms).
[17:36:08.997] <TB1> INFO: 2152270 events read in total (91712ms).
[17:36:39.324] <TB1> INFO: 2859840 events read in total (122039ms).
[17:37:09.651] <TB1> INFO: 3564755 events read in total (152366ms).
[17:37:31.595] <TB1> INFO: 4076800 events read in total (174310ms).
[17:37:31.655] <TB1> INFO: Test took 175282ms.
[17:38:00.058] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 193 (-1/-1) hits flags = 528 (plus default)
[17:38:00.066] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[17:38:00.066] <TB1> INFO: run 1 of 1
[17:38:00.300] <TB1> INFO: Expecting 4035200 events.
[17:38:31.478] <TB1> INFO: 724490 events read in total (30587ms).
[17:39:02.322] <TB1> INFO: 1444515 events read in total (61431ms).
[17:39:32.785] <TB1> INFO: 2160600 events read in total (91894ms).
[17:40:03.330] <TB1> INFO: 2870610 events read in total (122439ms).
[17:40:33.944] <TB1> INFO: 3578170 events read in total (153053ms).
[17:40:53.560] <TB1> INFO: 4035200 events read in total (172669ms).
[17:40:53.633] <TB1> INFO: Test took 173568ms.
[17:41:22.372] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 194 (-1/-1) hits flags = 528 (plus default)
[17:41:22.383] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[17:41:22.383] <TB1> INFO: run 1 of 1
[17:41:22.652] <TB1> INFO: Expecting 4056000 events.
[17:41:53.855] <TB1> INFO: 723190 events read in total (30611ms).
[17:42:24.517] <TB1> INFO: 1441820 events read in total (61273ms).
[17:42:54.862] <TB1> INFO: 2156665 events read in total (91618ms).
[17:43:25.382] <TB1> INFO: 2865485 events read in total (122138ms).
[17:43:56.263] <TB1> INFO: 3571655 events read in total (153019ms).
[17:44:16.715] <TB1> INFO: 4056000 events read in total (173471ms).
[17:44:16.783] <TB1> INFO: Test took 174400ms.
[17:44:45.501] <TB1> INFO: PixTestTrim::trimBitTest() done
[17:44:45.502] <TB1> INFO: PixTestTrim::doTest() done, duration: 2459 seconds
[17:44:45.502] <TB1> INFO: Decoding statistics:
[17:44:45.502] <TB1> INFO: General information:
[17:44:45.502] <TB1> INFO: 16bit words read: 0
[17:44:45.502] <TB1> INFO: valid events total: 0
[17:44:45.502] <TB1> INFO: empty events: 0
[17:44:45.502] <TB1> INFO: valid events with pixels: 0
[17:44:45.503] <TB1> INFO: valid pixel hits: 0
[17:44:45.503] <TB1> INFO: Event errors: 0
[17:44:45.503] <TB1> INFO: start marker: 0
[17:44:45.503] <TB1> INFO: stop marker: 0
[17:44:45.503] <TB1> INFO: overflow: 0
[17:44:45.503] <TB1> INFO: invalid 5bit words: 0
[17:44:45.503] <TB1> INFO: invalid XOR eye diagram: 0
[17:44:45.503] <TB1> INFO: frame (failed synchr.): 0
[17:44:45.503] <TB1> INFO: idle data (no TBM trl): 0
[17:44:45.503] <TB1> INFO: no data (only TBM hdr): 0
[17:44:45.503] <TB1> INFO: TBM errors: 0
[17:44:45.503] <TB1> INFO: flawed TBM headers: 0
[17:44:45.503] <TB1> INFO: flawed TBM trailers: 0
[17:44:45.503] <TB1> INFO: event ID mismatches: 0
[17:44:45.503] <TB1> INFO: ROC errors: 0
[17:44:45.503] <TB1> INFO: missing ROC header(s): 0
[17:44:45.503] <TB1> INFO: misplaced readback start: 0
[17:44:45.503] <TB1> INFO: Pixel decoding errors: 0
[17:44:45.503] <TB1> INFO: pixel data incomplete: 0
[17:44:45.503] <TB1> INFO: pixel address: 0
[17:44:45.503] <TB1> INFO: pulse height fill bit: 0
[17:44:45.503] <TB1> INFO: buffer corruption: 0
[17:44:46.225] <TB1> INFO: ######################################################################
[17:44:46.225] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[17:44:46.225] <TB1> INFO: ######################################################################
[17:44:46.486] <TB1> INFO: Expecting 41600 events.
[17:44:50.092] <TB1> INFO: 41600 events read in total (3014ms).
[17:44:50.093] <TB1> INFO: Test took 3867ms.
[17:44:50.538] <TB1> INFO: Expecting 41600 events.
[17:44:54.021] <TB1> INFO: 41600 events read in total (2892ms).
[17:44:54.022] <TB1> INFO: Test took 3726ms.
[17:44:54.310] <TB1> INFO: Expecting 41600 events.
[17:44:57.914] <TB1> INFO: 41600 events read in total (3013ms).
[17:44:57.915] <TB1> INFO: Test took 3870ms.
[17:44:58.203] <TB1> INFO: Expecting 41600 events.
[17:45:01.743] <TB1> INFO: 41600 events read in total (2948ms).
[17:45:01.744] <TB1> INFO: Test took 3805ms.
[17:45:02.032] <TB1> INFO: Expecting 41600 events.
[17:45:05.552] <TB1> INFO: 41600 events read in total (2928ms).
[17:45:05.553] <TB1> INFO: Test took 3786ms.
[17:45:05.841] <TB1> INFO: Expecting 41600 events.
[17:45:09.371] <TB1> INFO: 41600 events read in total (2939ms).
[17:45:09.372] <TB1> INFO: Test took 3796ms.
[17:45:09.660] <TB1> INFO: Expecting 41600 events.
[17:45:13.132] <TB1> INFO: 41600 events read in total (2880ms).
[17:45:13.133] <TB1> INFO: Test took 3737ms.
[17:45:13.430] <TB1> INFO: Expecting 41600 events.
[17:45:16.979] <TB1> INFO: 41600 events read in total (2958ms).
[17:45:16.980] <TB1> INFO: Test took 3824ms.
[17:45:17.271] <TB1> INFO: Expecting 41600 events.
[17:45:20.810] <TB1> INFO: 41600 events read in total (2948ms).
[17:45:20.811] <TB1> INFO: Test took 3805ms.
[17:45:21.099] <TB1> INFO: Expecting 41600 events.
[17:45:24.784] <TB1> INFO: 41600 events read in total (3094ms).
[17:45:24.785] <TB1> INFO: Test took 3951ms.
[17:45:25.073] <TB1> INFO: Expecting 41600 events.
[17:45:28.551] <TB1> INFO: 41600 events read in total (2887ms).
[17:45:28.551] <TB1> INFO: Test took 3743ms.
[17:45:28.839] <TB1> INFO: Expecting 41600 events.
[17:45:32.317] <TB1> INFO: 41600 events read in total (2886ms).
[17:45:32.318] <TB1> INFO: Test took 3743ms.
[17:45:32.615] <TB1> INFO: Expecting 41600 events.
[17:45:36.081] <TB1> INFO: 41600 events read in total (2875ms).
[17:45:36.082] <TB1> INFO: Test took 3741ms.
[17:45:36.370] <TB1> INFO: Expecting 41600 events.
[17:45:39.865] <TB1> INFO: 41600 events read in total (2904ms).
[17:45:39.866] <TB1> INFO: Test took 3761ms.
[17:45:40.154] <TB1> INFO: Expecting 41600 events.
[17:45:43.623] <TB1> INFO: 41600 events read in total (2878ms).
[17:45:43.624] <TB1> INFO: Test took 3735ms.
[17:45:43.924] <TB1> INFO: Expecting 41600 events.
[17:45:47.493] <TB1> INFO: 41600 events read in total (2977ms).
[17:45:47.494] <TB1> INFO: Test took 3843ms.
[17:45:47.791] <TB1> INFO: Expecting 41600 events.
[17:45:51.343] <TB1> INFO: 41600 events read in total (2960ms).
[17:45:51.344] <TB1> INFO: Test took 3827ms.
[17:45:51.635] <TB1> INFO: Expecting 41600 events.
[17:45:55.121] <TB1> INFO: 41600 events read in total (2895ms).
[17:45:55.122] <TB1> INFO: Test took 3752ms.
[17:45:55.410] <TB1> INFO: Expecting 41600 events.
[17:45:58.924] <TB1> INFO: 41600 events read in total (2923ms).
[17:45:58.925] <TB1> INFO: Test took 3780ms.
[17:45:59.213] <TB1> INFO: Expecting 41600 events.
[17:46:02.753] <TB1> INFO: 41600 events read in total (2949ms).
[17:46:02.754] <TB1> INFO: Test took 3806ms.
[17:46:03.042] <TB1> INFO: Expecting 41600 events.
[17:46:06.579] <TB1> INFO: 41600 events read in total (2946ms).
[17:46:06.580] <TB1> INFO: Test took 3803ms.
[17:46:06.868] <TB1> INFO: Expecting 41600 events.
[17:46:10.316] <TB1> INFO: 41600 events read in total (2857ms).
[17:46:10.317] <TB1> INFO: Test took 3714ms.
[17:46:10.605] <TB1> INFO: Expecting 41600 events.
[17:46:14.148] <TB1> INFO: 41600 events read in total (2952ms).
[17:46:14.149] <TB1> INFO: Test took 3809ms.
[17:46:14.439] <TB1> INFO: Expecting 41600 events.
[17:46:17.966] <TB1> INFO: 41600 events read in total (2935ms).
[17:46:17.966] <TB1> INFO: Test took 3791ms.
[17:46:18.262] <TB1> INFO: Expecting 41600 events.
[17:46:21.815] <TB1> INFO: 41600 events read in total (2962ms).
[17:46:21.816] <TB1> INFO: Test took 3826ms.
[17:46:22.104] <TB1> INFO: Expecting 41600 events.
[17:46:25.748] <TB1> INFO: 41600 events read in total (3052ms).
[17:46:25.748] <TB1> INFO: Test took 3908ms.
[17:46:26.039] <TB1> INFO: Expecting 41600 events.
[17:46:29.493] <TB1> INFO: 41600 events read in total (2863ms).
[17:46:29.493] <TB1> INFO: Test took 3719ms.
[17:46:29.782] <TB1> INFO: Expecting 41600 events.
[17:46:33.228] <TB1> INFO: 41600 events read in total (2855ms).
[17:46:33.229] <TB1> INFO: Test took 3712ms.
[17:46:33.527] <TB1> INFO: Expecting 41600 events.
[17:46:36.995] <TB1> INFO: 41600 events read in total (2877ms).
[17:46:36.995] <TB1> INFO: Test took 3741ms.
[17:46:37.284] <TB1> INFO: Expecting 41600 events.
[17:46:40.773] <TB1> INFO: 41600 events read in total (2898ms).
[17:46:40.774] <TB1> INFO: Test took 3755ms.
[17:46:41.065] <TB1> INFO: Expecting 41600 events.
[17:46:44.637] <TB1> INFO: 41600 events read in total (2981ms).
[17:46:44.637] <TB1> INFO: Test took 3837ms.
[17:46:44.925] <TB1> INFO: Expecting 41600 events.
[17:46:48.571] <TB1> INFO: 41600 events read in total (3054ms).
[17:46:48.572] <TB1> INFO: Test took 3911ms.
[17:46:48.860] <TB1> INFO: Expecting 41600 events.
[17:46:52.327] <TB1> INFO: 41600 events read in total (2875ms).
[17:46:52.328] <TB1> INFO: Test took 3732ms.
[17:46:52.624] <TB1> INFO: Expecting 41600 events.
[17:46:56.102] <TB1> INFO: 41600 events read in total (2887ms).
[17:46:56.103] <TB1> INFO: Test took 3752ms.
[17:46:56.391] <TB1> INFO: Expecting 41600 events.
[17:46:59.852] <TB1> INFO: 41600 events read in total (2870ms).
[17:46:59.853] <TB1> INFO: Test took 3727ms.
[17:47:00.141] <TB1> INFO: Expecting 41600 events.
[17:47:03.699] <TB1> INFO: 41600 events read in total (2967ms).
[17:47:03.699] <TB1> INFO: Test took 3823ms.
[17:47:03.987] <TB1> INFO: Expecting 41600 events.
[17:47:07.465] <TB1> INFO: 41600 events read in total (2886ms).
[17:47:07.466] <TB1> INFO: Test took 3743ms.
[17:47:07.754] <TB1> INFO: Expecting 41600 events.
[17:47:11.308] <TB1> INFO: 41600 events read in total (2962ms).
[17:47:11.309] <TB1> INFO: Test took 3820ms.
[17:47:11.600] <TB1> INFO: Expecting 41600 events.
[17:47:15.091] <TB1> INFO: 41600 events read in total (2899ms).
[17:47:15.091] <TB1> INFO: Test took 3756ms.
[17:47:15.379] <TB1> INFO: Expecting 41600 events.
[17:47:18.992] <TB1> INFO: 41600 events read in total (3021ms).
[17:47:18.992] <TB1> INFO: Test took 3877ms.
[17:47:19.284] <TB1> INFO: Expecting 41600 events.
[17:47:22.775] <TB1> INFO: 41600 events read in total (2899ms).
[17:47:22.776] <TB1> INFO: Test took 3757ms.
[17:47:23.064] <TB1> INFO: Expecting 41600 events.
[17:47:26.637] <TB1> INFO: 41600 events read in total (2981ms).
[17:47:26.637] <TB1> INFO: Test took 3838ms.
[17:47:26.928] <TB1> INFO: Expecting 41600 events.
[17:47:30.502] <TB1> INFO: 41600 events read in total (2982ms).
[17:47:30.503] <TB1> INFO: Test took 3839ms.
[17:47:30.792] <TB1> INFO: Expecting 41600 events.
[17:47:34.398] <TB1> INFO: 41600 events read in total (3015ms).
[17:47:34.399] <TB1> INFO: Test took 3872ms.
[17:47:34.687] <TB1> INFO: Expecting 41600 events.
[17:47:38.236] <TB1> INFO: 41600 events read in total (2957ms).
[17:47:38.237] <TB1> INFO: Test took 3814ms.
[17:47:38.525] <TB1> INFO: Expecting 41600 events.
[17:47:41.976] <TB1> INFO: 41600 events read in total (2859ms).
[17:47:41.977] <TB1> INFO: Test took 3716ms.
[17:47:42.265] <TB1> INFO: Expecting 41600 events.
[17:47:45.717] <TB1> INFO: 41600 events read in total (2860ms).
[17:47:45.718] <TB1> INFO: Test took 3718ms.
[17:47:46.017] <TB1> INFO: Expecting 41600 events.
[17:47:49.462] <TB1> INFO: 41600 events read in total (2853ms).
[17:47:49.463] <TB1> INFO: Test took 3721ms.
[17:47:49.784] <TB1> INFO: Expecting 41600 events.
[17:47:53.330] <TB1> INFO: 41600 events read in total (2954ms).
[17:47:53.331] <TB1> INFO: Test took 3844ms.
[17:47:53.619] <TB1> INFO: Expecting 41600 events.
[17:47:57.165] <TB1> INFO: 41600 events read in total (2955ms).
[17:47:57.166] <TB1> INFO: Test took 3812ms.
[17:47:57.454] <TB1> INFO: Expecting 41600 events.
[17:48:00.903] <TB1> INFO: 41600 events read in total (2857ms).
[17:48:00.904] <TB1> INFO: Test took 3714ms.
[17:48:01.192] <TB1> INFO: Expecting 41600 events.
[17:48:04.715] <TB1> INFO: 41600 events read in total (2931ms).
[17:48:04.716] <TB1> INFO: Test took 3789ms.
[17:48:05.008] <TB1> INFO: Expecting 41600 events.
[17:48:08.620] <TB1> INFO: 41600 events read in total (3020ms).
[17:48:08.621] <TB1> INFO: Test took 3878ms.
[17:48:08.911] <TB1> INFO: Expecting 41600 events.
[17:48:12.392] <TB1> INFO: 41600 events read in total (2889ms).
[17:48:12.393] <TB1> INFO: Test took 3747ms.
[17:48:12.681] <TB1> INFO: Expecting 2560 events.
[17:48:13.566] <TB1> INFO: 2560 events read in total (293ms).
[17:48:13.566] <TB1> INFO: Test took 1161ms.
[17:48:13.874] <TB1> INFO: Expecting 2560 events.
[17:48:14.756] <TB1> INFO: 2560 events read in total (290ms).
[17:48:14.757] <TB1> INFO: Test took 1190ms.
[17:48:15.065] <TB1> INFO: Expecting 2560 events.
[17:48:15.948] <TB1> INFO: 2560 events read in total (292ms).
[17:48:15.948] <TB1> INFO: Test took 1191ms.
[17:48:16.256] <TB1> INFO: Expecting 2560 events.
[17:48:17.147] <TB1> INFO: 2560 events read in total (290ms).
[17:48:17.148] <TB1> INFO: Test took 1200ms.
[17:48:17.456] <TB1> INFO: Expecting 2560 events.
[17:48:18.333] <TB1> INFO: 2560 events read in total (285ms).
[17:48:18.333] <TB1> INFO: Test took 1185ms.
[17:48:18.641] <TB1> INFO: Expecting 2560 events.
[17:48:19.519] <TB1> INFO: 2560 events read in total (286ms).
[17:48:19.520] <TB1> INFO: Test took 1186ms.
[17:48:19.828] <TB1> INFO: Expecting 2560 events.
[17:48:20.708] <TB1> INFO: 2560 events read in total (289ms).
[17:48:20.708] <TB1> INFO: Test took 1188ms.
[17:48:21.016] <TB1> INFO: Expecting 2560 events.
[17:48:21.897] <TB1> INFO: 2560 events read in total (290ms).
[17:48:21.897] <TB1> INFO: Test took 1189ms.
[17:48:22.205] <TB1> INFO: Expecting 2560 events.
[17:48:23.084] <TB1> INFO: 2560 events read in total (287ms).
[17:48:23.084] <TB1> INFO: Test took 1186ms.
[17:48:23.392] <TB1> INFO: Expecting 2560 events.
[17:48:24.273] <TB1> INFO: 2560 events read in total (290ms).
[17:48:24.273] <TB1> INFO: Test took 1188ms.
[17:48:24.582] <TB1> INFO: Expecting 2560 events.
[17:48:25.461] <TB1> INFO: 2560 events read in total (288ms).
[17:48:25.461] <TB1> INFO: Test took 1187ms.
[17:48:25.769] <TB1> INFO: Expecting 2560 events.
[17:48:26.647] <TB1> INFO: 2560 events read in total (286ms).
[17:48:26.647] <TB1> INFO: Test took 1185ms.
[17:48:26.955] <TB1> INFO: Expecting 2560 events.
[17:48:27.840] <TB1> INFO: 2560 events read in total (293ms).
[17:48:27.841] <TB1> INFO: Test took 1193ms.
[17:48:28.149] <TB1> INFO: Expecting 2560 events.
[17:48:29.034] <TB1> INFO: 2560 events read in total (294ms).
[17:48:29.034] <TB1> INFO: Test took 1193ms.
[17:48:29.342] <TB1> INFO: Expecting 2560 events.
[17:48:30.224] <TB1> INFO: 2560 events read in total (290ms).
[17:48:30.224] <TB1> INFO: Test took 1189ms.
[17:48:30.532] <TB1> INFO: Expecting 2560 events.
[17:48:31.414] <TB1> INFO: 2560 events read in total (290ms).
[17:48:31.414] <TB1> INFO: Test took 1189ms.
[17:48:31.417] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:48:31.723] <TB1> INFO: Expecting 655360 events.
[17:48:45.953] <TB1> INFO: 655360 events read in total (13638ms).
[17:48:45.965] <TB1> INFO: Expecting 655360 events.
[17:48:59.869] <TB1> INFO: 655360 events read in total (13501ms).
[17:48:59.884] <TB1> INFO: Expecting 655360 events.
[17:49:13.927] <TB1> INFO: 655360 events read in total (13640ms).
[17:49:13.946] <TB1> INFO: Expecting 655360 events.
[17:49:27.892] <TB1> INFO: 655360 events read in total (13543ms).
[17:49:27.923] <TB1> INFO: Expecting 655360 events.
[17:49:41.969] <TB1> INFO: 655360 events read in total (13643ms).
[17:49:41.006] <TB1> INFO: Expecting 655360 events.
[17:49:56.070] <TB1> INFO: 655360 events read in total (13661ms).
[17:49:56.116] <TB1> INFO: Expecting 655360 events.
[17:50:10.105] <TB1> INFO: 655360 events read in total (13586ms).
[17:50:10.140] <TB1> INFO: Expecting 655360 events.
[17:50:24.105] <TB1> INFO: 655360 events read in total (13561ms).
[17:50:24.147] <TB1> INFO: Expecting 655360 events.
[17:50:38.113] <TB1> INFO: 655360 events read in total (13563ms).
[17:50:38.175] <TB1> INFO: Expecting 655360 events.
[17:50:51.837] <TB1> INFO: 655360 events read in total (13259ms).
[17:50:51.885] <TB1> INFO: Expecting 655360 events.
[17:51:05.849] <TB1> INFO: 655360 events read in total (13561ms).
[17:51:05.910] <TB1> INFO: Expecting 655360 events.
[17:51:19.890] <TB1> INFO: 655360 events read in total (13577ms).
[17:51:19.967] <TB1> INFO: Expecting 655360 events.
[17:51:34.075] <TB1> INFO: 655360 events read in total (13705ms).
[17:51:34.143] <TB1> INFO: Expecting 655360 events.
[17:51:48.220] <TB1> INFO: 655360 events read in total (13674ms).
[17:51:48.287] <TB1> INFO: Expecting 655360 events.
[17:52:02.296] <TB1> INFO: 655360 events read in total (13606ms).
[17:52:02.390] <TB1> INFO: Expecting 655360 events.
[17:52:16.464] <TB1> INFO: 655360 events read in total (13671ms).
[17:52:16.536] <TB1> INFO: Test took 225119ms.
[17:52:16.614] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:52:16.879] <TB1> INFO: Expecting 655360 events.
[17:52:30.826] <TB1> INFO: 655360 events read in total (13355ms).
[17:52:30.837] <TB1> INFO: Expecting 655360 events.
[17:52:44.691] <TB1> INFO: 655360 events read in total (13451ms).
[17:52:44.706] <TB1> INFO: Expecting 655360 events.
[17:52:58.585] <TB1> INFO: 655360 events read in total (13476ms).
[17:52:58.604] <TB1> INFO: Expecting 655360 events.
[17:53:12.370] <TB1> INFO: 655360 events read in total (13363ms).
[17:53:12.400] <TB1> INFO: Expecting 655360 events.
[17:53:26.390] <TB1> INFO: 655360 events read in total (13587ms).
[17:53:26.424] <TB1> INFO: Expecting 655360 events.
[17:53:40.295] <TB1> INFO: 655360 events read in total (13468ms).
[17:53:40.327] <TB1> INFO: Expecting 655360 events.
[17:53:54.253] <TB1> INFO: 655360 events read in total (13523ms).
[17:53:54.288] <TB1> INFO: Expecting 655360 events.
[17:54:08.128] <TB1> INFO: 655360 events read in total (13437ms).
[17:54:08.169] <TB1> INFO: Expecting 655360 events.
[17:54:21.821] <TB1> INFO: 655360 events read in total (13249ms).
[17:54:21.866] <TB1> INFO: Expecting 655360 events.
[17:54:35.684] <TB1> INFO: 655360 events read in total (13415ms).
[17:54:35.733] <TB1> INFO: Expecting 655360 events.
[17:54:49.744] <TB1> INFO: 655360 events read in total (13608ms).
[17:54:49.815] <TB1> INFO: Expecting 655360 events.
[17:55:03.859] <TB1> INFO: 655360 events read in total (13641ms).
[17:55:03.916] <TB1> INFO: Expecting 655360 events.
[17:55:18.092] <TB1> INFO: 655360 events read in total (13773ms).
[17:55:18.176] <TB1> INFO: Expecting 655360 events.
[17:55:32.260] <TB1> INFO: 655360 events read in total (13681ms).
[17:55:32.326] <TB1> INFO: Expecting 655360 events.
[17:55:46.194] <TB1> INFO: 655360 events read in total (13465ms).
[17:55:46.273] <TB1> INFO: Expecting 655360 events.
[17:56:00.259] <TB1> INFO: 655360 events read in total (13583ms).
[17:56:00.333] <TB1> INFO: Test took 223719ms.
[17:56:00.494] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:56:00.498] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[17:56:00.503] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:56:00.508] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:56:00.512] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[17:56:00.517] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:56:00.521] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:56:00.526] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:56:00.530] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[17:56:00.535] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[17:56:00.540] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[17:56:00.544] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[17:56:00.549] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[17:56:00.553] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[17:56:00.558] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[17:56:00.562] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[17:56:00.567] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[17:56:00.572] <TB1> INFO: safety margin for low PH: adding 10, margin is now 30
[17:56:00.577] <TB1> INFO: safety margin for low PH: adding 11, margin is now 31
[17:56:00.581] <TB1> INFO: safety margin for low PH: adding 12, margin is now 32
[17:56:00.586] <TB1> INFO: safety margin for low PH: adding 13, margin is now 33
[17:56:00.590] <TB1> INFO: safety margin for low PH: adding 14, margin is now 34
[17:56:00.595] <TB1> INFO: safety margin for low PH: adding 15, margin is now 35
[17:56:00.600] <TB1> INFO: safety margin for low PH: adding 16, margin is now 36
[17:56:00.604] <TB1> INFO: safety margin for low PH: adding 17, margin is now 37
[17:56:00.609] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:56:00.614] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:56:00.618] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[17:56:00.623] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[17:56:00.627] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[17:56:00.632] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:56:00.637] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[17:56:00.642] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:56:00.646] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[17:56:00.651] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[17:56:00.655] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[17:56:00.660] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[17:56:00.665] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[17:56:00.669] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[17:56:00.674] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[17:56:00.679] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[17:56:00.683] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[17:56:00.688] <TB1> INFO: safety margin for low PH: adding 10, margin is now 30
[17:56:00.692] <TB1> INFO: safety margin for low PH: adding 11, margin is now 31
[17:56:00.697] <TB1> INFO: safety margin for low PH: adding 12, margin is now 32
[17:56:00.701] <TB1> INFO: safety margin for low PH: adding 13, margin is now 33
[17:56:00.706] <TB1> INFO: safety margin for low PH: adding 14, margin is now 34
[17:56:00.711] <TB1> INFO: safety margin for low PH: adding 15, margin is now 35
[17:56:00.716] <TB1> INFO: safety margin for low PH: adding 16, margin is now 36
[17:56:00.720] <TB1> INFO: safety margin for low PH: adding 17, margin is now 37
[17:56:00.725] <TB1> INFO: safety margin for low PH: adding 18, margin is now 38
[17:56:00.729] <TB1> INFO: safety margin for low PH: adding 19, margin is now 39
[17:56:00.734] <TB1> INFO: safety margin for low PH: adding 20, margin is now 40
[17:56:00.739] <TB1> INFO: safety margin for low PH: adding 21, margin is now 41
[17:56:00.744] <TB1> INFO: safety margin for low PH: adding 22, margin is now 42
[17:56:00.748] <TB1> INFO: safety margin for low PH: adding 23, margin is now 43
[17:56:00.753] <TB1> INFO: safety margin for low PH: adding 24, margin is now 44
[17:56:00.759] <TB1> INFO: safety margin for low PH: adding 25, margin is now 45
[17:56:00.765] <TB1> INFO: safety margin for low PH: adding 26, margin is now 46
[17:56:00.772] <TB1> INFO: safety margin for low PH: adding 27, margin is now 47
[17:56:00.778] <TB1> INFO: safety margin for low PH: adding 28, margin is now 48
[17:56:00.784] <TB1> INFO: safety margin for low PH: adding 29, margin is now 49
[17:56:00.791] <TB1> INFO: safety margin for low PH: adding 30, margin is now 50
[17:56:00.798] <TB1> INFO: safety margin for low PH: adding 31, margin is now 51
[17:56:00.804] <TB1> INFO: safety margin for low PH: adding 32, margin is now 52
[17:56:00.811] <TB1> INFO: safety margin for low PH: adding 33, margin is now 53
[17:56:00.817] <TB1> INFO: safety margin for low PH: adding 34, margin is now 54
[17:56:00.824] <TB1> INFO: safety margin for low PH: adding 35, margin is now 55
[17:56:00.830] <TB1> INFO: safety margin for low PH: adding 36, margin is now 56
[17:56:00.837] <TB1> INFO: safety margin for low PH: adding 37, margin is now 57
[17:56:00.843] <TB1> INFO: safety margin for low PH: adding 38, margin is now 58
[17:56:00.850] <TB1> INFO: safety margin for low PH: adding 39, margin is now 59
[17:56:00.857] <TB1> INFO: safety margin for low PH: adding 40, margin is now 60
[17:56:00.863] <TB1> INFO: safety margin for low PH: adding 41, margin is now 61
[17:56:00.870] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:56:00.876] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[17:56:00.882] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:56:00.889] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:56:00.895] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[17:56:00.901] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[17:56:00.908] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[17:56:00.914] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[17:56:00.921] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[17:56:00.927] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[17:56:00.933] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[17:56:00.939] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[17:56:00.946] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:56:00.952] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:56:00.959] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[17:56:00.965] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[17:56:00.971] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[17:56:00.978] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[17:56:00.984] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[17:56:00.990] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[17:56:00.997] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[17:56:00.003] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[17:56:01.010] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[17:56:01.016] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:56:01.052] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C0.dat
[17:56:01.052] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C1.dat
[17:56:01.052] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C2.dat
[17:56:01.052] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C3.dat
[17:56:01.052] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C4.dat
[17:56:01.052] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C5.dat
[17:56:01.052] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C6.dat
[17:56:01.052] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C7.dat
[17:56:01.053] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C8.dat
[17:56:01.053] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C9.dat
[17:56:01.053] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C10.dat
[17:56:01.053] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C11.dat
[17:56:01.053] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C12.dat
[17:56:01.053] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C13.dat
[17:56:01.053] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C14.dat
[17:56:01.053] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters35_C15.dat
[17:56:01.287] <TB1> INFO: Expecting 41600 events.
[17:56:04.362] <TB1> INFO: 41600 events read in total (2483ms).
[17:56:04.363] <TB1> INFO: Test took 3307ms.
[17:56:04.811] <TB1> INFO: Expecting 41600 events.
[17:56:07.814] <TB1> INFO: 41600 events read in total (2412ms).
[17:56:07.814] <TB1> INFO: Test took 3238ms.
[17:56:08.260] <TB1> INFO: Expecting 41600 events.
[17:56:11.397] <TB1> INFO: 41600 events read in total (2546ms).
[17:56:11.397] <TB1> INFO: Test took 3371ms.
[17:56:11.614] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:11.704] <TB1> INFO: Expecting 2560 events.
[17:56:12.587] <TB1> INFO: 2560 events read in total (292ms).
[17:56:12.587] <TB1> INFO: Test took 973ms.
[17:56:12.589] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:12.896] <TB1> INFO: Expecting 2560 events.
[17:56:13.781] <TB1> INFO: 2560 events read in total (294ms).
[17:56:13.782] <TB1> INFO: Test took 1193ms.
[17:56:13.784] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:14.090] <TB1> INFO: Expecting 2560 events.
[17:56:14.973] <TB1> INFO: 2560 events read in total (291ms).
[17:56:14.973] <TB1> INFO: Test took 1189ms.
[17:56:14.975] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:15.281] <TB1> INFO: Expecting 2560 events.
[17:56:16.165] <TB1> INFO: 2560 events read in total (292ms).
[17:56:16.165] <TB1> INFO: Test took 1190ms.
[17:56:16.167] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:16.474] <TB1> INFO: Expecting 2560 events.
[17:56:17.356] <TB1> INFO: 2560 events read in total (291ms).
[17:56:17.356] <TB1> INFO: Test took 1189ms.
[17:56:17.358] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:17.665] <TB1> INFO: Expecting 2560 events.
[17:56:18.550] <TB1> INFO: 2560 events read in total (295ms).
[17:56:18.551] <TB1> INFO: Test took 1193ms.
[17:56:18.554] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:18.859] <TB1> INFO: Expecting 2560 events.
[17:56:19.744] <TB1> INFO: 2560 events read in total (293ms).
[17:56:19.744] <TB1> INFO: Test took 1191ms.
[17:56:19.746] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:20.053] <TB1> INFO: Expecting 2560 events.
[17:56:20.936] <TB1> INFO: 2560 events read in total (292ms).
[17:56:20.936] <TB1> INFO: Test took 1190ms.
[17:56:20.938] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:21.244] <TB1> INFO: Expecting 2560 events.
[17:56:22.123] <TB1> INFO: 2560 events read in total (287ms).
[17:56:22.124] <TB1> INFO: Test took 1186ms.
[17:56:22.126] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:22.432] <TB1> INFO: Expecting 2560 events.
[17:56:23.312] <TB1> INFO: 2560 events read in total (289ms).
[17:56:23.313] <TB1> INFO: Test took 1187ms.
[17:56:23.314] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:23.621] <TB1> INFO: Expecting 2560 events.
[17:56:24.500] <TB1> INFO: 2560 events read in total (287ms).
[17:56:24.500] <TB1> INFO: Test took 1186ms.
[17:56:24.502] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:24.809] <TB1> INFO: Expecting 2560 events.
[17:56:25.688] <TB1> INFO: 2560 events read in total (287ms).
[17:56:25.688] <TB1> INFO: Test took 1186ms.
[17:56:25.689] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:25.996] <TB1> INFO: Expecting 2560 events.
[17:56:26.878] <TB1> INFO: 2560 events read in total (290ms).
[17:56:26.878] <TB1> INFO: Test took 1189ms.
[17:56:26.880] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:27.187] <TB1> INFO: Expecting 2560 events.
[17:56:28.065] <TB1> INFO: 2560 events read in total (287ms).
[17:56:28.065] <TB1> INFO: Test took 1185ms.
[17:56:28.068] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:28.373] <TB1> INFO: Expecting 2560 events.
[17:56:29.256] <TB1> INFO: 2560 events read in total (291ms).
[17:56:29.256] <TB1> INFO: Test took 1189ms.
[17:56:29.258] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:29.564] <TB1> INFO: Expecting 2560 events.
[17:56:30.446] <TB1> INFO: 2560 events read in total (290ms).
[17:56:30.446] <TB1> INFO: Test took 1188ms.
[17:56:30.448] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:30.754] <TB1> INFO: Expecting 2560 events.
[17:56:31.634] <TB1> INFO: 2560 events read in total (288ms).
[17:56:31.634] <TB1> INFO: Test took 1186ms.
[17:56:31.636] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:31.942] <TB1> INFO: Expecting 2560 events.
[17:56:32.822] <TB1> INFO: 2560 events read in total (288ms).
[17:56:32.823] <TB1> INFO: Test took 1187ms.
[17:56:32.825] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:33.131] <TB1> INFO: Expecting 2560 events.
[17:56:34.007] <TB1> INFO: 2560 events read in total (285ms).
[17:56:34.007] <TB1> INFO: Test took 1182ms.
[17:56:34.009] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:34.316] <TB1> INFO: Expecting 2560 events.
[17:56:35.195] <TB1> INFO: 2560 events read in total (287ms).
[17:56:35.196] <TB1> INFO: Test took 1187ms.
[17:56:35.198] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:35.504] <TB1> INFO: Expecting 2560 events.
[17:56:36.382] <TB1> INFO: 2560 events read in total (287ms).
[17:56:36.382] <TB1> INFO: Test took 1185ms.
[17:56:36.384] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:36.691] <TB1> INFO: Expecting 2560 events.
[17:56:37.570] <TB1> INFO: 2560 events read in total (288ms).
[17:56:37.571] <TB1> INFO: Test took 1187ms.
[17:56:37.572] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:37.879] <TB1> INFO: Expecting 2560 events.
[17:56:38.757] <TB1> INFO: 2560 events read in total (287ms).
[17:56:38.758] <TB1> INFO: Test took 1186ms.
[17:56:38.759] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:39.066] <TB1> INFO: Expecting 2560 events.
[17:56:39.948] <TB1> INFO: 2560 events read in total (290ms).
[17:56:39.948] <TB1> INFO: Test took 1189ms.
[17:56:39.951] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:40.257] <TB1> INFO: Expecting 2560 events.
[17:56:41.142] <TB1> INFO: 2560 events read in total (294ms).
[17:56:41.142] <TB1> INFO: Test took 1191ms.
[17:56:41.144] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:41.451] <TB1> INFO: Expecting 2560 events.
[17:56:42.335] <TB1> INFO: 2560 events read in total (293ms).
[17:56:42.335] <TB1> INFO: Test took 1191ms.
[17:56:42.337] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:42.643] <TB1> INFO: Expecting 2560 events.
[17:56:43.527] <TB1> INFO: 2560 events read in total (292ms).
[17:56:43.527] <TB1> INFO: Test took 1190ms.
[17:56:43.529] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:43.835] <TB1> INFO: Expecting 2560 events.
[17:56:44.718] <TB1> INFO: 2560 events read in total (291ms).
[17:56:44.718] <TB1> INFO: Test took 1189ms.
[17:56:44.720] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:45.026] <TB1> INFO: Expecting 2560 events.
[17:56:45.912] <TB1> INFO: 2560 events read in total (294ms).
[17:56:45.912] <TB1> INFO: Test took 1192ms.
[17:56:45.914] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:46.220] <TB1> INFO: Expecting 2560 events.
[17:56:47.103] <TB1> INFO: 2560 events read in total (291ms).
[17:56:47.104] <TB1> INFO: Test took 1190ms.
[17:56:47.105] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:47.412] <TB1> INFO: Expecting 2560 events.
[17:56:48.295] <TB1> INFO: 2560 events read in total (292ms).
[17:56:48.296] <TB1> INFO: Test took 1191ms.
[17:56:48.298] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:48.604] <TB1> INFO: Expecting 2560 events.
[17:56:49.486] <TB1> INFO: 2560 events read in total (291ms).
[17:56:49.486] <TB1> INFO: Test took 1188ms.
[17:56:49.950] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 723 seconds
[17:56:49.950] <TB1> INFO: PH scale (per ROC): 41 50 34 34 38 44 57 30 38 30 39 35 37 37 37 35
[17:56:49.950] <TB1> INFO: PH offset (per ROC): 95 128 105 110 99 112 134 91 105 125 114 96 97 105 97 108
[17:56:49.956] <TB1> INFO: Decoding statistics:
[17:56:49.956] <TB1> INFO: General information:
[17:56:49.956] <TB1> INFO: 16bit words read: 127886
[17:56:49.956] <TB1> INFO: valid events total: 20480
[17:56:49.957] <TB1> INFO: empty events: 17977
[17:56:49.957] <TB1> INFO: valid events with pixels: 2503
[17:56:49.957] <TB1> INFO: valid pixel hits: 2503
[17:56:49.957] <TB1> INFO: Event errors: 0
[17:56:49.957] <TB1> INFO: start marker: 0
[17:56:49.957] <TB1> INFO: stop marker: 0
[17:56:49.957] <TB1> INFO: overflow: 0
[17:56:49.957] <TB1> INFO: invalid 5bit words: 0
[17:56:49.957] <TB1> INFO: invalid XOR eye diagram: 0
[17:56:49.957] <TB1> INFO: frame (failed synchr.): 0
[17:56:49.957] <TB1> INFO: idle data (no TBM trl): 0
[17:56:49.957] <TB1> INFO: no data (only TBM hdr): 0
[17:56:49.957] <TB1> INFO: TBM errors: 0
[17:56:49.957] <TB1> INFO: flawed TBM headers: 0
[17:56:49.957] <TB1> INFO: flawed TBM trailers: 0
[17:56:49.957] <TB1> INFO: event ID mismatches: 0
[17:56:49.957] <TB1> INFO: ROC errors: 0
[17:56:49.957] <TB1> INFO: missing ROC header(s): 0
[17:56:49.957] <TB1> INFO: misplaced readback start: 0
[17:56:49.957] <TB1> INFO: Pixel decoding errors: 0
[17:56:49.957] <TB1> INFO: pixel data incomplete: 0
[17:56:49.957] <TB1> INFO: pixel address: 0
[17:56:49.957] <TB1> INFO: pulse height fill bit: 0
[17:56:49.957] <TB1> INFO: buffer corruption: 0
[17:56:50.228] <TB1> INFO: ######################################################################
[17:56:50.228] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[17:56:50.228] <TB1> INFO: ######################################################################
[17:56:50.239] <TB1> INFO: scanning low vcal = 10
[17:56:50.471] <TB1> INFO: Expecting 41600 events.
[17:56:54.039] <TB1> INFO: 41600 events read in total (2977ms).
[17:56:54.040] <TB1> INFO: Test took 3801ms.
[17:56:54.042] <TB1> INFO: scanning low vcal = 20
[17:56:54.340] <TB1> INFO: Expecting 41600 events.
[17:56:57.891] <TB1> INFO: 41600 events read in total (2959ms).
[17:56:57.891] <TB1> INFO: Test took 3849ms.
[17:56:57.892] <TB1> INFO: scanning low vcal = 30
[17:56:58.191] <TB1> INFO: Expecting 41600 events.
[17:57:01.816] <TB1> INFO: 41600 events read in total (3034ms).
[17:57:01.818] <TB1> INFO: Test took 3925ms.
[17:57:01.820] <TB1> INFO: scanning low vcal = 40
[17:57:02.097] <TB1> INFO: Expecting 41600 events.
[17:57:06.025] <TB1> INFO: 41600 events read in total (3337ms).
[17:57:06.026] <TB1> INFO: Test took 4206ms.
[17:57:06.029] <TB1> INFO: scanning low vcal = 50
[17:57:06.306] <TB1> INFO: Expecting 41600 events.
[17:57:10.241] <TB1> INFO: 41600 events read in total (3344ms).
[17:57:10.242] <TB1> INFO: Test took 4213ms.
[17:57:10.244] <TB1> INFO: scanning low vcal = 60
[17:57:10.521] <TB1> INFO: Expecting 41600 events.
[17:57:14.448] <TB1> INFO: 41600 events read in total (3335ms).
[17:57:14.449] <TB1> INFO: Test took 4204ms.
[17:57:14.452] <TB1> INFO: scanning low vcal = 70
[17:57:14.728] <TB1> INFO: Expecting 41600 events.
[17:57:18.669] <TB1> INFO: 41600 events read in total (3349ms).
[17:57:18.670] <TB1> INFO: Test took 4218ms.
[17:57:18.672] <TB1> INFO: scanning low vcal = 80
[17:57:18.949] <TB1> INFO: Expecting 41600 events.
[17:57:22.908] <TB1> INFO: 41600 events read in total (3367ms).
[17:57:22.909] <TB1> INFO: Test took 4237ms.
[17:57:22.911] <TB1> INFO: scanning low vcal = 90
[17:57:23.188] <TB1> INFO: Expecting 41600 events.
[17:57:27.113] <TB1> INFO: 41600 events read in total (3334ms).
[17:57:27.114] <TB1> INFO: Test took 4203ms.
[17:57:27.117] <TB1> INFO: scanning low vcal = 100
[17:57:27.393] <TB1> INFO: Expecting 41600 events.
[17:57:31.341] <TB1> INFO: 41600 events read in total (3356ms).
[17:57:31.342] <TB1> INFO: Test took 4225ms.
[17:57:31.345] <TB1> INFO: scanning low vcal = 110
[17:57:31.621] <TB1> INFO: Expecting 41600 events.
[17:57:35.568] <TB1> INFO: 41600 events read in total (3355ms).
[17:57:35.568] <TB1> INFO: Test took 4223ms.
[17:57:35.571] <TB1> INFO: scanning low vcal = 120
[17:57:35.848] <TB1> INFO: Expecting 41600 events.
[17:57:39.782] <TB1> INFO: 41600 events read in total (3343ms).
[17:57:39.783] <TB1> INFO: Test took 4212ms.
[17:57:39.785] <TB1> INFO: scanning low vcal = 130
[17:57:40.062] <TB1> INFO: Expecting 41600 events.
[17:57:44.039] <TB1> INFO: 41600 events read in total (3386ms).
[17:57:44.040] <TB1> INFO: Test took 4254ms.
[17:57:44.043] <TB1> INFO: scanning low vcal = 140
[17:57:44.319] <TB1> INFO: Expecting 41600 events.
[17:57:48.256] <TB1> INFO: 41600 events read in total (3345ms).
[17:57:48.257] <TB1> INFO: Test took 4214ms.
[17:57:48.260] <TB1> INFO: scanning low vcal = 150
[17:57:48.536] <TB1> INFO: Expecting 41600 events.
[17:57:52.467] <TB1> INFO: 41600 events read in total (3339ms).
[17:57:52.468] <TB1> INFO: Test took 4207ms.
[17:57:52.471] <TB1> INFO: scanning low vcal = 160
[17:57:52.747] <TB1> INFO: Expecting 41600 events.
[17:57:56.761] <TB1> INFO: 41600 events read in total (3422ms).
[17:57:56.762] <TB1> INFO: Test took 4291ms.
[17:57:56.764] <TB1> INFO: scanning low vcal = 170
[17:57:57.041] <TB1> INFO: Expecting 41600 events.
[17:58:00.004] <TB1> INFO: 41600 events read in total (3371ms).
[17:58:00.005] <TB1> INFO: Test took 4240ms.
[17:58:01.008] <TB1> INFO: scanning low vcal = 180
[17:58:01.285] <TB1> INFO: Expecting 41600 events.
[17:58:05.220] <TB1> INFO: 41600 events read in total (3344ms).
[17:58:05.221] <TB1> INFO: Test took 4213ms.
[17:58:05.223] <TB1> INFO: scanning low vcal = 190
[17:58:05.501] <TB1> INFO: Expecting 41600 events.
[17:58:09.513] <TB1> INFO: 41600 events read in total (3420ms).
[17:58:09.514] <TB1> INFO: Test took 4290ms.
[17:58:09.517] <TB1> INFO: scanning low vcal = 200
[17:58:09.793] <TB1> INFO: Expecting 41600 events.
[17:58:13.782] <TB1> INFO: 41600 events read in total (3397ms).
[17:58:13.783] <TB1> INFO: Test took 4266ms.
[17:58:13.786] <TB1> INFO: scanning low vcal = 210
[17:58:14.063] <TB1> INFO: Expecting 41600 events.
[17:58:18.008] <TB1> INFO: 41600 events read in total (3354ms).
[17:58:18.008] <TB1> INFO: Test took 4222ms.
[17:58:18.011] <TB1> INFO: scanning low vcal = 220
[17:58:18.288] <TB1> INFO: Expecting 41600 events.
[17:58:22.247] <TB1> INFO: 41600 events read in total (3367ms).
[17:58:22.248] <TB1> INFO: Test took 4237ms.
[17:58:22.251] <TB1> INFO: scanning low vcal = 230
[17:58:22.528] <TB1> INFO: Expecting 41600 events.
[17:58:26.495] <TB1> INFO: 41600 events read in total (3376ms).
[17:58:26.496] <TB1> INFO: Test took 4244ms.
[17:58:26.498] <TB1> INFO: scanning low vcal = 240
[17:58:26.785] <TB1> INFO: Expecting 41600 events.
[17:58:30.780] <TB1> INFO: 41600 events read in total (3403ms).
[17:58:30.781] <TB1> INFO: Test took 4282ms.
[17:58:30.784] <TB1> INFO: scanning low vcal = 250
[17:58:31.060] <TB1> INFO: Expecting 41600 events.
[17:58:34.001] <TB1> INFO: 41600 events read in total (3349ms).
[17:58:34.002] <TB1> INFO: Test took 4218ms.
[17:58:34.006] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[17:58:35.282] <TB1> INFO: Expecting 41600 events.
[17:58:39.236] <TB1> INFO: 41600 events read in total (3362ms).
[17:58:39.237] <TB1> INFO: Test took 4231ms.
[17:58:39.240] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[17:58:39.516] <TB1> INFO: Expecting 41600 events.
[17:58:43.470] <TB1> INFO: 41600 events read in total (3362ms).
[17:58:43.471] <TB1> INFO: Test took 4231ms.
[17:58:43.473] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[17:58:43.750] <TB1> INFO: Expecting 41600 events.
[17:58:47.677] <TB1> INFO: 41600 events read in total (3335ms).
[17:58:47.677] <TB1> INFO: Test took 4203ms.
[17:58:47.680] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[17:58:47.957] <TB1> INFO: Expecting 41600 events.
[17:58:51.916] <TB1> INFO: 41600 events read in total (3368ms).
[17:58:51.917] <TB1> INFO: Test took 4237ms.
[17:58:51.920] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[17:58:52.197] <TB1> INFO: Expecting 41600 events.
[17:58:56.177] <TB1> INFO: 41600 events read in total (3388ms).
[17:58:56.178] <TB1> INFO: Test took 4258ms.
[17:58:56.743] <TB1> INFO: PixTestGainPedestal::measure() done
[17:59:39.942] <TB1> INFO: PixTestGainPedestal::fit() done
[17:59:39.942] <TB1> INFO: non-linearity mean: 0.925 0.976 0.940 0.945 0.920 0.950 0.983 0.952 0.935 0.913 0.948 0.929 0.936 0.949 0.933 0.918
[17:59:39.942] <TB1> INFO: non-linearity RMS: 0.066 0.004 0.059 0.039 0.099 0.034 0.003 0.135 0.051 0.116 0.159 0.144 0.116 0.029 0.049 0.084
[17:59:39.942] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[17:59:39.963] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[17:59:39.984] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[17:59:39.003] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[17:59:40.022] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[17:59:40.040] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[17:59:40.059] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[17:59:40.078] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[17:59:40.097] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[17:59:40.116] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[17:59:40.135] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[17:59:40.154] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[17:59:40.173] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[17:59:40.192] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[17:59:40.211] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[17:59:40.231] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[17:59:40.251] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 170 seconds
[17:59:40.251] <TB1> INFO: Decoding statistics:
[17:59:40.251] <TB1> INFO: General information:
[17:59:40.251] <TB1> INFO: 16bit words read: 3326718
[17:59:40.251] <TB1> INFO: valid events total: 332800
[17:59:40.251] <TB1> INFO: empty events: 0
[17:59:40.251] <TB1> INFO: valid events with pixels: 332800
[17:59:40.251] <TB1> INFO: valid pixel hits: 664959
[17:59:40.251] <TB1> INFO: Event errors: 0
[17:59:40.251] <TB1> INFO: start marker: 0
[17:59:40.251] <TB1> INFO: stop marker: 0
[17:59:40.251] <TB1> INFO: overflow: 0
[17:59:40.251] <TB1> INFO: invalid 5bit words: 0
[17:59:40.251] <TB1> INFO: invalid XOR eye diagram: 0
[17:59:40.251] <TB1> INFO: frame (failed synchr.): 0
[17:59:40.251] <TB1> INFO: idle data (no TBM trl): 0
[17:59:40.251] <TB1> INFO: no data (only TBM hdr): 0
[17:59:40.251] <TB1> INFO: TBM errors: 0
[17:59:40.251] <TB1> INFO: flawed TBM headers: 0
[17:59:40.251] <TB1> INFO: flawed TBM trailers: 0
[17:59:40.251] <TB1> INFO: event ID mismatches: 0
[17:59:40.251] <TB1> INFO: ROC errors: 0
[17:59:40.251] <TB1> INFO: missing ROC header(s): 0
[17:59:40.251] <TB1> INFO: misplaced readback start: 0
[17:59:40.251] <TB1> INFO: Pixel decoding errors: 0
[17:59:40.251] <TB1> INFO: pixel data incomplete: 0
[17:59:40.251] <TB1> INFO: pixel address: 0
[17:59:40.251] <TB1> INFO: pulse height fill bit: 0
[17:59:40.251] <TB1> INFO: buffer corruption: 0
[17:59:40.274] <TB1> INFO: Decoding statistics:
[17:59:40.274] <TB1> INFO: General information:
[17:59:40.274] <TB1> INFO: 16bit words read: 3456140
[17:59:40.274] <TB1> INFO: valid events total: 353536
[17:59:40.274] <TB1> INFO: empty events: 18233
[17:59:40.274] <TB1> INFO: valid events with pixels: 335303
[17:59:40.274] <TB1> INFO: valid pixel hits: 667462
[17:59:40.274] <TB1> INFO: Event errors: 0
[17:59:40.274] <TB1> INFO: start marker: 0
[17:59:40.274] <TB1> INFO: stop marker: 0
[17:59:40.274] <TB1> INFO: overflow: 0
[17:59:40.274] <TB1> INFO: invalid 5bit words: 0
[17:59:40.274] <TB1> INFO: invalid XOR eye diagram: 0
[17:59:40.274] <TB1> INFO: frame (failed synchr.): 0
[17:59:40.274] <TB1> INFO: idle data (no TBM trl): 0
[17:59:40.274] <TB1> INFO: no data (only TBM hdr): 0
[17:59:40.274] <TB1> INFO: TBM errors: 0
[17:59:40.274] <TB1> INFO: flawed TBM headers: 0
[17:59:40.274] <TB1> INFO: flawed TBM trailers: 0
[17:59:40.274] <TB1> INFO: event ID mismatches: 0
[17:59:40.274] <TB1> INFO: ROC errors: 0
[17:59:40.274] <TB1> INFO: missing ROC header(s): 0
[17:59:40.274] <TB1> INFO: misplaced readback start: 0
[17:59:40.274] <TB1> INFO: Pixel decoding errors: 0
[17:59:40.274] <TB1> INFO: pixel data incomplete: 0
[17:59:40.274] <TB1> INFO: pixel address: 0
[17:59:40.274] <TB1> INFO: pulse height fill bit: 0
[17:59:40.274] <TB1> INFO: buffer corruption: 0
[17:59:40.274] <TB1> INFO: enter test to run
[17:59:40.274] <TB1> INFO: test: Trim80 no parameter change
[17:59:40.274] <TB1> INFO: running: trim80
[17:59:40.297] <TB1> INFO: ######################################################################
[17:59:40.297] <TB1> INFO: PixTestTrim80::doTest()
[17:59:40.297] <TB1> INFO: ######################################################################
[17:59:40.298] <TB1> INFO: ----------------------------------------------------------------------
[17:59:40.298] <TB1> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[17:59:40.298] <TB1> INFO: ----------------------------------------------------------------------
[17:59:40.338] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[17:59:40.338] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:59:40.347] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:59:40.347] <TB1> INFO: run 1 of 1
[17:59:40.581] <TB1> INFO: Expecting 5025280 events.
[18:00:08.331] <TB1> INFO: 680480 events read in total (27158ms).
[18:00:35.313] <TB1> INFO: 1357688 events read in total (54140ms).
[18:01:02.011] <TB1> INFO: 2032512 events read in total (80838ms).
[18:01:29.166] <TB1> INFO: 2707224 events read in total (107993ms).
[18:01:56.404] <TB1> INFO: 3381712 events read in total (135231ms).
[18:02:23.117] <TB1> INFO: 4054976 events read in total (161944ms).
[18:02:49.926] <TB1> INFO: 4728656 events read in total (188753ms).
[18:03:02.038] <TB1> INFO: 5025280 events read in total (200865ms).
[18:03:02.102] <TB1> INFO: Test took 201755ms.
[18:03:23.055] <TB1> INFO: ROC 0 VthrComp = 71
[18:03:23.055] <TB1> INFO: ROC 1 VthrComp = 74
[18:03:23.055] <TB1> INFO: ROC 2 VthrComp = 74
[18:03:23.055] <TB1> INFO: ROC 3 VthrComp = 67
[18:03:23.055] <TB1> INFO: ROC 4 VthrComp = 66
[18:03:23.056] <TB1> INFO: ROC 5 VthrComp = 62
[18:03:23.056] <TB1> INFO: ROC 6 VthrComp = 70
[18:03:23.056] <TB1> INFO: ROC 7 VthrComp = 66
[18:03:23.056] <TB1> INFO: ROC 8 VthrComp = 63
[18:03:23.056] <TB1> INFO: ROC 9 VthrComp = 76
[18:03:23.056] <TB1> INFO: ROC 10 VthrComp = 67
[18:03:23.056] <TB1> INFO: ROC 11 VthrComp = 58
[18:03:23.056] <TB1> INFO: ROC 12 VthrComp = 71
[18:03:23.056] <TB1> INFO: ROC 13 VthrComp = 70
[18:03:23.057] <TB1> INFO: ROC 14 VthrComp = 67
[18:03:23.057] <TB1> INFO: ROC 15 VthrComp = 66
[18:03:23.378] <TB1> INFO: Expecting 41600 events.
[18:03:26.837] <TB1> INFO: 41600 events read in total (2864ms).
[18:03:26.838] <TB1> INFO: Test took 3779ms.
[18:03:26.847] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[18:03:26.847] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[18:03:26.856] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:03:26.856] <TB1> INFO: run 1 of 1
[18:03:27.134] <TB1> INFO: Expecting 5025280 events.
[18:03:54.891] <TB1> INFO: 687968 events read in total (27166ms).
[18:04:22.076] <TB1> INFO: 1371936 events read in total (54352ms).
[18:04:48.769] <TB1> INFO: 2054624 events read in total (81044ms).
[18:05:15.970] <TB1> INFO: 2734032 events read in total (108245ms).
[18:05:42.902] <TB1> INFO: 3410152 events read in total (135177ms).
[18:06:09.620] <TB1> INFO: 4083552 events read in total (161895ms).
[18:06:35.905] <TB1> INFO: 4757696 events read in total (188180ms).
[18:06:46.876] <TB1> INFO: 5025280 events read in total (199151ms).
[18:06:46.942] <TB1> INFO: Test took 200086ms.
[18:07:11.122] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 111 for pixel 50/1 mean/min/max = 92.8778/74.6324/111.123
[18:07:11.122] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 111.388 for pixel 28/79 mean/min/max = 94.3813/77.2692/111.493
[18:07:11.122] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 114.539 for pixel 0/4 mean/min/max = 96.01/77.216/114.804
[18:07:11.123] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 112.273 for pixel 0/3 mean/min/max = 93.5348/74.2742/112.795
[18:07:11.123] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 109.724 for pixel 0/79 mean/min/max = 92.1455/74.566/109.725
[18:07:11.124] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 110.674 for pixel 2/15 mean/min/max = 92.8077/74.9091/110.706
[18:07:11.124] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 110.61 for pixel 25/76 mean/min/max = 92.9392/75.1672/110.711
[18:07:11.124] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 112.735 for pixel 51/22 mean/min/max = 93.1537/73.3502/112.957
[18:07:11.125] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 112.09 for pixel 2/1 mean/min/max = 93.438/74.5474/112.329
[18:07:11.125] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 113.334 for pixel 0/12 mean/min/max = 95.8321/77.3918/114.272
[18:07:11.125] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 108.053 for pixel 22/76 mean/min/max = 90.6575/73.2171/108.098
[18:07:11.126] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 110.205 for pixel 0/70 mean/min/max = 93.0013/75.7375/110.265
[18:07:11.126] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 109.412 for pixel 0/79 mean/min/max = 91.837/74.0172/109.657
[18:07:11.127] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 110.526 for pixel 51/5 mean/min/max = 92.2992/74.0381/110.56
[18:07:11.127] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 110.121 for pixel 51/79 mean/min/max = 92.3109/74.3159/110.306
[18:07:11.127] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 109.469 for pixel 12/75 mean/min/max = 91.7068/73.8599/109.554
[18:07:11.128] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:07:11.216] <TB1> INFO: Expecting 411648 events.
[18:07:20.493] <TB1> INFO: 411648 events read in total (8685ms).
[18:07:20.501] <TB1> INFO: Expecting 411648 events.
[18:07:29.453] <TB1> INFO: 411648 events read in total (8549ms).
[18:07:29.462] <TB1> INFO: Expecting 411648 events.
[18:07:38.539] <TB1> INFO: 411648 events read in total (8674ms).
[18:07:38.551] <TB1> INFO: Expecting 411648 events.
[18:07:47.533] <TB1> INFO: 411648 events read in total (8579ms).
[18:07:47.547] <TB1> INFO: Expecting 411648 events.
[18:07:56.577] <TB1> INFO: 411648 events read in total (8627ms).
[18:07:56.595] <TB1> INFO: Expecting 411648 events.
[18:08:05.677] <TB1> INFO: 411648 events read in total (8680ms).
[18:08:05.697] <TB1> INFO: Expecting 411648 events.
[18:08:14.726] <TB1> INFO: 411648 events read in total (8626ms).
[18:08:14.756] <TB1> INFO: Expecting 411648 events.
[18:08:23.908] <TB1> INFO: 411648 events read in total (8749ms).
[18:08:23.932] <TB1> INFO: Expecting 411648 events.
[18:08:33.051] <TB1> INFO: 411648 events read in total (8716ms).
[18:08:33.079] <TB1> INFO: Expecting 411648 events.
[18:08:42.101] <TB1> INFO: 411648 events read in total (8619ms).
[18:08:42.133] <TB1> INFO: Expecting 411648 events.
[18:08:51.224] <TB1> INFO: 411648 events read in total (8688ms).
[18:08:51.260] <TB1> INFO: Expecting 411648 events.
[18:09:00.335] <TB1> INFO: 411648 events read in total (8672ms).
[18:09:00.383] <TB1> INFO: Expecting 411648 events.
[18:09:09.519] <TB1> INFO: 411648 events read in total (8733ms).
[18:09:09.559] <TB1> INFO: Expecting 411648 events.
[18:09:18.620] <TB1> INFO: 411648 events read in total (8658ms).
[18:09:18.663] <TB1> INFO: Expecting 411648 events.
[18:09:27.812] <TB1> INFO: 411648 events read in total (8746ms).
[18:09:27.859] <TB1> INFO: Expecting 411648 events.
[18:09:37.110] <TB1> INFO: 411648 events read in total (8847ms).
[18:09:37.160] <TB1> INFO: Test took 146032ms.
[18:09:38.936] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[18:09:38.947] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:09:38.947] <TB1> INFO: run 1 of 1
[18:09:39.220] <TB1> INFO: Expecting 5025280 events.
[18:10:06.450] <TB1> INFO: 665104 events read in total (26638ms).
[18:10:32.888] <TB1> INFO: 1327776 events read in total (53076ms).
[18:10:59.719] <TB1> INFO: 1990320 events read in total (79907ms).
[18:11:26.974] <TB1> INFO: 2650248 events read in total (107162ms).
[18:11:53.968] <TB1> INFO: 3306496 events read in total (134156ms).
[18:12:20.572] <TB1> INFO: 3961992 events read in total (160760ms).
[18:12:46.991] <TB1> INFO: 4617360 events read in total (187179ms).
[18:13:03.194] <TB1> INFO: 5025280 events read in total (203382ms).
[18:13:03.260] <TB1> INFO: Test took 204313ms.
[18:13:28.190] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 48.704642 .. 99.725192
[18:13:28.428] <TB1> INFO: Expecting 208000 events.
[18:13:38.279] <TB1> INFO: 208000 events read in total (9260ms).
[18:13:38.280] <TB1> INFO: Test took 10088ms.
[18:13:38.329] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 38 .. 109 (-1/-1) hits flags = 528 (plus default)
[18:13:38.339] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:13:38.339] <TB1> INFO: run 1 of 1
[18:13:38.617] <TB1> INFO: Expecting 2396160 events.
[18:14:06.713] <TB1> INFO: 703640 events read in total (27494ms).
[18:14:34.229] <TB1> INFO: 1402224 events read in total (55010ms).
[18:15:01.443] <TB1> INFO: 2095152 events read in total (82224ms).
[18:15:13.522] <TB1> INFO: 2396160 events read in total (94303ms).
[18:15:13.558] <TB1> INFO: Test took 95219ms.
[18:15:32.974] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 60.378101 .. 89.189748
[18:15:33.209] <TB1> INFO: Expecting 208000 events.
[18:15:43.212] <TB1> INFO: 208000 events read in total (9411ms).
[18:15:43.213] <TB1> INFO: Test took 10237ms.
[18:15:43.260] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 50 .. 99 (-1/-1) hits flags = 528 (plus default)
[18:15:43.268] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:15:43.268] <TB1> INFO: run 1 of 1
[18:15:43.546] <TB1> INFO: Expecting 1664000 events.
[18:16:12.015] <TB1> INFO: 707192 events read in total (27877ms).
[18:16:39.985] <TB1> INFO: 1413912 events read in total (55847ms).
[18:16:50.028] <TB1> INFO: 1664000 events read in total (65890ms).
[18:16:50.064] <TB1> INFO: Test took 66796ms.
[18:17:07.780] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 65.296897 .. 83.872085
[18:17:08.038] <TB1> INFO: Expecting 208000 events.
[18:17:17.583] <TB1> INFO: 208000 events read in total (8953ms).
[18:17:17.584] <TB1> INFO: Test took 9803ms.
[18:17:17.651] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 55 .. 93 (-1/-1) hits flags = 528 (plus default)
[18:17:17.662] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:17:17.662] <TB1> INFO: run 1 of 1
[18:17:17.940] <TB1> INFO: Expecting 1297920 events.
[18:17:46.796] <TB1> INFO: 724696 events read in total (28264ms).
[18:18:09.664] <TB1> INFO: 1297920 events read in total (51132ms).
[18:18:09.688] <TB1> INFO: Test took 52025ms.
[18:18:26.068] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 68.810185 .. 83.824545
[18:18:26.334] <TB1> INFO: Expecting 208000 events.
[18:18:36.213] <TB1> INFO: 208000 events read in total (9287ms).
[18:18:36.213] <TB1> INFO: Test took 10144ms.
[18:18:36.261] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 58 .. 93 (-1/-1) hits flags = 528 (plus default)
[18:18:36.270] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:18:36.270] <TB1> INFO: run 1 of 1
[18:18:36.548] <TB1> INFO: Expecting 1198080 events.
[18:19:05.641] <TB1> INFO: 715264 events read in total (28501ms).
[18:19:25.254] <TB1> INFO: 1198080 events read in total (48114ms).
[18:19:25.279] <TB1> INFO: Test took 49010ms.
[18:19:40.536] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[18:19:40.536] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[18:19:40.545] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:19:40.545] <TB1> INFO: run 1 of 1
[18:19:40.785] <TB1> INFO: Expecting 1364480 events.
[18:20:08.422] <TB1> INFO: 667792 events read in total (27045ms).
[18:20:36.279] <TB1> INFO: 1335240 events read in total (54902ms).
[18:20:37.902] <TB1> INFO: 1364480 events read in total (56525ms).
[18:20:37.924] <TB1> INFO: Test took 57380ms.
[18:20:53.731] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C0.dat
[18:20:53.731] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C1.dat
[18:20:53.731] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C2.dat
[18:20:53.731] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C3.dat
[18:20:53.731] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C4.dat
[18:20:53.731] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C5.dat
[18:20:53.731] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C6.dat
[18:20:53.731] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C7.dat
[18:20:53.732] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C8.dat
[18:20:53.732] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C9.dat
[18:20:53.732] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C10.dat
[18:20:53.732] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C11.dat
[18:20:53.732] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C12.dat
[18:20:53.732] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C13.dat
[18:20:53.732] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C14.dat
[18:20:53.732] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//dacParameters80_C15.dat
[18:20:53.732] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C0.dat
[18:20:53.739] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C1.dat
[18:20:53.745] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C2.dat
[18:20:53.750] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C3.dat
[18:20:53.756] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C4.dat
[18:20:53.761] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C5.dat
[18:20:53.767] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C6.dat
[18:20:53.773] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C7.dat
[18:20:53.778] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C8.dat
[18:20:53.785] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C9.dat
[18:20:53.791] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C10.dat
[18:20:53.797] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C11.dat
[18:20:53.804] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C12.dat
[18:20:53.810] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C13.dat
[18:20:53.816] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C14.dat
[18:20:53.822] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1078_FullQualification_2016-10-25_15h54m_1477403681//001_Fulltest_m20//trimParameters80_C15.dat
[18:20:53.829] <TB1> INFO: PixTestTrim80::trimTest() done
[18:20:53.829] <TB1> INFO: vtrim: 98 119 117 112 92 109 111 106 105 120 94 87 87 106 92 101
[18:20:53.829] <TB1> INFO: vthrcomp: 71 74 74 67 66 62 70 66 63 76 67 58 71 70 67 66
[18:20:53.829] <TB1> INFO: vcal mean: 79.95 79.97 80.04 79.99 79.93 79.99 79.96 79.96 79.95 79.97 79.96 79.99 79.93 79.94 79.97 80.00
[18:20:53.829] <TB1> INFO: vcal RMS: 0.87 0.90 0.90 0.93 0.80 0.90 0.85 0.92 0.82 0.90 0.76 0.78 0.81 0.87 0.85 0.82
[18:20:53.829] <TB1> INFO: bits mean: 10.10 9.96 9.31 10.50 10.06 10.62 10.30 10.24 10.23 9.26 10.51 9.94 10.32 10.44 9.93 10.54
[18:20:53.829] <TB1> INFO: bits RMS: 2.38 2.09 2.30 2.15 2.39 2.08 2.18 2.41 2.24 2.31 2.38 2.28 2.35 2.28 2.50 2.25
[18:20:53.836] <TB1> INFO: ----------------------------------------------------------------------
[18:20:53.836] <TB1> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[18:20:53.836] <TB1> INFO: ----------------------------------------------------------------------
[18:20:53.838] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[18:20:53.848] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[18:20:53.848] <TB1> INFO: run 1 of 1
[18:20:54.122] <TB1> INFO: Expecting 4160000 events.
[18:21:25.699] <TB1> INFO: 741820 events read in total (30985ms).
[18:21:56.672] <TB1> INFO: 1478815 events read in total (61958ms).
[18:22:27.529] <TB1> INFO: 2211860 events read in total (92815ms).
[18:22:58.295] <TB1> INFO: 2938215 events read in total (123581ms).
[18:23:28.753] <TB1> INFO: 3661725 events read in total (154039ms).
[18:23:49.812] <TB1> INFO: 4160000 events read in total (175098ms).
[18:23:49.880] <TB1> INFO: Test took 176032ms.
[18:24:17.780] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[18:24:17.790] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[18:24:17.790] <TB1> INFO: run 1 of 1
[18:24:18.021] <TB1> INFO: Expecting 4284800 events.
[18:24:49.180] <TB1> INFO: 709120 events read in total (30567ms).
[18:25:19.517] <TB1> INFO: 1414380 events read in total (60904ms).
[18:25:49.789] <TB1> INFO: 2116300 events read in total (91176ms).
[18:26:20.277] <TB1> INFO: 2813535 events read in total (121664ms).
[18:26:50.467] <TB1> INFO: 3507200 events read in total (151854ms).
[18:27:20.671] <TB1> INFO: 4202385 events read in total (182058ms).
[18:27:24.553] <TB1> INFO: 4284800 events read in total (185940ms).
[18:27:24.619] <TB1> INFO: Test took 186829ms.
[18:27:53.530] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 193 (-1/-1) hits flags = 528 (plus default)
[18:27:53.539] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[18:27:53.539] <TB1> INFO: run 1 of 1
[18:27:53.773] <TB1> INFO: Expecting 4035200 events.
[18:28:24.840] <TB1> INFO: 724180 events read in total (30475ms).
[18:28:55.170] <TB1> INFO: 1443550 events read in total (60805ms).
[18:29:25.737] <TB1> INFO: 2159140 events read in total (91372ms).
[18:29:56.196] <TB1> INFO: 2868645 events read in total (121831ms).
[18:30:26.695] <TB1> INFO: 3575795 events read in total (152330ms).
[18:30:46.333] <TB1> INFO: 4035200 events read in total (171968ms).
[18:30:46.398] <TB1> INFO: Test took 172859ms.
[18:31:13.539] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 195 (-1/-1) hits flags = 528 (plus default)
[18:31:13.551] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[18:31:13.551] <TB1> INFO: run 1 of 1
[18:31:13.819] <TB1> INFO: Expecting 4076800 events.
[18:31:44.975] <TB1> INFO: 721740 events read in total (30564ms).
[18:32:15.088] <TB1> INFO: 1439015 events read in total (60677ms).
[18:32:45.025] <TB1> INFO: 2152465 events read in total (90614ms).
[18:33:15.037] <TB1> INFO: 2860015 events read in total (120626ms).
[18:33:46.115] <TB1> INFO: 3564780 events read in total (151704ms).
[18:34:07.779] <TB1> INFO: 4076800 events read in total (173368ms).
[18:34:07.845] <TB1> INFO: Test took 174294ms.
[18:34:34.970] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 193 (-1/-1) hits flags = 528 (plus default)
[18:34:34.979] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[18:34:34.979] <TB1> INFO: run 1 of 1
[18:34:35.228] <TB1> INFO: Expecting 4035200 events.
[18:35:06.198] <TB1> INFO: 724335 events read in total (30378ms).
[18:35:36.254] <TB1> INFO: 1444130 events read in total (60434ms).
[18:36:06.472] <TB1> INFO: 2160030 events read in total (90652ms).
[18:36:36.573] <TB1> INFO: 2869760 events read in total (120753ms).
[18:37:06.661] <TB1> INFO: 3577045 events read in total (150841ms).
[18:37:26.754] <TB1> INFO: 4035200 events read in total (170934ms).
[18:37:26.805] <TB1> INFO: Test took 171826ms.
[18:37:51.676] <TB1> INFO: PixTestTrim80::trimBitTest() done
[18:37:51.677] <TB1> INFO: PixTestTrim80::doTest() done, duration: 2291 seconds
[18:37:52.327] <TB1> INFO: enter test to run
[18:37:52.327] <TB1> INFO: test: exit no parameter change
[18:37:52.447] <TB1> QUIET: Connection to board 153 closed.
[18:37:52.448] <TB1> INFO: pXar: this is the end, my friend