[17:34:32.968] <TB2> INFO: *** Welcome to pxar ***
[17:34:32.968] <TB2> INFO: *** Today: 2016/10/25
[17:34:32.974] <TB2> INFO: *** Version: c8ba-dirty
[17:34:32.974] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C15.dat
[17:34:32.975] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//tbmParameters_C1b.dat
[17:34:32.975] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//defaultMaskFile.dat
[17:34:32.975] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters_C15.dat
[17:34:33.036] <TB2> INFO: clk: 4
[17:34:33.036] <TB2> INFO: ctr: 4
[17:34:33.036] <TB2> INFO: sda: 19
[17:34:33.036] <TB2> INFO: tin: 9
[17:34:33.036] <TB2> INFO: level: 15
[17:34:33.036] <TB2> INFO: triggerdelay: 0
[17:34:33.036] <TB2> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[17:34:33.036] <TB2> INFO: Log level: INFO
[17:34:33.045] <TB2> INFO: Found DTB DTB_WWXUD2
[17:34:33.052] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[17:34:33.054] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[17:34:33.056] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[17:34:34.552] <TB2> INFO: DUT info:
[17:34:34.552] <TB2> INFO: The DUT currently contains the following objects:
[17:34:34.552] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[17:34:34.552] <TB2> INFO: TBM Core alpha (0): 7 registers set
[17:34:34.552] <TB2> INFO: TBM Core beta (1): 7 registers set
[17:34:34.552] <TB2> INFO: TBM Core alpha (2): 7 registers set
[17:34:34.552] <TB2> INFO: TBM Core beta (3): 7 registers set
[17:34:34.552] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[17:34:34.552] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[17:34:34.553] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[17:34:34.553] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[17:34:34.553] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[17:34:34.553] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[17:34:34.553] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[17:34:34.553] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[17:34:34.553] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[17:34:34.553] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[17:34:34.553] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[17:34:34.553] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[17:34:34.553] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[17:34:34.553] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[17:34:34.553] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[17:34:34.553] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[17:34:34.553] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[17:34:34.954] <TB2> INFO: enter 'restricted' command line mode
[17:34:34.954] <TB2> INFO: enter test to run
[17:34:34.954] <TB2> INFO: test: pretest no parameter change
[17:34:34.954] <TB2> INFO: running: pretest
[17:34:34.959] <TB2> INFO: ######################################################################
[17:34:34.959] <TB2> INFO: PixTestPretest::doTest()
[17:34:34.959] <TB2> INFO: ######################################################################
[17:34:34.960] <TB2> INFO: ----------------------------------------------------------------------
[17:34:34.960] <TB2> INFO: PixTestPretest::programROC()
[17:34:34.960] <TB2> INFO: ----------------------------------------------------------------------
[17:34:52.974] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[17:34:52.974] <TB2> INFO: IA differences per ROC: 17.7 19.3 20.1 20.1 18.5 20.1 21.7 17.7 20.9 21.7 20.1 20.1 17.7 20.1 20.1 19.3
[17:34:53.037] <TB2> INFO: ----------------------------------------------------------------------
[17:34:53.037] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[17:34:53.037] <TB2> INFO: ----------------------------------------------------------------------
[17:35:01.359] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 388.3 mA = 24.2687 mA/ROC
[17:35:01.359] <TB2> INFO: i(loss) [mA/ROC]: 20.1 19.3 19.3 19.3 18.5 18.5 18.5 19.3 20.1 18.5 19.3 18.5 19.3 19.3 18.5 19.3
[17:35:01.394] <TB2> INFO: ----------------------------------------------------------------------
[17:35:01.394] <TB2> INFO: PixTestPretest::findTiming()
[17:35:01.394] <TB2> INFO: ----------------------------------------------------------------------
[17:35:01.395] <TB2> INFO: PixTestCmd::init()

[17:35:33.891] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[17:35:33.891] <TB2> INFO: (success/tries = 100/100), width = 3
[17:35:35.398] <TB2> INFO: ----------------------------------------------------------------------
[17:35:35.398] <TB2> INFO: PixTestPretest::findWorkingPixel()
[17:35:35.398] <TB2> INFO: ----------------------------------------------------------------------
[17:35:35.494] <TB2> INFO: Expecting 231680 events.
[17:35:45.488] <TB2> INFO: 231680 events read in total (9402ms).
[17:35:45.496] <TB2> INFO: Test took 10093ms.
[17:35:45.740] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[17:35:45.775] <TB2> INFO: ----------------------------------------------------------------------
[17:35:45.775] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[17:35:45.775] <TB2> INFO: ----------------------------------------------------------------------
[17:35:45.871] <TB2> INFO: Expecting 231680 events.
[17:35:55.796] <TB2> INFO: 231680 events read in total (9333ms).
[17:35:55.808] <TB2> INFO: Test took 10026ms.
[17:35:56.072] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[17:35:56.072] <TB2> INFO: CalDel: 97 97 100 95 97 91 99 91 100 102 103 96 92 87 93 91
[17:35:56.072] <TB2> INFO: VthrComp: 51 52 51 51 52 51 57 51 53 51 51 51 51 53 51 52
[17:35:56.075] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C0.dat
[17:35:56.076] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C1.dat
[17:35:56.076] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C2.dat
[17:35:56.076] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C3.dat
[17:35:56.076] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C4.dat
[17:35:56.076] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C5.dat
[17:35:56.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C6.dat
[17:35:56.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C7.dat
[17:35:56.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C8.dat
[17:35:56.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C9.dat
[17:35:56.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C10.dat
[17:35:56.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C11.dat
[17:35:56.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C12.dat
[17:35:56.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C13.dat
[17:35:56.078] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C14.dat
[17:35:56.078] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters_C15.dat
[17:35:56.078] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//tbmParameters_C0a.dat
[17:35:56.078] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//tbmParameters_C0b.dat
[17:35:56.078] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//tbmParameters_C1a.dat
[17:35:56.078] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//tbmParameters_C1b.dat
[17:35:56.078] <TB2> INFO: PixTestPretest::doTest() done, duration: 81 seconds
[17:35:56.133] <TB2> INFO: enter test to run
[17:35:56.133] <TB2> INFO: test: FullTest no parameter change
[17:35:56.133] <TB2> INFO: running: fulltest
[17:35:56.133] <TB2> INFO: ######################################################################
[17:35:56.133] <TB2> INFO: PixTestFullTest::doTest()
[17:35:56.133] <TB2> INFO: ######################################################################
[17:35:56.137] <TB2> INFO: ######################################################################
[17:35:56.137] <TB2> INFO: PixTestAlive::doTest()
[17:35:56.137] <TB2> INFO: ######################################################################
[17:35:56.138] <TB2> INFO: ----------------------------------------------------------------------
[17:35:56.138] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[17:35:56.138] <TB2> INFO: ----------------------------------------------------------------------
[17:35:56.396] <TB2> INFO: Expecting 41600 events.
[17:35:59.966] <TB2> INFO: 41600 events read in total (2978ms).
[17:35:59.967] <TB2> INFO: Test took 3827ms.
[17:36:00.200] <TB2> INFO: PixTestAlive::aliveTest() done
[17:36:00.200] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[17:36:00.201] <TB2> INFO: ----------------------------------------------------------------------
[17:36:00.202] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[17:36:00.202] <TB2> INFO: ----------------------------------------------------------------------
[17:36:00.453] <TB2> INFO: Expecting 41600 events.
[17:36:03.489] <TB2> INFO: 41600 events read in total (2444ms).
[17:36:03.489] <TB2> INFO: Test took 3286ms.
[17:36:03.489] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[17:36:03.726] <TB2> INFO: PixTestAlive::maskTest() done
[17:36:03.726] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[17:36:03.727] <TB2> INFO: ----------------------------------------------------------------------
[17:36:03.727] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[17:36:03.727] <TB2> INFO: ----------------------------------------------------------------------
[17:36:03.971] <TB2> INFO: Expecting 41600 events.
[17:36:07.509] <TB2> INFO: 41600 events read in total (2947ms).
[17:36:07.509] <TB2> INFO: Test took 3779ms.
[17:36:07.737] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[17:36:07.737] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[17:36:07.737] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[17:36:07.737] <TB2> INFO: Decoding statistics:
[17:36:07.737] <TB2> INFO: General information:
[17:36:07.737] <TB2> INFO: 16bit words read: 0
[17:36:07.737] <TB2> INFO: valid events total: 0
[17:36:07.737] <TB2> INFO: empty events: 0
[17:36:07.737] <TB2> INFO: valid events with pixels: 0
[17:36:07.737] <TB2> INFO: valid pixel hits: 0
[17:36:07.737] <TB2> INFO: Event errors: 0
[17:36:07.737] <TB2> INFO: start marker: 0
[17:36:07.737] <TB2> INFO: stop marker: 0
[17:36:07.737] <TB2> INFO: overflow: 0
[17:36:07.737] <TB2> INFO: invalid 5bit words: 0
[17:36:07.737] <TB2> INFO: invalid XOR eye diagram: 0
[17:36:07.737] <TB2> INFO: frame (failed synchr.): 0
[17:36:07.738] <TB2> INFO: idle data (no TBM trl): 0
[17:36:07.738] <TB2> INFO: no data (only TBM hdr): 0
[17:36:07.738] <TB2> INFO: TBM errors: 0
[17:36:07.738] <TB2> INFO: flawed TBM headers: 0
[17:36:07.738] <TB2> INFO: flawed TBM trailers: 0
[17:36:07.738] <TB2> INFO: event ID mismatches: 0
[17:36:07.738] <TB2> INFO: ROC errors: 0
[17:36:07.738] <TB2> INFO: missing ROC header(s): 0
[17:36:07.738] <TB2> INFO: misplaced readback start: 0
[17:36:07.738] <TB2> INFO: Pixel decoding errors: 0
[17:36:07.738] <TB2> INFO: pixel data incomplete: 0
[17:36:07.738] <TB2> INFO: pixel address: 0
[17:36:07.738] <TB2> INFO: pulse height fill bit: 0
[17:36:07.738] <TB2> INFO: buffer corruption: 0
[17:36:07.742] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C15.dat
[17:36:07.743] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr_C15.dat

[17:36:07.743] <TB2> INFO: ######################################################################
[17:36:07.743] <TB2> INFO: PixTestReadback::doTest()
[17:36:07.743] <TB2> INFO: ######################################################################
[17:36:07.743] <TB2> INFO: ----------------------------------------------------------------------
[17:36:07.743] <TB2> INFO: PixTestReadback::CalibrateVd()
[17:36:07.743] <TB2> INFO: ----------------------------------------------------------------------
[17:36:17.719] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C0.dat
[17:36:17.719] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C1.dat
[17:36:17.719] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C2.dat
[17:36:17.719] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C3.dat
[17:36:17.720] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C4.dat
[17:36:17.720] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C5.dat
[17:36:17.720] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C6.dat
[17:36:17.720] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C7.dat
[17:36:17.720] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C8.dat
[17:36:17.720] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C9.dat
[17:36:17.720] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C10.dat
[17:36:17.720] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C11.dat
[17:36:17.720] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C12.dat
[17:36:17.721] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C13.dat
[17:36:17.721] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C14.dat
[17:36:17.721] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C15.dat
[17:36:17.753] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[17:36:17.753] <TB2> INFO: ----------------------------------------------------------------------
[17:36:17.753] <TB2> INFO: PixTestReadback::CalibrateVa()
[17:36:17.753] <TB2> INFO: ----------------------------------------------------------------------
[17:36:27.684] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C0.dat
[17:36:27.684] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C1.dat
[17:36:27.684] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C2.dat
[17:36:27.684] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C3.dat
[17:36:27.684] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C4.dat
[17:36:27.684] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C5.dat
[17:36:27.684] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C6.dat
[17:36:27.684] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C7.dat
[17:36:27.684] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C8.dat
[17:36:27.684] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C9.dat
[17:36:27.684] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C10.dat
[17:36:27.684] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C11.dat
[17:36:27.685] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C12.dat
[17:36:27.685] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C13.dat
[17:36:27.685] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C14.dat
[17:36:27.685] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C15.dat
[17:36:27.714] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[17:36:27.714] <TB2> INFO: ----------------------------------------------------------------------
[17:36:27.714] <TB2> INFO: PixTestReadback::readbackVbg()
[17:36:27.714] <TB2> INFO: ----------------------------------------------------------------------
[17:36:35.384] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[17:36:35.384] <TB2> INFO: ----------------------------------------------------------------------
[17:36:35.384] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[17:36:35.384] <TB2> INFO: ----------------------------------------------------------------------
[17:36:35.385] <TB2> INFO: Vbg will be calibrated using Vd calibration
[17:36:35.385] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 155.8calibrated Vbg = 1.19425 :::*/*/*/*/
[17:36:35.385] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 155.7calibrated Vbg = 1.19884 :::*/*/*/*/
[17:36:35.385] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 150.8calibrated Vbg = 1.19531 :::*/*/*/*/
[17:36:35.385] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 145.7calibrated Vbg = 1.19014 :::*/*/*/*/
[17:36:35.385] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 158.8calibrated Vbg = 1.20032 :::*/*/*/*/
[17:36:35.385] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 155.7calibrated Vbg = 1.1965 :::*/*/*/*/
[17:36:35.385] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 165.8calibrated Vbg = 1.19399 :::*/*/*/*/
[17:36:35.385] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 153.3calibrated Vbg = 1.19985 :::*/*/*/*/
[17:36:35.385] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 159calibrated Vbg = 1.19032 :::*/*/*/*/
[17:36:35.385] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 158.6calibrated Vbg = 1.19509 :::*/*/*/*/
[17:36:35.385] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 159.2calibrated Vbg = 1.18828 :::*/*/*/*/
[17:36:35.385] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 157.6calibrated Vbg = 1.18246 :::*/*/*/*/
[17:36:35.385] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 158.9calibrated Vbg = 1.18482 :::*/*/*/*/
[17:36:35.385] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 162calibrated Vbg = 1.19434 :::*/*/*/*/
[17:36:35.385] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 155.1calibrated Vbg = 1.19526 :::*/*/*/*/
[17:36:35.385] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 157.4calibrated Vbg = 1.18781 :::*/*/*/*/
[17:36:35.388] <TB2> INFO: ----------------------------------------------------------------------
[17:36:35.388] <TB2> INFO: PixTestReadback::CalibrateIa()
[17:36:35.388] <TB2> INFO: ----------------------------------------------------------------------
[17:39:16.209] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C0.dat
[17:39:16.209] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C1.dat
[17:39:16.209] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C2.dat
[17:39:16.209] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C3.dat
[17:39:16.209] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C4.dat
[17:39:16.209] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C5.dat
[17:39:16.209] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C6.dat
[17:39:16.209] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C7.dat
[17:39:16.209] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C8.dat
[17:39:16.209] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C9.dat
[17:39:16.209] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C10.dat
[17:39:16.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C11.dat
[17:39:16.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C12.dat
[17:39:16.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C13.dat
[17:39:16.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C14.dat
[17:39:16.210] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//readbackCal_C15.dat
[17:39:16.237] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[17:39:16.238] <TB2> INFO: PixTestReadback::doTest() done
[17:39:16.239] <TB2> INFO: Decoding statistics:
[17:39:16.239] <TB2> INFO: General information:
[17:39:16.239] <TB2> INFO: 16bit words read: 1536
[17:39:16.239] <TB2> INFO: valid events total: 256
[17:39:16.239] <TB2> INFO: empty events: 256
[17:39:16.239] <TB2> INFO: valid events with pixels: 0
[17:39:16.239] <TB2> INFO: valid pixel hits: 0
[17:39:16.239] <TB2> INFO: Event errors: 0
[17:39:16.239] <TB2> INFO: start marker: 0
[17:39:16.239] <TB2> INFO: stop marker: 0
[17:39:16.239] <TB2> INFO: overflow: 0
[17:39:16.239] <TB2> INFO: invalid 5bit words: 0
[17:39:16.239] <TB2> INFO: invalid XOR eye diagram: 0
[17:39:16.239] <TB2> INFO: frame (failed synchr.): 0
[17:39:16.239] <TB2> INFO: idle data (no TBM trl): 0
[17:39:16.239] <TB2> INFO: no data (only TBM hdr): 0
[17:39:16.239] <TB2> INFO: TBM errors: 0
[17:39:16.239] <TB2> INFO: flawed TBM headers: 0
[17:39:16.239] <TB2> INFO: flawed TBM trailers: 0
[17:39:16.239] <TB2> INFO: event ID mismatches: 0
[17:39:16.239] <TB2> INFO: ROC errors: 0
[17:39:16.239] <TB2> INFO: missing ROC header(s): 0
[17:39:16.239] <TB2> INFO: misplaced readback start: 0
[17:39:16.239] <TB2> INFO: Pixel decoding errors: 0
[17:39:16.239] <TB2> INFO: pixel data incomplete: 0
[17:39:16.239] <TB2> INFO: pixel address: 0
[17:39:16.239] <TB2> INFO: pulse height fill bit: 0
[17:39:16.239] <TB2> INFO: buffer corruption: 0
[17:39:16.303] <TB2> INFO: ######################################################################
[17:39:16.303] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[17:39:16.303] <TB2> INFO: ######################################################################
[17:39:16.305] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[17:39:16.322] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:39:16.322] <TB2> INFO: run 1 of 1
[17:39:16.558] <TB2> INFO: Expecting 3120000 events.
[17:39:47.433] <TB2> INFO: 677995 events read in total (30282ms).











[17:40:17.831] <TB2> INFO: 1352005 events read in total (60680ms).











[17:40:48.298] <TB2> INFO: 2022420 events read in total (91148ms).











[17:41:18.876] <TB2> INFO: 2694780 events read in total (121725ms).











[17:41:38.618] <TB2> INFO: 3120000 events read in total (141467ms).
[17:41:38.697] <TB2> INFO: Test took 142376ms.
[17:42:04.509] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 168 seconds
[17:42:04.509] <TB2> INFO: number of dead bumps (per ROC): 1 0 1 0 0 1 0 3 0 2 0 1 0 1 2 2
[17:42:04.509] <TB2> INFO: separation cut (per ROC): 103 108 106 109 103 105 127 108 125 103 107 102 100 110 104 109
[17:42:04.509] <TB2> INFO: Decoding statistics:
[17:42:04.509] <TB2> INFO: General information:
[17:42:04.509] <TB2> INFO: 16bit words read: 0
[17:42:04.509] <TB2> INFO: valid events total: 0
[17:42:04.509] <TB2> INFO: empty events: 0
[17:42:04.509] <TB2> INFO: valid events with pixels: 0
[17:42:04.509] <TB2> INFO: valid pixel hits: 0
[17:42:04.509] <TB2> INFO: Event errors: 0
[17:42:04.509] <TB2> INFO: start marker: 0
[17:42:04.509] <TB2> INFO: stop marker: 0
[17:42:04.509] <TB2> INFO: overflow: 0
[17:42:04.509] <TB2> INFO: invalid 5bit words: 0
[17:42:04.509] <TB2> INFO: invalid XOR eye diagram: 0
[17:42:04.509] <TB2> INFO: frame (failed synchr.): 0
[17:42:04.509] <TB2> INFO: idle data (no TBM trl): 0
[17:42:04.509] <TB2> INFO: no data (only TBM hdr): 0
[17:42:04.509] <TB2> INFO: TBM errors: 0
[17:42:04.509] <TB2> INFO: flawed TBM headers: 0
[17:42:04.509] <TB2> INFO: flawed TBM trailers: 0
[17:42:04.509] <TB2> INFO: event ID mismatches: 0
[17:42:04.509] <TB2> INFO: ROC errors: 0
[17:42:04.509] <TB2> INFO: missing ROC header(s): 0
[17:42:04.509] <TB2> INFO: misplaced readback start: 0
[17:42:04.509] <TB2> INFO: Pixel decoding errors: 0
[17:42:04.509] <TB2> INFO: pixel data incomplete: 0
[17:42:04.510] <TB2> INFO: pixel address: 0
[17:42:04.510] <TB2> INFO: pulse height fill bit: 0
[17:42:04.510] <TB2> INFO: buffer corruption: 0
[17:42:04.552] <TB2> INFO: ######################################################################
[17:42:04.552] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[17:42:04.552] <TB2> INFO: ######################################################################
[17:42:04.552] <TB2> INFO: ----------------------------------------------------------------------
[17:42:04.552] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[17:42:04.552] <TB2> INFO: ----------------------------------------------------------------------
[17:42:04.552] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[17:42:04.568] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[17:42:04.568] <TB2> INFO: run 1 of 1
[17:42:04.815] <TB2> INFO: Expecting 36608000 events.
[17:42:28.254] <TB2> INFO: 692650 events read in total (22848ms).
[17:42:50.967] <TB2> INFO: 1369500 events read in total (45561ms).
[17:43:13.983] <TB2> INFO: 2043700 events read in total (68577ms).
[17:43:36.497] <TB2> INFO: 2718050 events read in total (91091ms).
[17:43:59.368] <TB2> INFO: 3393600 events read in total (113962ms).
[17:44:22.347] <TB2> INFO: 4071000 events read in total (136941ms).
[17:44:45.039] <TB2> INFO: 4747800 events read in total (159633ms).
[17:45:07.972] <TB2> INFO: 5424350 events read in total (182566ms).
[17:45:30.661] <TB2> INFO: 6099300 events read in total (205255ms).
[17:45:53.400] <TB2> INFO: 6773250 events read in total (227994ms).
[17:46:16.042] <TB2> INFO: 7447850 events read in total (250636ms).
[17:46:38.674] <TB2> INFO: 8120450 events read in total (273268ms).
[17:47:01.346] <TB2> INFO: 8794900 events read in total (295940ms).
[17:47:23.854] <TB2> INFO: 9467900 events read in total (318448ms).
[17:47:46.471] <TB2> INFO: 10142550 events read in total (341065ms).
[17:48:09.208] <TB2> INFO: 10814500 events read in total (363802ms).
[17:48:32.044] <TB2> INFO: 11487250 events read in total (386638ms).
[17:48:54.808] <TB2> INFO: 12158400 events read in total (409402ms).
[17:49:17.769] <TB2> INFO: 12827450 events read in total (432363ms).
[17:49:40.630] <TB2> INFO: 13497900 events read in total (455224ms).
[17:50:03.694] <TB2> INFO: 14167950 events read in total (478288ms).
[17:50:26.630] <TB2> INFO: 14840600 events read in total (501224ms).
[17:50:49.778] <TB2> INFO: 15511050 events read in total (524372ms).
[17:51:12.350] <TB2> INFO: 16181150 events read in total (546944ms).
[17:51:34.882] <TB2> INFO: 16852150 events read in total (569476ms).
[17:51:57.540] <TB2> INFO: 17524750 events read in total (592134ms).
[17:52:20.504] <TB2> INFO: 18194400 events read in total (615098ms).
[17:52:43.173] <TB2> INFO: 18863850 events read in total (637767ms).
[17:53:05.995] <TB2> INFO: 19532300 events read in total (660589ms).
[17:53:28.947] <TB2> INFO: 20197850 events read in total (683541ms).
[17:53:51.707] <TB2> INFO: 20864100 events read in total (706301ms).
[17:54:14.740] <TB2> INFO: 21530100 events read in total (729334ms).
[17:54:38.041] <TB2> INFO: 22196250 events read in total (752636ms).
[17:55:00.905] <TB2> INFO: 22861500 events read in total (775499ms).
[17:55:23.670] <TB2> INFO: 23528000 events read in total (798264ms).
[17:55:46.596] <TB2> INFO: 24193900 events read in total (821190ms).
[17:56:09.254] <TB2> INFO: 24859300 events read in total (843848ms).
[17:56:32.044] <TB2> INFO: 25525450 events read in total (866638ms).
[17:56:54.968] <TB2> INFO: 26191100 events read in total (889562ms).
[17:57:17.768] <TB2> INFO: 26855100 events read in total (912362ms).
[17:57:40.525] <TB2> INFO: 27520050 events read in total (935119ms).
[17:58:03.042] <TB2> INFO: 28183950 events read in total (957636ms).
[17:58:25.833] <TB2> INFO: 28846300 events read in total (980427ms).
[17:58:48.420] <TB2> INFO: 29511950 events read in total (1003014ms).
[17:59:11.207] <TB2> INFO: 30173300 events read in total (1025801ms).
[17:59:34.137] <TB2> INFO: 30835700 events read in total (1048731ms).
[17:59:57.451] <TB2> INFO: 31502250 events read in total (1072045ms).
[18:00:20.169] <TB2> INFO: 32169150 events read in total (1094763ms).
[18:00:43.111] <TB2> INFO: 32834350 events read in total (1117705ms).
[18:01:05.864] <TB2> INFO: 33499900 events read in total (1140458ms).
[18:01:28.551] <TB2> INFO: 34166150 events read in total (1163145ms).
[18:01:51.277] <TB2> INFO: 34834800 events read in total (1185871ms).
[18:02:14.324] <TB2> INFO: 35503450 events read in total (1208918ms).
[18:02:37.217] <TB2> INFO: 36176300 events read in total (1231811ms).
[18:02:51.693] <TB2> INFO: 36608000 events read in total (1246287ms).
[18:02:51.765] <TB2> INFO: Test took 1247197ms.
[18:02:52.206] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:02:53.692] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:02:55.287] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:02:56.762] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:02:58.261] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:02:59.812] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:03:01.308] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:03:02.802] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:03:04.300] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:03:05.783] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:03:07.238] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:03:08.700] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:03:10.179] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:03:11.662] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:03:13.206] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:03:14.766] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[18:03:16.333] <TB2> INFO: PixTestScurves::scurves() done
[18:03:16.333] <TB2> INFO: Vcal mean: 124.75 123.64 120.68 109.61 122.22 125.57 140.84 125.35 134.73 118.20 122.90 116.48 118.74 131.69 122.51 128.75
[18:03:16.333] <TB2> INFO: Vcal RMS: 6.52 6.02 5.94 5.61 6.39 5.55 6.44 6.73 6.55 5.91 6.72 5.44 5.55 6.60 6.76 5.85
[18:03:16.333] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1271 seconds
[18:03:16.333] <TB2> INFO: Decoding statistics:
[18:03:16.333] <TB2> INFO: General information:
[18:03:16.333] <TB2> INFO: 16bit words read: 0
[18:03:16.333] <TB2> INFO: valid events total: 0
[18:03:16.333] <TB2> INFO: empty events: 0
[18:03:16.333] <TB2> INFO: valid events with pixels: 0
[18:03:16.333] <TB2> INFO: valid pixel hits: 0
[18:03:16.333] <TB2> INFO: Event errors: 0
[18:03:16.333] <TB2> INFO: start marker: 0
[18:03:16.333] <TB2> INFO: stop marker: 0
[18:03:16.333] <TB2> INFO: overflow: 0
[18:03:16.333] <TB2> INFO: invalid 5bit words: 0
[18:03:16.333] <TB2> INFO: invalid XOR eye diagram: 0
[18:03:16.333] <TB2> INFO: frame (failed synchr.): 0
[18:03:16.333] <TB2> INFO: idle data (no TBM trl): 0
[18:03:16.333] <TB2> INFO: no data (only TBM hdr): 0
[18:03:16.334] <TB2> INFO: TBM errors: 0
[18:03:16.334] <TB2> INFO: flawed TBM headers: 0
[18:03:16.334] <TB2> INFO: flawed TBM trailers: 0
[18:03:16.334] <TB2> INFO: event ID mismatches: 0
[18:03:16.334] <TB2> INFO: ROC errors: 0
[18:03:16.334] <TB2> INFO: missing ROC header(s): 0
[18:03:16.334] <TB2> INFO: misplaced readback start: 0
[18:03:16.334] <TB2> INFO: Pixel decoding errors: 0
[18:03:16.334] <TB2> INFO: pixel data incomplete: 0
[18:03:16.334] <TB2> INFO: pixel address: 0
[18:03:16.334] <TB2> INFO: pulse height fill bit: 0
[18:03:16.334] <TB2> INFO: buffer corruption: 0
[18:03:16.403] <TB2> INFO: ######################################################################
[18:03:16.403] <TB2> INFO: PixTestTrim::doTest()
[18:03:16.403] <TB2> INFO: ######################################################################
[18:03:16.404] <TB2> INFO: ----------------------------------------------------------------------
[18:03:16.404] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[18:03:16.404] <TB2> INFO: ----------------------------------------------------------------------
[18:03:16.446] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[18:03:16.447] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[18:03:16.460] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:03:16.460] <TB2> INFO: run 1 of 1
[18:03:16.699] <TB2> INFO: Expecting 5025280 events.
[18:03:48.265] <TB2> INFO: 829744 events read in total (30969ms).
[18:04:18.460] <TB2> INFO: 1655952 events read in total (61164ms).
[18:04:48.719] <TB2> INFO: 2479800 events read in total (91424ms).
[18:05:19.079] <TB2> INFO: 3300032 events read in total (121783ms).
[18:05:49.201] <TB2> INFO: 4116400 events read in total (151906ms).
[18:06:19.160] <TB2> INFO: 4932656 events read in total (181864ms).
[18:06:22.971] <TB2> INFO: 5025280 events read in total (185675ms).
[18:06:23.024] <TB2> INFO: Test took 186563ms.
[18:06:41.269] <TB2> INFO: ROC 0 VthrComp = 115
[18:06:41.269] <TB2> INFO: ROC 1 VthrComp = 122
[18:06:41.269] <TB2> INFO: ROC 2 VthrComp = 117
[18:06:41.269] <TB2> INFO: ROC 3 VthrComp = 113
[18:06:41.269] <TB2> INFO: ROC 4 VthrComp = 114
[18:06:41.269] <TB2> INFO: ROC 5 VthrComp = 126
[18:06:41.269] <TB2> INFO: ROC 6 VthrComp = 138
[18:06:41.269] <TB2> INFO: ROC 7 VthrComp = 123
[18:06:41.269] <TB2> INFO: ROC 8 VthrComp = 131
[18:06:41.270] <TB2> INFO: ROC 9 VthrComp = 111
[18:06:41.270] <TB2> INFO: ROC 10 VthrComp = 120
[18:06:41.270] <TB2> INFO: ROC 11 VthrComp = 117
[18:06:41.270] <TB2> INFO: ROC 12 VthrComp = 117
[18:06:41.270] <TB2> INFO: ROC 13 VthrComp = 129
[18:06:41.270] <TB2> INFO: ROC 14 VthrComp = 115
[18:06:41.271] <TB2> INFO: ROC 15 VthrComp = 128
[18:06:41.509] <TB2> INFO: Expecting 41600 events.
[18:06:45.161] <TB2> INFO: 41600 events read in total (3061ms).
[18:06:45.162] <TB2> INFO: Test took 3889ms.
[18:06:45.172] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[18:06:45.172] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[18:06:45.184] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:06:45.184] <TB2> INFO: run 1 of 1
[18:06:45.462] <TB2> INFO: Expecting 5025280 events.
[18:07:12.317] <TB2> INFO: 591864 events read in total (26263ms).
[18:07:37.990] <TB2> INFO: 1183936 events read in total (51936ms).
[18:08:03.970] <TB2> INFO: 1775624 events read in total (77916ms).
[18:08:29.811] <TB2> INFO: 2366568 events read in total (103757ms).
[18:08:55.568] <TB2> INFO: 2955776 events read in total (129514ms).
[18:09:21.274] <TB2> INFO: 3543368 events read in total (155220ms).
[18:09:47.227] <TB2> INFO: 4129656 events read in total (181173ms).
[18:10:12.989] <TB2> INFO: 4714776 events read in total (206935ms).
[18:10:27.059] <TB2> INFO: 5025280 events read in total (221005ms).
[18:10:27.137] <TB2> INFO: Test took 221953ms.
[18:10:51.429] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 62.3652 for pixel 15/3 mean/min/max = 47.4314/32.4587/62.4041
[18:10:51.430] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 60.7679 for pixel 4/12 mean/min/max = 46.6105/32.3272/60.8939
[18:10:51.431] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 60.6055 for pixel 26/72 mean/min/max = 46.9194/33.182/60.6568
[18:10:51.431] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 61.3817 for pixel 0/79 mean/min/max = 46.6693/31.9451/61.3935
[18:10:51.432] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 63.2203 for pixel 13/69 mean/min/max = 47.6952/32.1374/63.2531
[18:10:51.433] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 60.2233 for pixel 2/67 mean/min/max = 46.0037/31.6915/60.3159
[18:10:51.433] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 68.8216 for pixel 0/8 mean/min/max = 51.903/34.9769/68.8292
[18:10:51.434] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 64.669 for pixel 1/0 mean/min/max = 47.8523/31.0187/64.6858
[18:10:51.434] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 64.414 for pixel 3/46 mean/min/max = 49.5056/34.0557/64.9554
[18:10:51.435] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 65.7851 for pixel 0/8 mean/min/max = 50.1491/34.4652/65.8331
[18:10:51.436] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 64.2834 for pixel 12/0 mean/min/max = 47.8191/31.2025/64.4358
[18:10:51.436] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 60.3034 for pixel 16/24 mean/min/max = 46.3384/32.2815/60.3952
[18:10:51.437] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 59.184 for pixel 24/49 mean/min/max = 45.9273/32.2502/59.6044
[18:10:51.438] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 62.9529 for pixel 5/5 mean/min/max = 47.804/32.5096/63.0984
[18:10:51.438] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 62.8666 for pixel 15/4 mean/min/max = 47.3365/31.5842/63.0889
[18:10:51.439] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 60.0024 for pixel 5/13 mean/min/max = 45.7718/31.2772/60.2663
[18:10:51.441] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:10:51.530] <TB2> INFO: Expecting 411648 events.
[18:11:01.057] <TB2> INFO: 411648 events read in total (8935ms).
[18:11:01.064] <TB2> INFO: Expecting 411648 events.
[18:11:10.239] <TB2> INFO: 411648 events read in total (8772ms).
[18:11:10.249] <TB2> INFO: Expecting 411648 events.
[18:11:19.567] <TB2> INFO: 411648 events read in total (8915ms).
[18:11:19.582] <TB2> INFO: Expecting 411648 events.
[18:11:28.921] <TB2> INFO: 411648 events read in total (8936ms).
[18:11:28.941] <TB2> INFO: Expecting 411648 events.
[18:11:38.264] <TB2> INFO: 411648 events read in total (8920ms).
[18:11:38.282] <TB2> INFO: Expecting 411648 events.
[18:11:47.503] <TB2> INFO: 411648 events read in total (8817ms).
[18:11:47.529] <TB2> INFO: Expecting 411648 events.
[18:11:56.849] <TB2> INFO: 411648 events read in total (8917ms).
[18:11:56.873] <TB2> INFO: Expecting 411648 events.
[18:12:06.121] <TB2> INFO: 411648 events read in total (8845ms).
[18:12:06.147] <TB2> INFO: Expecting 411648 events.
[18:12:15.496] <TB2> INFO: 411648 events read in total (8946ms).
[18:12:15.525] <TB2> INFO: Expecting 411648 events.
[18:12:24.849] <TB2> INFO: 411648 events read in total (8921ms).
[18:12:24.889] <TB2> INFO: Expecting 411648 events.
[18:12:34.128] <TB2> INFO: 411648 events read in total (8836ms).
[18:12:34.172] <TB2> INFO: Expecting 411648 events.
[18:12:43.488] <TB2> INFO: 411648 events read in total (8913ms).
[18:12:43.536] <TB2> INFO: Expecting 411648 events.
[18:12:52.837] <TB2> INFO: 411648 events read in total (8896ms).
[18:12:52.879] <TB2> INFO: Expecting 411648 events.
[18:13:02.179] <TB2> INFO: 411648 events read in total (8896ms).
[18:13:02.255] <TB2> INFO: Expecting 411648 events.
[18:13:11.521] <TB2> INFO: 411648 events read in total (8863ms).
[18:13:11.570] <TB2> INFO: Expecting 411648 events.
[18:13:20.726] <TB2> INFO: 411648 events read in total (8753ms).
[18:13:20.788] <TB2> INFO: Test took 149347ms.
[18:13:21.399] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[18:13:21.412] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:13:21.412] <TB2> INFO: run 1 of 1
[18:13:21.651] <TB2> INFO: Expecting 5025280 events.
[18:13:48.079] <TB2> INFO: 590032 events read in total (25836ms).
[18:14:13.962] <TB2> INFO: 1181288 events read in total (51720ms).
[18:14:40.480] <TB2> INFO: 1771248 events read in total (78237ms).
[18:15:06.712] <TB2> INFO: 2359632 events read in total (104469ms).
[18:15:32.960] <TB2> INFO: 2949368 events read in total (130717ms).
[18:15:59.175] <TB2> INFO: 3540272 events read in total (156932ms).
[18:16:25.468] <TB2> INFO: 4130000 events read in total (183225ms).
[18:16:51.136] <TB2> INFO: 4718944 events read in total (208893ms).
[18:17:05.924] <TB2> INFO: 5025280 events read in total (223682ms).
[18:17:06.099] <TB2> INFO: Test took 224688ms.
[18:17:31.194] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 2.500000 .. 147.515726
[18:17:31.456] <TB2> INFO: Expecting 208000 events.
[18:17:41.380] <TB2> INFO: 208000 events read in total (9332ms).
[18:17:41.381] <TB2> INFO: Test took 10185ms.
[18:17:41.431] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 157 (-1/-1) hits flags = 528 (plus default)
[18:17:41.448] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:17:41.448] <TB2> INFO: run 1 of 1
[18:17:41.726] <TB2> INFO: Expecting 5191680 events.
[18:18:08.018] <TB2> INFO: 583392 events read in total (25700ms).
[18:18:33.687] <TB2> INFO: 1166632 events read in total (51369ms).
[18:18:59.639] <TB2> INFO: 1749568 events read in total (77321ms).
[18:19:25.414] <TB2> INFO: 2332760 events read in total (103096ms).
[18:19:51.084] <TB2> INFO: 2915952 events read in total (128767ms).
[18:20:16.865] <TB2> INFO: 3498944 events read in total (154547ms).
[18:20:42.622] <TB2> INFO: 4081808 events read in total (180304ms).
[18:21:08.385] <TB2> INFO: 4664240 events read in total (206067ms).
[18:21:31.789] <TB2> INFO: 5191680 events read in total (229472ms).
[18:21:31.934] <TB2> INFO: Test took 230486ms.
[18:21:58.479] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.284409 .. 48.926452
[18:21:58.728] <TB2> INFO: Expecting 208000 events.
[18:22:08.500] <TB2> INFO: 208000 events read in total (9180ms).
[18:22:08.502] <TB2> INFO: Test took 10021ms.
[18:22:08.582] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 58 (-1/-1) hits flags = 528 (plus default)
[18:22:08.596] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:22:08.596] <TB2> INFO: run 1 of 1
[18:22:08.920] <TB2> INFO: Expecting 1397760 events.
[18:22:36.727] <TB2> INFO: 652624 events read in total (27215ms).
[18:23:03.868] <TB2> INFO: 1304296 events read in total (54356ms).
[18:23:08.156] <TB2> INFO: 1397760 events read in total (58644ms).
[18:23:08.196] <TB2> INFO: Test took 59601ms.
[18:23:23.103] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 28.010804 .. 49.426927
[18:23:23.345] <TB2> INFO: Expecting 208000 events.
[18:23:32.992] <TB2> INFO: 208000 events read in total (9055ms).
[18:23:32.993] <TB2> INFO: Test took 9887ms.
[18:23:33.056] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 18 .. 59 (-1/-1) hits flags = 528 (plus default)
[18:23:33.069] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:23:33.069] <TB2> INFO: run 1 of 1
[18:23:33.347] <TB2> INFO: Expecting 1397760 events.
[18:24:01.451] <TB2> INFO: 644368 events read in total (27512ms).
[18:24:28.556] <TB2> INFO: 1286656 events read in total (54617ms).
[18:24:33.587] <TB2> INFO: 1397760 events read in total (59648ms).
[18:24:33.626] <TB2> INFO: Test took 60558ms.
[18:24:48.631] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 25.936677 .. 52.626906
[18:24:48.956] <TB2> INFO: Expecting 208000 events.
[18:24:58.865] <TB2> INFO: 208000 events read in total (9317ms).
[18:24:58.867] <TB2> INFO: Test took 10234ms.
[18:24:58.948] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 62 (-1/-1) hits flags = 528 (plus default)
[18:24:58.963] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:24:58.963] <TB2> INFO: run 1 of 1
[18:24:59.275] <TB2> INFO: Expecting 1597440 events.
[18:25:26.727] <TB2> INFO: 645008 events read in total (26860ms).
[18:25:54.467] <TB2> INFO: 1288976 events read in total (54600ms).
[18:26:07.512] <TB2> INFO: 1597440 events read in total (67645ms).
[18:26:07.551] <TB2> INFO: Test took 68588ms.
[18:26:23.293] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[18:26:23.293] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[18:26:23.308] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[18:26:23.308] <TB2> INFO: run 1 of 1
[18:26:23.587] <TB2> INFO: Expecting 1364480 events.
[18:26:52.233] <TB2> INFO: 669976 events read in total (28055ms).
[18:27:20.109] <TB2> INFO: 1338448 events read in total (55931ms).
[18:27:21.680] <TB2> INFO: 1364480 events read in total (57503ms).
[18:27:21.713] <TB2> INFO: Test took 58405ms.
[18:27:37.028] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C0.dat
[18:27:37.028] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C1.dat
[18:27:37.028] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C2.dat
[18:27:37.028] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C3.dat
[18:27:37.028] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C4.dat
[18:27:37.028] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C5.dat
[18:27:37.028] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C6.dat
[18:27:37.028] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C7.dat
[18:27:37.028] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C8.dat
[18:27:37.028] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C9.dat
[18:27:37.029] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C10.dat
[18:27:37.029] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C11.dat
[18:27:37.029] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C12.dat
[18:27:37.029] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C13.dat
[18:27:37.029] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C14.dat
[18:27:37.029] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C15.dat
[18:27:37.029] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters35_C0.dat
[18:27:37.038] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters35_C1.dat
[18:27:37.045] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters35_C2.dat
[18:27:37.053] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters35_C3.dat
[18:27:37.060] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters35_C4.dat
[18:27:37.068] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters35_C5.dat
[18:27:37.075] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters35_C6.dat
[18:27:37.081] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters35_C7.dat
[18:27:37.086] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters35_C8.dat
[18:27:37.091] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters35_C9.dat
[18:27:37.095] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters35_C10.dat
[18:27:37.100] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters35_C11.dat
[18:27:37.105] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters35_C12.dat
[18:27:37.112] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters35_C13.dat
[18:27:37.119] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters35_C14.dat
[18:27:37.124] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//trimParameters35_C15.dat
[18:27:37.129] <TB2> INFO: PixTestTrim::trimTest() done
[18:27:37.129] <TB2> INFO: vtrim: 131 123 121 118 130 118 146 135 137 129 141 142 122 126 136 121
[18:27:37.129] <TB2> INFO: vthrcomp: 115 122 117 113 114 126 138 123 131 111 120 117 117 129 115 128
[18:27:37.129] <TB2> INFO: vcal mean: 35.22 35.22 35.18 35.07 35.33 35.11 35.32 35.84 35.15 35.28 35.23 35.06 35.06 35.31 35.30 35.07
[18:27:37.129] <TB2> INFO: vcal RMS: 1.23 1.14 1.31 0.99 1.34 1.18 1.43 2.03 1.15 1.39 1.38 1.07 1.14 1.43 1.44 1.27
[18:27:37.129] <TB2> INFO: bits mean: 9.28 9.17 9.39 8.53 9.52 9.34 7.77 9.69 8.57 8.29 9.46 9.61 9.55 9.32 9.74 9.77
[18:27:37.129] <TB2> INFO: bits RMS: 2.69 2.79 2.66 3.09 2.61 2.84 2.75 2.79 2.59 2.75 2.70 2.63 2.67 2.71 2.64 2.74
[18:27:37.137] <TB2> INFO: ----------------------------------------------------------------------
[18:27:37.137] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[18:27:37.137] <TB2> INFO: ----------------------------------------------------------------------
[18:27:37.139] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[18:27:37.154] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[18:27:37.154] <TB2> INFO: run 1 of 1
[18:27:37.393] <TB2> INFO: Expecting 4160000 events.
[18:28:10.423] <TB2> INFO: 763510 events read in total (32438ms).
[18:28:42.495] <TB2> INFO: 1519340 events read in total (64510ms).
[18:29:14.413] <TB2> INFO: 2272200 events read in total (96428ms).
[18:29:45.997] <TB2> INFO: 3019855 events read in total (128012ms).
[18:30:17.699] <TB2> INFO: 3766265 events read in total (159714ms).
[18:30:34.762] <TB2> INFO: 4160000 events read in total (176777ms).
[18:30:34.837] <TB2> INFO: Test took 177683ms.
[18:31:03.306] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 225 (-1/-1) hits flags = 528 (plus default)
[18:31:03.319] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[18:31:03.319] <TB2> INFO: run 1 of 1
[18:31:03.554] <TB2> INFO: Expecting 4700800 events.
[18:31:35.247] <TB2> INFO: 707595 events read in total (31101ms).
[18:32:06.112] <TB2> INFO: 1410530 events read in total (61966ms).
[18:32:36.947] <TB2> INFO: 2110575 events read in total (92801ms).
[18:33:07.572] <TB2> INFO: 2808715 events read in total (123426ms).
[18:33:38.241] <TB2> INFO: 3503790 events read in total (154095ms).
[18:34:08.773] <TB2> INFO: 4197890 events read in total (184627ms).
[18:34:31.269] <TB2> INFO: 4700800 events read in total (207123ms).
[18:34:31.375] <TB2> INFO: Test took 208055ms.
[18:34:59.968] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 216 (-1/-1) hits flags = 528 (plus default)
[18:34:59.982] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[18:34:59.982] <TB2> INFO: run 1 of 1
[18:35:00.259] <TB2> INFO: Expecting 4513600 events.
[18:35:31.820] <TB2> INFO: 717825 events read in total (30969ms).
[18:36:02.593] <TB2> INFO: 1430310 events read in total (61742ms).
[18:36:33.657] <TB2> INFO: 2139915 events read in total (92806ms).
[18:37:04.646] <TB2> INFO: 2845970 events read in total (123795ms).
[18:37:35.295] <TB2> INFO: 3549680 events read in total (154444ms).
[18:38:05.827] <TB2> INFO: 4253960 events read in total (184976ms).
[18:38:17.241] <TB2> INFO: 4513600 events read in total (196390ms).
[18:38:17.332] <TB2> INFO: Test took 197349ms.
[18:38:47.490] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 217 (-1/-1) hits flags = 528 (plus default)
[18:38:47.504] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[18:38:47.504] <TB2> INFO: run 1 of 1
[18:38:47.743] <TB2> INFO: Expecting 4534400 events.
[18:39:20.657] <TB2> INFO: 716810 events read in total (32323ms).
[18:39:51.735] <TB2> INFO: 1427720 events read in total (63402ms).
[18:40:22.651] <TB2> INFO: 2136605 events read in total (94317ms).
[18:40:53.582] <TB2> INFO: 2841945 events read in total (125248ms).
[18:41:24.731] <TB2> INFO: 3545380 events read in total (156397ms).
[18:41:55.400] <TB2> INFO: 4248615 events read in total (187066ms).
[18:42:07.953] <TB2> INFO: 4534400 events read in total (199619ms).
[18:42:08.037] <TB2> INFO: Test took 200534ms.
[18:42:35.896] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 218 (-1/-1) hits flags = 528 (plus default)
[18:42:35.910] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[18:42:35.910] <TB2> INFO: run 1 of 1
[18:42:36.145] <TB2> INFO: Expecting 4555200 events.
[18:43:07.996] <TB2> INFO: 716585 events read in total (31260ms).
[18:43:38.895] <TB2> INFO: 1427365 events read in total (62158ms).
[18:44:09.728] <TB2> INFO: 2135175 events read in total (92991ms).
[18:44:40.200] <TB2> INFO: 2840415 events read in total (123463ms).
[18:45:11.028] <TB2> INFO: 3542870 events read in total (154291ms).
[18:45:41.437] <TB2> INFO: 4244820 events read in total (184700ms).
[18:45:55.413] <TB2> INFO: 4555200 events read in total (198676ms).
[18:45:55.511] <TB2> INFO: Test took 199602ms.
[18:46:22.684] <TB2> INFO: PixTestTrim::trimBitTest() done
[18:46:22.685] <TB2> INFO: PixTestTrim::doTest() done, duration: 2586 seconds
[18:46:22.685] <TB2> INFO: Decoding statistics:
[18:46:22.685] <TB2> INFO: General information:
[18:46:22.685] <TB2> INFO: 16bit words read: 0
[18:46:22.685] <TB2> INFO: valid events total: 0
[18:46:22.685] <TB2> INFO: empty events: 0
[18:46:22.685] <TB2> INFO: valid events with pixels: 0
[18:46:22.685] <TB2> INFO: valid pixel hits: 0
[18:46:22.685] <TB2> INFO: Event errors: 0
[18:46:22.685] <TB2> INFO: start marker: 0
[18:46:22.685] <TB2> INFO: stop marker: 0
[18:46:22.685] <TB2> INFO: overflow: 0
[18:46:22.685] <TB2> INFO: invalid 5bit words: 0
[18:46:22.685] <TB2> INFO: invalid XOR eye diagram: 0
[18:46:22.685] <TB2> INFO: frame (failed synchr.): 0
[18:46:22.685] <TB2> INFO: idle data (no TBM trl): 0
[18:46:22.685] <TB2> INFO: no data (only TBM hdr): 0
[18:46:22.685] <TB2> INFO: TBM errors: 0
[18:46:22.685] <TB2> INFO: flawed TBM headers: 0
[18:46:22.685] <TB2> INFO: flawed TBM trailers: 0
[18:46:22.685] <TB2> INFO: event ID mismatches: 0
[18:46:22.685] <TB2> INFO: ROC errors: 0
[18:46:22.685] <TB2> INFO: missing ROC header(s): 0
[18:46:22.685] <TB2> INFO: misplaced readback start: 0
[18:46:22.685] <TB2> INFO: Pixel decoding errors: 0
[18:46:22.685] <TB2> INFO: pixel data incomplete: 0
[18:46:22.685] <TB2> INFO: pixel address: 0
[18:46:22.686] <TB2> INFO: pulse height fill bit: 0
[18:46:22.686] <TB2> INFO: buffer corruption: 0
[18:46:23.286] <TB2> INFO: ######################################################################
[18:46:23.286] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[18:46:23.286] <TB2> INFO: ######################################################################
[18:46:23.526] <TB2> INFO: Expecting 41600 events.
[18:46:26.969] <TB2> INFO: 41600 events read in total (2851ms).
[18:46:26.970] <TB2> INFO: Test took 3683ms.
[18:46:27.412] <TB2> INFO: Expecting 41600 events.
[18:46:30.913] <TB2> INFO: 41600 events read in total (2909ms).
[18:46:30.914] <TB2> INFO: Test took 3741ms.
[18:46:31.203] <TB2> INFO: Expecting 41600 events.
[18:46:34.683] <TB2> INFO: 41600 events read in total (2888ms).
[18:46:34.684] <TB2> INFO: Test took 3746ms.
[18:46:34.973] <TB2> INFO: Expecting 41600 events.
[18:46:38.541] <TB2> INFO: 41600 events read in total (2976ms).
[18:46:38.542] <TB2> INFO: Test took 3834ms.
[18:46:38.831] <TB2> INFO: Expecting 41600 events.
[18:46:42.349] <TB2> INFO: 41600 events read in total (2927ms).
[18:46:42.350] <TB2> INFO: Test took 3784ms.
[18:46:42.639] <TB2> INFO: Expecting 41600 events.
[18:46:46.120] <TB2> INFO: 41600 events read in total (2890ms).
[18:46:46.121] <TB2> INFO: Test took 3747ms.
[18:46:46.413] <TB2> INFO: Expecting 41600 events.
[18:46:49.931] <TB2> INFO: 41600 events read in total (2927ms).
[18:46:49.932] <TB2> INFO: Test took 3784ms.
[18:46:50.225] <TB2> INFO: Expecting 41600 events.
[18:46:53.710] <TB2> INFO: 41600 events read in total (2894ms).
[18:46:53.711] <TB2> INFO: Test took 3751ms.
[18:46:53.000] <TB2> INFO: Expecting 41600 events.
[18:46:57.496] <TB2> INFO: 41600 events read in total (2904ms).
[18:46:57.497] <TB2> INFO: Test took 3761ms.
[18:46:57.786] <TB2> INFO: Expecting 41600 events.
[18:47:01.385] <TB2> INFO: 41600 events read in total (3007ms).
[18:47:01.386] <TB2> INFO: Test took 3864ms.
[18:47:01.678] <TB2> INFO: Expecting 41600 events.
[18:47:05.212] <TB2> INFO: 41600 events read in total (2943ms).
[18:47:05.213] <TB2> INFO: Test took 3801ms.
[18:47:05.511] <TB2> INFO: Expecting 41600 events.
[18:47:09.062] <TB2> INFO: 41600 events read in total (2959ms).
[18:47:09.062] <TB2> INFO: Test took 3826ms.
[18:47:09.352] <TB2> INFO: Expecting 41600 events.
[18:47:12.844] <TB2> INFO: 41600 events read in total (2901ms).
[18:47:12.845] <TB2> INFO: Test took 3758ms.
[18:47:13.135] <TB2> INFO: Expecting 41600 events.
[18:47:16.670] <TB2> INFO: 41600 events read in total (2943ms).
[18:47:16.670] <TB2> INFO: Test took 3801ms.
[18:47:16.963] <TB2> INFO: Expecting 41600 events.
[18:47:20.467] <TB2> INFO: 41600 events read in total (2913ms).
[18:47:20.468] <TB2> INFO: Test took 3771ms.
[18:47:20.761] <TB2> INFO: Expecting 41600 events.
[18:47:24.282] <TB2> INFO: 41600 events read in total (2930ms).
[18:47:24.283] <TB2> INFO: Test took 3788ms.
[18:47:24.572] <TB2> INFO: Expecting 41600 events.
[18:47:28.115] <TB2> INFO: 41600 events read in total (2951ms).
[18:47:28.116] <TB2> INFO: Test took 3808ms.
[18:47:28.405] <TB2> INFO: Expecting 41600 events.
[18:47:31.996] <TB2> INFO: 41600 events read in total (3000ms).
[18:47:31.997] <TB2> INFO: Test took 3857ms.
[18:47:32.288] <TB2> INFO: Expecting 41600 events.
[18:47:35.797] <TB2> INFO: 41600 events read in total (2918ms).
[18:47:35.797] <TB2> INFO: Test took 3774ms.
[18:47:36.086] <TB2> INFO: Expecting 41600 events.
[18:47:39.651] <TB2> INFO: 41600 events read in total (2973ms).
[18:47:39.652] <TB2> INFO: Test took 3830ms.
[18:47:39.942] <TB2> INFO: Expecting 41600 events.
[18:47:43.429] <TB2> INFO: 41600 events read in total (2896ms).
[18:47:43.430] <TB2> INFO: Test took 3754ms.
[18:47:43.722] <TB2> INFO: Expecting 41600 events.
[18:47:47.232] <TB2> INFO: 41600 events read in total (2918ms).
[18:47:47.233] <TB2> INFO: Test took 3776ms.
[18:47:47.526] <TB2> INFO: Expecting 41600 events.
[18:47:51.062] <TB2> INFO: 41600 events read in total (2945ms).
[18:47:51.063] <TB2> INFO: Test took 3803ms.
[18:47:51.353] <TB2> INFO: Expecting 41600 events.
[18:47:54.853] <TB2> INFO: 41600 events read in total (2909ms).
[18:47:54.854] <TB2> INFO: Test took 3767ms.
[18:47:55.143] <TB2> INFO: Expecting 41600 events.
[18:47:58.672] <TB2> INFO: 41600 events read in total (2937ms).
[18:47:58.673] <TB2> INFO: Test took 3794ms.
[18:47:58.966] <TB2> INFO: Expecting 41600 events.
[18:48:02.666] <TB2> INFO: 41600 events read in total (3108ms).
[18:48:02.667] <TB2> INFO: Test took 3966ms.
[18:48:02.957] <TB2> INFO: Expecting 41600 events.
[18:48:06.619] <TB2> INFO: 41600 events read in total (3070ms).
[18:48:06.620] <TB2> INFO: Test took 3928ms.
[18:48:06.915] <TB2> INFO: Expecting 41600 events.
[18:48:10.495] <TB2> INFO: 41600 events read in total (2988ms).
[18:48:10.496] <TB2> INFO: Test took 3846ms.
[18:48:10.787] <TB2> INFO: Expecting 2560 events.
[18:48:11.673] <TB2> INFO: 2560 events read in total (295ms).
[18:48:11.674] <TB2> INFO: Test took 1164ms.
[18:48:11.981] <TB2> INFO: Expecting 2560 events.
[18:48:12.877] <TB2> INFO: 2560 events read in total (305ms).
[18:48:12.877] <TB2> INFO: Test took 1201ms.
[18:48:13.184] <TB2> INFO: Expecting 2560 events.
[18:48:14.070] <TB2> INFO: 2560 events read in total (294ms).
[18:48:14.070] <TB2> INFO: Test took 1192ms.
[18:48:14.377] <TB2> INFO: Expecting 2560 events.
[18:48:15.271] <TB2> INFO: 2560 events read in total (302ms).
[18:48:15.272] <TB2> INFO: Test took 1201ms.
[18:48:15.580] <TB2> INFO: Expecting 2560 events.
[18:48:16.468] <TB2> INFO: 2560 events read in total (297ms).
[18:48:16.469] <TB2> INFO: Test took 1197ms.
[18:48:16.777] <TB2> INFO: Expecting 2560 events.
[18:48:17.658] <TB2> INFO: 2560 events read in total (289ms).
[18:48:17.658] <TB2> INFO: Test took 1187ms.
[18:48:17.965] <TB2> INFO: Expecting 2560 events.
[18:48:18.854] <TB2> INFO: 2560 events read in total (297ms).
[18:48:18.854] <TB2> INFO: Test took 1195ms.
[18:48:19.163] <TB2> INFO: Expecting 2560 events.
[18:48:20.053] <TB2> INFO: 2560 events read in total (298ms).
[18:48:20.054] <TB2> INFO: Test took 1199ms.
[18:48:20.362] <TB2> INFO: Expecting 2560 events.
[18:48:21.245] <TB2> INFO: 2560 events read in total (292ms).
[18:48:21.246] <TB2> INFO: Test took 1192ms.
[18:48:21.553] <TB2> INFO: Expecting 2560 events.
[18:48:22.437] <TB2> INFO: 2560 events read in total (293ms).
[18:48:22.438] <TB2> INFO: Test took 1191ms.
[18:48:22.746] <TB2> INFO: Expecting 2560 events.
[18:48:23.632] <TB2> INFO: 2560 events read in total (295ms).
[18:48:23.632] <TB2> INFO: Test took 1194ms.
[18:48:23.940] <TB2> INFO: Expecting 2560 events.
[18:48:24.823] <TB2> INFO: 2560 events read in total (291ms).
[18:48:24.823] <TB2> INFO: Test took 1191ms.
[18:48:25.131] <TB2> INFO: Expecting 2560 events.
[18:48:26.019] <TB2> INFO: 2560 events read in total (295ms).
[18:48:26.019] <TB2> INFO: Test took 1195ms.
[18:48:26.328] <TB2> INFO: Expecting 2560 events.
[18:48:27.215] <TB2> INFO: 2560 events read in total (295ms).
[18:48:27.215] <TB2> INFO: Test took 1195ms.
[18:48:27.523] <TB2> INFO: Expecting 2560 events.
[18:48:28.406] <TB2> INFO: 2560 events read in total (291ms).
[18:48:28.406] <TB2> INFO: Test took 1190ms.
[18:48:28.715] <TB2> INFO: Expecting 2560 events.
[18:48:29.605] <TB2> INFO: 2560 events read in total (299ms).
[18:48:29.605] <TB2> INFO: Test took 1198ms.
[18:48:29.608] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:48:29.914] <TB2> INFO: Expecting 655360 events.
[18:48:44.658] <TB2> INFO: 655360 events read in total (14152ms).
[18:48:44.673] <TB2> INFO: Expecting 655360 events.
[18:48:59.372] <TB2> INFO: 655360 events read in total (14296ms).
[18:48:59.391] <TB2> INFO: Expecting 655360 events.
[18:49:13.897] <TB2> INFO: 655360 events read in total (14102ms).
[18:49:13.921] <TB2> INFO: Expecting 655360 events.
[18:49:28.459] <TB2> INFO: 655360 events read in total (14135ms).
[18:49:28.488] <TB2> INFO: Expecting 655360 events.
[18:49:43.016] <TB2> INFO: 655360 events read in total (14125ms).
[18:49:43.048] <TB2> INFO: Expecting 655360 events.
[18:49:57.479] <TB2> INFO: 655360 events read in total (14028ms).
[18:49:57.520] <TB2> INFO: Expecting 655360 events.
[18:50:12.067] <TB2> INFO: 655360 events read in total (14144ms).
[18:50:12.115] <TB2> INFO: Expecting 655360 events.
[18:50:26.650] <TB2> INFO: 655360 events read in total (14132ms).
[18:50:26.696] <TB2> INFO: Expecting 655360 events.
[18:50:41.164] <TB2> INFO: 655360 events read in total (14065ms).
[18:50:41.241] <TB2> INFO: Expecting 655360 events.
[18:50:55.752] <TB2> INFO: 655360 events read in total (14107ms).
[18:50:55.838] <TB2> INFO: Expecting 655360 events.
[18:51:10.329] <TB2> INFO: 655360 events read in total (14088ms).
[18:51:10.405] <TB2> INFO: Expecting 655360 events.
[18:51:24.935] <TB2> INFO: 655360 events read in total (14127ms).
[18:51:25.015] <TB2> INFO: Expecting 655360 events.
[18:51:39.449] <TB2> INFO: 655360 events read in total (14031ms).
[18:51:39.536] <TB2> INFO: Expecting 655360 events.
[18:51:54.045] <TB2> INFO: 655360 events read in total (14106ms).
[18:51:54.134] <TB2> INFO: Expecting 655360 events.
[18:52:08.731] <TB2> INFO: 655360 events read in total (14194ms).
[18:52:08.824] <TB2> INFO: Expecting 655360 events.
[18:52:23.363] <TB2> INFO: 655360 events read in total (14136ms).
[18:52:23.473] <TB2> INFO: Test took 233865ms.
[18:52:23.572] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:52:23.825] <TB2> INFO: Expecting 655360 events.
[18:52:38.482] <TB2> INFO: 655360 events read in total (14065ms).
[18:52:38.500] <TB2> INFO: Expecting 655360 events.
[18:52:52.953] <TB2> INFO: 655360 events read in total (14050ms).
[18:52:52.972] <TB2> INFO: Expecting 655360 events.
[18:53:07.453] <TB2> INFO: 655360 events read in total (14078ms).
[18:53:07.484] <TB2> INFO: Expecting 655360 events.
[18:53:21.956] <TB2> INFO: 655360 events read in total (14069ms).
[18:53:21.983] <TB2> INFO: Expecting 655360 events.
[18:53:36.498] <TB2> INFO: 655360 events read in total (14112ms).
[18:53:36.530] <TB2> INFO: Expecting 655360 events.
[18:53:50.996] <TB2> INFO: 655360 events read in total (14063ms).
[18:53:51.032] <TB2> INFO: Expecting 655360 events.
[18:54:05.389] <TB2> INFO: 655360 events read in total (13954ms).
[18:54:05.435] <TB2> INFO: Expecting 655360 events.
[18:54:19.689] <TB2> INFO: 655360 events read in total (13851ms).
[18:54:19.731] <TB2> INFO: Expecting 655360 events.
[18:54:33.835] <TB2> INFO: 655360 events read in total (13701ms).
[18:54:33.892] <TB2> INFO: Expecting 655360 events.
[18:54:48.149] <TB2> INFO: 655360 events read in total (13854ms).
[18:54:48.217] <TB2> INFO: Expecting 655360 events.
[18:55:02.840] <TB2> INFO: 655360 events read in total (14220ms).
[18:55:02.936] <TB2> INFO: Expecting 655360 events.
[18:55:17.372] <TB2> INFO: 655360 events read in total (14033ms).
[18:55:17.449] <TB2> INFO: Expecting 655360 events.
[18:55:32.118] <TB2> INFO: 655360 events read in total (14265ms).
[18:55:32.200] <TB2> INFO: Expecting 655360 events.
[18:55:46.756] <TB2> INFO: 655360 events read in total (14153ms).
[18:55:46.842] <TB2> INFO: Expecting 655360 events.
[18:56:01.428] <TB2> INFO: 655360 events read in total (14183ms).
[18:56:01.517] <TB2> INFO: Expecting 655360 events.
[18:56:16.106] <TB2> INFO: 655360 events read in total (14186ms).
[18:56:16.202] <TB2> INFO: Test took 232630ms.
[18:56:16.372] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:56:16.378] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:56:16.383] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:56:16.389] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:56:16.395] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:56:16.400] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:56:16.406] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:56:16.412] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[18:56:16.417] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[18:56:16.424] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[18:56:16.429] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[18:56:16.435] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[18:56:16.441] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[18:56:16.447] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[18:56:16.453] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[18:56:16.459] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:56:16.465] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:56:16.470] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[18:56:16.476] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:56:16.482] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:56:16.488] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:56:16.494] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[18:56:16.501] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[18:56:16.507] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[18:56:16.513] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[18:56:16.519] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[18:56:16.525] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[18:56:16.531] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:56:16.538] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:56:16.544] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:56:16.550] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:56:16.557] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[18:56:16.563] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[18:56:16.570] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[18:56:16.576] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[18:56:16.582] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[18:56:16.588] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[18:56:16.594] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[18:56:16.600] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[18:56:16.606] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:56:16.612] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:56:16.618] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[18:56:16.624] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[18:56:16.630] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[18:56:16.637] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[18:56:16.643] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:56:16.649] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:56:16.655] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:56:16.662] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:56:16.668] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[18:56:16.674] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[18:56:16.681] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[18:56:16.687] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[18:56:16.693] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[18:56:16.700] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[18:56:16.706] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[18:56:16.712] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[18:56:16.718] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:56:16.724] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:56:16.730] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[18:56:16.736] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[18:56:16.742] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[18:56:16.749] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[18:56:16.755] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[18:56:16.761] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[18:56:16.767] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[18:56:16.773] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[18:56:16.779] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[18:56:16.785] <TB2> INFO: safety margin for low PH: adding 11, margin is now 31
[18:56:16.791] <TB2> INFO: safety margin for low PH: adding 12, margin is now 32
[18:56:16.797] <TB2> INFO: safety margin for low PH: adding 13, margin is now 33
[18:56:16.804] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:56:16.838] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C0.dat
[18:56:16.838] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C1.dat
[18:56:16.838] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C2.dat
[18:56:16.839] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C3.dat
[18:56:16.839] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C4.dat
[18:56:16.839] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C5.dat
[18:56:16.839] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C6.dat
[18:56:16.839] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C7.dat
[18:56:16.839] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C8.dat
[18:56:16.839] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C9.dat
[18:56:16.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C10.dat
[18:56:16.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C11.dat
[18:56:16.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C12.dat
[18:56:16.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C13.dat
[18:56:16.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C14.dat
[18:56:16.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//dacParameters35_C15.dat
[18:56:17.120] <TB2> INFO: Expecting 41600 events.
[18:56:20.301] <TB2> INFO: 41600 events read in total (2589ms).
[18:56:20.302] <TB2> INFO: Test took 3457ms.
[18:56:20.764] <TB2> INFO: Expecting 41600 events.
[18:56:23.826] <TB2> INFO: 41600 events read in total (2470ms).
[18:56:23.827] <TB2> INFO: Test took 3307ms.
[18:56:24.298] <TB2> INFO: Expecting 41600 events.
[18:56:27.496] <TB2> INFO: 41600 events read in total (2606ms).
[18:56:27.497] <TB2> INFO: Test took 3456ms.
[18:56:27.714] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:27.805] <TB2> INFO: Expecting 2560 events.
[18:56:28.696] <TB2> INFO: 2560 events read in total (299ms).
[18:56:28.697] <TB2> INFO: Test took 983ms.
[18:56:28.700] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:29.005] <TB2> INFO: Expecting 2560 events.
[18:56:29.899] <TB2> INFO: 2560 events read in total (302ms).
[18:56:29.899] <TB2> INFO: Test took 1199ms.
[18:56:29.902] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:30.208] <TB2> INFO: Expecting 2560 events.
[18:56:31.096] <TB2> INFO: 2560 events read in total (296ms).
[18:56:31.097] <TB2> INFO: Test took 1195ms.
[18:56:31.100] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:31.404] <TB2> INFO: Expecting 2560 events.
[18:56:32.292] <TB2> INFO: 2560 events read in total (296ms).
[18:56:32.293] <TB2> INFO: Test took 1193ms.
[18:56:32.296] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:32.601] <TB2> INFO: Expecting 2560 events.
[18:56:33.496] <TB2> INFO: 2560 events read in total (304ms).
[18:56:33.496] <TB2> INFO: Test took 1200ms.
[18:56:33.500] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:33.804] <TB2> INFO: Expecting 2560 events.
[18:56:34.694] <TB2> INFO: 2560 events read in total (299ms).
[18:56:34.695] <TB2> INFO: Test took 1196ms.
[18:56:34.698] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:34.003] <TB2> INFO: Expecting 2560 events.
[18:56:35.893] <TB2> INFO: 2560 events read in total (298ms).
[18:56:35.894] <TB2> INFO: Test took 1196ms.
[18:56:35.896] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:36.202] <TB2> INFO: Expecting 2560 events.
[18:56:37.094] <TB2> INFO: 2560 events read in total (300ms).
[18:56:37.094] <TB2> INFO: Test took 1198ms.
[18:56:37.096] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:37.403] <TB2> INFO: Expecting 2560 events.
[18:56:38.283] <TB2> INFO: 2560 events read in total (289ms).
[18:56:38.284] <TB2> INFO: Test took 1188ms.
[18:56:38.286] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:38.593] <TB2> INFO: Expecting 2560 events.
[18:56:39.478] <TB2> INFO: 2560 events read in total (293ms).
[18:56:39.479] <TB2> INFO: Test took 1193ms.
[18:56:39.481] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:39.787] <TB2> INFO: Expecting 2560 events.
[18:56:40.682] <TB2> INFO: 2560 events read in total (303ms).
[18:56:40.683] <TB2> INFO: Test took 1202ms.
[18:56:40.687] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:40.990] <TB2> INFO: Expecting 2560 events.
[18:56:41.883] <TB2> INFO: 2560 events read in total (302ms).
[18:56:41.883] <TB2> INFO: Test took 1197ms.
[18:56:41.887] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:42.192] <TB2> INFO: Expecting 2560 events.
[18:56:43.080] <TB2> INFO: 2560 events read in total (296ms).
[18:56:43.080] <TB2> INFO: Test took 1193ms.
[18:56:43.084] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:43.388] <TB2> INFO: Expecting 2560 events.
[18:56:44.277] <TB2> INFO: 2560 events read in total (297ms).
[18:56:44.278] <TB2> INFO: Test took 1195ms.
[18:56:44.281] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:44.586] <TB2> INFO: Expecting 2560 events.
[18:56:45.480] <TB2> INFO: 2560 events read in total (302ms).
[18:56:45.481] <TB2> INFO: Test took 1200ms.
[18:56:45.484] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:45.789] <TB2> INFO: Expecting 2560 events.
[18:56:46.681] <TB2> INFO: 2560 events read in total (300ms).
[18:56:46.681] <TB2> INFO: Test took 1197ms.
[18:56:46.686] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:46.988] <TB2> INFO: Expecting 2560 events.
[18:56:47.882] <TB2> INFO: 2560 events read in total (302ms).
[18:56:47.883] <TB2> INFO: Test took 1198ms.
[18:56:47.885] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:48.191] <TB2> INFO: Expecting 2560 events.
[18:56:49.077] <TB2> INFO: 2560 events read in total (294ms).
[18:56:49.077] <TB2> INFO: Test took 1192ms.
[18:56:49.079] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:49.386] <TB2> INFO: Expecting 2560 events.
[18:56:50.265] <TB2> INFO: 2560 events read in total (287ms).
[18:56:50.265] <TB2> INFO: Test took 1186ms.
[18:56:50.268] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:50.575] <TB2> INFO: Expecting 2560 events.
[18:56:51.459] <TB2> INFO: 2560 events read in total (292ms).
[18:56:51.459] <TB2> INFO: Test took 1191ms.
[18:56:51.462] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:51.766] <TB2> INFO: Expecting 2560 events.
[18:56:52.652] <TB2> INFO: 2560 events read in total (294ms).
[18:56:52.653] <TB2> INFO: Test took 1191ms.
[18:56:52.656] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:52.961] <TB2> INFO: Expecting 2560 events.
[18:56:53.849] <TB2> INFO: 2560 events read in total (296ms).
[18:56:53.850] <TB2> INFO: Test took 1194ms.
[18:56:53.853] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:54.158] <TB2> INFO: Expecting 2560 events.
[18:56:55.042] <TB2> INFO: 2560 events read in total (293ms).
[18:56:55.043] <TB2> INFO: Test took 1190ms.
[18:56:55.045] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:55.352] <TB2> INFO: Expecting 2560 events.
[18:56:56.240] <TB2> INFO: 2560 events read in total (297ms).
[18:56:56.240] <TB2> INFO: Test took 1195ms.
[18:56:56.242] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:56.549] <TB2> INFO: Expecting 2560 events.
[18:56:57.446] <TB2> INFO: 2560 events read in total (306ms).
[18:56:57.447] <TB2> INFO: Test took 1205ms.
[18:56:57.450] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:57.755] <TB2> INFO: Expecting 2560 events.
[18:56:58.648] <TB2> INFO: 2560 events read in total (302ms).
[18:56:58.649] <TB2> INFO: Test took 1199ms.
[18:56:58.652] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:56:58.957] <TB2> INFO: Expecting 2560 events.
[18:56:59.846] <TB2> INFO: 2560 events read in total (297ms).
[18:56:59.847] <TB2> INFO: Test took 1195ms.
[18:56:59.849] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:57:00.156] <TB2> INFO: Expecting 2560 events.
[18:57:01.041] <TB2> INFO: 2560 events read in total (294ms).
[18:57:01.041] <TB2> INFO: Test took 1193ms.
[18:57:01.045] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:57:01.349] <TB2> INFO: Expecting 2560 events.
[18:57:02.245] <TB2> INFO: 2560 events read in total (304ms).
[18:57:02.245] <TB2> INFO: Test took 1200ms.
[18:57:02.247] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:57:02.554] <TB2> INFO: Expecting 2560 events.
[18:57:03.448] <TB2> INFO: 2560 events read in total (302ms).
[18:57:03.448] <TB2> INFO: Test took 1201ms.
[18:57:03.451] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:57:03.757] <TB2> INFO: Expecting 2560 events.
[18:57:04.650] <TB2> INFO: 2560 events read in total (301ms).
[18:57:04.651] <TB2> INFO: Test took 1200ms.
[18:57:04.653] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:57:04.958] <TB2> INFO: Expecting 2560 events.
[18:57:05.847] <TB2> INFO: 2560 events read in total (298ms).
[18:57:05.848] <TB2> INFO: Test took 1195ms.
[18:57:06.324] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 643 seconds
[18:57:06.324] <TB2> INFO: PH scale (per ROC): 38 35 45 61 44 32 35 33 33 48 33 46 36 34 41 42
[18:57:06.324] <TB2> INFO: PH offset (per ROC): 105 101 122 126 109 97 81 102 102 111 102 103 99 98 112 108
[18:57:06.332] <TB2> INFO: Decoding statistics:
[18:57:06.332] <TB2> INFO: General information:
[18:57:06.332] <TB2> INFO: 16bit words read: 127880
[18:57:06.332] <TB2> INFO: valid events total: 20480
[18:57:06.332] <TB2> INFO: empty events: 17980
[18:57:06.332] <TB2> INFO: valid events with pixels: 2500
[18:57:06.332] <TB2> INFO: valid pixel hits: 2500
[18:57:06.332] <TB2> INFO: Event errors: 0
[18:57:06.332] <TB2> INFO: start marker: 0
[18:57:06.332] <TB2> INFO: stop marker: 0
[18:57:06.332] <TB2> INFO: overflow: 0
[18:57:06.332] <TB2> INFO: invalid 5bit words: 0
[18:57:06.332] <TB2> INFO: invalid XOR eye diagram: 0
[18:57:06.332] <TB2> INFO: frame (failed synchr.): 0
[18:57:06.332] <TB2> INFO: idle data (no TBM trl): 0
[18:57:06.332] <TB2> INFO: no data (only TBM hdr): 0
[18:57:06.332] <TB2> INFO: TBM errors: 0
[18:57:06.332] <TB2> INFO: flawed TBM headers: 0
[18:57:06.332] <TB2> INFO: flawed TBM trailers: 0
[18:57:06.332] <TB2> INFO: event ID mismatches: 0
[18:57:06.332] <TB2> INFO: ROC errors: 0
[18:57:06.332] <TB2> INFO: missing ROC header(s): 0
[18:57:06.332] <TB2> INFO: misplaced readback start: 0
[18:57:06.332] <TB2> INFO: Pixel decoding errors: 0
[18:57:06.332] <TB2> INFO: pixel data incomplete: 0
[18:57:06.332] <TB2> INFO: pixel address: 0
[18:57:06.332] <TB2> INFO: pulse height fill bit: 0
[18:57:06.332] <TB2> INFO: buffer corruption: 0
[18:57:06.495] <TB2> INFO: ######################################################################
[18:57:06.495] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[18:57:06.495] <TB2> INFO: ######################################################################
[18:57:06.510] <TB2> INFO: scanning low vcal = 10
[18:57:06.749] <TB2> INFO: Expecting 41600 events.
[18:57:10.392] <TB2> INFO: 41600 events read in total (3051ms).
[18:57:10.392] <TB2> INFO: Test took 3882ms.
[18:57:10.395] <TB2> INFO: scanning low vcal = 20
[18:57:10.685] <TB2> INFO: Expecting 41600 events.
[18:57:14.276] <TB2> INFO: 41600 events read in total (2999ms).
[18:57:14.276] <TB2> INFO: Test took 3880ms.
[18:57:14.278] <TB2> INFO: scanning low vcal = 30
[18:57:14.571] <TB2> INFO: Expecting 41600 events.
[18:57:18.268] <TB2> INFO: 41600 events read in total (3105ms).
[18:57:18.269] <TB2> INFO: Test took 3990ms.
[18:57:18.271] <TB2> INFO: scanning low vcal = 40
[18:57:18.549] <TB2> INFO: Expecting 41600 events.
[18:57:22.529] <TB2> INFO: 41600 events read in total (3388ms).
[18:57:22.530] <TB2> INFO: Test took 4259ms.
[18:57:22.534] <TB2> INFO: scanning low vcal = 50
[18:57:22.811] <TB2> INFO: Expecting 41600 events.
[18:57:26.818] <TB2> INFO: 41600 events read in total (3415ms).
[18:57:26.819] <TB2> INFO: Test took 4285ms.
[18:57:26.823] <TB2> INFO: scanning low vcal = 60
[18:57:27.101] <TB2> INFO: Expecting 41600 events.
[18:57:31.126] <TB2> INFO: 41600 events read in total (3434ms).
[18:57:31.127] <TB2> INFO: Test took 4304ms.
[18:57:31.130] <TB2> INFO: scanning low vcal = 70
[18:57:31.407] <TB2> INFO: Expecting 41600 events.
[18:57:35.414] <TB2> INFO: 41600 events read in total (3415ms).
[18:57:35.415] <TB2> INFO: Test took 4285ms.
[18:57:35.418] <TB2> INFO: scanning low vcal = 80
[18:57:35.694] <TB2> INFO: Expecting 41600 events.
[18:57:39.699] <TB2> INFO: 41600 events read in total (3413ms).
[18:57:39.700] <TB2> INFO: Test took 4282ms.
[18:57:39.703] <TB2> INFO: scanning low vcal = 90
[18:57:39.981] <TB2> INFO: Expecting 41600 events.
[18:57:43.000] <TB2> INFO: 41600 events read in total (3428ms).
[18:57:43.000] <TB2> INFO: Test took 4296ms.
[18:57:44.004] <TB2> INFO: scanning low vcal = 100
[18:57:44.280] <TB2> INFO: Expecting 41600 events.
[18:57:48.245] <TB2> INFO: 41600 events read in total (3373ms).
[18:57:48.246] <TB2> INFO: Test took 4242ms.
[18:57:48.249] <TB2> INFO: scanning low vcal = 110
[18:57:48.526] <TB2> INFO: Expecting 41600 events.
[18:57:52.465] <TB2> INFO: 41600 events read in total (3348ms).
[18:57:52.466] <TB2> INFO: Test took 4216ms.
[18:57:52.469] <TB2> INFO: scanning low vcal = 120
[18:57:52.745] <TB2> INFO: Expecting 41600 events.
[18:57:56.697] <TB2> INFO: 41600 events read in total (3360ms).
[18:57:56.698] <TB2> INFO: Test took 4229ms.
[18:57:56.702] <TB2> INFO: scanning low vcal = 130
[18:57:56.982] <TB2> INFO: Expecting 41600 events.
[18:58:00.927] <TB2> INFO: 41600 events read in total (3354ms).
[18:58:00.928] <TB2> INFO: Test took 4226ms.
[18:58:00.931] <TB2> INFO: scanning low vcal = 140
[18:58:01.208] <TB2> INFO: Expecting 41600 events.
[18:58:05.164] <TB2> INFO: 41600 events read in total (3365ms).
[18:58:05.165] <TB2> INFO: Test took 4234ms.
[18:58:05.168] <TB2> INFO: scanning low vcal = 150
[18:58:05.444] <TB2> INFO: Expecting 41600 events.
[18:58:09.387] <TB2> INFO: 41600 events read in total (3351ms).
[18:58:09.388] <TB2> INFO: Test took 4220ms.
[18:58:09.392] <TB2> INFO: scanning low vcal = 160
[18:58:09.668] <TB2> INFO: Expecting 41600 events.
[18:58:13.640] <TB2> INFO: 41600 events read in total (3380ms).
[18:58:13.641] <TB2> INFO: Test took 4249ms.
[18:58:13.644] <TB2> INFO: scanning low vcal = 170
[18:58:13.921] <TB2> INFO: Expecting 41600 events.
[18:58:17.930] <TB2> INFO: 41600 events read in total (3418ms).
[18:58:17.931] <TB2> INFO: Test took 4287ms.
[18:58:17.937] <TB2> INFO: scanning low vcal = 180
[18:58:18.211] <TB2> INFO: Expecting 41600 events.
[18:58:22.242] <TB2> INFO: 41600 events read in total (3439ms).
[18:58:22.243] <TB2> INFO: Test took 4306ms.
[18:58:22.247] <TB2> INFO: scanning low vcal = 190
[18:58:22.543] <TB2> INFO: Expecting 41600 events.
[18:58:26.558] <TB2> INFO: 41600 events read in total (3424ms).
[18:58:26.559] <TB2> INFO: Test took 4312ms.
[18:58:26.562] <TB2> INFO: scanning low vcal = 200
[18:58:26.839] <TB2> INFO: Expecting 41600 events.
[18:58:30.871] <TB2> INFO: 41600 events read in total (3440ms).
[18:58:30.872] <TB2> INFO: Test took 4310ms.
[18:58:30.875] <TB2> INFO: scanning low vcal = 210
[18:58:31.152] <TB2> INFO: Expecting 41600 events.
[18:58:35.200] <TB2> INFO: 41600 events read in total (3456ms).
[18:58:35.201] <TB2> INFO: Test took 4326ms.
[18:58:35.204] <TB2> INFO: scanning low vcal = 220
[18:58:35.481] <TB2> INFO: Expecting 41600 events.
[18:58:39.506] <TB2> INFO: 41600 events read in total (3433ms).
[18:58:39.507] <TB2> INFO: Test took 4303ms.
[18:58:39.510] <TB2> INFO: scanning low vcal = 230
[18:58:39.787] <TB2> INFO: Expecting 41600 events.
[18:58:43.819] <TB2> INFO: 41600 events read in total (3441ms).
[18:58:43.820] <TB2> INFO: Test took 4310ms.
[18:58:43.823] <TB2> INFO: scanning low vcal = 240
[18:58:44.100] <TB2> INFO: Expecting 41600 events.
[18:58:48.113] <TB2> INFO: 41600 events read in total (3421ms).
[18:58:48.114] <TB2> INFO: Test took 4291ms.
[18:58:48.117] <TB2> INFO: scanning low vcal = 250
[18:58:48.394] <TB2> INFO: Expecting 41600 events.
[18:58:52.452] <TB2> INFO: 41600 events read in total (3466ms).
[18:58:52.453] <TB2> INFO: Test took 4336ms.
[18:58:52.458] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[18:58:52.733] <TB2> INFO: Expecting 41600 events.
[18:58:56.755] <TB2> INFO: 41600 events read in total (3430ms).
[18:58:56.756] <TB2> INFO: Test took 4298ms.
[18:58:56.759] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[18:58:57.036] <TB2> INFO: Expecting 41600 events.
[18:59:01.055] <TB2> INFO: 41600 events read in total (3428ms).
[18:59:01.056] <TB2> INFO: Test took 4297ms.
[18:59:01.059] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[18:59:01.336] <TB2> INFO: Expecting 41600 events.
[18:59:05.311] <TB2> INFO: 41600 events read in total (3383ms).
[18:59:05.311] <TB2> INFO: Test took 4252ms.
[18:59:05.315] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[18:59:05.591] <TB2> INFO: Expecting 41600 events.
[18:59:09.583] <TB2> INFO: 41600 events read in total (3401ms).
[18:59:09.584] <TB2> INFO: Test took 4269ms.
[18:59:09.587] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[18:59:09.864] <TB2> INFO: Expecting 41600 events.
[18:59:13.895] <TB2> INFO: 41600 events read in total (3440ms).
[18:59:13.896] <TB2> INFO: Test took 4308ms.
[18:59:14.300] <TB2> INFO: PixTestGainPedestal::measure() done
[18:59:47.711] <TB2> INFO: PixTestGainPedestal::fit() done
[18:59:47.711] <TB2> INFO: non-linearity mean: 0.943 0.954 0.979 0.984 0.956 0.988 0.938 0.932 0.917 0.973 0.934 0.954 0.933 0.957 0.941 0.938
[18:59:47.711] <TB2> INFO: non-linearity RMS: 0.074 0.187 0.005 0.002 0.075 0.179 0.160 0.138 0.126 0.017 0.082 0.045 0.072 0.149 0.071 0.096
[18:59:47.712] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr35_C0.dat
[18:59:47.725] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr35_C1.dat
[18:59:47.739] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr35_C2.dat
[18:59:47.752] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr35_C3.dat
[18:59:47.765] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr35_C4.dat
[18:59:47.778] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr35_C5.dat
[18:59:47.791] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr35_C6.dat
[18:59:47.804] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr35_C7.dat
[18:59:47.818] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr35_C8.dat
[18:59:47.831] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr35_C9.dat
[18:59:47.844] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr35_C10.dat
[18:59:47.857] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr35_C11.dat
[18:59:47.870] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr35_C12.dat
[18:59:47.883] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr35_C13.dat
[18:59:47.896] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr35_C14.dat
[18:59:47.909] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1075_FullQualification_2016-10-25_15h07m_1477400838//003_Fulltest_p17//phCalibrationFitErr35_C15.dat
[18:59:47.923] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 161 seconds
[18:59:47.923] <TB2> INFO: Decoding statistics:
[18:59:47.923] <TB2> INFO: General information:
[18:59:47.923] <TB2> INFO: 16bit words read: 3290048
[18:59:47.923] <TB2> INFO: valid events total: 332800
[18:59:47.923] <TB2> INFO: empty events: 476
[18:59:47.923] <TB2> INFO: valid events with pixels: 332324
[18:59:47.923] <TB2> INFO: valid pixel hits: 646624
[18:59:47.923] <TB2> INFO: Event errors: 0
[18:59:47.923] <TB2> INFO: start marker: 0
[18:59:47.923] <TB2> INFO: stop marker: 0
[18:59:47.923] <TB2> INFO: overflow: 0
[18:59:47.923] <TB2> INFO: invalid 5bit words: 0
[18:59:47.923] <TB2> INFO: invalid XOR eye diagram: 0
[18:59:47.923] <TB2> INFO: frame (failed synchr.): 0
[18:59:47.923] <TB2> INFO: idle data (no TBM trl): 0
[18:59:47.923] <TB2> INFO: no data (only TBM hdr): 0
[18:59:47.923] <TB2> INFO: TBM errors: 0
[18:59:47.923] <TB2> INFO: flawed TBM headers: 0
[18:59:47.923] <TB2> INFO: flawed TBM trailers: 0
[18:59:47.923] <TB2> INFO: event ID mismatches: 0
[18:59:47.923] <TB2> INFO: ROC errors: 0
[18:59:47.923] <TB2> INFO: missing ROC header(s): 0
[18:59:47.923] <TB2> INFO: misplaced readback start: 0
[18:59:47.923] <TB2> INFO: Pixel decoding errors: 0
[18:59:47.923] <TB2> INFO: pixel data incomplete: 0
[18:59:47.923] <TB2> INFO: pixel address: 0
[18:59:47.923] <TB2> INFO: pulse height fill bit: 0
[18:59:47.923] <TB2> INFO: buffer corruption: 0
[18:59:47.940] <TB2> INFO: Decoding statistics:
[18:59:47.940] <TB2> INFO: General information:
[18:59:47.940] <TB2> INFO: 16bit words read: 3419464
[18:59:47.940] <TB2> INFO: valid events total: 353536
[18:59:47.940] <TB2> INFO: empty events: 18712
[18:59:47.940] <TB2> INFO: valid events with pixels: 334824
[18:59:47.940] <TB2> INFO: valid pixel hits: 649124
[18:59:47.940] <TB2> INFO: Event errors: 0
[18:59:47.940] <TB2> INFO: start marker: 0
[18:59:47.940] <TB2> INFO: stop marker: 0
[18:59:47.940] <TB2> INFO: overflow: 0
[18:59:47.940] <TB2> INFO: invalid 5bit words: 0
[18:59:47.940] <TB2> INFO: invalid XOR eye diagram: 0
[18:59:47.940] <TB2> INFO: frame (failed synchr.): 0
[18:59:47.940] <TB2> INFO: idle data (no TBM trl): 0
[18:59:47.940] <TB2> INFO: no data (only TBM hdr): 0
[18:59:47.940] <TB2> INFO: TBM errors: 0
[18:59:47.940] <TB2> INFO: flawed TBM headers: 0
[18:59:47.940] <TB2> INFO: flawed TBM trailers: 0
[18:59:47.940] <TB2> INFO: event ID mismatches: 0
[18:59:47.940] <TB2> INFO: ROC errors: 0
[18:59:47.940] <TB2> INFO: missing ROC header(s): 0
[18:59:47.940] <TB2> INFO: misplaced readback start: 0
[18:59:47.940] <TB2> INFO: Pixel decoding errors: 0
[18:59:47.940] <TB2> INFO: pixel data incomplete: 0
[18:59:47.940] <TB2> INFO: pixel address: 0
[18:59:47.940] <TB2> INFO: pulse height fill bit: 0
[18:59:47.940] <TB2> INFO: buffer corruption: 0
[18:59:47.940] <TB2> INFO: enter test to run
[18:59:47.940] <TB2> INFO: test: exit no parameter change
[18:59:48.064] <TB2> QUIET: Connection to board 149 closed.
[18:59:48.064] <TB2> INFO: pXar: this is the end, my friend