[19:27:07.476] <TB2> INFO: *** Welcome to pxar ***
[19:27:07.476] <TB2> INFO: *** Today: 2016/11/03
[19:27:07.485] <TB2> INFO: *** Version: c8ba-dirty
[19:27:07.485] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C15.dat
[19:27:07.485] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//tbmParameters_C1b.dat
[19:27:07.485] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//defaultMaskFile.dat
[19:27:07.486] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters_C15.dat
[19:27:07.548] <TB2> INFO: clk: 4
[19:27:07.549] <TB2> INFO: ctr: 4
[19:27:07.549] <TB2> INFO: sda: 19
[19:27:07.549] <TB2> INFO: tin: 9
[19:27:07.549] <TB2> INFO: level: 15
[19:27:07.549] <TB2> INFO: triggerdelay: 0
[19:27:07.549] <TB2> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[19:27:07.549] <TB2> INFO: Log level: INFO
[19:27:07.558] <TB2> INFO: Found DTB DTB_WWXUD2
[19:27:07.566] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[19:27:07.568] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[19:27:07.570] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[19:27:09.059] <TB2> INFO: DUT info:
[19:27:09.060] <TB2> INFO: The DUT currently contains the following objects:
[19:27:09.060] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[19:27:09.060] <TB2> INFO: TBM Core alpha (0): 7 registers set
[19:27:09.060] <TB2> INFO: TBM Core beta (1): 7 registers set
[19:27:09.060] <TB2> INFO: TBM Core alpha (2): 7 registers set
[19:27:09.060] <TB2> INFO: TBM Core beta (3): 7 registers set
[19:27:09.060] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[19:27:09.060] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[19:27:09.060] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[19:27:09.060] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[19:27:09.060] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[19:27:09.060] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[19:27:09.060] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[19:27:09.060] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[19:27:09.060] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[19:27:09.060] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[19:27:09.060] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[19:27:09.060] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[19:27:09.060] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[19:27:09.060] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[19:27:09.060] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[19:27:09.060] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[19:27:09.060] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[19:27:09.462] <TB2> INFO: enter 'restricted' command line mode
[19:27:09.462] <TB2> INFO: enter test to run
[19:27:09.462] <TB2> INFO: test: pretest no parameter change
[19:27:09.462] <TB2> INFO: running: pretest
[19:27:09.469] <TB2> INFO: ######################################################################
[19:27:09.469] <TB2> INFO: PixTestPretest::doTest()
[19:27:09.469] <TB2> INFO: ######################################################################
[19:27:09.470] <TB2> INFO: ----------------------------------------------------------------------
[19:27:09.470] <TB2> INFO: PixTestPretest::programROC()
[19:27:09.470] <TB2> INFO: ----------------------------------------------------------------------
[19:27:27.484] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[19:27:27.484] <TB2> INFO: IA differences per ROC: 18.5 17.7 20.9 18.5 20.1 18.5 19.3 16.1 17.7 18.5 19.3 18.5 22.5 20.9 20.9 20.9
[19:27:27.552] <TB2> INFO: ----------------------------------------------------------------------
[19:27:27.552] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[19:27:27.552] <TB2> INFO: ----------------------------------------------------------------------
[19:27:35.358] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 380.2 mA = 23.7625 mA/ROC
[19:27:35.358] <TB2> INFO: i(loss) [mA/ROC]: 19.3 19.3 19.3 19.3 20.1 18.4 19.3 19.3 18.4 19.3 19.3 19.3 18.4 19.3 19.3 18.4
[19:27:35.395] <TB2> INFO: ----------------------------------------------------------------------
[19:27:35.395] <TB2> INFO: PixTestPretest::findTiming()
[19:27:35.395] <TB2> INFO: ----------------------------------------------------------------------
[19:27:35.395] <TB2> INFO: PixTestCmd::init()

[19:28:07.674] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[19:28:07.674] <TB2> INFO: (success/tries = 100/100), width = 3
[19:28:09.183] <TB2> INFO: ----------------------------------------------------------------------
[19:28:09.183] <TB2> INFO: PixTestPretest::findWorkingPixel()
[19:28:09.183] <TB2> INFO: ----------------------------------------------------------------------
[19:28:09.278] <TB2> INFO: Expecting 231680 events.
[19:28:19.097] <TB2> INFO: 231680 events read in total (9228ms).
[19:28:19.106] <TB2> INFO: Test took 9918ms.
[19:28:19.347] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[19:28:19.381] <TB2> INFO: ----------------------------------------------------------------------
[19:28:19.381] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[19:28:19.381] <TB2> INFO: ----------------------------------------------------------------------
[19:28:19.476] <TB2> INFO: Expecting 231680 events.
[19:28:29.480] <TB2> INFO: 231680 events read in total (9413ms).
[19:28:29.487] <TB2> INFO: Test took 10101ms.
[19:28:29.754] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[19:28:29.754] <TB2> INFO: CalDel: 108 115 130 104 108 97 99 84 113 132 97 104 105 118 109 99
[19:28:29.754] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[19:28:29.758] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C0.dat
[19:28:29.758] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C1.dat
[19:28:29.759] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C2.dat
[19:28:29.759] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C3.dat
[19:28:29.759] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C4.dat
[19:28:29.759] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C5.dat
[19:28:29.760] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C6.dat
[19:28:29.760] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C7.dat
[19:28:29.760] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C8.dat
[19:28:29.760] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C9.dat
[19:28:29.760] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C10.dat
[19:28:29.761] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C11.dat
[19:28:29.761] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C12.dat
[19:28:29.761] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C13.dat
[19:28:29.761] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C14.dat
[19:28:29.761] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters_C15.dat
[19:28:29.761] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//tbmParameters_C0a.dat
[19:28:29.762] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//tbmParameters_C0b.dat
[19:28:29.762] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//tbmParameters_C1a.dat
[19:28:29.762] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//tbmParameters_C1b.dat
[19:28:29.762] <TB2> INFO: PixTestPretest::doTest() done, duration: 80 seconds
[19:28:29.815] <TB2> INFO: enter test to run
[19:28:29.815] <TB2> INFO: test: FullTest no parameter change
[19:28:29.815] <TB2> INFO: running: fulltest
[19:28:29.815] <TB2> INFO: ######################################################################
[19:28:29.815] <TB2> INFO: PixTestFullTest::doTest()
[19:28:29.815] <TB2> INFO: ######################################################################
[19:28:29.816] <TB2> INFO: ######################################################################
[19:28:29.816] <TB2> INFO: PixTestAlive::doTest()
[19:28:29.816] <TB2> INFO: ######################################################################
[19:28:29.817] <TB2> INFO: ----------------------------------------------------------------------
[19:28:29.818] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[19:28:29.818] <TB2> INFO: ----------------------------------------------------------------------
[19:28:30.104] <TB2> INFO: Expecting 41600 events.
[19:28:33.768] <TB2> INFO: 41600 events read in total (3072ms).
[19:28:33.771] <TB2> INFO: Test took 3951ms.
[19:28:34.008] <TB2> INFO: PixTestAlive::aliveTest() done
[19:28:34.008] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[19:28:34.011] <TB2> INFO: ----------------------------------------------------------------------
[19:28:34.011] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[19:28:34.011] <TB2> INFO: ----------------------------------------------------------------------
[19:28:34.257] <TB2> INFO: Expecting 41600 events.
[19:28:37.365] <TB2> INFO: 41600 events read in total (2516ms).
[19:28:37.365] <TB2> INFO: Test took 3351ms.
[19:28:37.365] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[19:28:37.603] <TB2> INFO: PixTestAlive::maskTest() done
[19:28:37.604] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[19:28:37.606] <TB2> INFO: ----------------------------------------------------------------------
[19:28:37.606] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[19:28:37.606] <TB2> INFO: ----------------------------------------------------------------------
[19:28:37.894] <TB2> INFO: Expecting 41600 events.
[19:28:41.539] <TB2> INFO: 41600 events read in total (3052ms).
[19:28:41.541] <TB2> INFO: Test took 3933ms.
[19:28:41.774] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[19:28:41.774] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[19:28:41.774] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[19:28:41.774] <TB2> INFO: Decoding statistics:
[19:28:41.774] <TB2> INFO: General information:
[19:28:41.774] <TB2> INFO: 16bit words read: 0
[19:28:41.774] <TB2> INFO: valid events total: 0
[19:28:41.774] <TB2> INFO: empty events: 0
[19:28:41.774] <TB2> INFO: valid events with pixels: 0
[19:28:41.774] <TB2> INFO: valid pixel hits: 0
[19:28:41.774] <TB2> INFO: Event errors: 0
[19:28:41.774] <TB2> INFO: start marker: 0
[19:28:41.774] <TB2> INFO: stop marker: 0
[19:28:41.775] <TB2> INFO: overflow: 0
[19:28:41.775] <TB2> INFO: invalid 5bit words: 0
[19:28:41.775] <TB2> INFO: invalid XOR eye diagram: 0
[19:28:41.775] <TB2> INFO: frame (failed synchr.): 0
[19:28:41.775] <TB2> INFO: idle data (no TBM trl): 0
[19:28:41.775] <TB2> INFO: no data (only TBM hdr): 0
[19:28:41.775] <TB2> INFO: TBM errors: 0
[19:28:41.775] <TB2> INFO: flawed TBM headers: 0
[19:28:41.775] <TB2> INFO: flawed TBM trailers: 0
[19:28:41.775] <TB2> INFO: event ID mismatches: 0
[19:28:41.775] <TB2> INFO: ROC errors: 0
[19:28:41.775] <TB2> INFO: missing ROC header(s): 0
[19:28:41.775] <TB2> INFO: misplaced readback start: 0
[19:28:41.775] <TB2> INFO: Pixel decoding errors: 0
[19:28:41.775] <TB2> INFO: pixel data incomplete: 0
[19:28:41.775] <TB2> INFO: pixel address: 0
[19:28:41.775] <TB2> INFO: pulse height fill bit: 0
[19:28:41.775] <TB2> INFO: buffer corruption: 0
[19:28:41.780] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C15.dat
[19:28:41.780] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[19:28:41.780] <TB2> INFO: ######################################################################
[19:28:41.780] <TB2> INFO: PixTestReadback::doTest()
[19:28:41.780] <TB2> INFO: ######################################################################
[19:28:41.780] <TB2> INFO: ----------------------------------------------------------------------
[19:28:41.780] <TB2> INFO: PixTestReadback::CalibrateVd()
[19:28:41.780] <TB2> INFO: ----------------------------------------------------------------------
[19:28:51.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C0.dat
[19:28:51.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C1.dat
[19:28:51.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C2.dat
[19:28:51.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C3.dat
[19:28:51.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C4.dat
[19:28:51.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C5.dat
[19:28:51.796] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C6.dat
[19:28:51.797] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C7.dat
[19:28:51.797] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C8.dat
[19:28:51.797] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C9.dat
[19:28:51.797] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C10.dat
[19:28:51.797] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C11.dat
[19:28:51.797] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C12.dat
[19:28:51.797] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C13.dat
[19:28:51.797] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C14.dat
[19:28:51.797] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C15.dat
[19:28:51.829] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[19:28:51.830] <TB2> INFO: ----------------------------------------------------------------------
[19:28:51.830] <TB2> INFO: PixTestReadback::CalibrateVa()
[19:28:51.830] <TB2> INFO: ----------------------------------------------------------------------
[19:29:01.782] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C0.dat
[19:29:01.782] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C1.dat
[19:29:01.782] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C2.dat
[19:29:01.782] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C3.dat
[19:29:01.782] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C4.dat
[19:29:01.782] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C5.dat
[19:29:01.782] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C6.dat
[19:29:01.782] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C7.dat
[19:29:01.782] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C8.dat
[19:29:01.782] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C9.dat
[19:29:01.782] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C10.dat
[19:29:01.782] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C11.dat
[19:29:01.783] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C12.dat
[19:29:01.783] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C13.dat
[19:29:01.783] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C14.dat
[19:29:01.783] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C15.dat
[19:29:01.812] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[19:29:01.812] <TB2> INFO: ----------------------------------------------------------------------
[19:29:01.812] <TB2> INFO: PixTestReadback::readbackVbg()
[19:29:01.812] <TB2> INFO: ----------------------------------------------------------------------
[19:29:09.494] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[19:29:09.494] <TB2> INFO: ----------------------------------------------------------------------
[19:29:09.494] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[19:29:09.494] <TB2> INFO: ----------------------------------------------------------------------
[19:29:09.495] <TB2> INFO: Vbg will be calibrated using Vd calibration
[19:29:09.495] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 158.9calibrated Vbg = 1.18569 :::*/*/*/*/
[19:29:09.495] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 154.9calibrated Vbg = 1.17978 :::*/*/*/*/
[19:29:09.495] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 161.4calibrated Vbg = 1.17975 :::*/*/*/*/
[19:29:09.495] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 148.8calibrated Vbg = 1.17193 :::*/*/*/*/
[19:29:09.495] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 150.7calibrated Vbg = 1.18356 :::*/*/*/*/
[19:29:09.495] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 158.2calibrated Vbg = 1.18457 :::*/*/*/*/
[19:29:09.495] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 150.5calibrated Vbg = 1.17997 :::*/*/*/*/
[19:29:09.495] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 147.1calibrated Vbg = 1.17865 :::*/*/*/*/
[19:29:09.495] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 155.3calibrated Vbg = 1.17607 :::*/*/*/*/
[19:29:09.495] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 155.9calibrated Vbg = 1.18184 :::*/*/*/*/
[19:29:09.495] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 152.8calibrated Vbg = 1.16956 :::*/*/*/*/
[19:29:09.495] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 154.2calibrated Vbg = 1.16692 :::*/*/*/*/
[19:29:09.495] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 159.9calibrated Vbg = 1.17563 :::*/*/*/*/
[19:29:09.495] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 149calibrated Vbg = 1.17773 :::*/*/*/*/
[19:29:09.495] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 152.3calibrated Vbg = 1.17523 :::*/*/*/*/
[19:29:09.495] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 150.4calibrated Vbg = 1.18074 :::*/*/*/*/
[19:29:09.498] <TB2> INFO: ----------------------------------------------------------------------
[19:29:09.498] <TB2> INFO: PixTestReadback::CalibrateIa()
[19:29:09.498] <TB2> INFO: ----------------------------------------------------------------------
[19:31:50.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C0.dat
[19:31:50.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C1.dat
[19:31:50.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C2.dat
[19:31:50.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C3.dat
[19:31:50.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C4.dat
[19:31:50.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C5.dat
[19:31:50.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C6.dat
[19:31:50.301] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C7.dat
[19:31:50.302] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C8.dat
[19:31:50.302] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C9.dat
[19:31:50.302] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C10.dat
[19:31:50.302] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C11.dat
[19:31:50.302] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C12.dat
[19:31:50.302] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C13.dat
[19:31:50.302] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C14.dat
[19:31:50.302] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//readbackCal_C15.dat
[19:31:50.329] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[19:31:50.331] <TB2> INFO: PixTestReadback::doTest() done
[19:31:50.331] <TB2> INFO: Decoding statistics:
[19:31:50.331] <TB2> INFO: General information:
[19:31:50.331] <TB2> INFO: 16bit words read: 1536
[19:31:50.331] <TB2> INFO: valid events total: 256
[19:31:50.331] <TB2> INFO: empty events: 256
[19:31:50.331] <TB2> INFO: valid events with pixels: 0
[19:31:50.331] <TB2> INFO: valid pixel hits: 0
[19:31:50.331] <TB2> INFO: Event errors: 0
[19:31:50.331] <TB2> INFO: start marker: 0
[19:31:50.331] <TB2> INFO: stop marker: 0
[19:31:50.331] <TB2> INFO: overflow: 0
[19:31:50.331] <TB2> INFO: invalid 5bit words: 0
[19:31:50.331] <TB2> INFO: invalid XOR eye diagram: 0
[19:31:50.331] <TB2> INFO: frame (failed synchr.): 0
[19:31:50.331] <TB2> INFO: idle data (no TBM trl): 0
[19:31:50.331] <TB2> INFO: no data (only TBM hdr): 0
[19:31:50.331] <TB2> INFO: TBM errors: 0
[19:31:50.331] <TB2> INFO: flawed TBM headers: 0
[19:31:50.331] <TB2> INFO: flawed TBM trailers: 0
[19:31:50.331] <TB2> INFO: event ID mismatches: 0
[19:31:50.331] <TB2> INFO: ROC errors: 0
[19:31:50.331] <TB2> INFO: missing ROC header(s): 0
[19:31:50.331] <TB2> INFO: misplaced readback start: 0
[19:31:50.331] <TB2> INFO: Pixel decoding errors: 0
[19:31:50.331] <TB2> INFO: pixel data incomplete: 0
[19:31:50.331] <TB2> INFO: pixel address: 0
[19:31:50.331] <TB2> INFO: pulse height fill bit: 0
[19:31:50.331] <TB2> INFO: buffer corruption: 0
[19:31:50.395] <TB2> INFO: ######################################################################
[19:31:50.395] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[19:31:50.395] <TB2> INFO: ######################################################################
[19:31:50.400] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[19:31:50.437] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[19:31:50.437] <TB2> INFO: run 1 of 1
[19:31:50.673] <TB2> INFO: Expecting 3120000 events.
[19:32:22.617] <TB2> INFO: 668415 events read in total (31352ms).











[19:32:53.777] <TB2> INFO: 1333910 events read in total (62512ms).











[19:33:25.036] <TB2> INFO: 1998460 events read in total (93771ms).











[19:33:56.508] <TB2> INFO: 2664190 events read in total (125243ms).





















[19:34:18.913] <TB2> INFO: 3120000 events read in total (147648ms).
[19:34:18.991] <TB2> INFO: Test took 148555ms.
[19:34:39.284] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 168 seconds
[19:34:39.284] <TB2> INFO: number of dead bumps (per ROC): 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0
[19:34:39.284] <TB2> INFO: separation cut (per ROC): 103 107 102 108 107 107 104 109 97 95 104 100 111 96 106 108
[19:34:39.284] <TB2> INFO: Decoding statistics:
[19:34:39.284] <TB2> INFO: General information:
[19:34:39.284] <TB2> INFO: 16bit words read: 0
[19:34:39.284] <TB2> INFO: valid events total: 0
[19:34:39.284] <TB2> INFO: empty events: 0
[19:34:39.284] <TB2> INFO: valid events with pixels: 0
[19:34:39.284] <TB2> INFO: valid pixel hits: 0
[19:34:39.284] <TB2> INFO: Event errors: 0
[19:34:39.284] <TB2> INFO: start marker: 0
[19:34:39.284] <TB2> INFO: stop marker: 0
[19:34:39.284] <TB2> INFO: overflow: 0
[19:34:39.284] <TB2> INFO: invalid 5bit words: 0
[19:34:39.284] <TB2> INFO: invalid XOR eye diagram: 0
[19:34:39.284] <TB2> INFO: frame (failed synchr.): 0
[19:34:39.284] <TB2> INFO: idle data (no TBM trl): 0
[19:34:39.284] <TB2> INFO: no data (only TBM hdr): 0
[19:34:39.285] <TB2> INFO: TBM errors: 0
[19:34:39.285] <TB2> INFO: flawed TBM headers: 0
[19:34:39.285] <TB2> INFO: flawed TBM trailers: 0
[19:34:39.285] <TB2> INFO: event ID mismatches: 0
[19:34:39.285] <TB2> INFO: ROC errors: 0
[19:34:39.285] <TB2> INFO: missing ROC header(s): 0
[19:34:39.285] <TB2> INFO: misplaced readback start: 0
[19:34:39.285] <TB2> INFO: Pixel decoding errors: 0
[19:34:39.285] <TB2> INFO: pixel data incomplete: 0
[19:34:39.285] <TB2> INFO: pixel address: 0
[19:34:39.285] <TB2> INFO: pulse height fill bit: 0
[19:34:39.285] <TB2> INFO: buffer corruption: 0
[19:34:39.335] <TB2> INFO: ######################################################################
[19:34:39.335] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[19:34:39.335] <TB2> INFO: ######################################################################
[19:34:39.335] <TB2> INFO: ----------------------------------------------------------------------
[19:34:39.335] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[19:34:39.335] <TB2> INFO: ----------------------------------------------------------------------
[19:34:39.335] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[19:34:39.351] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[19:34:39.351] <TB2> INFO: run 1 of 1
[19:34:39.642] <TB2> INFO: Expecting 36608000 events.
[19:35:04.226] <TB2> INFO: 664450 events read in total (23992ms).
[19:35:27.748] <TB2> INFO: 1317800 events read in total (47514ms).
[19:35:51.026] <TB2> INFO: 1971800 events read in total (70792ms).
[19:36:14.633] <TB2> INFO: 2627600 events read in total (94399ms).
[19:36:38.139] <TB2> INFO: 3280700 events read in total (117905ms).
[19:37:01.332] <TB2> INFO: 3932900 events read in total (141098ms).
[19:37:24.910] <TB2> INFO: 4583800 events read in total (164676ms).
[19:37:48.434] <TB2> INFO: 5234600 events read in total (188200ms).
[19:38:11.887] <TB2> INFO: 5885450 events read in total (211653ms).
[19:38:34.889] <TB2> INFO: 6536500 events read in total (234655ms).
[19:38:58.447] <TB2> INFO: 7187450 events read in total (258213ms).
[19:39:21.599] <TB2> INFO: 7839200 events read in total (281365ms).
[19:39:45.233] <TB2> INFO: 8490700 events read in total (304999ms).
[19:40:08.457] <TB2> INFO: 9143400 events read in total (328223ms).
[19:40:31.963] <TB2> INFO: 9794100 events read in total (351729ms).
[19:40:55.123] <TB2> INFO: 10445200 events read in total (374889ms).
[19:41:18.547] <TB2> INFO: 11095600 events read in total (398313ms).
[19:41:41.718] <TB2> INFO: 11745350 events read in total (421484ms).
[19:42:05.044] <TB2> INFO: 12395200 events read in total (444810ms).
[19:42:28.428] <TB2> INFO: 13044750 events read in total (468194ms).
[19:42:51.472] <TB2> INFO: 13693050 events read in total (491238ms).
[19:43:14.597] <TB2> INFO: 14341550 events read in total (514363ms).
[19:43:37.719] <TB2> INFO: 14986550 events read in total (537485ms).
[19:44:00.864] <TB2> INFO: 15633250 events read in total (560630ms).
[19:44:24.340] <TB2> INFO: 16280450 events read in total (584106ms).
[19:44:48.087] <TB2> INFO: 16928700 events read in total (607853ms).
[19:45:11.207] <TB2> INFO: 17574650 events read in total (630973ms).
[19:45:34.535] <TB2> INFO: 18219500 events read in total (654301ms).
[19:45:58.045] <TB2> INFO: 18862900 events read in total (677811ms).
[19:46:21.530] <TB2> INFO: 19507250 events read in total (701296ms).
[19:46:44.834] <TB2> INFO: 20151700 events read in total (724600ms).
[19:47:07.940] <TB2> INFO: 20797700 events read in total (747706ms).
[19:47:31.308] <TB2> INFO: 21442400 events read in total (771074ms).
[19:47:54.925] <TB2> INFO: 22084800 events read in total (794691ms).
[19:48:18.404] <TB2> INFO: 22726400 events read in total (818170ms).
[19:48:41.732] <TB2> INFO: 23369450 events read in total (841498ms).
[19:49:04.805] <TB2> INFO: 24011100 events read in total (864571ms).
[19:49:28.039] <TB2> INFO: 24654050 events read in total (887805ms).
[19:49:50.896] <TB2> INFO: 25296350 events read in total (910662ms).
[19:50:14.098] <TB2> INFO: 25940200 events read in total (933864ms).
[19:50:37.095] <TB2> INFO: 26584000 events read in total (956861ms).
[19:51:00.926] <TB2> INFO: 27230200 events read in total (980692ms).
[19:51:23.794] <TB2> INFO: 27875000 events read in total (1003560ms).
[19:51:47.270] <TB2> INFO: 28518400 events read in total (1027036ms).
[19:52:10.426] <TB2> INFO: 29161350 events read in total (1050192ms).
[19:52:33.807] <TB2> INFO: 29803700 events read in total (1073573ms).
[19:52:56.806] <TB2> INFO: 30446000 events read in total (1096572ms).
[19:53:19.981] <TB2> INFO: 31088450 events read in total (1119747ms).
[19:53:42.973] <TB2> INFO: 31731600 events read in total (1142739ms).
[19:54:06.314] <TB2> INFO: 32375050 events read in total (1166080ms).
[19:54:29.478] <TB2> INFO: 33021650 events read in total (1189244ms).
[19:54:52.506] <TB2> INFO: 33667100 events read in total (1212272ms).
[19:55:15.563] <TB2> INFO: 34315400 events read in total (1235329ms).
[19:55:38.505] <TB2> INFO: 34960450 events read in total (1258271ms).
[19:56:01.792] <TB2> INFO: 35604850 events read in total (1281558ms).
[19:56:25.409] <TB2> INFO: 36256150 events read in total (1305175ms).
[19:56:38.206] <TB2> INFO: 36608000 events read in total (1317972ms).
[19:56:38.283] <TB2> INFO: Test took 1318932ms.
[19:56:38.664] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:56:40.213] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:56:41.764] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:56:43.873] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:56:46.337] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:56:48.794] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:56:51.232] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:56:53.674] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:56:56.156] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:56:58.168] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:56:59.001] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:57:01.450] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:57:02.930] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:57:04.441] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:57:05.937] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:57:07.638] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:57:09.807] <TB2> INFO: PixTestScurves::scurves() done
[19:57:09.807] <TB2> INFO: Vcal mean: 112.34 112.71 114.33 112.55 108.40 112.30 106.97 116.90 107.37 106.81 105.95 100.04 112.85 104.23 117.27 109.39
[19:57:09.807] <TB2> INFO: Vcal RMS: 5.03 4.74 5.63 5.17 4.73 4.93 4.61 5.22 4.84 6.18 4.90 5.33 5.10 5.45 5.35 4.85
[19:57:09.807] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1350 seconds
[19:57:09.807] <TB2> INFO: Decoding statistics:
[19:57:09.807] <TB2> INFO: General information:
[19:57:09.807] <TB2> INFO: 16bit words read: 0
[19:57:09.807] <TB2> INFO: valid events total: 0
[19:57:09.807] <TB2> INFO: empty events: 0
[19:57:09.807] <TB2> INFO: valid events with pixels: 0
[19:57:09.807] <TB2> INFO: valid pixel hits: 0
[19:57:09.807] <TB2> INFO: Event errors: 0
[19:57:09.807] <TB2> INFO: start marker: 0
[19:57:09.807] <TB2> INFO: stop marker: 0
[19:57:09.807] <TB2> INFO: overflow: 0
[19:57:09.807] <TB2> INFO: invalid 5bit words: 0
[19:57:09.807] <TB2> INFO: invalid XOR eye diagram: 0
[19:57:09.807] <TB2> INFO: frame (failed synchr.): 0
[19:57:09.807] <TB2> INFO: idle data (no TBM trl): 0
[19:57:09.807] <TB2> INFO: no data (only TBM hdr): 0
[19:57:09.807] <TB2> INFO: TBM errors: 0
[19:57:09.807] <TB2> INFO: flawed TBM headers: 0
[19:57:09.807] <TB2> INFO: flawed TBM trailers: 0
[19:57:09.807] <TB2> INFO: event ID mismatches: 0
[19:57:09.807] <TB2> INFO: ROC errors: 0
[19:57:09.807] <TB2> INFO: missing ROC header(s): 0
[19:57:09.807] <TB2> INFO: misplaced readback start: 0
[19:57:09.807] <TB2> INFO: Pixel decoding errors: 0
[19:57:09.807] <TB2> INFO: pixel data incomplete: 0
[19:57:09.807] <TB2> INFO: pixel address: 0
[19:57:09.807] <TB2> INFO: pulse height fill bit: 0
[19:57:09.807] <TB2> INFO: buffer corruption: 0
[19:57:09.873] <TB2> INFO: ######################################################################
[19:57:09.873] <TB2> INFO: PixTestTrim::doTest()
[19:57:09.873] <TB2> INFO: ######################################################################
[19:57:09.875] <TB2> INFO: ----------------------------------------------------------------------
[19:57:09.875] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[19:57:09.875] <TB2> INFO: ----------------------------------------------------------------------
[19:57:09.915] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[19:57:09.915] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[19:57:09.929] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[19:57:09.929] <TB2> INFO: run 1 of 1
[19:57:10.170] <TB2> INFO: Expecting 5025280 events.
[19:57:41.311] <TB2> INFO: 824088 events read in total (30532ms).
[19:58:12.201] <TB2> INFO: 1645952 events read in total (61422ms).
[19:58:43.064] <TB2> INFO: 2465352 events read in total (92286ms).
[19:59:14.170] <TB2> INFO: 3281080 events read in total (123391ms).
[19:59:44.854] <TB2> INFO: 4092592 events read in total (154076ms).
[20:00:15.645] <TB2> INFO: 4901568 events read in total (184866ms).
[20:00:20.658] <TB2> INFO: 5025280 events read in total (189879ms).
[20:00:20.730] <TB2> INFO: Test took 190801ms.
[20:00:38.078] <TB2> INFO: ROC 0 VthrComp = 115
[20:00:38.078] <TB2> INFO: ROC 1 VthrComp = 115
[20:00:38.078] <TB2> INFO: ROC 2 VthrComp = 112
[20:00:38.078] <TB2> INFO: ROC 3 VthrComp = 114
[20:00:38.078] <TB2> INFO: ROC 4 VthrComp = 116
[20:00:38.078] <TB2> INFO: ROC 5 VthrComp = 113
[20:00:38.079] <TB2> INFO: ROC 6 VthrComp = 109
[20:00:38.079] <TB2> INFO: ROC 7 VthrComp = 124
[20:00:38.079] <TB2> INFO: ROC 8 VthrComp = 108
[20:00:38.079] <TB2> INFO: ROC 9 VthrComp = 101
[20:00:38.080] <TB2> INFO: ROC 10 VthrComp = 106
[20:00:38.080] <TB2> INFO: ROC 11 VthrComp = 105
[20:00:38.080] <TB2> INFO: ROC 12 VthrComp = 123
[20:00:38.080] <TB2> INFO: ROC 13 VthrComp = 106
[20:00:38.080] <TB2> INFO: ROC 14 VthrComp = 121
[20:00:38.080] <TB2> INFO: ROC 15 VthrComp = 118
[20:00:38.318] <TB2> INFO: Expecting 41600 events.
[20:00:41.816] <TB2> INFO: 41600 events read in total (2906ms).
[20:00:41.817] <TB2> INFO: Test took 3735ms.
[20:00:41.829] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[20:00:41.829] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[20:00:41.843] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:00:41.843] <TB2> INFO: run 1 of 1
[20:00:42.121] <TB2> INFO: Expecting 5025280 events.
[20:01:08.983] <TB2> INFO: 589816 events read in total (26270ms).
[20:01:35.533] <TB2> INFO: 1178992 events read in total (52820ms).
[20:02:01.956] <TB2> INFO: 1768632 events read in total (79243ms).
[20:02:27.974] <TB2> INFO: 2358464 events read in total (105261ms).
[20:02:54.545] <TB2> INFO: 2946512 events read in total (131832ms).
[20:03:20.994] <TB2> INFO: 3533176 events read in total (158281ms).
[20:03:47.505] <TB2> INFO: 4118592 events read in total (184792ms).
[20:04:13.590] <TB2> INFO: 4703352 events read in total (210877ms).
[20:04:28.104] <TB2> INFO: 5025280 events read in total (225391ms).
[20:04:28.185] <TB2> INFO: Test took 226342ms.
[20:04:51.537] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 60.5473 for pixel 37/79 mean/min/max = 46.5552/32.0575/61.0529
[20:04:51.538] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 61.541 for pixel 4/59 mean/min/max = 47.0729/32.3254/61.8204
[20:04:51.538] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 67.343 for pixel 6/3 mean/min/max = 49.2572/31.1156/67.3987
[20:04:51.539] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 61.4003 for pixel 8/75 mean/min/max = 46.5178/31.5982/61.4374
[20:04:51.539] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 60.6436 for pixel 30/13 mean/min/max = 46.1717/31.6966/60.6468
[20:04:51.540] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 60.9016 for pixel 0/28 mean/min/max = 46.8558/32.6696/61.042
[20:04:51.540] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 61.8338 for pixel 20/12 mean/min/max = 47.9779/33.8102/62.1456
[20:04:51.541] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 59.3201 for pixel 23/19 mean/min/max = 45.7159/32.0352/59.3967
[20:04:51.541] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 62.4526 for pixel 22/70 mean/min/max = 48.6767/34.8479/62.5055
[20:04:51.542] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 68.3452 for pixel 0/16 mean/min/max = 49.7039/31.0456/68.3623
[20:04:51.542] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 63.5123 for pixel 48/39 mean/min/max = 49.1921/34.8632/63.5209
[20:04:51.543] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 60.9008 for pixel 13/4 mean/min/max = 47.6636/34.2905/61.0366
[20:04:51.543] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 58.4192 for pixel 4/19 mean/min/max = 45.094/31.4391/58.7489
[20:04:51.544] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 63.6838 for pixel 50/0 mean/min/max = 48.6678/33.6466/63.689
[20:04:51.544] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 59.6412 for pixel 51/16 mean/min/max = 46.152/32.5183/59.7856
[20:04:51.545] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 57.3897 for pixel 0/54 mean/min/max = 44.8095/31.827/57.7919
[20:04:51.546] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:04:51.634] <TB2> INFO: Expecting 411648 events.
[20:05:01.303] <TB2> INFO: 411648 events read in total (9077ms).
[20:05:01.309] <TB2> INFO: Expecting 411648 events.
[20:05:10.796] <TB2> INFO: 411648 events read in total (9084ms).
[20:05:10.806] <TB2> INFO: Expecting 411648 events.
[20:05:20.202] <TB2> INFO: 411648 events read in total (8993ms).
[20:05:20.215] <TB2> INFO: Expecting 411648 events.
[20:05:29.620] <TB2> INFO: 411648 events read in total (9002ms).
[20:05:29.636] <TB2> INFO: Expecting 411648 events.
[20:05:39.186] <TB2> INFO: 411648 events read in total (9147ms).
[20:05:39.206] <TB2> INFO: Expecting 411648 events.
[20:05:48.583] <TB2> INFO: 411648 events read in total (8974ms).
[20:05:48.612] <TB2> INFO: Expecting 411648 events.
[20:05:58.072] <TB2> INFO: 411648 events read in total (9057ms).
[20:05:58.096] <TB2> INFO: Expecting 411648 events.
[20:06:07.494] <TB2> INFO: 411648 events read in total (8995ms).
[20:06:07.521] <TB2> INFO: Expecting 411648 events.
[20:06:16.895] <TB2> INFO: 411648 events read in total (8971ms).
[20:06:17.010] <TB2> INFO: Expecting 411648 events.
[20:06:26.457] <TB2> INFO: 411648 events read in total (9044ms).
[20:06:26.534] <TB2> INFO: Expecting 411648 events.
[20:06:35.923] <TB2> INFO: 411648 events read in total (8986ms).
[20:06:36.046] <TB2> INFO: Expecting 411648 events.
[20:06:45.633] <TB2> INFO: 411648 events read in total (9184ms).
[20:06:45.745] <TB2> INFO: Expecting 411648 events.
[20:06:55.062] <TB2> INFO: 411648 events read in total (8914ms).
[20:06:55.115] <TB2> INFO: Expecting 411648 events.
[20:07:04.479] <TB2> INFO: 411648 events read in total (8961ms).
[20:07:04.642] <TB2> INFO: Expecting 411648 events.
[20:07:14.214] <TB2> INFO: 411648 events read in total (9169ms).
[20:07:14.333] <TB2> INFO: Expecting 411648 events.
[20:07:23.612] <TB2> INFO: 411648 events read in total (8876ms).
[20:07:23.709] <TB2> INFO: Test took 152164ms.
[20:07:24.462] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[20:07:24.475] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:07:24.475] <TB2> INFO: run 1 of 1
[20:07:24.710] <TB2> INFO: Expecting 5025280 events.
[20:07:51.726] <TB2> INFO: 587776 events read in total (26424ms).
[20:08:18.259] <TB2> INFO: 1173984 events read in total (52958ms).
[20:08:45.187] <TB2> INFO: 1759320 events read in total (79885ms).
[20:09:11.764] <TB2> INFO: 2343264 events read in total (106462ms).
[20:09:38.633] <TB2> INFO: 2927560 events read in total (133331ms).
[20:10:06.035] <TB2> INFO: 3513736 events read in total (160733ms).
[20:10:32.676] <TB2> INFO: 4099080 events read in total (187374ms).
[20:10:59.643] <TB2> INFO: 4683256 events read in total (214341ms).
[20:11:15.661] <TB2> INFO: 5025280 events read in total (230359ms).
[20:11:15.807] <TB2> INFO: Test took 231333ms.
[20:11:36.950] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 0.917280 .. 147.173709
[20:11:37.187] <TB2> INFO: Expecting 208000 events.
[20:11:47.274] <TB2> INFO: 208000 events read in total (9495ms).
[20:11:47.275] <TB2> INFO: Test took 10324ms.
[20:11:47.353] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 0 .. 157 (-1/-1) hits flags = 528 (plus default)
[20:11:47.370] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:11:47.370] <TB2> INFO: run 1 of 1
[20:11:47.667] <TB2> INFO: Expecting 5258240 events.
[20:12:13.002] <TB2> INFO: 584984 events read in total (25744ms).
[20:12:40.151] <TB2> INFO: 1170072 events read in total (51894ms).
[20:13:06.700] <TB2> INFO: 1754280 events read in total (78442ms).
[20:13:32.724] <TB2> INFO: 2338560 events read in total (104466ms).
[20:13:58.581] <TB2> INFO: 2923632 events read in total (130323ms).
[20:14:24.648] <TB2> INFO: 3508360 events read in total (156390ms).
[20:14:50.989] <TB2> INFO: 4093072 events read in total (182731ms).
[20:15:17.870] <TB2> INFO: 4676568 events read in total (209612ms).
[20:15:44.625] <TB2> INFO: 5258240 events read in total (236367ms).
[20:15:44.718] <TB2> INFO: Test took 237348ms.
[20:16:08.852] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.500000 .. 50.356693
[20:16:09.091] <TB2> INFO: Expecting 208000 events.
[20:16:18.964] <TB2> INFO: 208000 events read in total (9281ms).
[20:16:18.965] <TB2> INFO: Test took 10111ms.
[20:16:19.015] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 60 (-1/-1) hits flags = 528 (plus default)
[20:16:19.029] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:16:19.029] <TB2> INFO: run 1 of 1
[20:16:19.326] <TB2> INFO: Expecting 1464320 events.
[20:16:48.228] <TB2> INFO: 640832 events read in total (28311ms).
[20:17:16.227] <TB2> INFO: 1281104 events read in total (56310ms).
[20:17:24.680] <TB2> INFO: 1464320 events read in total (64763ms).
[20:17:24.729] <TB2> INFO: Test took 65701ms.
[20:17:37.329] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 26.304155 .. 48.130936
[20:17:37.567] <TB2> INFO: Expecting 208000 events.
[20:17:47.384] <TB2> INFO: 208000 events read in total (9226ms).
[20:17:47.385] <TB2> INFO: Test took 10054ms.
[20:17:47.433] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 58 (-1/-1) hits flags = 528 (plus default)
[20:17:47.447] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:17:47.447] <TB2> INFO: run 1 of 1
[20:17:47.730] <TB2> INFO: Expecting 1431040 events.
[20:18:16.293] <TB2> INFO: 652152 events read in total (27972ms).
[20:18:45.044] <TB2> INFO: 1303992 events read in total (56724ms).
[20:18:50.903] <TB2> INFO: 1431040 events read in total (62582ms).
[20:18:50.936] <TB2> INFO: Test took 63490ms.
[20:19:03.800] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 24.464093 .. 46.989726
[20:19:04.081] <TB2> INFO: Expecting 208000 events.
[20:19:14.438] <TB2> INFO: 208000 events read in total (9765ms).
[20:19:14.440] <TB2> INFO: Test took 10639ms.
[20:19:14.517] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 56 (-1/-1) hits flags = 528 (plus default)
[20:19:14.532] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:19:14.532] <TB2> INFO: run 1 of 1
[20:19:14.813] <TB2> INFO: Expecting 1431040 events.
[20:19:43.878] <TB2> INFO: 666632 events read in total (28474ms).
[20:20:12.284] <TB2> INFO: 1333224 events read in total (56881ms).
[20:20:16.685] <TB2> INFO: 1431040 events read in total (61281ms).
[20:20:16.728] <TB2> INFO: Test took 62197ms.
[20:20:28.714] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[20:20:28.714] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[20:20:28.731] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:20:28.731] <TB2> INFO: run 1 of 1
[20:20:28.968] <TB2> INFO: Expecting 1364480 events.
[20:20:58.149] <TB2> INFO: 666696 events read in total (28589ms).
[20:21:27.478] <TB2> INFO: 1333208 events read in total (57918ms).
[20:21:29.214] <TB2> INFO: 1364480 events read in total (59655ms).
[20:21:29.253] <TB2> INFO: Test took 60523ms.
[20:21:41.819] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C0.dat
[20:21:41.819] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C1.dat
[20:21:41.819] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C2.dat
[20:21:41.819] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C3.dat
[20:21:41.820] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C4.dat
[20:21:41.820] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C5.dat
[20:21:41.820] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C6.dat
[20:21:41.820] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C7.dat
[20:21:41.820] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C8.dat
[20:21:41.820] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C9.dat
[20:21:41.820] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C10.dat
[20:21:41.820] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C11.dat
[20:21:41.821] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C12.dat
[20:21:41.821] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C13.dat
[20:21:41.821] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C14.dat
[20:21:41.821] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C15.dat
[20:21:41.821] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters35_C0.dat
[20:21:41.829] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters35_C1.dat
[20:21:41.833] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters35_C2.dat
[20:21:41.838] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters35_C3.dat
[20:21:41.843] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters35_C4.dat
[20:21:41.847] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters35_C5.dat
[20:21:41.852] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters35_C6.dat
[20:21:41.857] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters35_C7.dat
[20:21:41.861] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters35_C8.dat
[20:21:41.866] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters35_C9.dat
[20:21:41.871] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters35_C10.dat
[20:21:41.876] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters35_C11.dat
[20:21:41.881] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters35_C12.dat
[20:21:41.885] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters35_C13.dat
[20:21:41.890] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters35_C14.dat
[20:21:41.895] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//trimParameters35_C15.dat
[20:21:41.900] <TB2> INFO: PixTestTrim::trimTest() done
[20:21:41.900] <TB2> INFO: vtrim: 117 136 158 131 144 116 135 130 131 107 134 120 119 139 124 108
[20:21:41.900] <TB2> INFO: vthrcomp: 115 115 112 114 116 113 109 124 108 101 106 105 123 106 121 118
[20:21:41.900] <TB2> INFO: vcal mean: 35.05 34.96 35.04 34.97 35.01 35.00 35.01 35.00 35.06 35.11 35.09 34.98 34.99 35.05 34.74 34.97
[20:21:41.900] <TB2> INFO: vcal RMS: 1.03 1.21 1.26 1.13 1.08 1.02 1.03 1.02 1.08 1.21 1.08 0.97 0.98 1.02 1.12 1.03
[20:21:41.900] <TB2> INFO: bits mean: 9.24 9.44 9.31 9.81 9.83 8.83 9.22 9.69 8.92 8.52 8.70 8.99 9.83 9.08 9.24 9.54
[20:21:41.900] <TB2> INFO: bits RMS: 2.77 2.65 2.73 2.54 2.59 2.89 2.49 2.66 2.47 3.00 2.49 2.48 2.64 2.46 2.79 2.80
[20:21:41.907] <TB2> INFO: ----------------------------------------------------------------------
[20:21:41.907] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[20:21:41.907] <TB2> INFO: ----------------------------------------------------------------------
[20:21:41.911] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[20:21:41.923] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[20:21:41.923] <TB2> INFO: run 1 of 1
[20:21:42.160] <TB2> INFO: Expecting 4160000 events.
[20:22:15.427] <TB2> INFO: 743850 events read in total (32676ms).
[20:22:47.985] <TB2> INFO: 1481095 events read in total (65234ms).
[20:23:20.603] <TB2> INFO: 2211900 events read in total (97852ms).
[20:23:52.510] <TB2> INFO: 2937625 events read in total (129759ms).
[20:24:24.435] <TB2> INFO: 3659195 events read in total (161684ms).
[20:24:46.670] <TB2> INFO: 4160000 events read in total (183919ms).
[20:24:46.752] <TB2> INFO: Test took 184828ms.
[20:25:09.166] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 193 (-1/-1) hits flags = 528 (plus default)
[20:25:09.180] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[20:25:09.180] <TB2> INFO: run 1 of 1
[20:25:09.416] <TB2> INFO: Expecting 4035200 events.
[20:25:42.196] <TB2> INFO: 724460 events read in total (32188ms).
[20:26:14.360] <TB2> INFO: 1443660 events read in total (64352ms).
[20:26:46.305] <TB2> INFO: 2155845 events read in total (96297ms).
[20:27:18.017] <TB2> INFO: 2863855 events read in total (128009ms).
[20:27:49.113] <TB2> INFO: 3568990 events read in total (159105ms).
[20:28:10.070] <TB2> INFO: 4035200 events read in total (180062ms).
[20:28:10.197] <TB2> INFO: Test took 181017ms.
[20:28:35.372] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 177 (-1/-1) hits flags = 528 (plus default)
[20:28:35.386] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[20:28:35.387] <TB2> INFO: run 1 of 1
[20:28:35.624] <TB2> INFO: Expecting 3702400 events.
[20:29:08.553] <TB2> INFO: 749460 events read in total (32338ms).
[20:29:40.630] <TB2> INFO: 1491500 events read in total (64415ms).
[20:30:12.797] <TB2> INFO: 2225675 events read in total (96582ms).
[20:30:45.154] <TB2> INFO: 2954595 events read in total (128939ms).
[20:31:17.534] <TB2> INFO: 3683245 events read in total (161319ms).
[20:31:18.733] <TB2> INFO: 3702400 events read in total (162518ms).
[20:31:18.794] <TB2> INFO: Test took 163408ms.
[20:31:41.122] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 179 (-1/-1) hits flags = 528 (plus default)
[20:31:41.136] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[20:31:41.137] <TB2> INFO: run 1 of 1
[20:31:41.377] <TB2> INFO: Expecting 3744000 events.
[20:32:14.640] <TB2> INFO: 746680 events read in total (32671ms).
[20:32:47.339] <TB2> INFO: 1485895 events read in total (65370ms).
[20:33:19.346] <TB2> INFO: 2217840 events read in total (97377ms).
[20:33:51.575] <TB2> INFO: 2944310 events read in total (129606ms).
[20:34:23.962] <TB2> INFO: 3669675 events read in total (161993ms).
[20:34:27.652] <TB2> INFO: 3744000 events read in total (165683ms).
[20:34:27.716] <TB2> INFO: Test took 166579ms.
[20:34:49.901] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 178 (-1/-1) hits flags = 528 (plus default)
[20:34:49.916] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[20:34:49.916] <TB2> INFO: run 1 of 1
[20:34:50.214] <TB2> INFO: Expecting 3723200 events.
[20:35:23.751] <TB2> INFO: 748595 events read in total (32947ms).
[20:35:56.255] <TB2> INFO: 1489685 events read in total (65450ms).
[20:36:28.602] <TB2> INFO: 2223010 events read in total (97797ms).
[20:37:01.075] <TB2> INFO: 2951120 events read in total (130270ms).
[20:37:33.332] <TB2> INFO: 3678065 events read in total (162527ms).
[20:37:35.724] <TB2> INFO: 3723200 events read in total (164919ms).
[20:37:35.788] <TB2> INFO: Test took 165873ms.
[20:37:57.519] <TB2> INFO: PixTestTrim::trimBitTest() done
[20:37:57.520] <TB2> INFO: PixTestTrim::doTest() done, duration: 2447 seconds
[20:37:57.520] <TB2> INFO: Decoding statistics:
[20:37:57.520] <TB2> INFO: General information:
[20:37:57.520] <TB2> INFO: 16bit words read: 0
[20:37:57.520] <TB2> INFO: valid events total: 0
[20:37:57.520] <TB2> INFO: empty events: 0
[20:37:57.520] <TB2> INFO: valid events with pixels: 0
[20:37:57.520] <TB2> INFO: valid pixel hits: 0
[20:37:57.520] <TB2> INFO: Event errors: 0
[20:37:57.520] <TB2> INFO: start marker: 0
[20:37:57.520] <TB2> INFO: stop marker: 0
[20:37:57.520] <TB2> INFO: overflow: 0
[20:37:57.520] <TB2> INFO: invalid 5bit words: 0
[20:37:57.520] <TB2> INFO: invalid XOR eye diagram: 0
[20:37:57.520] <TB2> INFO: frame (failed synchr.): 0
[20:37:57.520] <TB2> INFO: idle data (no TBM trl): 0
[20:37:57.520] <TB2> INFO: no data (only TBM hdr): 0
[20:37:57.520] <TB2> INFO: TBM errors: 0
[20:37:57.520] <TB2> INFO: flawed TBM headers: 0
[20:37:57.520] <TB2> INFO: flawed TBM trailers: 0
[20:37:57.520] <TB2> INFO: event ID mismatches: 0
[20:37:57.520] <TB2> INFO: ROC errors: 0
[20:37:57.520] <TB2> INFO: missing ROC header(s): 0
[20:37:57.520] <TB2> INFO: misplaced readback start: 0
[20:37:57.520] <TB2> INFO: Pixel decoding errors: 0
[20:37:57.520] <TB2> INFO: pixel data incomplete: 0
[20:37:57.520] <TB2> INFO: pixel address: 0
[20:37:57.520] <TB2> INFO: pulse height fill bit: 0
[20:37:57.520] <TB2> INFO: buffer corruption: 0
[20:37:58.296] <TB2> INFO: ######################################################################
[20:37:58.296] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[20:37:58.296] <TB2> INFO: ######################################################################
[20:37:58.583] <TB2> INFO: Expecting 41600 events.
[20:38:02.049] <TB2> INFO: 41600 events read in total (2874ms).
[20:38:02.050] <TB2> INFO: Test took 3753ms.
[20:38:02.488] <TB2> INFO: Expecting 41600 events.
[20:38:05.986] <TB2> INFO: 41600 events read in total (2906ms).
[20:38:05.987] <TB2> INFO: Test took 3734ms.
[20:38:06.306] <TB2> INFO: Expecting 41600 events.
[20:38:09.909] <TB2> INFO: 41600 events read in total (3011ms).
[20:38:09.910] <TB2> INFO: Test took 3899ms.
[20:38:10.229] <TB2> INFO: Expecting 41600 events.
[20:38:13.732] <TB2> INFO: 41600 events read in total (2911ms).
[20:38:13.733] <TB2> INFO: Test took 3795ms.
[20:38:14.022] <TB2> INFO: Expecting 41600 events.
[20:38:17.595] <TB2> INFO: 41600 events read in total (2982ms).
[20:38:17.596] <TB2> INFO: Test took 3839ms.
[20:38:17.885] <TB2> INFO: Expecting 41600 events.
[20:38:21.401] <TB2> INFO: 41600 events read in total (2925ms).
[20:38:21.402] <TB2> INFO: Test took 3782ms.
[20:38:21.691] <TB2> INFO: Expecting 41600 events.
[20:38:25.216] <TB2> INFO: 41600 events read in total (2933ms).
[20:38:25.217] <TB2> INFO: Test took 3791ms.
[20:38:25.506] <TB2> INFO: Expecting 41600 events.
[20:38:29.005] <TB2> INFO: 41600 events read in total (2908ms).
[20:38:29.006] <TB2> INFO: Test took 3765ms.
[20:38:29.305] <TB2> INFO: Expecting 41600 events.
[20:38:32.860] <TB2> INFO: 41600 events read in total (2963ms).
[20:38:32.861] <TB2> INFO: Test took 3831ms.
[20:38:33.154] <TB2> INFO: Expecting 41600 events.
[20:38:36.759] <TB2> INFO: 41600 events read in total (3014ms).
[20:38:36.760] <TB2> INFO: Test took 3871ms.
[20:38:37.049] <TB2> INFO: Expecting 41600 events.
[20:38:40.577] <TB2> INFO: 41600 events read in total (2936ms).
[20:38:40.578] <TB2> INFO: Test took 3794ms.
[20:38:40.868] <TB2> INFO: Expecting 41600 events.
[20:38:44.449] <TB2> INFO: 41600 events read in total (2990ms).
[20:38:44.451] <TB2> INFO: Test took 3848ms.
[20:38:44.767] <TB2> INFO: Expecting 41600 events.
[20:38:48.419] <TB2> INFO: 41600 events read in total (3060ms).
[20:38:48.420] <TB2> INFO: Test took 3945ms.
[20:38:48.713] <TB2> INFO: Expecting 41600 events.
[20:38:52.369] <TB2> INFO: 41600 events read in total (3064ms).
[20:38:52.370] <TB2> INFO: Test took 3922ms.
[20:38:52.660] <TB2> INFO: Expecting 41600 events.
[20:38:56.278] <TB2> INFO: 41600 events read in total (3027ms).
[20:38:56.279] <TB2> INFO: Test took 3884ms.
[20:38:56.569] <TB2> INFO: Expecting 41600 events.
[20:39:00.113] <TB2> INFO: 41600 events read in total (2953ms).
[20:39:00.114] <TB2> INFO: Test took 3810ms.
[20:39:00.423] <TB2> INFO: Expecting 41600 events.
[20:39:04.160] <TB2> INFO: 41600 events read in total (3145ms).
[20:39:04.161] <TB2> INFO: Test took 4022ms.
[20:39:04.450] <TB2> INFO: Expecting 41600 events.
[20:39:08.089] <TB2> INFO: 41600 events read in total (3048ms).
[20:39:08.090] <TB2> INFO: Test took 3905ms.
[20:39:08.444] <TB2> INFO: Expecting 41600 events.
[20:39:11.935] <TB2> INFO: 41600 events read in total (2899ms).
[20:39:11.936] <TB2> INFO: Test took 3817ms.
[20:39:12.258] <TB2> INFO: Expecting 41600 events.
[20:39:15.891] <TB2> INFO: 41600 events read in total (3041ms).
[20:39:15.892] <TB2> INFO: Test took 3931ms.
[20:39:16.185] <TB2> INFO: Expecting 41600 events.
[20:39:19.785] <TB2> INFO: 41600 events read in total (3008ms).
[20:39:19.785] <TB2> INFO: Test took 3865ms.
[20:39:20.113] <TB2> INFO: Expecting 41600 events.
[20:39:23.664] <TB2> INFO: 41600 events read in total (2959ms).
[20:39:23.665] <TB2> INFO: Test took 3855ms.
[20:39:23.954] <TB2> INFO: Expecting 41600 events.
[20:39:27.582] <TB2> INFO: 41600 events read in total (3036ms).
[20:39:27.582] <TB2> INFO: Test took 3892ms.
[20:39:27.873] <TB2> INFO: Expecting 41600 events.
[20:39:31.393] <TB2> INFO: 41600 events read in total (2929ms).
[20:39:31.393] <TB2> INFO: Test took 3785ms.
[20:39:31.682] <TB2> INFO: Expecting 41600 events.
[20:39:35.356] <TB2> INFO: 41600 events read in total (3082ms).
[20:39:35.357] <TB2> INFO: Test took 3940ms.
[20:39:35.656] <TB2> INFO: Expecting 41600 events.
[20:39:39.216] <TB2> INFO: 41600 events read in total (2968ms).
[20:39:39.217] <TB2> INFO: Test took 3834ms.
[20:39:39.506] <TB2> INFO: Expecting 41600 events.
[20:39:43.104] <TB2> INFO: 41600 events read in total (3006ms).
[20:39:43.104] <TB2> INFO: Test took 3863ms.
[20:39:43.393] <TB2> INFO: Expecting 41600 events.
[20:39:46.916] <TB2> INFO: 41600 events read in total (2931ms).
[20:39:46.917] <TB2> INFO: Test took 3788ms.
[20:39:47.205] <TB2> INFO: Expecting 41600 events.
[20:39:50.765] <TB2> INFO: 41600 events read in total (2968ms).
[20:39:50.766] <TB2> INFO: Test took 3825ms.
[20:39:51.059] <TB2> INFO: Expecting 41600 events.
[20:39:54.705] <TB2> INFO: 41600 events read in total (3055ms).
[20:39:54.705] <TB2> INFO: Test took 3911ms.
[20:39:54.994] <TB2> INFO: Expecting 41600 events.
[20:39:58.616] <TB2> INFO: 41600 events read in total (3030ms).
[20:39:58.617] <TB2> INFO: Test took 3887ms.
[20:39:58.910] <TB2> INFO: Expecting 41600 events.
[20:40:02.661] <TB2> INFO: 41600 events read in total (3159ms).
[20:40:02.662] <TB2> INFO: Test took 4017ms.
[20:40:02.981] <TB2> INFO: Expecting 41600 events.
[20:40:06.579] <TB2> INFO: 41600 events read in total (3006ms).
[20:40:06.579] <TB2> INFO: Test took 3890ms.
[20:40:06.868] <TB2> INFO: Expecting 41600 events.
[20:40:10.453] <TB2> INFO: 41600 events read in total (2993ms).
[20:40:10.454] <TB2> INFO: Test took 3851ms.
[20:40:10.747] <TB2> INFO: Expecting 41600 events.
[20:40:14.358] <TB2> INFO: 41600 events read in total (3020ms).
[20:40:14.358] <TB2> INFO: Test took 3876ms.
[20:40:14.647] <TB2> INFO: Expecting 41600 events.
[20:40:18.229] <TB2> INFO: 41600 events read in total (2990ms).
[20:40:18.229] <TB2> INFO: Test took 3846ms.
[20:40:18.523] <TB2> INFO: Expecting 41600 events.
[20:40:22.263] <TB2> INFO: 41600 events read in total (3149ms).
[20:40:22.264] <TB2> INFO: Test took 4006ms.
[20:40:22.554] <TB2> INFO: Expecting 41600 events.
[20:40:26.207] <TB2> INFO: 41600 events read in total (3062ms).
[20:40:26.208] <TB2> INFO: Test took 3919ms.
[20:40:26.497] <TB2> INFO: Expecting 41600 events.
[20:40:30.121] <TB2> INFO: 41600 events read in total (3032ms).
[20:40:30.122] <TB2> INFO: Test took 3889ms.
[20:40:30.411] <TB2> INFO: Expecting 41600 events.
[20:40:34.016] <TB2> INFO: 41600 events read in total (3013ms).
[20:40:34.017] <TB2> INFO: Test took 3871ms.
[20:40:34.317] <TB2> INFO: Expecting 41600 events.
[20:40:37.821] <TB2> INFO: 41600 events read in total (2912ms).
[20:40:37.822] <TB2> INFO: Test took 3777ms.
[20:40:38.115] <TB2> INFO: Expecting 41600 events.
[20:40:41.704] <TB2> INFO: 41600 events read in total (2999ms).
[20:40:41.705] <TB2> INFO: Test took 3855ms.
[20:40:41.994] <TB2> INFO: Expecting 41600 events.
[20:40:45.635] <TB2> INFO: 41600 events read in total (3049ms).
[20:40:45.636] <TB2> INFO: Test took 3907ms.
[20:40:45.928] <TB2> INFO: Expecting 41600 events.
[20:40:49.546] <TB2> INFO: 41600 events read in total (3026ms).
[20:40:49.547] <TB2> INFO: Test took 3883ms.
[20:40:49.836] <TB2> INFO: Expecting 41600 events.
[20:40:53.498] <TB2> INFO: 41600 events read in total (3071ms).
[20:40:53.499] <TB2> INFO: Test took 3928ms.
[20:40:53.791] <TB2> INFO: Expecting 41600 events.
[20:40:57.406] <TB2> INFO: 41600 events read in total (3023ms).
[20:40:57.407] <TB2> INFO: Test took 3880ms.
[20:40:57.701] <TB2> INFO: Expecting 41600 events.
[20:41:01.240] <TB2> INFO: 41600 events read in total (2948ms).
[20:41:01.241] <TB2> INFO: Test took 3805ms.
[20:41:01.531] <TB2> INFO: Expecting 41600 events.
[20:41:05.221] <TB2> INFO: 41600 events read in total (3099ms).
[20:41:05.221] <TB2> INFO: Test took 3955ms.
[20:41:05.542] <TB2> INFO: Expecting 41600 events.
[20:41:09.260] <TB2> INFO: 41600 events read in total (3126ms).
[20:41:09.261] <TB2> INFO: Test took 4015ms.
[20:41:09.549] <TB2> INFO: Expecting 41600 events.
[20:41:13.125] <TB2> INFO: 41600 events read in total (2984ms).
[20:41:13.126] <TB2> INFO: Test took 3841ms.
[20:41:13.416] <TB2> INFO: Expecting 41600 events.
[20:41:16.947] <TB2> INFO: 41600 events read in total (2940ms).
[20:41:16.948] <TB2> INFO: Test took 3798ms.
[20:41:17.237] <TB2> INFO: Expecting 41600 events.
[20:41:20.743] <TB2> INFO: 41600 events read in total (2914ms).
[20:41:20.744] <TB2> INFO: Test took 3772ms.
[20:41:21.033] <TB2> INFO: Expecting 41600 events.
[20:41:24.557] <TB2> INFO: 41600 events read in total (2933ms).
[20:41:24.558] <TB2> INFO: Test took 3790ms.
[20:41:24.850] <TB2> INFO: Expecting 41600 events.
[20:41:28.370] <TB2> INFO: 41600 events read in total (2929ms).
[20:41:28.370] <TB2> INFO: Test took 3785ms.
[20:41:28.659] <TB2> INFO: Expecting 2560 events.
[20:41:29.553] <TB2> INFO: 2560 events read in total (302ms).
[20:41:29.554] <TB2> INFO: Test took 1171ms.
[20:41:29.862] <TB2> INFO: Expecting 2560 events.
[20:41:30.750] <TB2> INFO: 2560 events read in total (298ms).
[20:41:30.751] <TB2> INFO: Test took 1197ms.
[20:41:31.058] <TB2> INFO: Expecting 2560 events.
[20:41:31.944] <TB2> INFO: 2560 events read in total (294ms).
[20:41:31.944] <TB2> INFO: Test took 1193ms.
[20:41:32.252] <TB2> INFO: Expecting 2560 events.
[20:41:33.144] <TB2> INFO: 2560 events read in total (301ms).
[20:41:33.145] <TB2> INFO: Test took 1201ms.
[20:41:33.453] <TB2> INFO: Expecting 2560 events.
[20:41:34.341] <TB2> INFO: 2560 events read in total (296ms).
[20:41:34.342] <TB2> INFO: Test took 1196ms.
[20:41:34.648] <TB2> INFO: Expecting 2560 events.
[20:41:35.532] <TB2> INFO: 2560 events read in total (292ms).
[20:41:35.532] <TB2> INFO: Test took 1190ms.
[20:41:35.841] <TB2> INFO: Expecting 2560 events.
[20:41:36.728] <TB2> INFO: 2560 events read in total (295ms).
[20:41:36.728] <TB2> INFO: Test took 1195ms.
[20:41:37.036] <TB2> INFO: Expecting 2560 events.
[20:41:37.923] <TB2> INFO: 2560 events read in total (295ms).
[20:41:37.923] <TB2> INFO: Test took 1194ms.
[20:41:38.231] <TB2> INFO: Expecting 2560 events.
[20:41:39.121] <TB2> INFO: 2560 events read in total (298ms).
[20:41:39.122] <TB2> INFO: Test took 1198ms.
[20:41:39.429] <TB2> INFO: Expecting 2560 events.
[20:41:40.316] <TB2> INFO: 2560 events read in total (295ms).
[20:41:40.316] <TB2> INFO: Test took 1194ms.
[20:41:40.624] <TB2> INFO: Expecting 2560 events.
[20:41:41.510] <TB2> INFO: 2560 events read in total (294ms).
[20:41:41.510] <TB2> INFO: Test took 1193ms.
[20:41:41.818] <TB2> INFO: Expecting 2560 events.
[20:41:42.698] <TB2> INFO: 2560 events read in total (289ms).
[20:41:42.699] <TB2> INFO: Test took 1188ms.
[20:41:43.006] <TB2> INFO: Expecting 2560 events.
[20:41:43.896] <TB2> INFO: 2560 events read in total (298ms).
[20:41:43.896] <TB2> INFO: Test took 1197ms.
[20:41:44.204] <TB2> INFO: Expecting 2560 events.
[20:41:45.094] <TB2> INFO: 2560 events read in total (298ms).
[20:41:45.094] <TB2> INFO: Test took 1197ms.
[20:41:45.402] <TB2> INFO: Expecting 2560 events.
[20:41:46.296] <TB2> INFO: 2560 events read in total (302ms).
[20:41:46.297] <TB2> INFO: Test took 1203ms.
[20:41:46.604] <TB2> INFO: Expecting 2560 events.
[20:41:47.489] <TB2> INFO: 2560 events read in total (294ms).
[20:41:47.490] <TB2> INFO: Test took 1193ms.
[20:41:47.797] <TB2> INFO: Expecting 655360 events.
[20:42:09.150] <TB2> INFO: 531260 events read in total (20761ms).
[20:42:14.205] <TB2> INFO: 655360 events read in total (25816ms).
[20:42:14.222] <TB2> INFO: Test took 26729ms.
[20:42:14.250] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:42:14.512] <TB2> INFO: Expecting 655360 events.
[20:42:29.702] <TB2> INFO: 655360 events read in total (14598ms).
[20:42:29.717] <TB2> INFO: Expecting 655360 events.
[20:42:44.567] <TB2> INFO: 655360 events read in total (14447ms).
[20:42:44.586] <TB2> INFO: Expecting 655360 events.
[20:42:59.234] <TB2> INFO: 655360 events read in total (14245ms).
[20:42:59.257] <TB2> INFO: Expecting 655360 events.
[20:43:13.803] <TB2> INFO: 655360 events read in total (14143ms).
[20:43:13.829] <TB2> INFO: Expecting 655360 events.
[20:43:28.603] <TB2> INFO: 655360 events read in total (14371ms).
[20:43:28.638] <TB2> INFO: Expecting 655360 events.
[20:43:43.484] <TB2> INFO: 655360 events read in total (14443ms).
[20:43:43.547] <TB2> INFO: Expecting 655360 events.
[20:43:58.251] <TB2> INFO: 655360 events read in total (14301ms).
[20:43:58.350] <TB2> INFO: Expecting 655360 events.
[20:44:13.147] <TB2> INFO: 655360 events read in total (14394ms).
[20:44:13.189] <TB2> INFO: Expecting 655360 events.
[20:44:28.020] <TB2> INFO: 655360 events read in total (14427ms).
[20:44:28.066] <TB2> INFO: Expecting 655360 events.
[20:44:42.769] <TB2> INFO: 655360 events read in total (14300ms).
[20:44:42.844] <TB2> INFO: Expecting 655360 events.
[20:44:57.765] <TB2> INFO: 655360 events read in total (14518ms).
[20:44:57.841] <TB2> INFO: Expecting 655360 events.
[20:45:12.688] <TB2> INFO: 655360 events read in total (14444ms).
[20:45:12.808] <TB2> INFO: Expecting 655360 events.
[20:45:27.721] <TB2> INFO: 655360 events read in total (14510ms).
[20:45:27.808] <TB2> INFO: Expecting 655360 events.
[20:45:42.861] <TB2> INFO: 655360 events read in total (14650ms).
[20:45:42.984] <TB2> INFO: Expecting 655360 events.
[20:45:57.691] <TB2> INFO: 655360 events read in total (14304ms).
[20:45:57.835] <TB2> INFO: Expecting 655360 events.
[20:46:12.383] <TB2> INFO: 655360 events read in total (14145ms).
[20:46:12.481] <TB2> INFO: Test took 238232ms.
[20:46:12.720] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:46:12.729] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:46:12.738] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:46:12.747] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:46:12.756] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[20:46:12.765] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[20:46:12.774] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[20:46:12.783] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[20:46:12.792] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[20:46:12.801] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[20:46:12.810] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:46:12.819] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:46:12.828] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:46:12.837] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:46:12.846] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[20:46:12.855] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[20:46:12.864] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[20:46:12.873] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:46:12.882] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[20:46:12.891] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[20:46:12.900] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:46:12.909] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:46:12.918] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:46:12.926] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[20:46:12.936] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[20:46:12.945] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[20:46:12.955] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[20:46:12.965] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:46:12.975] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[20:46:12.984] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[20:46:12.994] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[20:46:13.003] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[20:46:13.012] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[20:46:13.021] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:46:13.030] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:46:13.039] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:46:13.076] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C0.dat
[20:46:13.076] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C1.dat
[20:46:13.076] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C2.dat
[20:46:13.076] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C3.dat
[20:46:13.076] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C4.dat
[20:46:13.076] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C5.dat
[20:46:13.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C6.dat
[20:46:13.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C7.dat
[20:46:13.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C8.dat
[20:46:13.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C9.dat
[20:46:13.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C10.dat
[20:46:13.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C11.dat
[20:46:13.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C12.dat
[20:46:13.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C13.dat
[20:46:13.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C14.dat
[20:46:13.077] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//dacParameters35_C15.dat
[20:46:13.320] <TB2> INFO: Expecting 41600 events.
[20:46:16.471] <TB2> INFO: 41600 events read in total (2560ms).
[20:46:16.471] <TB2> INFO: Test took 3391ms.
[20:46:16.933] <TB2> INFO: Expecting 41600 events.
[20:46:20.014] <TB2> INFO: 41600 events read in total (2490ms).
[20:46:20.015] <TB2> INFO: Test took 3332ms.
[20:46:20.537] <TB2> INFO: Expecting 41600 events.
[20:46:23.726] <TB2> INFO: 41600 events read in total (2598ms).
[20:46:23.726] <TB2> INFO: Test took 3496ms.
[20:46:23.946] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:24.035] <TB2> INFO: Expecting 2560 events.
[20:46:24.923] <TB2> INFO: 2560 events read in total (296ms).
[20:46:24.923] <TB2> INFO: Test took 977ms.
[20:46:24.925] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:25.232] <TB2> INFO: Expecting 2560 events.
[20:46:26.120] <TB2> INFO: 2560 events read in total (297ms).
[20:46:26.120] <TB2> INFO: Test took 1195ms.
[20:46:26.123] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:26.429] <TB2> INFO: Expecting 2560 events.
[20:46:27.319] <TB2> INFO: 2560 events read in total (298ms).
[20:46:27.319] <TB2> INFO: Test took 1196ms.
[20:46:27.321] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:27.627] <TB2> INFO: Expecting 2560 events.
[20:46:28.514] <TB2> INFO: 2560 events read in total (295ms).
[20:46:28.515] <TB2> INFO: Test took 1194ms.
[20:46:28.518] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:28.823] <TB2> INFO: Expecting 2560 events.
[20:46:29.707] <TB2> INFO: 2560 events read in total (292ms).
[20:46:29.708] <TB2> INFO: Test took 1190ms.
[20:46:29.710] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:30.015] <TB2> INFO: Expecting 2560 events.
[20:46:30.899] <TB2> INFO: 2560 events read in total (292ms).
[20:46:30.899] <TB2> INFO: Test took 1189ms.
[20:46:30.902] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:31.207] <TB2> INFO: Expecting 2560 events.
[20:46:32.092] <TB2> INFO: 2560 events read in total (293ms).
[20:46:32.093] <TB2> INFO: Test took 1191ms.
[20:46:32.096] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:32.401] <TB2> INFO: Expecting 2560 events.
[20:46:33.291] <TB2> INFO: 2560 events read in total (298ms).
[20:46:33.291] <TB2> INFO: Test took 1195ms.
[20:46:33.294] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:33.600] <TB2> INFO: Expecting 2560 events.
[20:46:34.485] <TB2> INFO: 2560 events read in total (293ms).
[20:46:34.486] <TB2> INFO: Test took 1192ms.
[20:46:34.489] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:34.794] <TB2> INFO: Expecting 2560 events.
[20:46:35.680] <TB2> INFO: 2560 events read in total (295ms).
[20:46:35.680] <TB2> INFO: Test took 1191ms.
[20:46:35.683] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:35.989] <TB2> INFO: Expecting 2560 events.
[20:46:36.875] <TB2> INFO: 2560 events read in total (294ms).
[20:46:36.875] <TB2> INFO: Test took 1192ms.
[20:46:36.878] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:37.183] <TB2> INFO: Expecting 2560 events.
[20:46:38.074] <TB2> INFO: 2560 events read in total (299ms).
[20:46:38.075] <TB2> INFO: Test took 1197ms.
[20:46:38.077] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:38.383] <TB2> INFO: Expecting 2560 events.
[20:46:39.272] <TB2> INFO: 2560 events read in total (298ms).
[20:46:39.273] <TB2> INFO: Test took 1196ms.
[20:46:39.279] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:39.580] <TB2> INFO: Expecting 2560 events.
[20:46:40.458] <TB2> INFO: 2560 events read in total (287ms).
[20:46:40.458] <TB2> INFO: Test took 1179ms.
[20:46:40.461] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:40.767] <TB2> INFO: Expecting 2560 events.
[20:46:41.657] <TB2> INFO: 2560 events read in total (298ms).
[20:46:41.657] <TB2> INFO: Test took 1196ms.
[20:46:41.661] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:41.965] <TB2> INFO: Expecting 2560 events.
[20:46:42.850] <TB2> INFO: 2560 events read in total (294ms).
[20:46:42.851] <TB2> INFO: Test took 1190ms.
[20:46:42.853] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:43.158] <TB2> INFO: Expecting 2560 events.
[20:46:44.047] <TB2> INFO: 2560 events read in total (297ms).
[20:46:44.047] <TB2> INFO: Test took 1194ms.
[20:46:44.049] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:44.355] <TB2> INFO: Expecting 2560 events.
[20:46:45.243] <TB2> INFO: 2560 events read in total (297ms).
[20:46:45.244] <TB2> INFO: Test took 1195ms.
[20:46:45.246] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:45.552] <TB2> INFO: Expecting 2560 events.
[20:46:46.440] <TB2> INFO: 2560 events read in total (296ms).
[20:46:46.440] <TB2> INFO: Test took 1195ms.
[20:46:46.443] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:46.748] <TB2> INFO: Expecting 2560 events.
[20:46:47.631] <TB2> INFO: 2560 events read in total (292ms).
[20:46:47.632] <TB2> INFO: Test took 1189ms.
[20:46:47.634] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:47.940] <TB2> INFO: Expecting 2560 events.
[20:46:48.825] <TB2> INFO: 2560 events read in total (293ms).
[20:46:48.825] <TB2> INFO: Test took 1191ms.
[20:46:48.828] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:49.134] <TB2> INFO: Expecting 2560 events.
[20:46:50.022] <TB2> INFO: 2560 events read in total (296ms).
[20:46:50.022] <TB2> INFO: Test took 1195ms.
[20:46:50.025] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:50.331] <TB2> INFO: Expecting 2560 events.
[20:46:51.217] <TB2> INFO: 2560 events read in total (295ms).
[20:46:51.217] <TB2> INFO: Test took 1192ms.
[20:46:51.220] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:51.526] <TB2> INFO: Expecting 2560 events.
[20:46:52.409] <TB2> INFO: 2560 events read in total (292ms).
[20:46:52.409] <TB2> INFO: Test took 1190ms.
[20:46:52.412] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:52.718] <TB2> INFO: Expecting 2560 events.
[20:46:53.609] <TB2> INFO: 2560 events read in total (300ms).
[20:46:53.610] <TB2> INFO: Test took 1198ms.
[20:46:53.613] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:53.918] <TB2> INFO: Expecting 2560 events.
[20:46:54.804] <TB2> INFO: 2560 events read in total (294ms).
[20:46:54.805] <TB2> INFO: Test took 1193ms.
[20:46:54.807] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:55.113] <TB2> INFO: Expecting 2560 events.
[20:46:55.996] <TB2> INFO: 2560 events read in total (292ms).
[20:46:55.996] <TB2> INFO: Test took 1189ms.
[20:46:55.001] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:56.303] <TB2> INFO: Expecting 2560 events.
[20:46:57.187] <TB2> INFO: 2560 events read in total (292ms).
[20:46:57.188] <TB2> INFO: Test took 1188ms.
[20:46:57.191] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:57.496] <TB2> INFO: Expecting 2560 events.
[20:46:58.391] <TB2> INFO: 2560 events read in total (303ms).
[20:46:58.391] <TB2> INFO: Test took 1200ms.
[20:46:58.394] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:58.699] <TB2> INFO: Expecting 2560 events.
[20:46:59.586] <TB2> INFO: 2560 events read in total (295ms).
[20:46:59.586] <TB2> INFO: Test took 1192ms.
[20:46:59.589] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:46:59.895] <TB2> INFO: Expecting 2560 events.
[20:47:00.782] <TB2> INFO: 2560 events read in total (295ms).
[20:47:00.783] <TB2> INFO: Test took 1194ms.
[20:47:00.786] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:47:01.091] <TB2> INFO: Expecting 2560 events.
[20:47:01.976] <TB2> INFO: 2560 events read in total (293ms).
[20:47:01.977] <TB2> INFO: Test took 1192ms.
[20:47:02.451] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 544 seconds
[20:47:02.451] <TB2> INFO: PH scale (per ROC): 42 47 36 45 55 33 35 38 45 32 54 35 48 45 35 39
[20:47:02.451] <TB2> INFO: PH offset (per ROC): 121 137 105 99 117 89 129 92 141 115 129 101 141 141 110 114
[20:47:02.459] <TB2> INFO: Decoding statistics:
[20:47:02.459] <TB2> INFO: General information:
[20:47:02.459] <TB2> INFO: 16bit words read: 127882
[20:47:02.459] <TB2> INFO: valid events total: 20480
[20:47:02.459] <TB2> INFO: empty events: 17979
[20:47:02.459] <TB2> INFO: valid events with pixels: 2501
[20:47:02.459] <TB2> INFO: valid pixel hits: 2501
[20:47:02.459] <TB2> INFO: Event errors: 0
[20:47:02.459] <TB2> INFO: start marker: 0
[20:47:02.459] <TB2> INFO: stop marker: 0
[20:47:02.459] <TB2> INFO: overflow: 0
[20:47:02.459] <TB2> INFO: invalid 5bit words: 0
[20:47:02.459] <TB2> INFO: invalid XOR eye diagram: 0
[20:47:02.459] <TB2> INFO: frame (failed synchr.): 0
[20:47:02.460] <TB2> INFO: idle data (no TBM trl): 0
[20:47:02.460] <TB2> INFO: no data (only TBM hdr): 0
[20:47:02.460] <TB2> INFO: TBM errors: 0
[20:47:02.460] <TB2> INFO: flawed TBM headers: 0
[20:47:02.460] <TB2> INFO: flawed TBM trailers: 0
[20:47:02.460] <TB2> INFO: event ID mismatches: 0
[20:47:02.460] <TB2> INFO: ROC errors: 0
[20:47:02.460] <TB2> INFO: missing ROC header(s): 0
[20:47:02.460] <TB2> INFO: misplaced readback start: 0
[20:47:02.460] <TB2> INFO: Pixel decoding errors: 0
[20:47:02.460] <TB2> INFO: pixel data incomplete: 0
[20:47:02.460] <TB2> INFO: pixel address: 0
[20:47:02.460] <TB2> INFO: pulse height fill bit: 0
[20:47:02.460] <TB2> INFO: buffer corruption: 0
[20:47:02.627] <TB2> INFO: ######################################################################
[20:47:02.627] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[20:47:02.627] <TB2> INFO: ######################################################################
[20:47:02.642] <TB2> INFO: scanning low vcal = 10
[20:47:02.881] <TB2> INFO: Expecting 41600 events.
[20:47:06.523] <TB2> INFO: 41600 events read in total (3050ms).
[20:47:06.523] <TB2> INFO: Test took 3881ms.
[20:47:06.525] <TB2> INFO: scanning low vcal = 20
[20:47:06.817] <TB2> INFO: Expecting 41600 events.
[20:47:10.394] <TB2> INFO: 41600 events read in total (2986ms).
[20:47:10.395] <TB2> INFO: Test took 3870ms.
[20:47:10.396] <TB2> INFO: scanning low vcal = 30
[20:47:10.701] <TB2> INFO: Expecting 41600 events.
[20:47:14.346] <TB2> INFO: 41600 events read in total (3054ms).
[20:47:14.347] <TB2> INFO: Test took 3950ms.
[20:47:14.350] <TB2> INFO: scanning low vcal = 40
[20:47:14.627] <TB2> INFO: Expecting 41600 events.
[20:47:18.668] <TB2> INFO: 41600 events read in total (3449ms).
[20:47:18.669] <TB2> INFO: Test took 4319ms.
[20:47:18.673] <TB2> INFO: scanning low vcal = 50
[20:47:18.949] <TB2> INFO: Expecting 41600 events.
[20:47:22.982] <TB2> INFO: 41600 events read in total (3442ms).
[20:47:22.983] <TB2> INFO: Test took 4310ms.
[20:47:22.986] <TB2> INFO: scanning low vcal = 60
[20:47:23.263] <TB2> INFO: Expecting 41600 events.
[20:47:27.287] <TB2> INFO: 41600 events read in total (3433ms).
[20:47:27.288] <TB2> INFO: Test took 4302ms.
[20:47:27.291] <TB2> INFO: scanning low vcal = 70
[20:47:27.568] <TB2> INFO: Expecting 41600 events.
[20:47:31.585] <TB2> INFO: 41600 events read in total (3426ms).
[20:47:31.585] <TB2> INFO: Test took 4294ms.
[20:47:31.588] <TB2> INFO: scanning low vcal = 80
[20:47:31.864] <TB2> INFO: Expecting 41600 events.
[20:47:35.905] <TB2> INFO: 41600 events read in total (3450ms).
[20:47:35.906] <TB2> INFO: Test took 4318ms.
[20:47:35.910] <TB2> INFO: scanning low vcal = 90
[20:47:36.187] <TB2> INFO: Expecting 41600 events.
[20:47:40.182] <TB2> INFO: 41600 events read in total (3404ms).
[20:47:40.183] <TB2> INFO: Test took 4273ms.
[20:47:40.187] <TB2> INFO: scanning low vcal = 100
[20:47:40.478] <TB2> INFO: Expecting 41600 events.
[20:47:44.545] <TB2> INFO: 41600 events read in total (3475ms).
[20:47:44.545] <TB2> INFO: Test took 4357ms.
[20:47:44.548] <TB2> INFO: scanning low vcal = 110
[20:47:44.825] <TB2> INFO: Expecting 41600 events.
[20:47:48.815] <TB2> INFO: 41600 events read in total (3398ms).
[20:47:48.816] <TB2> INFO: Test took 4268ms.
[20:47:48.819] <TB2> INFO: scanning low vcal = 120
[20:47:49.096] <TB2> INFO: Expecting 41600 events.
[20:47:53.176] <TB2> INFO: 41600 events read in total (3488ms).
[20:47:53.176] <TB2> INFO: Test took 4356ms.
[20:47:53.180] <TB2> INFO: scanning low vcal = 130
[20:47:53.456] <TB2> INFO: Expecting 41600 events.
[20:47:57.445] <TB2> INFO: 41600 events read in total (3397ms).
[20:47:57.446] <TB2> INFO: Test took 4266ms.
[20:47:57.449] <TB2> INFO: scanning low vcal = 140
[20:47:57.725] <TB2> INFO: Expecting 41600 events.
[20:48:01.753] <TB2> INFO: 41600 events read in total (3436ms).
[20:48:01.753] <TB2> INFO: Test took 4304ms.
[20:48:01.756] <TB2> INFO: scanning low vcal = 150
[20:48:02.033] <TB2> INFO: Expecting 41600 events.
[20:48:06.033] <TB2> INFO: 41600 events read in total (3408ms).
[20:48:06.034] <TB2> INFO: Test took 4278ms.
[20:48:06.037] <TB2> INFO: scanning low vcal = 160
[20:48:06.314] <TB2> INFO: Expecting 41600 events.
[20:48:10.352] <TB2> INFO: 41600 events read in total (3446ms).
[20:48:10.353] <TB2> INFO: Test took 4316ms.
[20:48:10.356] <TB2> INFO: scanning low vcal = 170
[20:48:10.633] <TB2> INFO: Expecting 41600 events.
[20:48:14.645] <TB2> INFO: 41600 events read in total (3420ms).
[20:48:14.645] <TB2> INFO: Test took 4288ms.
[20:48:14.651] <TB2> INFO: scanning low vcal = 180
[20:48:14.925] <TB2> INFO: Expecting 41600 events.
[20:48:18.970] <TB2> INFO: 41600 events read in total (3453ms).
[20:48:18.971] <TB2> INFO: Test took 4320ms.
[20:48:18.975] <TB2> INFO: scanning low vcal = 190
[20:48:19.251] <TB2> INFO: Expecting 41600 events.
[20:48:23.286] <TB2> INFO: 41600 events read in total (3443ms).
[20:48:23.287] <TB2> INFO: Test took 4312ms.
[20:48:23.290] <TB2> INFO: scanning low vcal = 200
[20:48:23.567] <TB2> INFO: Expecting 41600 events.
[20:48:27.626] <TB2> INFO: 41600 events read in total (3468ms).
[20:48:27.626] <TB2> INFO: Test took 4336ms.
[20:48:27.629] <TB2> INFO: scanning low vcal = 210
[20:48:27.906] <TB2> INFO: Expecting 41600 events.
[20:48:31.935] <TB2> INFO: 41600 events read in total (3437ms).
[20:48:31.936] <TB2> INFO: Test took 4307ms.
[20:48:31.939] <TB2> INFO: scanning low vcal = 220
[20:48:32.216] <TB2> INFO: Expecting 41600 events.
[20:48:36.327] <TB2> INFO: 41600 events read in total (3519ms).
[20:48:36.328] <TB2> INFO: Test took 4389ms.
[20:48:36.331] <TB2> INFO: scanning low vcal = 230
[20:48:36.628] <TB2> INFO: Expecting 41600 events.
[20:48:40.664] <TB2> INFO: 41600 events read in total (3444ms).
[20:48:40.665] <TB2> INFO: Test took 4334ms.
[20:48:40.669] <TB2> INFO: scanning low vcal = 240
[20:48:40.946] <TB2> INFO: Expecting 41600 events.
[20:48:44.962] <TB2> INFO: 41600 events read in total (3425ms).
[20:48:44.963] <TB2> INFO: Test took 4294ms.
[20:48:44.966] <TB2> INFO: scanning low vcal = 250
[20:48:45.242] <TB2> INFO: Expecting 41600 events.
[20:48:49.297] <TB2> INFO: 41600 events read in total (3463ms).
[20:48:49.298] <TB2> INFO: Test took 4332ms.
[20:48:49.302] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[20:48:49.578] <TB2> INFO: Expecting 41600 events.
[20:48:53.602] <TB2> INFO: 41600 events read in total (3432ms).
[20:48:53.603] <TB2> INFO: Test took 4301ms.
[20:48:53.606] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[20:48:53.883] <TB2> INFO: Expecting 41600 events.
[20:48:57.869] <TB2> INFO: 41600 events read in total (3396ms).
[20:48:57.870] <TB2> INFO: Test took 4264ms.
[20:48:57.873] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[20:48:58.150] <TB2> INFO: Expecting 41600 events.
[20:49:02.173] <TB2> INFO: 41600 events read in total (3431ms).
[20:49:02.174] <TB2> INFO: Test took 4301ms.
[20:49:02.179] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[20:49:02.454] <TB2> INFO: Expecting 41600 events.
[20:49:06.530] <TB2> INFO: 41600 events read in total (3484ms).
[20:49:06.531] <TB2> INFO: Test took 4352ms.
[20:49:06.534] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[20:49:06.832] <TB2> INFO: Expecting 41600 events.
[20:49:10.843] <TB2> INFO: 41600 events read in total (3419ms).
[20:49:10.844] <TB2> INFO: Test took 4309ms.
[20:49:11.373] <TB2> INFO: PixTestGainPedestal::measure() done
[20:49:43.542] <TB2> INFO: PixTestGainPedestal::fit() done
[20:49:43.542] <TB2> INFO: non-linearity mean: 0.939 0.968 0.953 0.907 0.979 0.926 0.915 0.952 0.973 0.965 0.981 0.930 0.967 0.963 0.916 0.896
[20:49:43.542] <TB2> INFO: non-linearity RMS: 0.070 0.008 0.024 0.180 0.003 0.158 0.073 0.159 0.007 0.185 0.003 0.098 0.005 0.006 0.078 0.116
[20:49:43.542] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[20:49:43.558] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[20:49:43.571] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[20:49:43.585] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[20:49:43.598] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[20:49:43.612] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[20:49:43.626] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[20:49:43.639] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[20:49:43.656] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[20:49:43.671] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[20:49:43.685] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[20:49:43.705] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[20:49:43.729] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[20:49:43.752] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[20:49:43.769] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[20:49:43.782] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1068_FullQualification_2016-11-03_14h08m_1478178483//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[20:49:43.795] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 161 seconds
[20:49:43.795] <TB2> INFO: Decoding statistics:
[20:49:43.795] <TB2> INFO: General information:
[20:49:43.795] <TB2> INFO: 16bit words read: 3327918
[20:49:43.795] <TB2> INFO: valid events total: 332800
[20:49:43.795] <TB2> INFO: empty events: 0
[20:49:43.795] <TB2> INFO: valid events with pixels: 332800
[20:49:43.795] <TB2> INFO: valid pixel hits: 665559
[20:49:43.795] <TB2> INFO: Event errors: 0
[20:49:43.795] <TB2> INFO: start marker: 0
[20:49:43.795] <TB2> INFO: stop marker: 0
[20:49:43.795] <TB2> INFO: overflow: 0
[20:49:43.795] <TB2> INFO: invalid 5bit words: 0
[20:49:43.795] <TB2> INFO: invalid XOR eye diagram: 0
[20:49:43.795] <TB2> INFO: frame (failed synchr.): 0
[20:49:43.795] <TB2> INFO: idle data (no TBM trl): 0
[20:49:43.795] <TB2> INFO: no data (only TBM hdr): 0
[20:49:43.795] <TB2> INFO: TBM errors: 0
[20:49:43.796] <TB2> INFO: flawed TBM headers: 0
[20:49:43.796] <TB2> INFO: flawed TBM trailers: 0
[20:49:43.796] <TB2> INFO: event ID mismatches: 0
[20:49:43.796] <TB2> INFO: ROC errors: 0
[20:49:43.796] <TB2> INFO: missing ROC header(s): 0
[20:49:43.796] <TB2> INFO: misplaced readback start: 0
[20:49:43.796] <TB2> INFO: Pixel decoding errors: 0
[20:49:43.796] <TB2> INFO: pixel data incomplete: 0
[20:49:43.796] <TB2> INFO: pixel address: 0
[20:49:43.796] <TB2> INFO: pulse height fill bit: 0
[20:49:43.796] <TB2> INFO: buffer corruption: 0
[20:49:43.815] <TB2> INFO: Decoding statistics:
[20:49:43.815] <TB2> INFO: General information:
[20:49:43.815] <TB2> INFO: 16bit words read: 3457336
[20:49:43.815] <TB2> INFO: valid events total: 353536
[20:49:43.815] <TB2> INFO: empty events: 18235
[20:49:43.815] <TB2> INFO: valid events with pixels: 335301
[20:49:43.815] <TB2> INFO: valid pixel hits: 668060
[20:49:43.815] <TB2> INFO: Event errors: 0
[20:49:43.815] <TB2> INFO: start marker: 0
[20:49:43.815] <TB2> INFO: stop marker: 0
[20:49:43.815] <TB2> INFO: overflow: 0
[20:49:43.815] <TB2> INFO: invalid 5bit words: 0
[20:49:43.815] <TB2> INFO: invalid XOR eye diagram: 0
[20:49:43.816] <TB2> INFO: frame (failed synchr.): 0
[20:49:43.816] <TB2> INFO: idle data (no TBM trl): 0
[20:49:43.816] <TB2> INFO: no data (only TBM hdr): 0
[20:49:43.816] <TB2> INFO: TBM errors: 0
[20:49:43.816] <TB2> INFO: flawed TBM headers: 0
[20:49:43.816] <TB2> INFO: flawed TBM trailers: 0
[20:49:43.816] <TB2> INFO: event ID mismatches: 0
[20:49:43.816] <TB2> INFO: ROC errors: 0
[20:49:43.816] <TB2> INFO: missing ROC header(s): 0
[20:49:43.816] <TB2> INFO: misplaced readback start: 0
[20:49:43.816] <TB2> INFO: Pixel decoding errors: 0
[20:49:43.816] <TB2> INFO: pixel data incomplete: 0
[20:49:43.816] <TB2> INFO: pixel address: 0
[20:49:43.816] <TB2> INFO: pulse height fill bit: 0
[20:49:43.816] <TB2> INFO: buffer corruption: 0
[20:49:43.816] <TB2> INFO: enter test to run
[20:49:43.816] <TB2> INFO: test: exit no parameter change
[20:49:43.962] <TB2> QUIET: Connection to board 149 closed.
[20:49:43.962] <TB2> INFO: pXar: this is the end, my friend