Test Date: 2016-10-25 10:38
Analysis date: 2016-10-25 15:06
Logfile
LogfileView
[10:57:55.752] <TB2> INFO: *** Welcome to pxar ***
[10:57:55.753] <TB2> INFO: *** Today: 2016/10/25
[10:57:55.759] <TB2> INFO: *** Version: c8ba-dirty
[10:57:55.759] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C15.dat
[10:57:55.760] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//tbmParameters_C1b.dat
[10:57:55.760] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//defaultMaskFile.dat
[10:57:55.760] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters_C15.dat
[10:57:55.859] <TB2> INFO: clk: 4
[10:57:55.859] <TB2> INFO: ctr: 4
[10:57:55.859] <TB2> INFO: sda: 19
[10:57:55.859] <TB2> INFO: tin: 9
[10:57:55.859] <TB2> INFO: level: 15
[10:57:55.859] <TB2> INFO: triggerdelay: 0
[10:57:55.859] <TB2> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[10:57:55.859] <TB2> INFO: Log level: INFO
[10:57:55.868] <TB2> INFO: Found DTB DTB_WWXUD2
[10:57:55.875] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[10:57:55.877] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
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[10:57:55.880] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[10:57:57.375] <TB2> INFO: DUT info:
[10:57:57.376] <TB2> INFO: The DUT currently contains the following objects:
[10:57:57.376] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[10:57:57.376] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:57:57.376] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:57:57.376] <TB2> INFO: TBM Core alpha (2): 7 registers set
[10:57:57.376] <TB2> INFO: TBM Core beta (3): 7 registers set
[10:57:57.376] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[10:57:57.376] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[10:57:57.376] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[10:57:57.376] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[10:57:57.376] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[10:57:57.376] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[10:57:57.376] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[10:57:57.376] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[10:57:57.376] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[10:57:57.376] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[10:57:57.376] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[10:57:57.376] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[10:57:57.376] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[10:57:57.376] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[10:57:57.376] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[10:57:57.376] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[10:57:57.376] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[10:57:57.777] <TB2> INFO: enter 'restricted' command line mode
[10:57:57.777] <TB2> INFO: enter test to run
[10:57:57.777] <TB2> INFO: test: pretest no parameter change
[10:57:57.777] <TB2> INFO: running: pretest
[10:57:57.784] <TB2> INFO: ######################################################################
[10:57:57.784] <TB2> INFO: PixTestPretest::doTest()
[10:57:57.784] <TB2> INFO: ######################################################################
[10:57:57.785] <TB2> INFO: ----------------------------------------------------------------------
[10:57:57.785] <TB2> INFO: PixTestPretest::programROC()
[10:57:57.785] <TB2> INFO: ----------------------------------------------------------------------
[10:58:15.799] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[10:58:15.799] <TB2> INFO: IA differences per ROC: 17.7 17.7 19.3 19.3 17.7 19.3 17.7 18.5 17.7 18.5 18.5 19.3 21.7 17.7 18.5 18.5
[10:58:15.862] <TB2> INFO: ----------------------------------------------------------------------
[10:58:15.862] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[10:58:15.862] <TB2> INFO: ----------------------------------------------------------------------
[10:58:37.163] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 381.9 mA = 23.8688 mA/ROC
[10:58:37.163] <TB2> INFO: i(loss) [mA/ROC]: 20.1 20.1 18.5 18.5 18.5 18.5 18.5 19.3 20.1 18.5 18.5 19.3 18.5 19.3 18.5 18.5
[10:58:37.190] <TB2> INFO: ----------------------------------------------------------------------
[10:58:37.190] <TB2> INFO: PixTestPretest::findTiming()
[10:58:37.190] <TB2> INFO: ----------------------------------------------------------------------
[10:58:37.190] <TB2> INFO: PixTestCmd::init()
[10:58:37.752] <TB2> WARNING: Not unmasking DUT, not setting Calibrate bits!

[10:59:08.004] <TB2> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[10:59:08.004] <TB2> INFO: (success/tries = 100/100), width = 3
[10:59:10.514] <TB2> INFO: ----------------------------------------------------------------------
[10:59:10.514] <TB2> INFO: PixTestPretest::findWorkingPixel()
[10:59:10.514] <TB2> INFO: ----------------------------------------------------------------------
[10:59:10.609] <TB2> INFO: Expecting 231680 events.
[10:59:20.559] <TB2> INFO: 231680 events read in total (9358ms).
[10:59:20.567] <TB2> INFO: Test took 10048ms.
[10:59:20.814] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[10:59:20.844] <TB2> INFO: ----------------------------------------------------------------------
[10:59:20.844] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[10:59:20.844] <TB2> INFO: ----------------------------------------------------------------------
[10:59:20.939] <TB2> INFO: Expecting 231680 events.
[10:59:30.896] <TB2> INFO: 231680 events read in total (9365ms).
[10:59:30.906] <TB2> INFO: Test took 10057ms.
[10:59:31.167] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[10:59:31.167] <TB2> INFO: CalDel: 81 101 96 91 90 93 86 94 87 88 97 89 83 110 85 92
[10:59:31.167] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 53 51 51
[10:59:31.170] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C0.dat
[10:59:31.170] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C1.dat
[10:59:31.170] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C2.dat
[10:59:31.170] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C3.dat
[10:59:31.170] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C4.dat
[10:59:31.170] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C5.dat
[10:59:31.170] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C6.dat
[10:59:31.171] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C7.dat
[10:59:31.171] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C8.dat
[10:59:31.171] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C9.dat
[10:59:31.171] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C10.dat
[10:59:31.171] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C11.dat
[10:59:31.171] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C12.dat
[10:59:31.171] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C13.dat
[10:59:31.171] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C14.dat
[10:59:31.171] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters_C15.dat
[10:59:31.171] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//tbmParameters_C0a.dat
[10:59:31.171] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//tbmParameters_C0b.dat
[10:59:31.172] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//tbmParameters_C1a.dat
[10:59:31.172] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//tbmParameters_C1b.dat
[10:59:31.172] <TB2> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[10:59:31.226] <TB2> INFO: enter test to run
[10:59:31.226] <TB2> INFO: test: FullTest no parameter change
[10:59:31.226] <TB2> INFO: running: fulltest
[10:59:31.226] <TB2> INFO: ######################################################################
[10:59:31.226] <TB2> INFO: PixTestFullTest::doTest()
[10:59:31.226] <TB2> INFO: ######################################################################
[10:59:31.229] <TB2> INFO: ######################################################################
[10:59:31.229] <TB2> INFO: PixTestAlive::doTest()
[10:59:31.229] <TB2> INFO: ######################################################################
[10:59:31.230] <TB2> INFO: ----------------------------------------------------------------------
[10:59:31.230] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:59:31.230] <TB2> INFO: ----------------------------------------------------------------------
[10:59:31.468] <TB2> INFO: Expecting 41600 events.
[10:59:35.105] <TB2> INFO: 41600 events read in total (3045ms).
[10:59:35.106] <TB2> INFO: Test took 3874ms.
[10:59:35.338] <TB2> INFO: PixTestAlive::aliveTest() done
[10:59:35.338] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:59:35.339] <TB2> INFO: ----------------------------------------------------------------------
[10:59:35.339] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:59:35.339] <TB2> INFO: ----------------------------------------------------------------------
[10:59:35.582] <TB2> INFO: Expecting 41600 events.
[10:59:38.590] <TB2> INFO: 41600 events read in total (2416ms).
[10:59:38.590] <TB2> INFO: Test took 3249ms.
[10:59:38.591] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[10:59:38.826] <TB2> INFO: PixTestAlive::maskTest() done
[10:59:38.826] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:59:38.827] <TB2> INFO: ----------------------------------------------------------------------
[10:59:38.827] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:59:38.827] <TB2> INFO: ----------------------------------------------------------------------
[10:59:39.067] <TB2> INFO: Expecting 41600 events.
[10:59:42.642] <TB2> INFO: 41600 events read in total (2983ms).
[10:59:42.643] <TB2> INFO: Test took 3814ms.
[10:59:42.878] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[10:59:42.878] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:59:42.878] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[10:59:42.878] <TB2> INFO: Decoding statistics:
[10:59:42.878] <TB2> INFO: General information:
[10:59:42.878] <TB2> INFO: 16bit words read: 0
[10:59:42.878] <TB2> INFO: valid events total: 0
[10:59:42.878] <TB2> INFO: empty events: 0
[10:59:42.878] <TB2> INFO: valid events with pixels: 0
[10:59:42.878] <TB2> INFO: valid pixel hits: 0
[10:59:42.878] <TB2> INFO: Event errors: 0
[10:59:42.878] <TB2> INFO: start marker: 0
[10:59:42.879] <TB2> INFO: stop marker: 0
[10:59:42.879] <TB2> INFO: overflow: 0
[10:59:42.879] <TB2> INFO: invalid 5bit words: 0
[10:59:42.879] <TB2> INFO: invalid XOR eye diagram: 0
[10:59:42.879] <TB2> INFO: frame (failed synchr.): 0
[10:59:42.879] <TB2> INFO: idle data (no TBM trl): 0
[10:59:42.879] <TB2> INFO: no data (only TBM hdr): 0
[10:59:42.879] <TB2> INFO: TBM errors: 0
[10:59:42.879] <TB2> INFO: flawed TBM headers: 0
[10:59:42.879] <TB2> INFO: flawed TBM trailers: 0
[10:59:42.879] <TB2> INFO: event ID mismatches: 0
[10:59:42.879] <TB2> INFO: ROC errors: 0
[10:59:42.879] <TB2> INFO: missing ROC header(s): 0
[10:59:42.879] <TB2> INFO: misplaced readback start: 0
[10:59:42.879] <TB2> INFO: Pixel decoding errors: 0
[10:59:42.879] <TB2> INFO: pixel data incomplete: 0
[10:59:42.879] <TB2> INFO: pixel address: 0
[10:59:42.879] <TB2> INFO: pulse height fill bit: 0
[10:59:42.879] <TB2> INFO: buffer corruption: 0
[10:59:42.886] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C15.dat
[10:59:42.887] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr_C15.dat
[10:59:42.887] <TB2> ERROR: <ConfigParameters.cc/readGainPedestalParameters:L1005> cannot open /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr_C0.dat for reading PH calibration constants

[10:59:42.887] <TB2> INFO: ######################################################################
[10:59:42.887] <TB2> INFO: PixTestReadback::doTest()
[10:59:42.887] <TB2> INFO: ######################################################################
[10:59:42.887] <TB2> INFO: ----------------------------------------------------------------------
[10:59:42.887] <TB2> INFO: PixTestReadback::CalibrateVd()
[10:59:42.887] <TB2> INFO: ----------------------------------------------------------------------
[10:59:52.870] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C0.dat
[10:59:52.870] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C1.dat
[10:59:52.871] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C2.dat
[10:59:52.871] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C3.dat
[10:59:52.871] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C4.dat
[10:59:52.871] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C5.dat
[10:59:52.871] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C6.dat
[10:59:52.871] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C7.dat
[10:59:52.871] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C8.dat
[10:59:52.871] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C9.dat
[10:59:52.871] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C10.dat
[10:59:52.871] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C11.dat
[10:59:52.871] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C12.dat
[10:59:52.872] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C13.dat
[10:59:52.872] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C14.dat
[10:59:52.872] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C15.dat
[10:59:52.905] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:59:52.905] <TB2> INFO: ----------------------------------------------------------------------
[10:59:52.905] <TB2> INFO: PixTestReadback::CalibrateVa()
[10:59:52.905] <TB2> INFO: ----------------------------------------------------------------------
[11:00:02.845] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C0.dat
[11:00:02.845] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C1.dat
[11:00:02.845] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C2.dat
[11:00:02.845] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C3.dat
[11:00:02.845] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C4.dat
[11:00:02.845] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C5.dat
[11:00:02.845] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C6.dat
[11:00:02.845] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C7.dat
[11:00:02.845] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C8.dat
[11:00:02.845] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C9.dat
[11:00:02.845] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C10.dat
[11:00:02.846] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C11.dat
[11:00:02.846] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C12.dat
[11:00:02.846] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C13.dat
[11:00:02.846] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C14.dat
[11:00:02.846] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C15.dat
[11:00:02.877] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:00:02.877] <TB2> INFO: ----------------------------------------------------------------------
[11:00:02.877] <TB2> INFO: PixTestReadback::readbackVbg()
[11:00:02.877] <TB2> INFO: ----------------------------------------------------------------------
[11:00:10.558] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:00:10.558] <TB2> INFO: ----------------------------------------------------------------------
[11:00:10.558] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[11:00:10.558] <TB2> INFO: ----------------------------------------------------------------------
[11:00:10.558] <TB2> INFO: Vbg will be calibrated using Vd calibration
[11:00:10.558] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 153calibrated Vbg = 1.19823 :::*/*/*/*/
[11:00:10.559] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 154.2calibrated Vbg = 1.20304 :::*/*/*/*/
[11:00:10.559] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 162.3calibrated Vbg = 1.19449 :::*/*/*/*/
[11:00:10.559] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 150.7calibrated Vbg = 1.19321 :::*/*/*/*/
[11:00:10.559] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 160.8calibrated Vbg = 1.19422 :::*/*/*/*/
[11:00:10.559] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 155.6calibrated Vbg = 1.19876 :::*/*/*/*/
[11:00:10.559] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 165.6calibrated Vbg = 1.20137 :::*/*/*/*/
[11:00:10.559] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 158.1calibrated Vbg = 1.20265 :::*/*/*/*/
[11:00:10.559] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 152.5calibrated Vbg = 1.19666 :::*/*/*/*/
[11:00:10.559] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 162.5calibrated Vbg = 1.19481 :::*/*/*/*/
[11:00:10.559] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 163.3calibrated Vbg = 1.19091 :::*/*/*/*/
[11:00:10.559] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 156.6calibrated Vbg = 1.18765 :::*/*/*/*/
[11:00:10.559] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 150.9calibrated Vbg = 1.1929 :::*/*/*/*/
[11:00:10.559] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 154.3calibrated Vbg = 1.1926 :::*/*/*/*/
[11:00:10.559] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 152.8calibrated Vbg = 1.19383 :::*/*/*/*/
[11:00:10.559] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 149.3calibrated Vbg = 1.19654 :::*/*/*/*/
[11:00:10.562] <TB2> INFO: ----------------------------------------------------------------------
[11:00:10.562] <TB2> INFO: PixTestReadback::CalibrateIa()
[11:00:10.562] <TB2> INFO: ----------------------------------------------------------------------
[11:02:51.373] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C0.dat
[11:02:51.373] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C1.dat
[11:02:51.373] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C2.dat
[11:02:51.373] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C3.dat
[11:02:51.373] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C4.dat
[11:02:51.373] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C5.dat
[11:02:51.373] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C6.dat
[11:02:51.373] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C7.dat
[11:02:51.373] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C8.dat
[11:02:51.373] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C9.dat
[11:02:51.373] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C10.dat
[11:02:51.373] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C11.dat
[11:02:51.373] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C12.dat
[11:02:51.374] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C13.dat
[11:02:51.374] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C14.dat
[11:02:51.374] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//readbackCal_C15.dat
[11:02:51.403] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:02:51.406] <TB2> INFO: PixTestReadback::doTest() done
[11:02:51.407] <TB2> INFO: Decoding statistics:
[11:02:51.407] <TB2> INFO: General information:
[11:02:51.407] <TB2> INFO: 16bit words read: 1536
[11:02:51.407] <TB2> INFO: valid events total: 256
[11:02:51.407] <TB2> INFO: empty events: 256
[11:02:51.407] <TB2> INFO: valid events with pixels: 0
[11:02:51.407] <TB2> INFO: valid pixel hits: 0
[11:02:51.407] <TB2> INFO: Event errors: 0
[11:02:51.407] <TB2> INFO: start marker: 0
[11:02:51.407] <TB2> INFO: stop marker: 0
[11:02:51.407] <TB2> INFO: overflow: 0
[11:02:51.407] <TB2> INFO: invalid 5bit words: 0
[11:02:51.407] <TB2> INFO: invalid XOR eye diagram: 0
[11:02:51.407] <TB2> INFO: frame (failed synchr.): 0
[11:02:51.407] <TB2> INFO: idle data (no TBM trl): 0
[11:02:51.407] <TB2> INFO: no data (only TBM hdr): 0
[11:02:51.407] <TB2> INFO: TBM errors: 0
[11:02:51.407] <TB2> INFO: flawed TBM headers: 0
[11:02:51.407] <TB2> INFO: flawed TBM trailers: 0
[11:02:51.407] <TB2> INFO: event ID mismatches: 0
[11:02:51.407] <TB2> INFO: ROC errors: 0
[11:02:51.407] <TB2> INFO: missing ROC header(s): 0
[11:02:51.407] <TB2> INFO: misplaced readback start: 0
[11:02:51.407] <TB2> INFO: Pixel decoding errors: 0
[11:02:51.407] <TB2> INFO: pixel data incomplete: 0
[11:02:51.407] <TB2> INFO: pixel address: 0
[11:02:51.407] <TB2> INFO: pulse height fill bit: 0
[11:02:51.407] <TB2> INFO: buffer corruption: 0
[11:02:51.460] <TB2> INFO: ######################################################################
[11:02:51.460] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[11:02:51.460] <TB2> INFO: ######################################################################
[11:02:51.463] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[11:02:51.505] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:02:51.505] <TB2> INFO: run 1 of 1
[11:02:51.783] <TB2> INFO: Expecting 3120000 events.
[11:03:23.066] <TB2> INFO: 676310 events read in total (30691ms).
[11:03:54.127] <TB2> INFO: 1357075 events read in total (61752ms).
[11:04:06.622] <TB2> ERROR: <datapipe.cc/CheckEventID:L485> Channel 0 Event ID mismatch: local ID (148) != TBM ID (87)

[11:04:06.622] <TB2> ERROR: <datapipe.cc/CheckEventValidity:L523> Channel 0 Number of ROCs (1) != Token Chain Length (2)

[11:04:06.761] <TB2> ERROR: <datapipe.cc/CheckEventID:L485> Channel 0 Event ID mismatch: local ID (88) != TBM ID (149)

[11:04:06.761] <TB2> ERROR: <datapipe.cc/Read:L170> Dumping the flawed event +- 3 events:

[11:04:06.761] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a098 80b1 4810 4811 e022 c000

[11:04:06.761] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a092 8000 4810 4811 e022 c000

[11:04:06.761] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a093 8040 4810 4810 e022 c000

[11:04:06.761] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a057 8040 4810 264 e022 c000

[11:04:06.761] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a095 80c0 4810 4810 e022 c000

[11:04:06.761] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a096 8000 4810 4810 e022 c000

[11:04:06.761] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a097 8040 4810 4810 e022 c000

[11:04:25.451] <TB2> INFO: 2037535 events read in total (93076ms).
[11:04:56.414] <TB2> INFO: 2718155 events read in total (124039ms).
[11:05:03.912] <TB2> ERROR: <datapipe.cc/CheckEventID:L485> Channel 0 Event ID mismatch: local ID (76) != TBM ID (160)

[11:05:03.912] <TB2> ERROR: <datapipe.cc/CheckEventValidity:L523> Channel 0 Number of ROCs (1) != Token Chain Length (2)

[11:05:04.051] <TB2> ERROR: <datapipe.cc/CheckEventID:L485> Channel 0 Event ID mismatch: local ID (161) != TBM ID (77)

[11:05:04.051] <TB2> ERROR: <datapipe.cc/Read:L170> Dumping the flawed event +- 3 events:

[11:05:04.051] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a050 80b1 4810 4811 e022 c000

[11:05:04.051] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a04a 8000 4810 4811 e022 c000

[11:05:04.051] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a04b 8040 4811 4811 e022 c000

[11:05:04.051] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a0a0 80b1 4810 832 e022 c000

[11:05:04.051] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a04d 80c0 4811 4810 e022 c000

[11:05:04.051] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a04e 8000 4810 4812 e022 c000

[11:05:04.051] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a04f 8040 4812 4810 e022 c000

[11:05:14.748] <TB2> INFO: 3120000 events read in total (142373ms).
[11:05:14.833] <TB2> INFO: Test took 143328ms.
[11:05:42.581] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 171 seconds
[11:05:42.581] <TB2> INFO: number of dead bumps (per ROC): 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1
[11:05:42.581] <TB2> INFO: separation cut (per ROC): 116 127 109 117 119 120 130 121 110 109 106 130 111 108 124 105
[11:05:42.581] <TB2> INFO: Decoding statistics:
[11:05:42.581] <TB2> INFO: General information:
[11:05:42.581] <TB2> INFO: 16bit words read: 0
[11:05:42.581] <TB2> INFO: valid events total: 0
[11:05:42.581] <TB2> INFO: empty events: 0
[11:05:42.581] <TB2> INFO: valid events with pixels: 0
[11:05:42.581] <TB2> INFO: valid pixel hits: 0
[11:05:42.581] <TB2> INFO: Event errors: 0
[11:05:42.581] <TB2> INFO: start marker: 0
[11:05:42.581] <TB2> INFO: stop marker: 0
[11:05:42.581] <TB2> INFO: overflow: 0
[11:05:42.581] <TB2> INFO: invalid 5bit words: 0
[11:05:42.581] <TB2> INFO: invalid XOR eye diagram: 0
[11:05:42.581] <TB2> INFO: frame (failed synchr.): 0
[11:05:42.581] <TB2> INFO: idle data (no TBM trl): 0
[11:05:42.581] <TB2> INFO: no data (only TBM hdr): 0
[11:05:42.581] <TB2> INFO: TBM errors: 0
[11:05:42.581] <TB2> INFO: flawed TBM headers: 0
[11:05:42.582] <TB2> INFO: flawed TBM trailers: 0
[11:05:42.582] <TB2> INFO: event ID mismatches: 0
[11:05:42.582] <TB2> INFO: ROC errors: 0
[11:05:42.582] <TB2> INFO: missing ROC header(s): 0
[11:05:42.582] <TB2> INFO: misplaced readback start: 0
[11:05:42.582] <TB2> INFO: Pixel decoding errors: 0
[11:05:42.582] <TB2> INFO: pixel data incomplete: 0
[11:05:42.582] <TB2> INFO: pixel address: 0
[11:05:42.582] <TB2> INFO: pulse height fill bit: 0
[11:05:42.582] <TB2> INFO: buffer corruption: 0
[11:05:42.625] <TB2> INFO: ######################################################################
[11:05:42.625] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:05:42.625] <TB2> INFO: ######################################################################
[11:05:42.625] <TB2> INFO: ----------------------------------------------------------------------
[11:05:42.625] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:05:42.625] <TB2> INFO: ----------------------------------------------------------------------
[11:05:42.625] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[11:05:42.639] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[11:05:42.639] <TB2> INFO: run 1 of 1
[11:05:42.877] <TB2> INFO: Expecting 36608000 events.
[11:06:07.233] <TB2> INFO: 702650 events read in total (23756ms).
[11:06:30.511] <TB2> INFO: 1385500 events read in total (47035ms).
[11:06:54.069] <TB2> INFO: 2068750 events read in total (70592ms).
[11:07:17.670] <TB2> INFO: 2750350 events read in total (94193ms).
[11:07:41.095] <TB2> INFO: 3430950 events read in total (117618ms).
[11:08:04.521] <TB2> INFO: 4109250 events read in total (141044ms).
[11:08:28.046] <TB2> INFO: 4793050 events read in total (164569ms).
[11:08:51.524] <TB2> INFO: 5475000 events read in total (188047ms).
[11:09:14.841] <TB2> INFO: 6156250 events read in total (211364ms).
[11:09:37.938] <TB2> INFO: 6834650 events read in total (234461ms).
[11:10:01.387] <TB2> INFO: 7511000 events read in total (257910ms).
[11:10:24.851] <TB2> INFO: 8188100 events read in total (281374ms).
[11:10:48.541] <TB2> INFO: 8867300 events read in total (305064ms).
[11:11:12.125] <TB2> INFO: 9547550 events read in total (328648ms).
[11:11:35.135] <TB2> INFO: 10226400 events read in total (351658ms).
[11:11:58.613] <TB2> INFO: 10903700 events read in total (375136ms).
[11:12:22.147] <TB2> INFO: 11581550 events read in total (398670ms).
[11:12:45.568] <TB2> INFO: 12260950 events read in total (422091ms).
[11:13:08.885] <TB2> INFO: 12939850 events read in total (445408ms).
[11:13:32.060] <TB2> INFO: 13616200 events read in total (468583ms).
[11:13:55.235] <TB2> INFO: 14291250 events read in total (491758ms).
[11:14:18.637] <TB2> INFO: 14967350 events read in total (515160ms).
[11:14:42.260] <TB2> INFO: 15643850 events read in total (538783ms).
[11:15:05.788] <TB2> INFO: 16318900 events read in total (562311ms).
[11:15:29.134] <TB2> INFO: 16992850 events read in total (585657ms).
[11:15:52.407] <TB2> INFO: 17668550 events read in total (608930ms).
[11:16:15.569] <TB2> INFO: 18341900 events read in total (632092ms).
[11:16:38.829] <TB2> INFO: 19013950 events read in total (655352ms).
[11:17:02.151] <TB2> INFO: 19684050 events read in total (678674ms).
[11:17:25.489] <TB2> INFO: 20357050 events read in total (702012ms).
[11:17:49.161] <TB2> INFO: 21029850 events read in total (725684ms).
[11:18:12.447] <TB2> INFO: 21700700 events read in total (748970ms).
[11:18:35.862] <TB2> INFO: 22371850 events read in total (772385ms).
[11:18:59.125] <TB2> INFO: 23043400 events read in total (795648ms).
[11:19:22.561] <TB2> INFO: 23713050 events read in total (819084ms).
[11:19:45.699] <TB2> INFO: 24382800 events read in total (842222ms).
[11:20:09.122] <TB2> INFO: 25054150 events read in total (865645ms).
[11:20:32.791] <TB2> INFO: 25727100 events read in total (889314ms).
[11:20:56.336] <TB2> INFO: 26398600 events read in total (912859ms).
[11:21:19.836] <TB2> INFO: 27068950 events read in total (936359ms).
[11:21:43.064] <TB2> INFO: 27740200 events read in total (959587ms).
[11:22:06.682] <TB2> INFO: 28409750 events read in total (983205ms).
[11:22:30.279] <TB2> INFO: 29081050 events read in total (1006802ms).
[11:22:53.640] <TB2> INFO: 29750000 events read in total (1030163ms).
[11:23:16.755] <TB2> INFO: 30419800 events read in total (1053278ms).
[11:23:40.220] <TB2> INFO: 31088800 events read in total (1076743ms).
[11:24:03.654] <TB2> INFO: 31758700 events read in total (1100177ms).
[11:24:27.278] <TB2> INFO: 32426350 events read in total (1123801ms).
[11:24:50.563] <TB2> INFO: 33098600 events read in total (1147086ms).
[11:25:14.088] <TB2> INFO: 33769200 events read in total (1170611ms).
[11:25:37.488] <TB2> INFO: 34442250 events read in total (1194011ms).
[11:26:01.179] <TB2> INFO: 35112800 events read in total (1217702ms).
[11:26:25.756] <TB2> INFO: 35786350 events read in total (1242279ms).
[11:26:48.660] <TB2> INFO: 36466500 events read in total (1265183ms).
[11:26:53.701] <TB2> INFO: 36608000 events read in total (1270224ms).
[11:26:53.772] <TB2> INFO: Test took 1271132ms.
[11:26:54.145] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:26:55.615] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:26:57.069] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:26:58.536] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:26:59.000] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:27:01.524] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:27:02.003] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:27:04.507] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:27:06.029] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:27:07.662] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:27:09.203] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:27:10.952] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:27:12.368] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:27:13.757] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:27:15.189] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:27:16.586] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:27:18.020] <TB2> INFO: PixTestScurves::scurves() done
[11:27:18.020] <TB2> INFO: Vcal mean: 117.89 125.26 115.60 120.17 129.63 121.51 128.92 120.68 124.09 127.32 118.57 130.74 116.78 121.78 125.16 115.61
[11:27:18.020] <TB2> INFO: Vcal RMS: 5.54 6.48 5.11 5.98 6.05 5.97 6.38 6.02 5.88 6.36 5.92 6.47 5.30 6.64 6.11 5.34
[11:27:18.020] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1295 seconds
[11:27:18.020] <TB2> INFO: Decoding statistics:
[11:27:18.020] <TB2> INFO: General information:
[11:27:18.020] <TB2> INFO: 16bit words read: 0
[11:27:18.020] <TB2> INFO: valid events total: 0
[11:27:18.020] <TB2> INFO: empty events: 0
[11:27:18.020] <TB2> INFO: valid events with pixels: 0
[11:27:18.020] <TB2> INFO: valid pixel hits: 0
[11:27:18.020] <TB2> INFO: Event errors: 0
[11:27:18.020] <TB2> INFO: start marker: 0
[11:27:18.020] <TB2> INFO: stop marker: 0
[11:27:18.020] <TB2> INFO: overflow: 0
[11:27:18.020] <TB2> INFO: invalid 5bit words: 0
[11:27:18.020] <TB2> INFO: invalid XOR eye diagram: 0
[11:27:18.020] <TB2> INFO: frame (failed synchr.): 0
[11:27:18.020] <TB2> INFO: idle data (no TBM trl): 0
[11:27:18.020] <TB2> INFO: no data (only TBM hdr): 0
[11:27:18.020] <TB2> INFO: TBM errors: 0
[11:27:18.020] <TB2> INFO: flawed TBM headers: 0
[11:27:18.020] <TB2> INFO: flawed TBM trailers: 0
[11:27:18.020] <TB2> INFO: event ID mismatches: 0
[11:27:18.020] <TB2> INFO: ROC errors: 0
[11:27:18.020] <TB2> INFO: missing ROC header(s): 0
[11:27:18.020] <TB2> INFO: misplaced readback start: 0
[11:27:18.020] <TB2> INFO: Pixel decoding errors: 0
[11:27:18.020] <TB2> INFO: pixel data incomplete: 0
[11:27:18.020] <TB2> INFO: pixel address: 0
[11:27:18.020] <TB2> INFO: pulse height fill bit: 0
[11:27:18.020] <TB2> INFO: buffer corruption: 0
[11:27:18.102] <TB2> INFO: ######################################################################
[11:27:18.102] <TB2> INFO: PixTestTrim::doTest()
[11:27:18.102] <TB2> INFO: ######################################################################
[11:27:18.103] <TB2> INFO: ----------------------------------------------------------------------
[11:27:18.103] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[11:27:18.103] <TB2> INFO: ----------------------------------------------------------------------
[11:27:18.146] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[11:27:18.146] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:27:18.159] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:27:18.159] <TB2> INFO: run 1 of 1
[11:27:18.396] <TB2> INFO: Expecting 5025280 events.
[11:27:49.670] <TB2> INFO: 830720 events read in total (30674ms).
[11:28:20.100] <TB2> INFO: 1658280 events read in total (61104ms).
[11:28:50.552] <TB2> INFO: 2483104 events read in total (91556ms).
[11:29:20.880] <TB2> INFO: 3304376 events read in total (121884ms).
[11:29:51.933] <TB2> INFO: 4122144 events read in total (152937ms).
[11:30:22.153] <TB2> INFO: 4939320 events read in total (183157ms).
[11:30:25.690] <TB2> INFO: 5025280 events read in total (186694ms).
[11:30:25.736] <TB2> INFO: Test took 187577ms.
[11:30:41.851] <TB2> INFO: ROC 0 VthrComp = 124
[11:30:41.851] <TB2> INFO: ROC 1 VthrComp = 129
[11:30:41.851] <TB2> INFO: ROC 2 VthrComp = 119
[11:30:41.851] <TB2> INFO: ROC 3 VthrComp = 123
[11:30:41.851] <TB2> INFO: ROC 4 VthrComp = 129
[11:30:41.851] <TB2> INFO: ROC 5 VthrComp = 126
[11:30:41.852] <TB2> INFO: ROC 6 VthrComp = 130
[11:30:41.852] <TB2> INFO: ROC 7 VthrComp = 125
[11:30:41.852] <TB2> INFO: ROC 8 VthrComp = 124
[11:30:41.852] <TB2> INFO: ROC 9 VthrComp = 126
[11:30:41.852] <TB2> INFO: ROC 10 VthrComp = 117
[11:30:41.852] <TB2> INFO: ROC 11 VthrComp = 133
[11:30:41.852] <TB2> INFO: ROC 12 VthrComp = 123
[11:30:41.853] <TB2> INFO: ROC 13 VthrComp = 120
[11:30:41.853] <TB2> INFO: ROC 14 VthrComp = 132
[11:30:41.853] <TB2> INFO: ROC 15 VthrComp = 120
[11:30:42.132] <TB2> INFO: Expecting 41600 events.
[11:30:45.688] <TB2> INFO: 41600 events read in total (2965ms).
[11:30:45.689] <TB2> INFO: Test took 3835ms.
[11:30:45.700] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[11:30:45.701] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:30:45.714] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:30:45.714] <TB2> INFO: run 1 of 1
[11:30:45.993] <TB2> INFO: Expecting 5025280 events.
[11:31:12.844] <TB2> INFO: 590528 events read in total (26260ms).
[11:31:39.163] <TB2> INFO: 1180480 events read in total (52579ms).
[11:32:05.102] <TB2> INFO: 1770448 events read in total (78518ms).
[11:32:31.207] <TB2> INFO: 2359608 events read in total (104623ms).
[11:32:57.435] <TB2> INFO: 2945696 events read in total (130851ms).
[11:33:22.986] <TB2> INFO: 3530784 events read in total (156402ms).
[11:33:49.169] <TB2> INFO: 4115360 events read in total (182585ms).
[11:34:15.842] <TB2> INFO: 4699696 events read in total (209258ms).
[11:34:30.544] <TB2> INFO: 5025280 events read in total (223961ms).
[11:34:30.611] <TB2> INFO: Test took 224897ms.
[11:34:53.221] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 59.3583 for pixel 12/2 mean/min/max = 45.769/32.0178/59.5203
[11:34:53.221] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 58.091 for pixel 17/22 mean/min/max = 44.8371/31.5317/58.1425
[11:34:53.222] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 57.9123 for pixel 21/3 mean/min/max = 45.1588/32.314/58.0036
[11:34:53.222] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 59.701 for pixel 15/72 mean/min/max = 46.2088/32.6784/59.7392
[11:34:53.223] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 62.5066 for pixel 13/14 mean/min/max = 47.4931/32.1316/62.8546
[11:34:53.223] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 61.199 for pixel 4/1 mean/min/max = 46.6684/32.1371/61.1997
[11:34:53.224] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 61.3228 for pixel 8/74 mean/min/max = 46.7374/32.0678/61.407
[11:34:53.224] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 58.1877 for pixel 9/79 mean/min/max = 45.6597/32.8163/58.503
[11:34:53.224] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 60.2243 for pixel 0/18 mean/min/max = 46.4762/32.7192/60.2333
[11:34:53.225] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 62.1105 for pixel 2/3 mean/min/max = 47.0899/31.9256/62.2542
[11:34:53.225] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 61.8205 for pixel 2/5 mean/min/max = 47.3651/32.8682/61.8619
[11:34:53.226] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 62.7208 for pixel 16/31 mean/min/max = 47.8975/32.9564/62.8387
[11:34:53.226] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 56.9411 for pixel 18/10 mean/min/max = 44.6776/32.0741/57.2812
[11:34:53.227] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 65.4404 for pixel 6/0 mean/min/max = 48.75/31.9726/65.5274
[11:34:53.227] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 58.024 for pixel 12/10 mean/min/max = 44.7465/31.3315/58.1615
[11:34:53.228] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 59.483 for pixel 10/69 mean/min/max = 46.2131/32.8234/59.6028
[11:34:53.228] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:34:53.317] <TB2> INFO: Expecting 411648 events.
[11:35:02.960] <TB2> INFO: 411648 events read in total (9051ms).
[11:35:02.968] <TB2> INFO: Expecting 411648 events.
[11:35:12.407] <TB2> INFO: 411648 events read in total (9036ms).
[11:35:12.418] <TB2> INFO: Expecting 411648 events.
[11:35:22.034] <TB2> INFO: 411648 events read in total (9212ms).
[11:35:22.051] <TB2> INFO: Expecting 411648 events.
[11:35:31.473] <TB2> INFO: 411648 events read in total (9019ms).
[11:35:31.489] <TB2> INFO: Expecting 411648 events.
[11:35:41.012] <TB2> INFO: 411648 events read in total (9120ms).
[11:35:41.032] <TB2> INFO: Expecting 411648 events.
[11:35:50.507] <TB2> INFO: 411648 events read in total (9072ms).
[11:35:50.529] <TB2> INFO: Expecting 411648 events.
[11:36:00.032] <TB2> INFO: 411648 events read in total (9100ms).
[11:36:00.057] <TB2> INFO: Expecting 411648 events.
[11:36:09.470] <TB2> INFO: 411648 events read in total (9010ms).
[11:36:09.498] <TB2> INFO: Expecting 411648 events.
[11:36:18.927] <TB2> INFO: 411648 events read in total (9026ms).
[11:36:18.957] <TB2> INFO: Expecting 411648 events.
[11:36:28.445] <TB2> INFO: 411648 events read in total (9085ms).
[11:36:28.477] <TB2> INFO: Expecting 411648 events.
[11:36:37.896] <TB2> INFO: 411648 events read in total (9016ms).
[11:36:37.932] <TB2> INFO: Expecting 411648 events.
[11:36:47.345] <TB2> INFO: 411648 events read in total (9009ms).
[11:36:47.383] <TB2> INFO: Expecting 411648 events.
[11:36:56.608] <TB2> INFO: 411648 events read in total (8822ms).
[11:36:56.650] <TB2> INFO: Expecting 411648 events.
[11:37:05.890] <TB2> INFO: 411648 events read in total (8837ms).
[11:37:05.935] <TB2> INFO: Expecting 411648 events.
[11:37:15.178] <TB2> INFO: 411648 events read in total (8840ms).
[11:37:15.225] <TB2> INFO: Expecting 411648 events.
[11:37:24.438] <TB2> INFO: 411648 events read in total (8810ms).
[11:37:24.491] <TB2> INFO: Test took 151263ms.
[11:37:25.276] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[11:37:25.290] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:37:25.290] <TB2> INFO: run 1 of 1
[11:37:25.526] <TB2> INFO: Expecting 5025280 events.
[11:37:52.300] <TB2> INFO: 589056 events read in total (26182ms).
[11:38:18.647] <TB2> INFO: 1175112 events read in total (52529ms).
[11:38:45.165] <TB2> INFO: 1761128 events read in total (79048ms).
[11:39:11.854] <TB2> INFO: 2345472 events read in total (105736ms).
[11:39:38.132] <TB2> INFO: 2931680 events read in total (132014ms).
[11:40:04.788] <TB2> INFO: 3519224 events read in total (158670ms).
[11:40:31.254] <TB2> INFO: 4107552 events read in total (185136ms).
[11:40:58.467] <TB2> INFO: 4695128 events read in total (212349ms).
[11:41:13.712] <TB2> INFO: 5025280 events read in total (227594ms).
[11:41:13.841] <TB2> INFO: Test took 228551ms.
[11:41:39.348] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 12.164850 .. 142.968696
[11:41:39.585] <TB2> INFO: Expecting 208000 events.
[11:41:49.208] <TB2> INFO: 208000 events read in total (9032ms).
[11:41:49.210] <TB2> INFO: Test took 9861ms.
[11:41:49.257] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 152 (-1/-1) hits flags = 528 (plus default)
[11:41:49.271] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:41:49.271] <TB2> INFO: run 1 of 1
[11:41:49.549] <TB2> INFO: Expecting 5025280 events.
[11:42:16.308] <TB2> INFO: 584536 events read in total (26167ms).
[11:42:42.066] <TB2> INFO: 1168704 events read in total (51925ms).
[11:43:08.009] <TB2> INFO: 1752664 events read in total (77868ms).
[11:43:33.805] <TB2> INFO: 2337040 events read in total (103664ms).
[11:44:00.022] <TB2> INFO: 2921008 events read in total (129881ms).
[11:44:26.243] <TB2> INFO: 3504544 events read in total (156102ms).
[11:44:52.761] <TB2> INFO: 4087800 events read in total (182620ms).
[11:45:18.833] <TB2> INFO: 4670976 events read in total (208692ms).
[11:45:34.944] <TB2> INFO: 5025280 events read in total (224803ms).
[11:45:35.052] <TB2> INFO: Test took 225781ms.
[11:45:59.099] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.405075 .. 46.776658
[11:45:59.337] <TB2> INFO: Expecting 208000 events.
[11:46:09.284] <TB2> INFO: 208000 events read in total (9355ms).
[11:46:09.285] <TB2> INFO: Test took 10184ms.
[11:46:09.341] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[11:46:09.354] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:46:09.354] <TB2> INFO: run 1 of 1
[11:46:09.660] <TB2> INFO: Expecting 1331200 events.
[11:46:38.372] <TB2> INFO: 655600 events read in total (28121ms).
[11:47:06.375] <TB2> INFO: 1308904 events read in total (56124ms).
[11:47:07.736] <TB2> INFO: 1331200 events read in total (57486ms).
[11:47:07.766] <TB2> INFO: Test took 58412ms.
[11:47:21.997] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 26.772163 .. 47.886993
[11:47:22.241] <TB2> INFO: Expecting 208000 events.
[11:47:32.140] <TB2> INFO: 208000 events read in total (9307ms).
[11:47:32.142] <TB2> INFO: Test took 10142ms.
[11:47:32.192] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 57 (-1/-1) hits flags = 528 (plus default)
[11:47:32.204] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:47:32.204] <TB2> INFO: run 1 of 1
[11:47:32.482] <TB2> INFO: Expecting 1397760 events.
[11:48:01.194] <TB2> INFO: 657016 events read in total (28121ms).
[11:48:29.098] <TB2> INFO: 1312400 events read in total (56025ms).
[11:48:33.064] <TB2> INFO: 1397760 events read in total (59991ms).
[11:48:33.096] <TB2> INFO: Test took 60893ms.
[11:48:47.558] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 25.455588 .. 46.795107
[11:48:47.797] <TB2> INFO: Expecting 208000 events.
[11:48:57.693] <TB2> INFO: 208000 events read in total (9304ms).
[11:48:57.694] <TB2> INFO: Test took 10135ms.
[11:48:57.744] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 56 (-1/-1) hits flags = 528 (plus default)
[11:48:57.757] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:48:57.757] <TB2> INFO: run 1 of 1
[11:48:58.035] <TB2> INFO: Expecting 1397760 events.
[11:49:27.564] <TB2> INFO: 664192 events read in total (28937ms).
[11:49:55.663] <TB2> INFO: 1328088 events read in total (57037ms).
[11:49:59.087] <TB2> INFO: 1397760 events read in total (60460ms).
[11:49:59.117] <TB2> INFO: Test took 61359ms.
[11:50:13.293] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[11:50:13.293] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[11:50:13.306] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:50:13.306] <TB2> INFO: run 1 of 1
[11:50:13.548] <TB2> INFO: Expecting 1364480 events.
[11:50:41.937] <TB2> INFO: 667728 events read in total (27798ms).
[11:51:10.151] <TB2> INFO: 1334632 events read in total (56012ms).
[11:51:11.802] <TB2> INFO: 1364480 events read in total (57663ms).
[11:51:11.832] <TB2> INFO: Test took 58525ms.
[11:51:25.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C0.dat
[11:51:25.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C1.dat
[11:51:25.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C2.dat
[11:51:25.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C3.dat
[11:51:25.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C4.dat
[11:51:25.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C5.dat
[11:51:25.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C6.dat
[11:51:25.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C7.dat
[11:51:25.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C8.dat
[11:51:25.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C9.dat
[11:51:25.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C10.dat
[11:51:25.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C11.dat
[11:51:25.856] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C12.dat
[11:51:25.857] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C13.dat
[11:51:25.857] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C14.dat
[11:51:25.857] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C15.dat
[11:51:25.857] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters35_C0.dat
[11:51:25.866] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters35_C1.dat
[11:51:25.871] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters35_C2.dat
[11:51:25.876] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters35_C3.dat
[11:51:25.881] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters35_C4.dat
[11:51:25.886] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters35_C5.dat
[11:51:25.891] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters35_C6.dat
[11:51:25.896] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters35_C7.dat
[11:51:25.901] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters35_C8.dat
[11:51:25.906] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters35_C9.dat
[11:51:25.912] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters35_C10.dat
[11:51:25.918] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters35_C11.dat
[11:51:25.924] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters35_C12.dat
[11:51:25.930] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters35_C13.dat
[11:51:25.936] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters35_C14.dat
[11:51:25.942] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//trimParameters35_C15.dat
[11:51:25.949] <TB2> INFO: PixTestTrim::trimTest() done
[11:51:25.949] <TB2> INFO: vtrim: 127 132 117 125 136 141 129 122 114 141 127 156 118 147 122 134
[11:51:25.949] <TB2> INFO: vthrcomp: 124 129 119 123 129 126 130 125 124 126 117 133 123 120 132 120
[11:51:25.949] <TB2> INFO: vcal mean: 34.94 34.91 34.94 34.98 35.35 34.97 35.04 35.01 34.95 35.11 35.18 35.05 35.01 35.07 34.89 35.01
[11:51:25.949] <TB2> INFO: vcal RMS: 0.96 1.06 0.97 1.11 1.53 0.98 1.11 0.97 1.10 1.23 1.34 1.15 0.97 1.17 1.06 1.07
[11:51:25.949] <TB2> INFO: bits mean: 9.24 9.85 9.86 9.48 9.50 9.20 9.41 9.07 8.95 9.38 9.46 9.14 9.76 9.24 9.80 9.73
[11:51:25.949] <TB2> INFO: bits RMS: 2.85 2.67 2.58 2.64 2.74 2.80 2.72 2.83 2.87 2.67 2.65 2.60 2.66 2.64 2.75 2.47
[11:51:25.957] <TB2> INFO: ----------------------------------------------------------------------
[11:51:25.957] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[11:51:25.957] <TB2> INFO: ----------------------------------------------------------------------
[11:51:25.960] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[11:51:25.973] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:51:25.973] <TB2> INFO: run 1 of 1
[11:51:26.217] <TB2> INFO: Expecting 4160000 events.
[11:51:59.482] <TB2> INFO: 772190 events read in total (32673ms).
[11:52:31.915] <TB2> INFO: 1536975 events read in total (65106ms).
[11:53:04.427] <TB2> INFO: 2295965 events read in total (97618ms).
[11:53:37.108] <TB2> INFO: 3052460 events read in total (130299ms).
[11:54:08.787] <TB2> INFO: 3805995 events read in total (161978ms).
[11:54:24.145] <TB2> INFO: 4160000 events read in total (177336ms).
[11:54:24.224] <TB2> INFO: Test took 178252ms.
[11:54:46.821] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[11:54:46.835] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:54:46.835] <TB2> INFO: run 1 of 1
[11:54:47.113] <TB2> INFO: Expecting 4264000 events.
[11:55:19.867] <TB2> INFO: 738285 events read in total (32162ms).
[11:55:51.657] <TB2> INFO: 1471030 events read in total (63952ms).
[11:56:23.593] <TB2> INFO: 2200315 events read in total (95888ms).
[11:56:55.552] <TB2> INFO: 2925430 events read in total (127847ms).
[11:57:28.293] <TB2> INFO: 3649470 events read in total (160588ms).
[11:57:55.074] <TB2> INFO: 4264000 events read in total (187369ms).
[11:57:55.202] <TB2> INFO: Test took 188367ms.
[11:58:19.551] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[11:58:19.566] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:58:19.566] <TB2> INFO: run 1 of 1
[11:58:19.803] <TB2> INFO: Expecting 4139200 events.
[11:58:52.446] <TB2> INFO: 747325 events read in total (32052ms).
[11:59:24.175] <TB2> INFO: 1488590 events read in total (63781ms).
[11:59:56.462] <TB2> INFO: 2226020 events read in total (96068ms).
[12:00:28.984] <TB2> INFO: 2960095 events read in total (128590ms).
[12:01:01.699] <TB2> INFO: 3691715 events read in total (161305ms).
[12:01:21.133] <TB2> INFO: 4139200 events read in total (180739ms).
[12:01:21.203] <TB2> INFO: Test took 181638ms.
[12:01:46.882] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[12:01:46.896] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:01:46.896] <TB2> INFO: run 1 of 1
[12:01:47.132] <TB2> INFO: Expecting 4139200 events.
[12:02:20.378] <TB2> INFO: 747900 events read in total (32655ms).
[12:02:52.620] <TB2> INFO: 1489415 events read in total (64897ms).
[12:03:24.837] <TB2> INFO: 2227480 events read in total (97114ms).
[12:03:57.683] <TB2> INFO: 2961840 events read in total (129960ms).
[12:04:29.805] <TB2> INFO: 3693650 events read in total (162082ms).
[12:04:49.513] <TB2> INFO: 4139200 events read in total (181790ms).
[12:04:49.605] <TB2> INFO: Test took 182709ms.
[12:05:14.121] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:05:14.135] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:05:14.135] <TB2> INFO: run 1 of 1
[12:05:14.371] <TB2> INFO: Expecting 4180800 events.
[12:05:47.027] <TB2> INFO: 744405 events read in total (32064ms).
[12:06:19.058] <TB2> INFO: 1483220 events read in total (64095ms).
[12:06:51.225] <TB2> INFO: 2218175 events read in total (96262ms).
[12:07:22.461] <TB2> INFO: 2949615 events read in total (127498ms).
[12:07:54.879] <TB2> INFO: 3678955 events read in total (159916ms).
[12:08:17.084] <TB2> INFO: 4180800 events read in total (182121ms).
[12:08:17.207] <TB2> INFO: Test took 183072ms.
[12:08:44.973] <TB2> INFO: PixTestTrim::trimBitTest() done
[12:08:44.974] <TB2> INFO: PixTestTrim::doTest() done, duration: 2486 seconds
[12:08:44.974] <TB2> INFO: Decoding statistics:
[12:08:44.974] <TB2> INFO: General information:
[12:08:44.974] <TB2> INFO: 16bit words read: 0
[12:08:44.974] <TB2> INFO: valid events total: 0
[12:08:44.974] <TB2> INFO: empty events: 0
[12:08:44.974] <TB2> INFO: valid events with pixels: 0
[12:08:44.974] <TB2> INFO: valid pixel hits: 0
[12:08:44.974] <TB2> INFO: Event errors: 0
[12:08:44.974] <TB2> INFO: start marker: 0
[12:08:44.974] <TB2> INFO: stop marker: 0
[12:08:44.974] <TB2> INFO: overflow: 0
[12:08:44.974] <TB2> INFO: invalid 5bit words: 0
[12:08:44.974] <TB2> INFO: invalid XOR eye diagram: 0
[12:08:44.974] <TB2> INFO: frame (failed synchr.): 0
[12:08:44.974] <TB2> INFO: idle data (no TBM trl): 0
[12:08:44.974] <TB2> INFO: no data (only TBM hdr): 0
[12:08:44.974] <TB2> INFO: TBM errors: 0
[12:08:44.974] <TB2> INFO: flawed TBM headers: 0
[12:08:44.974] <TB2> INFO: flawed TBM trailers: 0
[12:08:44.974] <TB2> INFO: event ID mismatches: 0
[12:08:44.974] <TB2> INFO: ROC errors: 0
[12:08:44.974] <TB2> INFO: missing ROC header(s): 0
[12:08:44.974] <TB2> INFO: misplaced readback start: 0
[12:08:44.974] <TB2> INFO: Pixel decoding errors: 0
[12:08:44.974] <TB2> INFO: pixel data incomplete: 0
[12:08:44.974] <TB2> INFO: pixel address: 0
[12:08:44.974] <TB2> INFO: pulse height fill bit: 0
[12:08:44.974] <TB2> INFO: buffer corruption: 0
[12:08:45.634] <TB2> INFO: ######################################################################
[12:08:45.634] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[12:08:45.634] <TB2> INFO: ######################################################################
[12:08:45.884] <TB2> INFO: Expecting 41600 events.
[12:08:49.484] <TB2> INFO: 41600 events read in total (3009ms).
[12:08:49.484] <TB2> INFO: Test took 3848ms.
[12:08:49.924] <TB2> INFO: Expecting 41600 events.
[12:08:53.597] <TB2> INFO: 41600 events read in total (3081ms).
[12:08:53.598] <TB2> INFO: Test took 3910ms.
[12:08:53.887] <TB2> INFO: Expecting 41600 events.
[12:08:57.439] <TB2> INFO: 41600 events read in total (2960ms).
[12:08:57.440] <TB2> INFO: Test took 3818ms.
[12:08:57.729] <TB2> INFO: Expecting 41600 events.
[12:09:01.320] <TB2> INFO: 41600 events read in total (2999ms).
[12:09:01.321] <TB2> INFO: Test took 3857ms.
[12:09:01.610] <TB2> INFO: Expecting 41600 events.
[12:09:05.221] <TB2> INFO: 41600 events read in total (3019ms).
[12:09:05.222] <TB2> INFO: Test took 3877ms.
[12:09:05.533] <TB2> INFO: Expecting 41600 events.
[12:09:09.083] <TB2> INFO: 41600 events read in total (2958ms).
[12:09:09.084] <TB2> INFO: Test took 3837ms.
[12:09:09.389] <TB2> INFO: Expecting 41600 events.
[12:09:12.963] <TB2> INFO: 41600 events read in total (2982ms).
[12:09:12.964] <TB2> INFO: Test took 3856ms.
[12:09:13.253] <TB2> INFO: Expecting 41600 events.
[12:09:16.851] <TB2> INFO: 41600 events read in total (3006ms).
[12:09:16.852] <TB2> INFO: Test took 3864ms.
[12:09:17.142] <TB2> INFO: Expecting 41600 events.
[12:09:20.760] <TB2> INFO: 41600 events read in total (3026ms).
[12:09:20.760] <TB2> INFO: Test took 3884ms.
[12:09:21.050] <TB2> INFO: Expecting 41600 events.
[12:09:24.641] <TB2> INFO: 41600 events read in total (2999ms).
[12:09:24.642] <TB2> INFO: Test took 3857ms.
[12:09:24.953] <TB2> INFO: Expecting 41600 events.
[12:09:28.497] <TB2> INFO: 41600 events read in total (2952ms).
[12:09:28.497] <TB2> INFO: Test took 3831ms.
[12:09:28.787] <TB2> INFO: Expecting 41600 events.
[12:09:32.316] <TB2> INFO: 41600 events read in total (2937ms).
[12:09:32.317] <TB2> INFO: Test took 3795ms.
[12:09:32.607] <TB2> INFO: Expecting 41600 events.
[12:09:36.151] <TB2> INFO: 41600 events read in total (2953ms).
[12:09:36.152] <TB2> INFO: Test took 3811ms.
[12:09:36.442] <TB2> INFO: Expecting 41600 events.
[12:09:39.950] <TB2> INFO: 41600 events read in total (2917ms).
[12:09:39.950] <TB2> INFO: Test took 3774ms.
[12:09:40.240] <TB2> INFO: Expecting 41600 events.
[12:09:43.816] <TB2> INFO: 41600 events read in total (2985ms).
[12:09:43.817] <TB2> INFO: Test took 3842ms.
[12:09:44.123] <TB2> INFO: Expecting 41600 events.
[12:09:47.628] <TB2> INFO: 41600 events read in total (2913ms).
[12:09:47.629] <TB2> INFO: Test took 3786ms.
[12:09:47.921] <TB2> INFO: Expecting 41600 events.
[12:09:51.459] <TB2> INFO: 41600 events read in total (2946ms).
[12:09:51.460] <TB2> INFO: Test took 3804ms.
[12:09:51.750] <TB2> INFO: Expecting 41600 events.
[12:09:55.278] <TB2> INFO: 41600 events read in total (2936ms).
[12:09:55.279] <TB2> INFO: Test took 3794ms.
[12:09:55.569] <TB2> INFO: Expecting 41600 events.
[12:09:59.137] <TB2> INFO: 41600 events read in total (2976ms).
[12:09:59.138] <TB2> INFO: Test took 3834ms.
[12:09:59.428] <TB2> INFO: Expecting 41600 events.
[12:10:02.963] <TB2> INFO: 41600 events read in total (2944ms).
[12:10:02.964] <TB2> INFO: Test took 3802ms.
[12:10:03.275] <TB2> INFO: Expecting 41600 events.
[12:10:06.883] <TB2> INFO: 41600 events read in total (3016ms).
[12:10:06.884] <TB2> INFO: Test took 3896ms.
[12:10:07.174] <TB2> INFO: Expecting 41600 events.
[12:10:10.817] <TB2> INFO: 41600 events read in total (3052ms).
[12:10:10.818] <TB2> INFO: Test took 3910ms.
[12:10:11.111] <TB2> INFO: Expecting 41600 events.
[12:10:14.778] <TB2> INFO: 41600 events read in total (3075ms).
[12:10:14.779] <TB2> INFO: Test took 3934ms.
[12:10:15.084] <TB2> INFO: Expecting 41600 events.
[12:10:18.652] <TB2> INFO: 41600 events read in total (2976ms).
[12:10:18.653] <TB2> INFO: Test took 3850ms.
[12:10:18.942] <TB2> INFO: Expecting 41600 events.
[12:10:22.561] <TB2> INFO: 41600 events read in total (3027ms).
[12:10:22.561] <TB2> INFO: Test took 3884ms.
[12:10:22.852] <TB2> INFO: Expecting 41600 events.
[12:10:26.463] <TB2> INFO: 41600 events read in total (3019ms).
[12:10:26.464] <TB2> INFO: Test took 3878ms.
[12:10:26.759] <TB2> INFO: Expecting 41600 events.
[12:10:30.357] <TB2> INFO: 41600 events read in total (3006ms).
[12:10:30.358] <TB2> INFO: Test took 3865ms.
[12:10:30.650] <TB2> INFO: Expecting 41600 events.
[12:10:34.243] <TB2> INFO: 41600 events read in total (3001ms).
[12:10:34.244] <TB2> INFO: Test took 3860ms.
[12:10:34.535] <TB2> INFO: Expecting 2560 events.
[12:10:35.428] <TB2> INFO: 2560 events read in total (302ms).
[12:10:35.429] <TB2> INFO: Test took 1172ms.
[12:10:35.736] <TB2> INFO: Expecting 2560 events.
[12:10:36.628] <TB2> INFO: 2560 events read in total (300ms).
[12:10:36.628] <TB2> INFO: Test took 1199ms.
[12:10:36.937] <TB2> INFO: Expecting 2560 events.
[12:10:37.827] <TB2> INFO: 2560 events read in total (299ms).
[12:10:37.827] <TB2> INFO: Test took 1198ms.
[12:10:38.135] <TB2> INFO: Expecting 2560 events.
[12:10:39.021] <TB2> INFO: 2560 events read in total (295ms).
[12:10:39.022] <TB2> INFO: Test took 1194ms.
[12:10:39.330] <TB2> INFO: Expecting 2560 events.
[12:10:40.209] <TB2> INFO: 2560 events read in total (288ms).
[12:10:40.209] <TB2> INFO: Test took 1187ms.
[12:10:40.517] <TB2> INFO: Expecting 2560 events.
[12:10:41.399] <TB2> INFO: 2560 events read in total (291ms).
[12:10:41.400] <TB2> INFO: Test took 1190ms.
[12:10:41.707] <TB2> INFO: Expecting 2560 events.
[12:10:42.588] <TB2> INFO: 2560 events read in total (290ms).
[12:10:42.589] <TB2> INFO: Test took 1188ms.
[12:10:42.896] <TB2> INFO: Expecting 2560 events.
[12:10:43.788] <TB2> INFO: 2560 events read in total (301ms).
[12:10:43.788] <TB2> INFO: Test took 1198ms.
[12:10:44.096] <TB2> INFO: Expecting 2560 events.
[12:10:44.983] <TB2> INFO: 2560 events read in total (295ms).
[12:10:44.984] <TB2> INFO: Test took 1195ms.
[12:10:45.292] <TB2> INFO: Expecting 2560 events.
[12:10:46.173] <TB2> INFO: 2560 events read in total (289ms).
[12:10:46.173] <TB2> INFO: Test took 1189ms.
[12:10:46.482] <TB2> INFO: Expecting 2560 events.
[12:10:47.363] <TB2> INFO: 2560 events read in total (290ms).
[12:10:47.363] <TB2> INFO: Test took 1189ms.
[12:10:47.671] <TB2> INFO: Expecting 2560 events.
[12:10:48.559] <TB2> INFO: 2560 events read in total (297ms).
[12:10:48.559] <TB2> INFO: Test took 1195ms.
[12:10:48.866] <TB2> INFO: Expecting 2560 events.
[12:10:49.763] <TB2> INFO: 2560 events read in total (305ms).
[12:10:49.763] <TB2> INFO: Test took 1203ms.
[12:10:50.072] <TB2> INFO: Expecting 2560 events.
[12:10:50.967] <TB2> INFO: 2560 events read in total (303ms).
[12:10:50.968] <TB2> INFO: Test took 1204ms.
[12:10:51.275] <TB2> INFO: Expecting 2560 events.
[12:10:52.163] <TB2> INFO: 2560 events read in total (296ms).
[12:10:52.163] <TB2> INFO: Test took 1194ms.
[12:10:52.470] <TB2> INFO: Expecting 2560 events.
[12:10:53.354] <TB2> INFO: 2560 events read in total (292ms).
[12:10:53.355] <TB2> INFO: Test took 1191ms.
[12:10:53.359] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:10:53.663] <TB2> INFO: Expecting 655360 events.
[12:11:08.482] <TB2> INFO: 655360 events read in total (14227ms).
[12:11:08.495] <TB2> INFO: Expecting 655360 events.
[12:11:23.295] <TB2> INFO: 655360 events read in total (14397ms).
[12:11:23.312] <TB2> INFO: Expecting 655360 events.
[12:11:38.101] <TB2> INFO: 655360 events read in total (14386ms).
[12:11:38.130] <TB2> INFO: Expecting 655360 events.
[12:11:52.917] <TB2> INFO: 655360 events read in total (14384ms).
[12:11:52.943] <TB2> INFO: Expecting 655360 events.
[12:12:07.646] <TB2> INFO: 655360 events read in total (14299ms).
[12:12:07.676] <TB2> INFO: Expecting 655360 events.
[12:12:22.370] <TB2> INFO: 655360 events read in total (14291ms).
[12:12:22.404] <TB2> INFO: Expecting 655360 events.
[12:12:37.198] <TB2> INFO: 655360 events read in total (14391ms).
[12:12:37.237] <TB2> INFO: Expecting 655360 events.
[12:12:51.878] <TB2> INFO: 655360 events read in total (14238ms).
[12:12:51.936] <TB2> INFO: Expecting 655360 events.
[12:13:06.630] <TB2> INFO: 655360 events read in total (14291ms).
[12:13:06.686] <TB2> INFO: Expecting 655360 events.
[12:13:21.398] <TB2> INFO: 655360 events read in total (14309ms).
[12:13:21.450] <TB2> INFO: Expecting 655360 events.
[12:13:36.075] <TB2> INFO: 655360 events read in total (14222ms).
[12:13:36.134] <TB2> INFO: Expecting 655360 events.
[12:13:50.946] <TB2> INFO: 655360 events read in total (14409ms).
[12:13:51.113] <TB2> INFO: Expecting 655360 events.
[12:14:05.848] <TB2> INFO: 655360 events read in total (14332ms).
[12:14:05.930] <TB2> INFO: Expecting 655360 events.
[12:14:20.655] <TB2> INFO: 655360 events read in total (14322ms).
[12:14:20.771] <TB2> INFO: Expecting 655360 events.
[12:14:35.418] <TB2> INFO: 655360 events read in total (14244ms).
[12:14:35.512] <TB2> INFO: Expecting 655360 events.
[12:14:50.257] <TB2> INFO: 655360 events read in total (14342ms).
[12:14:50.357] <TB2> INFO: Test took 236998ms.
[12:14:50.459] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:14:50.710] <TB2> INFO: Expecting 655360 events.
[12:15:05.476] <TB2> INFO: 655360 events read in total (14174ms).
[12:15:05.488] <TB2> INFO: Expecting 655360 events.
[12:15:20.159] <TB2> INFO: 655360 events read in total (14268ms).
[12:15:20.176] <TB2> INFO: Expecting 655360 events.
[12:15:34.700] <TB2> INFO: 655360 events read in total (14121ms).
[12:15:34.721] <TB2> INFO: Expecting 655360 events.
[12:15:48.985] <TB2> INFO: 655360 events read in total (13861ms).
[12:15:49.018] <TB2> INFO: Expecting 655360 events.
[12:16:03.505] <TB2> INFO: 655360 events read in total (14084ms).
[12:16:03.536] <TB2> INFO: Expecting 655360 events.
[12:16:17.998] <TB2> INFO: 655360 events read in total (14059ms).
[12:16:18.034] <TB2> INFO: Expecting 655360 events.
[12:16:32.602] <TB2> INFO: 655360 events read in total (14165ms).
[12:16:32.641] <TB2> INFO: Expecting 655360 events.
[12:16:47.185] <TB2> INFO: 655360 events read in total (14142ms).
[12:16:47.242] <TB2> INFO: Expecting 655360 events.
[12:17:01.615] <TB2> INFO: 655360 events read in total (13970ms).
[12:17:01.678] <TB2> INFO: Expecting 655360 events.
[12:17:15.869] <TB2> INFO: 655360 events read in total (13788ms).
[12:17:15.923] <TB2> INFO: Expecting 655360 events.
[12:17:30.319] <TB2> INFO: 655360 events read in total (13993ms).
[12:17:30.392] <TB2> INFO: Expecting 655360 events.
[12:17:44.943] <TB2> INFO: 655360 events read in total (14148ms).
[12:17:45.017] <TB2> INFO: Expecting 655360 events.
[12:17:59.552] <TB2> INFO: 655360 events read in total (14132ms).
[12:17:59.635] <TB2> INFO: Expecting 655360 events.
[12:18:13.998] <TB2> INFO: 655360 events read in total (13960ms).
[12:18:14.098] <TB2> INFO: Expecting 655360 events.
[12:18:28.367] <TB2> INFO: 655360 events read in total (13866ms).
[12:18:28.459] <TB2> INFO: Expecting 655360 events.
[12:18:43.384] <TB2> INFO: 655360 events read in total (14523ms).
[12:18:43.486] <TB2> INFO: Test took 233027ms.
[12:18:43.656] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:18:43.662] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:18:43.668] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:18:43.674] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[12:18:43.679] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[12:18:43.685] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[12:18:43.691] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[12:18:43.697] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[12:18:43.703] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[12:18:43.709] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[12:18:43.716] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[12:18:43.722] <TB2> INFO: safety margin for low PH: adding 11, margin is now 31
[12:18:43.728] <TB2> INFO: safety margin for low PH: adding 12, margin is now 32
[12:18:43.734] <TB2> INFO: safety margin for low PH: adding 13, margin is now 33
[12:18:43.740] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:18:43.746] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:18:43.752] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:18:43.758] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:18:43.765] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[12:18:43.771] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:18:43.777] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:18:43.783] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:18:43.789] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:18:43.795] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:18:43.801] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:18:43.806] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:18:43.813] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:18:43.818] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:18:43.824] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[12:18:43.830] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[12:18:43.836] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[12:18:43.842] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[12:18:43.848] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:18:43.854] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:18:43.861] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:18:43.867] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[12:18:43.873] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[12:18:43.878] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[12:18:43.884] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[12:18:43.890] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[12:18:43.896] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[12:18:43.902] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[12:18:43.907] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:18:43.913] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:18:43.919] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:18:43.924] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[12:18:43.930] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[12:18:43.936] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[12:18:43.942] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[12:18:43.948] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[12:18:43.954] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[12:18:43.959] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[12:18:43.965] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:18:43.971] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:18:43.977] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:18:43.982] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[12:18:43.988] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[12:18:43.994] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[12:18:43.000] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[12:18:43.005] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[12:18:44.011] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:18:44.017] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:18:44.023] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:18:44.029] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:18:44.034] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:18:44.070] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C0.dat
[12:18:44.070] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C1.dat
[12:18:44.070] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C2.dat
[12:18:44.070] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C3.dat
[12:18:44.070] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C4.dat
[12:18:44.070] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C5.dat
[12:18:44.070] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C6.dat
[12:18:44.071] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C7.dat
[12:18:44.071] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C8.dat
[12:18:44.071] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C9.dat
[12:18:44.071] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C10.dat
[12:18:44.071] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C11.dat
[12:18:44.071] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C12.dat
[12:18:44.071] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C13.dat
[12:18:44.071] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C14.dat
[12:18:44.072] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//dacParameters35_C15.dat
[12:18:44.371] <TB2> INFO: Expecting 41600 events.
[12:18:47.574] <TB2> INFO: 41600 events read in total (2611ms).
[12:18:47.575] <TB2> INFO: Test took 3498ms.
[12:18:48.046] <TB2> INFO: Expecting 41600 events.
[12:18:51.110] <TB2> INFO: 41600 events read in total (2472ms).
[12:18:51.111] <TB2> INFO: Test took 3321ms.
[12:18:51.571] <TB2> INFO: Expecting 41600 events.
[12:18:54.785] <TB2> INFO: 41600 events read in total (2622ms).
[12:18:54.785] <TB2> INFO: Test took 3459ms.
[12:18:55.007] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:18:55.097] <TB2> INFO: Expecting 2560 events.
[12:18:55.986] <TB2> INFO: 2560 events read in total (297ms).
[12:18:55.986] <TB2> INFO: Test took 979ms.
[12:18:55.989] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:18:56.295] <TB2> INFO: Expecting 2560 events.
[12:18:57.186] <TB2> INFO: 2560 events read in total (299ms).
[12:18:57.187] <TB2> INFO: Test took 1198ms.
[12:18:57.190] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:18:57.495] <TB2> INFO: Expecting 2560 events.
[12:18:58.386] <TB2> INFO: 2560 events read in total (299ms).
[12:18:58.386] <TB2> INFO: Test took 1196ms.
[12:18:58.389] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:18:58.694] <TB2> INFO: Expecting 2560 events.
[12:18:59.586] <TB2> INFO: 2560 events read in total (301ms).
[12:18:59.587] <TB2> INFO: Test took 1198ms.
[12:18:59.592] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:18:59.895] <TB2> INFO: Expecting 2560 events.
[12:19:00.790] <TB2> INFO: 2560 events read in total (303ms).
[12:19:00.790] <TB2> INFO: Test took 1198ms.
[12:19:00.794] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:01.098] <TB2> INFO: Expecting 2560 events.
[12:19:01.995] <TB2> INFO: 2560 events read in total (305ms).
[12:19:01.996] <TB2> INFO: Test took 1202ms.
[12:19:01.999] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:02.303] <TB2> INFO: Expecting 2560 events.
[12:19:03.199] <TB2> INFO: 2560 events read in total (304ms).
[12:19:03.199] <TB2> INFO: Test took 1200ms.
[12:19:03.201] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:03.508] <TB2> INFO: Expecting 2560 events.
[12:19:04.401] <TB2> INFO: 2560 events read in total (301ms).
[12:19:04.402] <TB2> INFO: Test took 1201ms.
[12:19:04.406] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:04.710] <TB2> INFO: Expecting 2560 events.
[12:19:05.599] <TB2> INFO: 2560 events read in total (297ms).
[12:19:05.600] <TB2> INFO: Test took 1194ms.
[12:19:05.604] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:05.908] <TB2> INFO: Expecting 2560 events.
[12:19:06.793] <TB2> INFO: 2560 events read in total (293ms).
[12:19:06.793] <TB2> INFO: Test took 1189ms.
[12:19:06.798] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:07.101] <TB2> INFO: Expecting 2560 events.
[12:19:07.992] <TB2> INFO: 2560 events read in total (299ms).
[12:19:07.992] <TB2> INFO: Test took 1194ms.
[12:19:07.996] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:08.300] <TB2> INFO: Expecting 2560 events.
[12:19:09.186] <TB2> INFO: 2560 events read in total (293ms).
[12:19:09.187] <TB2> INFO: Test took 1192ms.
[12:19:09.190] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:09.495] <TB2> INFO: Expecting 2560 events.
[12:19:10.385] <TB2> INFO: 2560 events read in total (299ms).
[12:19:10.385] <TB2> INFO: Test took 1195ms.
[12:19:10.389] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:10.693] <TB2> INFO: Expecting 2560 events.
[12:19:11.580] <TB2> INFO: 2560 events read in total (295ms).
[12:19:11.581] <TB2> INFO: Test took 1192ms.
[12:19:11.583] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:11.889] <TB2> INFO: Expecting 2560 events.
[12:19:12.781] <TB2> INFO: 2560 events read in total (300ms).
[12:19:12.781] <TB2> INFO: Test took 1199ms.
[12:19:12.785] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:13.090] <TB2> INFO: Expecting 2560 events.
[12:19:13.977] <TB2> INFO: 2560 events read in total (295ms).
[12:19:13.978] <TB2> INFO: Test took 1193ms.
[12:19:13.981] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:14.287] <TB2> INFO: Expecting 2560 events.
[12:19:15.172] <TB2> INFO: 2560 events read in total (294ms).
[12:19:15.173] <TB2> INFO: Test took 1192ms.
[12:19:15.176] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:15.481] <TB2> INFO: Expecting 2560 events.
[12:19:16.365] <TB2> INFO: 2560 events read in total (292ms).
[12:19:16.365] <TB2> INFO: Test took 1189ms.
[12:19:16.369] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:16.674] <TB2> INFO: Expecting 2560 events.
[12:19:17.568] <TB2> INFO: 2560 events read in total (302ms).
[12:19:17.569] <TB2> INFO: Test took 1200ms.
[12:19:17.574] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:17.877] <TB2> INFO: Expecting 2560 events.
[12:19:18.765] <TB2> INFO: 2560 events read in total (296ms).
[12:19:18.765] <TB2> INFO: Test took 1191ms.
[12:19:18.770] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:19.073] <TB2> INFO: Expecting 2560 events.
[12:19:19.962] <TB2> INFO: 2560 events read in total (297ms).
[12:19:19.963] <TB2> INFO: Test took 1194ms.
[12:19:19.968] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:20.270] <TB2> INFO: Expecting 2560 events.
[12:19:21.164] <TB2> INFO: 2560 events read in total (302ms).
[12:19:21.164] <TB2> INFO: Test took 1196ms.
[12:19:21.167] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:21.471] <TB2> INFO: Expecting 2560 events.
[12:19:22.360] <TB2> INFO: 2560 events read in total (297ms).
[12:19:22.360] <TB2> INFO: Test took 1193ms.
[12:19:22.363] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:22.669] <TB2> INFO: Expecting 2560 events.
[12:19:23.558] <TB2> INFO: 2560 events read in total (298ms).
[12:19:23.559] <TB2> INFO: Test took 1196ms.
[12:19:23.562] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:23.867] <TB2> INFO: Expecting 2560 events.
[12:19:24.760] <TB2> INFO: 2560 events read in total (301ms).
[12:19:24.760] <TB2> INFO: Test took 1198ms.
[12:19:24.765] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:25.067] <TB2> INFO: Expecting 2560 events.
[12:19:25.960] <TB2> INFO: 2560 events read in total (301ms).
[12:19:25.960] <TB2> INFO: Test took 1195ms.
[12:19:25.962] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:26.270] <TB2> INFO: Expecting 2560 events.
[12:19:27.163] <TB2> INFO: 2560 events read in total (301ms).
[12:19:27.164] <TB2> INFO: Test took 1202ms.
[12:19:27.169] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:27.472] <TB2> INFO: Expecting 2560 events.
[12:19:28.363] <TB2> INFO: 2560 events read in total (299ms).
[12:19:28.363] <TB2> INFO: Test took 1194ms.
[12:19:28.367] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:28.672] <TB2> INFO: Expecting 2560 events.
[12:19:29.558] <TB2> INFO: 2560 events read in total (295ms).
[12:19:29.559] <TB2> INFO: Test took 1192ms.
[12:19:29.565] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:29.867] <TB2> INFO: Expecting 2560 events.
[12:19:30.761] <TB2> INFO: 2560 events read in total (302ms).
[12:19:30.761] <TB2> INFO: Test took 1197ms.
[12:19:30.765] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:31.070] <TB2> INFO: Expecting 2560 events.
[12:19:31.962] <TB2> INFO: 2560 events read in total (301ms).
[12:19:31.962] <TB2> INFO: Test took 1197ms.
[12:19:31.966] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:19:32.271] <TB2> INFO: Expecting 2560 events.
[12:19:33.160] <TB2> INFO: 2560 events read in total (297ms).
[12:19:33.160] <TB2> INFO: Test took 1194ms.
[12:19:33.627] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 647 seconds
[12:19:33.627] <TB2> INFO: PH scale (per ROC): 48 49 54 47 40 50 35 48 35 30 43 40 34 41 43 38
[12:19:33.627] <TB2> INFO: PH offset (per ROC): 92 100 129 117 104 127 102 112 85 100 112 109 91 102 98 105
[12:19:33.635] <TB2> INFO: Decoding statistics:
[12:19:33.635] <TB2> INFO: General information:
[12:19:33.635] <TB2> INFO: 16bit words read: 127882
[12:19:33.635] <TB2> INFO: valid events total: 20480
[12:19:33.635] <TB2> INFO: empty events: 17979
[12:19:33.635] <TB2> INFO: valid events with pixels: 2501
[12:19:33.635] <TB2> INFO: valid pixel hits: 2501
[12:19:33.635] <TB2> INFO: Event errors: 0
[12:19:33.635] <TB2> INFO: start marker: 0
[12:19:33.635] <TB2> INFO: stop marker: 0
[12:19:33.635] <TB2> INFO: overflow: 0
[12:19:33.635] <TB2> INFO: invalid 5bit words: 0
[12:19:33.635] <TB2> INFO: invalid XOR eye diagram: 0
[12:19:33.635] <TB2> INFO: frame (failed synchr.): 0
[12:19:33.635] <TB2> INFO: idle data (no TBM trl): 0
[12:19:33.635] <TB2> INFO: no data (only TBM hdr): 0
[12:19:33.635] <TB2> INFO: TBM errors: 0
[12:19:33.635] <TB2> INFO: flawed TBM headers: 0
[12:19:33.635] <TB2> INFO: flawed TBM trailers: 0
[12:19:33.635] <TB2> INFO: event ID mismatches: 0
[12:19:33.635] <TB2> INFO: ROC errors: 0
[12:19:33.635] <TB2> INFO: missing ROC header(s): 0
[12:19:33.635] <TB2> INFO: misplaced readback start: 0
[12:19:33.635] <TB2> INFO: Pixel decoding errors: 0
[12:19:33.635] <TB2> INFO: pixel data incomplete: 0
[12:19:33.636] <TB2> INFO: pixel address: 0
[12:19:33.636] <TB2> INFO: pulse height fill bit: 0
[12:19:33.636] <TB2> INFO: buffer corruption: 0
[12:19:33.798] <TB2> INFO: ######################################################################
[12:19:33.798] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[12:19:33.798] <TB2> INFO: ######################################################################
[12:19:33.813] <TB2> INFO: scanning low vcal = 10
[12:19:34.054] <TB2> INFO: Expecting 41600 events.
[12:19:37.630] <TB2> INFO: 41600 events read in total (2984ms).
[12:19:37.630] <TB2> INFO: Test took 3817ms.
[12:19:37.633] <TB2> INFO: scanning low vcal = 20
[12:19:37.928] <TB2> INFO: Expecting 41600 events.
[12:19:41.508] <TB2> INFO: 41600 events read in total (2989ms).
[12:19:41.508] <TB2> INFO: Test took 3875ms.
[12:19:41.510] <TB2> INFO: scanning low vcal = 30
[12:19:41.805] <TB2> INFO: Expecting 41600 events.
[12:19:45.490] <TB2> INFO: 41600 events read in total (3094ms).
[12:19:45.491] <TB2> INFO: Test took 3981ms.
[12:19:45.494] <TB2> INFO: scanning low vcal = 40
[12:19:45.771] <TB2> INFO: Expecting 41600 events.
[12:19:49.803] <TB2> INFO: 41600 events read in total (3438ms).
[12:19:49.804] <TB2> INFO: Test took 4310ms.
[12:19:49.808] <TB2> INFO: scanning low vcal = 50
[12:19:50.085] <TB2> INFO: Expecting 41600 events.
[12:19:54.106] <TB2> INFO: 41600 events read in total (3430ms).
[12:19:54.107] <TB2> INFO: Test took 4299ms.
[12:19:54.111] <TB2> INFO: scanning low vcal = 60
[12:19:54.388] <TB2> INFO: Expecting 41600 events.
[12:19:58.414] <TB2> INFO: 41600 events read in total (3435ms).
[12:19:58.415] <TB2> INFO: Test took 4304ms.
[12:19:58.418] <TB2> INFO: scanning low vcal = 70
[12:19:58.695] <TB2> INFO: Expecting 41600 events.
[12:20:02.714] <TB2> INFO: 41600 events read in total (3427ms).
[12:20:02.715] <TB2> INFO: Test took 4297ms.
[12:20:02.718] <TB2> INFO: scanning low vcal = 80
[12:20:02.995] <TB2> INFO: Expecting 41600 events.
[12:20:07.026] <TB2> INFO: 41600 events read in total (3440ms).
[12:20:07.027] <TB2> INFO: Test took 4309ms.
[12:20:07.030] <TB2> INFO: scanning low vcal = 90
[12:20:07.307] <TB2> INFO: Expecting 41600 events.
[12:20:11.323] <TB2> INFO: 41600 events read in total (3424ms).
[12:20:11.324] <TB2> INFO: Test took 4294ms.
[12:20:11.328] <TB2> INFO: scanning low vcal = 100
[12:20:11.604] <TB2> INFO: Expecting 41600 events.
[12:20:15.620] <TB2> INFO: 41600 events read in total (3424ms).
[12:20:15.620] <TB2> INFO: Test took 4292ms.
[12:20:15.623] <TB2> INFO: scanning low vcal = 110
[12:20:15.900] <TB2> INFO: Expecting 41600 events.
[12:20:19.844] <TB2> INFO: 41600 events read in total (3352ms).
[12:20:19.845] <TB2> INFO: Test took 4223ms.
[12:20:19.849] <TB2> INFO: scanning low vcal = 120
[12:20:20.125] <TB2> INFO: Expecting 41600 events.
[12:20:24.086] <TB2> INFO: 41600 events read in total (3369ms).
[12:20:24.087] <TB2> INFO: Test took 4238ms.
[12:20:24.090] <TB2> INFO: scanning low vcal = 130
[12:20:24.370] <TB2> INFO: Expecting 41600 events.
[12:20:28.306] <TB2> INFO: 41600 events read in total (3344ms).
[12:20:28.307] <TB2> INFO: Test took 4217ms.
[12:20:28.311] <TB2> INFO: scanning low vcal = 140
[12:20:28.587] <TB2> INFO: Expecting 41600 events.
[12:20:32.554] <TB2> INFO: 41600 events read in total (3375ms).
[12:20:32.555] <TB2> INFO: Test took 4244ms.
[12:20:32.559] <TB2> INFO: scanning low vcal = 150
[12:20:32.835] <TB2> INFO: Expecting 41600 events.
[12:20:36.776] <TB2> INFO: 41600 events read in total (3350ms).
[12:20:36.777] <TB2> INFO: Test took 4218ms.
[12:20:36.781] <TB2> INFO: scanning low vcal = 160
[12:20:37.057] <TB2> INFO: Expecting 41600 events.
[12:20:40.000] <TB2> INFO: 41600 events read in total (3351ms).
[12:20:40.001] <TB2> INFO: Test took 4219ms.
[12:20:40.005] <TB2> INFO: scanning low vcal = 170
[12:20:41.284] <TB2> INFO: Expecting 41600 events.
[12:20:45.396] <TB2> INFO: 41600 events read in total (3520ms).
[12:20:45.397] <TB2> INFO: Test took 4392ms.
[12:20:45.403] <TB2> INFO: scanning low vcal = 180
[12:20:45.728] <TB2> INFO: Expecting 41600 events.
[12:20:49.689] <TB2> INFO: 41600 events read in total (3370ms).
[12:20:49.690] <TB2> INFO: Test took 4287ms.
[12:20:49.693] <TB2> INFO: scanning low vcal = 190
[12:20:49.969] <TB2> INFO: Expecting 41600 events.
[12:20:53.975] <TB2> INFO: 41600 events read in total (3414ms).
[12:20:53.976] <TB2> INFO: Test took 4282ms.
[12:20:53.979] <TB2> INFO: scanning low vcal = 200
[12:20:54.256] <TB2> INFO: Expecting 41600 events.
[12:20:58.268] <TB2> INFO: 41600 events read in total (3420ms).
[12:20:58.268] <TB2> INFO: Test took 4289ms.
[12:20:58.271] <TB2> INFO: scanning low vcal = 210
[12:20:58.548] <TB2> INFO: Expecting 41600 events.
[12:21:02.580] <TB2> INFO: 41600 events read in total (3440ms).
[12:21:02.581] <TB2> INFO: Test took 4310ms.
[12:21:02.584] <TB2> INFO: scanning low vcal = 220
[12:21:02.860] <TB2> INFO: Expecting 41600 events.
[12:21:06.920] <TB2> INFO: 41600 events read in total (3469ms).
[12:21:06.921] <TB2> INFO: Test took 4337ms.
[12:21:06.924] <TB2> INFO: scanning low vcal = 230
[12:21:07.200] <TB2> INFO: Expecting 41600 events.
[12:21:11.242] <TB2> INFO: 41600 events read in total (3450ms).
[12:21:11.243] <TB2> INFO: Test took 4319ms.
[12:21:11.247] <TB2> INFO: scanning low vcal = 240
[12:21:11.523] <TB2> INFO: Expecting 41600 events.
[12:21:15.543] <TB2> INFO: 41600 events read in total (3428ms).
[12:21:15.544] <TB2> INFO: Test took 4297ms.
[12:21:15.547] <TB2> INFO: scanning low vcal = 250
[12:21:15.823] <TB2> INFO: Expecting 41600 events.
[12:21:19.827] <TB2> INFO: 41600 events read in total (3412ms).
[12:21:19.828] <TB2> INFO: Test took 4281ms.
[12:21:19.832] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[12:21:20.108] <TB2> INFO: Expecting 41600 events.
[12:21:24.190] <TB2> INFO: 41600 events read in total (3490ms).
[12:21:24.191] <TB2> INFO: Test took 4358ms.
[12:21:24.194] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[12:21:24.470] <TB2> INFO: Expecting 41600 events.
[12:21:28.476] <TB2> INFO: 41600 events read in total (3414ms).
[12:21:28.477] <TB2> INFO: Test took 4283ms.
[12:21:28.481] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[12:21:28.772] <TB2> INFO: Expecting 41600 events.
[12:21:32.816] <TB2> INFO: 41600 events read in total (3453ms).
[12:21:32.817] <TB2> INFO: Test took 4336ms.
[12:21:32.823] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[12:21:33.116] <TB2> INFO: Expecting 41600 events.
[12:21:37.186] <TB2> INFO: 41600 events read in total (3479ms).
[12:21:37.187] <TB2> INFO: Test took 4364ms.
[12:21:37.191] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[12:21:37.515] <TB2> INFO: Expecting 41600 events.
[12:21:41.554] <TB2> INFO: 41600 events read in total (3448ms).
[12:21:41.555] <TB2> INFO: Test took 4364ms.
[12:21:41.968] <TB2> INFO: PixTestGainPedestal::measure() done
[12:22:17.648] <TB2> INFO: PixTestGainPedestal::fit() done
[12:22:17.648] <TB2> INFO: non-linearity mean: 0.931 0.963 0.983 0.968 0.952 0.978 0.917 0.923 0.994 1.040 0.969 0.933 0.981 0.914 0.918 0.927
[12:22:17.648] <TB2> INFO: non-linearity RMS: 0.089 0.021 0.004 0.016 0.045 0.006 0.127 0.085 0.167 0.170 0.030 0.085 0.187 0.093 0.116 0.083
[12:22:17.648] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr35_C0.dat
[12:22:17.661] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr35_C1.dat
[12:22:17.675] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr35_C2.dat
[12:22:17.689] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr35_C3.dat
[12:22:17.702] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr35_C4.dat
[12:22:17.716] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr35_C5.dat
[12:22:17.729] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr35_C6.dat
[12:22:17.744] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr35_C7.dat
[12:22:17.757] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr35_C8.dat
[12:22:17.771] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr35_C9.dat
[12:22:17.785] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr35_C10.dat
[12:22:17.798] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr35_C11.dat
[12:22:17.812] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr35_C12.dat
[12:22:17.826] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr35_C13.dat
[12:22:17.839] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr35_C14.dat
[12:22:17.853] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_10h38m_1477384707//001_Fulltest_p17//phCalibrationFitErr35_C15.dat
[12:22:17.867] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 164 seconds
[12:22:17.867] <TB2> INFO: Decoding statistics:
[12:22:17.867] <TB2> INFO: General information:
[12:22:17.867] <TB2> INFO: 16bit words read: 3306032
[12:22:17.867] <TB2> INFO: valid events total: 332800
[12:22:17.867] <TB2> INFO: empty events: 105
[12:22:17.867] <TB2> INFO: valid events with pixels: 332695
[12:22:17.867] <TB2> INFO: valid pixel hits: 654616
[12:22:17.867] <TB2> INFO: Event errors: 0
[12:22:17.867] <TB2> INFO: start marker: 0
[12:22:17.867] <TB2> INFO: stop marker: 0
[12:22:17.867] <TB2> INFO: overflow: 0
[12:22:17.867] <TB2> INFO: invalid 5bit words: 0
[12:22:17.867] <TB2> INFO: invalid XOR eye diagram: 0
[12:22:17.867] <TB2> INFO: frame (failed synchr.): 0
[12:22:17.867] <TB2> INFO: idle data (no TBM trl): 0
[12:22:17.867] <TB2> INFO: no data (only TBM hdr): 0
[12:22:17.867] <TB2> INFO: TBM errors: 0
[12:22:17.867] <TB2> INFO: flawed TBM headers: 0
[12:22:17.867] <TB2> INFO: flawed TBM trailers: 0
[12:22:17.867] <TB2> INFO: event ID mismatches: 0
[12:22:17.867] <TB2> INFO: ROC errors: 0
[12:22:17.867] <TB2> INFO: missing ROC header(s): 0
[12:22:17.867] <TB2> INFO: misplaced readback start: 0
[12:22:17.867] <TB2> INFO: Pixel decoding errors: 0
[12:22:17.867] <TB2> INFO: pixel data incomplete: 0
[12:22:17.867] <TB2> INFO: pixel address: 0
[12:22:17.867] <TB2> INFO: pulse height fill bit: 0
[12:22:17.867] <TB2> INFO: buffer corruption: 0
[12:22:17.886] <TB2> INFO: Decoding statistics:
[12:22:17.886] <TB2> INFO: General information:
[12:22:17.886] <TB2> INFO: 16bit words read: 3435450
[12:22:17.886] <TB2> INFO: valid events total: 353536
[12:22:17.886] <TB2> INFO: empty events: 18340
[12:22:17.886] <TB2> INFO: valid events with pixels: 335196
[12:22:17.886] <TB2> INFO: valid pixel hits: 657117
[12:22:17.886] <TB2> INFO: Event errors: 0
[12:22:17.886] <TB2> INFO: start marker: 0
[12:22:17.886] <TB2> INFO: stop marker: 0
[12:22:17.886] <TB2> INFO: overflow: 0
[12:22:17.886] <TB2> INFO: invalid 5bit words: 0
[12:22:17.886] <TB2> INFO: invalid XOR eye diagram: 0
[12:22:17.886] <TB2> INFO: frame (failed synchr.): 0
[12:22:17.886] <TB2> INFO: idle data (no TBM trl): 0
[12:22:17.886] <TB2> INFO: no data (only TBM hdr): 0
[12:22:17.886] <TB2> INFO: TBM errors: 0
[12:22:17.886] <TB2> INFO: flawed TBM headers: 0
[12:22:17.886] <TB2> INFO: flawed TBM trailers: 0
[12:22:17.886] <TB2> INFO: event ID mismatches: 0
[12:22:17.886] <TB2> INFO: ROC errors: 0
[12:22:17.886] <TB2> INFO: missing ROC header(s): 0
[12:22:17.886] <TB2> INFO: misplaced readback start: 0
[12:22:17.886] <TB2> INFO: Pixel decoding errors: 0
[12:22:17.886] <TB2> INFO: pixel data incomplete: 0
[12:22:17.886] <TB2> INFO: pixel address: 0
[12:22:17.886] <TB2> INFO: pulse height fill bit: 0
[12:22:17.886] <TB2> INFO: buffer corruption: 0
[12:22:17.886] <TB2> INFO: enter test to run
[12:22:17.886] <TB2> INFO: test: exit no parameter change
[12:22:18.010] <TB2> QUIET: Connection to board 149 closed.
[12:22:18.011] <TB2> INFO: pXar: this is the end, my friend
MoReWeb-v1.0.5-10-g7383767 on branch 20161012_zhud