[13:27:27.141] <TB2> INFO: *** Welcome to pxar ***
[13:27:27.141] <TB2> INFO: *** Today: 2016/10/25
[13:27:27.148] <TB2> INFO: *** Version: c8ba-dirty
[13:27:27.148] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C15.dat
[13:27:27.148] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//tbmParameters_C1b.dat
[13:27:27.149] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//defaultMaskFile.dat
[13:27:27.149] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters_C15.dat
[13:27:27.210] <TB2> INFO: clk: 4
[13:27:27.210] <TB2> INFO: ctr: 4
[13:27:27.210] <TB2> INFO: sda: 19
[13:27:27.210] <TB2> INFO: tin: 9
[13:27:27.210] <TB2> INFO: level: 15
[13:27:27.210] <TB2> INFO: triggerdelay: 0
[13:27:27.210] <TB2> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[13:27:27.210] <TB2> INFO: Log level: INFO
[13:27:27.219] <TB2> INFO: Found DTB DTB_WWXUD2
[13:27:27.226] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[13:27:27.228] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[13:27:27.230] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[13:27:28.731] <TB2> INFO: DUT info:
[13:27:28.731] <TB2> INFO: The DUT currently contains the following objects:
[13:27:28.731] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[13:27:28.731] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:27:28.731] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:27:28.731] <TB2> INFO: TBM Core alpha (2): 7 registers set
[13:27:28.731] <TB2> INFO: TBM Core beta (3): 7 registers set
[13:27:28.731] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[13:27:28.731] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[13:27:28.731] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[13:27:28.731] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[13:27:28.731] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[13:27:28.731] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[13:27:28.731] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[13:27:28.731] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[13:27:28.731] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[13:27:28.731] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[13:27:28.731] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[13:27:28.731] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[13:27:28.731] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[13:27:28.731] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[13:27:28.731] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[13:27:28.731] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[13:27:28.731] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[13:27:29.132] <TB2> INFO: enter 'restricted' command line mode
[13:27:29.132] <TB2> INFO: enter test to run
[13:27:29.132] <TB2> INFO: test: pretest no parameter change
[13:27:29.132] <TB2> INFO: running: pretest
[13:27:29.137] <TB2> INFO: ######################################################################
[13:27:29.137] <TB2> INFO: PixTestPretest::doTest()
[13:27:29.137] <TB2> INFO: ######################################################################
[13:27:29.139] <TB2> INFO: ----------------------------------------------------------------------
[13:27:29.139] <TB2> INFO: PixTestPretest::programROC()
[13:27:29.139] <TB2> INFO: ----------------------------------------------------------------------
[13:27:47.153] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[13:27:47.153] <TB2> INFO: IA differences per ROC: 16.9 16.9 19.3 19.3 17.7 19.3 18.5 18.5 16.9 18.5 18.5 19.3 21.7 17.7 19.3 19.3
[13:27:47.216] <TB2> INFO: ----------------------------------------------------------------------
[13:27:47.216] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[13:27:47.216] <TB2> INFO: ----------------------------------------------------------------------
[13:28:08.516] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 393.1 mA = 24.5688 mA/ROC
[13:28:08.516] <TB2> INFO: i(loss) [mA/ROC]: 21.7 20.9 20.1 20.1 20.9 20.1 20.9 21.7 19.3 21.7 20.9 19.3 19.3 21.7 21.7 19.3
[13:28:08.546] <TB2> INFO: ----------------------------------------------------------------------
[13:28:08.546] <TB2> INFO: PixTestPretest::findTiming()
[13:28:08.546] <TB2> INFO: ----------------------------------------------------------------------
[13:28:08.546] <TB2> INFO: PixTestCmd::init()

[13:28:40.510] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 6, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[13:28:40.510] <TB2> INFO: (success/tries = 100/100), width = 3
[13:28:42.013] <TB2> INFO: ----------------------------------------------------------------------
[13:28:42.013] <TB2> INFO: PixTestPretest::findWorkingPixel()
[13:28:42.013] <TB2> INFO: ----------------------------------------------------------------------
[13:28:42.108] <TB2> INFO: Expecting 231680 events.
[13:28:51.981] <TB2> INFO: 231680 events read in total (9282ms).
[13:28:51.990] <TB2> INFO: Test took 9972ms.
[13:28:52.237] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[13:28:52.270] <TB2> INFO: ----------------------------------------------------------------------
[13:28:52.270] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[13:28:52.270] <TB2> INFO: ----------------------------------------------------------------------
[13:28:52.365] <TB2> INFO: Expecting 231680 events.
[13:29:02.309] <TB2> INFO: 231680 events read in total (9352ms).
[13:29:02.319] <TB2> INFO: Test took 10044ms.
[13:29:02.589] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[13:29:02.589] <TB2> INFO: CalDel: 88 112 107 101 100 106 97 104 100 97 109 100 94 121 95 103
[13:29:02.589] <TB2> INFO: VthrComp: 51 51 51 51 52 51 51 51 51 51 51 51 51 54 51 51
[13:29:02.593] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C0.dat
[13:29:02.593] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C1.dat
[13:29:02.593] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C2.dat
[13:29:02.594] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C3.dat
[13:29:02.594] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C4.dat
[13:29:02.594] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C5.dat
[13:29:02.594] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C6.dat
[13:29:02.594] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C7.dat
[13:29:02.595] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C8.dat
[13:29:02.595] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C9.dat
[13:29:02.595] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C10.dat
[13:29:02.595] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C11.dat
[13:29:02.595] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C12.dat
[13:29:02.596] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C13.dat
[13:29:02.596] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C14.dat
[13:29:02.596] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters_C15.dat
[13:29:02.596] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//tbmParameters_C0a.dat
[13:29:02.596] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//tbmParameters_C0b.dat
[13:29:02.597] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//tbmParameters_C1a.dat
[13:29:02.597] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//tbmParameters_C1b.dat
[13:29:02.597] <TB2> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[13:29:02.668] <TB2> INFO: enter test to run
[13:29:02.668] <TB2> INFO: test: FullTest no parameter change
[13:29:02.668] <TB2> INFO: running: fulltest
[13:29:02.668] <TB2> INFO: ######################################################################
[13:29:02.668] <TB2> INFO: PixTestFullTest::doTest()
[13:29:02.668] <TB2> INFO: ######################################################################
[13:29:02.669] <TB2> INFO: ######################################################################
[13:29:02.669] <TB2> INFO: PixTestAlive::doTest()
[13:29:02.669] <TB2> INFO: ######################################################################
[13:29:02.671] <TB2> INFO: ----------------------------------------------------------------------
[13:29:02.671] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:29:02.671] <TB2> INFO: ----------------------------------------------------------------------
[13:29:02.911] <TB2> INFO: Expecting 41600 events.
[13:29:06.472] <TB2> INFO: 41600 events read in total (2969ms).
[13:29:06.472] <TB2> INFO: Test took 3800ms.
[13:29:06.700] <TB2> INFO: PixTestAlive::aliveTest() done
[13:29:06.700] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:29:06.701] <TB2> INFO: ----------------------------------------------------------------------
[13:29:06.701] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:29:06.701] <TB2> INFO: ----------------------------------------------------------------------
[13:29:06.939] <TB2> INFO: Expecting 41600 events.
[13:29:09.968] <TB2> INFO: 41600 events read in total (2437ms).
[13:29:09.968] <TB2> INFO: Test took 3266ms.
[13:29:09.969] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[13:29:10.208] <TB2> INFO: PixTestAlive::maskTest() done
[13:29:10.208] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:29:10.210] <TB2> INFO: ----------------------------------------------------------------------
[13:29:10.210] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:29:10.210] <TB2> INFO: ----------------------------------------------------------------------
[13:29:10.454] <TB2> INFO: Expecting 41600 events.
[13:29:14.011] <TB2> INFO: 41600 events read in total (2965ms).
[13:29:14.011] <TB2> INFO: Test took 3799ms.
[13:29:14.247] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[13:29:14.247] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:29:14.247] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[13:29:14.247] <TB2> INFO: Decoding statistics:
[13:29:14.247] <TB2> INFO: General information:
[13:29:14.247] <TB2> INFO: 16bit words read: 0
[13:29:14.247] <TB2> INFO: valid events total: 0
[13:29:14.247] <TB2> INFO: empty events: 0
[13:29:14.247] <TB2> INFO: valid events with pixels: 0
[13:29:14.247] <TB2> INFO: valid pixel hits: 0
[13:29:14.247] <TB2> INFO: Event errors: 0
[13:29:14.247] <TB2> INFO: start marker: 0
[13:29:14.248] <TB2> INFO: stop marker: 0
[13:29:14.248] <TB2> INFO: overflow: 0
[13:29:14.248] <TB2> INFO: invalid 5bit words: 0
[13:29:14.248] <TB2> INFO: invalid XOR eye diagram: 0
[13:29:14.248] <TB2> INFO: frame (failed synchr.): 0
[13:29:14.248] <TB2> INFO: idle data (no TBM trl): 0
[13:29:14.248] <TB2> INFO: no data (only TBM hdr): 0
[13:29:14.248] <TB2> INFO: TBM errors: 0
[13:29:14.248] <TB2> INFO: flawed TBM headers: 0
[13:29:14.248] <TB2> INFO: flawed TBM trailers: 0
[13:29:14.248] <TB2> INFO: event ID mismatches: 0
[13:29:14.248] <TB2> INFO: ROC errors: 0
[13:29:14.248] <TB2> INFO: missing ROC header(s): 0
[13:29:14.248] <TB2> INFO: misplaced readback start: 0
[13:29:14.248] <TB2> INFO: Pixel decoding errors: 0
[13:29:14.248] <TB2> INFO: pixel data incomplete: 0
[13:29:14.248] <TB2> INFO: pixel address: 0
[13:29:14.248] <TB2> INFO: pulse height fill bit: 0
[13:29:14.248] <TB2> INFO: buffer corruption: 0
[13:29:14.254] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C15.dat
[13:29:14.254] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr_C15.dat

[13:29:14.254] <TB2> INFO: ######################################################################
[13:29:14.254] <TB2> INFO: PixTestReadback::doTest()
[13:29:14.254] <TB2> INFO: ######################################################################
[13:29:14.254] <TB2> INFO: ----------------------------------------------------------------------
[13:29:14.254] <TB2> INFO: PixTestReadback::CalibrateVd()
[13:29:14.254] <TB2> INFO: ----------------------------------------------------------------------
[13:29:24.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C0.dat
[13:29:24.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C1.dat
[13:29:24.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C2.dat
[13:29:24.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C3.dat
[13:29:24.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C4.dat
[13:29:24.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C5.dat
[13:29:24.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C6.dat
[13:29:24.240] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C7.dat
[13:29:24.241] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C8.dat
[13:29:24.241] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C9.dat
[13:29:24.241] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C10.dat
[13:29:24.241] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C11.dat
[13:29:24.241] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C12.dat
[13:29:24.241] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C13.dat
[13:29:24.241] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C14.dat
[13:29:24.241] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C15.dat
[13:29:24.273] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:29:24.273] <TB2> INFO: ----------------------------------------------------------------------
[13:29:24.273] <TB2> INFO: PixTestReadback::CalibrateVa()
[13:29:24.273] <TB2> INFO: ----------------------------------------------------------------------
[13:29:34.211] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C0.dat
[13:29:34.211] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C1.dat
[13:29:34.212] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C2.dat
[13:29:34.212] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C3.dat
[13:29:34.212] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C4.dat
[13:29:34.212] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C5.dat
[13:29:34.212] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C6.dat
[13:29:34.212] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C7.dat
[13:29:34.212] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C8.dat
[13:29:34.212] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C9.dat
[13:29:34.212] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C10.dat
[13:29:34.212] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C11.dat
[13:29:34.212] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C12.dat
[13:29:34.212] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C13.dat
[13:29:34.212] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C14.dat
[13:29:34.212] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C15.dat
[13:29:34.242] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:29:34.242] <TB2> INFO: ----------------------------------------------------------------------
[13:29:34.242] <TB2> INFO: PixTestReadback::readbackVbg()
[13:29:34.242] <TB2> INFO: ----------------------------------------------------------------------
[13:29:41.914] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:29:41.914] <TB2> INFO: ----------------------------------------------------------------------
[13:29:41.914] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[13:29:41.914] <TB2> INFO: ----------------------------------------------------------------------
[13:29:41.914] <TB2> INFO: Vbg will be calibrated using Vd calibration
[13:29:41.914] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 152.5calibrated Vbg = 1.18548 :::*/*/*/*/
[13:29:41.914] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 152.9calibrated Vbg = 1.18265 :::*/*/*/*/
[13:29:41.914] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 162.4calibrated Vbg = 1.1807 :::*/*/*/*/
[13:29:41.914] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 149.2calibrated Vbg = 1.17675 :::*/*/*/*/
[13:29:41.914] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 160.6calibrated Vbg = 1.17821 :::*/*/*/*/
[13:29:41.914] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 154.7calibrated Vbg = 1.18269 :::*/*/*/*/
[13:29:41.914] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 166.1calibrated Vbg = 1.18694 :::*/*/*/*/
[13:29:41.914] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 158.2calibrated Vbg = 1.1842 :::*/*/*/*/
[13:29:41.914] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 151.3calibrated Vbg = 1.18006 :::*/*/*/*/
[13:29:41.914] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 161.8calibrated Vbg = 1.18013 :::*/*/*/*/
[13:29:41.914] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 163.3calibrated Vbg = 1.17478 :::*/*/*/*/
[13:29:41.914] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 156calibrated Vbg = 1.173 :::*/*/*/*/
[13:29:41.914] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 149.3calibrated Vbg = 1.17288 :::*/*/*/*/
[13:29:41.914] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 153.1calibrated Vbg = 1.17821 :::*/*/*/*/
[13:29:41.914] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 150.9calibrated Vbg = 1.17393 :::*/*/*/*/
[13:29:41.914] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 148.5calibrated Vbg = 1.18018 :::*/*/*/*/
[13:29:41.917] <TB2> INFO: ----------------------------------------------------------------------
[13:29:41.917] <TB2> INFO: PixTestReadback::CalibrateIa()
[13:29:41.917] <TB2> INFO: ----------------------------------------------------------------------
[13:32:22.714] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C0.dat
[13:32:22.714] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C1.dat
[13:32:22.715] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C2.dat
[13:32:22.715] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C3.dat
[13:32:22.715] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C4.dat
[13:32:22.715] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C5.dat
[13:32:22.715] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C6.dat
[13:32:22.715] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C7.dat
[13:32:22.715] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C8.dat
[13:32:22.715] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C9.dat
[13:32:22.715] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C10.dat
[13:32:22.715] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C11.dat
[13:32:22.715] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C12.dat
[13:32:22.715] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C13.dat
[13:32:22.715] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C14.dat
[13:32:22.716] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//readbackCal_C15.dat
[13:32:22.747] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:32:22.748] <TB2> INFO: PixTestReadback::doTest() done
[13:32:22.749] <TB2> INFO: Decoding statistics:
[13:32:22.749] <TB2> INFO: General information:
[13:32:22.749] <TB2> INFO: 16bit words read: 1536
[13:32:22.749] <TB2> INFO: valid events total: 256
[13:32:22.749] <TB2> INFO: empty events: 256
[13:32:22.749] <TB2> INFO: valid events with pixels: 0
[13:32:22.749] <TB2> INFO: valid pixel hits: 0
[13:32:22.749] <TB2> INFO: Event errors: 0
[13:32:22.749] <TB2> INFO: start marker: 0
[13:32:22.749] <TB2> INFO: stop marker: 0
[13:32:22.749] <TB2> INFO: overflow: 0
[13:32:22.749] <TB2> INFO: invalid 5bit words: 0
[13:32:22.749] <TB2> INFO: invalid XOR eye diagram: 0
[13:32:22.749] <TB2> INFO: frame (failed synchr.): 0
[13:32:22.749] <TB2> INFO: idle data (no TBM trl): 0
[13:32:22.749] <TB2> INFO: no data (only TBM hdr): 0
[13:32:22.749] <TB2> INFO: TBM errors: 0
[13:32:22.749] <TB2> INFO: flawed TBM headers: 0
[13:32:22.749] <TB2> INFO: flawed TBM trailers: 0
[13:32:22.749] <TB2> INFO: event ID mismatches: 0
[13:32:22.749] <TB2> INFO: ROC errors: 0
[13:32:22.749] <TB2> INFO: missing ROC header(s): 0
[13:32:22.749] <TB2> INFO: misplaced readback start: 0
[13:32:22.749] <TB2> INFO: Pixel decoding errors: 0
[13:32:22.749] <TB2> INFO: pixel data incomplete: 0
[13:32:22.749] <TB2> INFO: pixel address: 0
[13:32:22.749] <TB2> INFO: pulse height fill bit: 0
[13:32:22.749] <TB2> INFO: buffer corruption: 0
[13:32:22.800] <TB2> INFO: ######################################################################
[13:32:22.800] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[13:32:22.800] <TB2> INFO: ######################################################################
[13:32:22.802] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[13:32:22.816] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:32:22.816] <TB2> INFO: run 1 of 1
[13:32:23.053] <TB2> INFO: Expecting 3120000 events.
[13:32:53.913] <TB2> INFO: 666665 events read in total (30268ms).











[13:33:24.688] <TB2> INFO: 1337800 events read in total (61043ms).
[13:33:55.150] <TB2> INFO: 2008995 events read in total (91505ms).











[13:34:25.959] <TB2> INFO: 2680230 events read in total (122314ms).











[13:34:46.243] <TB2> INFO: 3120000 events read in total (142598ms).
[13:34:46.329] <TB2> INFO: Test took 143514ms.
[13:35:13.159] <TB2> INFO: PixTestBBMap::doTest() done with 1 decoding errors: , duration: 170 seconds
[13:35:13.159] <TB2> INFO: number of dead bumps (per ROC): 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 1
[13:35:13.159] <TB2> INFO: separation cut (per ROC): 107 117 109 112 125 117 132 123 106 113 108 119 110 110 129 104
[13:35:13.159] <TB2> INFO: Decoding statistics:
[13:35:13.159] <TB2> INFO: General information:
[13:35:13.159] <TB2> INFO: 16bit words read: 0
[13:35:13.159] <TB2> INFO: valid events total: 0
[13:35:13.159] <TB2> INFO: empty events: 0
[13:35:13.159] <TB2> INFO: valid events with pixels: 0
[13:35:13.159] <TB2> INFO: valid pixel hits: 0
[13:35:13.159] <TB2> INFO: Event errors: 0
[13:35:13.159] <TB2> INFO: start marker: 0
[13:35:13.159] <TB2> INFO: stop marker: 0
[13:35:13.159] <TB2> INFO: overflow: 0
[13:35:13.160] <TB2> INFO: invalid 5bit words: 0
[13:35:13.160] <TB2> INFO: invalid XOR eye diagram: 0
[13:35:13.160] <TB2> INFO: frame (failed synchr.): 0
[13:35:13.160] <TB2> INFO: idle data (no TBM trl): 0
[13:35:13.160] <TB2> INFO: no data (only TBM hdr): 0
[13:35:13.160] <TB2> INFO: TBM errors: 0
[13:35:13.160] <TB2> INFO: flawed TBM headers: 0
[13:35:13.160] <TB2> INFO: flawed TBM trailers: 0
[13:35:13.160] <TB2> INFO: event ID mismatches: 0
[13:35:13.160] <TB2> INFO: ROC errors: 0
[13:35:13.160] <TB2> INFO: missing ROC header(s): 0
[13:35:13.160] <TB2> INFO: misplaced readback start: 0
[13:35:13.160] <TB2> INFO: Pixel decoding errors: 0
[13:35:13.160] <TB2> INFO: pixel data incomplete: 0
[13:35:13.160] <TB2> INFO: pixel address: 0
[13:35:13.160] <TB2> INFO: pulse height fill bit: 0
[13:35:13.160] <TB2> INFO: buffer corruption: 0
[13:35:13.197] <TB2> INFO: ######################################################################
[13:35:13.197] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:35:13.197] <TB2> INFO: ######################################################################
[13:35:13.197] <TB2> INFO: ----------------------------------------------------------------------
[13:35:13.197] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:35:13.197] <TB2> INFO: ----------------------------------------------------------------------
[13:35:13.197] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[13:35:13.210] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[13:35:13.210] <TB2> INFO: run 1 of 1
[13:35:13.488] <TB2> INFO: Expecting 36608000 events.
[13:35:37.540] <TB2> INFO: 678850 events read in total (23461ms).
[13:36:00.545] <TB2> INFO: 1343650 events read in total (46466ms).
[13:36:23.664] <TB2> INFO: 2009700 events read in total (69585ms).
[13:36:46.450] <TB2> INFO: 2672550 events read in total (92371ms).
[13:37:09.377] <TB2> INFO: 3336100 events read in total (115298ms).
[13:37:32.398] <TB2> INFO: 3999300 events read in total (138319ms).
[13:37:55.344] <TB2> INFO: 4662450 events read in total (161265ms).
[13:38:18.476] <TB2> INFO: 5324550 events read in total (184397ms).
[13:38:41.694] <TB2> INFO: 5985600 events read in total (207615ms).
[13:39:04.709] <TB2> INFO: 6648050 events read in total (230630ms).
[13:39:27.540] <TB2> INFO: 7308550 events read in total (253461ms).
[13:39:50.611] <TB2> INFO: 7968550 events read in total (276532ms).
[13:40:13.322] <TB2> INFO: 8629350 events read in total (299243ms).
[13:40:36.252] <TB2> INFO: 9290600 events read in total (322173ms).
[13:40:59.238] <TB2> INFO: 9950850 events read in total (345159ms).
[13:41:22.252] <TB2> INFO: 10610500 events read in total (368173ms).
[13:41:45.432] <TB2> INFO: 11268950 events read in total (391353ms).
[13:42:08.645] <TB2> INFO: 11929400 events read in total (414566ms).
[13:42:31.788] <TB2> INFO: 12588100 events read in total (437709ms).
[13:42:55.010] <TB2> INFO: 13246850 events read in total (460931ms).
[13:43:18.224] <TB2> INFO: 13905200 events read in total (484145ms).
[13:43:41.162] <TB2> INFO: 14563450 events read in total (507083ms).
[13:44:04.123] <TB2> INFO: 15223050 events read in total (530044ms).
[13:44:27.288] <TB2> INFO: 15881900 events read in total (553209ms).
[13:44:50.396] <TB2> INFO: 16540500 events read in total (576317ms).
[13:45:13.531] <TB2> INFO: 17197600 events read in total (599452ms).
[13:45:36.532] <TB2> INFO: 17854550 events read in total (622453ms).
[13:45:59.502] <TB2> INFO: 18511900 events read in total (645423ms).
[13:46:22.437] <TB2> INFO: 19166600 events read in total (668358ms).
[13:46:45.353] <TB2> INFO: 19821100 events read in total (691274ms).
[13:47:08.507] <TB2> INFO: 20474700 events read in total (714428ms).
[13:47:31.563] <TB2> INFO: 21126650 events read in total (737484ms).
[13:47:54.853] <TB2> INFO: 21782300 events read in total (760774ms).
[13:48:17.915] <TB2> INFO: 22435550 events read in total (783836ms).
[13:48:41.136] <TB2> INFO: 23089300 events read in total (807057ms).
[13:49:04.280] <TB2> INFO: 23744150 events read in total (830201ms).
[13:49:27.141] <TB2> INFO: 24398600 events read in total (853062ms).
[13:49:50.187] <TB2> INFO: 25052250 events read in total (876108ms).
[13:50:13.473] <TB2> INFO: 25706800 events read in total (899394ms).
[13:50:36.879] <TB2> INFO: 26362300 events read in total (922800ms).
[13:51:00.178] <TB2> INFO: 27015600 events read in total (946099ms).
[13:51:23.549] <TB2> INFO: 27671300 events read in total (969470ms).
[13:51:46.509] <TB2> INFO: 28324300 events read in total (992430ms).
[13:52:09.408] <TB2> INFO: 28978850 events read in total (1015329ms).
[13:52:32.403] <TB2> INFO: 29632150 events read in total (1038324ms).
[13:52:55.284] <TB2> INFO: 30286900 events read in total (1061205ms).
[13:53:18.143] <TB2> INFO: 30937950 events read in total (1084064ms).
[13:53:41.100] <TB2> INFO: 31591050 events read in total (1107021ms).
[13:54:04.182] <TB2> INFO: 32245050 events read in total (1130103ms).
[13:54:27.210] <TB2> INFO: 32900250 events read in total (1153131ms).
[13:54:50.461] <TB2> INFO: 33554300 events read in total (1176382ms).
[13:55:13.490] <TB2> INFO: 34210150 events read in total (1199411ms).
[13:55:36.366] <TB2> INFO: 34865250 events read in total (1222287ms).
[13:55:59.154] <TB2> INFO: 35522000 events read in total (1245075ms).
[13:56:23.484] <TB2> INFO: 36183000 events read in total (1269405ms).
[13:56:38.905] <TB2> INFO: 36608000 events read in total (1284826ms).
[13:56:38.973] <TB2> INFO: Test took 1285762ms.
[13:56:39.421] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:56:41.179] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:56:43.118] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:56:45.710] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:56:47.821] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:56:49.408] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:56:51.118] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:56:52.837] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:56:54.471] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:56:55.986] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:56:57.766] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:56:59.412] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:57:00.915] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:57:02.533] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:57:04.026] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:57:05.910] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:57:07.562] <TB2> INFO: PixTestScurves::scurves() done
[13:57:07.562] <TB2> INFO: Vcal mean: 105.82 112.28 108.16 111.20 122.96 113.56 120.92 113.24 112.04 120.43 110.80 116.23 105.29 113.39 119.63 105.80
[13:57:07.562] <TB2> INFO: Vcal RMS: 5.06 5.17 4.56 4.92 5.93 5.13 6.27 4.86 4.90 6.22 5.11 5.87 4.88 5.82 5.75 5.12
[13:57:07.562] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1314 seconds
[13:57:07.562] <TB2> INFO: Decoding statistics:
[13:57:07.562] <TB2> INFO: General information:
[13:57:07.562] <TB2> INFO: 16bit words read: 0
[13:57:07.562] <TB2> INFO: valid events total: 0
[13:57:07.562] <TB2> INFO: empty events: 0
[13:57:07.562] <TB2> INFO: valid events with pixels: 0
[13:57:07.562] <TB2> INFO: valid pixel hits: 0
[13:57:07.562] <TB2> INFO: Event errors: 0
[13:57:07.562] <TB2> INFO: start marker: 0
[13:57:07.562] <TB2> INFO: stop marker: 0
[13:57:07.562] <TB2> INFO: overflow: 0
[13:57:07.562] <TB2> INFO: invalid 5bit words: 0
[13:57:07.562] <TB2> INFO: invalid XOR eye diagram: 0
[13:57:07.562] <TB2> INFO: frame (failed synchr.): 0
[13:57:07.562] <TB2> INFO: idle data (no TBM trl): 0
[13:57:07.562] <TB2> INFO: no data (only TBM hdr): 0
[13:57:07.563] <TB2> INFO: TBM errors: 0
[13:57:07.563] <TB2> INFO: flawed TBM headers: 0
[13:57:07.563] <TB2> INFO: flawed TBM trailers: 0
[13:57:07.563] <TB2> INFO: event ID mismatches: 0
[13:57:07.563] <TB2> INFO: ROC errors: 0
[13:57:07.563] <TB2> INFO: missing ROC header(s): 0
[13:57:07.563] <TB2> INFO: misplaced readback start: 0
[13:57:07.563] <TB2> INFO: Pixel decoding errors: 0
[13:57:07.563] <TB2> INFO: pixel data incomplete: 0
[13:57:07.563] <TB2> INFO: pixel address: 0
[13:57:07.563] <TB2> INFO: pulse height fill bit: 0
[13:57:07.563] <TB2> INFO: buffer corruption: 0
[13:57:07.652] <TB2> INFO: ######################################################################
[13:57:07.652] <TB2> INFO: PixTestTrim::doTest()
[13:57:07.652] <TB2> INFO: ######################################################################
[13:57:07.654] <TB2> INFO: ----------------------------------------------------------------------
[13:57:07.654] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[13:57:07.654] <TB2> INFO: ----------------------------------------------------------------------
[13:57:07.700] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:57:07.700] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:57:07.714] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:57:07.714] <TB2> INFO: run 1 of 1
[13:57:07.990] <TB2> INFO: Expecting 5025280 events.
[13:57:38.620] <TB2> INFO: 820256 events read in total (30024ms).
[13:58:08.693] <TB2> INFO: 1636504 events read in total (60098ms).
[13:58:38.862] <TB2> INFO: 2449664 events read in total (90266ms).
[13:59:08.890] <TB2> INFO: 3258816 events read in total (120294ms).
[13:59:39.528] <TB2> INFO: 4065936 events read in total (150932ms).
[14:00:09.465] <TB2> INFO: 4871768 events read in total (180869ms).
[14:00:15.441] <TB2> INFO: 5025280 events read in total (186845ms).
[14:00:15.498] <TB2> INFO: Test took 187784ms.
[14:00:32.019] <TB2> INFO: ROC 0 VthrComp = 116
[14:00:32.019] <TB2> INFO: ROC 1 VthrComp = 118
[14:00:32.019] <TB2> INFO: ROC 2 VthrComp = 118
[14:00:32.019] <TB2> INFO: ROC 3 VthrComp = 120
[14:00:32.020] <TB2> INFO: ROC 4 VthrComp = 131
[14:00:32.020] <TB2> INFO: ROC 5 VthrComp = 124
[14:00:32.020] <TB2> INFO: ROC 6 VthrComp = 131
[14:00:32.020] <TB2> INFO: ROC 7 VthrComp = 127
[14:00:32.020] <TB2> INFO: ROC 8 VthrComp = 114
[14:00:32.020] <TB2> INFO: ROC 9 VthrComp = 128
[14:00:32.020] <TB2> INFO: ROC 10 VthrComp = 118
[14:00:32.020] <TB2> INFO: ROC 11 VthrComp = 125
[14:00:32.020] <TB2> INFO: ROC 12 VthrComp = 113
[14:00:32.021] <TB2> INFO: ROC 13 VthrComp = 122
[14:00:32.021] <TB2> INFO: ROC 14 VthrComp = 135
[14:00:32.021] <TB2> INFO: ROC 15 VthrComp = 113
[14:00:32.261] <TB2> INFO: Expecting 41600 events.
[14:00:35.803] <TB2> INFO: 41600 events read in total (2951ms).
[14:00:35.804] <TB2> INFO: Test took 3781ms.
[14:00:35.813] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:00:35.813] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:00:35.824] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:00:35.824] <TB2> INFO: run 1 of 1
[14:00:36.102] <TB2> INFO: Expecting 5025280 events.
[14:01:02.489] <TB2> INFO: 589432 events read in total (25795ms).
[14:01:28.378] <TB2> INFO: 1177800 events read in total (51684ms).
[14:01:54.423] <TB2> INFO: 1766072 events read in total (77729ms).
[14:02:20.239] <TB2> INFO: 2353896 events read in total (103545ms).
[14:02:46.116] <TB2> INFO: 2939312 events read in total (129422ms).
[14:03:12.080] <TB2> INFO: 3523800 events read in total (155386ms).
[14:03:37.689] <TB2> INFO: 4107480 events read in total (180995ms).
[14:04:03.742] <TB2> INFO: 4690720 events read in total (207048ms).
[14:04:18.886] <TB2> INFO: 5025280 events read in total (222192ms).
[14:04:18.960] <TB2> INFO: Test took 223136ms.
[14:04:41.224] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 58.4756 for pixel 46/74 mean/min/max = 45.1801/31.7517/58.6084
[14:04:41.224] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 58.5603 for pixel 47/77 mean/min/max = 45.4156/32.2597/58.5714
[14:04:41.225] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 57.2696 for pixel 12/2 mean/min/max = 44.7732/32.0558/57.4906
[14:04:41.225] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 59.1047 for pixel 15/72 mean/min/max = 46.0045/32.6686/59.3404
[14:04:41.226] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 63.4092 for pixel 19/21 mean/min/max = 48.5689/33.6261/63.5117
[14:04:41.226] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 60.3257 for pixel 7/11 mean/min/max = 46.2683/32.1989/60.3376
[14:04:41.226] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 59.234 for pixel 1/57 mean/min/max = 45.2805/30.903/59.658
[14:04:41.227] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 56.8158 for pixel 50/8 mean/min/max = 44.1086/31.2031/57.0141
[14:04:41.227] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 59.7271 for pixel 15/31 mean/min/max = 46.2894/32.5764/60.0024
[14:04:41.228] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 60.6352 for pixel 8/13 mean/min/max = 45.7725/30.7905/60.7544
[14:04:41.228] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 60.0749 for pixel 15/6 mean/min/max = 45.8777/31.6227/60.1327
[14:04:41.229] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 60.0315 for pixel 1/15 mean/min/max = 45.0358/29.8915/60.1801
[14:04:41.229] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 57.002 for pixel 24/2 mean/min/max = 45.1263/33.0399/57.2127
[14:04:41.230] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 62.3401 for pixel 4/15 mean/min/max = 46.4781/30.5441/62.4121
[14:04:41.230] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 58.0071 for pixel 37/5 mean/min/max = 45.3453/32.6348/58.0558
[14:04:41.231] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 58.4412 for pixel 46/2 mean/min/max = 45.2838/31.98/58.5875
[14:04:41.231] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:04:41.320] <TB2> INFO: Expecting 411648 events.
[14:04:51.040] <TB2> INFO: 411648 events read in total (9128ms).
[14:04:51.051] <TB2> INFO: Expecting 411648 events.
[14:05:00.435] <TB2> INFO: 411648 events read in total (8981ms).
[14:05:00.446] <TB2> INFO: Expecting 411648 events.
[14:05:09.859] <TB2> INFO: 411648 events read in total (9009ms).
[14:05:09.873] <TB2> INFO: Expecting 411648 events.
[14:05:19.302] <TB2> INFO: 411648 events read in total (9025ms).
[14:05:19.325] <TB2> INFO: Expecting 411648 events.
[14:05:28.752] <TB2> INFO: 411648 events read in total (9024ms).
[14:05:28.779] <TB2> INFO: Expecting 411648 events.
[14:05:38.305] <TB2> INFO: 411648 events read in total (9123ms).
[14:05:38.333] <TB2> INFO: Expecting 411648 events.
[14:05:47.759] <TB2> INFO: 411648 events read in total (9022ms).
[14:05:47.785] <TB2> INFO: Expecting 411648 events.
[14:05:57.201] <TB2> INFO: 411648 events read in total (9013ms).
[14:05:57.229] <TB2> INFO: Expecting 411648 events.
[14:06:06.641] <TB2> INFO: 411648 events read in total (9009ms).
[14:06:06.679] <TB2> INFO: Expecting 411648 events.
[14:06:16.155] <TB2> INFO: 411648 events read in total (9073ms).
[14:06:16.191] <TB2> INFO: Expecting 411648 events.
[14:06:25.528] <TB2> INFO: 411648 events read in total (8934ms).
[14:06:25.575] <TB2> INFO: Expecting 411648 events.
[14:06:35.033] <TB2> INFO: 411648 events read in total (9055ms).
[14:06:35.071] <TB2> INFO: Expecting 411648 events.
[14:06:44.360] <TB2> INFO: 411648 events read in total (8885ms).
[14:06:44.415] <TB2> INFO: Expecting 411648 events.
[14:06:53.694] <TB2> INFO: 411648 events read in total (8876ms).
[14:06:53.739] <TB2> INFO: Expecting 411648 events.
[14:07:03.046] <TB2> INFO: 411648 events read in total (8904ms).
[14:07:03.106] <TB2> INFO: Expecting 411648 events.
[14:07:12.399] <TB2> INFO: 411648 events read in total (8890ms).
[14:07:12.459] <TB2> INFO: Test took 151228ms.
[14:07:13.448] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:07:13.462] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:07:13.462] <TB2> INFO: run 1 of 1
[14:07:13.747] <TB2> INFO: Expecting 5025280 events.
[14:07:40.229] <TB2> INFO: 585560 events read in total (25891ms).
[14:08:06.254] <TB2> INFO: 1169000 events read in total (51916ms).
[14:08:32.094] <TB2> INFO: 1752736 events read in total (77756ms).
[14:08:57.947] <TB2> INFO: 2335144 events read in total (103609ms).
[14:09:24.239] <TB2> INFO: 2917952 events read in total (129901ms).
[14:09:50.580] <TB2> INFO: 3501976 events read in total (156242ms).
[14:10:16.756] <TB2> INFO: 4085072 events read in total (182418ms).
[14:10:43.027] <TB2> INFO: 4669528 events read in total (208689ms).
[14:10:59.177] <TB2> INFO: 5025280 events read in total (224840ms).
[14:10:59.297] <TB2> INFO: Test took 225836ms.
[14:11:20.377] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 2.500000 .. 146.900961
[14:11:20.621] <TB2> INFO: Expecting 208000 events.
[14:11:30.456] <TB2> INFO: 208000 events read in total (9243ms).
[14:11:30.457] <TB2> INFO: Test took 10079ms.
[14:11:30.505] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 156 (-1/-1) hits flags = 528 (plus default)
[14:11:30.521] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:11:30.521] <TB2> INFO: run 1 of 1
[14:11:30.799] <TB2> INFO: Expecting 5158400 events.
[14:11:56.994] <TB2> INFO: 582504 events read in total (25604ms).
[14:12:23.336] <TB2> INFO: 1165008 events read in total (51946ms).
[14:12:49.084] <TB2> INFO: 1747112 events read in total (77694ms).
[14:13:14.853] <TB2> INFO: 2329616 events read in total (103463ms).
[14:13:40.431] <TB2> INFO: 2911760 events read in total (129041ms).
[14:14:06.239] <TB2> INFO: 3493512 events read in total (154849ms).
[14:14:31.999] <TB2> INFO: 4075176 events read in total (180609ms).
[14:14:58.280] <TB2> INFO: 4655528 events read in total (206890ms).
[14:15:20.882] <TB2> INFO: 5158400 events read in total (229492ms).
[14:15:21.116] <TB2> INFO: Test took 230595ms.
[14:15:46.352] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 28.119961 .. 45.394883
[14:15:46.612] <TB2> INFO: Expecting 208000 events.
[14:15:56.364] <TB2> INFO: 208000 events read in total (9160ms).
[14:15:56.364] <TB2> INFO: Test took 10010ms.
[14:15:56.412] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 18 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:15:56.424] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:15:56.425] <TB2> INFO: run 1 of 1
[14:15:56.703] <TB2> INFO: Expecting 1264640 events.
[14:16:27.305] <TB2> INFO: 653280 events read in total (30010ms).
[14:16:53.281] <TB2> INFO: 1264640 events read in total (55986ms).
[14:16:53.315] <TB2> INFO: Test took 56891ms.
[14:17:07.193] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 25.810755 .. 44.338289
[14:17:07.433] <TB2> INFO: Expecting 208000 events.
[14:17:17.348] <TB2> INFO: 208000 events read in total (9323ms).
[14:17:17.349] <TB2> INFO: Test took 10154ms.
[14:17:17.397] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 54 (-1/-1) hits flags = 528 (plus default)
[14:17:17.410] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:17:17.410] <TB2> INFO: run 1 of 1
[14:17:17.688] <TB2> INFO: Expecting 1331200 events.
[14:17:48.011] <TB2> INFO: 671008 events read in total (29731ms).
[14:18:16.064] <TB2> INFO: 1331200 events read in total (57784ms).
[14:18:16.095] <TB2> INFO: Test took 58685ms.
[14:18:31.175] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 24.192170 .. 42.424209
[14:18:31.414] <TB2> INFO: Expecting 208000 events.
[14:18:41.462] <TB2> INFO: 208000 events read in total (9457ms).
[14:18:41.462] <TB2> INFO: Test took 10286ms.
[14:18:41.533] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 52 (-1/-1) hits flags = 528 (plus default)
[14:18:41.547] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:18:41.547] <TB2> INFO: run 1 of 1
[14:18:41.826] <TB2> INFO: Expecting 1297920 events.
[14:19:11.843] <TB2> INFO: 684848 events read in total (29425ms).
[14:19:37.969] <TB2> INFO: 1297920 events read in total (55551ms).
[14:19:38.016] <TB2> INFO: Test took 56470ms.
[14:19:50.296] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:19:50.296] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:19:50.309] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:19:50.309] <TB2> INFO: run 1 of 1
[14:19:50.547] <TB2> INFO: Expecting 1364480 events.
[14:20:19.649] <TB2> INFO: 666704 events read in total (28510ms).
[14:20:47.906] <TB2> INFO: 1332648 events read in total (56767ms).
[14:20:49.622] <TB2> INFO: 1364480 events read in total (58484ms).
[14:20:49.649] <TB2> INFO: Test took 59340ms.
[14:21:03.199] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C0.dat
[14:21:03.199] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C1.dat
[14:21:03.199] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C2.dat
[14:21:03.199] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C3.dat
[14:21:03.199] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C4.dat
[14:21:03.199] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C5.dat
[14:21:03.199] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C6.dat
[14:21:03.199] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C7.dat
[14:21:03.199] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C8.dat
[14:21:03.200] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C9.dat
[14:21:03.200] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C10.dat
[14:21:03.200] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C11.dat
[14:21:03.200] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C12.dat
[14:21:03.200] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C13.dat
[14:21:03.200] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C14.dat
[14:21:03.200] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C15.dat
[14:21:03.200] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters35_C0.dat
[14:21:03.205] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters35_C1.dat
[14:21:03.210] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters35_C2.dat
[14:21:03.215] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters35_C3.dat
[14:21:03.220] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters35_C4.dat
[14:21:03.225] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters35_C5.dat
[14:21:03.230] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters35_C6.dat
[14:21:03.234] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters35_C7.dat
[14:21:03.239] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters35_C8.dat
[14:21:03.244] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters35_C9.dat
[14:21:03.248] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters35_C10.dat
[14:21:03.253] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters35_C11.dat
[14:21:03.258] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters35_C12.dat
[14:21:03.263] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters35_C13.dat
[14:21:03.267] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters35_C14.dat
[14:21:03.272] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//trimParameters35_C15.dat
[14:21:03.277] <TB2> INFO: PixTestTrim::trimTest() done
[14:21:03.277] <TB2> INFO: vtrim: 143 135 117 132 168 151 123 143 119 146 127 151 122 143 136 130
[14:21:03.277] <TB2> INFO: vthrcomp: 116 118 118 120 131 124 131 127 114 128 118 125 113 122 135 113
[14:21:03.277] <TB2> INFO: vcal mean: 34.98 34.95 34.95 34.96 35.00 35.00 34.96 34.89 34.90 35.01 34.95 34.86 34.97 34.94 34.98 34.95
[14:21:03.277] <TB2> INFO: vcal RMS: 0.99 0.98 0.94 1.01 1.10 0.97 1.06 1.03 1.06 1.13 1.01 1.18 0.94 1.09 1.00 1.02
[14:21:03.277] <TB2> INFO: bits mean: 9.92 9.58 9.57 9.45 9.46 9.53 9.51 10.21 9.37 9.74 9.57 10.35 9.56 9.55 9.28 9.91
[14:21:03.277] <TB2> INFO: bits RMS: 2.54 2.64 2.73 2.60 2.32 2.65 2.89 2.56 2.69 2.67 2.73 2.57 2.57 2.79 2.69 2.53
[14:21:03.285] <TB2> INFO: ----------------------------------------------------------------------
[14:21:03.285] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:21:03.285] <TB2> INFO: ----------------------------------------------------------------------
[14:21:03.288] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:21:03.301] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:21:03.301] <TB2> INFO: run 1 of 1
[14:21:03.537] <TB2> INFO: Expecting 4160000 events.
[14:21:36.306] <TB2> INFO: 746625 events read in total (32177ms).
[14:22:08.389] <TB2> INFO: 1487220 events read in total (64260ms).
[14:22:40.438] <TB2> INFO: 2223825 events read in total (96309ms).
[14:23:12.511] <TB2> INFO: 2956890 events read in total (128382ms).
[14:23:45.578] <TB2> INFO: 3689150 events read in total (161449ms).
[14:24:06.166] <TB2> INFO: 4160000 events read in total (182037ms).
[14:24:06.256] <TB2> INFO: Test took 182955ms.
[14:24:32.869] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 194 (-1/-1) hits flags = 528 (plus default)
[14:24:32.882] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:24:32.882] <TB2> INFO: run 1 of 1
[14:24:33.119] <TB2> INFO: Expecting 4056000 events.
[14:25:05.358] <TB2> INFO: 728395 events read in total (31647ms).
[14:25:37.034] <TB2> INFO: 1451395 events read in total (63323ms).
[14:26:08.735] <TB2> INFO: 2170260 events read in total (95024ms).
[14:26:40.489] <TB2> INFO: 2886000 events read in total (126778ms).
[14:27:12.635] <TB2> INFO: 3600285 events read in total (158924ms).
[14:27:32.399] <TB2> INFO: 4056000 events read in total (178688ms).
[14:27:32.492] <TB2> INFO: Test took 179610ms.
[14:28:03.861] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 182 (-1/-1) hits flags = 528 (plus default)
[14:28:03.874] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:28:03.874] <TB2> INFO: run 1 of 1
[14:28:04.113] <TB2> INFO: Expecting 3806400 events.
[14:28:36.531] <TB2> INFO: 746430 events read in total (31827ms).
[14:29:08.218] <TB2> INFO: 1486450 events read in total (63514ms).
[14:29:39.938] <TB2> INFO: 2221715 events read in total (95234ms).
[14:30:11.632] <TB2> INFO: 2953570 events read in total (126928ms).
[14:30:43.494] <TB2> INFO: 3685930 events read in total (158790ms).
[14:30:49.098] <TB2> INFO: 3806400 events read in total (164394ms).
[14:30:49.205] <TB2> INFO: Test took 165330ms.
[14:31:13.902] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 183 (-1/-1) hits flags = 528 (plus default)
[14:31:13.915] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:31:13.915] <TB2> INFO: run 1 of 1
[14:31:14.158] <TB2> INFO: Expecting 3827200 events.
[14:31:46.498] <TB2> INFO: 745030 events read in total (31749ms).
[14:32:18.078] <TB2> INFO: 1483760 events read in total (63329ms).
[14:32:49.829] <TB2> INFO: 2217825 events read in total (95080ms).
[14:33:21.247] <TB2> INFO: 2948425 events read in total (126498ms).
[14:33:53.069] <TB2> INFO: 3679165 events read in total (158320ms).
[14:33:59.878] <TB2> INFO: 3827200 events read in total (165129ms).
[14:33:59.933] <TB2> INFO: Test took 166019ms.
[14:34:27.249] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 182 (-1/-1) hits flags = 528 (plus default)
[14:34:27.262] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:34:27.262] <TB2> INFO: run 1 of 1
[14:34:27.500] <TB2> INFO: Expecting 3806400 events.
[14:35:00.889] <TB2> INFO: 746610 events read in total (32798ms).
[14:35:33.417] <TB2> INFO: 1487025 events read in total (65326ms).
[14:36:05.022] <TB2> INFO: 2222890 events read in total (96931ms).
[14:36:37.059] <TB2> INFO: 2955335 events read in total (128968ms).
[14:37:09.184] <TB2> INFO: 3688100 events read in total (161093ms).
[14:37:14.562] <TB2> INFO: 3806400 events read in total (166471ms).
[14:37:14.624] <TB2> INFO: Test took 167362ms.
[14:37:40.341] <TB2> INFO: PixTestTrim::trimBitTest() done
[14:37:40.343] <TB2> INFO: PixTestTrim::doTest() done, duration: 2432 seconds
[14:37:40.343] <TB2> INFO: Decoding statistics:
[14:37:40.343] <TB2> INFO: General information:
[14:37:40.343] <TB2> INFO: 16bit words read: 0
[14:37:40.343] <TB2> INFO: valid events total: 0
[14:37:40.343] <TB2> INFO: empty events: 0
[14:37:40.343] <TB2> INFO: valid events with pixels: 0
[14:37:40.343] <TB2> INFO: valid pixel hits: 0
[14:37:40.343] <TB2> INFO: Event errors: 0
[14:37:40.343] <TB2> INFO: start marker: 0
[14:37:40.343] <TB2> INFO: stop marker: 0
[14:37:40.343] <TB2> INFO: overflow: 0
[14:37:40.343] <TB2> INFO: invalid 5bit words: 0
[14:37:40.343] <TB2> INFO: invalid XOR eye diagram: 0
[14:37:40.343] <TB2> INFO: frame (failed synchr.): 0
[14:37:40.343] <TB2> INFO: idle data (no TBM trl): 0
[14:37:40.343] <TB2> INFO: no data (only TBM hdr): 0
[14:37:40.343] <TB2> INFO: TBM errors: 0
[14:37:40.343] <TB2> INFO: flawed TBM headers: 0
[14:37:40.343] <TB2> INFO: flawed TBM trailers: 0
[14:37:40.343] <TB2> INFO: event ID mismatches: 0
[14:37:40.343] <TB2> INFO: ROC errors: 0
[14:37:40.343] <TB2> INFO: missing ROC header(s): 0
[14:37:40.343] <TB2> INFO: misplaced readback start: 0
[14:37:40.343] <TB2> INFO: Pixel decoding errors: 0
[14:37:40.343] <TB2> INFO: pixel data incomplete: 0
[14:37:40.343] <TB2> INFO: pixel address: 0
[14:37:40.343] <TB2> INFO: pulse height fill bit: 0
[14:37:40.343] <TB2> INFO: buffer corruption: 0
[14:37:41.082] <TB2> INFO: ######################################################################
[14:37:41.082] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[14:37:41.082] <TB2> INFO: ######################################################################
[14:37:41.364] <TB2> INFO: Expecting 41600 events.
[14:37:45.078] <TB2> INFO: 41600 events read in total (3122ms).
[14:37:45.080] <TB2> INFO: Test took 3996ms.
[14:37:45.549] <TB2> INFO: Expecting 41600 events.
[14:37:49.224] <TB2> INFO: 41600 events read in total (3083ms).
[14:37:49.225] <TB2> INFO: Test took 3939ms.
[14:37:49.517] <TB2> INFO: Expecting 41600 events.
[14:37:53.058] <TB2> INFO: 41600 events read in total (2950ms).
[14:37:53.059] <TB2> INFO: Test took 3807ms.
[14:37:53.348] <TB2> INFO: Expecting 41600 events.
[14:37:56.915] <TB2> INFO: 41600 events read in total (2975ms).
[14:37:56.916] <TB2> INFO: Test took 3833ms.
[14:37:57.208] <TB2> INFO: Expecting 41600 events.
[14:38:00.688] <TB2> INFO: 41600 events read in total (2888ms).
[14:38:00.689] <TB2> INFO: Test took 3746ms.
[14:38:00.977] <TB2> INFO: Expecting 41600 events.
[14:38:04.482] <TB2> INFO: 41600 events read in total (2913ms).
[14:38:04.483] <TB2> INFO: Test took 3770ms.
[14:38:04.772] <TB2> INFO: Expecting 41600 events.
[14:38:08.299] <TB2> INFO: 41600 events read in total (2935ms).
[14:38:08.300] <TB2> INFO: Test took 3793ms.
[14:38:08.589] <TB2> INFO: Expecting 41600 events.
[14:38:12.172] <TB2> INFO: 41600 events read in total (2991ms).
[14:38:12.173] <TB2> INFO: Test took 3849ms.
[14:38:12.463] <TB2> INFO: Expecting 41600 events.
[14:38:16.054] <TB2> INFO: 41600 events read in total (2999ms).
[14:38:16.055] <TB2> INFO: Test took 3857ms.
[14:38:16.347] <TB2> INFO: Expecting 41600 events.
[14:38:19.999] <TB2> INFO: 41600 events read in total (3060ms).
[14:38:19.000] <TB2> INFO: Test took 3918ms.
[14:38:20.290] <TB2> INFO: Expecting 41600 events.
[14:38:23.932] <TB2> INFO: 41600 events read in total (3050ms).
[14:38:23.932] <TB2> INFO: Test took 3908ms.
[14:38:24.223] <TB2> INFO: Expecting 41600 events.
[14:38:27.847] <TB2> INFO: 41600 events read in total (3032ms).
[14:38:27.848] <TB2> INFO: Test took 3890ms.
[14:38:28.137] <TB2> INFO: Expecting 41600 events.
[14:38:31.661] <TB2> INFO: 41600 events read in total (2932ms).
[14:38:31.662] <TB2> INFO: Test took 3790ms.
[14:38:31.952] <TB2> INFO: Expecting 41600 events.
[14:38:35.525] <TB2> INFO: 41600 events read in total (2982ms).
[14:38:35.526] <TB2> INFO: Test took 3840ms.
[14:38:35.816] <TB2> INFO: Expecting 41600 events.
[14:38:39.383] <TB2> INFO: 41600 events read in total (2975ms).
[14:38:39.383] <TB2> INFO: Test took 3833ms.
[14:38:39.672] <TB2> INFO: Expecting 41600 events.
[14:38:43.241] <TB2> INFO: 41600 events read in total (2977ms).
[14:38:43.242] <TB2> INFO: Test took 3835ms.
[14:38:43.532] <TB2> INFO: Expecting 41600 events.
[14:38:47.164] <TB2> INFO: 41600 events read in total (3041ms).
[14:38:47.165] <TB2> INFO: Test took 3899ms.
[14:38:47.476] <TB2> INFO: Expecting 41600 events.
[14:38:51.123] <TB2> INFO: 41600 events read in total (3055ms).
[14:38:51.124] <TB2> INFO: Test took 3931ms.
[14:38:51.414] <TB2> INFO: Expecting 41600 events.
[14:38:54.945] <TB2> INFO: 41600 events read in total (2939ms).
[14:38:54.946] <TB2> INFO: Test took 3798ms.
[14:38:55.239] <TB2> INFO: Expecting 41600 events.
[14:38:58.754] <TB2> INFO: 41600 events read in total (2925ms).
[14:38:58.755] <TB2> INFO: Test took 3782ms.
[14:38:59.044] <TB2> INFO: Expecting 41600 events.
[14:39:02.681] <TB2> INFO: 41600 events read in total (3045ms).
[14:39:02.681] <TB2> INFO: Test took 3902ms.
[14:39:02.972] <TB2> INFO: Expecting 41600 events.
[14:39:06.619] <TB2> INFO: 41600 events read in total (3055ms).
[14:39:06.620] <TB2> INFO: Test took 3914ms.
[14:39:06.909] <TB2> INFO: Expecting 41600 events.
[14:39:10.423] <TB2> INFO: 41600 events read in total (2922ms).
[14:39:10.424] <TB2> INFO: Test took 3780ms.
[14:39:10.714] <TB2> INFO: Expecting 41600 events.
[14:39:14.366] <TB2> INFO: 41600 events read in total (3061ms).
[14:39:14.367] <TB2> INFO: Test took 3919ms.
[14:39:14.686] <TB2> INFO: Expecting 41600 events.
[14:39:18.330] <TB2> INFO: 41600 events read in total (3052ms).
[14:39:18.331] <TB2> INFO: Test took 3940ms.
[14:39:18.621] <TB2> INFO: Expecting 41600 events.
[14:39:22.263] <TB2> INFO: 41600 events read in total (3050ms).
[14:39:22.263] <TB2> INFO: Test took 3908ms.
[14:39:22.554] <TB2> INFO: Expecting 41600 events.
[14:39:26.085] <TB2> INFO: 41600 events read in total (2940ms).
[14:39:26.085] <TB2> INFO: Test took 3797ms.
[14:39:26.377] <TB2> INFO: Expecting 41600 events.
[14:39:30.019] <TB2> INFO: 41600 events read in total (3050ms).
[14:39:30.020] <TB2> INFO: Test took 3908ms.
[14:39:30.310] <TB2> INFO: Expecting 41600 events.
[14:39:33.853] <TB2> INFO: 41600 events read in total (2952ms).
[14:39:33.854] <TB2> INFO: Test took 3810ms.
[14:39:34.145] <TB2> INFO: Expecting 41600 events.
[14:39:37.680] <TB2> INFO: 41600 events read in total (2943ms).
[14:39:37.680] <TB2> INFO: Test took 3799ms.
[14:39:37.971] <TB2> INFO: Expecting 2560 events.
[14:39:38.863] <TB2> INFO: 2560 events read in total (300ms).
[14:39:38.863] <TB2> INFO: Test took 1169ms.
[14:39:39.171] <TB2> INFO: Expecting 2560 events.
[14:39:40.060] <TB2> INFO: 2560 events read in total (298ms).
[14:39:40.060] <TB2> INFO: Test took 1197ms.
[14:39:40.368] <TB2> INFO: Expecting 2560 events.
[14:39:41.254] <TB2> INFO: 2560 events read in total (294ms).
[14:39:41.254] <TB2> INFO: Test took 1193ms.
[14:39:41.562] <TB2> INFO: Expecting 2560 events.
[14:39:42.460] <TB2> INFO: 2560 events read in total (306ms).
[14:39:42.461] <TB2> INFO: Test took 1206ms.
[14:39:42.767] <TB2> INFO: Expecting 2560 events.
[14:39:43.654] <TB2> INFO: 2560 events read in total (295ms).
[14:39:43.655] <TB2> INFO: Test took 1191ms.
[14:39:43.964] <TB2> INFO: Expecting 2560 events.
[14:39:44.850] <TB2> INFO: 2560 events read in total (295ms).
[14:39:44.850] <TB2> INFO: Test took 1193ms.
[14:39:45.158] <TB2> INFO: Expecting 2560 events.
[14:39:46.048] <TB2> INFO: 2560 events read in total (298ms).
[14:39:46.048] <TB2> INFO: Test took 1197ms.
[14:39:46.356] <TB2> INFO: Expecting 2560 events.
[14:39:47.238] <TB2> INFO: 2560 events read in total (290ms).
[14:39:47.238] <TB2> INFO: Test took 1189ms.
[14:39:47.545] <TB2> INFO: Expecting 2560 events.
[14:39:48.433] <TB2> INFO: 2560 events read in total (296ms).
[14:39:48.433] <TB2> INFO: Test took 1195ms.
[14:39:48.741] <TB2> INFO: Expecting 2560 events.
[14:39:49.634] <TB2> INFO: 2560 events read in total (301ms).
[14:39:49.634] <TB2> INFO: Test took 1200ms.
[14:39:49.941] <TB2> INFO: Expecting 2560 events.
[14:39:50.820] <TB2> INFO: 2560 events read in total (288ms).
[14:39:50.820] <TB2> INFO: Test took 1185ms.
[14:39:51.128] <TB2> INFO: Expecting 2560 events.
[14:39:52.012] <TB2> INFO: 2560 events read in total (292ms).
[14:39:52.012] <TB2> INFO: Test took 1192ms.
[14:39:52.321] <TB2> INFO: Expecting 2560 events.
[14:39:53.208] <TB2> INFO: 2560 events read in total (295ms).
[14:39:53.208] <TB2> INFO: Test took 1195ms.
[14:39:53.516] <TB2> INFO: Expecting 2560 events.
[14:39:54.407] <TB2> INFO: 2560 events read in total (299ms).
[14:39:54.408] <TB2> INFO: Test took 1199ms.
[14:39:54.716] <TB2> INFO: Expecting 2560 events.
[14:39:55.605] <TB2> INFO: 2560 events read in total (298ms).
[14:39:55.605] <TB2> INFO: Test took 1197ms.
[14:39:55.914] <TB2> INFO: Expecting 2560 events.
[14:39:56.805] <TB2> INFO: 2560 events read in total (299ms).
[14:39:56.805] <TB2> INFO: Test took 1200ms.
[14:39:56.808] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:39:57.114] <TB2> INFO: Expecting 655360 events.
[14:40:12.014] <TB2> INFO: 655360 events read in total (14308ms).
[14:40:12.026] <TB2> INFO: Expecting 655360 events.
[14:40:26.449] <TB2> INFO: 655360 events read in total (14020ms).
[14:40:26.466] <TB2> INFO: Expecting 655360 events.
[14:40:40.988] <TB2> INFO: 655360 events read in total (14119ms).
[14:40:41.011] <TB2> INFO: Expecting 655360 events.
[14:40:55.525] <TB2> INFO: 655360 events read in total (14111ms).
[14:40:55.552] <TB2> INFO: Expecting 655360 events.
[14:41:10.145] <TB2> INFO: 655360 events read in total (14190ms).
[14:41:10.179] <TB2> INFO: Expecting 655360 events.
[14:41:24.838] <TB2> INFO: 655360 events read in total (14256ms).
[14:41:24.888] <TB2> INFO: Expecting 655360 events.
[14:41:39.446] <TB2> INFO: 655360 events read in total (14155ms).
[14:41:39.488] <TB2> INFO: Expecting 655360 events.
[14:41:53.923] <TB2> INFO: 655360 events read in total (14032ms).
[14:41:53.981] <TB2> INFO: Expecting 655360 events.
[14:42:08.446] <TB2> INFO: 655360 events read in total (14062ms).
[14:42:08.499] <TB2> INFO: Expecting 655360 events.
[14:42:22.991] <TB2> INFO: 655360 events read in total (14089ms).
[14:42:23.057] <TB2> INFO: Expecting 655360 events.
[14:42:37.608] <TB2> INFO: 655360 events read in total (14148ms).
[14:42:37.689] <TB2> INFO: Expecting 655360 events.
[14:42:52.351] <TB2> INFO: 655360 events read in total (14259ms).
[14:42:52.433] <TB2> INFO: Expecting 655360 events.
[14:43:07.007] <TB2> INFO: 655360 events read in total (14171ms).
[14:43:07.138] <TB2> INFO: Expecting 655360 events.
[14:43:21.657] <TB2> INFO: 655360 events read in total (14116ms).
[14:43:21.792] <TB2> INFO: Expecting 655360 events.
[14:43:36.357] <TB2> INFO: 655360 events read in total (14162ms).
[14:43:36.456] <TB2> INFO: Expecting 655360 events.
[14:43:50.842] <TB2> INFO: 655360 events read in total (13983ms).
[14:43:50.950] <TB2> INFO: Test took 234142ms.
[14:43:51.043] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:43:51.303] <TB2> INFO: Expecting 655360 events.
[14:44:05.852] <TB2> INFO: 655360 events read in total (13958ms).
[14:44:05.867] <TB2> INFO: Expecting 655360 events.
[14:44:20.290] <TB2> INFO: 655360 events read in total (14020ms).
[14:44:20.308] <TB2> INFO: Expecting 655360 events.
[14:44:34.750] <TB2> INFO: 655360 events read in total (14039ms).
[14:44:34.777] <TB2> INFO: Expecting 655360 events.
[14:44:49.042] <TB2> INFO: 655360 events read in total (13862ms).
[14:44:49.069] <TB2> INFO: Expecting 655360 events.
[14:45:03.585] <TB2> INFO: 655360 events read in total (14113ms).
[14:45:03.619] <TB2> INFO: Expecting 655360 events.
[14:45:18.166] <TB2> INFO: 655360 events read in total (14144ms).
[14:45:18.214] <TB2> INFO: Expecting 655360 events.
[14:45:32.606] <TB2> INFO: 655360 events read in total (13989ms).
[14:45:32.647] <TB2> INFO: Expecting 655360 events.
[14:45:47.016] <TB2> INFO: 655360 events read in total (13966ms).
[14:45:47.074] <TB2> INFO: Expecting 655360 events.
[14:46:01.462] <TB2> INFO: 655360 events read in total (13985ms).
[14:46:01.516] <TB2> INFO: Expecting 655360 events.
[14:46:16.156] <TB2> INFO: 655360 events read in total (14237ms).
[14:46:16.302] <TB2> INFO: Expecting 655360 events.
[14:46:30.964] <TB2> INFO: 655360 events read in total (14259ms).
[14:46:31.031] <TB2> INFO: Expecting 655360 events.
[14:46:45.827] <TB2> INFO: 655360 events read in total (14393ms).
[14:46:45.910] <TB2> INFO: Expecting 655360 events.
[14:47:00.764] <TB2> INFO: 655360 events read in total (14451ms).
[14:47:00.900] <TB2> INFO: Expecting 655360 events.
[14:47:15.385] <TB2> INFO: 655360 events read in total (14082ms).
[14:47:15.536] <TB2> INFO: Expecting 655360 events.
[14:47:30.230] <TB2> INFO: 655360 events read in total (14291ms).
[14:47:30.400] <TB2> INFO: Expecting 655360 events.
[14:47:45.088] <TB2> INFO: 655360 events read in total (14285ms).
[14:47:45.223] <TB2> INFO: Test took 234180ms.
[14:47:45.386] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:47:45.392] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:47:45.398] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:47:45.403] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:47:45.409] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:47:45.415] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:47:45.420] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:47:45.426] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:47:45.432] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:47:45.437] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:47:45.444] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:47:45.451] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:47:45.457] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:47:45.463] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:47:45.469] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:47:45.474] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:47:45.481] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:47:45.488] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:47:45.495] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:47:45.501] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:47:45.509] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:47:45.516] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:47:45.522] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:47:45.529] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:47:45.535] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:47:45.541] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:47:45.548] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:47:45.554] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:47:45.560] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:47:45.567] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:47:45.574] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:47:45.611] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C0.dat
[14:47:45.611] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C1.dat
[14:47:45.611] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C2.dat
[14:47:45.611] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C3.dat
[14:47:45.612] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C4.dat
[14:47:45.612] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C5.dat
[14:47:45.612] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C6.dat
[14:47:45.612] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C7.dat
[14:47:45.612] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C8.dat
[14:47:45.612] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C9.dat
[14:47:45.612] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C10.dat
[14:47:45.612] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C11.dat
[14:47:45.612] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C12.dat
[14:47:45.612] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C13.dat
[14:47:45.612] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C14.dat
[14:47:45.613] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//dacParameters35_C15.dat
[14:47:45.857] <TB2> INFO: Expecting 41600 events.
[14:47:49.014] <TB2> INFO: 41600 events read in total (2565ms).
[14:47:49.015] <TB2> INFO: Test took 3399ms.
[14:47:49.485] <TB2> INFO: Expecting 41600 events.
[14:47:52.565] <TB2> INFO: 41600 events read in total (2488ms).
[14:47:52.566] <TB2> INFO: Test took 3337ms.
[14:47:53.061] <TB2> INFO: Expecting 41600 events.
[14:47:56.241] <TB2> INFO: 41600 events read in total (2588ms).
[14:47:56.241] <TB2> INFO: Test took 3464ms.
[14:47:56.459] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:47:56.549] <TB2> INFO: Expecting 2560 events.
[14:47:57.440] <TB2> INFO: 2560 events read in total (299ms).
[14:47:57.441] <TB2> INFO: Test took 982ms.
[14:47:57.444] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:47:57.749] <TB2> INFO: Expecting 2560 events.
[14:47:58.636] <TB2> INFO: 2560 events read in total (295ms).
[14:47:58.636] <TB2> INFO: Test took 1192ms.
[14:47:58.640] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:47:58.945] <TB2> INFO: Expecting 2560 events.
[14:47:59.838] <TB2> INFO: 2560 events read in total (301ms).
[14:47:59.839] <TB2> INFO: Test took 1199ms.
[14:47:59.842] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:00.147] <TB2> INFO: Expecting 2560 events.
[14:48:01.040] <TB2> INFO: 2560 events read in total (301ms).
[14:48:01.041] <TB2> INFO: Test took 1200ms.
[14:48:01.044] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:01.348] <TB2> INFO: Expecting 2560 events.
[14:48:02.234] <TB2> INFO: 2560 events read in total (294ms).
[14:48:02.234] <TB2> INFO: Test took 1190ms.
[14:48:02.237] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:02.542] <TB2> INFO: Expecting 2560 events.
[14:48:03.435] <TB2> INFO: 2560 events read in total (301ms).
[14:48:03.436] <TB2> INFO: Test took 1199ms.
[14:48:03.439] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:03.745] <TB2> INFO: Expecting 2560 events.
[14:48:04.634] <TB2> INFO: 2560 events read in total (297ms).
[14:48:04.635] <TB2> INFO: Test took 1196ms.
[14:48:04.636] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:04.944] <TB2> INFO: Expecting 2560 events.
[14:48:05.829] <TB2> INFO: 2560 events read in total (293ms).
[14:48:05.829] <TB2> INFO: Test took 1193ms.
[14:48:05.834] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:06.137] <TB2> INFO: Expecting 2560 events.
[14:48:07.018] <TB2> INFO: 2560 events read in total (289ms).
[14:48:07.018] <TB2> INFO: Test took 1184ms.
[14:48:07.020] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:07.328] <TB2> INFO: Expecting 2560 events.
[14:48:08.212] <TB2> INFO: 2560 events read in total (292ms).
[14:48:08.212] <TB2> INFO: Test took 1192ms.
[14:48:08.217] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:08.520] <TB2> INFO: Expecting 2560 events.
[14:48:09.412] <TB2> INFO: 2560 events read in total (300ms).
[14:48:09.412] <TB2> INFO: Test took 1195ms.
[14:48:09.417] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:09.721] <TB2> INFO: Expecting 2560 events.
[14:48:10.601] <TB2> INFO: 2560 events read in total (289ms).
[14:48:10.601] <TB2> INFO: Test took 1184ms.
[14:48:10.604] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:10.909] <TB2> INFO: Expecting 2560 events.
[14:48:11.796] <TB2> INFO: 2560 events read in total (295ms).
[14:48:11.797] <TB2> INFO: Test took 1193ms.
[14:48:11.801] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:12.105] <TB2> INFO: Expecting 2560 events.
[14:48:12.996] <TB2> INFO: 2560 events read in total (299ms).
[14:48:12.997] <TB2> INFO: Test took 1196ms.
[14:48:12.000] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:13.305] <TB2> INFO: Expecting 2560 events.
[14:48:14.197] <TB2> INFO: 2560 events read in total (300ms).
[14:48:14.197] <TB2> INFO: Test took 1197ms.
[14:48:14.201] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:14.504] <TB2> INFO: Expecting 2560 events.
[14:48:15.387] <TB2> INFO: 2560 events read in total (291ms).
[14:48:15.387] <TB2> INFO: Test took 1186ms.
[14:48:15.391] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:15.696] <TB2> INFO: Expecting 2560 events.
[14:48:16.588] <TB2> INFO: 2560 events read in total (300ms).
[14:48:16.588] <TB2> INFO: Test took 1197ms.
[14:48:16.591] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:16.897] <TB2> INFO: Expecting 2560 events.
[14:48:17.788] <TB2> INFO: 2560 events read in total (300ms).
[14:48:17.789] <TB2> INFO: Test took 1198ms.
[14:48:17.793] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:18.096] <TB2> INFO: Expecting 2560 events.
[14:48:18.986] <TB2> INFO: 2560 events read in total (298ms).
[14:48:18.986] <TB2> INFO: Test took 1193ms.
[14:48:18.991] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:19.295] <TB2> INFO: Expecting 2560 events.
[14:48:20.175] <TB2> INFO: 2560 events read in total (289ms).
[14:48:20.176] <TB2> INFO: Test took 1185ms.
[14:48:20.180] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:20.484] <TB2> INFO: Expecting 2560 events.
[14:48:21.375] <TB2> INFO: 2560 events read in total (299ms).
[14:48:21.376] <TB2> INFO: Test took 1197ms.
[14:48:21.379] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:21.684] <TB2> INFO: Expecting 2560 events.
[14:48:22.578] <TB2> INFO: 2560 events read in total (302ms).
[14:48:22.579] <TB2> INFO: Test took 1200ms.
[14:48:22.581] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:22.886] <TB2> INFO: Expecting 2560 events.
[14:48:23.765] <TB2> INFO: 2560 events read in total (287ms).
[14:48:23.766] <TB2> INFO: Test took 1185ms.
[14:48:23.770] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:24.074] <TB2> INFO: Expecting 2560 events.
[14:48:24.962] <TB2> INFO: 2560 events read in total (297ms).
[14:48:24.962] <TB2> INFO: Test took 1193ms.
[14:48:24.965] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:25.271] <TB2> INFO: Expecting 2560 events.
[14:48:26.165] <TB2> INFO: 2560 events read in total (302ms).
[14:48:26.165] <TB2> INFO: Test took 1200ms.
[14:48:26.170] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:26.474] <TB2> INFO: Expecting 2560 events.
[14:48:27.366] <TB2> INFO: 2560 events read in total (301ms).
[14:48:27.366] <TB2> INFO: Test took 1196ms.
[14:48:27.369] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:27.674] <TB2> INFO: Expecting 2560 events.
[14:48:28.560] <TB2> INFO: 2560 events read in total (294ms).
[14:48:28.560] <TB2> INFO: Test took 1191ms.
[14:48:28.562] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:28.869] <TB2> INFO: Expecting 2560 events.
[14:48:29.763] <TB2> INFO: 2560 events read in total (302ms).
[14:48:29.764] <TB2> INFO: Test took 1202ms.
[14:48:29.767] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:30.072] <TB2> INFO: Expecting 2560 events.
[14:48:30.964] <TB2> INFO: 2560 events read in total (300ms).
[14:48:30.965] <TB2> INFO: Test took 1198ms.
[14:48:30.970] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:31.273] <TB2> INFO: Expecting 2560 events.
[14:48:32.165] <TB2> INFO: 2560 events read in total (300ms).
[14:48:32.165] <TB2> INFO: Test took 1195ms.
[14:48:32.169] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:32.473] <TB2> INFO: Expecting 2560 events.
[14:48:33.368] <TB2> INFO: 2560 events read in total (303ms).
[14:48:33.368] <TB2> INFO: Test took 1199ms.
[14:48:33.373] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:48:33.677] <TB2> INFO: Expecting 2560 events.
[14:48:34.576] <TB2> INFO: 2560 events read in total (307ms).
[14:48:34.577] <TB2> INFO: Test took 1204ms.
[14:48:35.065] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 653 seconds
[14:48:35.065] <TB2> INFO: PH scale (per ROC): 50 57 66 61 48 58 58 57 66 60 33 59 41 69 54 46
[14:48:35.065] <TB2> INFO: PH offset (per ROC): 97 107 134 127 107 137 119 116 112 121 109 117 96 119 101 111
[14:48:35.071] <TB2> INFO: Decoding statistics:
[14:48:35.071] <TB2> INFO: General information:
[14:48:35.071] <TB2> INFO: 16bit words read: 127886
[14:48:35.071] <TB2> INFO: valid events total: 20480
[14:48:35.071] <TB2> INFO: empty events: 17977
[14:48:35.071] <TB2> INFO: valid events with pixels: 2503
[14:48:35.071] <TB2> INFO: valid pixel hits: 2503
[14:48:35.071] <TB2> INFO: Event errors: 0
[14:48:35.071] <TB2> INFO: start marker: 0
[14:48:35.071] <TB2> INFO: stop marker: 0
[14:48:35.071] <TB2> INFO: overflow: 0
[14:48:35.071] <TB2> INFO: invalid 5bit words: 0
[14:48:35.071] <TB2> INFO: invalid XOR eye diagram: 0
[14:48:35.071] <TB2> INFO: frame (failed synchr.): 0
[14:48:35.071] <TB2> INFO: idle data (no TBM trl): 0
[14:48:35.071] <TB2> INFO: no data (only TBM hdr): 0
[14:48:35.071] <TB2> INFO: TBM errors: 0
[14:48:35.071] <TB2> INFO: flawed TBM headers: 0
[14:48:35.071] <TB2> INFO: flawed TBM trailers: 0
[14:48:35.071] <TB2> INFO: event ID mismatches: 0
[14:48:35.072] <TB2> INFO: ROC errors: 0
[14:48:35.072] <TB2> INFO: missing ROC header(s): 0
[14:48:35.072] <TB2> INFO: misplaced readback start: 0
[14:48:35.072] <TB2> INFO: Pixel decoding errors: 0
[14:48:35.072] <TB2> INFO: pixel data incomplete: 0
[14:48:35.072] <TB2> INFO: pixel address: 0
[14:48:35.072] <TB2> INFO: pulse height fill bit: 0
[14:48:35.072] <TB2> INFO: buffer corruption: 0
[14:48:35.231] <TB2> INFO: ######################################################################
[14:48:35.231] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[14:48:35.231] <TB2> INFO: ######################################################################
[14:48:35.245] <TB2> INFO: scanning low vcal = 10
[14:48:35.483] <TB2> INFO: Expecting 41600 events.
[14:48:39.118] <TB2> INFO: 41600 events read in total (3043ms).
[14:48:39.119] <TB2> INFO: Test took 3874ms.
[14:48:39.120] <TB2> INFO: scanning low vcal = 20
[14:48:39.410] <TB2> INFO: Expecting 41600 events.
[14:48:43.032] <TB2> INFO: 41600 events read in total (3030ms).
[14:48:43.032] <TB2> INFO: Test took 3912ms.
[14:48:43.034] <TB2> INFO: scanning low vcal = 30
[14:48:43.328] <TB2> INFO: Expecting 41600 events.
[14:48:47.032] <TB2> INFO: 41600 events read in total (3112ms).
[14:48:47.033] <TB2> INFO: Test took 3999ms.
[14:48:47.036] <TB2> INFO: scanning low vcal = 40
[14:48:47.314] <TB2> INFO: Expecting 41600 events.
[14:48:51.343] <TB2> INFO: 41600 events read in total (3437ms).
[14:48:51.344] <TB2> INFO: Test took 4308ms.
[14:48:51.347] <TB2> INFO: scanning low vcal = 50
[14:48:51.625] <TB2> INFO: Expecting 41600 events.
[14:48:55.606] <TB2> INFO: 41600 events read in total (3389ms).
[14:48:55.606] <TB2> INFO: Test took 4259ms.
[14:48:55.610] <TB2> INFO: scanning low vcal = 60
[14:48:55.886] <TB2> INFO: Expecting 41600 events.
[14:48:59.827] <TB2> INFO: 41600 events read in total (3350ms).
[14:48:59.828] <TB2> INFO: Test took 4218ms.
[14:48:59.832] <TB2> INFO: scanning low vcal = 70
[14:49:00.107] <TB2> INFO: Expecting 41600 events.
[14:49:04.056] <TB2> INFO: 41600 events read in total (3357ms).
[14:49:04.057] <TB2> INFO: Test took 4225ms.
[14:49:04.060] <TB2> INFO: scanning low vcal = 80
[14:49:04.337] <TB2> INFO: Expecting 41600 events.
[14:49:08.302] <TB2> INFO: 41600 events read in total (3374ms).
[14:49:08.303] <TB2> INFO: Test took 4243ms.
[14:49:08.306] <TB2> INFO: scanning low vcal = 90
[14:49:08.582] <TB2> INFO: Expecting 41600 events.
[14:49:12.520] <TB2> INFO: 41600 events read in total (3346ms).
[14:49:12.520] <TB2> INFO: Test took 4214ms.
[14:49:12.525] <TB2> INFO: scanning low vcal = 100
[14:49:12.800] <TB2> INFO: Expecting 41600 events.
[14:49:16.771] <TB2> INFO: 41600 events read in total (3380ms).
[14:49:16.772] <TB2> INFO: Test took 4247ms.
[14:49:16.777] <TB2> INFO: scanning low vcal = 110
[14:49:17.052] <TB2> INFO: Expecting 41600 events.
[14:49:21.054] <TB2> INFO: 41600 events read in total (3410ms).
[14:49:21.054] <TB2> INFO: Test took 4277ms.
[14:49:21.058] <TB2> INFO: scanning low vcal = 120
[14:49:21.334] <TB2> INFO: Expecting 41600 events.
[14:49:25.320] <TB2> INFO: 41600 events read in total (3394ms).
[14:49:25.321] <TB2> INFO: Test took 4263ms.
[14:49:25.325] <TB2> INFO: scanning low vcal = 130
[14:49:25.601] <TB2> INFO: Expecting 41600 events.
[14:49:29.605] <TB2> INFO: 41600 events read in total (3412ms).
[14:49:29.606] <TB2> INFO: Test took 4281ms.
[14:49:29.611] <TB2> INFO: scanning low vcal = 140
[14:49:29.887] <TB2> INFO: Expecting 41600 events.
[14:49:33.908] <TB2> INFO: 41600 events read in total (3430ms).
[14:49:33.909] <TB2> INFO: Test took 4298ms.
[14:49:33.913] <TB2> INFO: scanning low vcal = 150
[14:49:34.189] <TB2> INFO: Expecting 41600 events.
[14:49:38.138] <TB2> INFO: 41600 events read in total (3357ms).
[14:49:38.139] <TB2> INFO: Test took 4226ms.
[14:49:38.143] <TB2> INFO: scanning low vcal = 160
[14:49:38.419] <TB2> INFO: Expecting 41600 events.
[14:49:42.398] <TB2> INFO: 41600 events read in total (3387ms).
[14:49:42.399] <TB2> INFO: Test took 4256ms.
[14:49:42.402] <TB2> INFO: scanning low vcal = 170
[14:49:42.678] <TB2> INFO: Expecting 41600 events.
[14:49:46.660] <TB2> INFO: 41600 events read in total (3390ms).
[14:49:46.661] <TB2> INFO: Test took 4259ms.
[14:49:46.667] <TB2> INFO: scanning low vcal = 180
[14:49:46.966] <TB2> INFO: Expecting 41600 events.
[14:49:51.027] <TB2> INFO: 41600 events read in total (3469ms).
[14:49:51.028] <TB2> INFO: Test took 4361ms.
[14:49:51.031] <TB2> INFO: scanning low vcal = 190
[14:49:51.307] <TB2> INFO: Expecting 41600 events.
[14:49:55.332] <TB2> INFO: 41600 events read in total (3433ms).
[14:49:55.333] <TB2> INFO: Test took 4302ms.
[14:49:55.336] <TB2> INFO: scanning low vcal = 200
[14:49:55.613] <TB2> INFO: Expecting 41600 events.
[14:49:59.594] <TB2> INFO: 41600 events read in total (3390ms).
[14:49:59.594] <TB2> INFO: Test took 4258ms.
[14:49:59.597] <TB2> INFO: scanning low vcal = 210
[14:49:59.874] <TB2> INFO: Expecting 41600 events.
[14:50:03.890] <TB2> INFO: 41600 events read in total (3424ms).
[14:50:03.891] <TB2> INFO: Test took 4294ms.
[14:50:03.894] <TB2> INFO: scanning low vcal = 220
[14:50:04.170] <TB2> INFO: Expecting 41600 events.
[14:50:08.216] <TB2> INFO: 41600 events read in total (3454ms).
[14:50:08.217] <TB2> INFO: Test took 4323ms.
[14:50:08.219] <TB2> INFO: scanning low vcal = 230
[14:50:08.496] <TB2> INFO: Expecting 41600 events.
[14:50:12.498] <TB2> INFO: 41600 events read in total (3410ms).
[14:50:12.499] <TB2> INFO: Test took 4279ms.
[14:50:12.502] <TB2> INFO: scanning low vcal = 240
[14:50:12.779] <TB2> INFO: Expecting 41600 events.
[14:50:16.782] <TB2> INFO: 41600 events read in total (3412ms).
[14:50:16.783] <TB2> INFO: Test took 4281ms.
[14:50:16.786] <TB2> INFO: scanning low vcal = 250
[14:50:17.063] <TB2> INFO: Expecting 41600 events.
[14:50:21.126] <TB2> INFO: 41600 events read in total (3472ms).
[14:50:21.127] <TB2> INFO: Test took 4341ms.
[14:50:21.131] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[14:50:21.447] <TB2> INFO: Expecting 41600 events.
[14:50:25.542] <TB2> INFO: 41600 events read in total (3505ms).
[14:50:25.544] <TB2> INFO: Test took 4413ms.
[14:50:25.547] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[14:50:25.867] <TB2> INFO: Expecting 41600 events.
[14:50:29.878] <TB2> INFO: 41600 events read in total (3419ms).
[14:50:29.878] <TB2> INFO: Test took 4331ms.
[14:50:29.882] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[14:50:30.158] <TB2> INFO: Expecting 41600 events.
[14:50:34.169] <TB2> INFO: 41600 events read in total (3419ms).
[14:50:34.170] <TB2> INFO: Test took 4288ms.
[14:50:34.173] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[14:50:34.450] <TB2> INFO: Expecting 41600 events.
[14:50:38.489] <TB2> INFO: 41600 events read in total (3448ms).
[14:50:38.490] <TB2> INFO: Test took 4317ms.
[14:50:38.493] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[14:50:38.769] <TB2> INFO: Expecting 41600 events.
[14:50:42.759] <TB2> INFO: 41600 events read in total (3398ms).
[14:50:42.760] <TB2> INFO: Test took 4266ms.
[14:50:43.171] <TB2> INFO: PixTestGainPedestal::measure() done
[14:51:15.761] <TB2> INFO: PixTestGainPedestal::fit() done
[14:51:15.761] <TB2> INFO: non-linearity mean: 0.915 0.969 0.984 0.982 0.956 0.977 0.979 0.927 0.985 0.980 0.995 0.981 0.969 0.986 0.913 0.939
[14:51:15.761] <TB2> INFO: non-linearity RMS: 0.124 0.018 0.004 0.003 0.038 0.005 0.004 0.080 0.003 0.004 0.179 0.004 0.179 0.002 0.103 0.062
[14:51:15.761] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr35_C0.dat
[14:51:15.774] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr35_C1.dat
[14:51:15.787] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr35_C2.dat
[14:51:15.800] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr35_C3.dat
[14:51:15.813] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr35_C4.dat
[14:51:15.825] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr35_C5.dat
[14:51:15.838] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr35_C6.dat
[14:51:15.851] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr35_C7.dat
[14:51:15.864] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr35_C8.dat
[14:51:15.877] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr35_C9.dat
[14:51:15.889] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr35_C10.dat
[14:51:15.902] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr35_C11.dat
[14:51:15.915] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr35_C12.dat
[14:51:15.928] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr35_C13.dat
[14:51:15.940] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr35_C14.dat
[14:51:15.953] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1066_FullQualification_2016-10-25_13h17m_1477394256//000_Fulltest_m20//phCalibrationFitErr35_C15.dat
[14:51:15.966] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 160 seconds
[14:51:15.966] <TB2> INFO: Decoding statistics:
[14:51:15.966] <TB2> INFO: General information:
[14:51:15.966] <TB2> INFO: 16bit words read: 3327960
[14:51:15.966] <TB2> INFO: valid events total: 332800
[14:51:15.966] <TB2> INFO: empty events: 0
[14:51:15.966] <TB2> INFO: valid events with pixels: 332800
[14:51:15.966] <TB2> INFO: valid pixel hits: 665580
[14:51:15.966] <TB2> INFO: Event errors: 0
[14:51:15.966] <TB2> INFO: start marker: 0
[14:51:15.966] <TB2> INFO: stop marker: 0
[14:51:15.966] <TB2> INFO: overflow: 0
[14:51:15.966] <TB2> INFO: invalid 5bit words: 0
[14:51:15.966] <TB2> INFO: invalid XOR eye diagram: 0
[14:51:15.966] <TB2> INFO: frame (failed synchr.): 0
[14:51:15.966] <TB2> INFO: idle data (no TBM trl): 0
[14:51:15.966] <TB2> INFO: no data (only TBM hdr): 0
[14:51:15.966] <TB2> INFO: TBM errors: 0
[14:51:15.966] <TB2> INFO: flawed TBM headers: 0
[14:51:15.966] <TB2> INFO: flawed TBM trailers: 0
[14:51:15.966] <TB2> INFO: event ID mismatches: 0
[14:51:15.966] <TB2> INFO: ROC errors: 0
[14:51:15.966] <TB2> INFO: missing ROC header(s): 0
[14:51:15.966] <TB2> INFO: misplaced readback start: 0
[14:51:15.966] <TB2> INFO: Pixel decoding errors: 0
[14:51:15.966] <TB2> INFO: pixel data incomplete: 0
[14:51:15.966] <TB2> INFO: pixel address: 0
[14:51:15.966] <TB2> INFO: pulse height fill bit: 0
[14:51:15.966] <TB2> INFO: buffer corruption: 0
[14:51:15.983] <TB2> INFO: Decoding statistics:
[14:51:15.983] <TB2> INFO: General information:
[14:51:15.983] <TB2> INFO: 16bit words read: 3457382
[14:51:15.983] <TB2> INFO: valid events total: 353536
[14:51:15.983] <TB2> INFO: empty events: 18233
[14:51:15.983] <TB2> INFO: valid events with pixels: 335303
[14:51:15.983] <TB2> INFO: valid pixel hits: 668083
[14:51:15.983] <TB2> INFO: Event errors: 0
[14:51:15.983] <TB2> INFO: start marker: 0
[14:51:15.983] <TB2> INFO: stop marker: 0
[14:51:15.983] <TB2> INFO: overflow: 0
[14:51:15.983] <TB2> INFO: invalid 5bit words: 0
[14:51:15.983] <TB2> INFO: invalid XOR eye diagram: 0
[14:51:15.983] <TB2> INFO: frame (failed synchr.): 0
[14:51:15.983] <TB2> INFO: idle data (no TBM trl): 0
[14:51:15.983] <TB2> INFO: no data (only TBM hdr): 0
[14:51:15.983] <TB2> INFO: TBM errors: 0
[14:51:15.983] <TB2> INFO: flawed TBM headers: 0
[14:51:15.983] <TB2> INFO: flawed TBM trailers: 0
[14:51:15.983] <TB2> INFO: event ID mismatches: 0
[14:51:15.983] <TB2> INFO: ROC errors: 0
[14:51:15.983] <TB2> INFO: missing ROC header(s): 0
[14:51:15.983] <TB2> INFO: misplaced readback start: 0
[14:51:15.983] <TB2> INFO: Pixel decoding errors: 0
[14:51:15.983] <TB2> INFO: pixel data incomplete: 0
[14:51:15.984] <TB2> INFO: pixel address: 0
[14:51:15.984] <TB2> INFO: pulse height fill bit: 0
[14:51:15.984] <TB2> INFO: buffer corruption: 0
[14:51:15.984] <TB2> INFO: enter test to run
[14:51:15.984] <TB2> INFO: test: exit no parameter change
[14:51:16.125] <TB2> QUIET: Connection to board 149 closed.
[14:51:16.127] <TB2> INFO: pXar: this is the end, my friend