[08:09:18.104] <TB1> INFO: *** Welcome to pxar ***
[08:09:18.104] <TB1> INFO: *** Today: 2016/10/25
[08:09:18.110] <TB1> INFO: *** Version: c8ba-dirty
[08:09:18.110] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C15.dat
[08:09:18.111] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//tbmParameters_C1b.dat
[08:09:18.111] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//defaultMaskFile.dat
[08:09:18.111] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters_C15.dat
[08:09:18.173] <TB1> INFO: clk: 4
[08:09:18.173] <TB1> INFO: ctr: 4
[08:09:18.173] <TB1> INFO: sda: 19
[08:09:18.173] <TB1> INFO: tin: 9
[08:09:18.173] <TB1> INFO: level: 15
[08:09:18.173] <TB1> INFO: triggerdelay: 0
[08:09:18.173] <TB1> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[08:09:18.173] <TB1> INFO: Log level: INFO
[08:09:18.182] <TB1> INFO: Found DTB DTB_WXC03A
[08:09:18.205] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[08:09:18.207] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
------------------------------------------------------
[08:09:18.208] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[08:09:19.699] <TB1> INFO: DUT info:
[08:09:19.699] <TB1> INFO: The DUT currently contains the following objects:
[08:09:19.699] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[08:09:19.699] <TB1> INFO: TBM Core alpha (0): 7 registers set
[08:09:19.699] <TB1> INFO: TBM Core beta (1): 7 registers set
[08:09:19.699] <TB1> INFO: TBM Core alpha (2): 7 registers set
[08:09:19.699] <TB1> INFO: TBM Core beta (3): 7 registers set
[08:09:19.699] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[08:09:19.699] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[08:09:19.699] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[08:09:19.699] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[08:09:19.699] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[08:09:19.699] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[08:09:19.699] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[08:09:19.699] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[08:09:19.699] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[08:09:19.699] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[08:09:19.699] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[08:09:19.699] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[08:09:19.699] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[08:09:19.699] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[08:09:19.699] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[08:09:19.699] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[08:09:19.699] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[08:09:20.100] <TB1> INFO: enter 'restricted' command line mode
[08:09:20.100] <TB1> INFO: enter test to run
[08:09:20.100] <TB1> INFO: test: pretest no parameter change
[08:09:20.100] <TB1> INFO: running: pretest
[08:09:20.108] <TB1> INFO: ######################################################################
[08:09:20.108] <TB1> INFO: PixTestPretest::doTest()
[08:09:20.108] <TB1> INFO: ######################################################################
[08:09:20.109] <TB1> INFO: ----------------------------------------------------------------------
[08:09:20.109] <TB1> INFO: PixTestPretest::programROC()
[08:09:20.109] <TB1> INFO: ----------------------------------------------------------------------
[08:09:38.122] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[08:09:38.122] <TB1> INFO: IA differences per ROC: 17.7 19.3 17.7 17.7 17.7 18.5 18.5 18.5 19.3 20.1 17.7 20.9 17.7 18.5 19.3 19.3
[08:09:38.201] <TB1> INFO: ----------------------------------------------------------------------
[08:09:38.201] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[08:09:38.201] <TB1> INFO: ----------------------------------------------------------------------
[08:09:59.452] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 394.7 mA = 24.6687 mA/ROC
[08:09:59.453] <TB1> INFO: i(loss) [mA/ROC]: 19.3 20.9 18.5 20.1 20.1 20.1 20.1 18.5 18.5 18.5 18.5 20.1 20.9 20.1 18.5 18.5
[08:09:59.481] <TB1> INFO: ----------------------------------------------------------------------
[08:09:59.481] <TB1> INFO: PixTestPretest::findTiming()
[08:09:59.481] <TB1> INFO: ----------------------------------------------------------------------
[08:09:59.481] <TB1> INFO: PixTestCmd::init()

[08:10:30.427] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 3, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[08:10:30.427] <TB1> INFO: (success/tries = 100/100), width = 4
[08:10:31.930] <TB1> INFO: ----------------------------------------------------------------------
[08:10:31.930] <TB1> INFO: PixTestPretest::findWorkingPixel()
[08:10:31.930] <TB1> INFO: ----------------------------------------------------------------------
[08:10:32.022] <TB1> INFO: Expecting 231680 events.
[08:10:41.950] <TB1> INFO: 231680 events read in total (9337ms).
[08:10:41.961] <TB1> INFO: Test took 10028ms.
[08:10:42.198] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[08:10:42.229] <TB1> INFO: ----------------------------------------------------------------------
[08:10:42.229] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[08:10:42.229] <TB1> INFO: ----------------------------------------------------------------------
[08:10:42.322] <TB1> INFO: Expecting 231680 events.
[08:10:52.313] <TB1> INFO: 231680 events read in total (9399ms).
[08:10:52.321] <TB1> INFO: Test took 10088ms.
[08:10:52.572] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[08:10:52.572] <TB1> INFO: CalDel: 95 96 111 85 79 85 86 81 110 93 97 105 83 117 116 103
[08:10:52.572] <TB1> INFO: VthrComp: 51 51 51 51 51 56 51 51 55 51 53 56 51 51 54 52
[08:10:52.577] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C0.dat
[08:10:52.577] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C1.dat
[08:10:52.577] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C2.dat
[08:10:52.577] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C3.dat
[08:10:52.577] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C4.dat
[08:10:52.577] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C5.dat
[08:10:52.577] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C6.dat
[08:10:52.577] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C7.dat
[08:10:52.577] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C8.dat
[08:10:52.578] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C9.dat
[08:10:52.578] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C10.dat
[08:10:52.578] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C11.dat
[08:10:52.578] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C12.dat
[08:10:52.578] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C13.dat
[08:10:52.578] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C14.dat
[08:10:52.578] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters_C15.dat
[08:10:52.578] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//tbmParameters_C0a.dat
[08:10:52.578] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//tbmParameters_C0b.dat
[08:10:52.578] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//tbmParameters_C1a.dat
[08:10:52.578] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//tbmParameters_C1b.dat
[08:10:52.578] <TB1> INFO: PixTestPretest::doTest() done, duration: 92 seconds
[08:10:52.632] <TB1> INFO: enter test to run
[08:10:52.632] <TB1> INFO: test: FullTest no parameter change
[08:10:52.632] <TB1> INFO: running: fulltest
[08:10:52.632] <TB1> INFO: ######################################################################
[08:10:52.632] <TB1> INFO: PixTestFullTest::doTest()
[08:10:52.632] <TB1> INFO: ######################################################################
[08:10:52.634] <TB1> INFO: ######################################################################
[08:10:52.634] <TB1> INFO: PixTestAlive::doTest()
[08:10:52.634] <TB1> INFO: ######################################################################
[08:10:52.635] <TB1> INFO: ----------------------------------------------------------------------
[08:10:52.635] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:10:52.635] <TB1> INFO: ----------------------------------------------------------------------
[08:10:52.878] <TB1> INFO: Expecting 41600 events.
[08:10:56.517] <TB1> INFO: 41600 events read in total (3047ms).
[08:10:56.517] <TB1> INFO: Test took 3880ms.
[08:10:56.743] <TB1> INFO: PixTestAlive::aliveTest() done
[08:10:56.743] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[08:10:56.745] <TB1> INFO: ----------------------------------------------------------------------
[08:10:56.745] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:10:56.745] <TB1> INFO: ----------------------------------------------------------------------
[08:10:56.985] <TB1> INFO: Expecting 41600 events.
[08:11:00.098] <TB1> INFO: 41600 events read in total (2522ms).
[08:11:00.099] <TB1> INFO: Test took 3353ms.
[08:11:00.099] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[08:11:00.335] <TB1> INFO: PixTestAlive::maskTest() done
[08:11:00.335] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[08:11:00.337] <TB1> INFO: ----------------------------------------------------------------------
[08:11:00.337] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:11:00.337] <TB1> INFO: ----------------------------------------------------------------------
[08:11:00.576] <TB1> INFO: Expecting 41600 events.
[08:11:04.077] <TB1> INFO: 41600 events read in total (2910ms).
[08:11:04.078] <TB1> INFO: Test took 3740ms.
[08:11:04.307] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[08:11:04.307] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[08:11:04.307] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[08:11:04.307] <TB1> INFO: Decoding statistics:
[08:11:04.307] <TB1> INFO: General information:
[08:11:04.307] <TB1> INFO: 16bit words read: 0
[08:11:04.307] <TB1> INFO: valid events total: 0
[08:11:04.308] <TB1> INFO: empty events: 0
[08:11:04.308] <TB1> INFO: valid events with pixels: 0
[08:11:04.308] <TB1> INFO: valid pixel hits: 0
[08:11:04.308] <TB1> INFO: Event errors: 0
[08:11:04.308] <TB1> INFO: start marker: 0
[08:11:04.308] <TB1> INFO: stop marker: 0
[08:11:04.308] <TB1> INFO: overflow: 0
[08:11:04.308] <TB1> INFO: invalid 5bit words: 0
[08:11:04.308] <TB1> INFO: invalid XOR eye diagram: 0
[08:11:04.308] <TB1> INFO: frame (failed synchr.): 0
[08:11:04.308] <TB1> INFO: idle data (no TBM trl): 0
[08:11:04.308] <TB1> INFO: no data (only TBM hdr): 0
[08:11:04.308] <TB1> INFO: TBM errors: 0
[08:11:04.308] <TB1> INFO: flawed TBM headers: 0
[08:11:04.308] <TB1> INFO: flawed TBM trailers: 0
[08:11:04.308] <TB1> INFO: event ID mismatches: 0
[08:11:04.308] <TB1> INFO: ROC errors: 0
[08:11:04.308] <TB1> INFO: missing ROC header(s): 0
[08:11:04.308] <TB1> INFO: misplaced readback start: 0
[08:11:04.308] <TB1> INFO: Pixel decoding errors: 0
[08:11:04.308] <TB1> INFO: pixel data incomplete: 0
[08:11:04.308] <TB1> INFO: pixel address: 0
[08:11:04.308] <TB1> INFO: pulse height fill bit: 0
[08:11:04.308] <TB1> INFO: buffer corruption: 0
[08:11:04.313] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C15.dat
[08:11:04.315] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr_C15.dat

[08:11:04.315] <TB1> INFO: ######################################################################
[08:11:04.315] <TB1> INFO: PixTestReadback::doTest()
[08:11:04.315] <TB1> INFO: ######################################################################
[08:11:04.315] <TB1> INFO: ----------------------------------------------------------------------
[08:11:04.315] <TB1> INFO: PixTestReadback::CalibrateVd()
[08:11:04.315] <TB1> INFO: ----------------------------------------------------------------------
[08:11:14.240] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C0.dat
[08:11:14.240] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C1.dat
[08:11:14.240] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C2.dat
[08:11:14.240] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C3.dat
[08:11:14.240] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C4.dat
[08:11:14.240] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C5.dat
[08:11:14.240] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C6.dat
[08:11:14.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C7.dat
[08:11:14.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C8.dat
[08:11:14.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C9.dat
[08:11:14.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C10.dat
[08:11:14.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C11.dat
[08:11:14.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C12.dat
[08:11:14.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C13.dat
[08:11:14.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C14.dat
[08:11:14.241] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C15.dat
[08:11:14.269] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[08:11:14.269] <TB1> INFO: ----------------------------------------------------------------------
[08:11:14.269] <TB1> INFO: PixTestReadback::CalibrateVa()
[08:11:14.269] <TB1> INFO: ----------------------------------------------------------------------
[08:11:24.165] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C0.dat
[08:11:24.165] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C1.dat
[08:11:24.165] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C2.dat
[08:11:24.165] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C3.dat
[08:11:24.165] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C4.dat
[08:11:24.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C5.dat
[08:11:24.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C6.dat
[08:11:24.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C7.dat
[08:11:24.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C8.dat
[08:11:24.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C9.dat
[08:11:24.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C10.dat
[08:11:24.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C11.dat
[08:11:24.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C12.dat
[08:11:24.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C13.dat
[08:11:24.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C14.dat
[08:11:24.166] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C15.dat
[08:11:24.196] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[08:11:24.196] <TB1> INFO: ----------------------------------------------------------------------
[08:11:24.196] <TB1> INFO: PixTestReadback::readbackVbg()
[08:11:24.196] <TB1> INFO: ----------------------------------------------------------------------
[08:11:31.841] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[08:11:31.841] <TB1> INFO: ----------------------------------------------------------------------
[08:11:31.841] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[08:11:31.841] <TB1> INFO: ----------------------------------------------------------------------
[08:11:31.841] <TB1> INFO: Vbg will be calibrated using Vd calibration
[08:11:31.841] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 161.5calibrated Vbg = 1.19227 :::*/*/*/*/
[08:11:31.841] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 151.8calibrated Vbg = 1.19756 :::*/*/*/*/
[08:11:31.841] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 162.7calibrated Vbg = 1.19081 :::*/*/*/*/
[08:11:31.841] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 159.5calibrated Vbg = 1.18627 :::*/*/*/*/
[08:11:31.841] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 155.5calibrated Vbg = 1.18978 :::*/*/*/*/
[08:11:31.841] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 155.2calibrated Vbg = 1.1903 :::*/*/*/*/
[08:11:31.841] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 157.4calibrated Vbg = 1.20031 :::*/*/*/*/
[08:11:31.841] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 149.1calibrated Vbg = 1.19434 :::*/*/*/*/
[08:11:31.841] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 158.1calibrated Vbg = 1.19577 :::*/*/*/*/
[08:11:31.841] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 156.9calibrated Vbg = 1.19153 :::*/*/*/*/
[08:11:31.841] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 163.1calibrated Vbg = 1.18935 :::*/*/*/*/
[08:11:31.841] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 159.4calibrated Vbg = 1.182 :::*/*/*/*/
[08:11:31.841] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 152.5calibrated Vbg = 1.19001 :::*/*/*/*/
[08:11:31.841] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 156.3calibrated Vbg = 1.20002 :::*/*/*/*/
[08:11:31.841] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 156.8calibrated Vbg = 1.19238 :::*/*/*/*/
[08:11:31.841] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 159.3calibrated Vbg = 1.1873 :::*/*/*/*/
[08:11:31.843] <TB1> INFO: ----------------------------------------------------------------------
[08:11:31.843] <TB1> INFO: PixTestReadback::CalibrateIa()
[08:11:31.843] <TB1> INFO: ----------------------------------------------------------------------
[08:14:12.193] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C0.dat
[08:14:12.193] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C1.dat
[08:14:12.193] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C2.dat
[08:14:12.193] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C3.dat
[08:14:12.194] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C4.dat
[08:14:12.194] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C5.dat
[08:14:12.194] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C6.dat
[08:14:12.194] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C7.dat
[08:14:12.194] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C8.dat
[08:14:12.194] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C9.dat
[08:14:12.194] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C10.dat
[08:14:12.194] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C11.dat
[08:14:12.194] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C12.dat
[08:14:12.194] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C13.dat
[08:14:12.194] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C14.dat
[08:14:12.194] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//readbackCal_C15.dat
[08:14:12.222] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[08:14:12.223] <TB1> INFO: PixTestReadback::doTest() done
[08:14:12.223] <TB1> INFO: Decoding statistics:
[08:14:12.223] <TB1> INFO: General information:
[08:14:12.223] <TB1> INFO: 16bit words read: 1536
[08:14:12.223] <TB1> INFO: valid events total: 256
[08:14:12.223] <TB1> INFO: empty events: 256
[08:14:12.223] <TB1> INFO: valid events with pixels: 0
[08:14:12.223] <TB1> INFO: valid pixel hits: 0
[08:14:12.223] <TB1> INFO: Event errors: 0
[08:14:12.223] <TB1> INFO: start marker: 0
[08:14:12.223] <TB1> INFO: stop marker: 0
[08:14:12.223] <TB1> INFO: overflow: 0
[08:14:12.223] <TB1> INFO: invalid 5bit words: 0
[08:14:12.223] <TB1> INFO: invalid XOR eye diagram: 0
[08:14:12.223] <TB1> INFO: frame (failed synchr.): 0
[08:14:12.223] <TB1> INFO: idle data (no TBM trl): 0
[08:14:12.224] <TB1> INFO: no data (only TBM hdr): 0
[08:14:12.224] <TB1> INFO: TBM errors: 0
[08:14:12.224] <TB1> INFO: flawed TBM headers: 0
[08:14:12.224] <TB1> INFO: flawed TBM trailers: 0
[08:14:12.224] <TB1> INFO: event ID mismatches: 0
[08:14:12.224] <TB1> INFO: ROC errors: 0
[08:14:12.224] <TB1> INFO: missing ROC header(s): 0
[08:14:12.224] <TB1> INFO: misplaced readback start: 0
[08:14:12.224] <TB1> INFO: Pixel decoding errors: 0
[08:14:12.224] <TB1> INFO: pixel data incomplete: 0
[08:14:12.224] <TB1> INFO: pixel address: 0
[08:14:12.224] <TB1> INFO: pulse height fill bit: 0
[08:14:12.224] <TB1> INFO: buffer corruption: 0
[08:14:12.275] <TB1> INFO: ######################################################################
[08:14:12.275] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[08:14:12.275] <TB1> INFO: ######################################################################
[08:14:12.278] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[08:14:12.305] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[08:14:12.305] <TB1> INFO: run 1 of 1
[08:14:12.542] <TB1> INFO: Expecting 3120000 events.
[08:14:45.261] <TB1> INFO: 672100 events read in total (32127ms).











[08:15:17.139] <TB1> INFO: 1340300 events read in total (64005ms).











[08:15:48.488] <TB1> INFO: 2006180 events read in total (95354ms).











[08:16:20.490] <TB1> INFO: 2672020 events read in total (127356ms).











[08:16:42.008] <TB1> INFO: 3120000 events read in total (148874ms).
[08:16:42.069] <TB1> INFO: Test took 149765ms.
[08:17:02.934] <TB1> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 170 seconds
[08:17:02.934] <TB1> INFO: number of dead bumps (per ROC): 3 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1
[08:17:02.934] <TB1> INFO: separation cut (per ROC): 105 118 98 108 122 131 121 104 114 113 109 129 116 105 111 114
[08:17:02.934] <TB1> INFO: Decoding statistics:
[08:17:02.934] <TB1> INFO: General information:
[08:17:02.934] <TB1> INFO: 16bit words read: 0
[08:17:02.934] <TB1> INFO: valid events total: 0
[08:17:02.934] <TB1> INFO: empty events: 0
[08:17:02.934] <TB1> INFO: valid events with pixels: 0
[08:17:02.934] <TB1> INFO: valid pixel hits: 0
[08:17:02.934] <TB1> INFO: Event errors: 0
[08:17:02.934] <TB1> INFO: start marker: 0
[08:17:02.934] <TB1> INFO: stop marker: 0
[08:17:02.934] <TB1> INFO: overflow: 0
[08:17:02.934] <TB1> INFO: invalid 5bit words: 0
[08:17:02.934] <TB1> INFO: invalid XOR eye diagram: 0
[08:17:02.934] <TB1> INFO: frame (failed synchr.): 0
[08:17:02.934] <TB1> INFO: idle data (no TBM trl): 0
[08:17:02.934] <TB1> INFO: no data (only TBM hdr): 0
[08:17:02.934] <TB1> INFO: TBM errors: 0
[08:17:02.934] <TB1> INFO: flawed TBM headers: 0
[08:17:02.934] <TB1> INFO: flawed TBM trailers: 0
[08:17:02.934] <TB1> INFO: event ID mismatches: 0
[08:17:02.934] <TB1> INFO: ROC errors: 0
[08:17:02.934] <TB1> INFO: missing ROC header(s): 0
[08:17:02.934] <TB1> INFO: misplaced readback start: 0
[08:17:02.934] <TB1> INFO: Pixel decoding errors: 0
[08:17:02.934] <TB1> INFO: pixel data incomplete: 0
[08:17:02.934] <TB1> INFO: pixel address: 0
[08:17:02.934] <TB1> INFO: pulse height fill bit: 0
[08:17:02.934] <TB1> INFO: buffer corruption: 0
[08:17:02.971] <TB1> INFO: ######################################################################
[08:17:02.971] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[08:17:02.971] <TB1> INFO: ######################################################################
[08:17:02.971] <TB1> INFO: ----------------------------------------------------------------------
[08:17:02.971] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[08:17:02.971] <TB1> INFO: ----------------------------------------------------------------------
[08:17:02.971] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[08:17:02.984] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[08:17:02.984] <TB1> INFO: run 1 of 1
[08:17:03.220] <TB1> INFO: Expecting 36608000 events.
[08:17:28.505] <TB1> INFO: 711450 events read in total (24694ms).
[08:17:53.186] <TB1> INFO: 1405000 events read in total (49375ms).
[08:18:17.441] <TB1> INFO: 2100550 events read in total (73630ms).
[08:18:42.212] <TB1> INFO: 2793650 events read in total (98401ms).
[08:19:06.217] <TB1> INFO: 3486600 events read in total (122406ms).
[08:19:30.507] <TB1> INFO: 4178550 events read in total (146696ms).
[08:19:55.157] <TB1> INFO: 4871450 events read in total (171346ms).
[08:20:18.753] <TB1> INFO: 5562700 events read in total (194942ms).
[08:20:42.733] <TB1> INFO: 6251700 events read in total (218922ms).
[08:21:06.834] <TB1> INFO: 6939350 events read in total (243023ms).
[08:21:30.679] <TB1> INFO: 7627350 events read in total (266868ms).
[08:21:55.496] <TB1> INFO: 8316050 events read in total (291685ms).
[08:22:19.600] <TB1> INFO: 9007950 events read in total (315789ms).
[08:22:43.702] <TB1> INFO: 9696600 events read in total (339891ms).
[08:23:58.110] <TB1> INFO: 10387500 events read in total (414299ms).
[08:24:22.571] <TB1> INFO: 11075950 events read in total (438760ms).
[08:25:37.470] <TB1> INFO: 11765150 events read in total (513659ms).
[08:26:02.405] <TB1> INFO: 12455900 events read in total (538594ms).
[08:27:11.279] <TB1> INFO: 13142250 events read in total (607468ms).
[08:27:35.990] <TB1> INFO: 13825450 events read in total (632179ms).
[08:28:00.391] <TB1> INFO: 14510100 events read in total (656580ms).
[08:28:24.406] <TB1> INFO: 15194950 events read in total (680595ms).
[08:28:48.595] <TB1> INFO: 15880050 events read in total (704784ms).
[08:29:12.625] <TB1> INFO: 16566050 events read in total (728814ms).
[08:29:37.159] <TB1> INFO: 17250700 events read in total (753348ms).
[08:30:01.126] <TB1> INFO: 17933500 events read in total (777315ms).
[08:30:25.547] <TB1> INFO: 18616950 events read in total (801736ms).
[08:30:49.731] <TB1> INFO: 19299350 events read in total (825920ms).
[08:31:13.708] <TB1> INFO: 19982950 events read in total (849897ms).
[08:31:37.955] <TB1> INFO: 20665800 events read in total (874144ms).
[08:32:01.820] <TB1> INFO: 21346950 events read in total (898009ms).
[08:32:25.426] <TB1> INFO: 22024900 events read in total (921615ms).
[08:32:49.139] <TB1> INFO: 22703000 events read in total (945328ms).
[08:33:13.139] <TB1> INFO: 23385050 events read in total (969328ms).
[08:33:37.288] <TB1> INFO: 24065950 events read in total (993477ms).
[08:34:01.663] <TB1> INFO: 24745450 events read in total (1017852ms).
[08:34:25.751] <TB1> INFO: 25425000 events read in total (1041940ms).
[08:34:50.197] <TB1> INFO: 26104200 events read in total (1066386ms).
[08:35:14.614] <TB1> INFO: 26782500 events read in total (1090803ms).
[08:35:39.307] <TB1> INFO: 27463700 events read in total (1115496ms).
[08:36:03.142] <TB1> INFO: 28142200 events read in total (1139331ms).
[08:36:27.487] <TB1> INFO: 28823400 events read in total (1163676ms).
[08:36:51.329] <TB1> INFO: 29503250 events read in total (1187518ms).
[08:37:15.506] <TB1> INFO: 30182250 events read in total (1211695ms).
[08:37:39.697] <TB1> INFO: 30861150 events read in total (1235886ms).
[08:38:03.461] <TB1> INFO: 31541400 events read in total (1259650ms).
[08:38:27.188] <TB1> INFO: 32221800 events read in total (1283377ms).
[08:38:51.247] <TB1> INFO: 32901100 events read in total (1307436ms).
[08:39:15.579] <TB1> INFO: 33581450 events read in total (1331768ms).
[08:39:39.647] <TB1> INFO: 34262950 events read in total (1355836ms).
[08:40:03.539] <TB1> INFO: 34942550 events read in total (1379728ms).
[08:40:27.711] <TB1> INFO: 35624500 events read in total (1403900ms).
[08:40:51.918] <TB1> INFO: 36317350 events read in total (1428107ms).
[08:41:02.306] <TB1> INFO: 36608000 events read in total (1438495ms).
[08:41:02.364] <TB1> INFO: Test took 1439380ms.
[08:41:02.759] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:41:04.190] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:41:05.634] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:41:07.080] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:41:08.545] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:41:09.994] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:41:11.457] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:41:12.892] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:41:14.342] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:41:15.807] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:41:17.225] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:41:18.681] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:41:20.133] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:41:21.580] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:41:23.021] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:41:24.446] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:41:25.884] <TB1> INFO: PixTestScurves::scurves() done
[08:41:25.884] <TB1> INFO: Vcal mean: 127.33 128.07 119.43 129.54 128.38 142.02 135.24 118.02 129.64 135.41 127.11 142.34 125.77 120.17 135.30 135.40
[08:41:25.884] <TB1> INFO: Vcal RMS: 5.85 6.60 6.17 6.38 6.30 5.60 5.92 5.94 6.54 6.15 6.76 5.64 5.87 6.48 6.47 5.97
[08:41:25.884] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1462 seconds
[08:41:25.884] <TB1> INFO: Decoding statistics:
[08:41:25.884] <TB1> INFO: General information:
[08:41:25.884] <TB1> INFO: 16bit words read: 0
[08:41:25.884] <TB1> INFO: valid events total: 0
[08:41:25.885] <TB1> INFO: empty events: 0
[08:41:25.885] <TB1> INFO: valid events with pixels: 0
[08:41:25.885] <TB1> INFO: valid pixel hits: 0
[08:41:25.885] <TB1> INFO: Event errors: 0
[08:41:25.885] <TB1> INFO: start marker: 0
[08:41:25.885] <TB1> INFO: stop marker: 0
[08:41:25.885] <TB1> INFO: overflow: 0
[08:41:25.885] <TB1> INFO: invalid 5bit words: 0
[08:41:25.885] <TB1> INFO: invalid XOR eye diagram: 0
[08:41:25.885] <TB1> INFO: frame (failed synchr.): 0
[08:41:25.885] <TB1> INFO: idle data (no TBM trl): 0
[08:41:25.885] <TB1> INFO: no data (only TBM hdr): 0
[08:41:25.885] <TB1> INFO: TBM errors: 0
[08:41:25.885] <TB1> INFO: flawed TBM headers: 0
[08:41:25.885] <TB1> INFO: flawed TBM trailers: 0
[08:41:25.885] <TB1> INFO: event ID mismatches: 0
[08:41:25.885] <TB1> INFO: ROC errors: 0
[08:41:25.885] <TB1> INFO: missing ROC header(s): 0
[08:41:25.885] <TB1> INFO: misplaced readback start: 0
[08:41:25.885] <TB1> INFO: Pixel decoding errors: 0
[08:41:25.885] <TB1> INFO: pixel data incomplete: 0
[08:41:25.885] <TB1> INFO: pixel address: 0
[08:41:25.885] <TB1> INFO: pulse height fill bit: 0
[08:41:25.885] <TB1> INFO: buffer corruption: 0
[08:41:25.949] <TB1> INFO: ######################################################################
[08:41:25.949] <TB1> INFO: PixTestTrim::doTest()
[08:41:25.949] <TB1> INFO: ######################################################################
[08:41:25.950] <TB1> INFO: ----------------------------------------------------------------------
[08:41:25.950] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[08:41:25.950] <TB1> INFO: ----------------------------------------------------------------------
[08:41:26.025] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[08:41:26.025] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[08:41:26.040] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[08:41:26.040] <TB1> INFO: run 1 of 1
[08:41:26.355] <TB1> INFO: Expecting 5025280 events.
[08:41:58.644] <TB1> INFO: 843736 events read in total (31697ms).
[08:42:30.362] <TB1> INFO: 1686432 events read in total (63415ms).
[08:43:01.993] <TB1> INFO: 2525032 events read in total (95046ms).
[08:43:33.670] <TB1> INFO: 3359416 events read in total (126723ms).
[08:44:05.026] <TB1> INFO: 4190344 events read in total (158080ms).
[08:44:36.571] <TB1> INFO: 5020176 events read in total (189624ms).
[08:44:37.170] <TB1> INFO: 5025280 events read in total (190223ms).
[08:44:37.233] <TB1> INFO: Test took 191194ms.
[08:44:49.396] <TB1> INFO: ROC 0 VthrComp = 127
[08:44:49.396] <TB1> INFO: ROC 1 VthrComp = 131
[08:44:49.396] <TB1> INFO: ROC 2 VthrComp = 111
[08:44:49.396] <TB1> INFO: ROC 3 VthrComp = 130
[08:44:49.396] <TB1> INFO: ROC 4 VthrComp = 133
[08:44:49.396] <TB1> INFO: ROC 5 VthrComp = 140
[08:44:49.397] <TB1> INFO: ROC 6 VthrComp = 136
[08:44:49.397] <TB1> INFO: ROC 7 VthrComp = 119
[08:44:49.397] <TB1> INFO: ROC 8 VthrComp = 125
[08:44:49.397] <TB1> INFO: ROC 9 VthrComp = 133
[08:44:49.397] <TB1> INFO: ROC 10 VthrComp = 116
[08:44:49.397] <TB1> INFO: ROC 11 VthrComp = 137
[08:44:49.397] <TB1> INFO: ROC 12 VthrComp = 132
[08:44:49.398] <TB1> INFO: ROC 13 VthrComp = 117
[08:44:49.398] <TB1> INFO: ROC 14 VthrComp = 126
[08:44:49.398] <TB1> INFO: ROC 15 VthrComp = 123
[08:44:49.656] <TB1> INFO: Expecting 41600 events.
[08:44:53.447] <TB1> INFO: 41600 events read in total (3200ms).
[08:44:53.447] <TB1> INFO: Test took 4048ms.
[08:44:53.456] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[08:44:53.456] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[08:44:53.468] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[08:44:53.468] <TB1> INFO: run 1 of 1
[08:44:53.746] <TB1> INFO: Expecting 5025280 events.
[08:45:22.460] <TB1> INFO: 594176 events read in total (28123ms).
[08:45:49.308] <TB1> INFO: 1186512 events read in total (54971ms).
[08:46:16.679] <TB1> INFO: 1779904 events read in total (82342ms).
[08:46:44.015] <TB1> INFO: 2372176 events read in total (109678ms).
[08:47:11.568] <TB1> INFO: 2962352 events read in total (137231ms).
[08:47:38.482] <TB1> INFO: 3550704 events read in total (164145ms).
[08:48:05.756] <TB1> INFO: 4137848 events read in total (191419ms).
[08:48:32.496] <TB1> INFO: 4724048 events read in total (218159ms).
[08:48:46.745] <TB1> INFO: 5025280 events read in total (232408ms).
[08:48:46.816] <TB1> INFO: Test took 233347ms.
[08:49:08.150] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 60.7 for pixel 12/24 mean/min/max = 46.2289/31.6285/60.8292
[08:49:08.151] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 63.0634 for pixel 0/0 mean/min/max = 48.026/32.6976/63.3543
[08:49:08.152] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 70.3316 for pixel 0/6 mean/min/max = 51.9903/33.5629/70.4178
[08:49:08.152] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 61.729 for pixel 17/48 mean/min/max = 46.4555/31.1095/61.8015
[08:49:08.153] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 64.3852 for pixel 12/9 mean/min/max = 49.868/35.1853/64.5506
[08:49:08.153] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 71.2417 for pixel 35/28 mean/min/max = 55.0577/38.7594/71.356
[08:49:08.154] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 63.2062 for pixel 37/1 mean/min/max = 49.0847/34.8909/63.2784
[08:49:08.155] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 59.764 for pixel 0/19 mean/min/max = 45.5127/31.1916/59.8337
[08:49:08.155] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 68.2065 for pixel 17/3 mean/min/max = 49.864/31.4603/68.2676
[08:49:08.156] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 64.0549 for pixel 5/2 mean/min/max = 48.5972/33.1201/64.0743
[08:49:08.157] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 67.9987 for pixel 13/8 mean/min/max = 50.1364/32.2603/68.0126
[08:49:08.157] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 69.6235 for pixel 0/7 mean/min/max = 53.7994/37.786/69.8129
[08:49:08.158] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 60.8572 for pixel 16/48 mean/min/max = 47.7043/34.5442/60.8643
[08:49:08.158] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 64.8057 for pixel 0/14 mean/min/max = 47.8982/30.7232/65.0732
[08:49:08.159] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 66.1016 for pixel 4/1 mean/min/max = 48.7697/31.4004/66.139
[08:49:08.159] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 67.5062 for pixel 15/6 mean/min/max = 49.5466/30.8944/68.1987
[08:49:08.160] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[08:49:08.248] <TB1> INFO: Expecting 411648 events.
[08:49:17.978] <TB1> INFO: 411648 events read in total (9139ms).
[08:49:17.986] <TB1> INFO: Expecting 411648 events.
[08:49:27.537] <TB1> INFO: 411648 events read in total (9148ms).
[08:49:27.547] <TB1> INFO: Expecting 411648 events.
[08:49:37.090] <TB1> INFO: 411648 events read in total (9140ms).
[08:49:37.103] <TB1> INFO: Expecting 411648 events.
[08:49:46.726] <TB1> INFO: 411648 events read in total (9220ms).
[08:49:46.749] <TB1> INFO: Expecting 411648 events.
[08:49:56.320] <TB1> INFO: 411648 events read in total (9168ms).
[08:49:56.338] <TB1> INFO: Expecting 411648 events.
[08:50:05.926] <TB1> INFO: 411648 events read in total (9185ms).
[08:50:05.948] <TB1> INFO: Expecting 411648 events.
[08:50:15.542] <TB1> INFO: 411648 events read in total (9191ms).
[08:50:15.577] <TB1> INFO: Expecting 411648 events.
[08:50:25.187] <TB1> INFO: 411648 events read in total (9207ms).
[08:50:25.213] <TB1> INFO: Expecting 411648 events.
[08:50:34.727] <TB1> INFO: 411648 events read in total (9111ms).
[08:50:34.757] <TB1> INFO: Expecting 411648 events.
[08:50:44.362] <TB1> INFO: 411648 events read in total (9202ms).
[08:50:44.394] <TB1> INFO: Expecting 411648 events.
[08:50:53.981] <TB1> INFO: 411648 events read in total (9184ms).
[08:50:54.016] <TB1> INFO: Expecting 411648 events.
[08:51:03.673] <TB1> INFO: 411648 events read in total (9254ms).
[08:51:03.729] <TB1> INFO: Expecting 411648 events.
[08:51:13.279] <TB1> INFO: 411648 events read in total (9147ms).
[08:51:13.321] <TB1> INFO: Expecting 411648 events.
[08:51:22.872] <TB1> INFO: 411648 events read in total (9148ms).
[08:51:22.916] <TB1> INFO: Expecting 411648 events.
[08:51:32.505] <TB1> INFO: 411648 events read in total (9186ms).
[08:51:32.552] <TB1> INFO: Expecting 411648 events.
[08:51:42.332] <TB1> INFO: 411648 events read in total (9377ms).
[08:51:42.404] <TB1> INFO: Test took 154244ms.
[08:51:43.070] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[08:51:43.082] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[08:51:43.083] <TB1> INFO: run 1 of 1
[08:51:43.321] <TB1> INFO: Expecting 5025280 events.
[08:52:11.073] <TB1> INFO: 591736 events read in total (27161ms).
[08:52:38.714] <TB1> INFO: 1180952 events read in total (54802ms).
[08:53:06.551] <TB1> INFO: 1768864 events read in total (82639ms).
[08:53:33.318] <TB1> INFO: 2355992 events read in total (109406ms).
[08:54:00.246] <TB1> INFO: 2942328 events read in total (136334ms).
[08:54:27.463] <TB1> INFO: 3528872 events read in total (163551ms).
[08:54:54.898] <TB1> INFO: 4117472 events read in total (190986ms).
[08:55:21.980] <TB1> INFO: 4704880 events read in total (218068ms).
[08:55:37.379] <TB1> INFO: 5025280 events read in total (233468ms).
[08:55:37.509] <TB1> INFO: Test took 234428ms.
[08:55:56.719] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 2.500000 .. 144.538319
[08:55:57.035] <TB1> INFO: Expecting 208000 events.
[08:56:07.109] <TB1> INFO: 208000 events read in total (9482ms).
[08:56:07.111] <TB1> INFO: Test took 10391ms.
[08:56:07.159] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 154 (-1/-1) hits flags = 528 (plus default)
[08:56:07.172] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[08:56:07.172] <TB1> INFO: run 1 of 1
[08:56:07.465] <TB1> INFO: Expecting 5091840 events.
[08:56:34.559] <TB1> INFO: 583520 events read in total (26502ms).
[08:57:01.961] <TB1> INFO: 1167288 events read in total (53904ms).
[08:57:29.398] <TB1> INFO: 1751192 events read in total (81341ms).
[08:57:56.052] <TB1> INFO: 2334848 events read in total (107996ms).
[08:58:23.234] <TB1> INFO: 2918496 events read in total (135177ms).
[08:58:50.409] <TB1> INFO: 3501720 events read in total (162352ms).
[08:59:17.564] <TB1> INFO: 4085240 events read in total (189508ms).
[08:59:44.789] <TB1> INFO: 4668432 events read in total (216732ms).
[09:00:03.765] <TB1> INFO: 5091840 events read in total (235708ms).
[09:00:03.867] <TB1> INFO: Test took 236695ms.
[09:00:25.980] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 26.894447 .. 47.224366
[09:00:26.217] <TB1> INFO: Expecting 208000 events.
[09:00:36.916] <TB1> INFO: 208000 events read in total (10107ms).
[09:00:36.917] <TB1> INFO: Test took 10936ms.
[09:00:36.964] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 57 (-1/-1) hits flags = 528 (plus default)
[09:00:36.976] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[09:00:36.976] <TB1> INFO: run 1 of 1
[09:00:37.254] <TB1> INFO: Expecting 1397760 events.
[09:01:07.796] <TB1> INFO: 656544 events read in total (29950ms).
[09:01:36.330] <TB1> INFO: 1312072 events read in total (58485ms).
[09:01:40.597] <TB1> INFO: 1397760 events read in total (62751ms).
[09:01:40.644] <TB1> INFO: Test took 63667ms.
[09:01:52.683] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 28.343400 .. 52.197045
[09:01:52.921] <TB1> INFO: Expecting 208000 events.
[09:02:03.142] <TB1> INFO: 208000 events read in total (9629ms).
[09:02:03.143] <TB1> INFO: Test took 10458ms.
[09:02:03.192] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 18 .. 62 (-1/-1) hits flags = 528 (plus default)
[09:02:03.205] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[09:02:03.205] <TB1> INFO: run 1 of 1
[09:02:03.483] <TB1> INFO: Expecting 1497600 events.
[09:02:32.799] <TB1> INFO: 633104 events read in total (28724ms).
[09:03:01.272] <TB1> INFO: 1265568 events read in total (57197ms).
[09:03:12.139] <TB1> INFO: 1497600 events read in total (68064ms).
[09:03:12.184] <TB1> INFO: Test took 68980ms.
[09:03:24.983] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 26.425757 .. 56.962997
[09:03:25.220] <TB1> INFO: Expecting 208000 events.
[09:03:35.470] <TB1> INFO: 208000 events read in total (9659ms).
[09:03:35.470] <TB1> INFO: Test took 10486ms.
[09:03:35.517] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 66 (-1/-1) hits flags = 528 (plus default)
[09:03:35.530] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[09:03:35.531] <TB1> INFO: run 1 of 1
[09:03:35.809] <TB1> INFO: Expecting 1697280 events.
[09:04:04.876] <TB1> INFO: 630320 events read in total (28476ms).
[09:04:33.352] <TB1> INFO: 1260328 events read in total (56952ms).
[09:04:53.114] <TB1> INFO: 1697280 events read in total (76714ms).
[09:04:53.163] <TB1> INFO: Test took 77632ms.
[09:05:06.493] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[09:05:06.493] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[09:05:06.505] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[09:05:06.505] <TB1> INFO: run 1 of 1
[09:05:06.742] <TB1> INFO: Expecting 1364480 events.
[09:05:36.609] <TB1> INFO: 668328 events read in total (29276ms).
[09:06:05.637] <TB1> INFO: 1336184 events read in total (58305ms).
[09:06:07.339] <TB1> INFO: 1364480 events read in total (60006ms).
[09:06:07.376] <TB1> INFO: Test took 60871ms.
[09:06:19.640] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C0.dat
[09:06:19.640] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C1.dat
[09:06:19.640] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C2.dat
[09:06:19.640] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C3.dat
[09:06:19.640] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C4.dat
[09:06:19.640] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C5.dat
[09:06:19.640] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C6.dat
[09:06:19.640] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C7.dat
[09:06:19.640] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C8.dat
[09:06:19.640] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C9.dat
[09:06:19.641] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C10.dat
[09:06:19.641] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C11.dat
[09:06:19.641] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C12.dat
[09:06:19.641] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C13.dat
[09:06:19.641] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C14.dat
[09:06:19.641] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C15.dat
[09:06:19.641] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters35_C0.dat
[09:06:19.648] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters35_C1.dat
[09:06:19.653] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters35_C2.dat
[09:06:19.658] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters35_C3.dat
[09:06:19.663] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters35_C4.dat
[09:06:19.667] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters35_C5.dat
[09:06:19.672] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters35_C6.dat
[09:06:19.677] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters35_C7.dat
[09:06:19.682] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters35_C8.dat
[09:06:19.686] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters35_C9.dat
[09:06:19.691] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters35_C10.dat
[09:06:19.696] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters35_C11.dat
[09:06:19.701] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters35_C12.dat
[09:06:19.705] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters35_C13.dat
[09:06:19.710] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters35_C14.dat
[09:06:19.715] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//trimParameters35_C15.dat
[09:06:19.720] <TB1> INFO: PixTestTrim::trimTest() done
[09:06:19.720] <TB1> INFO: vtrim: 128 147 148 140 173 201 146 115 153 151 125 161 130 136 142 145
[09:06:19.720] <TB1> INFO: vthrcomp: 127 131 111 130 133 140 136 119 125 133 116 137 132 117 126 123
[09:06:19.720] <TB1> INFO: vcal mean: 35.05 35.01 35.82 34.99 35.16 36.35 35.01 34.94 35.88 35.17 35.45 35.00 34.96 35.00 35.64 35.25
[09:06:19.720] <TB1> INFO: vcal RMS: 1.20 1.09 2.15 1.23 1.17 2.71 1.03 1.08 2.09 1.33 1.66 1.23 0.97 1.16 1.88 1.45
[09:06:19.720] <TB1> INFO: bits mean: 9.56 8.59 8.86 9.66 8.59 8.45 8.25 9.19 9.65 9.14 8.81 7.68 8.79 8.92 9.70 9.40
[09:06:19.720] <TB1> INFO: bits RMS: 2.76 2.87 2.79 2.73 2.41 2.35 2.58 3.01 2.71 2.61 2.85 2.30 2.51 3.02 2.69 2.80
[09:06:19.728] <TB1> INFO: ----------------------------------------------------------------------
[09:06:19.728] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[09:06:19.728] <TB1> INFO: ----------------------------------------------------------------------
[09:06:19.730] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[09:06:19.744] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[09:06:19.744] <TB1> INFO: run 1 of 1
[09:06:19.980] <TB1> INFO: Expecting 4160000 events.
[09:06:54.646] <TB1> INFO: 782920 events read in total (34074ms).
[09:07:27.845] <TB1> INFO: 1558710 events read in total (67273ms).
[09:08:01.242] <TB1> INFO: 2327780 events read in total (100670ms).
[09:08:34.566] <TB1> INFO: 3092005 events read in total (133994ms).
[09:09:07.877] <TB1> INFO: 3856880 events read in total (167305ms).
[09:09:21.493] <TB1> INFO: 4160000 events read in total (180921ms).
[09:09:21.568] <TB1> INFO: Test took 181825ms.
[09:09:44.805] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 224 (-1/-1) hits flags = 528 (plus default)
[09:09:44.818] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[09:09:44.818] <TB1> INFO: run 1 of 1
[09:09:45.055] <TB1> INFO: Expecting 4680000 events.
[09:10:17.984] <TB1> INFO: 722165 events read in total (32337ms).
[09:10:50.727] <TB1> INFO: 1438915 events read in total (65080ms).
[09:11:23.446] <TB1> INFO: 2153225 events read in total (97799ms).
[09:11:55.256] <TB1> INFO: 2864245 events read in total (129609ms).
[09:12:27.483] <TB1> INFO: 3573840 events read in total (161836ms).
[09:12:59.825] <TB1> INFO: 4283480 events read in total (194178ms).
[09:13:17.686] <TB1> INFO: 4680000 events read in total (212039ms).
[09:13:17.782] <TB1> INFO: Test took 212964ms.
[09:13:42.350] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[09:13:42.363] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[09:13:42.363] <TB1> INFO: run 1 of 1
[09:13:42.599] <TB1> INFO: Expecting 4472000 events.
[09:14:15.533] <TB1> INFO: 734210 events read in total (32342ms).
[09:14:48.344] <TB1> INFO: 1463400 events read in total (65153ms).
[09:15:21.126] <TB1> INFO: 2188690 events read in total (97935ms).
[09:15:53.890] <TB1> INFO: 2910785 events read in total (130699ms).
[09:16:26.221] <TB1> INFO: 3632000 events read in total (163030ms).
[09:16:58.817] <TB1> INFO: 4352805 events read in total (195626ms).
[09:17:04.366] <TB1> INFO: 4472000 events read in total (201175ms).
[09:17:04.428] <TB1> INFO: Test took 202065ms.
[09:17:28.246] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[09:17:28.259] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[09:17:28.259] <TB1> INFO: run 1 of 1
[09:17:28.496] <TB1> INFO: Expecting 4472000 events.
[09:18:01.944] <TB1> INFO: 734290 events read in total (32857ms).
[09:18:34.516] <TB1> INFO: 1463590 events read in total (65429ms).
[09:19:06.823] <TB1> INFO: 2188930 events read in total (97736ms).
[09:19:38.913] <TB1> INFO: 2911285 events read in total (129826ms).
[09:20:11.460] <TB1> INFO: 3632345 events read in total (162373ms).
[09:20:44.007] <TB1> INFO: 4353600 events read in total (194920ms).
[09:20:49.563] <TB1> INFO: 4472000 events read in total (200476ms).
[09:20:49.625] <TB1> INFO: Test took 201366ms.
[09:21:13.173] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 215 (-1/-1) hits flags = 528 (plus default)
[09:21:13.186] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[09:21:13.186] <TB1> INFO: run 1 of 1
[09:21:13.425] <TB1> INFO: Expecting 4492800 events.
[09:21:46.625] <TB1> INFO: 733700 events read in total (32608ms).
[09:22:18.849] <TB1> INFO: 1461480 events read in total (64832ms).
[09:22:51.645] <TB1> INFO: 2185820 events read in total (97628ms).
[09:23:23.947] <TB1> INFO: 2906770 events read in total (129930ms).
[09:23:56.670] <TB1> INFO: 3626365 events read in total (162653ms).
[09:24:29.183] <TB1> INFO: 4346115 events read in total (195166ms).
[09:24:36.329] <TB1> INFO: 4492800 events read in total (202312ms).
[09:24:36.390] <TB1> INFO: Test took 203204ms.
[09:25:00.166] <TB1> INFO: PixTestTrim::trimBitTest() done
[09:25:00.167] <TB1> INFO: PixTestTrim::doTest() done, duration: 2614 seconds
[09:25:00.167] <TB1> INFO: Decoding statistics:
[09:25:00.167] <TB1> INFO: General information:
[09:25:00.167] <TB1> INFO: 16bit words read: 0
[09:25:00.167] <TB1> INFO: valid events total: 0
[09:25:00.167] <TB1> INFO: empty events: 0
[09:25:00.167] <TB1> INFO: valid events with pixels: 0
[09:25:00.167] <TB1> INFO: valid pixel hits: 0
[09:25:00.167] <TB1> INFO: Event errors: 0
[09:25:00.167] <TB1> INFO: start marker: 0
[09:25:00.167] <TB1> INFO: stop marker: 0
[09:25:00.167] <TB1> INFO: overflow: 0
[09:25:00.167] <TB1> INFO: invalid 5bit words: 0
[09:25:00.167] <TB1> INFO: invalid XOR eye diagram: 0
[09:25:00.167] <TB1> INFO: frame (failed synchr.): 0
[09:25:00.167] <TB1> INFO: idle data (no TBM trl): 0
[09:25:00.167] <TB1> INFO: no data (only TBM hdr): 0
[09:25:00.167] <TB1> INFO: TBM errors: 0
[09:25:00.167] <TB1> INFO: flawed TBM headers: 0
[09:25:00.167] <TB1> INFO: flawed TBM trailers: 0
[09:25:00.167] <TB1> INFO: event ID mismatches: 0
[09:25:00.167] <TB1> INFO: ROC errors: 0
[09:25:00.167] <TB1> INFO: missing ROC header(s): 0
[09:25:00.167] <TB1> INFO: misplaced readback start: 0
[09:25:00.167] <TB1> INFO: Pixel decoding errors: 0
[09:25:00.167] <TB1> INFO: pixel data incomplete: 0
[09:25:00.167] <TB1> INFO: pixel address: 0
[09:25:00.167] <TB1> INFO: pulse height fill bit: 0
[09:25:00.167] <TB1> INFO: buffer corruption: 0
[09:25:00.811] <TB1> INFO: ######################################################################
[09:25:00.811] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[09:25:00.811] <TB1> INFO: ######################################################################
[09:25:01.073] <TB1> INFO: Expecting 41600 events.
[09:25:04.542] <TB1> INFO: 41600 events read in total (2878ms).
[09:25:04.543] <TB1> INFO: Test took 3730ms.
[09:25:04.990] <TB1> INFO: Expecting 41600 events.
[09:25:08.685] <TB1> INFO: 41600 events read in total (3103ms).
[09:25:08.686] <TB1> INFO: Test took 3940ms.
[09:25:09.024] <TB1> INFO: Expecting 41600 events.
[09:25:12.689] <TB1> INFO: 41600 events read in total (3073ms).
[09:25:12.690] <TB1> INFO: Test took 3979ms.
[09:25:12.979] <TB1> INFO: Expecting 41600 events.
[09:25:16.500] <TB1> INFO: 41600 events read in total (2929ms).
[09:25:16.501] <TB1> INFO: Test took 3787ms.
[09:25:16.839] <TB1> INFO: Expecting 41600 events.
[09:25:20.339] <TB1> INFO: 41600 events read in total (2909ms).
[09:25:20.339] <TB1> INFO: Test took 3815ms.
[09:25:20.675] <TB1> INFO: Expecting 41600 events.
[09:25:24.322] <TB1> INFO: 41600 events read in total (3055ms).
[09:25:24.323] <TB1> INFO: Test took 3960ms.
[09:25:24.612] <TB1> INFO: Expecting 41600 events.
[09:25:28.257] <TB1> INFO: 41600 events read in total (3053ms).
[09:25:28.257] <TB1> INFO: Test took 3910ms.
[09:25:28.546] <TB1> INFO: Expecting 41600 events.
[09:25:32.184] <TB1> INFO: 41600 events read in total (3046ms).
[09:25:32.185] <TB1> INFO: Test took 3904ms.
[09:25:32.475] <TB1> INFO: Expecting 41600 events.
[09:25:36.270] <TB1> INFO: 41600 events read in total (3203ms).
[09:25:36.270] <TB1> INFO: Test took 4061ms.
[09:25:36.559] <TB1> INFO: Expecting 41600 events.
[09:25:40.269] <TB1> INFO: 41600 events read in total (3118ms).
[09:25:40.270] <TB1> INFO: Test took 3976ms.
[09:25:40.607] <TB1> INFO: Expecting 41600 events.
[09:25:44.450] <TB1> INFO: 41600 events read in total (3251ms).
[09:25:44.451] <TB1> INFO: Test took 4157ms.
[09:25:44.795] <TB1> INFO: Expecting 41600 events.
[09:25:48.589] <TB1> INFO: 41600 events read in total (3203ms).
[09:25:48.590] <TB1> INFO: Test took 4111ms.
[09:25:48.879] <TB1> INFO: Expecting 41600 events.
[09:25:52.529] <TB1> INFO: 41600 events read in total (3058ms).
[09:25:52.530] <TB1> INFO: Test took 3916ms.
[09:25:52.868] <TB1> INFO: Expecting 41600 events.
[09:25:56.363] <TB1> INFO: 41600 events read in total (2904ms).
[09:25:56.364] <TB1> INFO: Test took 3810ms.
[09:25:56.658] <TB1> INFO: Expecting 41600 events.
[09:26:00.194] <TB1> INFO: 41600 events read in total (2944ms).
[09:26:00.195] <TB1> INFO: Test took 3802ms.
[09:26:00.485] <TB1> INFO: Expecting 41600 events.
[09:26:04.259] <TB1> INFO: 41600 events read in total (3183ms).
[09:26:04.261] <TB1> INFO: Test took 4041ms.
[09:26:04.556] <TB1> INFO: Expecting 41600 events.
[09:26:08.373] <TB1> INFO: 41600 events read in total (3226ms).
[09:26:08.376] <TB1> INFO: Test took 4085ms.
[09:26:08.665] <TB1> INFO: Expecting 41600 events.
[09:26:12.196] <TB1> INFO: 41600 events read in total (2940ms).
[09:26:12.197] <TB1> INFO: Test took 3797ms.
[09:26:12.540] <TB1> INFO: Expecting 41600 events.
[09:26:16.060] <TB1> INFO: 41600 events read in total (2929ms).
[09:26:16.061] <TB1> INFO: Test took 3839ms.
[09:26:16.351] <TB1> INFO: Expecting 41600 events.
[09:26:20.151] <TB1> INFO: 41600 events read in total (3209ms).
[09:26:20.151] <TB1> INFO: Test took 4065ms.
[09:26:20.496] <TB1> INFO: Expecting 41600 events.
[09:26:24.030] <TB1> INFO: 41600 events read in total (2943ms).
[09:26:24.031] <TB1> INFO: Test took 3855ms.
[09:26:24.325] <TB1> INFO: Expecting 41600 events.
[09:26:27.828] <TB1> INFO: 41600 events read in total (2911ms).
[09:26:27.829] <TB1> INFO: Test took 3769ms.
[09:26:28.117] <TB1> INFO: Expecting 41600 events.
[09:26:31.878] <TB1> INFO: 41600 events read in total (3169ms).
[09:26:31.879] <TB1> INFO: Test took 4026ms.
[09:26:32.169] <TB1> INFO: Expecting 41600 events.
[09:26:35.824] <TB1> INFO: 41600 events read in total (3064ms).
[09:26:35.824] <TB1> INFO: Test took 3920ms.
[09:26:36.166] <TB1> INFO: Expecting 41600 events.
[09:26:39.819] <TB1> INFO: 41600 events read in total (3061ms).
[09:26:39.819] <TB1> INFO: Test took 3966ms.
[09:26:40.159] <TB1> INFO: Expecting 41600 events.
[09:26:43.965] <TB1> INFO: 41600 events read in total (3214ms).
[09:26:43.966] <TB1> INFO: Test took 4123ms.
[09:26:44.259] <TB1> INFO: Expecting 41600 events.
[09:26:48.123] <TB1> INFO: 41600 events read in total (3272ms).
[09:26:48.124] <TB1> INFO: Test took 4130ms.
[09:26:48.469] <TB1> INFO: Expecting 41600 events.
[09:26:52.112] <TB1> INFO: 41600 events read in total (3052ms).
[09:26:52.113] <TB1> INFO: Test took 3960ms.
[09:26:52.404] <TB1> INFO: Expecting 41600 events.
[09:26:56.207] <TB1> INFO: 41600 events read in total (3212ms).
[09:26:56.207] <TB1> INFO: Test took 4068ms.
[09:26:56.497] <TB1> INFO: Expecting 2560 events.
[09:26:57.381] <TB1> INFO: 2560 events read in total (293ms).
[09:26:57.381] <TB1> INFO: Test took 1161ms.
[09:26:57.689] <TB1> INFO: Expecting 2560 events.
[09:26:58.579] <TB1> INFO: 2560 events read in total (298ms).
[09:26:58.579] <TB1> INFO: Test took 1197ms.
[09:26:58.887] <TB1> INFO: Expecting 2560 events.
[09:26:59.774] <TB1> INFO: 2560 events read in total (295ms).
[09:26:59.774] <TB1> INFO: Test took 1195ms.
[09:27:00.082] <TB1> INFO: Expecting 2560 events.
[09:27:00.975] <TB1> INFO: 2560 events read in total (301ms).
[09:27:00.975] <TB1> INFO: Test took 1200ms.
[09:27:01.283] <TB1> INFO: Expecting 2560 events.
[09:27:02.166] <TB1> INFO: 2560 events read in total (291ms).
[09:27:02.166] <TB1> INFO: Test took 1191ms.
[09:27:02.473] <TB1> INFO: Expecting 2560 events.
[09:27:03.358] <TB1> INFO: 2560 events read in total (293ms).
[09:27:03.358] <TB1> INFO: Test took 1191ms.
[09:27:03.665] <TB1> INFO: Expecting 2560 events.
[09:27:04.553] <TB1> INFO: 2560 events read in total (296ms).
[09:27:04.553] <TB1> INFO: Test took 1195ms.
[09:27:04.861] <TB1> INFO: Expecting 2560 events.
[09:27:05.744] <TB1> INFO: 2560 events read in total (291ms).
[09:27:05.744] <TB1> INFO: Test took 1190ms.
[09:27:06.052] <TB1> INFO: Expecting 2560 events.
[09:27:06.938] <TB1> INFO: 2560 events read in total (294ms).
[09:27:06.938] <TB1> INFO: Test took 1194ms.
[09:27:07.246] <TB1> INFO: Expecting 2560 events.
[09:27:08.126] <TB1> INFO: 2560 events read in total (289ms).
[09:27:08.126] <TB1> INFO: Test took 1186ms.
[09:27:08.434] <TB1> INFO: Expecting 2560 events.
[09:27:09.324] <TB1> INFO: 2560 events read in total (298ms).
[09:27:09.324] <TB1> INFO: Test took 1197ms.
[09:27:09.632] <TB1> INFO: Expecting 2560 events.
[09:27:10.519] <TB1> INFO: 2560 events read in total (296ms).
[09:27:10.519] <TB1> INFO: Test took 1194ms.
[09:27:10.827] <TB1> INFO: Expecting 2560 events.
[09:27:11.719] <TB1> INFO: 2560 events read in total (300ms).
[09:27:11.719] <TB1> INFO: Test took 1200ms.
[09:27:12.026] <TB1> INFO: Expecting 2560 events.
[09:27:12.913] <TB1> INFO: 2560 events read in total (295ms).
[09:27:12.913] <TB1> INFO: Test took 1194ms.
[09:27:13.222] <TB1> INFO: Expecting 2560 events.
[09:27:14.107] <TB1> INFO: 2560 events read in total (294ms).
[09:27:14.107] <TB1> INFO: Test took 1193ms.
[09:27:14.415] <TB1> INFO: Expecting 2560 events.
[09:27:15.302] <TB1> INFO: 2560 events read in total (295ms).
[09:27:15.302] <TB1> INFO: Test took 1194ms.
[09:27:15.305] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:27:15.611] <TB1> INFO: Expecting 655360 events.
[09:27:30.648] <TB1> INFO: 655360 events read in total (14445ms).
[09:27:30.661] <TB1> INFO: Expecting 655360 events.
[09:27:45.621] <TB1> INFO: 655360 events read in total (14557ms).
[09:27:45.637] <TB1> INFO: Expecting 655360 events.
[09:28:00.548] <TB1> INFO: 655360 events read in total (14508ms).
[09:28:00.570] <TB1> INFO: Expecting 655360 events.
[09:28:15.335] <TB1> INFO: 655360 events read in total (14362ms).
[09:28:15.360] <TB1> INFO: Expecting 655360 events.
[09:28:30.208] <TB1> INFO: 655360 events read in total (14445ms).
[09:28:30.239] <TB1> INFO: Expecting 655360 events.
[09:28:45.216] <TB1> INFO: 655360 events read in total (14574ms).
[09:28:45.255] <TB1> INFO: Expecting 655360 events.
[09:29:00.187] <TB1> INFO: 655360 events read in total (14529ms).
[09:29:00.233] <TB1> INFO: Expecting 655360 events.
[09:29:15.138] <TB1> INFO: 655360 events read in total (14502ms).
[09:29:15.182] <TB1> INFO: Expecting 655360 events.
[09:29:30.183] <TB1> INFO: 655360 events read in total (14598ms).
[09:29:30.238] <TB1> INFO: Expecting 655360 events.
[09:29:45.055] <TB1> INFO: 655360 events read in total (14413ms).
[09:29:45.108] <TB1> INFO: Expecting 655360 events.
[09:29:59.927] <TB1> INFO: 655360 events read in total (14416ms).
[09:29:59.992] <TB1> INFO: Expecting 655360 events.
[09:30:14.993] <TB1> INFO: 655360 events read in total (14598ms).
[09:30:15.059] <TB1> INFO: Expecting 655360 events.
[09:30:30.245] <TB1> INFO: 655360 events read in total (14783ms).
[09:30:30.317] <TB1> INFO: Expecting 655360 events.
[09:30:45.383] <TB1> INFO: 655360 events read in total (14663ms).
[09:30:45.487] <TB1> INFO: Expecting 655360 events.
[09:31:00.495] <TB1> INFO: 655360 events read in total (14605ms).
[09:31:00.581] <TB1> INFO: Expecting 655360 events.
[09:31:15.335] <TB1> INFO: 655360 events read in total (14351ms).
[09:31:15.422] <TB1> INFO: Test took 240117ms.
[09:31:15.523] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:31:15.781] <TB1> INFO: Expecting 655360 events.
[09:31:30.744] <TB1> INFO: 655360 events read in total (14371ms).
[09:31:30.760] <TB1> INFO: Expecting 655360 events.
[09:31:45.716] <TB1> INFO: 655360 events read in total (14553ms).
[09:31:45.742] <TB1> INFO: Expecting 655360 events.
[09:32:00.267] <TB1> INFO: 655360 events read in total (14122ms).
[09:32:00.288] <TB1> INFO: Expecting 655360 events.
[09:32:14.730] <TB1> INFO: 655360 events read in total (14039ms).
[09:32:14.755] <TB1> INFO: Expecting 655360 events.
[09:32:29.307] <TB1> INFO: 655360 events read in total (14149ms).
[09:32:29.343] <TB1> INFO: Expecting 655360 events.
[09:32:44.109] <TB1> INFO: 655360 events read in total (14363ms).
[09:32:44.144] <TB1> INFO: Expecting 655360 events.
[09:32:59.184] <TB1> INFO: 655360 events read in total (14637ms).
[09:32:59.227] <TB1> INFO: Expecting 655360 events.
[09:33:14.196] <TB1> INFO: 655360 events read in total (14566ms).
[09:33:14.263] <TB1> INFO: Expecting 655360 events.
[09:33:28.946] <TB1> INFO: 655360 events read in total (14280ms).
[09:33:29.010] <TB1> INFO: Expecting 655360 events.
[09:33:43.872] <TB1> INFO: 655360 events read in total (14458ms).
[09:33:43.927] <TB1> INFO: Expecting 655360 events.
[09:33:58.690] <TB1> INFO: 655360 events read in total (14360ms).
[09:33:58.755] <TB1> INFO: Expecting 655360 events.
[09:34:13.316] <TB1> INFO: 655360 events read in total (14158ms).
[09:34:13.386] <TB1> INFO: Expecting 655360 events.
[09:34:28.060] <TB1> INFO: 655360 events read in total (14271ms).
[09:34:28.127] <TB1> INFO: Expecting 655360 events.
[09:34:43.015] <TB1> INFO: 655360 events read in total (14485ms).
[09:34:43.091] <TB1> INFO: Expecting 655360 events.
[09:34:57.914] <TB1> INFO: 655360 events read in total (14420ms).
[09:34:57.995] <TB1> INFO: Expecting 655360 events.
[09:35:12.751] <TB1> INFO: 655360 events read in total (14353ms).
[09:35:12.838] <TB1> INFO: Test took 237315ms.
[09:35:13.004] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[09:35:13.010] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[09:35:13.016] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[09:35:13.021] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[09:35:13.027] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[09:35:13.033] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[09:35:13.039] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[09:35:13.044] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[09:35:13.050] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[09:35:13.056] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[09:35:13.062] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[09:35:13.069] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[09:35:13.075] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[09:35:13.083] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[09:35:13.089] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[09:35:13.096] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[09:35:13.102] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[09:35:13.108] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[09:35:13.114] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[09:35:13.120] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[09:35:13.126] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[09:35:13.133] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[09:35:13.138] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[09:35:13.145] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[09:35:13.151] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[09:35:13.158] <TB1> INFO: safety margin for low PH: adding 10, margin is now 30
[09:35:13.166] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[09:35:13.173] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[09:35:13.180] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[09:35:13.187] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[09:35:13.193] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[09:35:13.200] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[09:35:13.205] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[09:35:13.212] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[09:35:13.218] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[09:35:13.253] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C0.dat
[09:35:13.253] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C1.dat
[09:35:13.253] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C2.dat
[09:35:13.253] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C3.dat
[09:35:13.253] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C4.dat
[09:35:13.254] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C5.dat
[09:35:13.254] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C6.dat
[09:35:13.254] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C7.dat
[09:35:13.254] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C8.dat
[09:35:13.254] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C9.dat
[09:35:13.254] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C10.dat
[09:35:13.254] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C11.dat
[09:35:13.254] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C12.dat
[09:35:13.254] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C13.dat
[09:35:13.254] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C14.dat
[09:35:13.254] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//dacParameters35_C15.dat
[09:35:13.494] <TB1> INFO: Expecting 41600 events.
[09:35:16.672] <TB1> INFO: 41600 events read in total (2586ms).
[09:35:16.673] <TB1> INFO: Test took 3416ms.
[09:35:17.120] <TB1> INFO: Expecting 41600 events.
[09:35:20.151] <TB1> INFO: 41600 events read in total (2439ms).
[09:35:20.152] <TB1> INFO: Test took 3268ms.
[09:35:20.600] <TB1> INFO: Expecting 41600 events.
[09:35:23.757] <TB1> INFO: 41600 events read in total (2566ms).
[09:35:23.758] <TB1> INFO: Test took 3395ms.
[09:35:23.973] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:24.062] <TB1> INFO: Expecting 2560 events.
[09:35:24.954] <TB1> INFO: 2560 events read in total (300ms).
[09:35:24.954] <TB1> INFO: Test took 981ms.
[09:35:24.956] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:25.263] <TB1> INFO: Expecting 2560 events.
[09:35:26.153] <TB1> INFO: 2560 events read in total (298ms).
[09:35:26.154] <TB1> INFO: Test took 1198ms.
[09:35:26.156] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:26.462] <TB1> INFO: Expecting 2560 events.
[09:35:27.349] <TB1> INFO: 2560 events read in total (295ms).
[09:35:27.350] <TB1> INFO: Test took 1194ms.
[09:35:27.352] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:27.658] <TB1> INFO: Expecting 2560 events.
[09:35:28.546] <TB1> INFO: 2560 events read in total (297ms).
[09:35:28.546] <TB1> INFO: Test took 1194ms.
[09:35:28.548] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:28.854] <TB1> INFO: Expecting 2560 events.
[09:35:29.739] <TB1> INFO: 2560 events read in total (293ms).
[09:35:29.739] <TB1> INFO: Test took 1191ms.
[09:35:29.741] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:30.047] <TB1> INFO: Expecting 2560 events.
[09:35:30.934] <TB1> INFO: 2560 events read in total (295ms).
[09:35:30.934] <TB1> INFO: Test took 1193ms.
[09:35:30.937] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:31.243] <TB1> INFO: Expecting 2560 events.
[09:35:32.130] <TB1> INFO: 2560 events read in total (295ms).
[09:35:32.131] <TB1> INFO: Test took 1195ms.
[09:35:32.133] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:32.439] <TB1> INFO: Expecting 2560 events.
[09:35:33.326] <TB1> INFO: 2560 events read in total (295ms).
[09:35:33.326] <TB1> INFO: Test took 1193ms.
[09:35:33.329] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:33.635] <TB1> INFO: Expecting 2560 events.
[09:35:34.520] <TB1> INFO: 2560 events read in total (294ms).
[09:35:34.521] <TB1> INFO: Test took 1192ms.
[09:35:34.523] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:34.829] <TB1> INFO: Expecting 2560 events.
[09:35:35.716] <TB1> INFO: 2560 events read in total (296ms).
[09:35:35.717] <TB1> INFO: Test took 1194ms.
[09:35:35.719] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:36.025] <TB1> INFO: Expecting 2560 events.
[09:35:36.914] <TB1> INFO: 2560 events read in total (297ms).
[09:35:36.914] <TB1> INFO: Test took 1196ms.
[09:35:36.916] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:37.223] <TB1> INFO: Expecting 2560 events.
[09:35:38.106] <TB1> INFO: 2560 events read in total (291ms).
[09:35:38.106] <TB1> INFO: Test took 1190ms.
[09:35:38.109] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:38.414] <TB1> INFO: Expecting 2560 events.
[09:35:39.295] <TB1> INFO: 2560 events read in total (289ms).
[09:35:39.295] <TB1> INFO: Test took 1187ms.
[09:35:39.298] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:39.604] <TB1> INFO: Expecting 2560 events.
[09:35:40.487] <TB1> INFO: 2560 events read in total (291ms).
[09:35:40.488] <TB1> INFO: Test took 1191ms.
[09:35:40.490] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:40.795] <TB1> INFO: Expecting 2560 events.
[09:35:41.678] <TB1> INFO: 2560 events read in total (291ms).
[09:35:41.678] <TB1> INFO: Test took 1188ms.
[09:35:41.680] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:41.987] <TB1> INFO: Expecting 2560 events.
[09:35:42.870] <TB1> INFO: 2560 events read in total (291ms).
[09:35:42.870] <TB1> INFO: Test took 1190ms.
[09:35:42.872] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:43.181] <TB1> INFO: Expecting 2560 events.
[09:35:44.062] <TB1> INFO: 2560 events read in total (290ms).
[09:35:44.062] <TB1> INFO: Test took 1190ms.
[09:35:44.064] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:44.371] <TB1> INFO: Expecting 2560 events.
[09:35:45.255] <TB1> INFO: 2560 events read in total (292ms).
[09:35:45.255] <TB1> INFO: Test took 1191ms.
[09:35:45.257] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:45.564] <TB1> INFO: Expecting 2560 events.
[09:35:46.454] <TB1> INFO: 2560 events read in total (298ms).
[09:35:46.454] <TB1> INFO: Test took 1197ms.
[09:35:46.457] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:46.763] <TB1> INFO: Expecting 2560 events.
[09:35:47.645] <TB1> INFO: 2560 events read in total (291ms).
[09:35:47.645] <TB1> INFO: Test took 1189ms.
[09:35:47.647] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:47.954] <TB1> INFO: Expecting 2560 events.
[09:35:48.842] <TB1> INFO: 2560 events read in total (297ms).
[09:35:48.843] <TB1> INFO: Test took 1196ms.
[09:35:48.845] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:49.151] <TB1> INFO: Expecting 2560 events.
[09:35:50.041] <TB1> INFO: 2560 events read in total (298ms).
[09:35:50.041] <TB1> INFO: Test took 1196ms.
[09:35:50.044] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:50.349] <TB1> INFO: Expecting 2560 events.
[09:35:51.237] <TB1> INFO: 2560 events read in total (296ms).
[09:35:51.238] <TB1> INFO: Test took 1195ms.
[09:35:51.239] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:51.547] <TB1> INFO: Expecting 2560 events.
[09:35:52.429] <TB1> INFO: 2560 events read in total (291ms).
[09:35:52.429] <TB1> INFO: Test took 1190ms.
[09:35:52.431] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:52.738] <TB1> INFO: Expecting 2560 events.
[09:35:53.632] <TB1> INFO: 2560 events read in total (302ms).
[09:35:53.632] <TB1> INFO: Test took 1201ms.
[09:35:53.634] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:53.941] <TB1> INFO: Expecting 2560 events.
[09:35:54.827] <TB1> INFO: 2560 events read in total (295ms).
[09:35:54.827] <TB1> INFO: Test took 1193ms.
[09:35:54.829] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:55.135] <TB1> INFO: Expecting 2560 events.
[09:35:56.021] <TB1> INFO: 2560 events read in total (294ms).
[09:35:56.021] <TB1> INFO: Test took 1192ms.
[09:35:56.023] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:56.329] <TB1> INFO: Expecting 2560 events.
[09:35:57.221] <TB1> INFO: 2560 events read in total (300ms).
[09:35:57.221] <TB1> INFO: Test took 1198ms.
[09:35:57.223] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:57.530] <TB1> INFO: Expecting 2560 events.
[09:35:58.418] <TB1> INFO: 2560 events read in total (296ms).
[09:35:58.418] <TB1> INFO: Test took 1195ms.
[09:35:58.420] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:58.726] <TB1> INFO: Expecting 2560 events.
[09:35:59.613] <TB1> INFO: 2560 events read in total (295ms).
[09:35:59.613] <TB1> INFO: Test took 1193ms.
[09:35:59.615] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:35:59.921] <TB1> INFO: Expecting 2560 events.
[09:36:00.811] <TB1> INFO: 2560 events read in total (298ms).
[09:36:00.812] <TB1> INFO: Test took 1197ms.
[09:36:00.813] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:36:01.121] <TB1> INFO: Expecting 2560 events.
[09:36:02.008] <TB1> INFO: 2560 events read in total (295ms).
[09:36:02.008] <TB1> INFO: Test took 1195ms.
[09:36:02.470] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 661 seconds
[09:36:02.470] <TB1> INFO: PH scale (per ROC): 47 44 31 38 37 43 42 39 47 48 43 41 41 43 36 43
[09:36:02.470] <TB1> INFO: PH offset (per ROC): 99 112 105 104 99 109 108 123 99 112 81 104 102 97 97 94
[09:36:02.477] <TB1> INFO: Decoding statistics:
[09:36:02.477] <TB1> INFO: General information:
[09:36:02.477] <TB1> INFO: 16bit words read: 127884
[09:36:02.477] <TB1> INFO: valid events total: 20480
[09:36:02.477] <TB1> INFO: empty events: 17978
[09:36:02.477] <TB1> INFO: valid events with pixels: 2502
[09:36:02.477] <TB1> INFO: valid pixel hits: 2502
[09:36:02.477] <TB1> INFO: Event errors: 0
[09:36:02.477] <TB1> INFO: start marker: 0
[09:36:02.477] <TB1> INFO: stop marker: 0
[09:36:02.477] <TB1> INFO: overflow: 0
[09:36:02.477] <TB1> INFO: invalid 5bit words: 0
[09:36:02.477] <TB1> INFO: invalid XOR eye diagram: 0
[09:36:02.477] <TB1> INFO: frame (failed synchr.): 0
[09:36:02.477] <TB1> INFO: idle data (no TBM trl): 0
[09:36:02.478] <TB1> INFO: no data (only TBM hdr): 0
[09:36:02.478] <TB1> INFO: TBM errors: 0
[09:36:02.478] <TB1> INFO: flawed TBM headers: 0
[09:36:02.478] <TB1> INFO: flawed TBM trailers: 0
[09:36:02.478] <TB1> INFO: event ID mismatches: 0
[09:36:02.478] <TB1> INFO: ROC errors: 0
[09:36:02.478] <TB1> INFO: missing ROC header(s): 0
[09:36:02.478] <TB1> INFO: misplaced readback start: 0
[09:36:02.478] <TB1> INFO: Pixel decoding errors: 0
[09:36:02.478] <TB1> INFO: pixel data incomplete: 0
[09:36:02.478] <TB1> INFO: pixel address: 0
[09:36:02.478] <TB1> INFO: pulse height fill bit: 0
[09:36:02.478] <TB1> INFO: buffer corruption: 0
[09:36:02.636] <TB1> INFO: ######################################################################
[09:36:02.637] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[09:36:02.637] <TB1> INFO: ######################################################################
[09:36:02.651] <TB1> INFO: scanning low vcal = 10
[09:36:02.890] <TB1> INFO: Expecting 41600 events.
[09:36:06.481] <TB1> INFO: 41600 events read in total (3000ms).
[09:36:06.481] <TB1> INFO: Test took 3830ms.
[09:36:06.483] <TB1> INFO: scanning low vcal = 20
[09:36:06.797] <TB1> INFO: Expecting 41600 events.
[09:36:10.428] <TB1> INFO: 41600 events read in total (3039ms).
[09:36:10.428] <TB1> INFO: Test took 3945ms.
[09:36:10.430] <TB1> INFO: scanning low vcal = 30
[09:36:10.724] <TB1> INFO: Expecting 41600 events.
[09:36:14.378] <TB1> INFO: 41600 events read in total (3062ms).
[09:36:14.379] <TB1> INFO: Test took 3949ms.
[09:36:14.381] <TB1> INFO: scanning low vcal = 40
[09:36:14.658] <TB1> INFO: Expecting 41600 events.
[09:36:18.717] <TB1> INFO: 41600 events read in total (3467ms).
[09:36:18.719] <TB1> INFO: Test took 4338ms.
[09:36:18.722] <TB1> INFO: scanning low vcal = 50
[09:36:19.039] <TB1> INFO: Expecting 41600 events.
[09:36:23.049] <TB1> INFO: 41600 events read in total (3418ms).
[09:36:23.049] <TB1> INFO: Test took 4327ms.
[09:36:23.053] <TB1> INFO: scanning low vcal = 60
[09:36:23.329] <TB1> INFO: Expecting 41600 events.
[09:36:27.340] <TB1> INFO: 41600 events read in total (3419ms).
[09:36:27.341] <TB1> INFO: Test took 4288ms.
[09:36:27.344] <TB1> INFO: scanning low vcal = 70
[09:36:27.621] <TB1> INFO: Expecting 41600 events.
[09:36:31.726] <TB1> INFO: 41600 events read in total (3514ms).
[09:36:31.727] <TB1> INFO: Test took 4383ms.
[09:36:31.731] <TB1> INFO: scanning low vcal = 80
[09:36:32.007] <TB1> INFO: Expecting 41600 events.
[09:36:36.016] <TB1> INFO: 41600 events read in total (3417ms).
[09:36:36.017] <TB1> INFO: Test took 4286ms.
[09:36:36.020] <TB1> INFO: scanning low vcal = 90
[09:36:36.297] <TB1> INFO: Expecting 41600 events.
[09:36:40.285] <TB1> INFO: 41600 events read in total (3396ms).
[09:36:40.286] <TB1> INFO: Test took 4266ms.
[09:36:40.290] <TB1> INFO: scanning low vcal = 100
[09:36:40.566] <TB1> INFO: Expecting 41600 events.
[09:36:44.626] <TB1> INFO: 41600 events read in total (3468ms).
[09:36:44.627] <TB1> INFO: Test took 4337ms.
[09:36:44.631] <TB1> INFO: scanning low vcal = 110
[09:36:44.945] <TB1> INFO: Expecting 41600 events.
[09:36:48.933] <TB1> INFO: 41600 events read in total (3397ms).
[09:36:48.934] <TB1> INFO: Test took 4303ms.
[09:36:48.937] <TB1> INFO: scanning low vcal = 120
[09:36:49.213] <TB1> INFO: Expecting 41600 events.
[09:36:53.258] <TB1> INFO: 41600 events read in total (3453ms).
[09:36:53.259] <TB1> INFO: Test took 4322ms.
[09:36:53.262] <TB1> INFO: scanning low vcal = 130
[09:36:53.579] <TB1> INFO: Expecting 41600 events.
[09:36:57.589] <TB1> INFO: 41600 events read in total (3418ms).
[09:36:57.590] <TB1> INFO: Test took 4328ms.
[09:36:57.593] <TB1> INFO: scanning low vcal = 140
[09:36:57.870] <TB1> INFO: Expecting 41600 events.
[09:37:01.901] <TB1> INFO: 41600 events read in total (3440ms).
[09:37:01.902] <TB1> INFO: Test took 4309ms.
[09:37:01.905] <TB1> INFO: scanning low vcal = 150
[09:37:02.181] <TB1> INFO: Expecting 41600 events.
[09:37:06.198] <TB1> INFO: 41600 events read in total (3425ms).
[09:37:06.199] <TB1> INFO: Test took 4294ms.
[09:37:06.203] <TB1> INFO: scanning low vcal = 160
[09:37:06.517] <TB1> INFO: Expecting 41600 events.
[09:37:10.528] <TB1> INFO: 41600 events read in total (3419ms).
[09:37:10.529] <TB1> INFO: Test took 4326ms.
[09:37:10.532] <TB1> INFO: scanning low vcal = 170
[09:37:10.808] <TB1> INFO: Expecting 41600 events.
[09:37:14.809] <TB1> INFO: 41600 events read in total (3409ms).
[09:37:14.810] <TB1> INFO: Test took 4278ms.
[09:37:14.815] <TB1> INFO: scanning low vcal = 180
[09:37:15.090] <TB1> INFO: Expecting 41600 events.
[09:37:19.148] <TB1> INFO: 41600 events read in total (3467ms).
[09:37:19.149] <TB1> INFO: Test took 4333ms.
[09:37:19.152] <TB1> INFO: scanning low vcal = 190
[09:37:19.470] <TB1> INFO: Expecting 41600 events.
[09:37:23.500] <TB1> INFO: 41600 events read in total (3439ms).
[09:37:23.501] <TB1> INFO: Test took 4349ms.
[09:37:23.505] <TB1> INFO: scanning low vcal = 200
[09:37:23.781] <TB1> INFO: Expecting 41600 events.
[09:37:27.790] <TB1> INFO: 41600 events read in total (3417ms).
[09:37:27.791] <TB1> INFO: Test took 4286ms.
[09:37:27.794] <TB1> INFO: scanning low vcal = 210
[09:37:28.070] <TB1> INFO: Expecting 41600 events.
[09:37:32.153] <TB1> INFO: 41600 events read in total (3491ms).
[09:37:32.154] <TB1> INFO: Test took 4360ms.
[09:37:32.158] <TB1> INFO: scanning low vcal = 220
[09:37:32.434] <TB1> INFO: Expecting 41600 events.
[09:37:36.397] <TB1> INFO: 41600 events read in total (3371ms).
[09:37:36.398] <TB1> INFO: Test took 4240ms.
[09:37:36.401] <TB1> INFO: scanning low vcal = 230
[09:37:36.677] <TB1> INFO: Expecting 41600 events.
[09:37:40.687] <TB1> INFO: 41600 events read in total (3418ms).
[09:37:40.688] <TB1> INFO: Test took 4287ms.
[09:37:40.691] <TB1> INFO: scanning low vcal = 240
[09:37:41.008] <TB1> INFO: Expecting 41600 events.
[09:37:45.056] <TB1> INFO: 41600 events read in total (3456ms).
[09:37:45.057] <TB1> INFO: Test took 4366ms.
[09:37:45.060] <TB1> INFO: scanning low vcal = 250
[09:37:45.375] <TB1> INFO: Expecting 41600 events.
[09:37:49.336] <TB1> INFO: 41600 events read in total (3369ms).
[09:37:49.337] <TB1> INFO: Test took 4277ms.
[09:37:49.341] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[09:37:49.617] <TB1> INFO: Expecting 41600 events.
[09:37:53.579] <TB1> INFO: 41600 events read in total (3370ms).
[09:37:53.580] <TB1> INFO: Test took 4239ms.
[09:37:53.583] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[09:37:53.860] <TB1> INFO: Expecting 41600 events.
[09:37:57.810] <TB1> INFO: 41600 events read in total (3358ms).
[09:37:57.810] <TB1> INFO: Test took 4227ms.
[09:37:57.814] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[09:37:58.090] <TB1> INFO: Expecting 41600 events.
[09:38:02.039] <TB1> INFO: 41600 events read in total (3357ms).
[09:38:02.040] <TB1> INFO: Test took 4226ms.
[09:38:02.044] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[09:38:02.320] <TB1> INFO: Expecting 41600 events.
[09:38:06.267] <TB1> INFO: 41600 events read in total (3355ms).
[09:38:06.268] <TB1> INFO: Test took 4224ms.
[09:38:06.271] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[09:38:06.548] <TB1> INFO: Expecting 41600 events.
[09:38:10.500] <TB1> INFO: 41600 events read in total (3360ms).
[09:38:10.502] <TB1> INFO: Test took 4231ms.
[09:38:10.903] <TB1> INFO: PixTestGainPedestal::measure() done
[09:38:42.768] <TB1> INFO: PixTestGainPedestal::fit() done
[09:38:42.768] <TB1> INFO: non-linearity mean: 0.948 0.938 0.923 0.929 0.938 0.928 0.929 0.933 0.969 0.972 0.949 0.935 0.936 0.940 0.936 0.969
[09:38:42.768] <TB1> INFO: non-linearity RMS: 0.064 0.053 0.152 0.107 0.178 0.100 0.103 0.079 0.026 0.019 0.064 0.083 0.126 0.081 0.108 0.025
[09:38:42.768] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr35_C0.dat
[09:38:42.782] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr35_C1.dat
[09:38:42.796] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr35_C2.dat
[09:38:42.810] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr35_C3.dat
[09:38:42.823] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr35_C4.dat
[09:38:42.837] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr35_C5.dat
[09:38:42.851] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr35_C6.dat
[09:38:42.865] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr35_C7.dat
[09:38:42.878] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr35_C8.dat
[09:38:42.892] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr35_C9.dat
[09:38:42.905] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr35_C10.dat
[09:38:42.919] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr35_C11.dat
[09:38:42.932] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr35_C12.dat
[09:38:42.946] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr35_C13.dat
[09:38:42.960] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr35_C14.dat
[09:38:42.973] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1061_FullQualification_2016-10-25_08h01m_1477375284//001_Fulltest_p17//phCalibrationFitErr35_C15.dat
[09:38:42.987] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 160 seconds
[09:38:42.987] <TB1> INFO: Decoding statistics:
[09:38:42.987] <TB1> INFO: General information:
[09:38:42.987] <TB1> INFO: 16bit words read: 3273070
[09:38:42.987] <TB1> INFO: valid events total: 332800
[09:38:42.987] <TB1> INFO: empty events: 2990
[09:38:42.987] <TB1> INFO: valid events with pixels: 329810
[09:38:42.987] <TB1> INFO: valid pixel hits: 638135
[09:38:42.987] <TB1> INFO: Event errors: 0
[09:38:42.987] <TB1> INFO: start marker: 0
[09:38:42.987] <TB1> INFO: stop marker: 0
[09:38:42.987] <TB1> INFO: overflow: 0
[09:38:42.987] <TB1> INFO: invalid 5bit words: 0
[09:38:42.987] <TB1> INFO: invalid XOR eye diagram: 0
[09:38:42.987] <TB1> INFO: frame (failed synchr.): 0
[09:38:42.987] <TB1> INFO: idle data (no TBM trl): 0
[09:38:42.987] <TB1> INFO: no data (only TBM hdr): 0
[09:38:42.987] <TB1> INFO: TBM errors: 0
[09:38:42.987] <TB1> INFO: flawed TBM headers: 0
[09:38:42.987] <TB1> INFO: flawed TBM trailers: 0
[09:38:42.987] <TB1> INFO: event ID mismatches: 0
[09:38:42.987] <TB1> INFO: ROC errors: 0
[09:38:42.987] <TB1> INFO: missing ROC header(s): 0
[09:38:42.987] <TB1> INFO: misplaced readback start: 0
[09:38:42.987] <TB1> INFO: Pixel decoding errors: 0
[09:38:42.987] <TB1> INFO: pixel data incomplete: 0
[09:38:42.987] <TB1> INFO: pixel address: 0
[09:38:42.987] <TB1> INFO: pulse height fill bit: 0
[09:38:42.987] <TB1> INFO: buffer corruption: 0
[09:38:42.003] <TB1> INFO: Decoding statistics:
[09:38:42.003] <TB1> INFO: General information:
[09:38:42.003] <TB1> INFO: 16bit words read: 3402490
[09:38:42.003] <TB1> INFO: valid events total: 353536
[09:38:42.003] <TB1> INFO: empty events: 21224
[09:38:42.003] <TB1> INFO: valid events with pixels: 332312
[09:38:42.003] <TB1> INFO: valid pixel hits: 640637
[09:38:42.003] <TB1> INFO: Event errors: 0
[09:38:42.003] <TB1> INFO: start marker: 0
[09:38:42.003] <TB1> INFO: stop marker: 0
[09:38:42.003] <TB1> INFO: overflow: 0
[09:38:42.003] <TB1> INFO: invalid 5bit words: 0
[09:38:42.003] <TB1> INFO: invalid XOR eye diagram: 0
[09:38:42.003] <TB1> INFO: frame (failed synchr.): 0
[09:38:42.003] <TB1> INFO: idle data (no TBM trl): 0
[09:38:42.003] <TB1> INFO: no data (only TBM hdr): 0
[09:38:42.003] <TB1> INFO: TBM errors: 0
[09:38:42.003] <TB1> INFO: flawed TBM headers: 0
[09:38:42.003] <TB1> INFO: flawed TBM trailers: 0
[09:38:42.003] <TB1> INFO: event ID mismatches: 0
[09:38:42.003] <TB1> INFO: ROC errors: 0
[09:38:42.003] <TB1> INFO: missing ROC header(s): 0
[09:38:42.003] <TB1> INFO: misplaced readback start: 0
[09:38:42.003] <TB1> INFO: Pixel decoding errors: 0
[09:38:42.003] <TB1> INFO: pixel data incomplete: 0
[09:38:42.003] <TB1> INFO: pixel address: 0
[09:38:42.003] <TB1> INFO: pulse height fill bit: 0
[09:38:42.003] <TB1> INFO: buffer corruption: 0
[09:38:43.003] <TB1> INFO: enter test to run
[09:38:43.003] <TB1> INFO: test: exit no parameter change
[09:38:43.116] <TB1> QUIET: Connection to board 154 closed.
[09:38:43.116] <TB1> INFO: pXar: this is the end, my friend