[09:38:55.476] <TB1> INFO: *** Welcome to pxar ***
[09:38:55.476] <TB1> INFO: *** Today: 2016/11/09
[09:38:55.482] <TB1> INFO: *** Version: c8ba-dirty
[09:38:55.482] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C15.dat
[09:38:55.483] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//tbmParameters_C1b.dat
[09:38:55.483] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//defaultMaskFile.dat
[09:38:55.483] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters_C15.dat
[09:38:55.586] <TB1> INFO: clk: 4
[09:38:55.586] <TB1> INFO: ctr: 4
[09:38:55.586] <TB1> INFO: sda: 19
[09:38:55.586] <TB1> INFO: tin: 9
[09:38:55.586] <TB1> INFO: level: 15
[09:38:55.586] <TB1> INFO: triggerdelay: 0
[09:38:55.586] <TB1> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[09:38:55.586] <TB1> INFO: Log level: INFO
[09:38:55.597] <TB1> INFO: Found DTB DTB_WXC03A
[09:38:55.608] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[09:38:55.610] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
------------------------------------------------------
[09:38:55.612] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[09:38:57.166] <TB1> INFO: DUT info:
[09:38:57.166] <TB1> INFO: The DUT currently contains the following objects:
[09:38:57.166] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[09:38:57.166] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:38:57.166] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:38:57.166] <TB1> INFO: TBM Core alpha (2): 7 registers set
[09:38:57.166] <TB1> INFO: TBM Core beta (3): 7 registers set
[09:38:57.166] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[09:38:57.166] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[09:38:57.166] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[09:38:57.166] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[09:38:57.166] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[09:38:57.166] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[09:38:57.166] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[09:38:57.166] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[09:38:57.166] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[09:38:57.166] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[09:38:57.167] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[09:38:57.167] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[09:38:57.167] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[09:38:57.167] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[09:38:57.167] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[09:38:57.167] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[09:38:57.167] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[09:38:57.567] <TB1> INFO: enter 'restricted' command line mode
[09:38:57.567] <TB1> INFO: enter test to run
[09:38:57.568] <TB1> INFO: test: pretest no parameter change
[09:38:57.568] <TB1> INFO: running: pretest
[09:38:57.573] <TB1> INFO: ######################################################################
[09:38:57.573] <TB1> INFO: PixTestPretest::doTest()
[09:38:57.573] <TB1> INFO: ######################################################################
[09:38:57.574] <TB1> INFO: ----------------------------------------------------------------------
[09:38:57.574] <TB1> INFO: PixTestPretest::programROC()
[09:38:57.574] <TB1> INFO: ----------------------------------------------------------------------
[09:39:15.590] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[09:39:15.590] <TB1> INFO: IA differences per ROC: 18.5 20.1 22.5 18.5 20.1 17.7 17.7 19.3 18.5 20.1 18.5 16.9 21.7 18.5 19.3 17.7
[09:39:15.657] <TB1> INFO: ----------------------------------------------------------------------
[09:39:15.657] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[09:39:15.657] <TB1> INFO: ----------------------------------------------------------------------
[09:39:36.902] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 379.4 mA = 23.7125 mA/ROC
[09:39:36.902] <TB1> INFO: i(loss) [mA/ROC]: 18.5 19.3 20.1 20.1 20.1 20.9 20.1 20.1 19.3 19.3 20.1 20.1 20.1 20.1 19.3 20.1
[09:39:36.930] <TB1> INFO: ----------------------------------------------------------------------
[09:39:36.930] <TB1> INFO: PixTestPretest::findTiming()
[09:39:36.930] <TB1> INFO: ----------------------------------------------------------------------
[09:39:36.931] <TB1> INFO: PixTestCmd::init()

[09:40:07.902] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 4, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[09:40:07.902] <TB1> INFO: (success/tries = 100/100), width = 3
[09:40:09.407] <TB1> INFO: ----------------------------------------------------------------------
[09:40:09.407] <TB1> INFO: PixTestPretest::findWorkingPixel()
[09:40:09.407] <TB1> INFO: ----------------------------------------------------------------------
[09:40:09.502] <TB1> INFO: Expecting 231680 events.
[09:40:19.379] <TB1> INFO: 231680 events read in total (9286ms).
[09:40:19.389] <TB1> INFO: Test took 9978ms.
[09:40:19.633] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[09:40:19.665] <TB1> INFO: ----------------------------------------------------------------------
[09:40:19.665] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[09:40:19.665] <TB1> INFO: ----------------------------------------------------------------------
[09:40:19.760] <TB1> INFO: Expecting 231680 events.
[09:40:29.631] <TB1> INFO: 231680 events read in total (9280ms).
[09:40:29.642] <TB1> INFO: Test took 9971ms.
[09:40:29.894] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[09:40:29.895] <TB1> INFO: CalDel: 100 99 103 96 102 103 101 123 108 98 113 111 105 91 94 80
[09:40:29.895] <TB1> INFO: VthrComp: 51 51 51 52 52 54 51 51 53 51 52 51 52 51 51 51
[09:40:29.901] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C0.dat
[09:40:29.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C1.dat
[09:40:29.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C2.dat
[09:40:29.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C3.dat
[09:40:29.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C4.dat
[09:40:29.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C5.dat
[09:40:29.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C6.dat
[09:40:29.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C7.dat
[09:40:29.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C8.dat
[09:40:29.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C9.dat
[09:40:29.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C10.dat
[09:40:29.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C11.dat
[09:40:29.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C12.dat
[09:40:29.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C13.dat
[09:40:29.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C14.dat
[09:40:29.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters_C15.dat
[09:40:29.903] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//tbmParameters_C0a.dat
[09:40:29.903] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//tbmParameters_C0b.dat
[09:40:29.904] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//tbmParameters_C1a.dat
[09:40:29.904] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//tbmParameters_C1b.dat
[09:40:29.904] <TB1> INFO: PixTestPretest::doTest() done, duration: 92 seconds
[09:40:29.955] <TB1> INFO: enter test to run
[09:40:29.955] <TB1> INFO: test: FullTest no parameter change
[09:40:29.955] <TB1> INFO: running: fulltest
[09:40:29.955] <TB1> INFO: ######################################################################
[09:40:29.955] <TB1> INFO: PixTestFullTest::doTest()
[09:40:29.955] <TB1> INFO: ######################################################################
[09:40:29.957] <TB1> INFO: ######################################################################
[09:40:29.957] <TB1> INFO: PixTestAlive::doTest()
[09:40:29.957] <TB1> INFO: ######################################################################
[09:40:29.958] <TB1> INFO: ----------------------------------------------------------------------
[09:40:29.958] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:40:29.958] <TB1> INFO: ----------------------------------------------------------------------
[09:40:30.249] <TB1> INFO: Expecting 41600 events.
[09:40:33.797] <TB1> INFO: 41600 events read in total (2957ms).
[09:40:33.798] <TB1> INFO: Test took 3839ms.
[09:40:34.025] <TB1> INFO: PixTestAlive::aliveTest() done
[09:40:34.025] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:40:34.026] <TB1> INFO: ----------------------------------------------------------------------
[09:40:34.026] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:40:34.026] <TB1> INFO: ----------------------------------------------------------------------
[09:40:34.263] <TB1> INFO: Expecting 41600 events.
[09:40:37.195] <TB1> INFO: 41600 events read in total (2340ms).
[09:40:37.195] <TB1> INFO: Test took 3167ms.
[09:40:37.195] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[09:40:37.432] <TB1> INFO: PixTestAlive::maskTest() done
[09:40:37.432] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:40:37.433] <TB1> INFO: ----------------------------------------------------------------------
[09:40:37.433] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:40:37.433] <TB1> INFO: ----------------------------------------------------------------------
[09:40:37.672] <TB1> INFO: Expecting 41600 events.
[09:40:41.196] <TB1> INFO: 41600 events read in total (2933ms).
[09:40:41.196] <TB1> INFO: Test took 3762ms.
[09:40:41.424] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[09:40:41.424] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:40:41.424] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[09:40:41.424] <TB1> INFO: Decoding statistics:
[09:40:41.424] <TB1> INFO: General information:
[09:40:41.424] <TB1> INFO: 16bit words read: 0
[09:40:41.424] <TB1> INFO: valid events total: 0
[09:40:41.424] <TB1> INFO: empty events: 0
[09:40:41.424] <TB1> INFO: valid events with pixels: 0
[09:40:41.424] <TB1> INFO: valid pixel hits: 0
[09:40:41.424] <TB1> INFO: Event errors: 0
[09:40:41.424] <TB1> INFO: start marker: 0
[09:40:41.424] <TB1> INFO: stop marker: 0
[09:40:41.424] <TB1> INFO: overflow: 0
[09:40:41.424] <TB1> INFO: invalid 5bit words: 0
[09:40:41.424] <TB1> INFO: invalid XOR eye diagram: 0
[09:40:41.424] <TB1> INFO: frame (failed synchr.): 0
[09:40:41.424] <TB1> INFO: idle data (no TBM trl): 0
[09:40:41.424] <TB1> INFO: no data (only TBM hdr): 0
[09:40:41.424] <TB1> INFO: TBM errors: 0
[09:40:41.424] <TB1> INFO: flawed TBM headers: 0
[09:40:41.424] <TB1> INFO: flawed TBM trailers: 0
[09:40:41.424] <TB1> INFO: event ID mismatches: 0
[09:40:41.425] <TB1> INFO: ROC errors: 0
[09:40:41.425] <TB1> INFO: missing ROC header(s): 0
[09:40:41.425] <TB1> INFO: misplaced readback start: 0
[09:40:41.425] <TB1> INFO: Pixel decoding errors: 0
[09:40:41.425] <TB1> INFO: pixel data incomplete: 0
[09:40:41.425] <TB1> INFO: pixel address: 0
[09:40:41.425] <TB1> INFO: pulse height fill bit: 0
[09:40:41.425] <TB1> INFO: buffer corruption: 0
[09:40:41.430] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C15.dat
[09:40:41.430] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr_C15.dat

[09:40:41.430] <TB1> INFO: ######################################################################
[09:40:41.431] <TB1> INFO: PixTestReadback::doTest()
[09:40:41.431] <TB1> INFO: ######################################################################
[09:40:41.431] <TB1> INFO: ----------------------------------------------------------------------
[09:40:41.431] <TB1> INFO: PixTestReadback::CalibrateVd()
[09:40:41.431] <TB1> INFO: ----------------------------------------------------------------------
[09:40:51.351] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C0.dat
[09:40:51.352] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C1.dat
[09:40:51.352] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C2.dat
[09:40:51.352] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C3.dat
[09:40:51.352] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C4.dat
[09:40:51.352] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C5.dat
[09:40:51.352] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C6.dat
[09:40:51.352] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C7.dat
[09:40:51.352] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C8.dat
[09:40:51.352] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C9.dat
[09:40:51.352] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C10.dat
[09:40:51.352] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C11.dat
[09:40:51.352] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C12.dat
[09:40:51.352] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C13.dat
[09:40:51.352] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C14.dat
[09:40:51.352] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C15.dat
[09:40:51.382] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[09:40:51.382] <TB1> INFO: ----------------------------------------------------------------------
[09:40:51.382] <TB1> INFO: PixTestReadback::CalibrateVa()
[09:40:51.382] <TB1> INFO: ----------------------------------------------------------------------
[09:41:01.273] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C0.dat
[09:41:01.273] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C1.dat
[09:41:01.273] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C2.dat
[09:41:01.273] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C3.dat
[09:41:01.273] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C4.dat
[09:41:01.273] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C5.dat
[09:41:01.274] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C6.dat
[09:41:01.274] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C7.dat
[09:41:01.274] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C8.dat
[09:41:01.274] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C9.dat
[09:41:01.274] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C10.dat
[09:41:01.274] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C11.dat
[09:41:01.274] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C12.dat
[09:41:01.274] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C13.dat
[09:41:01.274] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C14.dat
[09:41:01.274] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C15.dat
[09:41:01.304] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[09:41:01.304] <TB1> INFO: ----------------------------------------------------------------------
[09:41:01.304] <TB1> INFO: PixTestReadback::readbackVbg()
[09:41:01.304] <TB1> INFO: ----------------------------------------------------------------------
[09:41:08.947] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[09:41:08.947] <TB1> INFO: ----------------------------------------------------------------------
[09:41:08.947] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[09:41:08.947] <TB1> INFO: ----------------------------------------------------------------------
[09:41:08.947] <TB1> INFO: Vbg will be calibrated using Vd calibration
[09:41:08.947] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 152.9calibrated Vbg = 1.18304 :::*/*/*/*/
[09:41:08.947] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 167.5calibrated Vbg = 1.17898 :::*/*/*/*/
[09:41:08.947] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 151.5calibrated Vbg = 1.17674 :::*/*/*/*/
[09:41:08.947] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 155calibrated Vbg = 1.17223 :::*/*/*/*/
[09:41:08.947] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 155.6calibrated Vbg = 1.17155 :::*/*/*/*/
[09:41:08.947] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 153.7calibrated Vbg = 1.18165 :::*/*/*/*/
[09:41:08.947] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 153.1calibrated Vbg = 1.17948 :::*/*/*/*/
[09:41:08.947] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 155.9calibrated Vbg = 1.18629 :::*/*/*/*/
[09:41:08.947] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 152.6calibrated Vbg = 1.17897 :::*/*/*/*/
[09:41:08.947] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 154.8calibrated Vbg = 1.17164 :::*/*/*/*/
[09:41:08.947] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 159.3calibrated Vbg = 1.17354 :::*/*/*/*/
[09:41:08.947] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 155.2calibrated Vbg = 1.17504 :::*/*/*/*/
[09:41:08.947] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 152.4calibrated Vbg = 1.17626 :::*/*/*/*/
[09:41:08.947] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 153.2calibrated Vbg = 1.17878 :::*/*/*/*/
[09:41:08.947] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 162.8calibrated Vbg = 1.17776 :::*/*/*/*/
[09:41:08.947] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 155.8calibrated Vbg = 1.18216 :::*/*/*/*/
[09:41:08.951] <TB1> INFO: ----------------------------------------------------------------------
[09:41:08.951] <TB1> INFO: PixTestReadback::CalibrateIa()
[09:41:08.951] <TB1> INFO: ----------------------------------------------------------------------
[09:43:49.323] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C0.dat
[09:43:49.324] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C1.dat
[09:43:49.324] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C2.dat
[09:43:49.324] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C3.dat
[09:43:49.324] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C4.dat
[09:43:49.324] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C5.dat
[09:43:49.324] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C6.dat
[09:43:49.324] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C7.dat
[09:43:49.324] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C8.dat
[09:43:49.324] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C9.dat
[09:43:49.324] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C10.dat
[09:43:49.324] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C11.dat
[09:43:49.324] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C12.dat
[09:43:49.324] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C13.dat
[09:43:49.324] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C14.dat
[09:43:49.324] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//readbackCal_C15.dat
[09:43:49.352] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[09:43:49.353] <TB1> INFO: PixTestReadback::doTest() done
[09:43:49.353] <TB1> INFO: Decoding statistics:
[09:43:49.353] <TB1> INFO: General information:
[09:43:49.353] <TB1> INFO: 16bit words read: 1536
[09:43:49.353] <TB1> INFO: valid events total: 256
[09:43:49.353] <TB1> INFO: empty events: 256
[09:43:49.353] <TB1> INFO: valid events with pixels: 0
[09:43:49.353] <TB1> INFO: valid pixel hits: 0
[09:43:49.353] <TB1> INFO: Event errors: 0
[09:43:49.353] <TB1> INFO: start marker: 0
[09:43:49.353] <TB1> INFO: stop marker: 0
[09:43:49.353] <TB1> INFO: overflow: 0
[09:43:49.353] <TB1> INFO: invalid 5bit words: 0
[09:43:49.353] <TB1> INFO: invalid XOR eye diagram: 0
[09:43:49.353] <TB1> INFO: frame (failed synchr.): 0
[09:43:49.353] <TB1> INFO: idle data (no TBM trl): 0
[09:43:49.353] <TB1> INFO: no data (only TBM hdr): 0
[09:43:49.353] <TB1> INFO: TBM errors: 0
[09:43:49.353] <TB1> INFO: flawed TBM headers: 0
[09:43:49.353] <TB1> INFO: flawed TBM trailers: 0
[09:43:49.353] <TB1> INFO: event ID mismatches: 0
[09:43:49.353] <TB1> INFO: ROC errors: 0
[09:43:49.353] <TB1> INFO: missing ROC header(s): 0
[09:43:49.353] <TB1> INFO: misplaced readback start: 0
[09:43:49.353] <TB1> INFO: Pixel decoding errors: 0
[09:43:49.353] <TB1> INFO: pixel data incomplete: 0
[09:43:49.353] <TB1> INFO: pixel address: 0
[09:43:49.353] <TB1> INFO: pulse height fill bit: 0
[09:43:49.353] <TB1> INFO: buffer corruption: 0
[09:43:49.401] <TB1> INFO: ######################################################################
[09:43:49.401] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[09:43:49.401] <TB1> INFO: ######################################################################
[09:43:49.404] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[09:43:49.436] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[09:43:49.436] <TB1> INFO: run 1 of 1
[09:43:49.675] <TB1> INFO: Expecting 3120000 events.
[09:44:21.730] <TB1> INFO: 664960 events read in total (31463ms).











[09:44:52.804] <TB1> INFO: 1325775 events read in total (62537ms).











[09:45:23.656] <TB1> INFO: 1985580 events read in total (93389ms).











[09:45:54.837] <TB1> INFO: 2647925 events read in total (124570ms).











[09:46:17.819] <TB1> INFO: 3120000 events read in total (147552ms).
[09:46:17.896] <TB1> INFO: Test took 148460ms.
[09:46:47.929] <TB1> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 178 seconds
[09:46:47.929] <TB1> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:46:47.929] <TB1> INFO: separation cut (per ROC): 105 108 111 111 109 108 94 100 104 102 101 106 108 103 103 116
[09:46:47.929] <TB1> INFO: Decoding statistics:
[09:46:47.929] <TB1> INFO: General information:
[09:46:47.929] <TB1> INFO: 16bit words read: 0
[09:46:47.929] <TB1> INFO: valid events total: 0
[09:46:47.929] <TB1> INFO: empty events: 0
[09:46:47.929] <TB1> INFO: valid events with pixels: 0
[09:46:47.929] <TB1> INFO: valid pixel hits: 0
[09:46:47.929] <TB1> INFO: Event errors: 0
[09:46:47.929] <TB1> INFO: start marker: 0
[09:46:47.929] <TB1> INFO: stop marker: 0
[09:46:47.929] <TB1> INFO: overflow: 0
[09:46:47.929] <TB1> INFO: invalid 5bit words: 0
[09:46:47.929] <TB1> INFO: invalid XOR eye diagram: 0
[09:46:47.929] <TB1> INFO: frame (failed synchr.): 0
[09:46:47.929] <TB1> INFO: idle data (no TBM trl): 0
[09:46:47.929] <TB1> INFO: no data (only TBM hdr): 0
[09:46:47.929] <TB1> INFO: TBM errors: 0
[09:46:47.929] <TB1> INFO: flawed TBM headers: 0
[09:46:47.929] <TB1> INFO: flawed TBM trailers: 0
[09:46:47.929] <TB1> INFO: event ID mismatches: 0
[09:46:47.929] <TB1> INFO: ROC errors: 0
[09:46:47.929] <TB1> INFO: missing ROC header(s): 0
[09:46:47.929] <TB1> INFO: misplaced readback start: 0
[09:46:47.929] <TB1> INFO: Pixel decoding errors: 0
[09:46:47.929] <TB1> INFO: pixel data incomplete: 0
[09:46:47.929] <TB1> INFO: pixel address: 0
[09:46:47.929] <TB1> INFO: pulse height fill bit: 0
[09:46:47.929] <TB1> INFO: buffer corruption: 0
[09:46:47.966] <TB1> INFO: ######################################################################
[09:46:47.966] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[09:46:47.966] <TB1> INFO: ######################################################################
[09:46:47.966] <TB1> INFO: ----------------------------------------------------------------------
[09:46:47.966] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[09:46:47.966] <TB1> INFO: ----------------------------------------------------------------------
[09:46:47.966] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[09:46:47.982] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[09:46:47.982] <TB1> INFO: run 1 of 1
[09:46:48.221] <TB1> INFO: Expecting 36608000 events.
[09:47:12.837] <TB1> INFO: 691650 events read in total (24022ms).
[09:47:36.439] <TB1> INFO: 1369300 events read in total (47624ms).
[09:47:59.928] <TB1> INFO: 2044650 events read in total (71113ms).
[09:48:24.344] <TB1> INFO: 2721400 events read in total (95529ms).
[09:48:48.279] <TB1> INFO: 3397950 events read in total (119464ms).
[09:49:12.080] <TB1> INFO: 4073950 events read in total (143265ms).
[09:49:36.470] <TB1> INFO: 4750600 events read in total (167655ms).
[09:50:00.959] <TB1> INFO: 5427300 events read in total (192144ms).
[09:50:24.537] <TB1> INFO: 6101600 events read in total (215722ms).
[09:50:48.275] <TB1> INFO: 6775200 events read in total (239460ms).
[09:51:12.377] <TB1> INFO: 7450500 events read in total (263562ms).
[09:51:36.340] <TB1> INFO: 8126150 events read in total (287525ms).
[09:52:00.141] <TB1> INFO: 8799950 events read in total (311326ms).
[09:52:24.353] <TB1> INFO: 9475350 events read in total (335538ms).
[09:52:48.645] <TB1> INFO: 10150700 events read in total (359830ms).
[09:53:12.397] <TB1> INFO: 10824500 events read in total (383582ms).
[09:53:36.061] <TB1> INFO: 11498150 events read in total (407246ms).
[09:54:00.040] <TB1> INFO: 12171500 events read in total (431225ms).
[09:54:24.121] <TB1> INFO: 12843750 events read in total (455306ms).
[09:54:47.609] <TB1> INFO: 13516700 events read in total (478794ms).
[09:55:11.528] <TB1> INFO: 14188900 events read in total (502713ms).
[09:55:35.594] <TB1> INFO: 14861400 events read in total (526779ms).
[09:55:59.162] <TB1> INFO: 15532050 events read in total (550347ms).
[09:56:22.749] <TB1> INFO: 16205700 events read in total (573934ms).
[09:56:46.325] <TB1> INFO: 16875600 events read in total (597510ms).
[09:57:09.911] <TB1> INFO: 17546500 events read in total (621096ms).
[09:57:33.915] <TB1> INFO: 18215300 events read in total (645100ms).
[09:57:57.680] <TB1> INFO: 18883550 events read in total (668865ms).
[09:58:21.187] <TB1> INFO: 19551750 events read in total (692372ms).
[09:58:44.736] <TB1> INFO: 20221200 events read in total (715921ms).
[09:59:08.657] <TB1> INFO: 20889450 events read in total (739842ms).
[09:59:32.360] <TB1> INFO: 21558350 events read in total (763545ms).
[09:59:56.523] <TB1> INFO: 22227150 events read in total (787708ms).
[10:00:20.787] <TB1> INFO: 22895900 events read in total (811972ms).
[10:00:44.432] <TB1> INFO: 23563250 events read in total (835617ms).
[10:01:08.449] <TB1> INFO: 24231500 events read in total (859634ms).
[10:01:32.045] <TB1> INFO: 24900050 events read in total (883230ms).
[10:01:55.950] <TB1> INFO: 25567950 events read in total (907135ms).
[10:02:20.637] <TB1> INFO: 26235950 events read in total (931822ms).
[10:02:44.085] <TB1> INFO: 26902250 events read in total (955270ms).
[10:03:07.625] <TB1> INFO: 27569500 events read in total (978810ms).
[10:03:31.398] <TB1> INFO: 28235300 events read in total (1002583ms).
[10:03:55.029] <TB1> INFO: 28902500 events read in total (1026214ms).
[10:04:18.582] <TB1> INFO: 29566350 events read in total (1049767ms).
[10:04:42.677] <TB1> INFO: 30233550 events read in total (1073862ms).
[10:05:06.533] <TB1> INFO: 30896200 events read in total (1097718ms).
[10:05:30.533] <TB1> INFO: 31563000 events read in total (1121718ms).
[10:05:54.380] <TB1> INFO: 32228400 events read in total (1145565ms).
[10:06:18.479] <TB1> INFO: 32893250 events read in total (1169664ms).
[10:06:42.701] <TB1> INFO: 33560200 events read in total (1193886ms).
[10:07:06.176] <TB1> INFO: 34228550 events read in total (1217361ms).
[10:07:30.272] <TB1> INFO: 34895500 events read in total (1241457ms).
[10:07:53.809] <TB1> INFO: 35563000 events read in total (1264994ms).
[10:08:17.561] <TB1> INFO: 36236850 events read in total (1288746ms).
[10:08:31.673] <TB1> INFO: 36608000 events read in total (1302858ms).
[10:08:31.777] <TB1> INFO: Test took 1303795ms.
[10:08:32.412] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:08:34.870] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:08:37.062] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:08:39.531] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:08:41.717] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:08:43.744] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:08:45.322] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:08:46.880] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:08:48.929] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:08:51.180] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:08:53.417] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:08:55.613] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:08:57.491] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:08:59.994] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:09:02.526] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:09:04.788] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:09:06.570] <TB1> INFO: PixTestScurves::scurves() done
[10:09:06.570] <TB1> INFO: Vcal mean: 117.67 121.29 118.09 122.38 127.79 121.59 117.28 115.74 123.85 112.15 115.02 118.88 122.89 113.17 113.10 119.47
[10:09:06.570] <TB1> INFO: Vcal RMS: 5.79 5.59 6.12 6.58 6.26 6.33 5.89 5.88 7.03 6.48 5.77 5.67 6.67 5.87 5.62 6.28
[10:09:06.570] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1338 seconds
[10:09:06.570] <TB1> INFO: Decoding statistics:
[10:09:06.570] <TB1> INFO: General information:
[10:09:06.570] <TB1> INFO: 16bit words read: 0
[10:09:06.570] <TB1> INFO: valid events total: 0
[10:09:06.570] <TB1> INFO: empty events: 0
[10:09:06.570] <TB1> INFO: valid events with pixels: 0
[10:09:06.570] <TB1> INFO: valid pixel hits: 0
[10:09:06.570] <TB1> INFO: Event errors: 0
[10:09:06.570] <TB1> INFO: start marker: 0
[10:09:06.570] <TB1> INFO: stop marker: 0
[10:09:06.570] <TB1> INFO: overflow: 0
[10:09:06.570] <TB1> INFO: invalid 5bit words: 0
[10:09:06.570] <TB1> INFO: invalid XOR eye diagram: 0
[10:09:06.570] <TB1> INFO: frame (failed synchr.): 0
[10:09:06.570] <TB1> INFO: idle data (no TBM trl): 0
[10:09:06.570] <TB1> INFO: no data (only TBM hdr): 0
[10:09:06.570] <TB1> INFO: TBM errors: 0
[10:09:06.570] <TB1> INFO: flawed TBM headers: 0
[10:09:06.570] <TB1> INFO: flawed TBM trailers: 0
[10:09:06.570] <TB1> INFO: event ID mismatches: 0
[10:09:06.570] <TB1> INFO: ROC errors: 0
[10:09:06.570] <TB1> INFO: missing ROC header(s): 0
[10:09:06.570] <TB1> INFO: misplaced readback start: 0
[10:09:06.570] <TB1> INFO: Pixel decoding errors: 0
[10:09:06.570] <TB1> INFO: pixel data incomplete: 0
[10:09:06.570] <TB1> INFO: pixel address: 0
[10:09:06.570] <TB1> INFO: pulse height fill bit: 0
[10:09:06.570] <TB1> INFO: buffer corruption: 0
[10:09:06.665] <TB1> INFO: ######################################################################
[10:09:06.665] <TB1> INFO: PixTestTrim::doTest()
[10:09:06.665] <TB1> INFO: ######################################################################
[10:09:06.666] <TB1> INFO: ----------------------------------------------------------------------
[10:09:06.666] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[10:09:06.666] <TB1> INFO: ----------------------------------------------------------------------
[10:09:06.735] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[10:09:06.735] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[10:09:06.749] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:09:06.749] <TB1> INFO: run 1 of 1
[10:09:07.075] <TB1> INFO: Expecting 5025280 events.
[10:09:38.314] <TB1> INFO: 833600 events read in total (30633ms).
[10:10:09.118] <TB1> INFO: 1664296 events read in total (61437ms).
[10:10:40.136] <TB1> INFO: 2492744 events read in total (92455ms).
[10:11:11.820] <TB1> INFO: 3314992 events read in total (124139ms).
[10:11:42.331] <TB1> INFO: 4132360 events read in total (154651ms).
[10:12:13.635] <TB1> INFO: 4949032 events read in total (185954ms).
[10:12:17.011] <TB1> INFO: 5025280 events read in total (189330ms).
[10:12:17.092] <TB1> INFO: Test took 190342ms.
[10:12:38.048] <TB1> INFO: ROC 0 VthrComp = 118
[10:12:38.048] <TB1> INFO: ROC 1 VthrComp = 124
[10:12:38.048] <TB1> INFO: ROC 2 VthrComp = 122
[10:12:38.048] <TB1> INFO: ROC 3 VthrComp = 125
[10:12:38.048] <TB1> INFO: ROC 4 VthrComp = 126
[10:12:38.048] <TB1> INFO: ROC 5 VthrComp = 127
[10:12:38.048] <TB1> INFO: ROC 6 VthrComp = 111
[10:12:38.049] <TB1> INFO: ROC 7 VthrComp = 109
[10:12:38.049] <TB1> INFO: ROC 8 VthrComp = 124
[10:12:38.049] <TB1> INFO: ROC 9 VthrComp = 108
[10:12:38.050] <TB1> INFO: ROC 10 VthrComp = 109
[10:12:38.050] <TB1> INFO: ROC 11 VthrComp = 111
[10:12:38.050] <TB1> INFO: ROC 12 VthrComp = 128
[10:12:38.050] <TB1> INFO: ROC 13 VthrComp = 112
[10:12:38.050] <TB1> INFO: ROC 14 VthrComp = 115
[10:12:38.050] <TB1> INFO: ROC 15 VthrComp = 129
[10:12:38.293] <TB1> INFO: Expecting 41600 events.
[10:12:42.024] <TB1> INFO: 41600 events read in total (3140ms).
[10:12:42.024] <TB1> INFO: Test took 3972ms.
[10:12:42.034] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[10:12:42.034] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[10:12:42.047] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:12:42.047] <TB1> INFO: run 1 of 1
[10:12:42.325] <TB1> INFO: Expecting 5025280 events.
[10:13:09.579] <TB1> INFO: 591408 events read in total (26663ms).
[10:13:35.530] <TB1> INFO: 1181648 events read in total (52614ms).
[10:14:01.816] <TB1> INFO: 1772144 events read in total (78900ms).
[10:14:28.577] <TB1> INFO: 2362448 events read in total (105661ms).
[10:14:54.605] <TB1> INFO: 2950064 events read in total (131689ms).
[10:15:20.633] <TB1> INFO: 3537112 events read in total (157717ms).
[10:15:46.594] <TB1> INFO: 4122816 events read in total (183678ms).
[10:16:12.975] <TB1> INFO: 4707880 events read in total (210059ms).
[10:16:27.799] <TB1> INFO: 5025280 events read in total (224883ms).
[10:16:27.953] <TB1> INFO: Test took 225906ms.
[10:17:00.638] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 61.0886 for pixel 0/18 mean/min/max = 46.1583/31.122/61.1946
[10:17:00.638] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 61.0795 for pixel 12/23 mean/min/max = 45.997/30.8731/61.1208
[10:17:00.639] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 63.4386 for pixel 0/73 mean/min/max = 46.8526/30.0828/63.6223
[10:17:00.639] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 62.3054 for pixel 18/2 mean/min/max = 46.5072/30.6497/62.3647
[10:17:00.640] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 62.7637 for pixel 3/77 mean/min/max = 46.7561/30.5242/62.988
[10:17:00.640] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 61.3536 for pixel 15/6 mean/min/max = 45.8566/30.0625/61.6508
[10:17:00.640] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 67.2309 for pixel 45/0 mean/min/max = 50.0107/32.6741/67.3473
[10:17:00.641] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 67.1297 for pixel 6/34 mean/min/max = 50.0933/33.0399/67.1468
[10:17:00.642] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 64.6594 for pixel 6/49 mean/min/max = 47.378/29.9785/64.7776
[10:17:00.642] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 67.2378 for pixel 16/2 mean/min/max = 50.0879/32.7783/67.3976
[10:17:00.642] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 69.2294 for pixel 34/14 mean/min/max = 51.3848/33.5083/69.2612
[10:17:00.643] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 66.2334 for pixel 7/69 mean/min/max = 49.8069/33.3424/66.2715
[10:17:00.643] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 61.0052 for pixel 21/19 mean/min/max = 45.7342/30.2749/61.1935
[10:17:00.644] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 63.7821 for pixel 51/4 mean/min/max = 47.8509/31.4847/64.217
[10:17:00.644] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 62.1906 for pixel 18/8 mean/min/max = 46.7065/31.197/62.2159
[10:17:00.645] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 59.9862 for pixel 18/1 mean/min/max = 45.8951/31.6615/60.1287
[10:17:00.645] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:17:00.734] <TB1> INFO: Expecting 411648 events.
[10:17:10.174] <TB1> INFO: 411648 events read in total (8848ms).
[10:17:10.181] <TB1> INFO: Expecting 411648 events.
[10:17:19.418] <TB1> INFO: 411648 events read in total (8834ms).
[10:17:19.429] <TB1> INFO: Expecting 411648 events.
[10:17:28.611] <TB1> INFO: 411648 events read in total (8779ms).
[10:17:28.626] <TB1> INFO: Expecting 411648 events.
[10:17:37.677] <TB1> INFO: 411648 events read in total (8648ms).
[10:17:37.694] <TB1> INFO: Expecting 411648 events.
[10:17:46.884] <TB1> INFO: 411648 events read in total (8787ms).
[10:17:46.905] <TB1> INFO: Expecting 411648 events.
[10:17:55.965] <TB1> INFO: 411648 events read in total (8657ms).
[10:17:55.987] <TB1> INFO: Expecting 411648 events.
[10:18:05.493] <TB1> INFO: 411648 events read in total (9103ms).
[10:18:05.533] <TB1> INFO: Expecting 411648 events.
[10:18:14.883] <TB1> INFO: 411648 events read in total (8947ms).
[10:18:14.920] <TB1> INFO: Expecting 411648 events.
[10:18:24.116] <TB1> INFO: 411648 events read in total (8793ms).
[10:18:24.145] <TB1> INFO: Expecting 411648 events.
[10:18:33.350] <TB1> INFO: 411648 events read in total (8802ms).
[10:18:33.384] <TB1> INFO: Expecting 411648 events.
[10:18:42.695] <TB1> INFO: 411648 events read in total (8908ms).
[10:18:42.734] <TB1> INFO: Expecting 411648 events.
[10:18:52.063] <TB1> INFO: 411648 events read in total (8926ms).
[10:18:52.117] <TB1> INFO: Expecting 411648 events.
[10:19:01.497] <TB1> INFO: 411648 events read in total (8977ms).
[10:19:01.570] <TB1> INFO: Expecting 411648 events.
[10:19:10.978] <TB1> INFO: 411648 events read in total (9005ms).
[10:19:11.032] <TB1> INFO: Expecting 411648 events.
[10:19:20.336] <TB1> INFO: 411648 events read in total (8901ms).
[10:19:20.386] <TB1> INFO: Expecting 411648 events.
[10:19:29.568] <TB1> INFO: 411648 events read in total (8778ms).
[10:19:29.706] <TB1> INFO: Test took 149061ms.
[10:19:30.503] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[10:19:30.516] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:19:30.516] <TB1> INFO: run 1 of 1
[10:19:30.752] <TB1> INFO: Expecting 5025280 events.
[10:19:58.041] <TB1> INFO: 594200 events read in total (26695ms).
[10:20:24.562] <TB1> INFO: 1184456 events read in total (53216ms).
[10:20:51.633] <TB1> INFO: 1774952 events read in total (80289ms).
[10:21:18.168] <TB1> INFO: 2363104 events read in total (106822ms).
[10:21:45.258] <TB1> INFO: 2952728 events read in total (133912ms).
[10:22:11.953] <TB1> INFO: 3544504 events read in total (160607ms).
[10:22:39.244] <TB1> INFO: 4140208 events read in total (187898ms).
[10:23:06.745] <TB1> INFO: 4735600 events read in total (215399ms).
[10:23:20.766] <TB1> INFO: 5025280 events read in total (229420ms).
[10:23:21.029] <TB1> INFO: Test took 230514ms.
[10:23:48.935] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 2.701499 .. 146.662001
[10:23:49.176] <TB1> INFO: Expecting 208000 events.
[10:23:58.918] <TB1> INFO: 208000 events read in total (9150ms).
[10:23:58.920] <TB1> INFO: Test took 9982ms.
[10:23:58.993] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 156 (-1/-1) hits flags = 528 (plus default)
[10:23:59.008] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:23:59.008] <TB1> INFO: run 1 of 1
[10:23:59.286] <TB1> INFO: Expecting 5158400 events.
[10:24:27.190] <TB1> INFO: 583544 events read in total (27313ms).
[10:24:53.650] <TB1> INFO: 1166744 events read in total (53774ms).
[10:25:19.765] <TB1> INFO: 1750008 events read in total (79889ms).
[10:25:46.665] <TB1> INFO: 2332984 events read in total (106788ms).
[10:26:13.087] <TB1> INFO: 2916232 events read in total (133210ms).
[10:26:40.277] <TB1> INFO: 3498568 events read in total (160400ms).
[10:27:07.148] <TB1> INFO: 4080584 events read in total (187271ms).
[10:27:33.489] <TB1> INFO: 4661640 events read in total (213612ms).
[10:27:56.138] <TB1> INFO: 5158400 events read in total (236261ms).
[10:27:56.308] <TB1> INFO: Test took 237301ms.
[10:28:27.935] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 26.848141 .. 46.990604
[10:28:28.175] <TB1> INFO: Expecting 208000 events.
[10:28:38.960] <TB1> INFO: 208000 events read in total (10194ms).
[10:28:38.962] <TB1> INFO: Test took 11023ms.
[10:28:39.042] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 56 (-1/-1) hits flags = 528 (plus default)
[10:28:39.056] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:28:39.057] <TB1> INFO: run 1 of 1
[10:28:39.351] <TB1> INFO: Expecting 1364480 events.
[10:29:08.616] <TB1> INFO: 661792 events read in total (28674ms).
[10:29:37.374] <TB1> INFO: 1319360 events read in total (57433ms).
[10:29:39.692] <TB1> INFO: 1364480 events read in total (59750ms).
[10:29:39.728] <TB1> INFO: Test took 60672ms.
[10:29:54.572] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 26.787408 .. 49.946387
[10:29:54.813] <TB1> INFO: Expecting 208000 events.
[10:30:04.798] <TB1> INFO: 208000 events read in total (9394ms).
[10:30:04.799] <TB1> INFO: Test took 10224ms.
[10:30:04.848] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 59 (-1/-1) hits flags = 528 (plus default)
[10:30:04.861] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:30:04.861] <TB1> INFO: run 1 of 1
[10:30:05.139] <TB1> INFO: Expecting 1464320 events.
[10:30:34.202] <TB1> INFO: 649440 events read in total (28471ms).
[10:31:02.262] <TB1> INFO: 1297456 events read in total (56531ms).
[10:31:10.087] <TB1> INFO: 1464320 events read in total (64356ms).
[10:31:10.122] <TB1> INFO: Test took 65262ms.
[10:31:26.207] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 25.863271 .. 47.603763
[10:31:26.452] <TB1> INFO: Expecting 208000 events.
[10:31:36.211] <TB1> INFO: 208000 events read in total (9168ms).
[10:31:36.212] <TB1> INFO: Test took 10003ms.
[10:31:36.260] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 57 (-1/-1) hits flags = 528 (plus default)
[10:31:36.272] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:31:36.272] <TB1> INFO: run 1 of 1
[10:31:36.550] <TB1> INFO: Expecting 1431040 events.
[10:32:06.065] <TB1> INFO: 659696 events read in total (28923ms).
[10:32:34.913] <TB1> INFO: 1318792 events read in total (57771ms).
[10:32:40.468] <TB1> INFO: 1431040 events read in total (63326ms).
[10:32:40.511] <TB1> INFO: Test took 64240ms.
[10:32:55.335] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[10:32:55.336] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[10:32:55.350] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:32:55.350] <TB1> INFO: run 1 of 1
[10:32:55.643] <TB1> INFO: Expecting 1364480 events.
[10:33:25.050] <TB1> INFO: 667696 events read in total (28816ms).
[10:33:55.081] <TB1> INFO: 1334632 events read in total (58847ms).
[10:33:56.854] <TB1> INFO: 1364480 events read in total (60621ms).
[10:33:56.893] <TB1> INFO: Test took 61544ms.
[10:34:10.260] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C0.dat
[10:34:10.260] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C1.dat
[10:34:10.260] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C2.dat
[10:34:10.260] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C3.dat
[10:34:10.261] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C4.dat
[10:34:10.261] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C5.dat
[10:34:10.261] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C6.dat
[10:34:10.261] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C7.dat
[10:34:10.261] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C8.dat
[10:34:10.261] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C9.dat
[10:34:10.261] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C10.dat
[10:34:10.261] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C11.dat
[10:34:10.261] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C12.dat
[10:34:10.261] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C13.dat
[10:34:10.261] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C14.dat
[10:34:10.262] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C15.dat
[10:34:10.262] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters35_C0.dat
[10:34:10.267] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters35_C1.dat
[10:34:10.272] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters35_C2.dat
[10:34:10.277] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters35_C3.dat
[10:34:10.281] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters35_C4.dat
[10:34:10.286] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters35_C5.dat
[10:34:10.291] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters35_C6.dat
[10:34:10.296] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters35_C7.dat
[10:34:10.301] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters35_C8.dat
[10:34:10.305] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters35_C9.dat
[10:34:10.312] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters35_C10.dat
[10:34:10.319] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters35_C11.dat
[10:34:10.326] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters35_C12.dat
[10:34:10.332] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters35_C13.dat
[10:34:10.339] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters35_C14.dat
[10:34:10.346] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//trimParameters35_C15.dat
[10:34:10.352] <TB1> INFO: PixTestTrim::trimTest() done
[10:34:10.352] <TB1> INFO: vtrim: 116 132 131 154 120 140 150 134 132 157 162 138 139 135 140 144
[10:34:10.352] <TB1> INFO: vthrcomp: 118 124 122 125 126 127 111 109 124 108 109 111 128 112 115 129
[10:34:10.352] <TB1> INFO: vcal mean: 35.00 34.98 34.93 35.07 35.04 34.92 35.59 34.98 35.13 35.05 35.43 35.05 34.95 34.96 35.01 34.98
[10:34:10.352] <TB1> INFO: vcal RMS: 1.18 1.13 1.11 1.29 1.28 1.25 1.89 1.14 1.36 1.13 1.55 1.20 1.13 1.10 1.27 1.14
[10:34:10.352] <TB1> INFO: bits mean: 9.48 9.90 9.09 10.20 9.59 9.75 9.63 9.03 9.93 8.69 8.94 8.93 9.63 9.21 9.92 10.01
[10:34:10.352] <TB1> INFO: bits RMS: 2.83 2.64 2.96 2.49 2.82 2.78 2.49 2.51 2.68 2.64 2.55 2.62 2.85 2.74 2.55 2.48
[10:34:10.361] <TB1> INFO: ----------------------------------------------------------------------
[10:34:10.361] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[10:34:10.361] <TB1> INFO: ----------------------------------------------------------------------
[10:34:10.364] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[10:34:10.376] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[10:34:10.376] <TB1> INFO: run 1 of 1
[10:34:10.614] <TB1> INFO: Expecting 4160000 events.
[10:34:44.378] <TB1> INFO: 765260 events read in total (33172ms).
[10:35:16.839] <TB1> INFO: 1522905 events read in total (65633ms).
[10:35:49.692] <TB1> INFO: 2274970 events read in total (98486ms).
[10:36:22.079] <TB1> INFO: 3024785 events read in total (130873ms).
[10:36:54.262] <TB1> INFO: 3771810 events read in total (163056ms).
[10:37:11.822] <TB1> INFO: 4160000 events read in total (180616ms).
[10:37:11.897] <TB1> INFO: Test took 181521ms.
[10:37:44.924] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[10:37:44.937] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[10:37:44.937] <TB1> INFO: run 1 of 1
[10:37:45.174] <TB1> INFO: Expecting 4284800 events.
[10:38:18.172] <TB1> INFO: 732120 events read in total (32406ms).
[10:38:50.704] <TB1> INFO: 1457540 events read in total (64938ms).
[10:39:23.426] <TB1> INFO: 2180095 events read in total (97660ms).
[10:39:56.411] <TB1> INFO: 2898345 events read in total (130645ms).
[10:40:28.792] <TB1> INFO: 3614700 events read in total (163026ms).
[10:40:59.209] <TB1> INFO: 4284800 events read in total (193443ms).
[10:40:59.356] <TB1> INFO: Test took 194419ms.
[10:41:32.879] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 227 (-1/-1) hits flags = 528 (plus default)
[10:41:32.892] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[10:41:32.892] <TB1> INFO: run 1 of 1
[10:41:33.128] <TB1> INFO: Expecting 4742400 events.
[10:42:05.263] <TB1> INFO: 707030 events read in total (31544ms).
[10:42:36.885] <TB1> INFO: 1409210 events read in total (63166ms).
[10:43:07.827] <TB1> INFO: 2108665 events read in total (94108ms).
[10:43:39.153] <TB1> INFO: 2804265 events read in total (125434ms).
[10:44:10.748] <TB1> INFO: 3499670 events read in total (157029ms).
[10:44:44.421] <TB1> INFO: 4192540 events read in total (190702ms).
[10:45:09.723] <TB1> INFO: 4742400 events read in total (216004ms).
[10:45:09.893] <TB1> INFO: Test took 217001ms.
[10:45:40.701] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[10:45:40.719] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[10:45:40.719] <TB1> INFO: run 1 of 1
[10:45:41.026] <TB1> INFO: Expecting 4430400 events.
[10:46:14.164] <TB1> INFO: 723860 events read in total (32546ms).
[10:46:46.194] <TB1> INFO: 1441980 events read in total (64576ms).
[10:47:18.015] <TB1> INFO: 2157105 events read in total (96397ms).
[10:47:50.344] <TB1> INFO: 2867585 events read in total (128726ms).
[10:48:22.950] <TB1> INFO: 3577600 events read in total (161332ms).
[10:48:54.742] <TB1> INFO: 4286810 events read in total (193124ms).
[10:49:01.304] <TB1> INFO: 4430400 events read in total (199686ms).
[10:49:01.430] <TB1> INFO: Test took 200711ms.
[10:49:31.355] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 219 (-1/-1) hits flags = 528 (plus default)
[10:49:31.368] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[10:49:31.368] <TB1> INFO: run 1 of 1
[10:49:31.604] <TB1> INFO: Expecting 4576000 events.
[10:50:04.326] <TB1> INFO: 716035 events read in total (32130ms).
[10:50:35.925] <TB1> INFO: 1426800 events read in total (63729ms).
[10:51:07.937] <TB1> INFO: 2134640 events read in total (95741ms).
[10:51:41.185] <TB1> INFO: 2838655 events read in total (128989ms).
[10:52:13.077] <TB1> INFO: 3541715 events read in total (160881ms).
[10:52:44.581] <TB1> INFO: 4243375 events read in total (192385ms).
[10:53:00.007] <TB1> INFO: 4576000 events read in total (207811ms).
[10:53:00.139] <TB1> INFO: Test took 208770ms.
[10:53:29.376] <TB1> INFO: PixTestTrim::trimBitTest() done
[10:53:29.377] <TB1> INFO: PixTestTrim::doTest() done, duration: 2662 seconds
[10:53:29.377] <TB1> INFO: Decoding statistics:
[10:53:29.377] <TB1> INFO: General information:
[10:53:29.377] <TB1> INFO: 16bit words read: 0
[10:53:29.377] <TB1> INFO: valid events total: 0
[10:53:29.377] <TB1> INFO: empty events: 0
[10:53:29.377] <TB1> INFO: valid events with pixels: 0
[10:53:29.377] <TB1> INFO: valid pixel hits: 0
[10:53:29.377] <TB1> INFO: Event errors: 0
[10:53:29.377] <TB1> INFO: start marker: 0
[10:53:29.377] <TB1> INFO: stop marker: 0
[10:53:29.377] <TB1> INFO: overflow: 0
[10:53:29.377] <TB1> INFO: invalid 5bit words: 0
[10:53:29.377] <TB1> INFO: invalid XOR eye diagram: 0
[10:53:29.377] <TB1> INFO: frame (failed synchr.): 0
[10:53:29.377] <TB1> INFO: idle data (no TBM trl): 0
[10:53:29.377] <TB1> INFO: no data (only TBM hdr): 0
[10:53:29.377] <TB1> INFO: TBM errors: 0
[10:53:29.377] <TB1> INFO: flawed TBM headers: 0
[10:53:29.377] <TB1> INFO: flawed TBM trailers: 0
[10:53:29.377] <TB1> INFO: event ID mismatches: 0
[10:53:29.377] <TB1> INFO: ROC errors: 0
[10:53:29.377] <TB1> INFO: missing ROC header(s): 0
[10:53:29.377] <TB1> INFO: misplaced readback start: 0
[10:53:29.377] <TB1> INFO: Pixel decoding errors: 0
[10:53:29.377] <TB1> INFO: pixel data incomplete: 0
[10:53:29.377] <TB1> INFO: pixel address: 0
[10:53:29.377] <TB1> INFO: pulse height fill bit: 0
[10:53:29.377] <TB1> INFO: buffer corruption: 0
[10:53:30.396] <TB1> INFO: ######################################################################
[10:53:30.396] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[10:53:30.396] <TB1> INFO: ######################################################################
[10:53:30.775] <TB1> INFO: Expecting 41600 events.
[10:53:34.437] <TB1> INFO: 41600 events read in total (3070ms).
[10:53:34.442] <TB1> INFO: Test took 4045ms.
[10:53:34.888] <TB1> INFO: Expecting 41600 events.
[10:53:38.460] <TB1> INFO: 41600 events read in total (2980ms).
[10:53:38.461] <TB1> INFO: Test took 3808ms.
[10:53:38.750] <TB1> INFO: Expecting 41600 events.
[10:53:42.350] <TB1> INFO: 41600 events read in total (3006ms).
[10:53:42.351] <TB1> INFO: Test took 3866ms.
[10:53:42.640] <TB1> INFO: Expecting 41600 events.
[10:53:46.131] <TB1> INFO: 41600 events read in total (2898ms).
[10:53:46.132] <TB1> INFO: Test took 3756ms.
[10:53:46.422] <TB1> INFO: Expecting 41600 events.
[10:53:50.247] <TB1> INFO: 41600 events read in total (3234ms).
[10:53:50.248] <TB1> INFO: Test took 4091ms.
[10:53:50.540] <TB1> INFO: Expecting 41600 events.
[10:53:54.013] <TB1> INFO: 41600 events read in total (2881ms).
[10:53:54.015] <TB1> INFO: Test took 3739ms.
[10:53:54.305] <TB1> INFO: Expecting 41600 events.
[10:53:57.862] <TB1> INFO: 41600 events read in total (2966ms).
[10:53:57.863] <TB1> INFO: Test took 3823ms.
[10:53:58.154] <TB1> INFO: Expecting 41600 events.
[10:54:01.713] <TB1> INFO: 41600 events read in total (2968ms).
[10:54:01.714] <TB1> INFO: Test took 3825ms.
[10:54:02.031] <TB1> INFO: Expecting 41600 events.
[10:54:05.510] <TB1> INFO: 41600 events read in total (2887ms).
[10:54:05.511] <TB1> INFO: Test took 3772ms.
[10:54:05.801] <TB1> INFO: Expecting 41600 events.
[10:54:09.338] <TB1> INFO: 41600 events read in total (2946ms).
[10:54:09.339] <TB1> INFO: Test took 3803ms.
[10:54:09.629] <TB1> INFO: Expecting 41600 events.
[10:54:13.312] <TB1> INFO: 41600 events read in total (3091ms).
[10:54:13.313] <TB1> INFO: Test took 3949ms.
[10:54:13.603] <TB1> INFO: Expecting 41600 events.
[10:54:17.342] <TB1> INFO: 41600 events read in total (3148ms).
[10:54:17.343] <TB1> INFO: Test took 4005ms.
[10:54:17.638] <TB1> INFO: Expecting 41600 events.
[10:54:21.394] <TB1> INFO: 41600 events read in total (3164ms).
[10:54:21.395] <TB1> INFO: Test took 4023ms.
[10:54:21.688] <TB1> INFO: Expecting 41600 events.
[10:54:25.388] <TB1> INFO: 41600 events read in total (3108ms).
[10:54:25.389] <TB1> INFO: Test took 3966ms.
[10:54:25.685] <TB1> INFO: Expecting 41600 events.
[10:54:29.236] <TB1> INFO: 41600 events read in total (2960ms).
[10:54:29.237] <TB1> INFO: Test took 3822ms.
[10:54:29.529] <TB1> INFO: Expecting 41600 events.
[10:54:33.077] <TB1> INFO: 41600 events read in total (2956ms).
[10:54:33.078] <TB1> INFO: Test took 3815ms.
[10:54:33.368] <TB1> INFO: Expecting 41600 events.
[10:54:36.973] <TB1> INFO: 41600 events read in total (3013ms).
[10:54:36.974] <TB1> INFO: Test took 3872ms.
[10:54:37.274] <TB1> INFO: Expecting 41600 events.
[10:54:40.796] <TB1> INFO: 41600 events read in total (2931ms).
[10:54:40.797] <TB1> INFO: Test took 3798ms.
[10:54:41.124] <TB1> INFO: Expecting 41600 events.
[10:54:44.735] <TB1> INFO: 41600 events read in total (3019ms).
[10:54:44.735] <TB1> INFO: Test took 3907ms.
[10:54:45.025] <TB1> INFO: Expecting 41600 events.
[10:54:48.540] <TB1> INFO: 41600 events read in total (2923ms).
[10:54:48.541] <TB1> INFO: Test took 3781ms.
[10:54:48.830] <TB1> INFO: Expecting 41600 events.
[10:54:52.383] <TB1> INFO: 41600 events read in total (2962ms).
[10:54:52.384] <TB1> INFO: Test took 3819ms.
[10:54:52.674] <TB1> INFO: Expecting 41600 events.
[10:54:56.317] <TB1> INFO: 41600 events read in total (3051ms).
[10:54:56.318] <TB1> INFO: Test took 3908ms.
[10:54:56.612] <TB1> INFO: Expecting 41600 events.
[10:55:00.133] <TB1> INFO: 41600 events read in total (2929ms).
[10:55:00.141] <TB1> INFO: Test took 3795ms.
[10:55:00.449] <TB1> INFO: Expecting 41600 events.
[10:55:04.042] <TB1> INFO: 41600 events read in total (3002ms).
[10:55:04.043] <TB1> INFO: Test took 3878ms.
[10:55:04.335] <TB1> INFO: Expecting 41600 events.
[10:55:07.817] <TB1> INFO: 41600 events read in total (2891ms).
[10:55:07.817] <TB1> INFO: Test took 3748ms.
[10:55:08.108] <TB1> INFO: Expecting 41600 events.
[10:55:11.816] <TB1> INFO: 41600 events read in total (3117ms).
[10:55:11.817] <TB1> INFO: Test took 3975ms.
[10:55:12.107] <TB1> INFO: Expecting 41600 events.
[10:55:15.702] <TB1> INFO: 41600 events read in total (3004ms).
[10:55:15.703] <TB1> INFO: Test took 3861ms.
[10:55:16.006] <TB1> INFO: Expecting 41600 events.
[10:55:19.675] <TB1> INFO: 41600 events read in total (3077ms).
[10:55:19.675] <TB1> INFO: Test took 3948ms.
[10:55:19.965] <TB1> INFO: Expecting 41600 events.
[10:55:23.665] <TB1> INFO: 41600 events read in total (3108ms).
[10:55:23.666] <TB1> INFO: Test took 3966ms.
[10:55:23.955] <TB1> INFO: Expecting 41600 events.
[10:55:27.488] <TB1> INFO: 41600 events read in total (2942ms).
[10:55:27.489] <TB1> INFO: Test took 3799ms.
[10:55:27.784] <TB1> INFO: Expecting 41600 events.
[10:55:31.292] <TB1> INFO: 41600 events read in total (2917ms).
[10:55:31.293] <TB1> INFO: Test took 3774ms.
[10:55:31.583] <TB1> INFO: Expecting 2560 events.
[10:55:32.472] <TB1> INFO: 2560 events read in total (298ms).
[10:55:32.472] <TB1> INFO: Test took 1165ms.
[10:55:32.780] <TB1> INFO: Expecting 2560 events.
[10:55:33.665] <TB1> INFO: 2560 events read in total (294ms).
[10:55:33.665] <TB1> INFO: Test took 1192ms.
[10:55:33.973] <TB1> INFO: Expecting 2560 events.
[10:55:34.859] <TB1> INFO: 2560 events read in total (294ms).
[10:55:34.859] <TB1> INFO: Test took 1194ms.
[10:55:35.168] <TB1> INFO: Expecting 2560 events.
[10:55:36.055] <TB1> INFO: 2560 events read in total (295ms).
[10:55:36.055] <TB1> INFO: Test took 1195ms.
[10:55:36.363] <TB1> INFO: Expecting 2560 events.
[10:55:37.244] <TB1> INFO: 2560 events read in total (290ms).
[10:55:37.244] <TB1> INFO: Test took 1189ms.
[10:55:37.552] <TB1> INFO: Expecting 2560 events.
[10:55:38.435] <TB1> INFO: 2560 events read in total (291ms).
[10:55:38.435] <TB1> INFO: Test took 1191ms.
[10:55:38.743] <TB1> INFO: Expecting 2560 events.
[10:55:39.622] <TB1> INFO: 2560 events read in total (287ms).
[10:55:39.623] <TB1> INFO: Test took 1188ms.
[10:55:39.930] <TB1> INFO: Expecting 2560 events.
[10:55:40.811] <TB1> INFO: 2560 events read in total (289ms).
[10:55:40.812] <TB1> INFO: Test took 1189ms.
[10:55:41.119] <TB1> INFO: Expecting 2560 events.
[10:55:41.002] <TB1> INFO: 2560 events read in total (291ms).
[10:55:41.002] <TB1> INFO: Test took 1190ms.
[10:55:42.309] <TB1> INFO: Expecting 2560 events.
[10:55:43.189] <TB1> INFO: 2560 events read in total (288ms).
[10:55:43.189] <TB1> INFO: Test took 1186ms.
[10:55:43.497] <TB1> INFO: Expecting 2560 events.
[10:55:44.376] <TB1> INFO: 2560 events read in total (288ms).
[10:55:44.376] <TB1> INFO: Test took 1187ms.
[10:55:44.684] <TB1> INFO: Expecting 2560 events.
[10:55:45.562] <TB1> INFO: 2560 events read in total (287ms).
[10:55:45.562] <TB1> INFO: Test took 1187ms.
[10:55:45.874] <TB1> INFO: Expecting 2560 events.
[10:55:46.757] <TB1> INFO: 2560 events read in total (292ms).
[10:55:46.757] <TB1> INFO: Test took 1194ms.
[10:55:47.065] <TB1> INFO: Expecting 2560 events.
[10:55:47.951] <TB1> INFO: 2560 events read in total (294ms).
[10:55:47.952] <TB1> INFO: Test took 1194ms.
[10:55:48.259] <TB1> INFO: Expecting 2560 events.
[10:55:49.141] <TB1> INFO: 2560 events read in total (290ms).
[10:55:49.142] <TB1> INFO: Test took 1190ms.
[10:55:49.450] <TB1> INFO: Expecting 2560 events.
[10:55:50.336] <TB1> INFO: 2560 events read in total (295ms).
[10:55:50.339] <TB1> INFO: Test took 1197ms.
[10:55:50.343] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:55:50.646] <TB1> INFO: Expecting 655360 events.
[10:56:05.128] <TB1> INFO: 655360 events read in total (13891ms).
[10:56:05.142] <TB1> INFO: Expecting 655360 events.
[10:56:19.749] <TB1> INFO: 655360 events read in total (14203ms).
[10:56:19.769] <TB1> INFO: Expecting 655360 events.
[10:56:34.426] <TB1> INFO: 655360 events read in total (14254ms).
[10:56:34.451] <TB1> INFO: Expecting 655360 events.
[10:56:49.113] <TB1> INFO: 655360 events read in total (14259ms).
[10:56:49.142] <TB1> INFO: Expecting 655360 events.
[10:57:03.551] <TB1> INFO: 655360 events read in total (14006ms).
[10:57:03.607] <TB1> INFO: Expecting 655360 events.
[10:57:18.207] <TB1> INFO: 655360 events read in total (14198ms).
[10:57:18.244] <TB1> INFO: Expecting 655360 events.
[10:57:32.890] <TB1> INFO: 655360 events read in total (14242ms).
[10:57:32.961] <TB1> INFO: Expecting 655360 events.
[10:57:47.312] <TB1> INFO: 655360 events read in total (13948ms).
[10:57:47.366] <TB1> INFO: Expecting 655360 events.
[10:58:01.931] <TB1> INFO: 655360 events read in total (14162ms).
[10:58:02.027] <TB1> INFO: Expecting 655360 events.
[10:58:16.460] <TB1> INFO: 655360 events read in total (14030ms).
[10:58:16.615] <TB1> INFO: Expecting 655360 events.
[10:58:31.086] <TB1> INFO: 655360 events read in total (14065ms).
[10:58:31.222] <TB1> INFO: Expecting 655360 events.
[10:58:45.621] <TB1> INFO: 655360 events read in total (13996ms).
[10:58:45.708] <TB1> INFO: Expecting 655360 events.
[10:59:00.359] <TB1> INFO: 655360 events read in total (14249ms).
[10:59:00.501] <TB1> INFO: Expecting 655360 events.
[10:59:14.860] <TB1> INFO: 655360 events read in total (13956ms).
[10:59:14.955] <TB1> INFO: Expecting 655360 events.
[10:59:29.438] <TB1> INFO: 655360 events read in total (14080ms).
[10:59:29.539] <TB1> INFO: Expecting 655360 events.
[10:59:44.026] <TB1> INFO: 655360 events read in total (14083ms).
[10:59:44.189] <TB1> INFO: Test took 233846ms.
[10:59:44.319] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:59:44.574] <TB1> INFO: Expecting 655360 events.
[10:59:59.127] <TB1> INFO: 655360 events read in total (13962ms).
[10:59:59.144] <TB1> INFO: Expecting 655360 events.
[11:00:13.426] <TB1> INFO: 655360 events read in total (13879ms).
[11:00:13.447] <TB1> INFO: Expecting 655360 events.
[11:00:27.900] <TB1> INFO: 655360 events read in total (14050ms).
[11:00:27.926] <TB1> INFO: Expecting 655360 events.
[11:00:42.132] <TB1> INFO: 655360 events read in total (13803ms).
[11:00:42.170] <TB1> INFO: Expecting 655360 events.
[11:00:56.076] <TB1> INFO: 655360 events read in total (13503ms).
[11:00:56.109] <TB1> INFO: Expecting 655360 events.
[11:01:10.271] <TB1> INFO: 655360 events read in total (13759ms).
[11:01:10.307] <TB1> INFO: Expecting 655360 events.
[11:01:24.764] <TB1> INFO: 655360 events read in total (14054ms).
[11:01:24.806] <TB1> INFO: Expecting 655360 events.
[11:01:39.180] <TB1> INFO: 655360 events read in total (13970ms).
[11:01:39.225] <TB1> INFO: Expecting 655360 events.
[11:01:53.495] <TB1> INFO: 655360 events read in total (13867ms).
[11:01:53.557] <TB1> INFO: Expecting 655360 events.
[11:02:07.820] <TB1> INFO: 655360 events read in total (13860ms).
[11:02:07.931] <TB1> INFO: Expecting 655360 events.
[11:02:22.449] <TB1> INFO: 655360 events read in total (14115ms).
[11:02:22.531] <TB1> INFO: Expecting 655360 events.
[11:02:36.910] <TB1> INFO: 655360 events read in total (13976ms).
[11:02:36.994] <TB1> INFO: Expecting 655360 events.
[11:02:51.237] <TB1> INFO: 655360 events read in total (13841ms).
[11:02:51.399] <TB1> INFO: Expecting 655360 events.
[11:03:05.911] <TB1> INFO: 655360 events read in total (14109ms).
[11:03:05.002] <TB1> INFO: Expecting 655360 events.
[11:03:20.391] <TB1> INFO: 655360 events read in total (13987ms).
[11:03:20.504] <TB1> INFO: Expecting 655360 events.
[11:03:35.072] <TB1> INFO: 655360 events read in total (14165ms).
[11:03:35.275] <TB1> INFO: Test took 230956ms.
[11:03:35.537] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:03:35.542] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:03:35.549] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[11:03:35.555] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[11:03:35.561] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[11:03:35.568] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[11:03:35.573] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[11:03:35.579] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[11:03:35.586] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[11:03:35.592] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[11:03:35.598] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:03:35.605] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:03:35.610] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:03:35.617] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:03:35.623] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:03:35.629] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:03:35.635] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:03:35.641] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:03:35.647] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[11:03:35.654] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[11:03:35.660] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[11:03:35.667] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:03:35.673] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:03:35.679] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:03:35.686] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[11:03:35.694] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[11:03:35.700] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:03:35.708] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:03:35.715] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:03:35.721] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[11:03:35.729] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:03:35.735] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:03:35.741] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:03:35.747] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:03:35.755] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:03:35.761] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[11:03:35.767] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[11:03:35.773] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[11:03:35.807] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C0.dat
[11:03:35.807] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C1.dat
[11:03:35.807] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C2.dat
[11:03:35.807] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C3.dat
[11:03:35.807] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C4.dat
[11:03:35.807] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C5.dat
[11:03:35.807] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C6.dat
[11:03:35.807] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C7.dat
[11:03:35.807] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C8.dat
[11:03:35.807] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C9.dat
[11:03:35.807] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C10.dat
[11:03:35.808] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C11.dat
[11:03:35.808] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C12.dat
[11:03:35.808] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C13.dat
[11:03:35.808] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C14.dat
[11:03:35.808] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//dacParameters35_C15.dat
[11:03:36.048] <TB1> INFO: Expecting 41600 events.
[11:03:39.162] <TB1> INFO: 41600 events read in total (2522ms).
[11:03:39.162] <TB1> INFO: Test took 3352ms.
[11:03:39.611] <TB1> INFO: Expecting 41600 events.
[11:03:42.620] <TB1> INFO: 41600 events read in total (2418ms).
[11:03:42.621] <TB1> INFO: Test took 3247ms.
[11:03:43.071] <TB1> INFO: Expecting 41600 events.
[11:03:46.204] <TB1> INFO: 41600 events read in total (2541ms).
[11:03:46.205] <TB1> INFO: Test took 3372ms.
[11:03:46.421] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:03:46.510] <TB1> INFO: Expecting 2560 events.
[11:03:47.399] <TB1> INFO: 2560 events read in total (297ms).
[11:03:47.399] <TB1> INFO: Test took 978ms.
[11:03:47.401] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:03:47.707] <TB1> INFO: Expecting 2560 events.
[11:03:48.591] <TB1> INFO: 2560 events read in total (292ms).
[11:03:48.591] <TB1> INFO: Test took 1190ms.
[11:03:48.593] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:03:48.899] <TB1> INFO: Expecting 2560 events.
[11:03:49.788] <TB1> INFO: 2560 events read in total (297ms).
[11:03:49.788] <TB1> INFO: Test took 1195ms.
[11:03:49.791] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:03:50.097] <TB1> INFO: Expecting 2560 events.
[11:03:50.981] <TB1> INFO: 2560 events read in total (293ms).
[11:03:50.981] <TB1> INFO: Test took 1190ms.
[11:03:50.986] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:03:51.290] <TB1> INFO: Expecting 2560 events.
[11:03:52.183] <TB1> INFO: 2560 events read in total (302ms).
[11:03:52.183] <TB1> INFO: Test took 1197ms.
[11:03:52.185] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:03:52.491] <TB1> INFO: Expecting 2560 events.
[11:03:53.375] <TB1> INFO: 2560 events read in total (293ms).
[11:03:53.376] <TB1> INFO: Test took 1191ms.
[11:03:53.380] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:03:53.685] <TB1> INFO: Expecting 2560 events.
[11:03:54.569] <TB1> INFO: 2560 events read in total (293ms).
[11:03:54.569] <TB1> INFO: Test took 1189ms.
[11:03:54.572] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:03:54.877] <TB1> INFO: Expecting 2560 events.
[11:03:55.761] <TB1> INFO: 2560 events read in total (292ms).
[11:03:55.761] <TB1> INFO: Test took 1189ms.
[11:03:55.766] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:03:56.069] <TB1> INFO: Expecting 2560 events.
[11:03:56.949] <TB1> INFO: 2560 events read in total (288ms).
[11:03:56.950] <TB1> INFO: Test took 1184ms.
[11:03:56.952] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:03:57.258] <TB1> INFO: Expecting 2560 events.
[11:03:58.138] <TB1> INFO: 2560 events read in total (288ms).
[11:03:58.138] <TB1> INFO: Test took 1186ms.
[11:03:58.141] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:03:58.447] <TB1> INFO: Expecting 2560 events.
[11:03:59.330] <TB1> INFO: 2560 events read in total (292ms).
[11:03:59.330] <TB1> INFO: Test took 1189ms.
[11:03:59.333] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:03:59.638] <TB1> INFO: Expecting 2560 events.
[11:04:00.518] <TB1> INFO: 2560 events read in total (289ms).
[11:04:00.518] <TB1> INFO: Test took 1185ms.
[11:04:00.521] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:00.828] <TB1> INFO: Expecting 2560 events.
[11:04:01.706] <TB1> INFO: 2560 events read in total (287ms).
[11:04:01.707] <TB1> INFO: Test took 1186ms.
[11:04:01.709] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:02.014] <TB1> INFO: Expecting 2560 events.
[11:04:02.894] <TB1> INFO: 2560 events read in total (288ms).
[11:04:02.894] <TB1> INFO: Test took 1185ms.
[11:04:02.896] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:03.203] <TB1> INFO: Expecting 2560 events.
[11:04:04.085] <TB1> INFO: 2560 events read in total (290ms).
[11:04:04.086] <TB1> INFO: Test took 1190ms.
[11:04:04.090] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:04.394] <TB1> INFO: Expecting 2560 events.
[11:04:05.276] <TB1> INFO: 2560 events read in total (291ms).
[11:04:05.276] <TB1> INFO: Test took 1186ms.
[11:04:05.278] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:05.585] <TB1> INFO: Expecting 2560 events.
[11:04:06.463] <TB1> INFO: 2560 events read in total (287ms).
[11:04:06.463] <TB1> INFO: Test took 1185ms.
[11:04:06.466] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:06.772] <TB1> INFO: Expecting 2560 events.
[11:04:07.654] <TB1> INFO: 2560 events read in total (292ms).
[11:04:07.655] <TB1> INFO: Test took 1190ms.
[11:04:07.657] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:07.963] <TB1> INFO: Expecting 2560 events.
[11:04:08.842] <TB1> INFO: 2560 events read in total (287ms).
[11:04:08.842] <TB1> INFO: Test took 1185ms.
[11:04:08.846] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:09.150] <TB1> INFO: Expecting 2560 events.
[11:04:10.030] <TB1> INFO: 2560 events read in total (288ms).
[11:04:10.030] <TB1> INFO: Test took 1184ms.
[11:04:10.034] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:10.338] <TB1> INFO: Expecting 2560 events.
[11:04:11.223] <TB1> INFO: 2560 events read in total (291ms).
[11:04:11.223] <TB1> INFO: Test took 1189ms.
[11:04:11.227] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:11.532] <TB1> INFO: Expecting 2560 events.
[11:04:12.416] <TB1> INFO: 2560 events read in total (292ms).
[11:04:12.417] <TB1> INFO: Test took 1190ms.
[11:04:12.419] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:12.725] <TB1> INFO: Expecting 2560 events.
[11:04:13.605] <TB1> INFO: 2560 events read in total (288ms).
[11:04:13.605] <TB1> INFO: Test took 1186ms.
[11:04:13.607] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:13.914] <TB1> INFO: Expecting 2560 events.
[11:04:14.794] <TB1> INFO: 2560 events read in total (289ms).
[11:04:14.794] <TB1> INFO: Test took 1187ms.
[11:04:14.796] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:15.102] <TB1> INFO: Expecting 2560 events.
[11:04:15.990] <TB1> INFO: 2560 events read in total (296ms).
[11:04:15.990] <TB1> INFO: Test took 1194ms.
[11:04:15.992] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:16.298] <TB1> INFO: Expecting 2560 events.
[11:04:17.186] <TB1> INFO: 2560 events read in total (296ms).
[11:04:17.186] <TB1> INFO: Test took 1194ms.
[11:04:17.190] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:17.495] <TB1> INFO: Expecting 2560 events.
[11:04:18.382] <TB1> INFO: 2560 events read in total (296ms).
[11:04:18.382] <TB1> INFO: Test took 1192ms.
[11:04:18.385] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:18.690] <TB1> INFO: Expecting 2560 events.
[11:04:19.582] <TB1> INFO: 2560 events read in total (300ms).
[11:04:19.582] <TB1> INFO: Test took 1198ms.
[11:04:19.584] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:19.890] <TB1> INFO: Expecting 2560 events.
[11:04:20.774] <TB1> INFO: 2560 events read in total (292ms).
[11:04:20.774] <TB1> INFO: Test took 1190ms.
[11:04:20.777] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:21.082] <TB1> INFO: Expecting 2560 events.
[11:04:21.964] <TB1> INFO: 2560 events read in total (290ms).
[11:04:21.964] <TB1> INFO: Test took 1188ms.
[11:04:21.967] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:22.273] <TB1> INFO: Expecting 2560 events.
[11:04:23.157] <TB1> INFO: 2560 events read in total (292ms).
[11:04:23.158] <TB1> INFO: Test took 1192ms.
[11:04:23.159] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:04:23.466] <TB1> INFO: Expecting 2560 events.
[11:04:24.355] <TB1> INFO: 2560 events read in total (298ms).
[11:04:24.355] <TB1> INFO: Test took 1196ms.
[11:04:24.820] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 654 seconds
[11:04:24.820] <TB1> INFO: PH scale (per ROC): 48 58 51 46 62 59 55 34 50 47 64 48 60 44 58 43
[11:04:24.820] <TB1> INFO: PH offset (per ROC): 114 125 107 88 132 121 101 81 104 110 114 110 115 101 121 84
[11:04:24.828] <TB1> INFO: Decoding statistics:
[11:04:24.828] <TB1> INFO: General information:
[11:04:24.828] <TB1> INFO: 16bit words read: 127882
[11:04:24.828] <TB1> INFO: valid events total: 20480
[11:04:24.828] <TB1> INFO: empty events: 17979
[11:04:24.828] <TB1> INFO: valid events with pixels: 2501
[11:04:24.828] <TB1> INFO: valid pixel hits: 2501
[11:04:24.828] <TB1> INFO: Event errors: 0
[11:04:24.828] <TB1> INFO: start marker: 0
[11:04:24.828] <TB1> INFO: stop marker: 0
[11:04:24.828] <TB1> INFO: overflow: 0
[11:04:24.828] <TB1> INFO: invalid 5bit words: 0
[11:04:24.828] <TB1> INFO: invalid XOR eye diagram: 0
[11:04:24.828] <TB1> INFO: frame (failed synchr.): 0
[11:04:24.828] <TB1> INFO: idle data (no TBM trl): 0
[11:04:24.828] <TB1> INFO: no data (only TBM hdr): 0
[11:04:24.828] <TB1> INFO: TBM errors: 0
[11:04:24.828] <TB1> INFO: flawed TBM headers: 0
[11:04:24.828] <TB1> INFO: flawed TBM trailers: 0
[11:04:24.828] <TB1> INFO: event ID mismatches: 0
[11:04:24.828] <TB1> INFO: ROC errors: 0
[11:04:24.828] <TB1> INFO: missing ROC header(s): 0
[11:04:24.828] <TB1> INFO: misplaced readback start: 0
[11:04:24.828] <TB1> INFO: Pixel decoding errors: 0
[11:04:24.828] <TB1> INFO: pixel data incomplete: 0
[11:04:24.828] <TB1> INFO: pixel address: 0
[11:04:24.828] <TB1> INFO: pulse height fill bit: 0
[11:04:24.828] <TB1> INFO: buffer corruption: 0
[11:04:24.989] <TB1> INFO: ######################################################################
[11:04:24.989] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[11:04:24.989] <TB1> INFO: ######################################################################
[11:04:25.005] <TB1> INFO: scanning low vcal = 10
[11:04:25.244] <TB1> INFO: Expecting 41600 events.
[11:04:28.817] <TB1> INFO: 41600 events read in total (2982ms).
[11:04:28.817] <TB1> INFO: Test took 3811ms.
[11:04:28.820] <TB1> INFO: scanning low vcal = 20
[11:04:29.118] <TB1> INFO: Expecting 41600 events.
[11:04:32.696] <TB1> INFO: 41600 events read in total (2987ms).
[11:04:32.696] <TB1> INFO: Test took 3876ms.
[11:04:32.698] <TB1> INFO: scanning low vcal = 30
[11:04:32.997] <TB1> INFO: Expecting 41600 events.
[11:04:36.697] <TB1> INFO: 41600 events read in total (3108ms).
[11:04:36.698] <TB1> INFO: Test took 4000ms.
[11:04:36.701] <TB1> INFO: scanning low vcal = 40
[11:04:36.996] <TB1> INFO: Expecting 41600 events.
[11:04:41.041] <TB1> INFO: 41600 events read in total (3454ms).
[11:04:41.043] <TB1> INFO: Test took 4342ms.
[11:04:41.047] <TB1> INFO: scanning low vcal = 50
[11:04:41.327] <TB1> INFO: Expecting 41600 events.
[11:04:45.459] <TB1> INFO: 41600 events read in total (3538ms).
[11:04:45.459] <TB1> INFO: Test took 4412ms.
[11:04:45.463] <TB1> INFO: scanning low vcal = 60
[11:04:45.739] <TB1> INFO: Expecting 41600 events.
[11:04:49.762] <TB1> INFO: 41600 events read in total (3431ms).
[11:04:49.763] <TB1> INFO: Test took 4300ms.
[11:04:49.766] <TB1> INFO: scanning low vcal = 70
[11:04:50.043] <TB1> INFO: Expecting 41600 events.
[11:04:54.014] <TB1> INFO: 41600 events read in total (3379ms).
[11:04:54.015] <TB1> INFO: Test took 4249ms.
[11:04:54.018] <TB1> INFO: scanning low vcal = 80
[11:04:54.295] <TB1> INFO: Expecting 41600 events.
[11:04:58.319] <TB1> INFO: 41600 events read in total (3432ms).
[11:04:58.320] <TB1> INFO: Test took 4302ms.
[11:04:58.323] <TB1> INFO: scanning low vcal = 90
[11:04:58.601] <TB1> INFO: Expecting 41600 events.
[11:05:02.592] <TB1> INFO: 41600 events read in total (3397ms).
[11:05:02.593] <TB1> INFO: Test took 4269ms.
[11:05:02.597] <TB1> INFO: scanning low vcal = 100
[11:05:02.887] <TB1> INFO: Expecting 41600 events.
[11:05:06.820] <TB1> INFO: 41600 events read in total (3341ms).
[11:05:06.821] <TB1> INFO: Test took 4224ms.
[11:05:06.825] <TB1> INFO: scanning low vcal = 110
[11:05:07.101] <TB1> INFO: Expecting 41600 events.
[11:05:11.159] <TB1> INFO: 41600 events read in total (3466ms).
[11:05:11.160] <TB1> INFO: Test took 4335ms.
[11:05:11.163] <TB1> INFO: scanning low vcal = 120
[11:05:11.538] <TB1> INFO: Expecting 41600 events.
[11:05:15.540] <TB1> INFO: 41600 events read in total (3410ms).
[11:05:15.541] <TB1> INFO: Test took 4378ms.
[11:05:15.544] <TB1> INFO: scanning low vcal = 130
[11:05:15.820] <TB1> INFO: Expecting 41600 events.
[11:05:19.815] <TB1> INFO: 41600 events read in total (3403ms).
[11:05:19.816] <TB1> INFO: Test took 4272ms.
[11:05:19.822] <TB1> INFO: scanning low vcal = 140
[11:05:20.136] <TB1> INFO: Expecting 41600 events.
[11:05:24.145] <TB1> INFO: 41600 events read in total (3417ms).
[11:05:24.146] <TB1> INFO: Test took 4324ms.
[11:05:24.149] <TB1> INFO: scanning low vcal = 150
[11:05:24.425] <TB1> INFO: Expecting 41600 events.
[11:05:28.425] <TB1> INFO: 41600 events read in total (3408ms).
[11:05:28.426] <TB1> INFO: Test took 4277ms.
[11:05:28.429] <TB1> INFO: scanning low vcal = 160
[11:05:28.739] <TB1> INFO: Expecting 41600 events.
[11:05:32.855] <TB1> INFO: 41600 events read in total (3524ms).
[11:05:32.855] <TB1> INFO: Test took 4426ms.
[11:05:32.861] <TB1> INFO: scanning low vcal = 170
[11:05:33.135] <TB1> INFO: Expecting 41600 events.
[11:05:37.171] <TB1> INFO: 41600 events read in total (3444ms).
[11:05:37.172] <TB1> INFO: Test took 4311ms.
[11:05:37.177] <TB1> INFO: scanning low vcal = 180
[11:05:37.487] <TB1> INFO: Expecting 41600 events.
[11:05:41.573] <TB1> INFO: 41600 events read in total (3494ms).
[11:05:41.574] <TB1> INFO: Test took 4397ms.
[11:05:41.578] <TB1> INFO: scanning low vcal = 190
[11:05:41.892] <TB1> INFO: Expecting 41600 events.
[11:05:45.956] <TB1> INFO: 41600 events read in total (3472ms).
[11:05:45.957] <TB1> INFO: Test took 4379ms.
[11:05:45.960] <TB1> INFO: scanning low vcal = 200
[11:05:46.236] <TB1> INFO: Expecting 41600 events.
[11:05:50.294] <TB1> INFO: 41600 events read in total (3466ms).
[11:05:50.304] <TB1> INFO: Test took 4344ms.
[11:05:50.308] <TB1> INFO: scanning low vcal = 210
[11:05:50.620] <TB1> INFO: Expecting 41600 events.
[11:05:54.692] <TB1> INFO: 41600 events read in total (3480ms).
[11:05:54.693] <TB1> INFO: Test took 4385ms.
[11:05:54.696] <TB1> INFO: scanning low vcal = 220
[11:05:55.011] <TB1> INFO: Expecting 41600 events.
[11:05:59.104] <TB1> INFO: 41600 events read in total (3501ms).
[11:05:59.105] <TB1> INFO: Test took 4408ms.
[11:05:59.109] <TB1> INFO: scanning low vcal = 230
[11:05:59.393] <TB1> INFO: Expecting 41600 events.
[11:06:03.399] <TB1> INFO: 41600 events read in total (3414ms).
[11:06:03.399] <TB1> INFO: Test took 4290ms.
[11:06:03.405] <TB1> INFO: scanning low vcal = 240
[11:06:03.719] <TB1> INFO: Expecting 41600 events.
[11:06:07.817] <TB1> INFO: 41600 events read in total (3506ms).
[11:06:07.818] <TB1> INFO: Test took 4413ms.
[11:06:07.821] <TB1> INFO: scanning low vcal = 250
[11:06:08.097] <TB1> INFO: Expecting 41600 events.
[11:06:12.151] <TB1> INFO: 41600 events read in total (3462ms).
[11:06:12.152] <TB1> INFO: Test took 4331ms.
[11:06:12.156] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[11:06:12.468] <TB1> INFO: Expecting 41600 events.
[11:06:16.513] <TB1> INFO: 41600 events read in total (3453ms).
[11:06:16.514] <TB1> INFO: Test took 4357ms.
[11:06:16.518] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[11:06:16.794] <TB1> INFO: Expecting 41600 events.
[11:06:20.891] <TB1> INFO: 41600 events read in total (3506ms).
[11:06:20.892] <TB1> INFO: Test took 4374ms.
[11:06:20.896] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[11:06:21.206] <TB1> INFO: Expecting 41600 events.
[11:06:25.211] <TB1> INFO: 41600 events read in total (3414ms).
[11:06:25.212] <TB1> INFO: Test took 4316ms.
[11:06:25.216] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[11:06:25.492] <TB1> INFO: Expecting 41600 events.
[11:06:29.448] <TB1> INFO: 41600 events read in total (3364ms).
[11:06:29.449] <TB1> INFO: Test took 4233ms.
[11:06:29.452] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[11:06:29.728] <TB1> INFO: Expecting 41600 events.
[11:06:33.692] <TB1> INFO: 41600 events read in total (3372ms).
[11:06:33.692] <TB1> INFO: Test took 4240ms.
[11:06:34.104] <TB1> INFO: PixTestGainPedestal::measure() done
[11:07:07.851] <TB1> INFO: PixTestGainPedestal::fit() done
[11:07:07.851] <TB1> INFO: non-linearity mean: 0.938 0.978 0.937 0.938 0.988 0.983 0.977 0.991 0.960 0.923 0.985 0.974 0.955 0.939 0.984 0.940
[11:07:07.851] <TB1> INFO: non-linearity RMS: 0.059 0.004 0.100 0.142 0.002 0.003 0.014 0.169 0.044 0.087 0.004 0.008 0.045 0.078 0.003 0.159
[11:07:07.851] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr35_C0.dat
[11:07:07.864] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr35_C1.dat
[11:07:07.878] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr35_C2.dat
[11:07:07.891] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr35_C3.dat
[11:07:07.905] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr35_C4.dat
[11:07:07.918] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr35_C5.dat
[11:07:07.932] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr35_C6.dat
[11:07:07.945] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr35_C7.dat
[11:07:07.959] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr35_C8.dat
[11:07:07.972] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr35_C9.dat
[11:07:07.986] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr35_C10.dat
[11:07:07.999] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr35_C11.dat
[11:07:08.013] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr35_C12.dat
[11:07:08.026] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr35_C13.dat
[11:07:08.040] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr35_C14.dat
[11:07:08.053] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//000_Fulltest_m20//phCalibrationFitErr35_C15.dat
[11:07:08.066] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 163 seconds
[11:07:08.066] <TB1> INFO: Decoding statistics:
[11:07:08.066] <TB1> INFO: General information:
[11:07:08.066] <TB1> INFO: 16bit words read: 3327210
[11:07:08.066] <TB1> INFO: valid events total: 332800
[11:07:08.066] <TB1> INFO: empty events: 1
[11:07:08.066] <TB1> INFO: valid events with pixels: 332799
[11:07:08.066] <TB1> INFO: valid pixel hits: 665205
[11:07:08.066] <TB1> INFO: Event errors: 0
[11:07:08.066] <TB1> INFO: start marker: 0
[11:07:08.066] <TB1> INFO: stop marker: 0
[11:07:08.066] <TB1> INFO: overflow: 0
[11:07:08.066] <TB1> INFO: invalid 5bit words: 0
[11:07:08.066] <TB1> INFO: invalid XOR eye diagram: 0
[11:07:08.066] <TB1> INFO: frame (failed synchr.): 0
[11:07:08.066] <TB1> INFO: idle data (no TBM trl): 0
[11:07:08.066] <TB1> INFO: no data (only TBM hdr): 0
[11:07:08.066] <TB1> INFO: TBM errors: 0
[11:07:08.066] <TB1> INFO: flawed TBM headers: 0
[11:07:08.066] <TB1> INFO: flawed TBM trailers: 0
[11:07:08.066] <TB1> INFO: event ID mismatches: 0
[11:07:08.066] <TB1> INFO: ROC errors: 0
[11:07:08.066] <TB1> INFO: missing ROC header(s): 0
[11:07:08.066] <TB1> INFO: misplaced readback start: 0
[11:07:08.066] <TB1> INFO: Pixel decoding errors: 0
[11:07:08.066] <TB1> INFO: pixel data incomplete: 0
[11:07:08.067] <TB1> INFO: pixel address: 0
[11:07:08.067] <TB1> INFO: pulse height fill bit: 0
[11:07:08.067] <TB1> INFO: buffer corruption: 0
[11:07:08.083] <TB1> INFO: Decoding statistics:
[11:07:08.083] <TB1> INFO: General information:
[11:07:08.083] <TB1> INFO: 16bit words read: 3456628
[11:07:08.083] <TB1> INFO: valid events total: 353536
[11:07:08.083] <TB1> INFO: empty events: 18236
[11:07:08.083] <TB1> INFO: valid events with pixels: 335300
[11:07:08.083] <TB1> INFO: valid pixel hits: 667706
[11:07:08.083] <TB1> INFO: Event errors: 0
[11:07:08.083] <TB1> INFO: start marker: 0
[11:07:08.083] <TB1> INFO: stop marker: 0
[11:07:08.083] <TB1> INFO: overflow: 0
[11:07:08.083] <TB1> INFO: invalid 5bit words: 0
[11:07:08.083] <TB1> INFO: invalid XOR eye diagram: 0
[11:07:08.083] <TB1> INFO: frame (failed synchr.): 0
[11:07:08.083] <TB1> INFO: idle data (no TBM trl): 0
[11:07:08.083] <TB1> INFO: no data (only TBM hdr): 0
[11:07:08.083] <TB1> INFO: TBM errors: 0
[11:07:08.083] <TB1> INFO: flawed TBM headers: 0
[11:07:08.083] <TB1> INFO: flawed TBM trailers: 0
[11:07:08.083] <TB1> INFO: event ID mismatches: 0
[11:07:08.083] <TB1> INFO: ROC errors: 0
[11:07:08.083] <TB1> INFO: missing ROC header(s): 0
[11:07:08.083] <TB1> INFO: misplaced readback start: 0
[11:07:08.083] <TB1> INFO: Pixel decoding errors: 0
[11:07:08.083] <TB1> INFO: pixel data incomplete: 0
[11:07:08.083] <TB1> INFO: pixel address: 0
[11:07:08.083] <TB1> INFO: pulse height fill bit: 0
[11:07:08.083] <TB1> INFO: buffer corruption: 0
[11:07:08.083] <TB1> INFO: enter test to run
[11:07:08.083] <TB1> INFO: test: exit no parameter change
[11:07:08.205] <TB1> QUIET: Connection to board 154 closed.
[11:07:08.206] <TB1> INFO: pXar: this is the end, my friend