[11:14:57.040] <TB1> INFO: *** Welcome to pxar ***
[11:14:57.040] <TB1> INFO: *** Today: 2016/11/09
[11:14:57.048] <TB1> INFO: *** Version: c8ba-dirty
[11:14:57.048] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C15.dat
[11:14:57.048] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//tbmParameters_C1b.dat
[11:14:57.049] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//defaultMaskFile.dat
[11:14:57.049] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters_C15.dat
[11:14:57.110] <TB1> INFO: clk: 4
[11:14:57.110] <TB1> INFO: ctr: 4
[11:14:57.110] <TB1> INFO: sda: 19
[11:14:57.110] <TB1> INFO: tin: 9
[11:14:57.110] <TB1> INFO: level: 15
[11:14:57.110] <TB1> INFO: triggerdelay: 0
[11:14:57.110] <TB1> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[11:14:57.110] <TB1> INFO: Log level: INFO
[11:14:57.119] <TB1> INFO: Found DTB DTB_WXC03A
[11:14:57.130] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[11:14:57.132] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
------------------------------------------------------
[11:14:57.134] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[11:14:58.621] <TB1> INFO: DUT info:
[11:14:58.621] <TB1> INFO: The DUT currently contains the following objects:
[11:14:58.621] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[11:14:58.621] <TB1> INFO: TBM Core alpha (0): 7 registers set
[11:14:58.621] <TB1> INFO: TBM Core beta (1): 7 registers set
[11:14:58.621] <TB1> INFO: TBM Core alpha (2): 7 registers set
[11:14:58.621] <TB1> INFO: TBM Core beta (3): 7 registers set
[11:14:58.621] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:14:58.621] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:58.621] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:58.621] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:58.621] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:58.621] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:58.621] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:58.621] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:58.621] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:58.621] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:58.621] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:58.621] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:58.621] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:58.622] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:58.622] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:58.622] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:58.622] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:14:59.023] <TB1> INFO: enter 'restricted' command line mode
[11:14:59.023] <TB1> INFO: enter test to run
[11:14:59.023] <TB1> INFO: test: pretest no parameter change
[11:14:59.023] <TB1> INFO: running: pretest
[11:14:59.029] <TB1> INFO: ######################################################################
[11:14:59.029] <TB1> INFO: PixTestPretest::doTest()
[11:14:59.029] <TB1> INFO: ######################################################################
[11:14:59.031] <TB1> INFO: ----------------------------------------------------------------------
[11:14:59.031] <TB1> INFO: PixTestPretest::programROC()
[11:14:59.031] <TB1> INFO: ----------------------------------------------------------------------
[11:15:17.044] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:15:17.044] <TB1> INFO: IA differences per ROC: 16.9 18.5 20.9 17.7 19.3 16.9 16.9 18.5 17.7 19.3 17.7 16.9 20.1 17.7 17.7 16.9
[11:15:17.112] <TB1> INFO: ----------------------------------------------------------------------
[11:15:17.112] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:15:17.112] <TB1> INFO: ----------------------------------------------------------------------
[11:15:38.358] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 396.3 mA = 24.7688 mA/ROC
[11:15:38.358] <TB1> INFO: i(loss) [mA/ROC]: 19.3 19.3 20.1 20.9 19.3 20.1 20.1 19.3 20.1 20.1 20.1 19.3 19.3 20.1 17.7 19.3
[11:15:38.393] <TB1> INFO: ----------------------------------------------------------------------
[11:15:38.393] <TB1> INFO: PixTestPretest::findTiming()
[11:15:38.393] <TB1> INFO: ----------------------------------------------------------------------
[11:15:38.393] <TB1> INFO: PixTestCmd::init()

[11:16:09.652] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[11:16:09.652] <TB1> INFO: (success/tries = 100/100), width = 3
[11:16:11.172] <TB1> INFO: ----------------------------------------------------------------------
[11:16:11.172] <TB1> INFO: PixTestPretest::findWorkingPixel()
[11:16:11.172] <TB1> INFO: ----------------------------------------------------------------------
[11:16:11.265] <TB1> INFO: Expecting 231680 events.
[11:16:21.084] <TB1> INFO: 231680 events read in total (9227ms).
[11:16:21.094] <TB1> INFO: Test took 9918ms.
[11:16:21.335] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:16:21.365] <TB1> INFO: ----------------------------------------------------------------------
[11:16:21.365] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[11:16:21.366] <TB1> INFO: ----------------------------------------------------------------------
[11:16:21.458] <TB1> INFO: Expecting 231680 events.
[11:16:31.246] <TB1> INFO: 231680 events read in total (9196ms).
[11:16:31.260] <TB1> INFO: Test took 9890ms.
[11:16:31.516] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[11:16:31.516] <TB1> INFO: CalDel: 90 88 91 85 91 93 91 111 98 88 103 99 93 83 83 72
[11:16:31.516] <TB1> INFO: VthrComp: 53 51 51 56 54 56 53 52 57 55 56 51 54 54 51 51
[11:16:31.519] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C0.dat
[11:16:31.519] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C1.dat
[11:16:31.519] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C2.dat
[11:16:31.519] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C3.dat
[11:16:31.519] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C4.dat
[11:16:31.519] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C5.dat
[11:16:31.519] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C6.dat
[11:16:31.519] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C7.dat
[11:16:31.519] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C8.dat
[11:16:31.520] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C9.dat
[11:16:31.520] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C10.dat
[11:16:31.520] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C11.dat
[11:16:31.520] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C12.dat
[11:16:31.520] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C13.dat
[11:16:31.520] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C14.dat
[11:16:31.520] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters_C15.dat
[11:16:31.520] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//tbmParameters_C0a.dat
[11:16:31.520] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//tbmParameters_C0b.dat
[11:16:31.520] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//tbmParameters_C1a.dat
[11:16:31.520] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//tbmParameters_C1b.dat
[11:16:31.521] <TB1> INFO: PixTestPretest::doTest() done, duration: 92 seconds
[11:16:31.574] <TB1> INFO: enter test to run
[11:16:31.574] <TB1> INFO: test: fulltest no parameter change
[11:16:31.574] <TB1> INFO: running: fulltest
[11:16:31.574] <TB1> INFO: ######################################################################
[11:16:31.574] <TB1> INFO: PixTestFullTest::doTest()
[11:16:31.574] <TB1> INFO: ######################################################################
[11:16:31.576] <TB1> INFO: ######################################################################
[11:16:31.576] <TB1> INFO: PixTestAlive::doTest()
[11:16:31.576] <TB1> INFO: ######################################################################
[11:16:31.577] <TB1> INFO: ----------------------------------------------------------------------
[11:16:31.577] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:16:31.577] <TB1> INFO: ----------------------------------------------------------------------
[11:16:31.818] <TB1> INFO: Expecting 41600 events.
[11:16:35.313] <TB1> INFO: 41600 events read in total (2904ms).
[11:16:35.314] <TB1> INFO: Test took 3735ms.
[11:16:35.542] <TB1> INFO: PixTestAlive::aliveTest() done
[11:16:35.543] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:16:35.544] <TB1> INFO: ----------------------------------------------------------------------
[11:16:35.544] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:16:35.544] <TB1> INFO: ----------------------------------------------------------------------
[11:16:35.920] <TB1> INFO: Expecting 41600 events.
[11:16:38.868] <TB1> INFO: 41600 events read in total (2356ms).
[11:16:38.869] <TB1> INFO: Test took 3321ms.
[11:16:38.869] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:16:39.106] <TB1> INFO: PixTestAlive::maskTest() done
[11:16:39.106] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:16:39.108] <TB1> INFO: ----------------------------------------------------------------------
[11:16:39.108] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:16:39.108] <TB1> INFO: ----------------------------------------------------------------------
[11:16:39.354] <TB1> INFO: Expecting 41600 events.
[11:16:42.943] <TB1> INFO: 41600 events read in total (2997ms).
[11:16:42.944] <TB1> INFO: Test took 3835ms.
[11:16:43.172] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[11:16:43.172] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:16:43.172] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:16:43.172] <TB1> INFO: Decoding statistics:
[11:16:43.172] <TB1> INFO: General information:
[11:16:43.172] <TB1> INFO: 16bit words read: 0
[11:16:43.172] <TB1> INFO: valid events total: 0
[11:16:43.172] <TB1> INFO: empty events: 0
[11:16:43.172] <TB1> INFO: valid events with pixels: 0
[11:16:43.172] <TB1> INFO: valid pixel hits: 0
[11:16:43.172] <TB1> INFO: Event errors: 0
[11:16:43.172] <TB1> INFO: start marker: 0
[11:16:43.172] <TB1> INFO: stop marker: 0
[11:16:43.172] <TB1> INFO: overflow: 0
[11:16:43.172] <TB1> INFO: invalid 5bit words: 0
[11:16:43.172] <TB1> INFO: invalid XOR eye diagram: 0
[11:16:43.172] <TB1> INFO: frame (failed synchr.): 0
[11:16:43.172] <TB1> INFO: idle data (no TBM trl): 0
[11:16:43.172] <TB1> INFO: no data (only TBM hdr): 0
[11:16:43.172] <TB1> INFO: TBM errors: 0
[11:16:43.172] <TB1> INFO: flawed TBM headers: 0
[11:16:43.172] <TB1> INFO: flawed TBM trailers: 0
[11:16:43.172] <TB1> INFO: event ID mismatches: 0
[11:16:43.172] <TB1> INFO: ROC errors: 0
[11:16:43.172] <TB1> INFO: missing ROC header(s): 0
[11:16:43.172] <TB1> INFO: misplaced readback start: 0
[11:16:43.172] <TB1> INFO: Pixel decoding errors: 0
[11:16:43.172] <TB1> INFO: pixel data incomplete: 0
[11:16:43.172] <TB1> INFO: pixel address: 0
[11:16:43.172] <TB1> INFO: pulse height fill bit: 0
[11:16:43.172] <TB1> INFO: buffer corruption: 0
[11:16:43.177] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C15.dat
[11:16:43.177] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[11:16:43.177] <TB1> INFO: ######################################################################
[11:16:43.177] <TB1> INFO: PixTestReadback::doTest()
[11:16:43.178] <TB1> INFO: ######################################################################
[11:16:43.178] <TB1> INFO: ----------------------------------------------------------------------
[11:16:43.178] <TB1> INFO: PixTestReadback::CalibrateVd()
[11:16:43.178] <TB1> INFO: ----------------------------------------------------------------------
[11:16:53.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C0.dat
[11:16:53.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C1.dat
[11:16:53.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C2.dat
[11:16:53.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C3.dat
[11:16:53.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C4.dat
[11:16:53.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C5.dat
[11:16:53.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C6.dat
[11:16:53.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C7.dat
[11:16:53.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C8.dat
[11:16:53.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C9.dat
[11:16:53.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C10.dat
[11:16:53.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C11.dat
[11:16:53.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C12.dat
[11:16:53.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C13.dat
[11:16:53.098] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C14.dat
[11:16:53.099] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C15.dat
[11:16:53.125] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:16:53.125] <TB1> INFO: ----------------------------------------------------------------------
[11:16:53.125] <TB1> INFO: PixTestReadback::CalibrateVa()
[11:16:53.125] <TB1> INFO: ----------------------------------------------------------------------
[11:17:03.022] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C0.dat
[11:17:03.022] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C1.dat
[11:17:03.022] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C2.dat
[11:17:03.022] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C3.dat
[11:17:03.022] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C4.dat
[11:17:03.022] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C5.dat
[11:17:03.023] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C6.dat
[11:17:03.023] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C7.dat
[11:17:03.023] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C8.dat
[11:17:03.023] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C9.dat
[11:17:03.023] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C10.dat
[11:17:03.023] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C11.dat
[11:17:03.023] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C12.dat
[11:17:03.023] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C13.dat
[11:17:03.023] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C14.dat
[11:17:03.023] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C15.dat
[11:17:03.051] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:17:03.051] <TB1> INFO: ----------------------------------------------------------------------
[11:17:03.051] <TB1> INFO: PixTestReadback::readbackVbg()
[11:17:03.051] <TB1> INFO: ----------------------------------------------------------------------
[11:17:10.691] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:17:10.691] <TB1> INFO: ----------------------------------------------------------------------
[11:17:10.691] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[11:17:10.691] <TB1> INFO: ----------------------------------------------------------------------
[11:17:10.691] <TB1> INFO: Vbg will be calibrated using Vd calibration
[11:17:10.691] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 153.8calibrated Vbg = 1.20462 :::*/*/*/*/
[11:17:10.691] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 167.4calibrated Vbg = 1.19704 :::*/*/*/*/
[11:17:10.691] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 152.6calibrated Vbg = 1.19686 :::*/*/*/*/
[11:17:10.691] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 156.1calibrated Vbg = 1.19101 :::*/*/*/*/
[11:17:10.691] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 156calibrated Vbg = 1.19128 :::*/*/*/*/
[11:17:10.691] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 154calibrated Vbg = 1.20255 :::*/*/*/*/
[11:17:10.691] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 154.6calibrated Vbg = 1.19965 :::*/*/*/*/
[11:17:10.691] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 156calibrated Vbg = 1.20476 :::*/*/*/*/
[11:17:10.691] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 153.9calibrated Vbg = 1.19901 :::*/*/*/*/
[11:17:10.691] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 155.8calibrated Vbg = 1.19121 :::*/*/*/*/
[11:17:10.691] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 159.1calibrated Vbg = 1.18978 :::*/*/*/*/
[11:17:10.691] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 155.6calibrated Vbg = 1.19337 :::*/*/*/*/
[11:17:10.691] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 153.1calibrated Vbg = 1.19301 :::*/*/*/*/
[11:17:10.691] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 154.5calibrated Vbg = 1.19811 :::*/*/*/*/
[11:17:10.691] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 162.7calibrated Vbg = 1.19474 :::*/*/*/*/
[11:17:10.691] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 156.6calibrated Vbg = 1.19847 :::*/*/*/*/
[11:17:10.693] <TB1> INFO: ----------------------------------------------------------------------
[11:17:10.693] <TB1> INFO: PixTestReadback::CalibrateIa()
[11:17:10.693] <TB1> INFO: ----------------------------------------------------------------------
[11:19:51.012] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C0.dat
[11:19:51.012] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C1.dat
[11:19:51.013] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C2.dat
[11:19:51.013] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C3.dat
[11:19:51.013] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C4.dat
[11:19:51.013] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C5.dat
[11:19:51.013] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C6.dat
[11:19:51.013] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C7.dat
[11:19:51.013] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C8.dat
[11:19:51.013] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C9.dat
[11:19:51.013] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C10.dat
[11:19:51.013] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C11.dat
[11:19:51.013] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C12.dat
[11:19:51.013] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C13.dat
[11:19:51.013] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C14.dat
[11:19:51.014] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//readbackCal_C15.dat
[11:19:51.042] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:19:51.043] <TB1> INFO: PixTestReadback::doTest() done
[11:19:51.043] <TB1> INFO: Decoding statistics:
[11:19:51.043] <TB1> INFO: General information:
[11:19:51.043] <TB1> INFO: 16bit words read: 1536
[11:19:51.043] <TB1> INFO: valid events total: 256
[11:19:51.043] <TB1> INFO: empty events: 256
[11:19:51.043] <TB1> INFO: valid events with pixels: 0
[11:19:51.043] <TB1> INFO: valid pixel hits: 0
[11:19:51.043] <TB1> INFO: Event errors: 0
[11:19:51.043] <TB1> INFO: start marker: 0
[11:19:51.043] <TB1> INFO: stop marker: 0
[11:19:51.043] <TB1> INFO: overflow: 0
[11:19:51.043] <TB1> INFO: invalid 5bit words: 0
[11:19:51.043] <TB1> INFO: invalid XOR eye diagram: 0
[11:19:51.044] <TB1> INFO: frame (failed synchr.): 0
[11:19:51.044] <TB1> INFO: idle data (no TBM trl): 0
[11:19:51.044] <TB1> INFO: no data (only TBM hdr): 0
[11:19:51.044] <TB1> INFO: TBM errors: 0
[11:19:51.044] <TB1> INFO: flawed TBM headers: 0
[11:19:51.044] <TB1> INFO: flawed TBM trailers: 0
[11:19:51.044] <TB1> INFO: event ID mismatches: 0
[11:19:51.044] <TB1> INFO: ROC errors: 0
[11:19:51.044] <TB1> INFO: missing ROC header(s): 0
[11:19:51.044] <TB1> INFO: misplaced readback start: 0
[11:19:51.044] <TB1> INFO: Pixel decoding errors: 0
[11:19:51.044] <TB1> INFO: pixel data incomplete: 0
[11:19:51.044] <TB1> INFO: pixel address: 0
[11:19:51.044] <TB1> INFO: pulse height fill bit: 0
[11:19:51.044] <TB1> INFO: buffer corruption: 0
[11:19:51.110] <TB1> INFO: ######################################################################
[11:19:51.110] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[11:19:51.110] <TB1> INFO: ######################################################################
[11:19:51.113] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[11:19:51.134] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:19:51.134] <TB1> INFO: run 1 of 1
[11:19:51.371] <TB1> INFO: Expecting 3120000 events.
[11:20:23.089] <TB1> INFO: 675555 events read in total (31126ms).
[11:20:53.836] <TB1> INFO: 1345110 events read in total (61873ms).











[11:21:25.699] <TB1> INFO: 2011420 events read in total (93736ms).











[11:21:57.496] <TB1> INFO: 2678390 events read in total (125533ms).











[11:22:19.081] <TB1> INFO: 3120000 events read in total (147118ms).
[11:22:19.191] <TB1> INFO: Test took 148057ms.
[11:22:45.090] <TB1> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 173 seconds
[11:22:45.090] <TB1> INFO: number of dead bumps (per ROC): 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
[11:22:45.090] <TB1> INFO: separation cut (per ROC): 117 117 122 128 120 114 105 106 114 114 110 107 116 108 103 126
[11:22:45.090] <TB1> INFO: Decoding statistics:
[11:22:45.090] <TB1> INFO: General information:
[11:22:45.090] <TB1> INFO: 16bit words read: 0
[11:22:45.090] <TB1> INFO: valid events total: 0
[11:22:45.090] <TB1> INFO: empty events: 0
[11:22:45.090] <TB1> INFO: valid events with pixels: 0
[11:22:45.090] <TB1> INFO: valid pixel hits: 0
[11:22:45.090] <TB1> INFO: Event errors: 0
[11:22:45.090] <TB1> INFO: start marker: 0
[11:22:45.090] <TB1> INFO: stop marker: 0
[11:22:45.090] <TB1> INFO: overflow: 0
[11:22:45.090] <TB1> INFO: invalid 5bit words: 0
[11:22:45.090] <TB1> INFO: invalid XOR eye diagram: 0
[11:22:45.090] <TB1> INFO: frame (failed synchr.): 0
[11:22:45.090] <TB1> INFO: idle data (no TBM trl): 0
[11:22:45.090] <TB1> INFO: no data (only TBM hdr): 0
[11:22:45.090] <TB1> INFO: TBM errors: 0
[11:22:45.090] <TB1> INFO: flawed TBM headers: 0
[11:22:45.090] <TB1> INFO: flawed TBM trailers: 0
[11:22:45.090] <TB1> INFO: event ID mismatches: 0
[11:22:45.090] <TB1> INFO: ROC errors: 0
[11:22:45.090] <TB1> INFO: missing ROC header(s): 0
[11:22:45.090] <TB1> INFO: misplaced readback start: 0
[11:22:45.090] <TB1> INFO: Pixel decoding errors: 0
[11:22:45.090] <TB1> INFO: pixel data incomplete: 0
[11:22:45.090] <TB1> INFO: pixel address: 0
[11:22:45.090] <TB1> INFO: pulse height fill bit: 0
[11:22:45.090] <TB1> INFO: buffer corruption: 0
[11:22:45.128] <TB1> INFO: ######################################################################
[11:22:45.128] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:22:45.128] <TB1> INFO: ######################################################################
[11:22:45.128] <TB1> INFO: ----------------------------------------------------------------------
[11:22:45.128] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:22:45.128] <TB1> INFO: ----------------------------------------------------------------------
[11:22:45.128] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[11:22:45.143] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[11:22:45.143] <TB1> INFO: run 1 of 1
[11:22:45.385] <TB1> INFO: Expecting 36608000 events.
[11:23:10.855] <TB1> INFO: 725000 events read in total (24879ms).
[11:23:34.825] <TB1> INFO: 1424700 events read in total (48849ms).
[11:23:59.169] <TB1> INFO: 2129250 events read in total (73193ms).
[11:24:23.654] <TB1> INFO: 2829750 events read in total (97678ms).
[11:24:47.950] <TB1> INFO: 3533400 events read in total (121974ms).
[11:25:12.365] <TB1> INFO: 4229500 events read in total (146389ms).
[11:25:36.424] <TB1> INFO: 4931650 events read in total (170448ms).
[11:26:00.678] <TB1> INFO: 5628050 events read in total (194702ms).
[11:26:25.100] <TB1> INFO: 6327050 events read in total (219124ms).
[11:26:49.503] <TB1> INFO: 7020600 events read in total (243527ms).
[11:27:13.841] <TB1> INFO: 7720800 events read in total (267865ms).
[11:27:37.844] <TB1> INFO: 8414250 events read in total (291868ms).
[11:28:02.556] <TB1> INFO: 9116850 events read in total (316580ms).
[11:28:27.107] <TB1> INFO: 9812500 events read in total (341131ms).
[11:28:51.416] <TB1> INFO: 10511200 events read in total (365440ms).
[11:29:15.881] <TB1> INFO: 11204700 events read in total (389905ms).
[11:29:40.463] <TB1> INFO: 11900350 events read in total (414487ms).
[11:30:04.940] <TB1> INFO: 12591150 events read in total (438964ms).
[11:30:30.042] <TB1> INFO: 13287400 events read in total (464066ms).
[11:30:54.989] <TB1> INFO: 13979450 events read in total (489013ms).
[11:31:18.878] <TB1> INFO: 14675450 events read in total (512902ms).
[11:31:42.722] <TB1> INFO: 15366550 events read in total (536746ms).
[11:32:06.789] <TB1> INFO: 16061700 events read in total (560813ms).
[11:32:30.707] <TB1> INFO: 16753250 events read in total (584731ms).
[11:32:54.626] <TB1> INFO: 17446500 events read in total (608650ms).
[11:33:18.365] <TB1> INFO: 18134900 events read in total (632389ms).
[11:33:42.235] <TB1> INFO: 18822700 events read in total (656259ms).
[11:34:06.041] <TB1> INFO: 19509950 events read in total (680065ms).
[11:34:29.571] <TB1> INFO: 20199600 events read in total (703595ms).
[11:34:53.395] <TB1> INFO: 20886450 events read in total (727419ms).
[11:35:16.841] <TB1> INFO: 21574800 events read in total (750865ms).
[11:35:40.396] <TB1> INFO: 22263100 events read in total (774420ms).
[11:36:04.054] <TB1> INFO: 22950500 events read in total (798078ms).
[11:36:27.552] <TB1> INFO: 23636000 events read in total (821576ms).
[11:36:51.717] <TB1> INFO: 24323550 events read in total (845741ms).
[11:37:15.318] <TB1> INFO: 25011300 events read in total (869342ms).
[11:37:39.110] <TB1> INFO: 25698500 events read in total (893134ms).
[11:38:03.554] <TB1> INFO: 26387500 events read in total (917578ms).
[11:38:26.808] <TB1> INFO: 27074200 events read in total (940832ms).
[11:38:50.894] <TB1> INFO: 27758400 events read in total (964918ms).
[11:39:14.658] <TB1> INFO: 28441400 events read in total (988682ms).
[11:39:38.873] <TB1> INFO: 29126550 events read in total (1012897ms).
[11:40:03.088] <TB1> INFO: 29810550 events read in total (1037112ms).
[11:40:26.459] <TB1> INFO: 30494600 events read in total (1060483ms).
[11:40:51.042] <TB1> INFO: 31176400 events read in total (1085066ms).
[11:41:14.996] <TB1> INFO: 31863200 events read in total (1109020ms).
[11:41:38.608] <TB1> INFO: 32547600 events read in total (1132632ms).
[11:42:02.954] <TB1> INFO: 33233950 events read in total (1156978ms).
[11:42:26.677] <TB1> INFO: 33919050 events read in total (1180701ms).
[11:42:50.521] <TB1> INFO: 34607300 events read in total (1204545ms).
[11:43:14.666] <TB1> INFO: 35292050 events read in total (1228690ms).
[11:43:38.278] <TB1> INFO: 35981500 events read in total (1252302ms).
[11:43:59.901] <TB1> INFO: 36608000 events read in total (1273925ms).
[11:43:59.976] <TB1> INFO: Test took 1274830ms.
[11:44:00.404] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:44:02.397] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:44:04.464] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:44:06.538] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:44:08.856] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:44:11.076] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:44:13.244] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:44:15.314] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:44:17.125] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:44:19.069] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:44:21.219] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:44:23.405] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:44:25.516] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:44:27.867] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:44:29.885] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:44:31.880] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[11:44:33.474] <TB1> INFO: PixTestScurves::scurves() done
[11:44:33.474] <TB1> INFO: Vcal mean: 133.29 134.91 132.36 137.81 139.97 134.76 129.23 128.62 139.16 126.14 132.86 132.60 133.36 124.35 119.40 133.18
[11:44:33.474] <TB1> INFO: Vcal RMS: 6.07 5.56 6.34 6.32 6.09 6.26 6.24 6.23 6.77 7.46 6.33 5.79 6.89 6.61 6.45 6.52
[11:44:33.474] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1308 seconds
[11:44:33.475] <TB1> INFO: Decoding statistics:
[11:44:33.475] <TB1> INFO: General information:
[11:44:33.475] <TB1> INFO: 16bit words read: 0
[11:44:33.475] <TB1> INFO: valid events total: 0
[11:44:33.475] <TB1> INFO: empty events: 0
[11:44:33.475] <TB1> INFO: valid events with pixels: 0
[11:44:33.475] <TB1> INFO: valid pixel hits: 0
[11:44:33.475] <TB1> INFO: Event errors: 0
[11:44:33.475] <TB1> INFO: start marker: 0
[11:44:33.475] <TB1> INFO: stop marker: 0
[11:44:33.475] <TB1> INFO: overflow: 0
[11:44:33.475] <TB1> INFO: invalid 5bit words: 0
[11:44:33.475] <TB1> INFO: invalid XOR eye diagram: 0
[11:44:33.475] <TB1> INFO: frame (failed synchr.): 0
[11:44:33.475] <TB1> INFO: idle data (no TBM trl): 0
[11:44:33.475] <TB1> INFO: no data (only TBM hdr): 0
[11:44:33.475] <TB1> INFO: TBM errors: 0
[11:44:33.475] <TB1> INFO: flawed TBM headers: 0
[11:44:33.475] <TB1> INFO: flawed TBM trailers: 0
[11:44:33.475] <TB1> INFO: event ID mismatches: 0
[11:44:33.475] <TB1> INFO: ROC errors: 0
[11:44:33.475] <TB1> INFO: missing ROC header(s): 0
[11:44:33.475] <TB1> INFO: misplaced readback start: 0
[11:44:33.475] <TB1> INFO: Pixel decoding errors: 0
[11:44:33.475] <TB1> INFO: pixel data incomplete: 0
[11:44:33.475] <TB1> INFO: pixel address: 0
[11:44:33.475] <TB1> INFO: pulse height fill bit: 0
[11:44:33.475] <TB1> INFO: buffer corruption: 0
[11:44:33.574] <TB1> INFO: ######################################################################
[11:44:33.574] <TB1> INFO: PixTestTrim::doTest()
[11:44:33.574] <TB1> INFO: ######################################################################
[11:44:33.575] <TB1> INFO: ----------------------------------------------------------------------
[11:44:33.576] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[11:44:33.576] <TB1> INFO: ----------------------------------------------------------------------
[11:44:33.655] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[11:44:33.655] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:44:33.672] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:44:33.672] <TB1> INFO: run 1 of 1
[11:44:34.049] <TB1> INFO: Expecting 5025280 events.
[11:45:05.820] <TB1> INFO: 842328 events read in total (31151ms).
[11:45:36.703] <TB1> INFO: 1682352 events read in total (62034ms).
[11:46:07.647] <TB1> INFO: 2519984 events read in total (92978ms).
[11:46:39.484] <TB1> INFO: 3353816 events read in total (124815ms).
[11:47:11.213] <TB1> INFO: 4184552 events read in total (156544ms).
[11:47:43.415] <TB1> INFO: 5013704 events read in total (188746ms).
[11:47:44.311] <TB1> INFO: 5025280 events read in total (189642ms).
[11:47:44.394] <TB1> INFO: Test took 190723ms.
[11:47:57.202] <TB1> INFO: ROC 0 VthrComp = 134
[11:47:57.202] <TB1> INFO: ROC 1 VthrComp = 131
[11:47:57.202] <TB1> INFO: ROC 2 VthrComp = 129
[11:47:57.202] <TB1> INFO: ROC 3 VthrComp = 134
[11:47:57.202] <TB1> INFO: ROC 4 VthrComp = 130
[11:47:57.202] <TB1> INFO: ROC 5 VthrComp = 130
[11:47:57.203] <TB1> INFO: ROC 6 VthrComp = 123
[11:47:57.203] <TB1> INFO: ROC 7 VthrComp = 123
[11:47:57.203] <TB1> INFO: ROC 8 VthrComp = 135
[11:47:57.203] <TB1> INFO: ROC 9 VthrComp = 128
[11:47:57.204] <TB1> INFO: ROC 10 VthrComp = 129
[11:47:57.207] <TB1> INFO: ROC 11 VthrComp = 121
[11:47:57.207] <TB1> INFO: ROC 12 VthrComp = 131
[11:47:57.207] <TB1> INFO: ROC 13 VthrComp = 128
[11:47:57.208] <TB1> INFO: ROC 14 VthrComp = 112
[11:47:57.208] <TB1> INFO: ROC 15 VthrComp = 134
[11:47:57.537] <TB1> INFO: Expecting 41600 events.
[11:48:01.286] <TB1> INFO: 41600 events read in total (3157ms).
[11:48:01.287] <TB1> INFO: Test took 4077ms.
[11:48:01.305] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[11:48:01.305] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:48:01.323] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:48:01.324] <TB1> INFO: run 1 of 1
[11:48:01.668] <TB1> INFO: Expecting 5025280 events.
[11:48:30.027] <TB1> INFO: 595984 events read in total (27767ms).
[11:48:55.544] <TB1> INFO: 1190616 events read in total (53284ms).
[11:49:21.696] <TB1> INFO: 1786056 events read in total (79436ms).
[11:49:48.869] <TB1> INFO: 2380888 events read in total (106609ms).
[11:50:15.087] <TB1> INFO: 2972776 events read in total (132827ms).
[11:50:41.659] <TB1> INFO: 3563208 events read in total (159399ms).
[11:51:08.369] <TB1> INFO: 4151744 events read in total (186109ms).
[11:51:36.335] <TB1> INFO: 4740736 events read in total (214075ms).
[11:51:49.105] <TB1> INFO: 5025280 events read in total (226845ms).
[11:51:49.184] <TB1> INFO: Test took 227860ms.
[11:52:19.288] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 62.3505 for pixel 2/17 mean/min/max = 47.9172/33.4276/62.4068
[11:52:19.289] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 64.0592 for pixel 25/18 mean/min/max = 49.378/34.6731/64.0829
[11:52:19.289] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 68.4166 for pixel 12/3 mean/min/max = 51.5351/34.5841/68.4861
[11:52:19.290] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 70.1282 for pixel 0/3 mean/min/max = 53.5302/36.9178/70.1425
[11:52:19.290] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 70.4309 for pixel 18/0 mean/min/max = 53.4439/36.2411/70.6468
[11:52:19.291] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 66.2893 for pixel 1/9 mean/min/max = 50.26/34.1313/66.3888
[11:52:19.292] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 66.71 for pixel 9/17 mean/min/max = 49.3863/31.9706/66.802
[11:52:19.292] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 64.5789 for pixel 1/0 mean/min/max = 47.7023/30.6662/64.7385
[11:52:19.293] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 73.1314 for pixel 36/0 mean/min/max = 54.9153/36.0159/73.8146
[11:52:19.293] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 66.9726 for pixel 4/20 mean/min/max = 50.0897/32.724/67.4554
[11:52:19.294] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 67.6247 for pixel 21/0 mean/min/max = 50.1343/32.2665/68.002
[11:52:19.294] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 65.77 for pixel 23/3 mean/min/max = 49.3714/32.8919/65.851
[11:52:19.295] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 66.506 for pixel 9/8 mean/min/max = 50.2313/33.9251/66.5375
[11:52:19.295] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 64.5923 for pixel 9/0 mean/min/max = 47.5551/30.516/64.5942
[11:52:19.296] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 65.3714 for pixel 8/32 mean/min/max = 49.3559/33.009/65.7027
[11:52:19.296] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 63.7921 for pixel 0/4 mean/min/max = 50.0103/35.5294/64.4912
[11:52:19.297] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:52:19.386] <TB1> INFO: Expecting 411648 events.
[11:52:29.608] <TB1> INFO: 411648 events read in total (9630ms).
[11:52:29.618] <TB1> INFO: Expecting 411648 events.
[11:52:39.056] <TB1> INFO: 411648 events read in total (9032ms).
[11:52:39.069] <TB1> INFO: Expecting 411648 events.
[11:52:48.533] <TB1> INFO: 411648 events read in total (9057ms).
[11:52:48.552] <TB1> INFO: Expecting 411648 events.
[11:52:57.734] <TB1> INFO: 411648 events read in total (8779ms).
[11:52:57.752] <TB1> INFO: Expecting 411648 events.
[11:53:07.074] <TB1> INFO: 411648 events read in total (8919ms).
[11:53:07.097] <TB1> INFO: Expecting 411648 events.
[11:53:16.652] <TB1> INFO: 411648 events read in total (9151ms).
[11:53:16.680] <TB1> INFO: Expecting 411648 events.
[11:53:25.003] <TB1> INFO: 411648 events read in total (8920ms).
[11:53:26.030] <TB1> INFO: Expecting 411648 events.
[11:53:35.330] <TB1> INFO: 411648 events read in total (8897ms).
[11:53:35.368] <TB1> INFO: Expecting 411648 events.
[11:53:44.657] <TB1> INFO: 411648 events read in total (8886ms).
[11:53:44.696] <TB1> INFO: Expecting 411648 events.
[11:53:53.998] <TB1> INFO: 411648 events read in total (8899ms).
[11:53:54.048] <TB1> INFO: Expecting 411648 events.
[11:54:03.295] <TB1> INFO: 411648 events read in total (8844ms).
[11:54:03.347] <TB1> INFO: Expecting 411648 events.
[11:54:12.837] <TB1> INFO: 411648 events read in total (9087ms).
[11:54:12.894] <TB1> INFO: Expecting 411648 events.
[11:54:22.342] <TB1> INFO: 411648 events read in total (9045ms).
[11:54:22.424] <TB1> INFO: Expecting 411648 events.
[11:54:31.745] <TB1> INFO: 411648 events read in total (8915ms).
[11:54:32.004] <TB1> INFO: Expecting 411648 events.
[11:54:41.294] <TB1> INFO: 411648 events read in total (8887ms).
[11:54:41.359] <TB1> INFO: Expecting 411648 events.
[11:54:50.592] <TB1> INFO: 411648 events read in total (8830ms).
[11:54:50.814] <TB1> INFO: Test took 151517ms.
[11:54:51.757] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[11:54:51.774] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:54:51.774] <TB1> INFO: run 1 of 1
[11:54:52.147] <TB1> INFO: Expecting 5025280 events.
[11:55:19.114] <TB1> INFO: 592104 events read in total (26375ms).
[11:55:45.904] <TB1> INFO: 1183448 events read in total (53165ms).
[11:56:13.169] <TB1> INFO: 1774416 events read in total (80430ms).
[11:56:40.634] <TB1> INFO: 2364544 events read in total (107895ms).
[11:57:07.723] <TB1> INFO: 2952976 events read in total (134984ms).
[11:57:35.107] <TB1> INFO: 3542640 events read in total (162368ms).
[11:58:01.932] <TB1> INFO: 4136200 events read in total (189193ms).
[11:58:28.864] <TB1> INFO: 4729632 events read in total (216126ms).
[11:58:42.619] <TB1> INFO: 5025280 events read in total (229880ms).
[11:58:42.776] <TB1> INFO: Test took 231003ms.
[11:59:09.673] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 1.397393 .. 147.152917
[11:59:09.945] <TB1> INFO: Expecting 208000 events.
[11:59:20.393] <TB1> INFO: 208000 events read in total (9856ms).
[11:59:20.394] <TB1> INFO: Test took 10720ms.
[11:59:20.476] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 1 .. 157 (-1/-1) hits flags = 528 (plus default)
[11:59:20.491] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[11:59:20.491] <TB1> INFO: run 1 of 1
[11:59:20.852] <TB1> INFO: Expecting 5224960 events.
[11:59:48.070] <TB1> INFO: 586048 events read in total (26626ms).
[12:00:14.640] <TB1> INFO: 1171384 events read in total (53197ms).
[12:00:41.033] <TB1> INFO: 1756408 events read in total (79590ms).
[12:01:07.453] <TB1> INFO: 2341296 events read in total (106009ms).
[12:01:35.027] <TB1> INFO: 2926744 events read in total (133583ms).
[12:02:01.891] <TB1> INFO: 3510960 events read in total (160447ms).
[12:02:27.881] <TB1> INFO: 4095632 events read in total (186437ms).
[12:02:54.980] <TB1> INFO: 4679360 events read in total (213536ms).
[12:03:19.784] <TB1> INFO: 5224960 events read in total (238340ms).
[12:03:19.937] <TB1> INFO: Test took 239446ms.
[12:03:53.595] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.177338 .. 46.862886
[12:03:53.921] <TB1> INFO: Expecting 208000 events.
[12:04:04.699] <TB1> INFO: 208000 events read in total (10186ms).
[12:04:04.700] <TB1> INFO: Test took 11103ms.
[12:04:04.747] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[12:04:04.760] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:04:04.760] <TB1> INFO: run 1 of 1
[12:04:05.038] <TB1> INFO: Expecting 1331200 events.
[12:04:34.116] <TB1> INFO: 664296 events read in total (28486ms).
[12:05:02.853] <TB1> INFO: 1328776 events read in total (57223ms).
[12:05:03.426] <TB1> INFO: 1331200 events read in total (57797ms).
[12:05:03.475] <TB1> INFO: Test took 58716ms.
[12:05:17.413] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 29.580718 .. 52.652847
[12:05:17.681] <TB1> INFO: Expecting 208000 events.
[12:05:28.475] <TB1> INFO: 208000 events read in total (10203ms).
[12:05:28.476] <TB1> INFO: Test took 11061ms.
[12:05:28.524] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 19 .. 62 (-1/-1) hits flags = 528 (plus default)
[12:05:28.539] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:05:28.539] <TB1> INFO: run 1 of 1
[12:05:28.817] <TB1> INFO: Expecting 1464320 events.
[12:05:57.524] <TB1> INFO: 632760 events read in total (28115ms).
[12:06:25.628] <TB1> INFO: 1264584 events read in total (56220ms).
[12:06:34.990] <TB1> INFO: 1464320 events read in total (65581ms).
[12:06:35.039] <TB1> INFO: Test took 66501ms.
[12:06:51.432] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 28.085520 .. 57.222458
[12:06:51.705] <TB1> INFO: Expecting 208000 events.
[12:07:02.238] <TB1> INFO: 208000 events read in total (9942ms).
[12:07:02.238] <TB1> INFO: Test took 10805ms.
[12:07:02.287] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 18 .. 67 (-1/-1) hits flags = 528 (plus default)
[12:07:02.299] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:07:02.300] <TB1> INFO: run 1 of 1
[12:07:02.577] <TB1> INFO: Expecting 1664000 events.
[12:07:29.902] <TB1> INFO: 622056 events read in total (26733ms).
[12:07:57.920] <TB1> INFO: 1243320 events read in total (54751ms).
[12:08:16.866] <TB1> INFO: 1664000 events read in total (73697ms).
[12:08:16.914] <TB1> INFO: Test took 74614ms.
[12:08:34.578] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:08:34.578] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:08:34.592] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:08:34.592] <TB1> INFO: run 1 of 1
[12:08:34.880] <TB1> INFO: Expecting 1364480 events.
[12:09:04.347] <TB1> INFO: 670008 events read in total (28875ms).
[12:09:33.688] <TB1> INFO: 1338560 events read in total (58216ms).
[12:09:35.312] <TB1> INFO: 1364480 events read in total (59841ms).
[12:09:35.347] <TB1> INFO: Test took 60755ms.
[12:09:52.850] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C0.dat
[12:09:52.850] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C1.dat
[12:09:52.850] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C2.dat
[12:09:52.850] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C3.dat
[12:09:52.850] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C4.dat
[12:09:52.850] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C5.dat
[12:09:52.850] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C6.dat
[12:09:52.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C7.dat
[12:09:52.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C8.dat
[12:09:52.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C9.dat
[12:09:52.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C10.dat
[12:09:52.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C11.dat
[12:09:52.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C12.dat
[12:09:52.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C13.dat
[12:09:52.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C14.dat
[12:09:52.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C15.dat
[12:09:52.851] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C0.dat
[12:09:52.858] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C1.dat
[12:09:52.864] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C2.dat
[12:09:52.871] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C3.dat
[12:09:52.876] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C4.dat
[12:09:52.881] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C5.dat
[12:09:52.886] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C6.dat
[12:09:52.890] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C7.dat
[12:09:52.895] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C8.dat
[12:09:52.900] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C9.dat
[12:09:52.904] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C10.dat
[12:09:52.909] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C11.dat
[12:09:52.914] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C12.dat
[12:09:52.918] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C13.dat
[12:09:52.923] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C14.dat
[12:09:52.928] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters35_C15.dat
[12:09:52.933] <TB1> INFO: PixTestTrim::trimTest() done
[12:09:52.933] <TB1> INFO: vtrim: 133 151 172 171 152 160 150 130 165 179 159 136 171 148 134 143
[12:09:52.933] <TB1> INFO: vthrcomp: 134 131 129 134 130 130 123 123 135 128 129 121 131 128 112 134
[12:09:52.933] <TB1> INFO: vcal mean: 35.23 35.48 35.06 35.59 35.88 36.15 36.89 35.13 35.75 35.42 35.60 35.23 35.21 35.06 36.18 35.45
[12:09:52.933] <TB1> INFO: vcal RMS: 1.28 1.67 1.16 1.87 2.18 1.77 2.98 1.27 2.05 1.66 1.80 1.38 1.38 1.25 2.29 1.55
[12:09:52.933] <TB1> INFO: bits mean: 9.04 9.25 8.61 7.77 8.30 9.11 10.15 9.62 8.13 9.14 8.92 8.95 9.00 9.66 9.41 7.92
[12:09:52.933] <TB1> INFO: bits RMS: 2.65 2.41 2.40 2.57 2.55 2.55 2.58 2.74 2.54 2.57 2.83 2.75 2.44 2.71 2.71 2.69
[12:09:52.941] <TB1> INFO: ----------------------------------------------------------------------
[12:09:52.941] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:09:52.941] <TB1> INFO: ----------------------------------------------------------------------
[12:09:52.944] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:09:52.960] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:09:52.960] <TB1> INFO: run 1 of 1
[12:09:53.200] <TB1> INFO: Expecting 4160000 events.
[12:10:27.708] <TB1> INFO: 794600 events read in total (33916ms).
[12:11:00.744] <TB1> INFO: 1579365 events read in total (66952ms).
[12:11:33.993] <TB1> INFO: 2357025 events read in total (100201ms).
[12:12:07.492] <TB1> INFO: 3131020 events read in total (133700ms).
[12:12:40.934] <TB1> INFO: 3900765 events read in total (167142ms).
[12:12:52.302] <TB1> INFO: 4160000 events read in total (178510ms).
[12:12:52.395] <TB1> INFO: Test took 179435ms.
[12:13:21.009] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[12:13:21.023] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:13:21.023] <TB1> INFO: run 1 of 1
[12:13:21.268] <TB1> INFO: Expecting 5324800 events.
[12:13:53.669] <TB1> INFO: 699185 events read in total (31810ms).
[12:14:24.902] <TB1> INFO: 1393000 events read in total (63043ms).
[12:14:56.105] <TB1> INFO: 2084420 events read in total (94246ms).
[12:15:26.952] <TB1> INFO: 2773655 events read in total (125093ms).
[12:15:58.154] <TB1> INFO: 3459980 events read in total (156295ms).
[12:16:29.234] <TB1> INFO: 4146140 events read in total (187375ms).
[12:17:01.775] <TB1> INFO: 4830675 events read in total (219916ms).
[12:17:24.386] <TB1> INFO: 5324800 events read in total (242527ms).
[12:17:24.564] <TB1> INFO: Test took 243540ms.
[12:17:56.731] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 243 (-1/-1) hits flags = 528 (plus default)
[12:17:56.746] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:17:56.746] <TB1> INFO: run 1 of 1
[12:17:56.000] <TB1> INFO: Expecting 5075200 events.
[12:18:29.403] <TB1> INFO: 710590 events read in total (31811ms).
[12:19:00.932] <TB1> INFO: 1415145 events read in total (63340ms).
[12:19:31.945] <TB1> INFO: 2117050 events read in total (94353ms).
[12:20:03.456] <TB1> INFO: 2815690 events read in total (125864ms).
[12:20:36.085] <TB1> INFO: 3512980 events read in total (158493ms).
[12:21:07.451] <TB1> INFO: 4208580 events read in total (189859ms).
[12:21:38.988] <TB1> INFO: 4904040 events read in total (221396ms).
[12:21:47.079] <TB1> INFO: 5075200 events read in total (229488ms).
[12:21:47.234] <TB1> INFO: Test took 230488ms.
[12:22:17.848] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 229 (-1/-1) hits flags = 528 (plus default)
[12:22:17.861] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:22:17.861] <TB1> INFO: run 1 of 1
[12:22:18.097] <TB1> INFO: Expecting 4784000 events.
[12:22:50.623] <TB1> INFO: 725310 events read in total (31934ms).
[12:23:22.514] <TB1> INFO: 1444320 events read in total (63825ms).
[12:23:55.140] <TB1> INFO: 2160275 events read in total (96452ms).
[12:24:27.549] <TB1> INFO: 2872275 events read in total (128860ms).
[12:24:59.098] <TB1> INFO: 3582885 events read in total (160409ms).
[12:25:30.468] <TB1> INFO: 4290965 events read in total (191779ms).
[12:25:53.004] <TB1> INFO: 4784000 events read in total (214315ms).
[12:25:53.093] <TB1> INFO: Test took 215232ms.
[12:26:22.922] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 238 (-1/-1) hits flags = 528 (plus default)
[12:26:22.938] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:26:22.938] <TB1> INFO: run 1 of 1
[12:26:23.176] <TB1> INFO: Expecting 4971200 events.
[12:26:55.692] <TB1> INFO: 715710 events read in total (31924ms).
[12:27:28.120] <TB1> INFO: 1425855 events read in total (64352ms).
[12:28:00.094] <TB1> INFO: 2132720 events read in total (96326ms).
[12:28:32.245] <TB1> INFO: 2836375 events read in total (128477ms).
[12:29:03.870] <TB1> INFO: 3539035 events read in total (160102ms).
[12:29:34.675] <TB1> INFO: 4238960 events read in total (190907ms).
[12:30:05.240] <TB1> INFO: 4941245 events read in total (221472ms).
[12:30:06.002] <TB1> INFO: 4971200 events read in total (223234ms).
[12:30:07.095] <TB1> INFO: Test took 224157ms.
[12:30:34.929] <TB1> INFO: PixTestTrim::trimBitTest() done
[12:30:34.930] <TB1> INFO: PixTestTrim::doTest() done, duration: 2761 seconds
[12:30:34.930] <TB1> INFO: Decoding statistics:
[12:30:34.930] <TB1> INFO: General information:
[12:30:34.930] <TB1> INFO: 16bit words read: 0
[12:30:34.930] <TB1> INFO: valid events total: 0
[12:30:34.930] <TB1> INFO: empty events: 0
[12:30:34.930] <TB1> INFO: valid events with pixels: 0
[12:30:34.930] <TB1> INFO: valid pixel hits: 0
[12:30:34.930] <TB1> INFO: Event errors: 0
[12:30:34.930] <TB1> INFO: start marker: 0
[12:30:34.930] <TB1> INFO: stop marker: 0
[12:30:34.930] <TB1> INFO: overflow: 0
[12:30:34.930] <TB1> INFO: invalid 5bit words: 0
[12:30:34.930] <TB1> INFO: invalid XOR eye diagram: 0
[12:30:34.930] <TB1> INFO: frame (failed synchr.): 0
[12:30:34.930] <TB1> INFO: idle data (no TBM trl): 0
[12:30:34.930] <TB1> INFO: no data (only TBM hdr): 0
[12:30:34.930] <TB1> INFO: TBM errors: 0
[12:30:34.930] <TB1> INFO: flawed TBM headers: 0
[12:30:34.930] <TB1> INFO: flawed TBM trailers: 0
[12:30:34.930] <TB1> INFO: event ID mismatches: 0
[12:30:34.930] <TB1> INFO: ROC errors: 0
[12:30:34.930] <TB1> INFO: missing ROC header(s): 0
[12:30:34.930] <TB1> INFO: misplaced readback start: 0
[12:30:34.930] <TB1> INFO: Pixel decoding errors: 0
[12:30:34.930] <TB1> INFO: pixel data incomplete: 0
[12:30:34.930] <TB1> INFO: pixel address: 0
[12:30:34.930] <TB1> INFO: pulse height fill bit: 0
[12:30:34.930] <TB1> INFO: buffer corruption: 0
[12:30:35.753] <TB1> INFO: ######################################################################
[12:30:35.753] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[12:30:35.753] <TB1> INFO: ######################################################################
[12:30:35.001] <TB1> INFO: Expecting 41600 events.
[12:30:39.632] <TB1> INFO: 41600 events read in total (3039ms).
[12:30:39.633] <TB1> INFO: Test took 3879ms.
[12:30:40.193] <TB1> INFO: Expecting 41600 events.
[12:30:44.030] <TB1> INFO: 41600 events read in total (3246ms).
[12:30:44.031] <TB1> INFO: Test took 4195ms.
[12:30:44.321] <TB1> INFO: Expecting 41600 events.
[12:30:47.839] <TB1> INFO: 41600 events read in total (2927ms).
[12:30:47.840] <TB1> INFO: Test took 3784ms.
[12:30:48.128] <TB1> INFO: Expecting 41600 events.
[12:30:51.637] <TB1> INFO: 41600 events read in total (2917ms).
[12:30:51.638] <TB1> INFO: Test took 3774ms.
[12:30:51.934] <TB1> INFO: Expecting 41600 events.
[12:30:55.612] <TB1> INFO: 41600 events read in total (3086ms).
[12:30:55.613] <TB1> INFO: Test took 3951ms.
[12:30:55.902] <TB1> INFO: Expecting 41600 events.
[12:30:59.388] <TB1> INFO: 41600 events read in total (2894ms).
[12:30:59.389] <TB1> INFO: Test took 3752ms.
[12:30:59.679] <TB1> INFO: Expecting 41600 events.
[12:31:03.147] <TB1> INFO: 41600 events read in total (2877ms).
[12:31:03.148] <TB1> INFO: Test took 3735ms.
[12:31:03.467] <TB1> INFO: Expecting 41600 events.
[12:31:07.096] <TB1> INFO: 41600 events read in total (3038ms).
[12:31:07.097] <TB1> INFO: Test took 3924ms.
[12:31:07.413] <TB1> INFO: Expecting 41600 events.
[12:31:10.849] <TB1> INFO: 41600 events read in total (2844ms).
[12:31:10.850] <TB1> INFO: Test took 3728ms.
[12:31:11.139] <TB1> INFO: Expecting 41600 events.
[12:31:14.739] <TB1> INFO: 41600 events read in total (3008ms).
[12:31:14.741] <TB1> INFO: Test took 3866ms.
[12:31:15.033] <TB1> INFO: Expecting 41600 events.
[12:31:18.461] <TB1> INFO: 41600 events read in total (2836ms).
[12:31:18.462] <TB1> INFO: Test took 3693ms.
[12:31:18.753] <TB1> INFO: Expecting 41600 events.
[12:31:22.227] <TB1> INFO: 41600 events read in total (2882ms).
[12:31:22.228] <TB1> INFO: Test took 3742ms.
[12:31:22.517] <TB1> INFO: Expecting 41600 events.
[12:31:25.953] <TB1> INFO: 41600 events read in total (2846ms).
[12:31:25.955] <TB1> INFO: Test took 3703ms.
[12:31:26.247] <TB1> INFO: Expecting 41600 events.
[12:31:29.733] <TB1> INFO: 41600 events read in total (2895ms).
[12:31:29.734] <TB1> INFO: Test took 3752ms.
[12:31:30.024] <TB1> INFO: Expecting 41600 events.
[12:31:33.511] <TB1> INFO: 41600 events read in total (2895ms).
[12:31:33.513] <TB1> INFO: Test took 3754ms.
[12:31:33.809] <TB1> INFO: Expecting 41600 events.
[12:31:37.270] <TB1> INFO: 41600 events read in total (2870ms).
[12:31:37.271] <TB1> INFO: Test took 3732ms.
[12:31:37.560] <TB1> INFO: Expecting 41600 events.
[12:31:41.207] <TB1> INFO: 41600 events read in total (3056ms).
[12:31:41.208] <TB1> INFO: Test took 3913ms.
[12:31:41.520] <TB1> INFO: Expecting 41600 events.
[12:31:45.084] <TB1> INFO: 41600 events read in total (2972ms).
[12:31:45.085] <TB1> INFO: Test took 3853ms.
[12:31:45.377] <TB1> INFO: Expecting 41600 events.
[12:31:48.951] <TB1> INFO: 41600 events read in total (2982ms).
[12:31:48.952] <TB1> INFO: Test took 3839ms.
[12:31:49.242] <TB1> INFO: Expecting 41600 events.
[12:31:52.671] <TB1> INFO: 41600 events read in total (2838ms).
[12:31:52.672] <TB1> INFO: Test took 3695ms.
[12:31:53.016] <TB1> INFO: Expecting 41600 events.
[12:31:56.485] <TB1> INFO: 41600 events read in total (2878ms).
[12:31:56.486] <TB1> INFO: Test took 3789ms.
[12:31:56.778] <TB1> INFO: Expecting 41600 events.
[12:32:00.362] <TB1> INFO: 41600 events read in total (2992ms).
[12:32:00.363] <TB1> INFO: Test took 3850ms.
[12:32:00.653] <TB1> INFO: Expecting 41600 events.
[12:32:04.238] <TB1> INFO: 41600 events read in total (2994ms).
[12:32:04.239] <TB1> INFO: Test took 3851ms.
[12:32:04.644] <TB1> INFO: Expecting 41600 events.
[12:32:08.102] <TB1> INFO: 41600 events read in total (2866ms).
[12:32:08.103] <TB1> INFO: Test took 3833ms.
[12:32:08.394] <TB1> INFO: Expecting 41600 events.
[12:32:11.989] <TB1> INFO: 41600 events read in total (3004ms).
[12:32:11.990] <TB1> INFO: Test took 3861ms.
[12:32:12.313] <TB1> INFO: Expecting 41600 events.
[12:32:15.759] <TB1> INFO: 41600 events read in total (2854ms).
[12:32:15.760] <TB1> INFO: Test took 3743ms.
[12:32:16.050] <TB1> INFO: Expecting 41600 events.
[12:32:19.650] <TB1> INFO: 41600 events read in total (3009ms).
[12:32:19.651] <TB1> INFO: Test took 3866ms.
[12:32:19.963] <TB1> INFO: Expecting 41600 events.
[12:32:23.432] <TB1> INFO: 41600 events read in total (2877ms).
[12:32:23.434] <TB1> INFO: Test took 3759ms.
[12:32:23.726] <TB1> INFO: Expecting 41600 events.
[12:32:27.186] <TB1> INFO: 41600 events read in total (2868ms).
[12:32:27.187] <TB1> INFO: Test took 3726ms.
[12:32:27.479] <TB1> INFO: Expecting 2560 events.
[12:32:28.366] <TB1> INFO: 2560 events read in total (296ms).
[12:32:28.366] <TB1> INFO: Test took 1164ms.
[12:32:28.675] <TB1> INFO: Expecting 2560 events.
[12:32:29.557] <TB1> INFO: 2560 events read in total (291ms).
[12:32:29.557] <TB1> INFO: Test took 1190ms.
[12:32:29.865] <TB1> INFO: Expecting 2560 events.
[12:32:30.752] <TB1> INFO: 2560 events read in total (296ms).
[12:32:30.752] <TB1> INFO: Test took 1195ms.
[12:32:31.060] <TB1> INFO: Expecting 2560 events.
[12:32:31.943] <TB1> INFO: 2560 events read in total (291ms).
[12:32:31.943] <TB1> INFO: Test took 1190ms.
[12:32:32.251] <TB1> INFO: Expecting 2560 events.
[12:32:33.130] <TB1> INFO: 2560 events read in total (288ms).
[12:32:33.130] <TB1> INFO: Test took 1187ms.
[12:32:33.439] <TB1> INFO: Expecting 2560 events.
[12:32:34.319] <TB1> INFO: 2560 events read in total (289ms).
[12:32:34.320] <TB1> INFO: Test took 1189ms.
[12:32:34.627] <TB1> INFO: Expecting 2560 events.
[12:32:35.506] <TB1> INFO: 2560 events read in total (288ms).
[12:32:35.506] <TB1> INFO: Test took 1185ms.
[12:32:35.814] <TB1> INFO: Expecting 2560 events.
[12:32:36.697] <TB1> INFO: 2560 events read in total (291ms).
[12:32:36.698] <TB1> INFO: Test took 1191ms.
[12:32:37.006] <TB1> INFO: Expecting 2560 events.
[12:32:37.884] <TB1> INFO: 2560 events read in total (287ms).
[12:32:37.884] <TB1> INFO: Test took 1186ms.
[12:32:38.192] <TB1> INFO: Expecting 2560 events.
[12:32:39.072] <TB1> INFO: 2560 events read in total (288ms).
[12:32:39.072] <TB1> INFO: Test took 1187ms.
[12:32:39.380] <TB1> INFO: Expecting 2560 events.
[12:32:40.261] <TB1> INFO: 2560 events read in total (289ms).
[12:32:40.262] <TB1> INFO: Test took 1190ms.
[12:32:40.570] <TB1> INFO: Expecting 2560 events.
[12:32:41.448] <TB1> INFO: 2560 events read in total (287ms).
[12:32:41.448] <TB1> INFO: Test took 1186ms.
[12:32:41.756] <TB1> INFO: Expecting 2560 events.
[12:32:42.642] <TB1> INFO: 2560 events read in total (295ms).
[12:32:42.642] <TB1> INFO: Test took 1193ms.
[12:32:42.950] <TB1> INFO: Expecting 2560 events.
[12:32:43.836] <TB1> INFO: 2560 events read in total (295ms).
[12:32:43.836] <TB1> INFO: Test took 1194ms.
[12:32:44.143] <TB1> INFO: Expecting 2560 events.
[12:32:45.027] <TB1> INFO: 2560 events read in total (292ms).
[12:32:45.028] <TB1> INFO: Test took 1191ms.
[12:32:45.337] <TB1> INFO: Expecting 2560 events.
[12:32:46.225] <TB1> INFO: 2560 events read in total (297ms).
[12:32:46.225] <TB1> INFO: Test took 1197ms.
[12:32:46.228] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:32:46.534] <TB1> INFO: Expecting 655360 events.
[12:33:01.217] <TB1> INFO: 655360 events read in total (14091ms).
[12:33:01.240] <TB1> INFO: Expecting 655360 events.
[12:33:15.511] <TB1> INFO: 655360 events read in total (13868ms).
[12:33:15.533] <TB1> INFO: Expecting 655360 events.
[12:33:30.205] <TB1> INFO: 655360 events read in total (14269ms).
[12:33:30.230] <TB1> INFO: Expecting 655360 events.
[12:33:44.907] <TB1> INFO: 655360 events read in total (14274ms).
[12:33:44.944] <TB1> INFO: Expecting 655360 events.
[12:33:59.402] <TB1> INFO: 655360 events read in total (14055ms).
[12:33:59.440] <TB1> INFO: Expecting 655360 events.
[12:34:13.921] <TB1> INFO: 655360 events read in total (14078ms).
[12:34:13.960] <TB1> INFO: Expecting 655360 events.
[12:34:28.367] <TB1> INFO: 655360 events read in total (14005ms).
[12:34:28.424] <TB1> INFO: Expecting 655360 events.
[12:34:43.075] <TB1> INFO: 655360 events read in total (14248ms).
[12:34:43.132] <TB1> INFO: Expecting 655360 events.
[12:34:57.467] <TB1> INFO: 655360 events read in total (13932ms).
[12:34:57.531] <TB1> INFO: Expecting 655360 events.
[12:35:11.745] <TB1> INFO: 655360 events read in total (13811ms).
[12:35:11.849] <TB1> INFO: Expecting 655360 events.
[12:35:26.450] <TB1> INFO: 655360 events read in total (14198ms).
[12:35:26.528] <TB1> INFO: Expecting 655360 events.
[12:35:41.037] <TB1> INFO: 655360 events read in total (14106ms).
[12:35:41.145] <TB1> INFO: Expecting 655360 events.
[12:35:55.419] <TB1> INFO: 655360 events read in total (13871ms).
[12:35:55.515] <TB1> INFO: Expecting 655360 events.
[12:36:09.910] <TB1> INFO: 655360 events read in total (13992ms).
[12:36:10.059] <TB1> INFO: Expecting 655360 events.
[12:36:24.456] <TB1> INFO: 655360 events read in total (13994ms).
[12:36:24.551] <TB1> INFO: Expecting 655360 events.
[12:36:38.943] <TB1> INFO: 655360 events read in total (13989ms).
[12:36:39.050] <TB1> INFO: Test took 232822ms.
[12:36:39.156] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:36:39.413] <TB1> INFO: Expecting 655360 events.
[12:36:54.051] <TB1> INFO: 655360 events read in total (14046ms).
[12:36:54.070] <TB1> INFO: Expecting 655360 events.
[12:37:08.196] <TB1> INFO: 655360 events read in total (13723ms).
[12:37:08.221] <TB1> INFO: Expecting 655360 events.
[12:37:22.530] <TB1> INFO: 655360 events read in total (13906ms).
[12:37:22.554] <TB1> INFO: Expecting 655360 events.
[12:37:37.154] <TB1> INFO: 655360 events read in total (14197ms).
[12:37:37.183] <TB1> INFO: Expecting 655360 events.
[12:37:51.744] <TB1> INFO: 655360 events read in total (14158ms).
[12:37:51.801] <TB1> INFO: Expecting 655360 events.
[12:38:06.125] <TB1> INFO: 655360 events read in total (13921ms).
[12:38:06.180] <TB1> INFO: Expecting 655360 events.
[12:38:20.457] <TB1> INFO: 655360 events read in total (13874ms).
[12:38:20.509] <TB1> INFO: Expecting 655360 events.
[12:38:34.812] <TB1> INFO: 655360 events read in total (13896ms).
[12:38:34.868] <TB1> INFO: Expecting 655360 events.
[12:38:49.421] <TB1> INFO: 655360 events read in total (14150ms).
[12:38:49.487] <TB1> INFO: Expecting 655360 events.
[12:39:03.985] <TB1> INFO: 655360 events read in total (14095ms).
[12:39:04.050] <TB1> INFO: Expecting 655360 events.
[12:39:18.077] <TB1> INFO: 655360 events read in total (13624ms).
[12:39:18.134] <TB1> INFO: Expecting 655360 events.
[12:39:32.410] <TB1> INFO: 655360 events read in total (13873ms).
[12:39:32.543] <TB1> INFO: Expecting 655360 events.
[12:39:46.932] <TB1> INFO: 655360 events read in total (13986ms).
[12:39:47.027] <TB1> INFO: Expecting 655360 events.
[12:40:01.411] <TB1> INFO: 655360 events read in total (13981ms).
[12:40:01.522] <TB1> INFO: Expecting 655360 events.
[12:40:15.992] <TB1> INFO: 655360 events read in total (14067ms).
[12:40:16.146] <TB1> INFO: Expecting 655360 events.
[12:40:30.912] <TB1> INFO: 655360 events read in total (14363ms).
[12:40:31.030] <TB1> INFO: Test took 231874ms.
[12:40:31.269] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:40:31.279] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:40:31.285] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:40:31.291] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:40:31.297] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[12:40:31.303] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[12:40:31.308] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:40:31.314] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:40:31.320] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:40:31.328] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:40:31.334] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[12:40:31.341] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:40:31.348] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:40:31.354] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:40:31.362] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:40:31.368] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[12:40:31.375] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:40:31.381] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:40:31.390] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:40:31.400] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:40:31.407] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:40:31.415] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:40:31.423] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:40:31.432] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:40:31.441] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:40:31.449] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[12:40:31.458] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[12:40:31.467] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[12:40:31.474] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[12:40:31.484] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[12:40:31.493] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[12:40:31.502] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:40:31.512] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:40:31.521] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:40:31.531] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:40:31.540] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[12:40:31.549] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[12:40:31.558] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[12:40:31.567] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[12:40:31.576] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[12:40:31.585] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[12:40:31.594] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[12:40:31.603] <TB1> INFO: safety margin for low PH: adding 10, margin is now 30
[12:40:31.611] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:40:31.617] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:40:31.622] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:40:31.628] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[12:40:31.634] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:40:31.640] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:40:31.646] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:40:31.651] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[12:40:31.662] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[12:40:31.672] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:40:31.683] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:40:31.693] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:40:31.703] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[12:40:31.714] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[12:40:31.724] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[12:40:31.735] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[12:40:31.745] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[12:40:31.755] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[12:40:31.798] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C0.dat
[12:40:31.798] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C1.dat
[12:40:31.798] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C2.dat
[12:40:31.798] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C3.dat
[12:40:31.798] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C4.dat
[12:40:31.799] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C5.dat
[12:40:31.799] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C6.dat
[12:40:31.799] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C7.dat
[12:40:31.799] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C8.dat
[12:40:31.799] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C9.dat
[12:40:31.799] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C10.dat
[12:40:31.799] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C11.dat
[12:40:31.800] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C12.dat
[12:40:31.800] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C13.dat
[12:40:31.800] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C14.dat
[12:40:31.800] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters35_C15.dat
[12:40:32.131] <TB1> INFO: Expecting 41600 events.
[12:40:35.250] <TB1> INFO: 41600 events read in total (2528ms).
[12:40:35.251] <TB1> INFO: Test took 3448ms.
[12:40:35.703] <TB1> INFO: Expecting 41600 events.
[12:40:38.831] <TB1> INFO: 41600 events read in total (2536ms).
[12:40:38.833] <TB1> INFO: Test took 3368ms.
[12:40:39.285] <TB1> INFO: Expecting 41600 events.
[12:40:42.421] <TB1> INFO: 41600 events read in total (2544ms).
[12:40:42.423] <TB1> INFO: Test took 3376ms.
[12:40:42.643] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:40:42.732] <TB1> INFO: Expecting 2560 events.
[12:40:43.630] <TB1> INFO: 2560 events read in total (297ms).
[12:40:43.630] <TB1> INFO: Test took 987ms.
[12:40:43.632] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:40:43.939] <TB1> INFO: Expecting 2560 events.
[12:40:44.826] <TB1> INFO: 2560 events read in total (295ms).
[12:40:44.826] <TB1> INFO: Test took 1194ms.
[12:40:44.828] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:40:45.135] <TB1> INFO: Expecting 2560 events.
[12:40:46.024] <TB1> INFO: 2560 events read in total (298ms).
[12:40:46.025] <TB1> INFO: Test took 1197ms.
[12:40:46.027] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:40:46.334] <TB1> INFO: Expecting 2560 events.
[12:40:47.222] <TB1> INFO: 2560 events read in total (297ms).
[12:40:47.222] <TB1> INFO: Test took 1195ms.
[12:40:47.224] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:40:47.531] <TB1> INFO: Expecting 2560 events.
[12:40:48.421] <TB1> INFO: 2560 events read in total (294ms).
[12:40:48.421] <TB1> INFO: Test took 1197ms.
[12:40:48.423] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:40:48.729] <TB1> INFO: Expecting 2560 events.
[12:40:49.620] <TB1> INFO: 2560 events read in total (299ms).
[12:40:49.620] <TB1> INFO: Test took 1197ms.
[12:40:49.622] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:40:49.928] <TB1> INFO: Expecting 2560 events.
[12:40:50.817] <TB1> INFO: 2560 events read in total (297ms).
[12:40:50.817] <TB1> INFO: Test took 1195ms.
[12:40:50.821] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:40:51.126] <TB1> INFO: Expecting 2560 events.
[12:40:52.016] <TB1> INFO: 2560 events read in total (299ms).
[12:40:52.016] <TB1> INFO: Test took 1195ms.
[12:40:52.019] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:40:52.324] <TB1> INFO: Expecting 2560 events.
[12:40:53.207] <TB1> INFO: 2560 events read in total (291ms).
[12:40:53.207] <TB1> INFO: Test took 1188ms.
[12:40:53.209] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:40:53.516] <TB1> INFO: Expecting 2560 events.
[12:40:54.399] <TB1> INFO: 2560 events read in total (291ms).
[12:40:54.400] <TB1> INFO: Test took 1191ms.
[12:40:54.402] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:40:54.708] <TB1> INFO: Expecting 2560 events.
[12:40:55.593] <TB1> INFO: 2560 events read in total (294ms).
[12:40:55.593] <TB1> INFO: Test took 1191ms.
[12:40:55.600] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:40:55.903] <TB1> INFO: Expecting 2560 events.
[12:40:56.785] <TB1> INFO: 2560 events read in total (290ms).
[12:40:56.785] <TB1> INFO: Test took 1186ms.
[12:40:56.787] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:40:57.093] <TB1> INFO: Expecting 2560 events.
[12:40:57.973] <TB1> INFO: 2560 events read in total (288ms).
[12:40:57.973] <TB1> INFO: Test took 1186ms.
[12:40:57.975] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:40:58.282] <TB1> INFO: Expecting 2560 events.
[12:40:59.161] <TB1> INFO: 2560 events read in total (288ms).
[12:40:59.161] <TB1> INFO: Test took 1186ms.
[12:40:59.164] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:40:59.469] <TB1> INFO: Expecting 2560 events.
[12:41:00.353] <TB1> INFO: 2560 events read in total (292ms).
[12:41:00.354] <TB1> INFO: Test took 1191ms.
[12:41:00.357] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:41:00.662] <TB1> INFO: Expecting 2560 events.
[12:41:01.546] <TB1> INFO: 2560 events read in total (293ms).
[12:41:01.546] <TB1> INFO: Test took 1189ms.
[12:41:01.549] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:41:01.854] <TB1> INFO: Expecting 2560 events.
[12:41:02.741] <TB1> INFO: 2560 events read in total (295ms).
[12:41:02.742] <TB1> INFO: Test took 1193ms.
[12:41:02.744] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:41:03.049] <TB1> INFO: Expecting 2560 events.
[12:41:03.929] <TB1> INFO: 2560 events read in total (288ms).
[12:41:03.930] <TB1> INFO: Test took 1186ms.
[12:41:03.932] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:41:04.238] <TB1> INFO: Expecting 2560 events.
[12:41:05.120] <TB1> INFO: 2560 events read in total (291ms).
[12:41:05.121] <TB1> INFO: Test took 1189ms.
[12:41:05.126] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:41:05.428] <TB1> INFO: Expecting 2560 events.
[12:41:06.316] <TB1> INFO: 2560 events read in total (296ms).
[12:41:06.316] <TB1> INFO: Test took 1190ms.
[12:41:06.318] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:41:06.625] <TB1> INFO: Expecting 2560 events.
[12:41:07.512] <TB1> INFO: 2560 events read in total (296ms).
[12:41:07.512] <TB1> INFO: Test took 1194ms.
[12:41:07.515] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:41:07.820] <TB1> INFO: Expecting 2560 events.
[12:41:08.705] <TB1> INFO: 2560 events read in total (293ms).
[12:41:08.705] <TB1> INFO: Test took 1190ms.
[12:41:08.709] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:41:09.013] <TB1> INFO: Expecting 2560 events.
[12:41:09.897] <TB1> INFO: 2560 events read in total (292ms).
[12:41:09.897] <TB1> INFO: Test took 1188ms.
[12:41:09.899] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:41:10.205] <TB1> INFO: Expecting 2560 events.
[12:41:11.085] <TB1> INFO: 2560 events read in total (288ms).
[12:41:11.085] <TB1> INFO: Test took 1186ms.
[12:41:11.088] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:41:11.394] <TB1> INFO: Expecting 2560 events.
[12:41:12.277] <TB1> INFO: 2560 events read in total (292ms).
[12:41:12.278] <TB1> INFO: Test took 1190ms.
[12:41:12.281] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:41:12.585] <TB1> INFO: Expecting 2560 events.
[12:41:13.476] <TB1> INFO: 2560 events read in total (299ms).
[12:41:13.476] <TB1> INFO: Test took 1195ms.
[12:41:13.479] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:41:13.785] <TB1> INFO: Expecting 2560 events.
[12:41:14.674] <TB1> INFO: 2560 events read in total (296ms).
[12:41:14.675] <TB1> INFO: Test took 1197ms.
[12:41:14.677] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:41:14.982] <TB1> INFO: Expecting 2560 events.
[12:41:15.868] <TB1> INFO: 2560 events read in total (294ms).
[12:41:15.868] <TB1> INFO: Test took 1191ms.
[12:41:15.871] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:41:16.178] <TB1> INFO: Expecting 2560 events.
[12:41:17.065] <TB1> INFO: 2560 events read in total (296ms).
[12:41:17.065] <TB1> INFO: Test took 1194ms.
[12:41:17.068] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:41:17.373] <TB1> INFO: Expecting 2560 events.
[12:41:18.261] <TB1> INFO: 2560 events read in total (296ms).
[12:41:18.261] <TB1> INFO: Test took 1193ms.
[12:41:18.265] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:41:18.570] <TB1> INFO: Expecting 2560 events.
[12:41:19.460] <TB1> INFO: 2560 events read in total (298ms).
[12:41:19.460] <TB1> INFO: Test took 1195ms.
[12:41:19.463] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:41:19.768] <TB1> INFO: Expecting 2560 events.
[12:41:20.653] <TB1> INFO: 2560 events read in total (293ms).
[12:41:20.653] <TB1> INFO: Test took 1190ms.
[12:41:21.122] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 645 seconds
[12:41:21.122] <TB1> INFO: PH scale (per ROC): 47 38 44 38 54 36 48 33 44 37 48 40 50 37 36 32
[12:41:21.122] <TB1> INFO: PH offset (per ROC): 106 112 101 83 124 106 96 75 98 103 102 104 112 95 108 83
[12:41:21.131] <TB1> INFO: Decoding statistics:
[12:41:21.131] <TB1> INFO: General information:
[12:41:21.131] <TB1> INFO: 16bit words read: 127868
[12:41:21.131] <TB1> INFO: valid events total: 20480
[12:41:21.131] <TB1> INFO: empty events: 17986
[12:41:21.131] <TB1> INFO: valid events with pixels: 2494
[12:41:21.131] <TB1> INFO: valid pixel hits: 2494
[12:41:21.131] <TB1> INFO: Event errors: 0
[12:41:21.131] <TB1> INFO: start marker: 0
[12:41:21.131] <TB1> INFO: stop marker: 0
[12:41:21.131] <TB1> INFO: overflow: 0
[12:41:21.131] <TB1> INFO: invalid 5bit words: 0
[12:41:21.131] <TB1> INFO: invalid XOR eye diagram: 0
[12:41:21.131] <TB1> INFO: frame (failed synchr.): 0
[12:41:21.131] <TB1> INFO: idle data (no TBM trl): 0
[12:41:21.131] <TB1> INFO: no data (only TBM hdr): 0
[12:41:21.131] <TB1> INFO: TBM errors: 0
[12:41:21.131] <TB1> INFO: flawed TBM headers: 0
[12:41:21.131] <TB1> INFO: flawed TBM trailers: 0
[12:41:21.131] <TB1> INFO: event ID mismatches: 0
[12:41:21.131] <TB1> INFO: ROC errors: 0
[12:41:21.132] <TB1> INFO: missing ROC header(s): 0
[12:41:21.132] <TB1> INFO: misplaced readback start: 0
[12:41:21.132] <TB1> INFO: Pixel decoding errors: 0
[12:41:21.132] <TB1> INFO: pixel data incomplete: 0
[12:41:21.132] <TB1> INFO: pixel address: 0
[12:41:21.132] <TB1> INFO: pulse height fill bit: 0
[12:41:21.132] <TB1> INFO: buffer corruption: 0
[12:41:21.344] <TB1> INFO: ######################################################################
[12:41:21.344] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[12:41:21.344] <TB1> INFO: ######################################################################
[12:41:21.363] <TB1> INFO: scanning low vcal = 10
[12:41:21.650] <TB1> INFO: Expecting 41600 events.
[12:41:25.233] <TB1> INFO: 41600 events read in total (2992ms).
[12:41:25.234] <TB1> INFO: Test took 3871ms.
[12:41:25.236] <TB1> INFO: scanning low vcal = 20
[12:41:25.536] <TB1> INFO: Expecting 41600 events.
[12:41:29.164] <TB1> INFO: 41600 events read in total (3033ms).
[12:41:29.165] <TB1> INFO: Test took 3929ms.
[12:41:29.167] <TB1> INFO: scanning low vcal = 30
[12:41:29.495] <TB1> INFO: Expecting 41600 events.
[12:41:33.213] <TB1> INFO: 41600 events read in total (3126ms).
[12:41:33.214] <TB1> INFO: Test took 4047ms.
[12:41:33.219] <TB1> INFO: scanning low vcal = 40
[12:41:33.493] <TB1> INFO: Expecting 41600 events.
[12:41:37.461] <TB1> INFO: 41600 events read in total (3375ms).
[12:41:37.462] <TB1> INFO: Test took 4243ms.
[12:41:37.465] <TB1> INFO: scanning low vcal = 50
[12:41:37.761] <TB1> INFO: Expecting 41600 events.
[12:41:41.781] <TB1> INFO: 41600 events read in total (3429ms).
[12:41:41.783] <TB1> INFO: Test took 4317ms.
[12:41:41.786] <TB1> INFO: scanning low vcal = 60
[12:41:42.159] <TB1> INFO: Expecting 41600 events.
[12:41:46.141] <TB1> INFO: 41600 events read in total (3390ms).
[12:41:46.142] <TB1> INFO: Test took 4355ms.
[12:41:46.147] <TB1> INFO: scanning low vcal = 70
[12:41:46.421] <TB1> INFO: Expecting 41600 events.
[12:41:50.368] <TB1> INFO: 41600 events read in total (3354ms).
[12:41:50.369] <TB1> INFO: Test took 4222ms.
[12:41:50.376] <TB1> INFO: scanning low vcal = 80
[12:41:50.668] <TB1> INFO: Expecting 41600 events.
[12:41:54.702] <TB1> INFO: 41600 events read in total (3443ms).
[12:41:54.703] <TB1> INFO: Test took 4327ms.
[12:41:54.707] <TB1> INFO: scanning low vcal = 90
[12:41:54.984] <TB1> INFO: Expecting 41600 events.
[12:41:58.924] <TB1> INFO: 41600 events read in total (3348ms).
[12:41:58.924] <TB1> INFO: Test took 4217ms.
[12:41:58.928] <TB1> INFO: scanning low vcal = 100
[12:41:59.204] <TB1> INFO: Expecting 41600 events.
[12:42:03.206] <TB1> INFO: 41600 events read in total (3410ms).
[12:42:03.207] <TB1> INFO: Test took 4279ms.
[12:42:03.210] <TB1> INFO: scanning low vcal = 110
[12:42:03.487] <TB1> INFO: Expecting 41600 events.
[12:42:07.513] <TB1> INFO: 41600 events read in total (3434ms).
[12:42:07.514] <TB1> INFO: Test took 4304ms.
[12:42:07.520] <TB1> INFO: scanning low vcal = 120
[12:42:07.841] <TB1> INFO: Expecting 41600 events.
[12:42:11.820] <TB1> INFO: 41600 events read in total (3387ms).
[12:42:11.821] <TB1> INFO: Test took 4301ms.
[12:42:11.824] <TB1> INFO: scanning low vcal = 130
[12:42:12.100] <TB1> INFO: Expecting 41600 events.
[12:42:16.080] <TB1> INFO: 41600 events read in total (3388ms).
[12:42:16.081] <TB1> INFO: Test took 4257ms.
[12:42:16.084] <TB1> INFO: scanning low vcal = 140
[12:42:16.361] <TB1> INFO: Expecting 41600 events.
[12:42:20.336] <TB1> INFO: 41600 events read in total (3383ms).
[12:42:20.337] <TB1> INFO: Test took 4253ms.
[12:42:20.341] <TB1> INFO: scanning low vcal = 150
[12:42:20.635] <TB1> INFO: Expecting 41600 events.
[12:42:24.620] <TB1> INFO: 41600 events read in total (3394ms).
[12:42:24.621] <TB1> INFO: Test took 4280ms.
[12:42:24.624] <TB1> INFO: scanning low vcal = 160
[12:42:24.900] <TB1> INFO: Expecting 41600 events.
[12:42:28.934] <TB1> INFO: 41600 events read in total (3442ms).
[12:42:28.935] <TB1> INFO: Test took 4311ms.
[12:42:28.938] <TB1> INFO: scanning low vcal = 170
[12:42:29.214] <TB1> INFO: Expecting 41600 events.
[12:42:33.232] <TB1> INFO: 41600 events read in total (3426ms).
[12:42:33.233] <TB1> INFO: Test took 4295ms.
[12:42:33.241] <TB1> INFO: scanning low vcal = 180
[12:42:33.513] <TB1> INFO: Expecting 41600 events.
[12:42:37.501] <TB1> INFO: 41600 events read in total (3397ms).
[12:42:37.502] <TB1> INFO: Test took 4260ms.
[12:42:37.505] <TB1> INFO: scanning low vcal = 190
[12:42:37.782] <TB1> INFO: Expecting 41600 events.
[12:42:41.750] <TB1> INFO: 41600 events read in total (3376ms).
[12:42:41.751] <TB1> INFO: Test took 4246ms.
[12:42:41.754] <TB1> INFO: scanning low vcal = 200
[12:42:42.078] <TB1> INFO: Expecting 41600 events.
[12:42:46.096] <TB1> INFO: 41600 events read in total (3426ms).
[12:42:46.097] <TB1> INFO: Test took 4342ms.
[12:42:46.100] <TB1> INFO: scanning low vcal = 210
[12:42:46.378] <TB1> INFO: Expecting 41600 events.
[12:42:50.409] <TB1> INFO: 41600 events read in total (3439ms).
[12:42:50.410] <TB1> INFO: Test took 4310ms.
[12:42:50.413] <TB1> INFO: scanning low vcal = 220
[12:42:50.690] <TB1> INFO: Expecting 41600 events.
[12:42:54.682] <TB1> INFO: 41600 events read in total (3400ms).
[12:42:54.683] <TB1> INFO: Test took 4270ms.
[12:42:54.686] <TB1> INFO: scanning low vcal = 230
[12:42:54.963] <TB1> INFO: Expecting 41600 events.
[12:42:58.905] <TB1> INFO: 41600 events read in total (3350ms).
[12:42:58.906] <TB1> INFO: Test took 4219ms.
[12:42:58.910] <TB1> INFO: scanning low vcal = 240
[12:42:59.185] <TB1> INFO: Expecting 41600 events.
[12:43:03.176] <TB1> INFO: 41600 events read in total (3399ms).
[12:43:03.176] <TB1> INFO: Test took 4266ms.
[12:43:03.180] <TB1> INFO: scanning low vcal = 250
[12:43:03.456] <TB1> INFO: Expecting 41600 events.
[12:43:07.448] <TB1> INFO: 41600 events read in total (3400ms).
[12:43:07.449] <TB1> INFO: Test took 4269ms.
[12:43:07.453] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[12:43:07.729] <TB1> INFO: Expecting 41600 events.
[12:43:11.781] <TB1> INFO: 41600 events read in total (3461ms).
[12:43:11.782] <TB1> INFO: Test took 4329ms.
[12:43:11.787] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[12:43:12.158] <TB1> INFO: Expecting 41600 events.
[12:43:16.132] <TB1> INFO: 41600 events read in total (3382ms).
[12:43:16.132] <TB1> INFO: Test took 4344ms.
[12:43:16.136] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[12:43:16.412] <TB1> INFO: Expecting 41600 events.
[12:43:20.394] <TB1> INFO: 41600 events read in total (3390ms).
[12:43:20.394] <TB1> INFO: Test took 4258ms.
[12:43:20.398] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[12:43:20.695] <TB1> INFO: Expecting 41600 events.
[12:43:24.687] <TB1> INFO: 41600 events read in total (3400ms).
[12:43:24.688] <TB1> INFO: Test took 4290ms.
[12:43:24.694] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[12:43:25.067] <TB1> INFO: Expecting 41600 events.
[12:43:28.994] <TB1> INFO: 41600 events read in total (3335ms).
[12:43:28.995] <TB1> INFO: Test took 4301ms.
[12:43:29.625] <TB1> INFO: PixTestGainPedestal::measure() done
[12:44:09.418] <TB1> INFO: PixTestGainPedestal::fit() done
[12:44:09.419] <TB1> INFO: non-linearity mean: 0.934 0.938 0.938 0.939 0.987 0.941 0.975 0.992 0.951 0.907 0.967 0.967 0.962 0.934 0.938 0.944
[12:44:09.419] <TB1> INFO: non-linearity RMS: 0.095 0.084 0.106 0.142 0.002 0.094 0.014 0.160 0.051 0.119 0.038 0.024 0.034 0.083 0.092 0.176
[12:44:09.419] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[12:44:09.432] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[12:44:09.446] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[12:44:09.459] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[12:44:09.473] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[12:44:09.486] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[12:44:09.510] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[12:44:09.535] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[12:44:09.560] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[12:44:09.585] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[12:44:09.610] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[12:44:09.626] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[12:44:09.640] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[12:44:09.655] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[12:44:09.669] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[12:44:09.683] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[12:44:09.696] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 168 seconds
[12:44:09.697] <TB1> INFO: Decoding statistics:
[12:44:09.697] <TB1> INFO: General information:
[12:44:09.697] <TB1> INFO: 16bit words read: 3171352
[12:44:09.697] <TB1> INFO: valid events total: 332800
[12:44:09.697] <TB1> INFO: empty events: 15305
[12:44:09.697] <TB1> INFO: valid events with pixels: 317495
[12:44:09.697] <TB1> INFO: valid pixel hits: 587276
[12:44:09.697] <TB1> INFO: Event errors: 0
[12:44:09.697] <TB1> INFO: start marker: 0
[12:44:09.697] <TB1> INFO: stop marker: 0
[12:44:09.697] <TB1> INFO: overflow: 0
[12:44:09.697] <TB1> INFO: invalid 5bit words: 0
[12:44:09.697] <TB1> INFO: invalid XOR eye diagram: 0
[12:44:09.697] <TB1> INFO: frame (failed synchr.): 0
[12:44:09.697] <TB1> INFO: idle data (no TBM trl): 0
[12:44:09.697] <TB1> INFO: no data (only TBM hdr): 0
[12:44:09.697] <TB1> INFO: TBM errors: 0
[12:44:09.697] <TB1> INFO: flawed TBM headers: 0
[12:44:09.697] <TB1> INFO: flawed TBM trailers: 0
[12:44:09.697] <TB1> INFO: event ID mismatches: 0
[12:44:09.697] <TB1> INFO: ROC errors: 0
[12:44:09.697] <TB1> INFO: missing ROC header(s): 0
[12:44:09.697] <TB1> INFO: misplaced readback start: 0
[12:44:09.697] <TB1> INFO: Pixel decoding errors: 0
[12:44:09.697] <TB1> INFO: pixel data incomplete: 0
[12:44:09.697] <TB1> INFO: pixel address: 0
[12:44:09.697] <TB1> INFO: pulse height fill bit: 0
[12:44:09.697] <TB1> INFO: buffer corruption: 0
[12:44:09.715] <TB1> INFO: Decoding statistics:
[12:44:09.715] <TB1> INFO: General information:
[12:44:09.715] <TB1> INFO: 16bit words read: 3300756
[12:44:09.715] <TB1> INFO: valid events total: 353536
[12:44:09.715] <TB1> INFO: empty events: 33547
[12:44:09.715] <TB1> INFO: valid events with pixels: 319989
[12:44:09.715] <TB1> INFO: valid pixel hits: 589770
[12:44:09.715] <TB1> INFO: Event errors: 0
[12:44:09.715] <TB1> INFO: start marker: 0
[12:44:09.715] <TB1> INFO: stop marker: 0
[12:44:09.715] <TB1> INFO: overflow: 0
[12:44:09.715] <TB1> INFO: invalid 5bit words: 0
[12:44:09.715] <TB1> INFO: invalid XOR eye diagram: 0
[12:44:09.715] <TB1> INFO: frame (failed synchr.): 0
[12:44:09.715] <TB1> INFO: idle data (no TBM trl): 0
[12:44:09.715] <TB1> INFO: no data (only TBM hdr): 0
[12:44:09.715] <TB1> INFO: TBM errors: 0
[12:44:09.715] <TB1> INFO: flawed TBM headers: 0
[12:44:09.715] <TB1> INFO: flawed TBM trailers: 0
[12:44:09.715] <TB1> INFO: event ID mismatches: 0
[12:44:09.715] <TB1> INFO: ROC errors: 0
[12:44:09.716] <TB1> INFO: missing ROC header(s): 0
[12:44:09.716] <TB1> INFO: misplaced readback start: 0
[12:44:09.716] <TB1> INFO: Pixel decoding errors: 0
[12:44:09.716] <TB1> INFO: pixel data incomplete: 0
[12:44:09.716] <TB1> INFO: pixel address: 0
[12:44:09.716] <TB1> INFO: pulse height fill bit: 0
[12:44:09.716] <TB1> INFO: buffer corruption: 0
[12:44:09.716] <TB1> INFO: enter test to run
[12:44:09.716] <TB1> INFO: test: trim80 no parameter change
[12:44:09.716] <TB1> INFO: running: trim80
[12:44:09.717] <TB1> INFO: ######################################################################
[12:44:09.717] <TB1> INFO: PixTestTrim80::doTest()
[12:44:09.717] <TB1> INFO: ######################################################################
[12:44:09.718] <TB1> INFO: ----------------------------------------------------------------------
[12:44:09.718] <TB1> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[12:44:09.718] <TB1> INFO: ----------------------------------------------------------------------
[12:44:09.764] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:44:09.764] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:44:09.778] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:44:09.778] <TB1> INFO: run 1 of 1
[12:44:10.048] <TB1> INFO: Expecting 5025280 events.
[12:44:39.916] <TB1> INFO: 696536 events read in total (29276ms).
[12:45:08.470] <TB1> INFO: 1390928 events read in total (57830ms).
[12:45:37.171] <TB1> INFO: 2083328 events read in total (86531ms).
[12:46:05.269] <TB1> INFO: 2772384 events read in total (114629ms).
[12:46:33.420] <TB1> INFO: 3457608 events read in total (142780ms).
[12:47:01.902] <TB1> INFO: 4139784 events read in total (171262ms).
[12:47:31.027] <TB1> INFO: 4821992 events read in total (200387ms).
[12:47:39.520] <TB1> INFO: 5025280 events read in total (208880ms).
[12:47:39.592] <TB1> INFO: Test took 209813ms.
[12:48:02.518] <TB1> INFO: ROC 0 VthrComp = 84
[12:48:02.519] <TB1> INFO: ROC 1 VthrComp = 84
[12:48:02.519] <TB1> INFO: ROC 2 VthrComp = 83
[12:48:02.519] <TB1> INFO: ROC 3 VthrComp = 90
[12:48:02.519] <TB1> INFO: ROC 4 VthrComp = 90
[12:48:02.519] <TB1> INFO: ROC 5 VthrComp = 85
[12:48:02.520] <TB1> INFO: ROC 6 VthrComp = 79
[12:48:02.520] <TB1> INFO: ROC 7 VthrComp = 77
[12:48:02.520] <TB1> INFO: ROC 8 VthrComp = 93
[12:48:02.520] <TB1> INFO: ROC 9 VthrComp = 79
[12:48:02.520] <TB1> INFO: ROC 10 VthrComp = 84
[12:48:02.520] <TB1> INFO: ROC 11 VthrComp = 79
[12:48:02.520] <TB1> INFO: ROC 12 VthrComp = 84
[12:48:02.520] <TB1> INFO: ROC 13 VthrComp = 78
[12:48:02.520] <TB1> INFO: ROC 14 VthrComp = 71
[12:48:02.520] <TB1> INFO: ROC 15 VthrComp = 84
[12:48:02.766] <TB1> INFO: Expecting 41600 events.
[12:48:06.319] <TB1> INFO: 41600 events read in total (2962ms).
[12:48:06.320] <TB1> INFO: Test took 3799ms.
[12:48:06.331] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:48:06.331] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:48:06.343] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:48:06.343] <TB1> INFO: run 1 of 1
[12:48:06.621] <TB1> INFO: Expecting 5025280 events.
[12:48:35.583] <TB1> INFO: 684672 events read in total (28371ms).
[12:49:03.851] <TB1> INFO: 1367064 events read in total (56640ms).
[12:49:32.133] <TB1> INFO: 2048672 events read in total (84921ms).
[12:50:00.229] <TB1> INFO: 2727968 events read in total (113017ms).
[12:50:28.208] <TB1> INFO: 3404352 events read in total (140996ms).
[12:50:56.477] <TB1> INFO: 4079416 events read in total (169265ms).
[12:51:24.610] <TB1> INFO: 4754296 events read in total (197398ms).
[12:51:35.974] <TB1> INFO: 5025280 events read in total (208762ms).
[12:51:36.062] <TB1> INFO: Test took 209719ms.
[12:51:59.150] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 107.954 for pixel 0/10 mean/min/max = 91.6744/75.2104/108.138
[12:51:59.151] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 106.999 for pixel 19/3 mean/min/max = 91.257/75.3366/107.177
[12:51:59.151] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 108.996 for pixel 6/66 mean/min/max = 92.0682/75.0246/109.112
[12:51:59.152] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 110.873 for pixel 0/75 mean/min/max = 93.5856/76.1441/111.027
[12:51:59.152] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 110.11 for pixel 15/73 mean/min/max = 93.0859/75.8437/110.328
[12:51:59.153] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 109.233 for pixel 11/13 mean/min/max = 91.7443/74.2072/109.281
[12:51:59.153] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 113.064 for pixel 0/0 mean/min/max = 94.9882/76.746/113.23
[12:51:59.154] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 113.62 for pixel 0/0 mean/min/max = 95.7402/77.7554/113.725
[12:51:59.154] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 111.839 for pixel 0/44 mean/min/max = 93.0274/74.0199/112.035
[12:51:59.155] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 116.116 for pixel 0/70 mean/min/max = 96.2451/76.1199/116.37
[12:51:59.155] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 110.425 for pixel 7/8 mean/min/max = 92.9069/74.8562/110.958
[12:51:59.156] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 109.695 for pixel 2/3 mean/min/max = 93.7031/77.6686/109.738
[12:51:59.156] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 111.342 for pixel 1/52 mean/min/max = 92.8632/74.2986/111.428
[12:51:59.157] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 113.904 for pixel 0/32 mean/min/max = 95.1167/76.2159/114.018
[12:51:59.157] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 110.686 for pixel 0/20 mean/min/max = 92.4339/74.1353/110.733
[12:51:59.158] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 108.706 for pixel 51/5 mean/min/max = 91.9209/74.9294/108.912
[12:51:59.158] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:51:59.247] <TB1> INFO: Expecting 411648 events.
[12:52:08.725] <TB1> INFO: 411648 events read in total (8886ms).
[12:52:08.733] <TB1> INFO: Expecting 411648 events.
[12:52:17.993] <TB1> INFO: 411648 events read in total (8850ms).
[12:52:18.004] <TB1> INFO: Expecting 411648 events.
[12:52:27.266] <TB1> INFO: 411648 events read in total (8859ms).
[12:52:27.281] <TB1> INFO: Expecting 411648 events.
[12:52:36.770] <TB1> INFO: 411648 events read in total (9086ms).
[12:52:36.793] <TB1> INFO: Expecting 411648 events.
[12:52:46.264] <TB1> INFO: 411648 events read in total (9068ms).
[12:52:46.294] <TB1> INFO: Expecting 411648 events.
[12:52:55.479] <TB1> INFO: 411648 events read in total (8779ms).
[12:52:55.504] <TB1> INFO: Expecting 411648 events.
[12:53:04.857] <TB1> INFO: 411648 events read in total (8950ms).
[12:53:04.882] <TB1> INFO: Expecting 411648 events.
[12:53:14.204] <TB1> INFO: 411648 events read in total (8919ms).
[12:53:14.232] <TB1> INFO: Expecting 411648 events.
[12:53:23.435] <TB1> INFO: 411648 events read in total (8800ms).
[12:53:23.469] <TB1> INFO: Expecting 411648 events.
[12:53:32.911] <TB1> INFO: 411648 events read in total (9039ms).
[12:53:32.968] <TB1> INFO: Expecting 411648 events.
[12:53:42.393] <TB1> INFO: 411648 events read in total (9022ms).
[12:53:42.454] <TB1> INFO: Expecting 411648 events.
[12:53:51.812] <TB1> INFO: 411648 events read in total (8955ms).
[12:53:51.886] <TB1> INFO: Expecting 411648 events.
[12:54:01.283] <TB1> INFO: 411648 events read in total (8994ms).
[12:54:01.330] <TB1> INFO: Expecting 411648 events.
[12:54:10.756] <TB1> INFO: 411648 events read in total (9023ms).
[12:54:10.846] <TB1> INFO: Expecting 411648 events.
[12:54:20.085] <TB1> INFO: 411648 events read in total (8836ms).
[12:54:20.185] <TB1> INFO: Expecting 411648 events.
[12:54:29.662] <TB1> INFO: 411648 events read in total (9074ms).
[12:54:29.764] <TB1> INFO: Test took 150606ms.
[12:54:31.252] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:54:31.266] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:54:31.266] <TB1> INFO: run 1 of 1
[12:54:31.503] <TB1> INFO: Expecting 5025280 events.
[12:55:00.078] <TB1> INFO: 668696 events read in total (27983ms).
[12:55:28.574] <TB1> INFO: 1333880 events read in total (56479ms).
[12:55:57.140] <TB1> INFO: 1998432 events read in total (85045ms).
[12:56:24.884] <TB1> INFO: 2661152 events read in total (112789ms).
[12:56:53.319] <TB1> INFO: 3320896 events read in total (141224ms).
[12:57:21.758] <TB1> INFO: 3978928 events read in total (169663ms).
[12:57:49.489] <TB1> INFO: 4635376 events read in total (197394ms).
[12:58:06.623] <TB1> INFO: 5025280 events read in total (214528ms).
[12:58:06.713] <TB1> INFO: Test took 215447ms.
[12:58:31.972] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 50.155336 .. 118.086839
[12:58:32.217] <TB1> INFO: Expecting 208000 events.
[12:58:42.263] <TB1> INFO: 208000 events read in total (9454ms).
[12:58:42.264] <TB1> INFO: Test took 10291ms.
[12:58:42.312] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 40 .. 128 (-1/-1) hits flags = 528 (plus default)
[12:58:42.325] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:58:42.325] <TB1> INFO: run 1 of 1
[12:58:42.603] <TB1> INFO: Expecting 2961920 events.
[12:59:12.121] <TB1> INFO: 654128 events read in total (28926ms).
[12:59:39.719] <TB1> INFO: 1308480 events read in total (56525ms).
[13:00:08.051] <TB1> INFO: 1960736 events read in total (84856ms).
[13:00:36.053] <TB1> INFO: 2610112 events read in total (112858ms).
[13:00:51.680] <TB1> INFO: 2961920 events read in total (128485ms).
[13:00:51.729] <TB1> INFO: Test took 129404ms.
[13:01:13.789] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 61.088419 .. 106.989379
[13:01:14.028] <TB1> INFO: Expecting 208000 events.
[13:01:24.017] <TB1> INFO: 208000 events read in total (9397ms).
[13:01:24.018] <TB1> INFO: Test took 10227ms.
[13:01:24.066] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 51 .. 116 (-1/-1) hits flags = 528 (plus default)
[13:01:24.080] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:01:24.080] <TB1> INFO: run 1 of 1
[13:01:24.358] <TB1> INFO: Expecting 2196480 events.
[13:01:53.037] <TB1> INFO: 649848 events read in total (28087ms).
[13:02:21.136] <TB1> INFO: 1299912 events read in total (56186ms).
[13:02:49.133] <TB1> INFO: 1949216 events read in total (84183ms).
[13:03:00.251] <TB1> INFO: 2196480 events read in total (95301ms).
[13:03:00.293] <TB1> INFO: Test took 96213ms.
[13:03:20.444] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 65.771190 .. 97.518475
[13:03:20.772] <TB1> INFO: Expecting 208000 events.
[13:03:31.278] <TB1> INFO: 208000 events read in total (9915ms).
[13:03:31.279] <TB1> INFO: Test took 10832ms.
[13:03:31.376] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 55 .. 107 (-1/-1) hits flags = 528 (plus default)
[13:03:31.393] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:03:31.393] <TB1> INFO: run 1 of 1
[13:03:31.730] <TB1> INFO: Expecting 1763840 events.
[13:04:01.013] <TB1> INFO: 661144 events read in total (28692ms).
[13:04:29.617] <TB1> INFO: 1322008 events read in total (57296ms).
[13:04:48.871] <TB1> INFO: 1763840 events read in total (76550ms).
[13:04:48.912] <TB1> INFO: Test took 77520ms.
[13:05:05.420] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 66.661568 .. 86.051328
[13:05:05.661] <TB1> INFO: Expecting 208000 events.
[13:05:15.938] <TB1> INFO: 208000 events read in total (9686ms).
[13:05:15.939] <TB1> INFO: Test took 10517ms.
[13:05:15.995] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 56 .. 96 (-1/-1) hits flags = 528 (plus default)
[13:05:16.013] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:05:16.013] <TB1> INFO: run 1 of 1
[13:05:16.296] <TB1> INFO: Expecting 1364480 events.
[13:05:45.607] <TB1> INFO: 703456 events read in total (28719ms).
[13:06:13.744] <TB1> INFO: 1364480 events read in total (56856ms).
[13:06:13.781] <TB1> INFO: Test took 57769ms.
[13:06:31.632] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[13:06:31.632] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[13:06:31.646] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:06:31.646] <TB1> INFO: run 1 of 1
[13:06:31.882] <TB1> INFO: Expecting 1364480 events.
[13:07:01.074] <TB1> INFO: 667832 events read in total (28601ms).
[13:07:29.919] <TB1> INFO: 1335880 events read in total (57447ms).
[13:07:31.645] <TB1> INFO: 1364480 events read in total (59172ms).
[13:07:31.675] <TB1> INFO: Test took 60029ms.
[13:07:50.875] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C0.dat
[13:07:50.875] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C1.dat
[13:07:50.875] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C2.dat
[13:07:50.875] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C3.dat
[13:07:50.876] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C4.dat
[13:07:50.876] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C5.dat
[13:07:50.876] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C6.dat
[13:07:50.876] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C7.dat
[13:07:50.876] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C8.dat
[13:07:50.876] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C9.dat
[13:07:50.876] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C10.dat
[13:07:50.876] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C11.dat
[13:07:50.876] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C12.dat
[13:07:50.876] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C13.dat
[13:07:50.876] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C14.dat
[13:07:50.876] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//dacParameters80_C15.dat
[13:07:50.877] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C0.dat
[13:07:50.884] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C1.dat
[13:07:50.891] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C2.dat
[13:07:50.898] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C3.dat
[13:07:50.905] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C4.dat
[13:07:50.912] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C5.dat
[13:07:50.919] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C6.dat
[13:07:50.926] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C7.dat
[13:07:50.933] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C8.dat
[13:07:50.940] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C9.dat
[13:07:50.947] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C10.dat
[13:07:50.954] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C11.dat
[13:07:50.961] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C12.dat
[13:07:50.969] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C13.dat
[13:07:50.976] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C14.dat
[13:07:50.983] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1060_FullQualification_2016-11-09_09h34m_1478680490//002_FulltestTrim80_p17//trimParameters80_C15.dat
[13:07:50.990] <TB1> INFO: PixTestTrim80::trimTest() done
[13:07:50.990] <TB1> INFO: vtrim: 93 98 108 115 112 111 118 101 106 135 122 102 116 114 94 111
[13:07:50.990] <TB1> INFO: vthrcomp: 84 84 83 90 90 85 79 77 93 79 84 79 84 78 71 84
[13:07:50.990] <TB1> INFO: vcal mean: 79.99 79.97 79.97 80.00 79.94 80.05 79.98 79.97 79.94 79.99 79.96 79.99 80.02 80.01 79.96 80.00
[13:07:50.990] <TB1> INFO: vcal RMS: 0.76 0.79 0.84 0.80 0.84 0.82 0.84 0.82 0.84 0.86 0.82 0.77 0.83 0.82 0.76 0.78
[13:07:50.990] <TB1> INFO: bits mean: 9.52 9.96 9.68 9.33 10.05 9.97 9.89 8.97 9.64 9.17 9.88 9.50 9.83 9.35 9.82 9.98
[13:07:50.990] <TB1> INFO: bits RMS: 2.58 2.43 2.59 2.53 2.25 2.43 2.13 2.39 2.61 2.46 2.41 2.25 2.52 2.42 2.48 2.39
[13:07:50.998] <TB1> INFO: ----------------------------------------------------------------------
[13:07:50.998] <TB1> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:07:50.998] <TB1> INFO: ----------------------------------------------------------------------
[13:07:50.001] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:07:51.015] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:07:51.015] <TB1> INFO: run 1 of 1
[13:07:51.341] <TB1> INFO: Expecting 4160000 events.
[13:08:25.951] <TB1> INFO: 794510 events read in total (34018ms).
[13:08:59.059] <TB1> INFO: 1578960 events read in total (67126ms).
[13:09:31.935] <TB1> INFO: 2356630 events read in total (100002ms).
[13:10:05.333] <TB1> INFO: 3130350 events read in total (133400ms).
[13:10:38.907] <TB1> INFO: 3900025 events read in total (166974ms).
[13:10:50.661] <TB1> INFO: 4160000 events read in total (178728ms).
[13:10:50.755] <TB1> INFO: Test took 179739ms.
[13:11:17.172] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[13:11:17.188] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:11:17.188] <TB1> INFO: run 1 of 1
[13:11:17.477] <TB1> INFO: Expecting 5324800 events.
[13:11:49.401] <TB1> INFO: 699290 events read in total (31332ms).
[13:12:20.854] <TB1> INFO: 1393015 events read in total (62785ms).
[13:12:52.110] <TB1> INFO: 2084500 events read in total (94041ms).
[13:13:23.114] <TB1> INFO: 2773665 events read in total (125045ms).
[13:13:53.893] <TB1> INFO: 3460025 events read in total (155824ms).
[13:14:25.519] <TB1> INFO: 4146250 events read in total (187450ms).
[13:14:57.076] <TB1> INFO: 4830985 events read in total (219007ms).
[13:15:20.026] <TB1> INFO: 5324800 events read in total (241957ms).
[13:15:20.199] <TB1> INFO: Test took 243010ms.
[13:15:53.309] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 245 (-1/-1) hits flags = 528 (plus default)
[13:15:53.323] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:15:53.323] <TB1> INFO: run 1 of 1
[13:15:53.561] <TB1> INFO: Expecting 5116800 events.
[13:16:25.581] <TB1> INFO: 708665 events read in total (31428ms).
[13:16:56.975] <TB1> INFO: 1411360 events read in total (62822ms).
[13:17:28.300] <TB1> INFO: 2111495 events read in total (94148ms).
[13:17:59.805] <TB1> INFO: 2808330 events read in total (125652ms).
[13:18:31.468] <TB1> INFO: 3503950 events read in total (157315ms).
[13:19:02.809] <TB1> INFO: 4197640 events read in total (188656ms).
[13:19:33.980] <TB1> INFO: 4891430 events read in total (219827ms).
[13:19:44.194] <TB1> INFO: 5116800 events read in total (230041ms).
[13:19:44.316] <TB1> INFO: Test took 230992ms.
[13:20:16.299] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 247 (-1/-1) hits flags = 528 (plus default)
[13:20:16.314] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:20:16.314] <TB1> INFO: run 1 of 1
[13:20:16.573] <TB1> INFO: Expecting 5158400 events.
[13:20:48.937] <TB1> INFO: 707275 events read in total (31772ms).
[13:21:20.986] <TB1> INFO: 1408325 events read in total (63821ms).
[13:21:53.443] <TB1> INFO: 2107040 events read in total (96279ms).
[13:22:26.526] <TB1> INFO: 2802655 events read in total (129361ms).
[13:22:58.436] <TB1> INFO: 3496700 events read in total (161271ms).
[13:23:28.557] <TB1> INFO: 4189290 events read in total (191392ms).
[13:23:58.937] <TB1> INFO: 4881455 events read in total (221772ms).
[13:24:10.932] <TB1> INFO: 5158400 events read in total (233767ms).
[13:24:11.186] <TB1> INFO: Test took 234872ms.
[13:24:37.821] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 227 (-1/-1) hits flags = 528 (plus default)
[13:24:37.834] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:24:37.834] <TB1> INFO: run 1 of 1
[13:24:38.074] <TB1> INFO: Expecting 4742400 events.
[13:25:09.000] <TB1> INFO: 727690 events read in total (31334ms).
[13:25:40.744] <TB1> INFO: 1448830 events read in total (62078ms).
[13:26:11.818] <TB1> INFO: 2166990 events read in total (93152ms).
[13:26:43.098] <TB1> INFO: 2881095 events read in total (124432ms).
[13:27:13.130] <TB1> INFO: 3594115 events read in total (154464ms).
[13:27:45.934] <TB1> INFO: 4304965 events read in total (187268ms).
[13:28:04.592] <TB1> INFO: 4742400 events read in total (205926ms).
[13:28:04.722] <TB1> INFO: Test took 206887ms.
[13:28:33.836] <TB1> INFO: PixTestTrim80::trimBitTest() done
[13:28:33.837] <TB1> INFO: PixTestTrim80::doTest() done, duration: 2664 seconds
[13:28:34.475] <TB1> INFO: enter test to run
[13:28:34.475] <TB1> INFO: test: exit no parameter change
[13:28:34.668] <TB1> QUIET: Connection to board 154 closed.
[13:28:34.669] <TB1> INFO: pXar: this is the end, my friend