[08:41:31.458] <TB2> INFO: *** Welcome to pxar ***
[08:41:31.458] <TB2> INFO: *** Today: 2016/10/25
[08:41:31.464] <TB2> INFO: *** Version: c8ba-dirty
[08:41:31.464] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C15.dat
[08:41:31.465] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//tbmParameters_C1b.dat
[08:41:31.465] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//defaultMaskFile.dat
[08:41:31.465] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters_C15.dat
[08:41:31.520] <TB2> INFO: clk: 4
[08:41:31.520] <TB2> INFO: ctr: 4
[08:41:31.520] <TB2> INFO: sda: 19
[08:41:31.520] <TB2> INFO: tin: 9
[08:41:31.520] <TB2> INFO: level: 15
[08:41:31.520] <TB2> INFO: triggerdelay: 0
[08:41:31.520] <TB2> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[08:41:31.520] <TB2> INFO: Log level: INFO
[08:41:31.527] <TB2> INFO: Found DTB DTB_WXC55Z
[08:41:31.537] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[08:41:31.539] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[08:41:31.541] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[08:41:33.028] <TB2> INFO: DUT info:
[08:41:33.028] <TB2> INFO: The DUT currently contains the following objects:
[08:41:33.028] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[08:41:33.028] <TB2> INFO: TBM Core alpha (0): 7 registers set
[08:41:33.028] <TB2> INFO: TBM Core beta (1): 7 registers set
[08:41:33.028] <TB2> INFO: TBM Core alpha (2): 7 registers set
[08:41:33.028] <TB2> INFO: TBM Core beta (3): 7 registers set
[08:41:33.028] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[08:41:33.028] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:33.028] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:33.028] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:33.028] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:33.028] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:33.028] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:33.028] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:33.028] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:33.028] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:33.028] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:33.028] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:33.028] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:33.028] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:33.028] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:33.028] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:33.028] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:33.429] <TB2> INFO: enter 'restricted' command line mode
[08:41:33.429] <TB2> INFO: enter test to run
[08:41:33.429] <TB2> INFO: test: pretest no parameter change
[08:41:33.429] <TB2> INFO: running: pretest
[08:41:34.321] <TB2> INFO: ######################################################################
[08:41:34.321] <TB2> INFO: PixTestPretest::doTest()
[08:41:34.321] <TB2> INFO: ######################################################################
[08:41:34.322] <TB2> INFO: ----------------------------------------------------------------------
[08:41:34.322] <TB2> INFO: PixTestPretest::programROC()
[08:41:34.322] <TB2> INFO: ----------------------------------------------------------------------
[08:41:52.335] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[08:41:52.335] <TB2> INFO: IA differences per ROC: 20.1 18.5 19.3 16.9 16.9 17.7 16.1 19.3 17.7 18.5 18.5 19.3 20.9 17.7 18.5 20.1
[08:41:52.370] <TB2> INFO: ----------------------------------------------------------------------
[08:41:52.370] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[08:41:52.370] <TB2> INFO: ----------------------------------------------------------------------
[08:42:13.610] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 387.5 mA = 24.2188 mA/ROC
[08:42:13.610] <TB2> INFO: i(loss) [mA/ROC]: 19.3 19.3 19.3 20.1 19.3 19.3 20.1 20.1 19.3 19.3 20.1 19.3 19.3 19.3 19.3 19.3
[08:42:13.638] <TB2> INFO: ----------------------------------------------------------------------
[08:42:13.638] <TB2> INFO: PixTestPretest::findTiming()
[08:42:13.638] <TB2> INFO: ----------------------------------------------------------------------
[08:42:13.638] <TB2> INFO: PixTestCmd::init()

[08:42:44.706] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[08:42:44.706] <TB2> INFO: (success/tries = 100/100), width = 4
[08:42:46.204] <TB2> INFO: ----------------------------------------------------------------------
[08:42:46.204] <TB2> INFO: PixTestPretest::findWorkingPixel()
[08:42:46.204] <TB2> INFO: ----------------------------------------------------------------------
[08:42:46.296] <TB2> INFO: Expecting 231680 events.
[08:42:56.019] <TB2> INFO: 231680 events read in total (9131ms).
[08:42:56.029] <TB2> INFO: Test took 9822ms.
[08:42:56.274] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[08:42:56.302] <TB2> INFO: ----------------------------------------------------------------------
[08:42:56.302] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[08:42:56.302] <TB2> INFO: ----------------------------------------------------------------------
[08:42:56.394] <TB2> INFO: Expecting 231680 events.
[08:43:06.298] <TB2> INFO: 231680 events read in total (9312ms).
[08:43:06.310] <TB2> INFO: Test took 10004ms.
[08:43:06.569] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[08:43:06.569] <TB2> INFO: CalDel: 87 77 81 65 83 83 108 107 90 80 92 96 94 94 96 99
[08:43:06.569] <TB2> INFO: VthrComp: 53 53 51 51 51 54 53 51 51 59 51 51 51 51 51 53
[08:43:06.572] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C0.dat
[08:43:06.572] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C1.dat
[08:43:06.572] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C2.dat
[08:43:06.572] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C3.dat
[08:43:06.572] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C4.dat
[08:43:06.572] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C5.dat
[08:43:06.572] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C6.dat
[08:43:06.572] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C7.dat
[08:43:06.573] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C8.dat
[08:43:06.573] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C9.dat
[08:43:06.573] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C10.dat
[08:43:06.573] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C11.dat
[08:43:06.573] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C12.dat
[08:43:06.573] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C13.dat
[08:43:06.573] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C14.dat
[08:43:06.573] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C15.dat
[08:43:06.573] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//tbmParameters_C0a.dat
[08:43:06.573] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//tbmParameters_C0b.dat
[08:43:06.574] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//tbmParameters_C1a.dat
[08:43:06.574] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//tbmParameters_C1b.dat
[08:43:06.574] <TB2> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[08:43:06.670] <TB2> INFO: enter test to run
[08:43:06.670] <TB2> INFO: test: FullTest no parameter change
[08:43:06.670] <TB2> INFO: running: fulltest
[08:43:06.670] <TB2> INFO: ######################################################################
[08:43:06.670] <TB2> INFO: PixTestFullTest::doTest()
[08:43:06.670] <TB2> INFO: ######################################################################
[08:43:06.671] <TB2> INFO: ######################################################################
[08:43:06.671] <TB2> INFO: PixTestAlive::doTest()
[08:43:06.671] <TB2> INFO: ######################################################################
[08:43:06.672] <TB2> INFO: ----------------------------------------------------------------------
[08:43:06.672] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:43:06.672] <TB2> INFO: ----------------------------------------------------------------------
[08:43:06.966] <TB2> INFO: Expecting 41600 events.
[08:43:10.450] <TB2> INFO: 41600 events read in total (2893ms).
[08:43:10.451] <TB2> INFO: Test took 3778ms.
[08:43:10.676] <TB2> INFO: PixTestAlive::aliveTest() done
[08:43:10.676] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[08:43:10.677] <TB2> INFO: ----------------------------------------------------------------------
[08:43:10.677] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:43:10.677] <TB2> INFO: ----------------------------------------------------------------------
[08:43:10.974] <TB2> INFO: Expecting 41600 events.
[08:43:14.046] <TB2> INFO: 41600 events read in total (2481ms).
[08:43:14.047] <TB2> INFO: Test took 3368ms.
[08:43:14.047] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[08:43:14.286] <TB2> INFO: PixTestAlive::maskTest() done
[08:43:14.286] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[08:43:14.288] <TB2> INFO: ----------------------------------------------------------------------
[08:43:14.288] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:43:14.288] <TB2> INFO: ----------------------------------------------------------------------
[08:43:14.521] <TB2> INFO: Expecting 41600 events.
[08:43:17.969] <TB2> INFO: 41600 events read in total (2856ms).
[08:43:17.969] <TB2> INFO: Test took 3680ms.
[08:43:18.196] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[08:43:18.196] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[08:43:18.196] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[08:43:18.196] <TB2> INFO: Decoding statistics:
[08:43:18.196] <TB2> INFO: General information:
[08:43:18.196] <TB2> INFO: 16bit words read: 0
[08:43:18.196] <TB2> INFO: valid events total: 0
[08:43:18.196] <TB2> INFO: empty events: 0
[08:43:18.196] <TB2> INFO: valid events with pixels: 0
[08:43:18.196] <TB2> INFO: valid pixel hits: 0
[08:43:18.196] <TB2> INFO: Event errors: 0
[08:43:18.196] <TB2> INFO: start marker: 0
[08:43:18.196] <TB2> INFO: stop marker: 0
[08:43:18.196] <TB2> INFO: overflow: 0
[08:43:18.196] <TB2> INFO: invalid 5bit words: 0
[08:43:18.196] <TB2> INFO: invalid XOR eye diagram: 0
[08:43:18.196] <TB2> INFO: frame (failed synchr.): 0
[08:43:18.196] <TB2> INFO: idle data (no TBM trl): 0
[08:43:18.196] <TB2> INFO: no data (only TBM hdr): 0
[08:43:18.196] <TB2> INFO: TBM errors: 0
[08:43:18.196] <TB2> INFO: flawed TBM headers: 0
[08:43:18.196] <TB2> INFO: flawed TBM trailers: 0
[08:43:18.196] <TB2> INFO: event ID mismatches: 0
[08:43:18.196] <TB2> INFO: ROC errors: 0
[08:43:18.196] <TB2> INFO: missing ROC header(s): 0
[08:43:18.196] <TB2> INFO: misplaced readback start: 0
[08:43:18.196] <TB2> INFO: Pixel decoding errors: 0
[08:43:18.196] <TB2> INFO: pixel data incomplete: 0
[08:43:18.196] <TB2> INFO: pixel address: 0
[08:43:18.196] <TB2> INFO: pulse height fill bit: 0
[08:43:18.196] <TB2> INFO: buffer corruption: 0
[08:43:18.203] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C15.dat
[08:43:18.203] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr_C15.dat

[08:43:18.203] <TB2> INFO: ######################################################################
[08:43:18.203] <TB2> INFO: PixTestReadback::doTest()
[08:43:18.203] <TB2> INFO: ######################################################################
[08:43:18.203] <TB2> INFO: ----------------------------------------------------------------------
[08:43:18.203] <TB2> INFO: PixTestReadback::CalibrateVd()
[08:43:18.203] <TB2> INFO: ----------------------------------------------------------------------
[08:43:28.157] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C0.dat
[08:43:28.157] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C1.dat
[08:43:28.157] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C2.dat
[08:43:28.157] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C3.dat
[08:43:28.157] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C4.dat
[08:43:28.157] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C5.dat
[08:43:28.157] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C6.dat
[08:43:28.157] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C7.dat
[08:43:28.158] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C8.dat
[08:43:28.158] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C9.dat
[08:43:28.158] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C10.dat
[08:43:28.158] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C11.dat
[08:43:28.158] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C12.dat
[08:43:28.158] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C13.dat
[08:43:28.158] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C14.dat
[08:43:28.158] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C15.dat
[08:43:28.185] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[08:43:28.185] <TB2> INFO: ----------------------------------------------------------------------
[08:43:28.185] <TB2> INFO: PixTestReadback::CalibrateVa()
[08:43:28.185] <TB2> INFO: ----------------------------------------------------------------------
[08:43:38.073] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C0.dat
[08:43:38.073] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C1.dat
[08:43:38.073] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C2.dat
[08:43:38.073] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C3.dat
[08:43:38.073] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C4.dat
[08:43:38.073] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C5.dat
[08:43:38.073] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C6.dat
[08:43:38.073] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C7.dat
[08:43:38.073] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C8.dat
[08:43:38.073] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C9.dat
[08:43:38.073] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C10.dat
[08:43:38.073] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C11.dat
[08:43:38.073] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C12.dat
[08:43:38.074] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C13.dat
[08:43:38.074] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C14.dat
[08:43:38.074] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C15.dat
[08:43:38.102] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[08:43:38.102] <TB2> INFO: ----------------------------------------------------------------------
[08:43:38.102] <TB2> INFO: PixTestReadback::readbackVbg()
[08:43:38.102] <TB2> INFO: ----------------------------------------------------------------------
[08:43:45.741] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[08:43:45.741] <TB2> INFO: ----------------------------------------------------------------------
[08:43:45.741] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[08:43:45.741] <TB2> INFO: ----------------------------------------------------------------------
[08:43:45.742] <TB2> INFO: Vbg will be calibrated using Vd calibration
[08:43:45.742] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 155.4calibrated Vbg = 1.18338 :::*/*/*/*/
[08:43:45.742] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 153.6calibrated Vbg = 1.17987 :::*/*/*/*/
[08:43:45.742] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 150.6calibrated Vbg = 1.17075 :::*/*/*/*/
[08:43:45.742] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 153.9calibrated Vbg = 1.17131 :::*/*/*/*/
[08:43:45.742] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 159.1calibrated Vbg = 1.16768 :::*/*/*/*/
[08:43:45.742] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 164.2calibrated Vbg = 1.18195 :::*/*/*/*/
[08:43:45.742] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 158.9calibrated Vbg = 1.18702 :::*/*/*/*/
[08:43:45.742] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 166.2calibrated Vbg = 1.18167 :::*/*/*/*/
[08:43:45.742] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 149calibrated Vbg = 1.16851 :::*/*/*/*/
[08:43:45.742] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 157.5calibrated Vbg = 1.17593 :::*/*/*/*/
[08:43:45.742] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 156.4calibrated Vbg = 1.1682 :::*/*/*/*/
[08:43:45.742] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 155calibrated Vbg = 1.16179 :::*/*/*/*/
[08:43:45.742] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 155.6calibrated Vbg = 1.17135 :::*/*/*/*/
[08:43:45.742] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 148calibrated Vbg = 1.17402 :::*/*/*/*/
[08:43:45.742] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 157.7calibrated Vbg = 1.17507 :::*/*/*/*/
[08:43:45.742] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 150.2calibrated Vbg = 1.1808 :::*/*/*/*/
[08:43:45.744] <TB2> INFO: ----------------------------------------------------------------------
[08:43:45.744] <TB2> INFO: PixTestReadback::CalibrateIa()
[08:43:45.744] <TB2> INFO: ----------------------------------------------------------------------
[08:46:26.016] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C0.dat
[08:46:26.016] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C1.dat
[08:46:26.017] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C2.dat
[08:46:26.017] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C3.dat
[08:46:26.017] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C4.dat
[08:46:26.017] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C5.dat
[08:46:26.017] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C6.dat
[08:46:26.017] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C7.dat
[08:46:26.017] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C8.dat
[08:46:26.017] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C9.dat
[08:46:26.017] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C10.dat
[08:46:26.017] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C11.dat
[08:46:26.017] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C12.dat
[08:46:26.017] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C13.dat
[08:46:26.017] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C14.dat
[08:46:26.017] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C15.dat
[08:46:26.045] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[08:46:26.046] <TB2> INFO: PixTestReadback::doTest() done
[08:46:26.046] <TB2> INFO: Decoding statistics:
[08:46:26.046] <TB2> INFO: General information:
[08:46:26.046] <TB2> INFO: 16bit words read: 1536
[08:46:26.046] <TB2> INFO: valid events total: 256
[08:46:26.046] <TB2> INFO: empty events: 256
[08:46:26.046] <TB2> INFO: valid events with pixels: 0
[08:46:26.046] <TB2> INFO: valid pixel hits: 0
[08:46:26.046] <TB2> INFO: Event errors: 0
[08:46:26.046] <TB2> INFO: start marker: 0
[08:46:26.046] <TB2> INFO: stop marker: 0
[08:46:26.046] <TB2> INFO: overflow: 0
[08:46:26.046] <TB2> INFO: invalid 5bit words: 0
[08:46:26.046] <TB2> INFO: invalid XOR eye diagram: 0
[08:46:26.046] <TB2> INFO: frame (failed synchr.): 0
[08:46:26.047] <TB2> INFO: idle data (no TBM trl): 0
[08:46:26.047] <TB2> INFO: no data (only TBM hdr): 0
[08:46:26.047] <TB2> INFO: TBM errors: 0
[08:46:26.047] <TB2> INFO: flawed TBM headers: 0
[08:46:26.047] <TB2> INFO: flawed TBM trailers: 0
[08:46:26.047] <TB2> INFO: event ID mismatches: 0
[08:46:26.047] <TB2> INFO: ROC errors: 0
[08:46:26.047] <TB2> INFO: missing ROC header(s): 0
[08:46:26.047] <TB2> INFO: misplaced readback start: 0
[08:46:26.047] <TB2> INFO: Pixel decoding errors: 0
[08:46:26.047] <TB2> INFO: pixel data incomplete: 0
[08:46:26.047] <TB2> INFO: pixel address: 0
[08:46:26.047] <TB2> INFO: pulse height fill bit: 0
[08:46:26.047] <TB2> INFO: buffer corruption: 0
[08:46:26.081] <TB2> INFO: ######################################################################
[08:46:26.081] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[08:46:26.081] <TB2> INFO: ######################################################################
[08:46:26.084] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[08:46:26.099] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[08:46:26.099] <TB2> INFO: run 1 of 1
[08:46:26.382] <TB2> INFO: Expecting 3120000 events.
[08:46:57.855] <TB2> INFO: 675415 events read in total (30881ms).











[08:47:28.038] <TB2> INFO: 1347595 events read in total (61064ms).











[08:47:58.949] <TB2> INFO: 2017940 events read in total (91975ms).











[08:48:30.024] <TB2> INFO: 2689125 events read in total (123050ms).











[08:48:49.712] <TB2> INFO: 3120000 events read in total (142738ms).
[08:48:49.774] <TB2> INFO: Test took 143676ms.
[08:49:14.383] <TB2> INFO: PixTestBBMap::doTest() done with 4 decoding errors: , duration: 168 seconds
[08:49:14.383] <TB2> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[08:49:14.383] <TB2> INFO: separation cut (per ROC): 105 107 113 110 104 112 104 111 109 121 105 114 112 103 106 110
[08:49:14.384] <TB2> INFO: Decoding statistics:
[08:49:14.384] <TB2> INFO: General information:
[08:49:14.384] <TB2> INFO: 16bit words read: 0
[08:49:14.384] <TB2> INFO: valid events total: 0
[08:49:14.384] <TB2> INFO: empty events: 0
[08:49:14.384] <TB2> INFO: valid events with pixels: 0
[08:49:14.384] <TB2> INFO: valid pixel hits: 0
[08:49:14.384] <TB2> INFO: Event errors: 0
[08:49:14.384] <TB2> INFO: start marker: 0
[08:49:14.384] <TB2> INFO: stop marker: 0
[08:49:14.384] <TB2> INFO: overflow: 0
[08:49:14.384] <TB2> INFO: invalid 5bit words: 0
[08:49:14.384] <TB2> INFO: invalid XOR eye diagram: 0
[08:49:14.384] <TB2> INFO: frame (failed synchr.): 0
[08:49:14.384] <TB2> INFO: idle data (no TBM trl): 0
[08:49:14.384] <TB2> INFO: no data (only TBM hdr): 0
[08:49:14.384] <TB2> INFO: TBM errors: 0
[08:49:14.384] <TB2> INFO: flawed TBM headers: 0
[08:49:14.384] <TB2> INFO: flawed TBM trailers: 0
[08:49:14.384] <TB2> INFO: event ID mismatches: 0
[08:49:14.384] <TB2> INFO: ROC errors: 0
[08:49:14.384] <TB2> INFO: missing ROC header(s): 0
[08:49:14.384] <TB2> INFO: misplaced readback start: 0
[08:49:14.384] <TB2> INFO: Pixel decoding errors: 0
[08:49:14.384] <TB2> INFO: pixel data incomplete: 0
[08:49:14.384] <TB2> INFO: pixel address: 0
[08:49:14.384] <TB2> INFO: pulse height fill bit: 0
[08:49:14.384] <TB2> INFO: buffer corruption: 0
[08:49:14.423] <TB2> INFO: ######################################################################
[08:49:14.423] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[08:49:14.423] <TB2> INFO: ######################################################################
[08:49:14.423] <TB2> INFO: ----------------------------------------------------------------------
[08:49:14.423] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[08:49:14.423] <TB2> INFO: ----------------------------------------------------------------------
[08:49:14.423] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[08:49:14.434] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[08:49:14.434] <TB2> INFO: run 1 of 1
[08:49:14.683] <TB2> INFO: Expecting 36608000 events.
[08:49:39.551] <TB2> INFO: 719700 events read in total (24277ms).
[08:50:03.095] <TB2> INFO: 1416500 events read in total (47821ms).
[08:50:26.644] <TB2> INFO: 2117350 events read in total (71370ms).
[08:50:50.255] <TB2> INFO: 2811550 events read in total (94981ms).
[08:51:13.616] <TB2> INFO: 3508450 events read in total (118342ms).
[08:51:36.932] <TB2> INFO: 4197300 events read in total (141658ms).
[08:52:00.509] <TB2> INFO: 4893550 events read in total (165235ms).
[08:52:23.701] <TB2> INFO: 5583600 events read in total (188427ms).
[08:52:47.130] <TB2> INFO: 6277350 events read in total (211856ms).
[08:53:10.176] <TB2> INFO: 6967550 events read in total (234902ms).
[08:53:34.088] <TB2> INFO: 7662400 events read in total (258814ms).
[08:53:57.685] <TB2> INFO: 8353700 events read in total (282411ms).
[08:54:20.649] <TB2> INFO: 9047500 events read in total (305375ms).
[08:54:44.254] <TB2> INFO: 9737700 events read in total (328980ms).
[08:55:07.448] <TB2> INFO: 10431050 events read in total (352174ms).
[08:55:30.895] <TB2> INFO: 11122250 events read in total (375621ms).
[08:55:54.156] <TB2> INFO: 11814750 events read in total (398882ms).
[08:56:17.526] <TB2> INFO: 12502600 events read in total (422252ms).
[08:56:41.485] <TB2> INFO: 13195450 events read in total (446211ms).
[08:57:04.878] <TB2> INFO: 13883850 events read in total (469604ms).
[08:57:28.396] <TB2> INFO: 14573200 events read in total (493122ms).
[08:57:51.850] <TB2> INFO: 15261850 events read in total (516576ms).
[08:58:15.259] <TB2> INFO: 15950050 events read in total (539985ms).
[08:58:38.492] <TB2> INFO: 16636100 events read in total (563218ms).
[08:59:01.537] <TB2> INFO: 17321650 events read in total (586263ms).
[08:59:25.017] <TB2> INFO: 18007700 events read in total (609743ms).
[08:59:48.481] <TB2> INFO: 18694100 events read in total (633207ms).
[09:00:11.405] <TB2> INFO: 19377500 events read in total (656131ms).
[09:00:34.688] <TB2> INFO: 20061400 events read in total (679414ms).
[09:00:57.745] <TB2> INFO: 20745350 events read in total (702471ms).
[09:01:21.195] <TB2> INFO: 21427400 events read in total (725921ms).
[09:01:44.898] <TB2> INFO: 22110650 events read in total (749624ms).
[09:02:07.928] <TB2> INFO: 22791050 events read in total (772654ms).
[09:02:31.137] <TB2> INFO: 23474000 events read in total (795863ms).
[09:02:54.556] <TB2> INFO: 24154150 events read in total (819282ms).
[09:03:17.684] <TB2> INFO: 24836700 events read in total (842410ms).
[09:03:40.515] <TB2> INFO: 25517100 events read in total (865241ms).
[09:04:03.713] <TB2> INFO: 26198650 events read in total (888439ms).
[09:04:26.957] <TB2> INFO: 26877950 events read in total (911683ms).
[09:04:50.332] <TB2> INFO: 27560550 events read in total (935058ms).
[09:05:13.626] <TB2> INFO: 28238400 events read in total (958352ms).
[09:05:36.809] <TB2> INFO: 28919450 events read in total (981535ms).
[09:05:59.944] <TB2> INFO: 29593500 events read in total (1004670ms).
[09:06:23.133] <TB2> INFO: 30275600 events read in total (1027859ms).
[09:06:46.107] <TB2> INFO: 30952700 events read in total (1050833ms).
[09:07:09.050] <TB2> INFO: 31631000 events read in total (1073776ms).
[09:07:32.517] <TB2> INFO: 32304800 events read in total (1097244ms).
[09:07:55.695] <TB2> INFO: 32986100 events read in total (1120421ms).
[09:08:19.349] <TB2> INFO: 33664800 events read in total (1144075ms).
[09:08:42.667] <TB2> INFO: 34349750 events read in total (1167393ms).
[09:09:06.594] <TB2> INFO: 35031100 events read in total (1191320ms).
[09:09:29.815] <TB2> INFO: 35713350 events read in total (1214541ms).
[09:09:53.322] <TB2> INFO: 36403450 events read in total (1238048ms).
[09:10:00.364] <TB2> INFO: 36608000 events read in total (1245090ms).
[09:10:00.411] <TB2> INFO: Test took 1245976ms.
[09:10:00.880] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:10:03.198] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:10:05.598] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:10:07.353] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:10:09.742] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:10:11.580] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:10:13.236] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:10:15.246] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:10:17.315] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:10:19.081] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:10:20.862] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:10:23.169] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:10:24.902] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:10:26.337] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:10:27.740] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:10:29.170] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:10:30.609] <TB2> INFO: PixTestScurves::scurves() done
[09:10:30.609] <TB2> INFO: Vcal mean: 129.39 130.40 126.95 126.27 124.05 129.83 123.01 124.41 129.39 133.10 126.07 132.75 135.19 120.60 128.67 137.28
[09:10:30.609] <TB2> INFO: Vcal RMS: 5.99 5.91 6.24 5.85 6.05 6.33 6.79 5.99 6.16 6.56 6.50 6.57 6.30 6.16 6.61 6.19
[09:10:30.609] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1276 seconds
[09:10:30.609] <TB2> INFO: Decoding statistics:
[09:10:30.609] <TB2> INFO: General information:
[09:10:30.609] <TB2> INFO: 16bit words read: 0
[09:10:30.609] <TB2> INFO: valid events total: 0
[09:10:30.609] <TB2> INFO: empty events: 0
[09:10:30.609] <TB2> INFO: valid events with pixels: 0
[09:10:30.609] <TB2> INFO: valid pixel hits: 0
[09:10:30.609] <TB2> INFO: Event errors: 0
[09:10:30.609] <TB2> INFO: start marker: 0
[09:10:30.609] <TB2> INFO: stop marker: 0
[09:10:30.609] <TB2> INFO: overflow: 0
[09:10:30.609] <TB2> INFO: invalid 5bit words: 0
[09:10:30.609] <TB2> INFO: invalid XOR eye diagram: 0
[09:10:30.609] <TB2> INFO: frame (failed synchr.): 0
[09:10:30.609] <TB2> INFO: idle data (no TBM trl): 0
[09:10:30.609] <TB2> INFO: no data (only TBM hdr): 0
[09:10:30.609] <TB2> INFO: TBM errors: 0
[09:10:30.609] <TB2> INFO: flawed TBM headers: 0
[09:10:30.609] <TB2> INFO: flawed TBM trailers: 0
[09:10:30.609] <TB2> INFO: event ID mismatches: 0
[09:10:30.609] <TB2> INFO: ROC errors: 0
[09:10:30.609] <TB2> INFO: missing ROC header(s): 0
[09:10:30.609] <TB2> INFO: misplaced readback start: 0
[09:10:30.609] <TB2> INFO: Pixel decoding errors: 0
[09:10:30.609] <TB2> INFO: pixel data incomplete: 0
[09:10:30.609] <TB2> INFO: pixel address: 0
[09:10:30.609] <TB2> INFO: pulse height fill bit: 0
[09:10:30.609] <TB2> INFO: buffer corruption: 0
[09:10:30.673] <TB2> INFO: ######################################################################
[09:10:30.673] <TB2> INFO: PixTestTrim::doTest()
[09:10:30.673] <TB2> INFO: ######################################################################
[09:10:30.674] <TB2> INFO: ----------------------------------------------------------------------
[09:10:30.674] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[09:10:30.674] <TB2> INFO: ----------------------------------------------------------------------
[09:10:30.714] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[09:10:30.714] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[09:10:30.723] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[09:10:30.723] <TB2> INFO: run 1 of 1
[09:10:30.954] <TB2> INFO: Expecting 5025280 events.
[09:11:02.779] <TB2> INFO: 839024 events read in total (31231ms).
[09:11:33.442] <TB2> INFO: 1676328 events read in total (61895ms).
[09:12:04.871] <TB2> INFO: 2511200 events read in total (93324ms).
[09:12:36.086] <TB2> INFO: 3340880 events read in total (124538ms).
[09:13:05.943] <TB2> INFO: 4165848 events read in total (154395ms).
[09:13:36.759] <TB2> INFO: 4989560 events read in total (185211ms).
[09:13:38.515] <TB2> INFO: 5025280 events read in total (186967ms).
[09:13:38.565] <TB2> INFO: Test took 187842ms.
[09:13:56.323] <TB2> INFO: ROC 0 VthrComp = 132
[09:13:56.323] <TB2> INFO: ROC 1 VthrComp = 133
[09:13:56.323] <TB2> INFO: ROC 2 VthrComp = 132
[09:13:56.324] <TB2> INFO: ROC 3 VthrComp = 129
[09:13:56.324] <TB2> INFO: ROC 4 VthrComp = 118
[09:13:56.324] <TB2> INFO: ROC 5 VthrComp = 129
[09:13:56.324] <TB2> INFO: ROC 6 VthrComp = 117
[09:13:56.324] <TB2> INFO: ROC 7 VthrComp = 128
[09:13:56.324] <TB2> INFO: ROC 8 VthrComp = 129
[09:13:56.324] <TB2> INFO: ROC 9 VthrComp = 133
[09:13:56.324] <TB2> INFO: ROC 10 VthrComp = 121
[09:13:56.325] <TB2> INFO: ROC 11 VthrComp = 128
[09:13:56.325] <TB2> INFO: ROC 12 VthrComp = 132
[09:13:56.325] <TB2> INFO: ROC 13 VthrComp = 114
[09:13:56.325] <TB2> INFO: ROC 14 VthrComp = 125
[09:13:56.325] <TB2> INFO: ROC 15 VthrComp = 130
[09:13:56.558] <TB2> INFO: Expecting 41600 events.
[09:14:00.110] <TB2> INFO: 41600 events read in total (2960ms).
[09:14:00.111] <TB2> INFO: Test took 3784ms.
[09:14:00.119] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[09:14:00.119] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[09:14:00.130] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[09:14:00.130] <TB2> INFO: run 1 of 1
[09:14:00.408] <TB2> INFO: Expecting 5025280 events.
[09:14:27.513] <TB2> INFO: 593640 events read in total (26513ms).
[09:14:53.854] <TB2> INFO: 1185296 events read in total (52854ms).
[09:15:19.713] <TB2> INFO: 1776888 events read in total (78713ms).
[09:15:45.987] <TB2> INFO: 2368440 events read in total (104987ms).
[09:16:11.823] <TB2> INFO: 2957032 events read in total (130823ms).
[09:16:38.240] <TB2> INFO: 3544600 events read in total (157240ms).
[09:17:04.632] <TB2> INFO: 4131040 events read in total (183632ms).
[09:17:30.483] <TB2> INFO: 4717072 events read in total (209483ms).
[09:17:44.855] <TB2> INFO: 5025280 events read in total (223855ms).
[09:17:44.914] <TB2> INFO: Test took 224784ms.
[09:18:08.809] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 61.6396 for pixel 5/5 mean/min/max = 46.9462/32.221/61.6714
[09:18:08.809] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 62.324 for pixel 26/1 mean/min/max = 46.7899/31.2491/62.3307
[09:18:08.809] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 61.0047 for pixel 5/2 mean/min/max = 47.1855/33.3318/61.0393
[09:18:08.810] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 62.6894 for pixel 50/33 mean/min/max = 48.1267/33.5562/62.6973
[09:18:08.810] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 61.2768 for pixel 51/4 mean/min/max = 46.7703/32.0091/61.5314
[09:18:08.810] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 64.0332 for pixel 11/17 mean/min/max = 49.0275/33.9794/64.0756
[09:18:08.810] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 65.8409 for pixel 14/1 mean/min/max = 48.1581/30.2912/66.0251
[09:18:08.811] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 61.4688 for pixel 0/6 mean/min/max = 46.392/31.3103/61.4737
[09:18:08.811] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 60.3088 for pixel 26/0 mean/min/max = 45.8475/31.3858/60.3091
[09:18:08.811] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 68.3297 for pixel 0/42 mean/min/max = 51.3431/34.204/68.4822
[09:18:08.811] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 61.8154 for pixel 4/73 mean/min/max = 47.3899/32.8815/61.8983
[09:18:08.812] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 61.3034 for pixel 0/7 mean/min/max = 46.3033/31.2827/61.3239
[09:18:08.812] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 61.993 for pixel 0/53 mean/min/max = 47.5271/32.9389/62.1153
[09:18:08.812] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 59.5515 for pixel 15/64 mean/min/max = 46.1534/32.7137/59.5932
[09:18:08.812] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 61.6376 for pixel 8/14 mean/min/max = 46.5414/31.4126/61.6702
[09:18:08.813] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 66.3093 for pixel 30/63 mean/min/max = 50.5328/34.653/66.4126
[09:18:08.813] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:18:08.901] <TB2> INFO: Expecting 411648 events.
[09:18:18.388] <TB2> INFO: 411648 events read in total (8895ms).
[09:18:18.397] <TB2> INFO: Expecting 411648 events.
[09:18:27.704] <TB2> INFO: 411648 events read in total (8904ms).
[09:18:27.713] <TB2> INFO: Expecting 411648 events.
[09:18:36.969] <TB2> INFO: 411648 events read in total (8853ms).
[09:18:36.981] <TB2> INFO: Expecting 411648 events.
[09:18:46.428] <TB2> INFO: 411648 events read in total (9044ms).
[09:18:46.451] <TB2> INFO: Expecting 411648 events.
[09:18:55.697] <TB2> INFO: 411648 events read in total (8843ms).
[09:18:55.715] <TB2> INFO: Expecting 411648 events.
[09:19:05.078] <TB2> INFO: 411648 events read in total (8960ms).
[09:19:05.097] <TB2> INFO: Expecting 411648 events.
[09:19:14.368] <TB2> INFO: 411648 events read in total (8868ms).
[09:19:14.402] <TB2> INFO: Expecting 411648 events.
[09:19:23.702] <TB2> INFO: 411648 events read in total (8897ms).
[09:19:23.727] <TB2> INFO: Expecting 411648 events.
[09:19:32.933] <TB2> INFO: 411648 events read in total (8803ms).
[09:19:32.961] <TB2> INFO: Expecting 411648 events.
[09:19:42.211] <TB2> INFO: 411648 events read in total (8847ms).
[09:19:42.254] <TB2> INFO: Expecting 411648 events.
[09:19:51.453] <TB2> INFO: 411648 events read in total (8796ms).
[09:19:51.485] <TB2> INFO: Expecting 411648 events.
[09:20:00.739] <TB2> INFO: 411648 events read in total (8851ms).
[09:20:00.773] <TB2> INFO: Expecting 411648 events.
[09:20:09.986] <TB2> INFO: 411648 events read in total (8811ms).
[09:20:10.021] <TB2> INFO: Expecting 411648 events.
[09:20:19.274] <TB2> INFO: 411648 events read in total (8850ms).
[09:20:19.330] <TB2> INFO: Expecting 411648 events.
[09:20:28.626] <TB2> INFO: 411648 events read in total (8893ms).
[09:20:28.668] <TB2> INFO: Expecting 411648 events.
[09:20:37.907] <TB2> INFO: 411648 events read in total (8836ms).
[09:20:37.971] <TB2> INFO: Test took 149158ms.
[09:20:38.808] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[09:20:38.820] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[09:20:38.820] <TB2> INFO: run 1 of 1
[09:20:39.066] <TB2> INFO: Expecting 5025280 events.
[09:21:05.945] <TB2> INFO: 592432 events read in total (26287ms).
[09:21:32.137] <TB2> INFO: 1183736 events read in total (52479ms).
[09:21:58.420] <TB2> INFO: 1774888 events read in total (78762ms).
[09:22:25.229] <TB2> INFO: 2366928 events read in total (105571ms).
[09:22:51.883] <TB2> INFO: 2958936 events read in total (132226ms).
[09:23:18.368] <TB2> INFO: 3555520 events read in total (158710ms).
[09:23:44.927] <TB2> INFO: 4148856 events read in total (185269ms).
[09:24:11.361] <TB2> INFO: 4742064 events read in total (211703ms).
[09:24:23.854] <TB2> INFO: 5025280 events read in total (224196ms).
[09:24:23.963] <TB2> INFO: Test took 225144ms.
[09:24:43.248] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 1.500000 .. 146.415215
[09:24:43.481] <TB2> INFO: Expecting 208000 events.
[09:24:53.141] <TB2> INFO: 208000 events read in total (9069ms).
[09:24:53.142] <TB2> INFO: Test took 9893ms.
[09:24:53.194] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 1 .. 156 (-1/-1) hits flags = 528 (plus default)
[09:24:53.204] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[09:24:53.205] <TB2> INFO: run 1 of 1
[09:24:53.482] <TB2> INFO: Expecting 5191680 events.
[09:25:20.064] <TB2> INFO: 584584 events read in total (25990ms).
[09:25:45.981] <TB2> INFO: 1169544 events read in total (51907ms).
[09:26:12.522] <TB2> INFO: 1754128 events read in total (78448ms).
[09:26:38.978] <TB2> INFO: 2338640 events read in total (104904ms).
[09:27:04.876] <TB2> INFO: 2923144 events read in total (130802ms).
[09:27:30.891] <TB2> INFO: 3507816 events read in total (156817ms).
[09:27:56.927] <TB2> INFO: 4091808 events read in total (182853ms).
[09:28:22.648] <TB2> INFO: 4675000 events read in total (208574ms).
[09:28:45.523] <TB2> INFO: 5191680 events read in total (231449ms).
[09:28:45.623] <TB2> INFO: Test took 232418ms.
[09:29:11.672] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.070670 .. 47.182620
[09:29:11.965] <TB2> INFO: Expecting 208000 events.
[09:29:21.682] <TB2> INFO: 208000 events read in total (9126ms).
[09:29:21.683] <TB2> INFO: Test took 10009ms.
[09:29:21.730] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 57 (-1/-1) hits flags = 528 (plus default)
[09:29:21.740] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[09:29:21.740] <TB2> INFO: run 1 of 1
[09:29:22.018] <TB2> INFO: Expecting 1364480 events.
[09:29:50.132] <TB2> INFO: 656464 events read in total (27523ms).
[09:30:17.314] <TB2> INFO: 1309216 events read in total (54705ms).
[09:30:20.062] <TB2> INFO: 1364480 events read in total (57453ms).
[09:30:20.091] <TB2> INFO: Test took 58351ms.
[09:30:33.478] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 27.612739 .. 49.775168
[09:30:33.711] <TB2> INFO: Expecting 208000 events.
[09:30:43.562] <TB2> INFO: 208000 events read in total (9260ms).
[09:30:43.563] <TB2> INFO: Test took 10084ms.
[09:30:43.639] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 59 (-1/-1) hits flags = 528 (plus default)
[09:30:43.651] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[09:30:43.651] <TB2> INFO: run 1 of 1
[09:30:43.929] <TB2> INFO: Expecting 1431040 events.
[09:31:12.865] <TB2> INFO: 648048 events read in total (28345ms).
[09:31:40.890] <TB2> INFO: 1294216 events read in total (56371ms).
[09:31:47.083] <TB2> INFO: 1431040 events read in total (62564ms).
[09:31:47.110] <TB2> INFO: Test took 63460ms.
[09:31:58.492] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 26.885070 .. 48.318026
[09:31:58.724] <TB2> INFO: Expecting 208000 events.
[09:32:08.782] <TB2> INFO: 208000 events read in total (9466ms).
[09:32:08.783] <TB2> INFO: Test took 10291ms.
[09:32:08.864] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 58 (-1/-1) hits flags = 528 (plus default)
[09:32:08.876] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[09:32:08.876] <TB2> INFO: run 1 of 1
[09:32:09.154] <TB2> INFO: Expecting 1431040 events.
[09:32:37.909] <TB2> INFO: 653072 events read in total (28163ms).
[09:33:05.556] <TB2> INFO: 1304928 events read in total (55811ms).
[09:33:11.492] <TB2> INFO: 1431040 events read in total (61746ms).
[09:33:11.517] <TB2> INFO: Test took 62642ms.
[09:33:23.034] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[09:33:23.034] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[09:33:23.044] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[09:33:23.044] <TB2> INFO: run 1 of 1
[09:33:23.312] <TB2> INFO: Expecting 1364480 events.
[09:33:52.658] <TB2> INFO: 668760 events read in total (28754ms).
[09:34:20.712] <TB2> INFO: 1336848 events read in total (56808ms).
[09:34:22.377] <TB2> INFO: 1364480 events read in total (58473ms).
[09:34:22.400] <TB2> INFO: Test took 59357ms.
[09:34:33.457] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C0.dat
[09:34:33.457] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C1.dat
[09:34:33.457] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C2.dat
[09:34:33.458] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C3.dat
[09:34:33.458] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C4.dat
[09:34:33.458] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C5.dat
[09:34:33.458] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C6.dat
[09:34:33.458] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C7.dat
[09:34:33.458] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C8.dat
[09:34:33.458] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C9.dat
[09:34:33.458] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C10.dat
[09:34:33.458] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C11.dat
[09:34:33.458] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C12.dat
[09:34:33.458] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C13.dat
[09:34:33.458] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C14.dat
[09:34:33.459] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C15.dat
[09:34:33.459] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C0.dat
[09:34:33.464] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C1.dat
[09:34:33.470] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C2.dat
[09:34:33.476] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C3.dat
[09:34:33.481] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C4.dat
[09:34:33.487] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C5.dat
[09:34:33.492] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C6.dat
[09:34:33.498] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C7.dat
[09:34:33.503] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C8.dat
[09:34:33.509] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C9.dat
[09:34:33.514] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C10.dat
[09:34:33.520] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C11.dat
[09:34:33.525] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C12.dat
[09:34:33.531] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C13.dat
[09:34:33.536] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C14.dat
[09:34:33.542] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C15.dat
[09:34:33.547] <TB2> INFO: PixTestTrim::trimTest() done
[09:34:33.547] <TB2> INFO: vtrim: 139 166 155 173 130 148 140 120 153 148 129 121 132 117 153 157
[09:34:33.547] <TB2> INFO: vthrcomp: 132 133 132 129 118 129 117 128 129 133 121 128 132 114 125 130
[09:34:33.547] <TB2> INFO: vcal mean: 35.04 35.08 34.99 35.16 34.89 35.11 35.05 34.97 35.11 35.49 35.06 35.07 35.16 34.98 35.24 35.94
[09:34:33.547] <TB2> INFO: vcal RMS: 1.17 1.29 1.07 1.26 1.15 1.23 1.23 1.06 1.27 1.67 1.18 1.29 1.31 1.06 1.47 2.14
[09:34:33.547] <TB2> INFO: bits mean: 9.66 10.03 9.41 9.90 9.69 9.01 9.51 9.19 10.56 8.72 9.57 9.37 9.26 9.67 10.63 9.62
[09:34:33.547] <TB2> INFO: bits RMS: 2.57 2.54 2.48 2.23 2.56 2.50 2.74 2.89 2.37 2.55 2.50 2.89 2.61 2.52 2.25 2.29
[09:34:33.554] <TB2> INFO: ----------------------------------------------------------------------
[09:34:33.554] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[09:34:33.554] <TB2> INFO: ----------------------------------------------------------------------
[09:34:33.556] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[09:34:33.565] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[09:34:33.565] <TB2> INFO: run 1 of 1
[09:34:33.798] <TB2> INFO: Expecting 4160000 events.
[09:35:07.914] <TB2> INFO: 788880 events read in total (33525ms).
[09:35:40.727] <TB2> INFO: 1570690 events read in total (66338ms).
[09:36:13.520] <TB2> INFO: 2348035 events read in total (99131ms).
[09:36:46.692] <TB2> INFO: 3119955 events read in total (132303ms).
[09:37:19.216] <TB2> INFO: 3888655 events read in total (164827ms).
[09:37:31.248] <TB2> INFO: 4160000 events read in total (176859ms).
[09:37:31.306] <TB2> INFO: Test took 177741ms.
[09:37:54.546] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[09:37:54.556] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[09:37:54.556] <TB2> INFO: run 1 of 1
[09:37:54.847] <TB2> INFO: Expecting 5324800 events.
[09:38:26.570] <TB2> INFO: 696345 events read in total (31131ms).
[09:38:57.529] <TB2> INFO: 1387875 events read in total (62090ms).
[09:39:28.175] <TB2> INFO: 2078385 events read in total (92736ms).
[09:39:59.336] <TB2> INFO: 2766845 events read in total (123897ms).
[09:40:30.179] <TB2> INFO: 3452210 events read in total (154740ms).
[09:41:00.540] <TB2> INFO: 4136975 events read in total (185101ms).
[09:41:31.341] <TB2> INFO: 4819880 events read in total (215902ms).
[09:41:53.913] <TB2> INFO: 5324800 events read in total (238474ms).
[09:41:53.985] <TB2> INFO: Test took 239428ms.
[09:42:23.717] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 209 (-1/-1) hits flags = 528 (plus default)
[09:42:23.727] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[09:42:23.727] <TB2> INFO: run 1 of 1
[09:42:23.963] <TB2> INFO: Expecting 4368000 events.
[09:42:57.015] <TB2> INFO: 746630 events read in total (32460ms).
[09:43:28.563] <TB2> INFO: 1487435 events read in total (64008ms).
[09:44:00.543] <TB2> INFO: 2225000 events read in total (95989ms).
[09:44:31.991] <TB2> INFO: 2957920 events read in total (127436ms).
[09:45:03.814] <TB2> INFO: 3688115 events read in total (159259ms).
[09:45:33.251] <TB2> INFO: 4368000 events read in total (188696ms).
[09:45:33.306] <TB2> INFO: Test took 189579ms.
[09:46:01.067] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 209 (-1/-1) hits flags = 528 (plus default)
[09:46:01.079] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[09:46:01.079] <TB2> INFO: run 1 of 1
[09:46:01.350] <TB2> INFO: Expecting 4368000 events.
[09:46:33.694] <TB2> INFO: 747075 events read in total (31753ms).
[09:47:05.922] <TB2> INFO: 1487770 events read in total (63980ms).
[09:47:37.830] <TB2> INFO: 2225890 events read in total (95889ms).
[09:48:09.842] <TB2> INFO: 2959275 events read in total (127900ms).
[09:48:41.411] <TB2> INFO: 3689635 events read in total (159469ms).
[09:49:10.773] <TB2> INFO: 4368000 events read in total (188831ms).
[09:49:10.825] <TB2> INFO: Test took 189746ms.
[09:49:36.222] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 210 (-1/-1) hits flags = 528 (plus default)
[09:49:36.231] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[09:49:36.231] <TB2> INFO: run 1 of 1
[09:49:36.463] <TB2> INFO: Expecting 4388800 events.
[09:50:08.890] <TB2> INFO: 745870 events read in total (31836ms).
[09:50:40.897] <TB2> INFO: 1485955 events read in total (63843ms).
[09:51:12.697] <TB2> INFO: 2222975 events read in total (95643ms).
[09:51:44.904] <TB2> INFO: 2955510 events read in total (127850ms).
[09:52:16.746] <TB2> INFO: 3684855 events read in total (159692ms).
[09:52:47.698] <TB2> INFO: 4388800 events read in total (190644ms).
[09:52:47.752] <TB2> INFO: Test took 191521ms.
[09:53:12.798] <TB2> INFO: PixTestTrim::trimBitTest() done
[09:53:12.799] <TB2> INFO: PixTestTrim::doTest() done, duration: 2562 seconds
[09:53:12.799] <TB2> INFO: Decoding statistics:
[09:53:12.799] <TB2> INFO: General information:
[09:53:12.799] <TB2> INFO: 16bit words read: 0
[09:53:12.799] <TB2> INFO: valid events total: 0
[09:53:12.799] <TB2> INFO: empty events: 0
[09:53:12.799] <TB2> INFO: valid events with pixels: 0
[09:53:12.799] <TB2> INFO: valid pixel hits: 0
[09:53:12.799] <TB2> INFO: Event errors: 0
[09:53:12.799] <TB2> INFO: start marker: 0
[09:53:12.799] <TB2> INFO: stop marker: 0
[09:53:12.799] <TB2> INFO: overflow: 0
[09:53:12.799] <TB2> INFO: invalid 5bit words: 0
[09:53:12.799] <TB2> INFO: invalid XOR eye diagram: 0
[09:53:12.799] <TB2> INFO: frame (failed synchr.): 0
[09:53:12.799] <TB2> INFO: idle data (no TBM trl): 0
[09:53:12.799] <TB2> INFO: no data (only TBM hdr): 0
[09:53:12.799] <TB2> INFO: TBM errors: 0
[09:53:12.799] <TB2> INFO: flawed TBM headers: 0
[09:53:12.799] <TB2> INFO: flawed TBM trailers: 0
[09:53:12.799] <TB2> INFO: event ID mismatches: 0
[09:53:12.799] <TB2> INFO: ROC errors: 0
[09:53:12.799] <TB2> INFO: missing ROC header(s): 0
[09:53:12.799] <TB2> INFO: misplaced readback start: 0
[09:53:12.799] <TB2> INFO: Pixel decoding errors: 0
[09:53:12.799] <TB2> INFO: pixel data incomplete: 0
[09:53:12.799] <TB2> INFO: pixel address: 0
[09:53:12.799] <TB2> INFO: pulse height fill bit: 0
[09:53:12.799] <TB2> INFO: buffer corruption: 0
[09:53:13.413] <TB2> INFO: ######################################################################
[09:53:13.413] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[09:53:13.413] <TB2> INFO: ######################################################################
[09:53:13.646] <TB2> INFO: Expecting 41600 events.
[09:53:17.210] <TB2> INFO: 41600 events read in total (2973ms).
[09:53:17.211] <TB2> INFO: Test took 3797ms.
[09:53:17.646] <TB2> INFO: Expecting 41600 events.
[09:53:21.116] <TB2> INFO: 41600 events read in total (2879ms).
[09:53:21.117] <TB2> INFO: Test took 3703ms.
[09:53:21.408] <TB2> INFO: Expecting 41600 events.
[09:53:24.942] <TB2> INFO: 41600 events read in total (2942ms).
[09:53:24.943] <TB2> INFO: Test took 3799ms.
[09:53:25.263] <TB2> INFO: Expecting 41600 events.
[09:53:28.756] <TB2> INFO: 41600 events read in total (2901ms).
[09:53:28.756] <TB2> INFO: Test took 3786ms.
[09:53:29.075] <TB2> INFO: Expecting 41600 events.
[09:53:32.816] <TB2> INFO: 41600 events read in total (3149ms).
[09:53:32.817] <TB2> INFO: Test took 4033ms.
[09:53:33.108] <TB2> INFO: Expecting 41600 events.
[09:53:36.722] <TB2> INFO: 41600 events read in total (3022ms).
[09:53:36.723] <TB2> INFO: Test took 3880ms.
[09:53:37.011] <TB2> INFO: Expecting 41600 events.
[09:53:40.649] <TB2> INFO: 41600 events read in total (3046ms).
[09:53:40.650] <TB2> INFO: Test took 3903ms.
[09:53:40.942] <TB2> INFO: Expecting 41600 events.
[09:53:44.429] <TB2> INFO: 41600 events read in total (2896ms).
[09:53:44.429] <TB2> INFO: Test took 3752ms.
[09:53:44.718] <TB2> INFO: Expecting 41600 events.
[09:53:48.242] <TB2> INFO: 41600 events read in total (2933ms).
[09:53:48.243] <TB2> INFO: Test took 3790ms.
[09:53:48.535] <TB2> INFO: Expecting 41600 events.
[09:53:52.068] <TB2> INFO: 41600 events read in total (2942ms).
[09:53:52.068] <TB2> INFO: Test took 3798ms.
[09:53:52.356] <TB2> INFO: Expecting 41600 events.
[09:53:56.055] <TB2> INFO: 41600 events read in total (3107ms).
[09:53:56.056] <TB2> INFO: Test took 3964ms.
[09:53:56.344] <TB2> INFO: Expecting 41600 events.
[09:54:00.158] <TB2> INFO: 41600 events read in total (3223ms).
[09:54:00.158] <TB2> INFO: Test took 4079ms.
[09:54:00.479] <TB2> INFO: Expecting 41600 events.
[09:54:03.973] <TB2> INFO: 41600 events read in total (2902ms).
[09:54:03.974] <TB2> INFO: Test took 3792ms.
[09:54:04.297] <TB2> INFO: Expecting 41600 events.
[09:54:07.888] <TB2> INFO: 41600 events read in total (3000ms).
[09:54:07.889] <TB2> INFO: Test took 3892ms.
[09:54:08.180] <TB2> INFO: Expecting 41600 events.
[09:54:11.925] <TB2> INFO: 41600 events read in total (3153ms).
[09:54:11.926] <TB2> INFO: Test took 4010ms.
[09:54:12.245] <TB2> INFO: Expecting 41600 events.
[09:54:15.964] <TB2> INFO: 41600 events read in total (3127ms).
[09:54:15.965] <TB2> INFO: Test took 4016ms.
[09:54:16.257] <TB2> INFO: Expecting 41600 events.
[09:54:19.727] <TB2> INFO: 41600 events read in total (2878ms).
[09:54:19.728] <TB2> INFO: Test took 3736ms.
[09:54:20.016] <TB2> INFO: Expecting 41600 events.
[09:54:23.615] <TB2> INFO: 41600 events read in total (3007ms).
[09:54:23.616] <TB2> INFO: Test took 3865ms.
[09:54:23.904] <TB2> INFO: Expecting 41600 events.
[09:54:27.421] <TB2> INFO: 41600 events read in total (2926ms).
[09:54:27.422] <TB2> INFO: Test took 3783ms.
[09:54:27.710] <TB2> INFO: Expecting 41600 events.
[09:54:31.272] <TB2> INFO: 41600 events read in total (2970ms).
[09:54:31.273] <TB2> INFO: Test took 3827ms.
[09:54:31.587] <TB2> INFO: Expecting 41600 events.
[09:54:35.334] <TB2> INFO: 41600 events read in total (3155ms).
[09:54:35.335] <TB2> INFO: Test took 4039ms.
[09:54:35.626] <TB2> INFO: Expecting 41600 events.
[09:54:39.097] <TB2> INFO: 41600 events read in total (2879ms).
[09:54:39.098] <TB2> INFO: Test took 3736ms.
[09:54:39.386] <TB2> INFO: Expecting 41600 events.
[09:54:42.983] <TB2> INFO: 41600 events read in total (3005ms).
[09:54:42.984] <TB2> INFO: Test took 3862ms.
[09:54:43.276] <TB2> INFO: Expecting 41600 events.
[09:54:46.800] <TB2> INFO: 41600 events read in total (2933ms).
[09:54:46.801] <TB2> INFO: Test took 3790ms.
[09:54:47.093] <TB2> INFO: Expecting 41600 events.
[09:54:50.568] <TB2> INFO: 41600 events read in total (2883ms).
[09:54:50.569] <TB2> INFO: Test took 3741ms.
[09:54:50.857] <TB2> INFO: Expecting 41600 events.
[09:54:54.421] <TB2> INFO: 41600 events read in total (2972ms).
[09:54:54.422] <TB2> INFO: Test took 3829ms.
[09:54:54.710] <TB2> INFO: Expecting 41600 events.
[09:54:58.328] <TB2> INFO: 41600 events read in total (3026ms).
[09:54:58.329] <TB2> INFO: Test took 3884ms.
[09:54:58.619] <TB2> INFO: Expecting 41600 events.
[09:55:02.139] <TB2> INFO: 41600 events read in total (2928ms).
[09:55:02.140] <TB2> INFO: Test took 3785ms.
[09:55:02.433] <TB2> INFO: Expecting 2560 events.
[09:55:03.317] <TB2> INFO: 2560 events read in total (293ms).
[09:55:03.317] <TB2> INFO: Test took 1161ms.
[09:55:03.625] <TB2> INFO: Expecting 2560 events.
[09:55:04.511] <TB2> INFO: 2560 events read in total (295ms).
[09:55:04.511] <TB2> INFO: Test took 1194ms.
[09:55:04.819] <TB2> INFO: Expecting 2560 events.
[09:55:05.703] <TB2> INFO: 2560 events read in total (292ms).
[09:55:05.703] <TB2> INFO: Test took 1191ms.
[09:55:06.011] <TB2> INFO: Expecting 2560 events.
[09:55:06.893] <TB2> INFO: 2560 events read in total (290ms).
[09:55:06.893] <TB2> INFO: Test took 1189ms.
[09:55:07.201] <TB2> INFO: Expecting 2560 events.
[09:55:08.079] <TB2> INFO: 2560 events read in total (286ms).
[09:55:08.079] <TB2> INFO: Test took 1185ms.
[09:55:08.388] <TB2> INFO: Expecting 2560 events.
[09:55:09.265] <TB2> INFO: 2560 events read in total (286ms).
[09:55:09.266] <TB2> INFO: Test took 1186ms.
[09:55:09.573] <TB2> INFO: Expecting 2560 events.
[09:55:10.451] <TB2> INFO: 2560 events read in total (286ms).
[09:55:10.452] <TB2> INFO: Test took 1186ms.
[09:55:10.759] <TB2> INFO: Expecting 2560 events.
[09:55:11.640] <TB2> INFO: 2560 events read in total (289ms).
[09:55:11.640] <TB2> INFO: Test took 1188ms.
[09:55:11.948] <TB2> INFO: Expecting 2560 events.
[09:55:12.830] <TB2> INFO: 2560 events read in total (290ms).
[09:55:12.830] <TB2> INFO: Test took 1189ms.
[09:55:13.138] <TB2> INFO: Expecting 2560 events.
[09:55:14.018] <TB2> INFO: 2560 events read in total (288ms).
[09:55:14.018] <TB2> INFO: Test took 1188ms.
[09:55:14.325] <TB2> INFO: Expecting 2560 events.
[09:55:15.208] <TB2> INFO: 2560 events read in total (291ms).
[09:55:15.208] <TB2> INFO: Test took 1190ms.
[09:55:15.516] <TB2> INFO: Expecting 2560 events.
[09:55:16.399] <TB2> INFO: 2560 events read in total (292ms).
[09:55:16.400] <TB2> INFO: Test took 1191ms.
[09:55:16.708] <TB2> INFO: Expecting 2560 events.
[09:55:17.595] <TB2> INFO: 2560 events read in total (296ms).
[09:55:17.596] <TB2> INFO: Test took 1196ms.
[09:55:17.904] <TB2> INFO: Expecting 2560 events.
[09:55:18.785] <TB2> INFO: 2560 events read in total (290ms).
[09:55:18.786] <TB2> INFO: Test took 1190ms.
[09:55:19.094] <TB2> INFO: Expecting 2560 events.
[09:55:19.980] <TB2> INFO: 2560 events read in total (295ms).
[09:55:19.980] <TB2> INFO: Test took 1194ms.
[09:55:20.289] <TB2> INFO: Expecting 2560 events.
[09:55:21.171] <TB2> INFO: 2560 events read in total (291ms).
[09:55:21.171] <TB2> INFO: Test took 1190ms.
[09:55:21.174] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:55:21.480] <TB2> INFO: Expecting 655360 events.
[09:55:36.114] <TB2> INFO: 655360 events read in total (14043ms).
[09:55:36.125] <TB2> INFO: Expecting 655360 events.
[09:55:50.579] <TB2> INFO: 655360 events read in total (14051ms).
[09:55:50.593] <TB2> INFO: Expecting 655360 events.
[09:56:05.228] <TB2> INFO: 655360 events read in total (14232ms).
[09:56:05.246] <TB2> INFO: Expecting 655360 events.
[09:56:19.747] <TB2> INFO: 655360 events read in total (14098ms).
[09:56:19.779] <TB2> INFO: Expecting 655360 events.
[09:56:34.469] <TB2> INFO: 655360 events read in total (14287ms).
[09:56:34.508] <TB2> INFO: Expecting 655360 events.
[09:56:48.961] <TB2> INFO: 655360 events read in total (14050ms).
[09:56:48.992] <TB2> INFO: Expecting 655360 events.
[09:57:03.475] <TB2> INFO: 655360 events read in total (14080ms).
[09:57:03.525] <TB2> INFO: Expecting 655360 events.
[09:57:18.053] <TB2> INFO: 655360 events read in total (14125ms).
[09:57:18.094] <TB2> INFO: Expecting 655360 events.
[09:57:32.631] <TB2> INFO: 655360 events read in total (14134ms).
[09:57:32.677] <TB2> INFO: Expecting 655360 events.
[09:57:47.157] <TB2> INFO: 655360 events read in total (14077ms).
[09:57:47.230] <TB2> INFO: Expecting 655360 events.
[09:58:01.725] <TB2> INFO: 655360 events read in total (14092ms).
[09:58:01.802] <TB2> INFO: Expecting 655360 events.
[09:58:16.297] <TB2> INFO: 655360 events read in total (14092ms).
[09:58:16.354] <TB2> INFO: Expecting 655360 events.
[09:58:31.019] <TB2> INFO: 655360 events read in total (14262ms).
[09:58:31.109] <TB2> INFO: Expecting 655360 events.
[09:58:45.544] <TB2> INFO: 655360 events read in total (14032ms).
[09:58:45.610] <TB2> INFO: Expecting 655360 events.
[09:59:00.272] <TB2> INFO: 655360 events read in total (14259ms).
[09:59:00.342] <TB2> INFO: Expecting 655360 events.
[09:59:14.767] <TB2> INFO: 655360 events read in total (14022ms).
[09:59:14.853] <TB2> INFO: Test took 233679ms.
[09:59:14.949] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:59:15.214] <TB2> INFO: Expecting 655360 events.
[09:59:29.538] <TB2> INFO: 655360 events read in total (13732ms).
[09:59:29.548] <TB2> INFO: Expecting 655360 events.
[09:59:44.085] <TB2> INFO: 655360 events read in total (14134ms).
[09:59:44.099] <TB2> INFO: Expecting 655360 events.
[09:59:58.529] <TB2> INFO: 655360 events read in total (14027ms).
[09:59:58.547] <TB2> INFO: Expecting 655360 events.
[10:00:12.769] <TB2> INFO: 655360 events read in total (13819ms).
[10:00:12.792] <TB2> INFO: Expecting 655360 events.
[10:00:27.257] <TB2> INFO: 655360 events read in total (14062ms).
[10:00:27.284] <TB2> INFO: Expecting 655360 events.
[10:00:41.707] <TB2> INFO: 655360 events read in total (14020ms).
[10:00:41.737] <TB2> INFO: Expecting 655360 events.
[10:00:56.053] <TB2> INFO: 655360 events read in total (13913ms).
[10:00:56.087] <TB2> INFO: Expecting 655360 events.
[10:01:10.226] <TB2> INFO: 655360 events read in total (13736ms).
[10:01:10.285] <TB2> INFO: Expecting 655360 events.
[10:01:24.582] <TB2> INFO: 655360 events read in total (13894ms).
[10:01:24.637] <TB2> INFO: Expecting 655360 events.
[10:01:38.954] <TB2> INFO: 655360 events read in total (13914ms).
[10:01:38.003] <TB2> INFO: Expecting 655360 events.
[10:01:53.373] <TB2> INFO: 655360 events read in total (13967ms).
[10:01:53.423] <TB2> INFO: Expecting 655360 events.
[10:02:07.761] <TB2> INFO: 655360 events read in total (13935ms).
[10:02:07.819] <TB2> INFO: Expecting 655360 events.
[10:02:22.332] <TB2> INFO: 655360 events read in total (14110ms).
[10:02:22.422] <TB2> INFO: Expecting 655360 events.
[10:02:36.526] <TB2> INFO: 655360 events read in total (13701ms).
[10:02:36.589] <TB2> INFO: Expecting 655360 events.
[10:02:50.923] <TB2> INFO: 655360 events read in total (13931ms).
[10:02:50.993] <TB2> INFO: Expecting 655360 events.
[10:03:05.132] <TB2> INFO: 655360 events read in total (13736ms).
[10:03:05.239] <TB2> INFO: Test took 230290ms.
[10:03:05.500] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:03:05.507] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:03:05.514] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[10:03:05.520] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[10:03:05.527] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[10:03:05.534] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[10:03:05.541] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[10:03:05.548] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[10:03:05.556] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[10:03:05.563] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[10:03:05.570] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[10:03:05.577] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[10:03:05.584] <TB2> INFO: safety margin for low PH: adding 11, margin is now 31
[10:03:05.591] <TB2> INFO: safety margin for low PH: adding 12, margin is now 32
[10:03:05.598] <TB2> INFO: safety margin for low PH: adding 13, margin is now 33
[10:03:05.605] <TB2> INFO: safety margin for low PH: adding 14, margin is now 34
[10:03:05.613] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:03:05.620] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[10:03:05.627] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:03:05.633] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:03:05.641] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:03:05.648] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:03:05.654] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[10:03:05.662] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[10:03:05.669] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[10:03:05.676] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[10:03:05.683] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[10:03:05.690] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:03:05.697] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:03:05.704] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[10:03:05.710] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:03:05.717] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:03:05.724] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:03:05.731] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:03:05.738] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[10:03:05.745] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[10:03:05.751] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[10:03:05.758] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[10:03:05.765] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[10:03:05.772] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[10:03:05.779] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[10:03:05.786] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[10:03:05.793] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[10:03:05.800] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[10:03:05.806] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:03:05.813] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:03:05.820] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:03:05.827] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[10:03:05.834] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[10:03:05.841] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[10:03:05.848] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[10:03:05.884] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C0.dat
[10:03:05.884] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C1.dat
[10:03:05.884] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C2.dat
[10:03:05.884] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C3.dat
[10:03:05.884] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C4.dat
[10:03:05.885] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C5.dat
[10:03:05.885] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C6.dat
[10:03:05.885] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C7.dat
[10:03:05.885] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C8.dat
[10:03:05.885] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C9.dat
[10:03:05.885] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C10.dat
[10:03:05.885] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C11.dat
[10:03:05.885] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C12.dat
[10:03:05.885] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C13.dat
[10:03:05.886] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C14.dat
[10:03:05.886] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C15.dat
[10:03:06.123] <TB2> INFO: Expecting 41600 events.
[10:03:09.271] <TB2> INFO: 41600 events read in total (2556ms).
[10:03:09.271] <TB2> INFO: Test took 3383ms.
[10:03:09.779] <TB2> INFO: Expecting 41600 events.
[10:03:12.817] <TB2> INFO: 41600 events read in total (2447ms).
[10:03:12.818] <TB2> INFO: Test took 3335ms.
[10:03:13.260] <TB2> INFO: Expecting 41600 events.
[10:03:16.468] <TB2> INFO: 41600 events read in total (2616ms).
[10:03:16.469] <TB2> INFO: Test took 3440ms.
[10:03:16.689] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:16.777] <TB2> INFO: Expecting 2560 events.
[10:03:17.661] <TB2> INFO: 2560 events read in total (292ms).
[10:03:17.662] <TB2> INFO: Test took 973ms.
[10:03:17.663] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:17.970] <TB2> INFO: Expecting 2560 events.
[10:03:18.852] <TB2> INFO: 2560 events read in total (291ms).
[10:03:18.853] <TB2> INFO: Test took 1190ms.
[10:03:18.855] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:19.161] <TB2> INFO: Expecting 2560 events.
[10:03:20.045] <TB2> INFO: 2560 events read in total (292ms).
[10:03:20.045] <TB2> INFO: Test took 1190ms.
[10:03:20.047] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:20.354] <TB2> INFO: Expecting 2560 events.
[10:03:21.238] <TB2> INFO: 2560 events read in total (293ms).
[10:03:21.239] <TB2> INFO: Test took 1192ms.
[10:03:21.240] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:21.547] <TB2> INFO: Expecting 2560 events.
[10:03:22.434] <TB2> INFO: 2560 events read in total (296ms).
[10:03:22.434] <TB2> INFO: Test took 1194ms.
[10:03:22.436] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:22.742] <TB2> INFO: Expecting 2560 events.
[10:03:23.627] <TB2> INFO: 2560 events read in total (294ms).
[10:03:23.627] <TB2> INFO: Test took 1191ms.
[10:03:23.629] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:23.935] <TB2> INFO: Expecting 2560 events.
[10:03:24.824] <TB2> INFO: 2560 events read in total (297ms).
[10:03:24.824] <TB2> INFO: Test took 1195ms.
[10:03:24.826] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:25.132] <TB2> INFO: Expecting 2560 events.
[10:03:26.020] <TB2> INFO: 2560 events read in total (296ms).
[10:03:26.020] <TB2> INFO: Test took 1194ms.
[10:03:26.022] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:26.329] <TB2> INFO: Expecting 2560 events.
[10:03:27.207] <TB2> INFO: 2560 events read in total (287ms).
[10:03:27.208] <TB2> INFO: Test took 1186ms.
[10:03:27.209] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:27.516] <TB2> INFO: Expecting 2560 events.
[10:03:28.396] <TB2> INFO: 2560 events read in total (288ms).
[10:03:28.396] <TB2> INFO: Test took 1187ms.
[10:03:28.398] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:28.704] <TB2> INFO: Expecting 2560 events.
[10:03:29.584] <TB2> INFO: 2560 events read in total (288ms).
[10:03:29.584] <TB2> INFO: Test took 1186ms.
[10:03:29.586] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:29.892] <TB2> INFO: Expecting 2560 events.
[10:03:30.772] <TB2> INFO: 2560 events read in total (288ms).
[10:03:30.772] <TB2> INFO: Test took 1186ms.
[10:03:30.774] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:31.081] <TB2> INFO: Expecting 2560 events.
[10:03:31.960] <TB2> INFO: 2560 events read in total (288ms).
[10:03:31.961] <TB2> INFO: Test took 1187ms.
[10:03:31.962] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:32.269] <TB2> INFO: Expecting 2560 events.
[10:03:33.149] <TB2> INFO: 2560 events read in total (288ms).
[10:03:33.149] <TB2> INFO: Test took 1187ms.
[10:03:33.151] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:33.457] <TB2> INFO: Expecting 2560 events.
[10:03:34.336] <TB2> INFO: 2560 events read in total (287ms).
[10:03:34.337] <TB2> INFO: Test took 1186ms.
[10:03:34.338] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:34.645] <TB2> INFO: Expecting 2560 events.
[10:03:35.524] <TB2> INFO: 2560 events read in total (287ms).
[10:03:35.524] <TB2> INFO: Test took 1186ms.
[10:03:35.527] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:35.832] <TB2> INFO: Expecting 2560 events.
[10:03:36.712] <TB2> INFO: 2560 events read in total (288ms).
[10:03:36.712] <TB2> INFO: Test took 1185ms.
[10:03:36.714] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:37.020] <TB2> INFO: Expecting 2560 events.
[10:03:37.903] <TB2> INFO: 2560 events read in total (291ms).
[10:03:37.904] <TB2> INFO: Test took 1190ms.
[10:03:37.906] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:38.212] <TB2> INFO: Expecting 2560 events.
[10:03:39.096] <TB2> INFO: 2560 events read in total (292ms).
[10:03:39.097] <TB2> INFO: Test took 1191ms.
[10:03:39.098] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:39.404] <TB2> INFO: Expecting 2560 events.
[10:03:40.283] <TB2> INFO: 2560 events read in total (287ms).
[10:03:40.283] <TB2> INFO: Test took 1185ms.
[10:03:40.285] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:40.592] <TB2> INFO: Expecting 2560 events.
[10:03:41.471] <TB2> INFO: 2560 events read in total (288ms).
[10:03:41.471] <TB2> INFO: Test took 1186ms.
[10:03:41.473] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:41.780] <TB2> INFO: Expecting 2560 events.
[10:03:42.659] <TB2> INFO: 2560 events read in total (288ms).
[10:03:42.660] <TB2> INFO: Test took 1187ms.
[10:03:42.662] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:42.968] <TB2> INFO: Expecting 2560 events.
[10:03:43.851] <TB2> INFO: 2560 events read in total (291ms).
[10:03:43.851] <TB2> INFO: Test took 1190ms.
[10:03:43.853] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:44.160] <TB2> INFO: Expecting 2560 events.
[10:03:45.039] <TB2> INFO: 2560 events read in total (288ms).
[10:03:45.040] <TB2> INFO: Test took 1187ms.
[10:03:45.041] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:45.348] <TB2> INFO: Expecting 2560 events.
[10:03:46.233] <TB2> INFO: 2560 events read in total (293ms).
[10:03:46.233] <TB2> INFO: Test took 1192ms.
[10:03:46.235] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:46.541] <TB2> INFO: Expecting 2560 events.
[10:03:47.425] <TB2> INFO: 2560 events read in total (292ms).
[10:03:47.426] <TB2> INFO: Test took 1191ms.
[10:03:47.427] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:47.734] <TB2> INFO: Expecting 2560 events.
[10:03:48.616] <TB2> INFO: 2560 events read in total (291ms).
[10:03:48.617] <TB2> INFO: Test took 1190ms.
[10:03:48.619] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:48.925] <TB2> INFO: Expecting 2560 events.
[10:03:49.809] <TB2> INFO: 2560 events read in total (292ms).
[10:03:49.809] <TB2> INFO: Test took 1190ms.
[10:03:49.811] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:50.118] <TB2> INFO: Expecting 2560 events.
[10:03:50.002] <TB2> INFO: 2560 events read in total (292ms).
[10:03:50.002] <TB2> INFO: Test took 1191ms.
[10:03:50.004] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:51.311] <TB2> INFO: Expecting 2560 events.
[10:03:52.198] <TB2> INFO: 2560 events read in total (296ms).
[10:03:52.198] <TB2> INFO: Test took 1194ms.
[10:03:52.200] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:52.507] <TB2> INFO: Expecting 2560 events.
[10:03:53.394] <TB2> INFO: 2560 events read in total (296ms).
[10:03:53.394] <TB2> INFO: Test took 1194ms.
[10:03:53.396] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:03:53.703] <TB2> INFO: Expecting 2560 events.
[10:03:54.586] <TB2> INFO: 2560 events read in total (292ms).
[10:03:54.586] <TB2> INFO: Test took 1190ms.
[10:03:55.046] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 641 seconds
[10:03:55.047] <TB2> INFO: PH scale (per ROC): 40 34 52 37 33 52 31 52 53 53 53 40 39 37 43 35
[10:03:55.047] <TB2> INFO: PH offset (per ROC): 101 112 129 87 93 128 107 119 128 117 135 102 106 108 129 90
[10:03:55.052] <TB2> INFO: Decoding statistics:
[10:03:55.052] <TB2> INFO: General information:
[10:03:55.052] <TB2> INFO: 16bit words read: 127860
[10:03:55.052] <TB2> INFO: valid events total: 20480
[10:03:55.052] <TB2> INFO: empty events: 17990
[10:03:55.052] <TB2> INFO: valid events with pixels: 2490
[10:03:55.052] <TB2> INFO: valid pixel hits: 2490
[10:03:55.052] <TB2> INFO: Event errors: 0
[10:03:55.052] <TB2> INFO: start marker: 0
[10:03:55.052] <TB2> INFO: stop marker: 0
[10:03:55.052] <TB2> INFO: overflow: 0
[10:03:55.052] <TB2> INFO: invalid 5bit words: 0
[10:03:55.052] <TB2> INFO: invalid XOR eye diagram: 0
[10:03:55.052] <TB2> INFO: frame (failed synchr.): 0
[10:03:55.052] <TB2> INFO: idle data (no TBM trl): 0
[10:03:55.052] <TB2> INFO: no data (only TBM hdr): 0
[10:03:55.052] <TB2> INFO: TBM errors: 0
[10:03:55.052] <TB2> INFO: flawed TBM headers: 0
[10:03:55.052] <TB2> INFO: flawed TBM trailers: 0
[10:03:55.052] <TB2> INFO: event ID mismatches: 0
[10:03:55.052] <TB2> INFO: ROC errors: 0
[10:03:55.052] <TB2> INFO: missing ROC header(s): 0
[10:03:55.052] <TB2> INFO: misplaced readback start: 0
[10:03:55.052] <TB2> INFO: Pixel decoding errors: 0
[10:03:55.052] <TB2> INFO: pixel data incomplete: 0
[10:03:55.052] <TB2> INFO: pixel address: 0
[10:03:55.052] <TB2> INFO: pulse height fill bit: 0
[10:03:55.052] <TB2> INFO: buffer corruption: 0
[10:03:55.321] <TB2> INFO: ######################################################################
[10:03:55.322] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[10:03:55.322] <TB2> INFO: ######################################################################
[10:03:55.332] <TB2> INFO: scanning low vcal = 10
[10:03:55.563] <TB2> INFO: Expecting 41600 events.
[10:03:59.136] <TB2> INFO: 41600 events read in total (2982ms).
[10:03:59.136] <TB2> INFO: Test took 3804ms.
[10:03:59.138] <TB2> INFO: scanning low vcal = 20
[10:03:59.434] <TB2> INFO: Expecting 41600 events.
[10:04:03.033] <TB2> INFO: 41600 events read in total (3007ms).
[10:04:03.033] <TB2> INFO: Test took 3895ms.
[10:04:03.035] <TB2> INFO: scanning low vcal = 30
[10:04:03.336] <TB2> INFO: Expecting 41600 events.
[10:04:06.975] <TB2> INFO: 41600 events read in total (3047ms).
[10:04:06.975] <TB2> INFO: Test took 3940ms.
[10:04:06.979] <TB2> INFO: scanning low vcal = 40
[10:04:07.256] <TB2> INFO: Expecting 41600 events.
[10:04:11.179] <TB2> INFO: 41600 events read in total (3331ms).
[10:04:11.180] <TB2> INFO: Test took 4201ms.
[10:04:11.183] <TB2> INFO: scanning low vcal = 50
[10:04:11.460] <TB2> INFO: Expecting 41600 events.
[10:04:15.448] <TB2> INFO: 41600 events read in total (3397ms).
[10:04:15.448] <TB2> INFO: Test took 4265ms.
[10:04:15.451] <TB2> INFO: scanning low vcal = 60
[10:04:15.745] <TB2> INFO: Expecting 41600 events.
[10:04:19.738] <TB2> INFO: 41600 events read in total (3401ms).
[10:04:19.739] <TB2> INFO: Test took 4288ms.
[10:04:19.742] <TB2> INFO: scanning low vcal = 70
[10:04:20.018] <TB2> INFO: Expecting 41600 events.
[10:04:24.013] <TB2> INFO: 41600 events read in total (3403ms).
[10:04:24.014] <TB2> INFO: Test took 4272ms.
[10:04:24.017] <TB2> INFO: scanning low vcal = 80
[10:04:24.293] <TB2> INFO: Expecting 41600 events.
[10:04:28.243] <TB2> INFO: 41600 events read in total (3358ms).
[10:04:28.244] <TB2> INFO: Test took 4227ms.
[10:04:28.246] <TB2> INFO: scanning low vcal = 90
[10:04:28.523] <TB2> INFO: Expecting 41600 events.
[10:04:32.521] <TB2> INFO: 41600 events read in total (3407ms).
[10:04:32.522] <TB2> INFO: Test took 4276ms.
[10:04:32.524] <TB2> INFO: scanning low vcal = 100
[10:04:32.817] <TB2> INFO: Expecting 41600 events.
[10:04:36.762] <TB2> INFO: 41600 events read in total (3354ms).
[10:04:36.762] <TB2> INFO: Test took 4238ms.
[10:04:36.765] <TB2> INFO: scanning low vcal = 110
[10:04:37.056] <TB2> INFO: Expecting 41600 events.
[10:04:41.047] <TB2> INFO: 41600 events read in total (3400ms).
[10:04:41.048] <TB2> INFO: Test took 4283ms.
[10:04:41.051] <TB2> INFO: scanning low vcal = 120
[10:04:41.328] <TB2> INFO: Expecting 41600 events.
[10:04:45.279] <TB2> INFO: 41600 events read in total (3360ms).
[10:04:45.280] <TB2> INFO: Test took 4229ms.
[10:04:45.282] <TB2> INFO: scanning low vcal = 130
[10:04:45.559] <TB2> INFO: Expecting 41600 events.
[10:04:49.531] <TB2> INFO: 41600 events read in total (3381ms).
[10:04:49.531] <TB2> INFO: Test took 4249ms.
[10:04:49.535] <TB2> INFO: scanning low vcal = 140
[10:04:49.811] <TB2> INFO: Expecting 41600 events.
[10:04:53.823] <TB2> INFO: 41600 events read in total (3421ms).
[10:04:53.824] <TB2> INFO: Test took 4289ms.
[10:04:53.826] <TB2> INFO: scanning low vcal = 150
[10:04:54.103] <TB2> INFO: Expecting 41600 events.
[10:04:58.081] <TB2> INFO: 41600 events read in total (3386ms).
[10:04:58.081] <TB2> INFO: Test took 4256ms.
[10:04:58.084] <TB2> INFO: scanning low vcal = 160
[10:04:58.370] <TB2> INFO: Expecting 41600 events.
[10:05:02.359] <TB2> INFO: 41600 events read in total (3398ms).
[10:05:02.359] <TB2> INFO: Test took 4275ms.
[10:05:02.362] <TB2> INFO: scanning low vcal = 170
[10:05:02.639] <TB2> INFO: Expecting 41600 events.
[10:05:06.642] <TB2> INFO: 41600 events read in total (3412ms).
[10:05:06.643] <TB2> INFO: Test took 4281ms.
[10:05:06.646] <TB2> INFO: scanning low vcal = 180
[10:05:06.941] <TB2> INFO: Expecting 41600 events.
[10:05:10.949] <TB2> INFO: 41600 events read in total (3417ms).
[10:05:10.950] <TB2> INFO: Test took 4304ms.
[10:05:10.953] <TB2> INFO: scanning low vcal = 190
[10:05:11.230] <TB2> INFO: Expecting 41600 events.
[10:05:15.217] <TB2> INFO: 41600 events read in total (3396ms).
[10:05:15.218] <TB2> INFO: Test took 4265ms.
[10:05:15.221] <TB2> INFO: scanning low vcal = 200
[10:05:15.498] <TB2> INFO: Expecting 41600 events.
[10:05:19.509] <TB2> INFO: 41600 events read in total (3420ms).
[10:05:19.510] <TB2> INFO: Test took 4289ms.
[10:05:19.513] <TB2> INFO: scanning low vcal = 210
[10:05:19.789] <TB2> INFO: Expecting 41600 events.
[10:05:23.767] <TB2> INFO: 41600 events read in total (3386ms).
[10:05:23.768] <TB2> INFO: Test took 4255ms.
[10:05:23.771] <TB2> INFO: scanning low vcal = 220
[10:05:24.048] <TB2> INFO: Expecting 41600 events.
[10:05:28.027] <TB2> INFO: 41600 events read in total (3387ms).
[10:05:28.028] <TB2> INFO: Test took 4257ms.
[10:05:28.031] <TB2> INFO: scanning low vcal = 230
[10:05:28.307] <TB2> INFO: Expecting 41600 events.
[10:05:32.377] <TB2> INFO: 41600 events read in total (3478ms).
[10:05:32.378] <TB2> INFO: Test took 4346ms.
[10:05:32.381] <TB2> INFO: scanning low vcal = 240
[10:05:32.666] <TB2> INFO: Expecting 41600 events.
[10:05:36.626] <TB2> INFO: 41600 events read in total (3368ms).
[10:05:36.627] <TB2> INFO: Test took 4246ms.
[10:05:36.630] <TB2> INFO: scanning low vcal = 250
[10:05:36.906] <TB2> INFO: Expecting 41600 events.
[10:05:40.867] <TB2> INFO: 41600 events read in total (3369ms).
[10:05:40.868] <TB2> INFO: Test took 4238ms.
[10:05:40.871] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[10:05:41.148] <TB2> INFO: Expecting 41600 events.
[10:05:45.113] <TB2> INFO: 41600 events read in total (3374ms).
[10:05:45.114] <TB2> INFO: Test took 4242ms.
[10:05:45.117] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[10:05:45.394] <TB2> INFO: Expecting 41600 events.
[10:05:49.348] <TB2> INFO: 41600 events read in total (3362ms).
[10:05:49.349] <TB2> INFO: Test took 4232ms.
[10:05:49.352] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[10:05:49.629] <TB2> INFO: Expecting 41600 events.
[10:05:53.579] <TB2> INFO: 41600 events read in total (3358ms).
[10:05:53.580] <TB2> INFO: Test took 4228ms.
[10:05:53.582] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[10:05:53.859] <TB2> INFO: Expecting 41600 events.
[10:05:57.853] <TB2> INFO: 41600 events read in total (3402ms).
[10:05:57.854] <TB2> INFO: Test took 4272ms.
[10:05:57.856] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[10:05:58.133] <TB2> INFO: Expecting 41600 events.
[10:06:02.084] <TB2> INFO: 41600 events read in total (3359ms).
[10:06:02.085] <TB2> INFO: Test took 4229ms.
[10:06:02.495] <TB2> INFO: PixTestGainPedestal::measure() done
[10:06:36.930] <TB2> INFO: PixTestGainPedestal::fit() done
[10:06:36.930] <TB2> INFO: non-linearity mean: 0.954 0.942 0.979 0.938 0.969 0.980 1.009 0.981 0.984 0.984 0.984 0.939 0.946 0.942 0.977 0.953
[10:06:36.930] <TB2> INFO: non-linearity RMS: 0.054 0.069 0.003 0.190 0.179 0.003 0.179 0.004 0.003 0.003 0.003 0.067 0.114 0.055 0.007 0.156
[10:06:36.930] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C0.dat
[10:06:36.944] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C1.dat
[10:06:36.957] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C2.dat
[10:06:36.971] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C3.dat
[10:06:36.984] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C4.dat
[10:06:36.998] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C5.dat
[10:06:37.011] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C6.dat
[10:06:37.025] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C7.dat
[10:06:37.039] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C8.dat
[10:06:37.052] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C9.dat
[10:06:37.065] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C10.dat
[10:06:37.079] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C11.dat
[10:06:37.092] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C12.dat
[10:06:37.106] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C13.dat
[10:06:37.119] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C14.dat
[10:06:37.133] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1058_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C15.dat
[10:06:37.146] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 161 seconds
[10:06:37.146] <TB2> INFO: Decoding statistics:
[10:06:37.146] <TB2> INFO: General information:
[10:06:37.146] <TB2> INFO: 16bit words read: 3302736
[10:06:37.146] <TB2> INFO: valid events total: 332800
[10:06:37.146] <TB2> INFO: empty events: 348
[10:06:37.146] <TB2> INFO: valid events with pixels: 332452
[10:06:37.146] <TB2> INFO: valid pixel hits: 652968
[10:06:37.146] <TB2> INFO: Event errors: 0
[10:06:37.146] <TB2> INFO: start marker: 0
[10:06:37.146] <TB2> INFO: stop marker: 0
[10:06:37.146] <TB2> INFO: overflow: 0
[10:06:37.146] <TB2> INFO: invalid 5bit words: 0
[10:06:37.146] <TB2> INFO: invalid XOR eye diagram: 0
[10:06:37.146] <TB2> INFO: frame (failed synchr.): 0
[10:06:37.146] <TB2> INFO: idle data (no TBM trl): 0
[10:06:37.146] <TB2> INFO: no data (only TBM hdr): 0
[10:06:37.146] <TB2> INFO: TBM errors: 0
[10:06:37.146] <TB2> INFO: flawed TBM headers: 0
[10:06:37.146] <TB2> INFO: flawed TBM trailers: 0
[10:06:37.146] <TB2> INFO: event ID mismatches: 0
[10:06:37.146] <TB2> INFO: ROC errors: 0
[10:06:37.146] <TB2> INFO: missing ROC header(s): 0
[10:06:37.146] <TB2> INFO: misplaced readback start: 0
[10:06:37.146] <TB2> INFO: Pixel decoding errors: 0
[10:06:37.146] <TB2> INFO: pixel data incomplete: 0
[10:06:37.146] <TB2> INFO: pixel address: 0
[10:06:37.146] <TB2> INFO: pulse height fill bit: 0
[10:06:37.146] <TB2> INFO: buffer corruption: 0
[10:06:37.162] <TB2> INFO: Decoding statistics:
[10:06:37.162] <TB2> INFO: General information:
[10:06:37.162] <TB2> INFO: 16bit words read: 3432132
[10:06:37.162] <TB2> INFO: valid events total: 353536
[10:06:37.162] <TB2> INFO: empty events: 18594
[10:06:37.162] <TB2> INFO: valid events with pixels: 334942
[10:06:37.162] <TB2> INFO: valid pixel hits: 655458
[10:06:37.162] <TB2> INFO: Event errors: 0
[10:06:37.162] <TB2> INFO: start marker: 0
[10:06:37.162] <TB2> INFO: stop marker: 0
[10:06:37.162] <TB2> INFO: overflow: 0
[10:06:37.162] <TB2> INFO: invalid 5bit words: 0
[10:06:37.162] <TB2> INFO: invalid XOR eye diagram: 0
[10:06:37.162] <TB2> INFO: frame (failed synchr.): 0
[10:06:37.162] <TB2> INFO: idle data (no TBM trl): 0
[10:06:37.162] <TB2> INFO: no data (only TBM hdr): 0
[10:06:37.162] <TB2> INFO: TBM errors: 0
[10:06:37.162] <TB2> INFO: flawed TBM headers: 0
[10:06:37.162] <TB2> INFO: flawed TBM trailers: 0
[10:06:37.162] <TB2> INFO: event ID mismatches: 0
[10:06:37.162] <TB2> INFO: ROC errors: 0
[10:06:37.162] <TB2> INFO: missing ROC header(s): 0
[10:06:37.162] <TB2> INFO: misplaced readback start: 0
[10:06:37.162] <TB2> INFO: Pixel decoding errors: 0
[10:06:37.162] <TB2> INFO: pixel data incomplete: 0
[10:06:37.162] <TB2> INFO: pixel address: 0
[10:06:37.162] <TB2> INFO: pulse height fill bit: 0
[10:06:37.162] <TB2> INFO: buffer corruption: 0
[10:06:37.162] <TB2> INFO: enter test to run
[10:06:37.162] <TB2> INFO: test: exit no parameter change
[10:06:37.202] <TB2> QUIET: Connection to board 156 closed.
[10:06:37.203] <TB2> INFO: pXar: this is the end, my friend