[14:03:53.836] <TB2> INFO: *** Welcome to pxar ***
[14:03:53.836] <TB2> INFO: *** Today: 2016/10/24
[14:03:53.842] <TB2> INFO: *** Version: c8ba-dirty
[14:03:53.842] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C15.dat
[14:03:53.842] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//tbmParameters_C1b.dat
[14:03:53.842] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//defaultMaskFile.dat
[14:03:53.842] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters_C15.dat
[14:03:53.907] <TB2> INFO: clk: 4
[14:03:53.907] <TB2> INFO: ctr: 4
[14:03:53.907] <TB2> INFO: sda: 19
[14:03:53.907] <TB2> INFO: tin: 9
[14:03:53.907] <TB2> INFO: level: 15
[14:03:53.907] <TB2> INFO: triggerdelay: 0
[14:03:53.907] <TB2> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[14:03:53.907] <TB2> INFO: Log level: INFO
[14:03:53.916] <TB2> INFO: Found DTB DTB_WWXUD2
[14:03:53.923] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[14:03:53.925] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[14:03:53.927] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[14:03:55.449] <TB2> INFO: DUT info:
[14:03:55.450] <TB2> INFO: The DUT currently contains the following objects:
[14:03:55.450] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[14:03:55.450] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:03:55.450] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:03:55.450] <TB2> INFO: TBM Core alpha (2): 7 registers set
[14:03:55.450] <TB2> INFO: TBM Core beta (3): 7 registers set
[14:03:55.450] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[14:03:55.450] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:55.450] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:55.450] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:55.450] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:55.450] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:55.450] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:55.450] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:55.450] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:55.450] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:55.450] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:55.450] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:55.450] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:55.450] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:55.450] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:55.450] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:55.450] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:55.851] <TB2> INFO: enter 'restricted' command line mode
[14:03:55.851] <TB2> INFO: enter test to run
[14:03:55.851] <TB2> INFO: test: pretest no parameter change
[14:03:55.851] <TB2> INFO: running: pretest
[14:03:55.858] <TB2> INFO: ######################################################################
[14:03:55.858] <TB2> INFO: PixTestPretest::doTest()
[14:03:55.858] <TB2> INFO: ######################################################################
[14:03:55.859] <TB2> INFO: ----------------------------------------------------------------------
[14:03:55.859] <TB2> INFO: PixTestPretest::programROC()
[14:03:55.859] <TB2> INFO: ----------------------------------------------------------------------
[14:04:13.875] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[14:04:13.875] <TB2> INFO: IA differences per ROC: 20.1 20.9 17.7 18.5 18.5 17.7 18.5 18.5 20.1 20.1 20.1 16.1 17.7 18.5 17.7 17.7
[14:04:13.936] <TB2> INFO: ----------------------------------------------------------------------
[14:04:13.936] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[14:04:13.936] <TB2> INFO: ----------------------------------------------------------------------
[14:04:35.240] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 383.5 mA = 23.9688 mA/ROC
[14:04:35.240] <TB2> INFO: i(loss) [mA/ROC]: 18.5 19.3 19.3 19.3 18.5 18.5 18.5 18.5 18.5 18.5 18.5 18.5 19.3 18.5 18.5 18.5
[14:04:35.274] <TB2> INFO: ----------------------------------------------------------------------
[14:04:35.275] <TB2> INFO: PixTestPretest::findTiming()
[14:04:35.275] <TB2> INFO: ----------------------------------------------------------------------
[14:04:35.275] <TB2> INFO: PixTestCmd::init()

[14:05:07.216] <TB2> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[14:05:07.216] <TB2> INFO: (success/tries = 100/100), width = 4
[14:05:08.714] <TB2> INFO: ----------------------------------------------------------------------
[14:05:08.714] <TB2> INFO: PixTestPretest::findWorkingPixel()
[14:05:08.714] <TB2> INFO: ----------------------------------------------------------------------
[14:05:08.808] <TB2> INFO: Expecting 231680 events.
[14:05:18.598] <TB2> INFO: 231680 events read in total (9198ms).
[14:05:18.607] <TB2> INFO: Test took 9889ms.
[14:05:18.847] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[14:05:18.881] <TB2> INFO: ----------------------------------------------------------------------
[14:05:18.881] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[14:05:18.881] <TB2> INFO: ----------------------------------------------------------------------
[14:05:18.975] <TB2> INFO: Expecting 231680 events.
[14:05:28.907] <TB2> INFO: 231680 events read in total (9340ms).
[14:05:28.917] <TB2> INFO: Test took 10031ms.
[14:05:29.184] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[14:05:29.184] <TB2> INFO: CalDel: 86 86 87 105 87 81 97 112 90 95 80 97 92 88 103 104
[14:05:29.184] <TB2> INFO: VthrComp: 51 53 56 51 52 51 51 51 52 51 52 51 51 51 52 51
[14:05:29.188] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C0.dat
[14:05:29.188] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C1.dat
[14:05:29.188] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C2.dat
[14:05:29.189] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C3.dat
[14:05:29.189] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C4.dat
[14:05:29.189] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C5.dat
[14:05:29.189] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C6.dat
[14:05:29.189] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C7.dat
[14:05:29.190] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C8.dat
[14:05:29.190] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C9.dat
[14:05:29.190] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C10.dat
[14:05:29.190] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C11.dat
[14:05:29.191] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C12.dat
[14:05:29.191] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C13.dat
[14:05:29.192] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C14.dat
[14:05:29.192] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C15.dat
[14:05:29.192] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//tbmParameters_C0a.dat
[14:05:29.192] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//tbmParameters_C0b.dat
[14:05:29.192] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//tbmParameters_C1a.dat
[14:05:29.192] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//tbmParameters_C1b.dat
[14:05:29.192] <TB2> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[14:05:29.246] <TB2> INFO: enter test to run
[14:05:29.246] <TB2> INFO: test: FullTest no parameter change
[14:05:29.246] <TB2> INFO: running: fulltest
[14:05:29.246] <TB2> INFO: ######################################################################
[14:05:29.246] <TB2> INFO: PixTestFullTest::doTest()
[14:05:29.246] <TB2> INFO: ######################################################################
[14:05:29.247] <TB2> INFO: ######################################################################
[14:05:29.247] <TB2> INFO: PixTestAlive::doTest()
[14:05:29.247] <TB2> INFO: ######################################################################
[14:05:29.249] <TB2> INFO: ----------------------------------------------------------------------
[14:05:29.249] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:05:29.249] <TB2> INFO: ----------------------------------------------------------------------
[14:05:29.496] <TB2> INFO: Expecting 41600 events.
[14:05:33.150] <TB2> INFO: 41600 events read in total (3062ms).
[14:05:33.151] <TB2> INFO: Test took 3901ms.
[14:05:33.384] <TB2> INFO: PixTestAlive::aliveTest() done
[14:05:33.384] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:05:33.386] <TB2> INFO: ----------------------------------------------------------------------
[14:05:33.386] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:05:33.386] <TB2> INFO: ----------------------------------------------------------------------
[14:05:33.632] <TB2> INFO: Expecting 41600 events.
[14:05:36.648] <TB2> INFO: 41600 events read in total (2424ms).
[14:05:36.649] <TB2> INFO: Test took 3261ms.
[14:05:36.649] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[14:05:36.883] <TB2> INFO: PixTestAlive::maskTest() done
[14:05:36.883] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:05:36.885] <TB2> INFO: ----------------------------------------------------------------------
[14:05:36.885] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:05:36.885] <TB2> INFO: ----------------------------------------------------------------------
[14:05:37.124] <TB2> INFO: Expecting 41600 events.
[14:05:40.635] <TB2> INFO: 41600 events read in total (2919ms).
[14:05:40.635] <TB2> INFO: Test took 3749ms.
[14:05:40.869] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[14:05:40.869] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:05:40.870] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[14:05:40.870] <TB2> INFO: Decoding statistics:
[14:05:40.870] <TB2> INFO: General information:
[14:05:40.870] <TB2> INFO: 16bit words read: 0
[14:05:40.870] <TB2> INFO: valid events total: 0
[14:05:40.870] <TB2> INFO: empty events: 0
[14:05:40.870] <TB2> INFO: valid events with pixels: 0
[14:05:40.870] <TB2> INFO: valid pixel hits: 0
[14:05:40.870] <TB2> INFO: Event errors: 0
[14:05:40.870] <TB2> INFO: start marker: 0
[14:05:40.870] <TB2> INFO: stop marker: 0
[14:05:40.870] <TB2> INFO: overflow: 0
[14:05:40.870] <TB2> INFO: invalid 5bit words: 0
[14:05:40.870] <TB2> INFO: invalid XOR eye diagram: 0
[14:05:40.870] <TB2> INFO: frame (failed synchr.): 0
[14:05:40.870] <TB2> INFO: idle data (no TBM trl): 0
[14:05:40.870] <TB2> INFO: no data (only TBM hdr): 0
[14:05:40.870] <TB2> INFO: TBM errors: 0
[14:05:40.870] <TB2> INFO: flawed TBM headers: 0
[14:05:40.870] <TB2> INFO: flawed TBM trailers: 0
[14:05:40.870] <TB2> INFO: event ID mismatches: 0
[14:05:40.870] <TB2> INFO: ROC errors: 0
[14:05:40.870] <TB2> INFO: missing ROC header(s): 0
[14:05:40.870] <TB2> INFO: misplaced readback start: 0
[14:05:40.870] <TB2> INFO: Pixel decoding errors: 0
[14:05:40.870] <TB2> INFO: pixel data incomplete: 0
[14:05:40.870] <TB2> INFO: pixel address: 0
[14:05:40.870] <TB2> INFO: pulse height fill bit: 0
[14:05:40.870] <TB2> INFO: buffer corruption: 0
[14:05:40.878] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C15.dat
[14:05:40.879] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr_C15.dat

[14:05:40.879] <TB2> INFO: ######################################################################
[14:05:40.879] <TB2> INFO: PixTestReadback::doTest()
[14:05:40.879] <TB2> INFO: ######################################################################
[14:05:40.879] <TB2> INFO: ----------------------------------------------------------------------
[14:05:40.879] <TB2> INFO: PixTestReadback::CalibrateVd()
[14:05:40.879] <TB2> INFO: ----------------------------------------------------------------------
[14:05:50.851] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C0.dat
[14:05:50.851] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C1.dat
[14:05:50.852] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C2.dat
[14:05:50.852] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C3.dat
[14:05:50.852] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C4.dat
[14:05:50.852] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C5.dat
[14:05:50.852] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C6.dat
[14:05:50.852] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C7.dat
[14:05:50.852] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C8.dat
[14:05:50.852] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C9.dat
[14:05:50.852] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C10.dat
[14:05:50.852] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C11.dat
[14:05:50.852] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C12.dat
[14:05:50.852] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C13.dat
[14:05:50.853] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C14.dat
[14:05:50.853] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C15.dat
[14:05:50.883] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:05:50.883] <TB2> INFO: ----------------------------------------------------------------------
[14:05:50.883] <TB2> INFO: PixTestReadback::CalibrateVa()
[14:05:50.883] <TB2> INFO: ----------------------------------------------------------------------
[14:06:00.817] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C0.dat
[14:06:00.817] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C1.dat
[14:06:00.817] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C2.dat
[14:06:00.817] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C3.dat
[14:06:00.817] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C4.dat
[14:06:00.817] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C5.dat
[14:06:00.818] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C6.dat
[14:06:00.818] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C7.dat
[14:06:00.818] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C8.dat
[14:06:00.818] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C9.dat
[14:06:00.818] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C10.dat
[14:06:00.818] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C11.dat
[14:06:00.818] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C12.dat
[14:06:00.818] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C13.dat
[14:06:00.818] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C14.dat
[14:06:00.818] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C15.dat
[14:06:00.850] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:06:00.850] <TB2> INFO: ----------------------------------------------------------------------
[14:06:00.850] <TB2> INFO: PixTestReadback::readbackVbg()
[14:06:00.850] <TB2> INFO: ----------------------------------------------------------------------
[14:06:08.523] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:06:08.523] <TB2> INFO: ----------------------------------------------------------------------
[14:06:08.523] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[14:06:08.523] <TB2> INFO: ----------------------------------------------------------------------
[14:06:08.523] <TB2> INFO: Vbg will be calibrated using Vd calibration
[14:06:08.523] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 158.3calibrated Vbg = 1.19858 :::*/*/*/*/
[14:06:08.523] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 150.9calibrated Vbg = 1.19292 :::*/*/*/*/
[14:06:08.523] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 156.9calibrated Vbg = 1.19236 :::*/*/*/*/
[14:06:08.523] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 158.7calibrated Vbg = 1.19438 :::*/*/*/*/
[14:06:08.523] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 150.1calibrated Vbg = 1.18691 :::*/*/*/*/
[14:06:08.523] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 155.6calibrated Vbg = 1.19941 :::*/*/*/*/
[14:06:08.523] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 159.9calibrated Vbg = 1.20344 :::*/*/*/*/
[14:06:08.523] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 151.2calibrated Vbg = 1.19776 :::*/*/*/*/
[14:06:08.523] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 154.6calibrated Vbg = 1.19965 :::*/*/*/*/
[14:06:08.523] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 155.1calibrated Vbg = 1.19456 :::*/*/*/*/
[14:06:08.523] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 158.9calibrated Vbg = 1.18681 :::*/*/*/*/
[14:06:08.523] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 159calibrated Vbg = 1.18488 :::*/*/*/*/
[14:06:08.523] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 155.1calibrated Vbg = 1.19103 :::*/*/*/*/
[14:06:08.523] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 153.5calibrated Vbg = 1.19911 :::*/*/*/*/
[14:06:08.523] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 158calibrated Vbg = 1.19823 :::*/*/*/*/
[14:06:08.523] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 155calibrated Vbg = 1.1993 :::*/*/*/*/
[14:06:08.526] <TB2> INFO: ----------------------------------------------------------------------
[14:06:08.526] <TB2> INFO: PixTestReadback::CalibrateIa()
[14:06:08.526] <TB2> INFO: ----------------------------------------------------------------------
[14:08:49.380] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C0.dat
[14:08:49.381] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C1.dat
[14:08:49.381] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C2.dat
[14:08:49.381] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C3.dat
[14:08:49.381] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C4.dat
[14:08:49.381] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C5.dat
[14:08:49.381] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C6.dat
[14:08:49.381] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C7.dat
[14:08:49.381] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C8.dat
[14:08:49.381] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C9.dat
[14:08:49.381] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C10.dat
[14:08:49.381] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C11.dat
[14:08:49.381] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C12.dat
[14:08:49.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C13.dat
[14:08:49.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C14.dat
[14:08:49.382] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C15.dat
[14:08:49.409] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:08:49.410] <TB2> INFO: PixTestReadback::doTest() done
[14:08:49.410] <TB2> INFO: Decoding statistics:
[14:08:49.410] <TB2> INFO: General information:
[14:08:49.410] <TB2> INFO: 16bit words read: 1536
[14:08:49.410] <TB2> INFO: valid events total: 256
[14:08:49.410] <TB2> INFO: empty events: 256
[14:08:49.410] <TB2> INFO: valid events with pixels: 0
[14:08:49.410] <TB2> INFO: valid pixel hits: 0
[14:08:49.410] <TB2> INFO: Event errors: 0
[14:08:49.410] <TB2> INFO: start marker: 0
[14:08:49.410] <TB2> INFO: stop marker: 0
[14:08:49.410] <TB2> INFO: overflow: 0
[14:08:49.411] <TB2> INFO: invalid 5bit words: 0
[14:08:49.411] <TB2> INFO: invalid XOR eye diagram: 0
[14:08:49.411] <TB2> INFO: frame (failed synchr.): 0
[14:08:49.411] <TB2> INFO: idle data (no TBM trl): 0
[14:08:49.411] <TB2> INFO: no data (only TBM hdr): 0
[14:08:49.411] <TB2> INFO: TBM errors: 0
[14:08:49.411] <TB2> INFO: flawed TBM headers: 0
[14:08:49.411] <TB2> INFO: flawed TBM trailers: 0
[14:08:49.411] <TB2> INFO: event ID mismatches: 0
[14:08:49.411] <TB2> INFO: ROC errors: 0
[14:08:49.411] <TB2> INFO: missing ROC header(s): 0
[14:08:49.411] <TB2> INFO: misplaced readback start: 0
[14:08:49.411] <TB2> INFO: Pixel decoding errors: 0
[14:08:49.411] <TB2> INFO: pixel data incomplete: 0
[14:08:49.411] <TB2> INFO: pixel address: 0
[14:08:49.411] <TB2> INFO: pulse height fill bit: 0
[14:08:49.411] <TB2> INFO: buffer corruption: 0
[14:08:49.457] <TB2> INFO: ######################################################################
[14:08:49.457] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[14:08:49.457] <TB2> INFO: ######################################################################
[14:08:49.459] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[14:08:49.473] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:08:49.473] <TB2> INFO: run 1 of 1
[14:08:49.711] <TB2> INFO: Expecting 3120000 events.
[14:09:20.981] <TB2> INFO: 669805 events read in total (30679ms).











[14:09:51.645] <TB2> INFO: 1336315 events read in total (61343ms).
[14:10:22.452] <TB2> INFO: 2001320 events read in total (92150ms).











[14:10:53.062] <TB2> INFO: 2668560 events read in total (122760ms).











[14:11:14.274] <TB2> INFO: 3120000 events read in total (143972ms).
[14:11:14.352] <TB2> INFO: Test took 144880ms.
[14:11:37.767] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 168 seconds
[14:11:37.767] <TB2> INFO: number of dead bumps (per ROC): 0 0 2 0 0 2 1 1 0 0 4 5 0 8 2 1
[14:11:37.767] <TB2> INFO: separation cut (per ROC): 106 108 107 101 108 102 99 107 110 107 110 112 106 118 105 98
[14:11:37.768] <TB2> INFO: Decoding statistics:
[14:11:37.768] <TB2> INFO: General information:
[14:11:37.768] <TB2> INFO: 16bit words read: 0
[14:11:37.768] <TB2> INFO: valid events total: 0
[14:11:37.768] <TB2> INFO: empty events: 0
[14:11:37.768] <TB2> INFO: valid events with pixels: 0
[14:11:37.768] <TB2> INFO: valid pixel hits: 0
[14:11:37.768] <TB2> INFO: Event errors: 0
[14:11:37.768] <TB2> INFO: start marker: 0
[14:11:37.768] <TB2> INFO: stop marker: 0
[14:11:37.768] <TB2> INFO: overflow: 0
[14:11:37.768] <TB2> INFO: invalid 5bit words: 0
[14:11:37.768] <TB2> INFO: invalid XOR eye diagram: 0
[14:11:37.768] <TB2> INFO: frame (failed synchr.): 0
[14:11:37.768] <TB2> INFO: idle data (no TBM trl): 0
[14:11:37.768] <TB2> INFO: no data (only TBM hdr): 0
[14:11:37.768] <TB2> INFO: TBM errors: 0
[14:11:37.768] <TB2> INFO: flawed TBM headers: 0
[14:11:37.768] <TB2> INFO: flawed TBM trailers: 0
[14:11:37.768] <TB2> INFO: event ID mismatches: 0
[14:11:37.768] <TB2> INFO: ROC errors: 0
[14:11:37.768] <TB2> INFO: missing ROC header(s): 0
[14:11:37.768] <TB2> INFO: misplaced readback start: 0
[14:11:37.768] <TB2> INFO: Pixel decoding errors: 0
[14:11:37.768] <TB2> INFO: pixel data incomplete: 0
[14:11:37.768] <TB2> INFO: pixel address: 0
[14:11:37.768] <TB2> INFO: pulse height fill bit: 0
[14:11:37.768] <TB2> INFO: buffer corruption: 0
[14:11:37.823] <TB2> INFO: ######################################################################
[14:11:37.823] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[14:11:37.823] <TB2> INFO: ######################################################################
[14:11:37.824] <TB2> INFO: ----------------------------------------------------------------------
[14:11:37.824] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[14:11:37.824] <TB2> INFO: ----------------------------------------------------------------------
[14:11:37.824] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[14:11:37.838] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[14:11:37.838] <TB2> INFO: run 1 of 1
[14:11:38.088] <TB2> INFO: Expecting 36608000 events.
[14:12:02.883] <TB2> INFO: 712450 events read in total (24203ms).
[14:12:26.590] <TB2> INFO: 1411450 events read in total (47910ms).
[14:12:50.165] <TB2> INFO: 2107050 events read in total (71485ms).
[14:13:13.773] <TB2> INFO: 2803350 events read in total (95093ms).
[14:13:37.334] <TB2> INFO: 3498400 events read in total (118654ms).
[14:14:01.093] <TB2> INFO: 4195400 events read in total (142413ms).
[14:14:24.638] <TB2> INFO: 4889900 events read in total (165958ms).
[14:14:48.364] <TB2> INFO: 5584700 events read in total (189684ms).
[14:15:11.903] <TB2> INFO: 6275850 events read in total (213223ms).
[14:15:35.511] <TB2> INFO: 6969600 events read in total (236831ms).
[14:15:58.971] <TB2> INFO: 7657450 events read in total (260291ms).
[14:16:22.624] <TB2> INFO: 8346550 events read in total (283944ms).
[14:16:45.986] <TB2> INFO: 9036500 events read in total (307306ms).
[14:17:09.308] <TB2> INFO: 9727150 events read in total (330628ms).
[14:17:32.914] <TB2> INFO: 10417450 events read in total (354234ms).
[14:17:56.424] <TB2> INFO: 11107650 events read in total (377744ms).
[14:18:20.184] <TB2> INFO: 11798300 events read in total (401504ms).
[14:18:43.928] <TB2> INFO: 12485950 events read in total (425248ms).
[14:19:07.436] <TB2> INFO: 13173000 events read in total (448756ms).
[14:19:31.084] <TB2> INFO: 13859550 events read in total (472404ms).
[14:19:54.455] <TB2> INFO: 14546550 events read in total (495775ms).
[14:20:18.186] <TB2> INFO: 15233900 events read in total (519506ms).
[14:20:42.288] <TB2> INFO: 15921550 events read in total (543608ms).
[14:21:05.645] <TB2> INFO: 16609300 events read in total (566965ms).
[14:21:29.253] <TB2> INFO: 17297100 events read in total (590573ms).
[14:21:52.777] <TB2> INFO: 17983050 events read in total (614097ms).
[14:22:16.533] <TB2> INFO: 18667600 events read in total (637853ms).
[14:22:40.055] <TB2> INFO: 19349950 events read in total (661375ms).
[14:23:03.494] <TB2> INFO: 20030200 events read in total (684814ms).
[14:23:26.835] <TB2> INFO: 20713750 events read in total (708155ms).
[14:23:50.454] <TB2> INFO: 21397400 events read in total (731774ms).
[14:24:13.775] <TB2> INFO: 22078200 events read in total (755095ms).
[14:24:37.405] <TB2> INFO: 22760600 events read in total (778725ms).
[14:25:00.944] <TB2> INFO: 23441700 events read in total (802264ms).
[14:25:24.214] <TB2> INFO: 24123150 events read in total (825534ms).
[14:25:47.844] <TB2> INFO: 24804050 events read in total (849164ms).
[14:26:11.063] <TB2> INFO: 25484050 events read in total (872383ms).
[14:26:34.102] <TB2> INFO: 26166400 events read in total (895422ms).
[14:26:57.420] <TB2> INFO: 26846900 events read in total (918740ms).
[14:27:20.829] <TB2> INFO: 27528250 events read in total (942149ms).
[14:27:44.192] <TB2> INFO: 28208900 events read in total (965512ms).
[14:28:07.820] <TB2> INFO: 28887700 events read in total (989140ms).
[14:28:31.255] <TB2> INFO: 29566800 events read in total (1012575ms).
[14:28:54.464] <TB2> INFO: 30244050 events read in total (1035784ms).
[14:29:17.839] <TB2> INFO: 30922700 events read in total (1059159ms).
[14:29:41.182] <TB2> INFO: 31600200 events read in total (1082502ms).
[14:30:04.497] <TB2> INFO: 32278250 events read in total (1105817ms).
[14:30:27.681] <TB2> INFO: 32957600 events read in total (1129001ms).
[14:30:51.224] <TB2> INFO: 33638450 events read in total (1152544ms).
[14:31:14.635] <TB2> INFO: 34318550 events read in total (1175955ms).
[14:31:38.134] <TB2> INFO: 35000000 events read in total (1199454ms).
[14:32:01.502] <TB2> INFO: 35681850 events read in total (1222822ms).
[14:32:25.220] <TB2> INFO: 36377900 events read in total (1246540ms).
[14:32:33.956] <TB2> INFO: 36608000 events read in total (1255276ms).
[14:32:34.034] <TB2> INFO: Test took 1256196ms.
[14:32:34.571] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:32:36.626] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:32:38.877] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:32:40.920] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:32:42.906] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:32:44.611] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:32:46.014] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:32:47.441] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:32:49.592] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:32:51.056] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:32:52.460] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:32:53.861] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:32:55.263] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:32:56.808] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:32:58.279] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:32:59.715] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:33:01.216] <TB2> INFO: PixTestScurves::scurves() done
[14:33:01.217] <TB2> INFO: Vcal mean: 128.21 134.61 132.33 130.46 128.93 118.54 121.86 129.73 126.69 123.51 129.45 132.52 122.03 129.64 137.05 116.76
[14:33:01.217] <TB2> INFO: Vcal RMS: 6.17 5.87 6.37 6.75 6.60 5.72 7.10 5.88 7.40 7.00 6.36 6.65 6.36 6.62 6.43 5.57
[14:33:01.217] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1283 seconds
[14:33:01.217] <TB2> INFO: Decoding statistics:
[14:33:01.217] <TB2> INFO: General information:
[14:33:01.217] <TB2> INFO: 16bit words read: 0
[14:33:01.217] <TB2> INFO: valid events total: 0
[14:33:01.217] <TB2> INFO: empty events: 0
[14:33:01.217] <TB2> INFO: valid events with pixels: 0
[14:33:01.217] <TB2> INFO: valid pixel hits: 0
[14:33:01.217] <TB2> INFO: Event errors: 0
[14:33:01.217] <TB2> INFO: start marker: 0
[14:33:01.217] <TB2> INFO: stop marker: 0
[14:33:01.217] <TB2> INFO: overflow: 0
[14:33:01.217] <TB2> INFO: invalid 5bit words: 0
[14:33:01.217] <TB2> INFO: invalid XOR eye diagram: 0
[14:33:01.217] <TB2> INFO: frame (failed synchr.): 0
[14:33:01.217] <TB2> INFO: idle data (no TBM trl): 0
[14:33:01.217] <TB2> INFO: no data (only TBM hdr): 0
[14:33:01.217] <TB2> INFO: TBM errors: 0
[14:33:01.217] <TB2> INFO: flawed TBM headers: 0
[14:33:01.217] <TB2> INFO: flawed TBM trailers: 0
[14:33:01.217] <TB2> INFO: event ID mismatches: 0
[14:33:01.217] <TB2> INFO: ROC errors: 0
[14:33:01.217] <TB2> INFO: missing ROC header(s): 0
[14:33:01.217] <TB2> INFO: misplaced readback start: 0
[14:33:01.217] <TB2> INFO: Pixel decoding errors: 0
[14:33:01.217] <TB2> INFO: pixel data incomplete: 0
[14:33:01.217] <TB2> INFO: pixel address: 0
[14:33:01.217] <TB2> INFO: pulse height fill bit: 0
[14:33:01.217] <TB2> INFO: buffer corruption: 0
[14:33:01.292] <TB2> INFO: ######################################################################
[14:33:01.292] <TB2> INFO: PixTestTrim::doTest()
[14:33:01.292] <TB2> INFO: ######################################################################
[14:33:01.294] <TB2> INFO: ----------------------------------------------------------------------
[14:33:01.294] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[14:33:01.294] <TB2> INFO: ----------------------------------------------------------------------
[14:33:01.357] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:33:01.357] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:33:01.369] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:33:01.369] <TB2> INFO: run 1 of 1
[14:33:01.607] <TB2> INFO: Expecting 5025280 events.
[14:33:32.771] <TB2> INFO: 836384 events read in total (30564ms).
[14:34:03.498] <TB2> INFO: 1670760 events read in total (61291ms).
[14:34:33.958] <TB2> INFO: 2502080 events read in total (91752ms).
[14:35:04.448] <TB2> INFO: 3329968 events read in total (122241ms).
[14:35:35.085] <TB2> INFO: 4155272 events read in total (152878ms).
[14:36:06.232] <TB2> INFO: 4980008 events read in total (184025ms).
[14:36:08.272] <TB2> INFO: 5025280 events read in total (186065ms).
[14:36:08.331] <TB2> INFO: Test took 186963ms.
[14:36:22.620] <TB2> INFO: ROC 0 VthrComp = 124
[14:36:22.621] <TB2> INFO: ROC 1 VthrComp = 134
[14:36:22.621] <TB2> INFO: ROC 2 VthrComp = 130
[14:36:22.621] <TB2> INFO: ROC 3 VthrComp = 123
[14:36:22.621] <TB2> INFO: ROC 4 VthrComp = 129
[14:36:22.621] <TB2> INFO: ROC 5 VthrComp = 113
[14:36:22.621] <TB2> INFO: ROC 6 VthrComp = 110
[14:36:22.621] <TB2> INFO: ROC 7 VthrComp = 122
[14:36:22.622] <TB2> INFO: ROC 8 VthrComp = 123
[14:36:22.622] <TB2> INFO: ROC 9 VthrComp = 118
[14:36:22.622] <TB2> INFO: ROC 10 VthrComp = 131
[14:36:22.622] <TB2> INFO: ROC 11 VthrComp = 125
[14:36:22.622] <TB2> INFO: ROC 12 VthrComp = 116
[14:36:22.622] <TB2> INFO: ROC 13 VthrComp = 124
[14:36:22.622] <TB2> INFO: ROC 14 VthrComp = 123
[14:36:22.622] <TB2> INFO: ROC 15 VthrComp = 108
[14:36:22.860] <TB2> INFO: Expecting 41600 events.
[14:36:26.356] <TB2> INFO: 41600 events read in total (2904ms).
[14:36:26.357] <TB2> INFO: Test took 3733ms.
[14:36:26.367] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:36:26.367] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:36:26.378] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:36:26.378] <TB2> INFO: run 1 of 1
[14:36:26.656] <TB2> INFO: Expecting 5025280 events.
[14:36:53.333] <TB2> INFO: 595120 events read in total (26086ms).
[14:37:18.896] <TB2> INFO: 1187928 events read in total (51649ms).
[14:37:44.729] <TB2> INFO: 1780512 events read in total (77482ms).
[14:38:10.473] <TB2> INFO: 2372352 events read in total (103226ms).
[14:38:36.440] <TB2> INFO: 2962152 events read in total (129193ms).
[14:39:02.450] <TB2> INFO: 3550048 events read in total (155203ms).
[14:39:28.293] <TB2> INFO: 4136584 events read in total (181046ms).
[14:39:53.866] <TB2> INFO: 4722392 events read in total (206619ms).
[14:40:08.477] <TB2> INFO: 5025280 events read in total (221230ms).
[14:40:08.554] <TB2> INFO: Test took 222176ms.
[14:40:35.466] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 62.7315 for pixel 51/3 mean/min/max = 47.374/31.8991/62.8489
[14:40:35.466] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 65.8181 for pixel 16/1 mean/min/max = 50.2506/34.5674/65.9338
[14:40:35.467] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 66.2927 for pixel 9/8 mean/min/max = 49.0912/31.8421/66.3403
[14:40:35.467] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 65.1366 for pixel 18/26 mean/min/max = 48.8628/32.1638/65.5618
[14:40:35.467] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 61.6053 for pixel 49/14 mean/min/max = 46.92/32.2089/61.6311
[14:40:35.468] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 62.0455 for pixel 5/2 mean/min/max = 47.6692/33.2306/62.1078
[14:40:35.468] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 69.4239 for pixel 0/16 mean/min/max = 51.552/33.5294/69.5746
[14:40:35.468] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 63.4759 for pixel 16/7 mean/min/max = 48.0783/32.549/63.6076
[14:40:35.469] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 62.9739 for pixel 0/17 mean/min/max = 47.2474/31.3286/63.1662
[14:40:35.469] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 61.657 for pixel 18/14 mean/min/max = 46.7385/31.8021/61.675
[14:40:35.470] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 59.7908 for pixel 18/59 mean/min/max = 45.471/30.7339/60.2081
[14:40:35.470] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 65.6038 for pixel 3/74 mean/min/max = 48.6415/31.4273/65.8557
[14:40:35.470] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 61.6198 for pixel 0/78 mean/min/max = 47.0746/32.5006/61.6486
[14:40:35.471] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 63.0293 for pixel 16/77 mean/min/max = 47.4271/31.7764/63.0778
[14:40:35.471] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 66.5913 for pixel 51/1 mean/min/max = 50.0599/32.807/67.3128
[14:40:35.471] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 65.6393 for pixel 1/9 mean/min/max = 50.8366/35.5645/66.1088
[14:40:35.472] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:40:35.561] <TB2> INFO: Expecting 411648 events.
[14:40:45.095] <TB2> INFO: 411648 events read in total (8942ms).
[14:40:45.102] <TB2> INFO: Expecting 411648 events.
[14:40:54.559] <TB2> INFO: 411648 events read in total (9054ms).
[14:40:54.570] <TB2> INFO: Expecting 411648 events.
[14:41:03.979] <TB2> INFO: 411648 events read in total (9006ms).
[14:41:03.992] <TB2> INFO: Expecting 411648 events.
[14:41:13.340] <TB2> INFO: 411648 events read in total (8945ms).
[14:41:13.356] <TB2> INFO: Expecting 411648 events.
[14:41:22.657] <TB2> INFO: 411648 events read in total (8898ms).
[14:41:22.676] <TB2> INFO: Expecting 411648 events.
[14:41:31.938] <TB2> INFO: 411648 events read in total (8859ms).
[14:41:31.960] <TB2> INFO: Expecting 411648 events.
[14:41:41.286] <TB2> INFO: 411648 events read in total (8923ms).
[14:41:41.309] <TB2> INFO: Expecting 411648 events.
[14:41:50.672] <TB2> INFO: 411648 events read in total (8960ms).
[14:41:50.706] <TB2> INFO: Expecting 411648 events.
[14:42:00.079] <TB2> INFO: 411648 events read in total (8970ms).
[14:42:00.111] <TB2> INFO: Expecting 411648 events.
[14:42:09.414] <TB2> INFO: 411648 events read in total (8900ms).
[14:42:09.445] <TB2> INFO: Expecting 411648 events.
[14:42:18.830] <TB2> INFO: 411648 events read in total (8982ms).
[14:42:18.866] <TB2> INFO: Expecting 411648 events.
[14:42:28.182] <TB2> INFO: 411648 events read in total (8913ms).
[14:42:28.219] <TB2> INFO: Expecting 411648 events.
[14:42:37.553] <TB2> INFO: 411648 events read in total (8931ms).
[14:42:37.594] <TB2> INFO: Expecting 411648 events.
[14:42:46.894] <TB2> INFO: 411648 events read in total (8897ms).
[14:42:46.938] <TB2> INFO: Expecting 411648 events.
[14:42:56.197] <TB2> INFO: 411648 events read in total (8856ms).
[14:42:56.242] <TB2> INFO: Expecting 411648 events.
[14:43:05.434] <TB2> INFO: 411648 events read in total (8789ms).
[14:43:05.486] <TB2> INFO: Test took 150014ms.
[14:43:06.112] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:43:06.125] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:43:06.125] <TB2> INFO: run 1 of 1
[14:43:06.360] <TB2> INFO: Expecting 5025280 events.
[14:43:32.956] <TB2> INFO: 593864 events read in total (26004ms).
[14:43:59.227] <TB2> INFO: 1188672 events read in total (52275ms).
[14:44:25.496] <TB2> INFO: 1782272 events read in total (78544ms).
[14:44:52.218] <TB2> INFO: 2374456 events read in total (105266ms).
[14:45:18.750] <TB2> INFO: 2967928 events read in total (131798ms).
[14:45:45.317] <TB2> INFO: 3564912 events read in total (158365ms).
[14:46:12.389] <TB2> INFO: 4165672 events read in total (185437ms).
[14:46:39.062] <TB2> INFO: 4762536 events read in total (212110ms).
[14:46:51.262] <TB2> INFO: 5025280 events read in total (224310ms).
[14:46:51.395] <TB2> INFO: Test took 225271ms.
[14:47:16.498] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 8.677466 .. 144.449781
[14:47:16.737] <TB2> INFO: Expecting 208000 events.
[14:47:26.150] <TB2> INFO: 208000 events read in total (8822ms).
[14:47:26.152] <TB2> INFO: Test took 9653ms.
[14:47:26.200] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 8 .. 154 (-1/-1) hits flags = 528 (plus default)
[14:47:26.213] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:47:26.213] <TB2> INFO: run 1 of 1
[14:47:26.492] <TB2> INFO: Expecting 4892160 events.
[14:47:53.118] <TB2> INFO: 576264 events read in total (26035ms).
[14:48:18.939] <TB2> INFO: 1152344 events read in total (51858ms).
[14:48:44.856] <TB2> INFO: 1728192 events read in total (77774ms).
[14:49:11.212] <TB2> INFO: 2304736 events read in total (104129ms).
[14:49:36.901] <TB2> INFO: 2880664 events read in total (129818ms).
[14:50:02.994] <TB2> INFO: 3456560 events read in total (155912ms).
[14:50:29.082] <TB2> INFO: 4031784 events read in total (181999ms).
[14:50:55.131] <TB2> INFO: 4607144 events read in total (208048ms).
[14:51:08.659] <TB2> INFO: 4892160 events read in total (221576ms).
[14:51:08.850] <TB2> INFO: Test took 222637ms.
[14:51:37.073] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 26.923927 .. 47.721560
[14:51:37.312] <TB2> INFO: Expecting 208000 events.
[14:51:47.414] <TB2> INFO: 208000 events read in total (9510ms).
[14:51:47.415] <TB2> INFO: Test took 10341ms.
[14:51:47.480] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 57 (-1/-1) hits flags = 528 (plus default)
[14:51:47.493] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:51:47.493] <TB2> INFO: run 1 of 1
[14:51:47.771] <TB2> INFO: Expecting 1397760 events.
[14:52:16.284] <TB2> INFO: 660408 events read in total (27921ms).
[14:52:44.942] <TB2> INFO: 1319048 events read in total (56579ms).
[14:52:48.758] <TB2> INFO: 1397760 events read in total (60395ms).
[14:52:48.790] <TB2> INFO: Test took 61296ms.
[14:53:04.213] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 28.364560 .. 49.260120
[14:53:04.450] <TB2> INFO: Expecting 208000 events.
[14:53:14.385] <TB2> INFO: 208000 events read in total (9343ms).
[14:53:14.386] <TB2> INFO: Test took 10171ms.
[14:53:14.435] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 18 .. 59 (-1/-1) hits flags = 528 (plus default)
[14:53:14.447] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:53:14.447] <TB2> INFO: run 1 of 1
[14:53:14.725] <TB2> INFO: Expecting 1397760 events.
[14:53:43.246] <TB2> INFO: 644424 events read in total (27929ms).
[14:54:11.116] <TB2> INFO: 1287104 events read in total (55799ms).
[14:54:16.245] <TB2> INFO: 1397760 events read in total (60928ms).
[14:54:16.277] <TB2> INFO: Test took 61831ms.
[14:54:30.094] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 27.458371 .. 50.448199
[14:54:30.332] <TB2> INFO: Expecting 208000 events.
[14:54:40.529] <TB2> INFO: 208000 events read in total (9606ms).
[14:54:40.530] <TB2> INFO: Test took 10434ms.
[14:54:40.580] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 17 .. 60 (-1/-1) hits flags = 528 (plus default)
[14:54:40.593] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:54:40.593] <TB2> INFO: run 1 of 1
[14:54:40.870] <TB2> INFO: Expecting 1464320 events.
[14:55:09.065] <TB2> INFO: 642872 events read in total (27603ms).
[14:55:36.961] <TB2> INFO: 1284656 events read in total (55500ms).
[14:55:45.256] <TB2> INFO: 1464320 events read in total (63794ms).
[14:55:45.295] <TB2> INFO: Test took 64703ms.
[14:56:00.732] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:56:00.732] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:56:00.745] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:56:00.745] <TB2> INFO: run 1 of 1
[14:56:00.982] <TB2> INFO: Expecting 1364480 events.
[14:56:29.783] <TB2> INFO: 669544 events read in total (28209ms).
[14:56:58.531] <TB2> INFO: 1338320 events read in total (56958ms).
[14:57:00.116] <TB2> INFO: 1364480 events read in total (58543ms).
[14:57:00.152] <TB2> INFO: Test took 59408ms.
[14:57:13.464] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C0.dat
[14:57:13.464] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C1.dat
[14:57:13.464] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C2.dat
[14:57:13.464] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C3.dat
[14:57:13.464] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C4.dat
[14:57:13.464] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C5.dat
[14:57:13.464] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C6.dat
[14:57:13.465] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C7.dat
[14:57:13.465] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C8.dat
[14:57:13.465] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C9.dat
[14:57:13.465] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C10.dat
[14:57:13.465] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C11.dat
[14:57:13.465] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C12.dat
[14:57:13.465] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C13.dat
[14:57:13.465] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C14.dat
[14:57:13.465] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C15.dat
[14:57:13.465] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C0.dat
[14:57:13.470] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C1.dat
[14:57:13.475] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C2.dat
[14:57:13.480] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C3.dat
[14:57:13.486] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C4.dat
[14:57:13.490] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C5.dat
[14:57:13.495] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C6.dat
[14:57:13.500] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C7.dat
[14:57:13.505] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C8.dat
[14:57:13.509] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C9.dat
[14:57:13.514] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C10.dat
[14:57:13.519] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C11.dat
[14:57:13.523] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C12.dat
[14:57:13.528] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C13.dat
[14:57:13.533] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C14.dat
[14:57:13.538] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C15.dat
[14:57:13.542] <TB2> INFO: PixTestTrim::trimTest() done
[14:57:13.542] <TB2> INFO: vtrim: 126 151 142 133 139 118 129 145 131 128 134 142 115 122 128 146
[14:57:13.542] <TB2> INFO: vthrcomp: 124 134 130 123 129 113 110 122 123 118 131 125 116 124 123 108
[14:57:13.542] <TB2> INFO: vcal mean: 35.11 36.05 35.36 35.37 35.20 35.07 35.19 35.19 35.19 35.30 34.94 35.57 35.00 35.15 35.81 35.67
[14:57:13.542] <TB2> INFO: vcal RMS: 1.25 2.18 1.51 1.50 1.26 1.23 1.31 1.34 1.34 1.39 1.23 1.97 1.06 1.21 2.13 1.90
[14:57:13.542] <TB2> INFO: bits mean: 8.93 9.00 9.28 9.24 9.87 9.21 8.39 9.61 9.05 9.96 10.06 9.23 8.84 9.26 8.95 9.31
[14:57:13.542] <TB2> INFO: bits RMS: 2.97 2.64 2.73 2.61 2.47 2.66 2.69 2.54 2.99 2.57 2.64 2.94 2.87 2.87 2.89 2.27
[14:57:13.549] <TB2> INFO: ----------------------------------------------------------------------
[14:57:13.549] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:57:13.549] <TB2> INFO: ----------------------------------------------------------------------
[14:57:13.552] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:57:13.563] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:57:13.563] <TB2> INFO: run 1 of 1
[14:57:13.800] <TB2> INFO: Expecting 4160000 events.
[14:57:48.149] <TB2> INFO: 793665 events read in total (33757ms).
[14:58:21.694] <TB2> INFO: 1575290 events read in total (67302ms).
[14:58:55.239] <TB2> INFO: 2351835 events read in total (100847ms).
[14:59:28.719] <TB2> INFO: 3123355 events read in total (134327ms).
[15:00:01.722] <TB2> INFO: 3889860 events read in total (167330ms).
[15:00:13.828] <TB2> INFO: 4160000 events read in total (179436ms).
[15:00:13.919] <TB2> INFO: Test took 180355ms.
[15:00:40.782] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 223 (-1/-1) hits flags = 528 (plus default)
[15:00:40.795] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:00:40.795] <TB2> INFO: run 1 of 1
[15:00:41.078] <TB2> INFO: Expecting 4659200 events.
[15:01:13.775] <TB2> INFO: 728750 events read in total (32106ms).
[15:01:45.613] <TB2> INFO: 1450150 events read in total (63944ms).
[15:02:17.774] <TB2> INFO: 2168830 events read in total (96106ms).
[15:02:49.866] <TB2> INFO: 2883610 events read in total (128197ms).
[15:03:21.608] <TB2> INFO: 3597105 events read in total (159939ms).
[15:03:53.839] <TB2> INFO: 4309555 events read in total (192170ms).
[15:04:09.582] <TB2> INFO: 4659200 events read in total (207913ms).
[15:04:09.684] <TB2> INFO: Test took 208889ms.
[15:04:40.586] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[15:04:40.600] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:04:40.600] <TB2> INFO: run 1 of 1
[15:04:40.854] <TB2> INFO: Expecting 4472000 events.
[15:05:13.326] <TB2> INFO: 740095 events read in total (31881ms).
[15:05:45.062] <TB2> INFO: 1472675 events read in total (63616ms).
[15:06:17.149] <TB2> INFO: 2202085 events read in total (95703ms).
[15:06:49.476] <TB2> INFO: 2927035 events read in total (128030ms).
[15:07:21.260] <TB2> INFO: 3651270 events read in total (159814ms).
[15:07:53.656] <TB2> INFO: 4374640 events read in total (192210ms).
[15:07:58.283] <TB2> INFO: 4472000 events read in total (196837ms).
[15:07:58.376] <TB2> INFO: Test took 197776ms.
[15:08:25.834] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 213 (-1/-1) hits flags = 528 (plus default)
[15:08:25.847] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:08:25.847] <TB2> INFO: run 1 of 1
[15:08:26.087] <TB2> INFO: Expecting 4451200 events.
[15:08:58.508] <TB2> INFO: 741790 events read in total (31829ms).
[15:09:30.479] <TB2> INFO: 1476050 events read in total (63800ms).
[15:10:02.806] <TB2> INFO: 2206410 events read in total (96127ms).
[15:10:34.574] <TB2> INFO: 2932605 events read in total (127895ms).
[15:11:05.946] <TB2> INFO: 3658085 events read in total (159267ms).
[15:11:37.484] <TB2> INFO: 4384005 events read in total (190806ms).
[15:11:40.738] <TB2> INFO: 4451200 events read in total (194059ms).
[15:11:40.870] <TB2> INFO: Test took 195023ms.
[15:12:11.848] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[15:12:11.860] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:12:11.860] <TB2> INFO: run 1 of 1
[15:12:12.096] <TB2> INFO: Expecting 4243200 events.
[15:12:46.413] <TB2> INFO: 756420 events read in total (33725ms).
[15:13:18.362] <TB2> INFO: 1504175 events read in total (65674ms).
[15:13:50.640] <TB2> INFO: 2247685 events read in total (97953ms).
[15:14:22.987] <TB2> INFO: 2986340 events read in total (130299ms).
[15:14:54.000] <TB2> INFO: 3724785 events read in total (162312ms).
[15:15:17.713] <TB2> INFO: 4243200 events read in total (185025ms).
[15:15:17.884] <TB2> INFO: Test took 186024ms.
[15:15:45.125] <TB2> INFO: PixTestTrim::trimBitTest() done
[15:15:45.127] <TB2> INFO: PixTestTrim::doTest() done, duration: 2563 seconds
[15:15:45.127] <TB2> INFO: Decoding statistics:
[15:15:45.127] <TB2> INFO: General information:
[15:15:45.127] <TB2> INFO: 16bit words read: 0
[15:15:45.127] <TB2> INFO: valid events total: 0
[15:15:45.127] <TB2> INFO: empty events: 0
[15:15:45.129] <TB2> INFO: valid events with pixels: 0
[15:15:45.129] <TB2> INFO: valid pixel hits: 0
[15:15:45.129] <TB2> INFO: Event errors: 0
[15:15:45.129] <TB2> INFO: start marker: 0
[15:15:45.129] <TB2> INFO: stop marker: 0
[15:15:45.129] <TB2> INFO: overflow: 0
[15:15:45.129] <TB2> INFO: invalid 5bit words: 0
[15:15:45.129] <TB2> INFO: invalid XOR eye diagram: 0
[15:15:45.129] <TB2> INFO: frame (failed synchr.): 0
[15:15:45.129] <TB2> INFO: idle data (no TBM trl): 0
[15:15:45.130] <TB2> INFO: no data (only TBM hdr): 0
[15:15:45.130] <TB2> INFO: TBM errors: 0
[15:15:45.130] <TB2> INFO: flawed TBM headers: 0
[15:15:45.130] <TB2> INFO: flawed TBM trailers: 0
[15:15:45.130] <TB2> INFO: event ID mismatches: 0
[15:15:45.130] <TB2> INFO: ROC errors: 0
[15:15:45.130] <TB2> INFO: missing ROC header(s): 0
[15:15:45.130] <TB2> INFO: misplaced readback start: 0
[15:15:45.130] <TB2> INFO: Pixel decoding errors: 0
[15:15:45.130] <TB2> INFO: pixel data incomplete: 0
[15:15:45.130] <TB2> INFO: pixel address: 0
[15:15:45.130] <TB2> INFO: pulse height fill bit: 0
[15:15:45.130] <TB2> INFO: buffer corruption: 0
[15:15:45.878] <TB2> INFO: ######################################################################
[15:15:45.878] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[15:15:45.878] <TB2> INFO: ######################################################################
[15:15:46.117] <TB2> INFO: Expecting 41600 events.
[15:15:49.680] <TB2> INFO: 41600 events read in total (2972ms).
[15:15:49.681] <TB2> INFO: Test took 3802ms.
[15:15:50.125] <TB2> INFO: Expecting 41600 events.
[15:15:53.651] <TB2> INFO: 41600 events read in total (2934ms).
[15:15:53.652] <TB2> INFO: Test took 3766ms.
[15:15:53.943] <TB2> INFO: Expecting 41600 events.
[15:15:57.427] <TB2> INFO: 41600 events read in total (2892ms).
[15:15:57.428] <TB2> INFO: Test took 3749ms.
[15:15:57.720] <TB2> INFO: Expecting 41600 events.
[15:16:01.262] <TB2> INFO: 41600 events read in total (2951ms).
[15:16:01.263] <TB2> INFO: Test took 3809ms.
[15:16:01.552] <TB2> INFO: Expecting 41600 events.
[15:16:05.039] <TB2> INFO: 41600 events read in total (2895ms).
[15:16:05.040] <TB2> INFO: Test took 3753ms.
[15:16:05.390] <TB2> INFO: Expecting 41600 events.
[15:16:09.095] <TB2> INFO: 41600 events read in total (3114ms).
[15:16:09.096] <TB2> INFO: Test took 4030ms.
[15:16:09.385] <TB2> INFO: Expecting 41600 events.
[15:16:13.092] <TB2> INFO: 41600 events read in total (3116ms).
[15:16:13.093] <TB2> INFO: Test took 3973ms.
[15:16:13.382] <TB2> INFO: Expecting 41600 events.
[15:16:16.905] <TB2> INFO: 41600 events read in total (2931ms).
[15:16:16.906] <TB2> INFO: Test took 3789ms.
[15:16:17.194] <TB2> INFO: Expecting 41600 events.
[15:16:20.761] <TB2> INFO: 41600 events read in total (2975ms).
[15:16:20.763] <TB2> INFO: Test took 3833ms.
[15:16:21.058] <TB2> INFO: Expecting 41600 events.
[15:16:24.613] <TB2> INFO: 41600 events read in total (2963ms).
[15:16:24.615] <TB2> INFO: Test took 3829ms.
[15:16:24.908] <TB2> INFO: Expecting 41600 events.
[15:16:28.463] <TB2> INFO: 41600 events read in total (2963ms).
[15:16:28.464] <TB2> INFO: Test took 3820ms.
[15:16:28.753] <TB2> INFO: Expecting 41600 events.
[15:16:32.394] <TB2> INFO: 41600 events read in total (3049ms).
[15:16:32.396] <TB2> INFO: Test took 3908ms.
[15:16:32.749] <TB2> INFO: Expecting 41600 events.
[15:16:36.251] <TB2> INFO: 41600 events read in total (2910ms).
[15:16:36.253] <TB2> INFO: Test took 3828ms.
[15:16:36.542] <TB2> INFO: Expecting 41600 events.
[15:16:40.115] <TB2> INFO: 41600 events read in total (2982ms).
[15:16:40.116] <TB2> INFO: Test took 3839ms.
[15:16:40.406] <TB2> INFO: Expecting 41600 events.
[15:16:43.900] <TB2> INFO: 41600 events read in total (2902ms).
[15:16:43.901] <TB2> INFO: Test took 3760ms.
[15:16:44.193] <TB2> INFO: Expecting 41600 events.
[15:16:47.784] <TB2> INFO: 41600 events read in total (3000ms).
[15:16:47.786] <TB2> INFO: Test took 3859ms.
[15:16:48.077] <TB2> INFO: Expecting 41600 events.
[15:16:51.584] <TB2> INFO: 41600 events read in total (2916ms).
[15:16:51.585] <TB2> INFO: Test took 3773ms.
[15:16:51.874] <TB2> INFO: Expecting 41600 events.
[15:16:55.411] <TB2> INFO: 41600 events read in total (2945ms).
[15:16:55.412] <TB2> INFO: Test took 3803ms.
[15:16:55.701] <TB2> INFO: Expecting 41600 events.
[15:16:59.224] <TB2> INFO: 41600 events read in total (2931ms).
[15:16:59.225] <TB2> INFO: Test took 3789ms.
[15:16:59.514] <TB2> INFO: Expecting 41600 events.
[15:17:03.152] <TB2> INFO: 41600 events read in total (3046ms).
[15:17:03.153] <TB2> INFO: Test took 3904ms.
[15:17:03.441] <TB2> INFO: Expecting 41600 events.
[15:17:07.100] <TB2> INFO: 41600 events read in total (3067ms).
[15:17:07.101] <TB2> INFO: Test took 3924ms.
[15:17:07.406] <TB2> INFO: Expecting 41600 events.
[15:17:10.917] <TB2> INFO: 41600 events read in total (2919ms).
[15:17:10.918] <TB2> INFO: Test took 3793ms.
[15:17:11.207] <TB2> INFO: Expecting 41600 events.
[15:17:14.727] <TB2> INFO: 41600 events read in total (2928ms).
[15:17:14.727] <TB2> INFO: Test took 3785ms.
[15:17:15.016] <TB2> INFO: Expecting 41600 events.
[15:17:18.661] <TB2> INFO: 41600 events read in total (3053ms).
[15:17:18.662] <TB2> INFO: Test took 3911ms.
[15:17:18.970] <TB2> INFO: Expecting 41600 events.
[15:17:22.518] <TB2> INFO: 41600 events read in total (2957ms).
[15:17:22.518] <TB2> INFO: Test took 3830ms.
[15:17:22.809] <TB2> INFO: Expecting 41600 events.
[15:17:26.344] <TB2> INFO: 41600 events read in total (2943ms).
[15:17:26.345] <TB2> INFO: Test took 3801ms.
[15:17:26.635] <TB2> INFO: Expecting 2560 events.
[15:17:27.525] <TB2> INFO: 2560 events read in total (298ms).
[15:17:27.526] <TB2> INFO: Test took 1167ms.
[15:17:27.833] <TB2> INFO: Expecting 2560 events.
[15:17:28.723] <TB2> INFO: 2560 events read in total (298ms).
[15:17:28.723] <TB2> INFO: Test took 1196ms.
[15:17:29.032] <TB2> INFO: Expecting 2560 events.
[15:17:29.915] <TB2> INFO: 2560 events read in total (292ms).
[15:17:29.916] <TB2> INFO: Test took 1192ms.
[15:17:30.224] <TB2> INFO: Expecting 2560 events.
[15:17:31.118] <TB2> INFO: 2560 events read in total (302ms).
[15:17:31.119] <TB2> INFO: Test took 1203ms.
[15:17:31.425] <TB2> INFO: Expecting 2560 events.
[15:17:32.307] <TB2> INFO: 2560 events read in total (290ms).
[15:17:32.307] <TB2> INFO: Test took 1188ms.
[15:17:32.614] <TB2> INFO: Expecting 2560 events.
[15:17:33.493] <TB2> INFO: 2560 events read in total (288ms).
[15:17:33.494] <TB2> INFO: Test took 1186ms.
[15:17:33.800] <TB2> INFO: Expecting 2560 events.
[15:17:34.686] <TB2> INFO: 2560 events read in total (294ms).
[15:17:34.686] <TB2> INFO: Test took 1192ms.
[15:17:34.994] <TB2> INFO: Expecting 2560 events.
[15:17:35.885] <TB2> INFO: 2560 events read in total (299ms).
[15:17:35.885] <TB2> INFO: Test took 1198ms.
[15:17:36.194] <TB2> INFO: Expecting 2560 events.
[15:17:37.072] <TB2> INFO: 2560 events read in total (287ms).
[15:17:37.072] <TB2> INFO: Test took 1185ms.
[15:17:37.381] <TB2> INFO: Expecting 2560 events.
[15:17:38.265] <TB2> INFO: 2560 events read in total (293ms).
[15:17:38.265] <TB2> INFO: Test took 1192ms.
[15:17:38.573] <TB2> INFO: Expecting 2560 events.
[15:17:39.461] <TB2> INFO: 2560 events read in total (297ms).
[15:17:39.461] <TB2> INFO: Test took 1195ms.
[15:17:39.767] <TB2> INFO: Expecting 2560 events.
[15:17:40.655] <TB2> INFO: 2560 events read in total (296ms).
[15:17:40.655] <TB2> INFO: Test took 1193ms.
[15:17:40.963] <TB2> INFO: Expecting 2560 events.
[15:17:41.859] <TB2> INFO: 2560 events read in total (304ms).
[15:17:41.859] <TB2> INFO: Test took 1203ms.
[15:17:42.167] <TB2> INFO: Expecting 2560 events.
[15:17:43.059] <TB2> INFO: 2560 events read in total (300ms).
[15:17:43.059] <TB2> INFO: Test took 1200ms.
[15:17:43.366] <TB2> INFO: Expecting 2560 events.
[15:17:44.251] <TB2> INFO: 2560 events read in total (293ms).
[15:17:44.251] <TB2> INFO: Test took 1192ms.
[15:17:44.558] <TB2> INFO: Expecting 2560 events.
[15:17:45.446] <TB2> INFO: 2560 events read in total (296ms).
[15:17:45.446] <TB2> INFO: Test took 1194ms.
[15:17:45.450] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:17:45.754] <TB2> INFO: Expecting 655360 events.
[15:18:00.815] <TB2> INFO: 655360 events read in total (14469ms).
[15:18:00.835] <TB2> INFO: Expecting 655360 events.
[15:18:15.365] <TB2> INFO: 655360 events read in total (14127ms).
[15:18:15.384] <TB2> INFO: Expecting 655360 events.
[15:18:30.064] <TB2> INFO: 655360 events read in total (14277ms).
[15:18:30.089] <TB2> INFO: Expecting 655360 events.
[15:18:44.692] <TB2> INFO: 655360 events read in total (14200ms).
[15:18:44.727] <TB2> INFO: Expecting 655360 events.
[15:18:59.526] <TB2> INFO: 655360 events read in total (14396ms).
[15:18:59.558] <TB2> INFO: Expecting 655360 events.
[15:19:14.121] <TB2> INFO: 655360 events read in total (14160ms).
[15:19:14.157] <TB2> INFO: Expecting 655360 events.
[15:19:28.637] <TB2> INFO: 655360 events read in total (14077ms).
[15:19:28.679] <TB2> INFO: Expecting 655360 events.
[15:19:43.245] <TB2> INFO: 655360 events read in total (14163ms).
[15:19:43.302] <TB2> INFO: Expecting 655360 events.
[15:19:58.099] <TB2> INFO: 655360 events read in total (14394ms).
[15:19:58.189] <TB2> INFO: Expecting 655360 events.
[15:20:12.782] <TB2> INFO: 655360 events read in total (14190ms).
[15:20:12.879] <TB2> INFO: Expecting 655360 events.
[15:20:27.346] <TB2> INFO: 655360 events read in total (14064ms).
[15:20:27.468] <TB2> INFO: Expecting 655360 events.
[15:20:42.028] <TB2> INFO: 655360 events read in total (14157ms).
[15:20:42.118] <TB2> INFO: Expecting 655360 events.
[15:20:56.764] <TB2> INFO: 655360 events read in total (14243ms).
[15:20:56.862] <TB2> INFO: Expecting 655360 events.
[15:21:11.516] <TB2> INFO: 655360 events read in total (14251ms).
[15:21:11.665] <TB2> INFO: Expecting 655360 events.
[15:21:26.143] <TB2> INFO: 655360 events read in total (14075ms).
[15:21:26.258] <TB2> INFO: Expecting 655360 events.
[15:21:40.725] <TB2> INFO: 654130 events read in total (14064ms).
[15:21:40.999] <TB2> INFO: 655360 events read in total (14338ms).
[15:21:41.097] <TB2> INFO: Test took 235647ms.
[15:21:41.196] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:21:41.452] <TB2> INFO: Expecting 655360 events.
[15:21:55.810] <TB2> INFO: 655360 events read in total (13766ms).
[15:21:55.832] <TB2> INFO: Expecting 655360 events.
[15:22:10.053] <TB2> INFO: 655360 events read in total (13818ms).
[15:22:10.072] <TB2> INFO: Expecting 655360 events.
[15:22:24.329] <TB2> INFO: 655360 events read in total (13854ms).
[15:22:24.359] <TB2> INFO: Expecting 655360 events.
[15:22:38.492] <TB2> INFO: 655360 events read in total (13729ms).
[15:22:38.520] <TB2> INFO: Expecting 655360 events.
[15:22:52.759] <TB2> INFO: 655360 events read in total (13836ms).
[15:22:52.795] <TB2> INFO: Expecting 655360 events.
[15:23:07.411] <TB2> INFO: 655360 events read in total (14213ms).
[15:23:07.455] <TB2> INFO: Expecting 655360 events.
[15:23:21.967] <TB2> INFO: 655360 events read in total (14109ms).
[15:23:22.009] <TB2> INFO: Expecting 655360 events.
[15:23:36.502] <TB2> INFO: 655360 events read in total (14090ms).
[15:23:36.548] <TB2> INFO: Expecting 655360 events.
[15:23:50.908] <TB2> INFO: 655360 events read in total (13957ms).
[15:23:50.966] <TB2> INFO: Expecting 655360 events.
[15:24:05.404] <TB2> INFO: 655360 events read in total (14035ms).
[15:24:05.472] <TB2> INFO: Expecting 655360 events.
[15:24:20.086] <TB2> INFO: 655360 events read in total (14211ms).
[15:24:20.157] <TB2> INFO: Expecting 655360 events.
[15:24:34.283] <TB2> INFO: 655360 events read in total (13723ms).
[15:24:34.356] <TB2> INFO: Expecting 655360 events.
[15:24:48.866] <TB2> INFO: 655360 events read in total (14106ms).
[15:24:49.009] <TB2> INFO: Expecting 655360 events.
[15:25:03.240] <TB2> INFO: 655360 events read in total (13828ms).
[15:25:03.336] <TB2> INFO: Expecting 655360 events.
[15:25:17.640] <TB2> INFO: 655360 events read in total (13901ms).
[15:25:17.731] <TB2> INFO: Expecting 655360 events.
[15:25:32.262] <TB2> INFO: 655360 events read in total (14128ms).
[15:25:32.384] <TB2> INFO: Test took 231189ms.
[15:25:32.556] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:25:32.562] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:25:32.568] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:25:32.573] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:25:32.579] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:25:32.584] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:25:32.590] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:25:32.596] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:25:32.601] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:25:32.606] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:25:32.612] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:25:32.618] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:25:32.623] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:25:32.628] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:25:32.634] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:25:32.639] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[15:25:32.645] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[15:25:32.650] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:25:32.656] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:25:32.661] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:25:32.667] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:25:32.672] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:25:32.678] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:25:32.683] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:25:32.689] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[15:25:32.694] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[15:25:32.700] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[15:25:32.705] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:25:32.711] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:25:32.717] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:25:32.723] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:25:32.729] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:25:32.734] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[15:25:32.740] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[15:25:32.746] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[15:25:32.751] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:25:32.757] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:25:32.762] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:25:32.768] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:25:32.773] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:25:32.779] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[15:25:32.784] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[15:25:32.790] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[15:25:32.796] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[15:25:32.801] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:25:32.807] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:25:32.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C0.dat
[15:25:32.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C1.dat
[15:25:32.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C2.dat
[15:25:32.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C3.dat
[15:25:32.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C4.dat
[15:25:32.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C5.dat
[15:25:32.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C6.dat
[15:25:32.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C7.dat
[15:25:32.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C8.dat
[15:25:32.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C9.dat
[15:25:32.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C10.dat
[15:25:32.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C11.dat
[15:25:32.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C12.dat
[15:25:32.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C13.dat
[15:25:32.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C14.dat
[15:25:32.842] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C15.dat
[15:25:33.084] <TB2> INFO: Expecting 41600 events.
[15:25:36.265] <TB2> INFO: 41600 events read in total (2589ms).
[15:25:36.266] <TB2> INFO: Test took 3422ms.
[15:25:36.714] <TB2> INFO: Expecting 41600 events.
[15:25:39.742] <TB2> INFO: 41600 events read in total (2436ms).
[15:25:39.743] <TB2> INFO: Test took 3266ms.
[15:25:40.234] <TB2> INFO: Expecting 41600 events.
[15:25:43.411] <TB2> INFO: 41600 events read in total (2585ms).
[15:25:43.412] <TB2> INFO: Test took 3458ms.
[15:25:43.627] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:43.717] <TB2> INFO: Expecting 2560 events.
[15:25:44.610] <TB2> INFO: 2560 events read in total (301ms).
[15:25:44.610] <TB2> INFO: Test took 983ms.
[15:25:44.613] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:44.917] <TB2> INFO: Expecting 2560 events.
[15:25:45.806] <TB2> INFO: 2560 events read in total (297ms).
[15:25:45.807] <TB2> INFO: Test took 1194ms.
[15:25:45.810] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:46.112] <TB2> INFO: Expecting 2560 events.
[15:25:46.002] <TB2> INFO: 2560 events read in total (298ms).
[15:25:46.002] <TB2> INFO: Test took 1192ms.
[15:25:47.005] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:47.308] <TB2> INFO: Expecting 2560 events.
[15:25:48.199] <TB2> INFO: 2560 events read in total (299ms).
[15:25:48.199] <TB2> INFO: Test took 1194ms.
[15:25:48.202] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:48.507] <TB2> INFO: Expecting 2560 events.
[15:25:49.392] <TB2> INFO: 2560 events read in total (294ms).
[15:25:49.393] <TB2> INFO: Test took 1191ms.
[15:25:49.395] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:49.701] <TB2> INFO: Expecting 2560 events.
[15:25:50.591] <TB2> INFO: 2560 events read in total (299ms).
[15:25:50.592] <TB2> INFO: Test took 1197ms.
[15:25:50.595] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:50.898] <TB2> INFO: Expecting 2560 events.
[15:25:51.788] <TB2> INFO: 2560 events read in total (299ms).
[15:25:51.789] <TB2> INFO: Test took 1194ms.
[15:25:51.791] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:52.096] <TB2> INFO: Expecting 2560 events.
[15:25:52.984] <TB2> INFO: 2560 events read in total (296ms).
[15:25:52.984] <TB2> INFO: Test took 1193ms.
[15:25:52.988] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:53.292] <TB2> INFO: Expecting 2560 events.
[15:25:54.184] <TB2> INFO: 2560 events read in total (300ms).
[15:25:54.185] <TB2> INFO: Test took 1197ms.
[15:25:54.188] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:54.492] <TB2> INFO: Expecting 2560 events.
[15:25:55.384] <TB2> INFO: 2560 events read in total (300ms).
[15:25:55.384] <TB2> INFO: Test took 1196ms.
[15:25:55.388] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:55.692] <TB2> INFO: Expecting 2560 events.
[15:25:56.579] <TB2> INFO: 2560 events read in total (295ms).
[15:25:56.580] <TB2> INFO: Test took 1192ms.
[15:25:56.582] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:56.887] <TB2> INFO: Expecting 2560 events.
[15:25:57.776] <TB2> INFO: 2560 events read in total (297ms).
[15:25:57.776] <TB2> INFO: Test took 1194ms.
[15:25:57.778] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:58.083] <TB2> INFO: Expecting 2560 events.
[15:25:58.976] <TB2> INFO: 2560 events read in total (302ms).
[15:25:58.976] <TB2> INFO: Test took 1198ms.
[15:25:58.980] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:59.283] <TB2> INFO: Expecting 2560 events.
[15:26:00.173] <TB2> INFO: 2560 events read in total (298ms).
[15:26:00.173] <TB2> INFO: Test took 1193ms.
[15:26:00.176] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:00.479] <TB2> INFO: Expecting 2560 events.
[15:26:01.361] <TB2> INFO: 2560 events read in total (290ms).
[15:26:01.361] <TB2> INFO: Test took 1185ms.
[15:26:01.364] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:01.669] <TB2> INFO: Expecting 2560 events.
[15:26:02.560] <TB2> INFO: 2560 events read in total (299ms).
[15:26:02.561] <TB2> INFO: Test took 1198ms.
[15:26:02.564] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:02.867] <TB2> INFO: Expecting 2560 events.
[15:26:03.752] <TB2> INFO: 2560 events read in total (293ms).
[15:26:03.753] <TB2> INFO: Test took 1189ms.
[15:26:03.756] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:04.060] <TB2> INFO: Expecting 2560 events.
[15:26:04.949] <TB2> INFO: 2560 events read in total (297ms).
[15:26:04.949] <TB2> INFO: Test took 1193ms.
[15:26:04.952] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:05.258] <TB2> INFO: Expecting 2560 events.
[15:26:06.148] <TB2> INFO: 2560 events read in total (298ms).
[15:26:06.149] <TB2> INFO: Test took 1198ms.
[15:26:06.152] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:06.455] <TB2> INFO: Expecting 2560 events.
[15:26:07.350] <TB2> INFO: 2560 events read in total (303ms).
[15:26:07.351] <TB2> INFO: Test took 1199ms.
[15:26:07.356] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:07.658] <TB2> INFO: Expecting 2560 events.
[15:26:08.553] <TB2> INFO: 2560 events read in total (303ms).
[15:26:08.553] <TB2> INFO: Test took 1197ms.
[15:26:08.556] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:08.860] <TB2> INFO: Expecting 2560 events.
[15:26:09.751] <TB2> INFO: 2560 events read in total (299ms).
[15:26:09.751] <TB2> INFO: Test took 1195ms.
[15:26:09.754] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:10.059] <TB2> INFO: Expecting 2560 events.
[15:26:10.950] <TB2> INFO: 2560 events read in total (299ms).
[15:26:10.951] <TB2> INFO: Test took 1197ms.
[15:26:10.953] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:11.258] <TB2> INFO: Expecting 2560 events.
[15:26:12.149] <TB2> INFO: 2560 events read in total (299ms).
[15:26:12.149] <TB2> INFO: Test took 1196ms.
[15:26:12.153] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:12.456] <TB2> INFO: Expecting 2560 events.
[15:26:13.348] <TB2> INFO: 2560 events read in total (301ms).
[15:26:13.348] <TB2> INFO: Test took 1196ms.
[15:26:13.351] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:13.656] <TB2> INFO: Expecting 2560 events.
[15:26:14.549] <TB2> INFO: 2560 events read in total (301ms).
[15:26:14.550] <TB2> INFO: Test took 1199ms.
[15:26:14.552] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:14.859] <TB2> INFO: Expecting 2560 events.
[15:26:15.746] <TB2> INFO: 2560 events read in total (296ms).
[15:26:15.747] <TB2> INFO: Test took 1196ms.
[15:26:15.749] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:16.054] <TB2> INFO: Expecting 2560 events.
[15:26:16.944] <TB2> INFO: 2560 events read in total (298ms).
[15:26:16.944] <TB2> INFO: Test took 1195ms.
[15:26:16.947] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:17.253] <TB2> INFO: Expecting 2560 events.
[15:26:18.142] <TB2> INFO: 2560 events read in total (297ms).
[15:26:18.143] <TB2> INFO: Test took 1196ms.
[15:26:18.147] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:18.450] <TB2> INFO: Expecting 2560 events.
[15:26:19.339] <TB2> INFO: 2560 events read in total (297ms).
[15:26:19.340] <TB2> INFO: Test took 1194ms.
[15:26:19.343] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:19.647] <TB2> INFO: Expecting 2560 events.
[15:26:20.540] <TB2> INFO: 2560 events read in total (302ms).
[15:26:20.541] <TB2> INFO: Test took 1199ms.
[15:26:20.544] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:26:20.848] <TB2> INFO: Expecting 2560 events.
[15:26:21.738] <TB2> INFO: 2560 events read in total (299ms).
[15:26:21.738] <TB2> INFO: Test took 1194ms.
[15:26:22.213] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 636 seconds
[15:26:22.213] <TB2> INFO: PH scale (per ROC): 38 48 48 35 37 35 28 37 53 51 41 48 34 31 47 35
[15:26:22.213] <TB2> INFO: PH offset (per ROC): 111 129 124 98 104 80 92 105 120 126 99 140 102 111 122 85
[15:26:22.221] <TB2> INFO: Decoding statistics:
[15:26:22.221] <TB2> INFO: General information:
[15:26:22.221] <TB2> INFO: 16bit words read: 127884
[15:26:22.221] <TB2> INFO: valid events total: 20480
[15:26:22.221] <TB2> INFO: empty events: 17978
[15:26:22.221] <TB2> INFO: valid events with pixels: 2502
[15:26:22.221] <TB2> INFO: valid pixel hits: 2502
[15:26:22.221] <TB2> INFO: Event errors: 0
[15:26:22.221] <TB2> INFO: start marker: 0
[15:26:22.221] <TB2> INFO: stop marker: 0
[15:26:22.221] <TB2> INFO: overflow: 0
[15:26:22.222] <TB2> INFO: invalid 5bit words: 0
[15:26:22.222] <TB2> INFO: invalid XOR eye diagram: 0
[15:26:22.222] <TB2> INFO: frame (failed synchr.): 0
[15:26:22.222] <TB2> INFO: idle data (no TBM trl): 0
[15:26:22.222] <TB2> INFO: no data (only TBM hdr): 0
[15:26:22.222] <TB2> INFO: TBM errors: 0
[15:26:22.222] <TB2> INFO: flawed TBM headers: 0
[15:26:22.222] <TB2> INFO: flawed TBM trailers: 0
[15:26:22.222] <TB2> INFO: event ID mismatches: 0
[15:26:22.222] <TB2> INFO: ROC errors: 0
[15:26:22.222] <TB2> INFO: missing ROC header(s): 0
[15:26:22.222] <TB2> INFO: misplaced readback start: 0
[15:26:22.222] <TB2> INFO: Pixel decoding errors: 0
[15:26:22.222] <TB2> INFO: pixel data incomplete: 0
[15:26:22.222] <TB2> INFO: pixel address: 0
[15:26:22.222] <TB2> INFO: pulse height fill bit: 0
[15:26:22.222] <TB2> INFO: buffer corruption: 0
[15:26:22.385] <TB2> INFO: ######################################################################
[15:26:22.385] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[15:26:22.385] <TB2> INFO: ######################################################################
[15:26:22.399] <TB2> INFO: scanning low vcal = 10
[15:26:22.682] <TB2> INFO: Expecting 41600 events.
[15:26:26.307] <TB2> INFO: 41600 events read in total (3033ms).
[15:26:26.307] <TB2> INFO: Test took 3908ms.
[15:26:26.309] <TB2> INFO: scanning low vcal = 20
[15:26:26.602] <TB2> INFO: Expecting 41600 events.
[15:26:30.177] <TB2> INFO: 41600 events read in total (2984ms).
[15:26:30.177] <TB2> INFO: Test took 3868ms.
[15:26:30.179] <TB2> INFO: scanning low vcal = 30
[15:26:30.477] <TB2> INFO: Expecting 41600 events.
[15:26:34.141] <TB2> INFO: 41600 events read in total (3073ms).
[15:26:34.142] <TB2> INFO: Test took 3963ms.
[15:26:34.145] <TB2> INFO: scanning low vcal = 40
[15:26:34.421] <TB2> INFO: Expecting 41600 events.
[15:26:38.425] <TB2> INFO: 41600 events read in total (3412ms).
[15:26:38.426] <TB2> INFO: Test took 4281ms.
[15:26:38.429] <TB2> INFO: scanning low vcal = 50
[15:26:38.707] <TB2> INFO: Expecting 41600 events.
[15:26:42.723] <TB2> INFO: 41600 events read in total (3425ms).
[15:26:42.724] <TB2> INFO: Test took 4295ms.
[15:26:42.728] <TB2> INFO: scanning low vcal = 60
[15:26:43.004] <TB2> INFO: Expecting 41600 events.
[15:26:47.082] <TB2> INFO: 41600 events read in total (3486ms).
[15:26:47.083] <TB2> INFO: Test took 4355ms.
[15:26:47.087] <TB2> INFO: scanning low vcal = 70
[15:26:47.363] <TB2> INFO: Expecting 41600 events.
[15:26:51.362] <TB2> INFO: 41600 events read in total (3407ms).
[15:26:51.363] <TB2> INFO: Test took 4276ms.
[15:26:51.366] <TB2> INFO: scanning low vcal = 80
[15:26:51.643] <TB2> INFO: Expecting 41600 events.
[15:26:55.639] <TB2> INFO: 41600 events read in total (3404ms).
[15:26:55.640] <TB2> INFO: Test took 4274ms.
[15:26:55.643] <TB2> INFO: scanning low vcal = 90
[15:26:55.919] <TB2> INFO: Expecting 41600 events.
[15:26:59.903] <TB2> INFO: 41600 events read in total (3392ms).
[15:26:59.904] <TB2> INFO: Test took 4261ms.
[15:26:59.908] <TB2> INFO: scanning low vcal = 100
[15:27:00.184] <TB2> INFO: Expecting 41600 events.
[15:27:04.197] <TB2> INFO: 41600 events read in total (3421ms).
[15:27:04.198] <TB2> INFO: Test took 4290ms.
[15:27:04.201] <TB2> INFO: scanning low vcal = 110
[15:27:04.478] <TB2> INFO: Expecting 41600 events.
[15:27:08.509] <TB2> INFO: 41600 events read in total (3439ms).
[15:27:08.510] <TB2> INFO: Test took 4309ms.
[15:27:08.513] <TB2> INFO: scanning low vcal = 120
[15:27:08.791] <TB2> INFO: Expecting 41600 events.
[15:27:12.798] <TB2> INFO: 41600 events read in total (3416ms).
[15:27:12.798] <TB2> INFO: Test took 4285ms.
[15:27:12.801] <TB2> INFO: scanning low vcal = 130
[15:27:13.079] <TB2> INFO: Expecting 41600 events.
[15:27:17.072] <TB2> INFO: 41600 events read in total (3401ms).
[15:27:17.073] <TB2> INFO: Test took 4272ms.
[15:27:17.075] <TB2> INFO: scanning low vcal = 140
[15:27:17.353] <TB2> INFO: Expecting 41600 events.
[15:27:21.371] <TB2> INFO: 41600 events read in total (3426ms).
[15:27:21.372] <TB2> INFO: Test took 4296ms.
[15:27:21.375] <TB2> INFO: scanning low vcal = 150
[15:27:21.652] <TB2> INFO: Expecting 41600 events.
[15:27:25.658] <TB2> INFO: 41600 events read in total (3414ms).
[15:27:25.659] <TB2> INFO: Test took 4284ms.
[15:27:25.662] <TB2> INFO: scanning low vcal = 160
[15:27:25.940] <TB2> INFO: Expecting 41600 events.
[15:27:29.945] <TB2> INFO: 41600 events read in total (3413ms).
[15:27:29.946] <TB2> INFO: Test took 4283ms.
[15:27:29.949] <TB2> INFO: scanning low vcal = 170
[15:27:30.226] <TB2> INFO: Expecting 41600 events.
[15:27:34.240] <TB2> INFO: 41600 events read in total (3422ms).
[15:27:34.241] <TB2> INFO: Test took 4292ms.
[15:27:34.245] <TB2> INFO: scanning low vcal = 180
[15:27:34.521] <TB2> INFO: Expecting 41600 events.
[15:27:38.525] <TB2> INFO: 41600 events read in total (3412ms).
[15:27:38.526] <TB2> INFO: Test took 4281ms.
[15:27:38.529] <TB2> INFO: scanning low vcal = 190
[15:27:38.806] <TB2> INFO: Expecting 41600 events.
[15:27:42.807] <TB2> INFO: 41600 events read in total (3410ms).
[15:27:42.808] <TB2> INFO: Test took 4279ms.
[15:27:42.811] <TB2> INFO: scanning low vcal = 200
[15:27:43.088] <TB2> INFO: Expecting 41600 events.
[15:27:47.083] <TB2> INFO: 41600 events read in total (3404ms).
[15:27:47.084] <TB2> INFO: Test took 4273ms.
[15:27:47.088] <TB2> INFO: scanning low vcal = 210
[15:27:47.363] <TB2> INFO: Expecting 41600 events.
[15:27:51.310] <TB2> INFO: 41600 events read in total (3355ms).
[15:27:51.311] <TB2> INFO: Test took 4223ms.
[15:27:51.314] <TB2> INFO: scanning low vcal = 220
[15:27:51.591] <TB2> INFO: Expecting 41600 events.
[15:27:55.570] <TB2> INFO: 41600 events read in total (3388ms).
[15:27:55.571] <TB2> INFO: Test took 4257ms.
[15:27:55.574] <TB2> INFO: scanning low vcal = 230
[15:27:55.850] <TB2> INFO: Expecting 41600 events.
[15:27:59.814] <TB2> INFO: 41600 events read in total (3372ms).
[15:27:59.815] <TB2> INFO: Test took 4241ms.
[15:27:59.818] <TB2> INFO: scanning low vcal = 240
[15:28:00.094] <TB2> INFO: Expecting 41600 events.
[15:28:04.053] <TB2> INFO: 41600 events read in total (3367ms).
[15:28:04.054] <TB2> INFO: Test took 4236ms.
[15:28:04.056] <TB2> INFO: scanning low vcal = 250
[15:28:04.333] <TB2> INFO: Expecting 41600 events.
[15:28:08.313] <TB2> INFO: 41600 events read in total (3388ms).
[15:28:08.314] <TB2> INFO: Test took 4258ms.
[15:28:08.318] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[15:28:08.594] <TB2> INFO: Expecting 41600 events.
[15:28:12.614] <TB2> INFO: 41600 events read in total (3429ms).
[15:28:12.616] <TB2> INFO: Test took 4298ms.
[15:28:12.619] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[15:28:12.895] <TB2> INFO: Expecting 41600 events.
[15:28:16.872] <TB2> INFO: 41600 events read in total (3385ms).
[15:28:16.873] <TB2> INFO: Test took 4254ms.
[15:28:16.877] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[15:28:17.153] <TB2> INFO: Expecting 41600 events.
[15:28:21.142] <TB2> INFO: 41600 events read in total (3397ms).
[15:28:21.143] <TB2> INFO: Test took 4266ms.
[15:28:21.146] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[15:28:21.423] <TB2> INFO: Expecting 41600 events.
[15:28:25.431] <TB2> INFO: 41600 events read in total (3416ms).
[15:28:25.432] <TB2> INFO: Test took 4285ms.
[15:28:25.436] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[15:28:25.712] <TB2> INFO: Expecting 41600 events.
[15:28:29.725] <TB2> INFO: 41600 events read in total (3421ms).
[15:28:29.725] <TB2> INFO: Test took 4289ms.
[15:28:30.144] <TB2> INFO: PixTestGainPedestal::measure() done
[15:29:05.389] <TB2> INFO: PixTestGainPedestal::fit() done
[15:29:05.389] <TB2> INFO: non-linearity mean: 0.920 0.983 0.980 0.943 0.931 0.976 1.065 0.940 0.985 0.982 0.944 0.982 0.947 0.970 0.976 1.015
[15:29:05.389] <TB2> INFO: non-linearity RMS: 0.094 0.004 0.003 0.141 0.103 0.163 0.162 0.134 0.003 0.003 0.051 0.004 0.169 0.161 0.007 0.153
[15:29:05.389] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C0.dat
[15:29:05.402] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C1.dat
[15:29:05.415] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C2.dat
[15:29:05.429] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C3.dat
[15:29:05.442] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C4.dat
[15:29:05.455] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C5.dat
[15:29:05.469] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C6.dat
[15:29:05.483] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C7.dat
[15:29:05.496] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C8.dat
[15:29:05.509] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C9.dat
[15:29:05.522] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C10.dat
[15:29:05.536] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C11.dat
[15:29:05.549] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C12.dat
[15:29:05.562] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C13.dat
[15:29:05.574] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C14.dat
[15:29:05.588] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C15.dat
[15:29:05.601] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 163 seconds
[15:29:05.601] <TB2> INFO: Decoding statistics:
[15:29:05.601] <TB2> INFO: General information:
[15:29:05.601] <TB2> INFO: 16bit words read: 3278566
[15:29:05.601] <TB2> INFO: valid events total: 332800
[15:29:05.601] <TB2> INFO: empty events: 894
[15:29:05.601] <TB2> INFO: valid events with pixels: 331906
[15:29:05.601] <TB2> INFO: valid pixel hits: 640883
[15:29:05.601] <TB2> INFO: Event errors: 0
[15:29:05.601] <TB2> INFO: start marker: 0
[15:29:05.601] <TB2> INFO: stop marker: 0
[15:29:05.601] <TB2> INFO: overflow: 0
[15:29:05.601] <TB2> INFO: invalid 5bit words: 0
[15:29:05.601] <TB2> INFO: invalid XOR eye diagram: 0
[15:29:05.601] <TB2> INFO: frame (failed synchr.): 0
[15:29:05.601] <TB2> INFO: idle data (no TBM trl): 0
[15:29:05.601] <TB2> INFO: no data (only TBM hdr): 0
[15:29:05.601] <TB2> INFO: TBM errors: 0
[15:29:05.601] <TB2> INFO: flawed TBM headers: 0
[15:29:05.601] <TB2> INFO: flawed TBM trailers: 0
[15:29:05.601] <TB2> INFO: event ID mismatches: 0
[15:29:05.601] <TB2> INFO: ROC errors: 0
[15:29:05.601] <TB2> INFO: missing ROC header(s): 0
[15:29:05.601] <TB2> INFO: misplaced readback start: 0
[15:29:05.601] <TB2> INFO: Pixel decoding errors: 0
[15:29:05.601] <TB2> INFO: pixel data incomplete: 0
[15:29:05.601] <TB2> INFO: pixel address: 0
[15:29:05.601] <TB2> INFO: pulse height fill bit: 0
[15:29:05.601] <TB2> INFO: buffer corruption: 0
[15:29:05.620] <TB2> INFO: Decoding statistics:
[15:29:05.620] <TB2> INFO: General information:
[15:29:05.620] <TB2> INFO: 16bit words read: 3407986
[15:29:05.620] <TB2> INFO: valid events total: 353536
[15:29:05.620] <TB2> INFO: empty events: 19128
[15:29:05.620] <TB2> INFO: valid events with pixels: 334408
[15:29:05.620] <TB2> INFO: valid pixel hits: 643385
[15:29:05.620] <TB2> INFO: Event errors: 0
[15:29:05.620] <TB2> INFO: start marker: 0
[15:29:05.620] <TB2> INFO: stop marker: 0
[15:29:05.620] <TB2> INFO: overflow: 0
[15:29:05.620] <TB2> INFO: invalid 5bit words: 0
[15:29:05.620] <TB2> INFO: invalid XOR eye diagram: 0
[15:29:05.620] <TB2> INFO: frame (failed synchr.): 0
[15:29:05.620] <TB2> INFO: idle data (no TBM trl): 0
[15:29:05.620] <TB2> INFO: no data (only TBM hdr): 0
[15:29:05.620] <TB2> INFO: TBM errors: 0
[15:29:05.620] <TB2> INFO: flawed TBM headers: 0
[15:29:05.620] <TB2> INFO: flawed TBM trailers: 0
[15:29:05.620] <TB2> INFO: event ID mismatches: 0
[15:29:05.620] <TB2> INFO: ROC errors: 0
[15:29:05.620] <TB2> INFO: missing ROC header(s): 0
[15:29:05.620] <TB2> INFO: misplaced readback start: 0
[15:29:05.620] <TB2> INFO: Pixel decoding errors: 0
[15:29:05.620] <TB2> INFO: pixel data incomplete: 0
[15:29:05.620] <TB2> INFO: pixel address: 0
[15:29:05.620] <TB2> INFO: pulse height fill bit: 0
[15:29:05.620] <TB2> INFO: buffer corruption: 0
[15:29:05.620] <TB2> INFO: enter test to run
[15:29:05.620] <TB2> INFO: test: exit no parameter change
[15:29:05.767] <TB2> QUIET: Connection to board 149 closed.
[15:29:05.768] <TB2> INFO: pXar: this is the end, my friend