[12:26:02.856] <TB2> INFO: *** Welcome to pxar ***
[12:26:02.856] <TB2> INFO: *** Today: 2016/10/24
[12:26:02.861] <TB2> INFO: *** Version: c8ba-dirty
[12:26:02.861] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C15.dat
[12:26:02.862] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C1b.dat
[12:26:02.862] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//defaultMaskFile.dat
[12:26:02.862] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters_C15.dat
[12:26:02.955] <TB2> INFO: clk: 4
[12:26:02.955] <TB2> INFO: ctr: 4
[12:26:02.955] <TB2> INFO: sda: 19
[12:26:02.955] <TB2> INFO: tin: 9
[12:26:02.955] <TB2> INFO: level: 15
[12:26:02.955] <TB2> INFO: triggerdelay: 0
[12:26:02.955] <TB2> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[12:26:02.955] <TB2> INFO: Log level: INFO
[12:26:02.965] <TB2> INFO: Found DTB DTB_WWXUD2
[12:26:02.972] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[12:26:02.974] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[12:26:02.976] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[12:26:04.466] <TB2> INFO: DUT info:
[12:26:04.466] <TB2> INFO: The DUT currently contains the following objects:
[12:26:04.466] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[12:26:04.466] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:26:04.466] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:26:04.466] <TB2> INFO: TBM Core alpha (2): 7 registers set
[12:26:04.466] <TB2> INFO: TBM Core beta (3): 7 registers set
[12:26:04.466] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[12:26:04.466] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:26:04.466] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:26:04.466] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:26:04.466] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:26:04.466] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:26:04.466] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:26:04.466] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:26:04.466] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:26:04.466] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:26:04.467] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:26:04.467] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:26:04.467] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:26:04.467] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:26:04.467] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:26:04.467] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:26:04.467] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:26:04.868] <TB2> INFO: enter 'restricted' command line mode
[12:26:04.868] <TB2> INFO: enter test to run
[12:26:04.868] <TB2> INFO: test: pretest no parameter change
[12:26:04.868] <TB2> INFO: running: pretest
[12:26:04.876] <TB2> INFO: ######################################################################
[12:26:04.876] <TB2> INFO: PixTestPretest::doTest()
[12:26:04.876] <TB2> INFO: ######################################################################
[12:26:04.877] <TB2> INFO: ----------------------------------------------------------------------
[12:26:04.877] <TB2> INFO: PixTestPretest::programROC()
[12:26:04.877] <TB2> INFO: ----------------------------------------------------------------------
[12:26:22.892] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:26:22.892] <TB2> INFO: IA differences per ROC: 20.9 21.7 17.7 18.5 18.5 17.7 18.5 17.7 19.3 20.1 19.3 16.1 17.7 18.5 16.9 17.7
[12:26:22.962] <TB2> INFO: ----------------------------------------------------------------------
[12:26:22.962] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:26:22.962] <TB2> INFO: ----------------------------------------------------------------------
[12:26:44.266] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 395.5 mA = 24.7188 mA/ROC
[12:26:44.266] <TB2> INFO: i(loss) [mA/ROC]: 20.1 19.3 20.9 20.9 20.9 20.9 20.9 19.3 19.3 19.3 19.3 19.3 20.9 20.9 19.3 19.3
[12:26:44.302] <TB2> INFO: ----------------------------------------------------------------------
[12:26:44.302] <TB2> INFO: PixTestPretest::findTiming()
[12:26:44.302] <TB2> INFO: ----------------------------------------------------------------------
[12:26:44.302] <TB2> INFO: PixTestCmd::init()

[12:27:16.222] <TB2> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[12:27:16.222] <TB2> INFO: (success/tries = 100/100), width = 4
[12:27:17.722] <TB2> INFO: ----------------------------------------------------------------------
[12:27:17.722] <TB2> INFO: PixTestPretest::findWorkingPixel()
[12:27:17.722] <TB2> INFO: ----------------------------------------------------------------------
[12:27:17.817] <TB2> INFO: Expecting 231680 events.
[12:27:27.615] <TB2> INFO: 231680 events read in total (9206ms).
[12:27:27.625] <TB2> INFO: Test took 9898ms.
[12:27:27.870] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:27:27.902] <TB2> INFO: ----------------------------------------------------------------------
[12:27:27.902] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[12:27:27.902] <TB2> INFO: ----------------------------------------------------------------------
[12:27:27.996] <TB2> INFO: Expecting 231680 events.
[12:27:37.930] <TB2> INFO: 231680 events read in total (9342ms).
[12:27:37.940] <TB2> INFO: Test took 10033ms.
[12:27:38.201] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[12:27:38.201] <TB2> INFO: CalDel: 97 98 97 114 98 92 109 124 101 105 91 110 103 99 113 114
[12:27:38.201] <TB2> INFO: VthrComp: 51 51 56 51 53 51 51 51 51 51 51 51 51 51 51 51
[12:27:38.206] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C0.dat
[12:27:38.207] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C1.dat
[12:27:38.207] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C2.dat
[12:27:38.207] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C3.dat
[12:27:38.207] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C4.dat
[12:27:38.207] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C5.dat
[12:27:38.208] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C6.dat
[12:27:38.208] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C7.dat
[12:27:38.208] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C8.dat
[12:27:38.208] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C9.dat
[12:27:38.208] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C10.dat
[12:27:38.208] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C11.dat
[12:27:38.209] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C12.dat
[12:27:38.209] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C13.dat
[12:27:38.209] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C14.dat
[12:27:38.209] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C15.dat
[12:27:38.209] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C0a.dat
[12:27:38.209] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C0b.dat
[12:27:38.209] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C1a.dat
[12:27:38.209] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C1b.dat
[12:27:38.210] <TB2> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[12:27:38.263] <TB2> INFO: enter test to run
[12:27:38.263] <TB2> INFO: test: FullTest no parameter change
[12:27:38.263] <TB2> INFO: running: fulltest
[12:27:38.263] <TB2> INFO: ######################################################################
[12:27:38.263] <TB2> INFO: PixTestFullTest::doTest()
[12:27:38.263] <TB2> INFO: ######################################################################
[12:27:38.264] <TB2> INFO: ######################################################################
[12:27:38.264] <TB2> INFO: PixTestAlive::doTest()
[12:27:38.264] <TB2> INFO: ######################################################################
[12:27:38.265] <TB2> INFO: ----------------------------------------------------------------------
[12:27:38.265] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:27:38.265] <TB2> INFO: ----------------------------------------------------------------------
[12:27:38.530] <TB2> INFO: Expecting 41600 events.
[12:27:42.053] <TB2> INFO: 41600 events read in total (2932ms).
[12:27:42.054] <TB2> INFO: Test took 3787ms.
[12:27:42.287] <TB2> INFO: PixTestAlive::aliveTest() done
[12:27:42.287] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:27:42.288] <TB2> INFO: ----------------------------------------------------------------------
[12:27:42.288] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:27:42.288] <TB2> INFO: ----------------------------------------------------------------------
[12:27:42.532] <TB2> INFO: Expecting 41600 events.
[12:27:45.570] <TB2> INFO: 41600 events read in total (2446ms).
[12:27:45.571] <TB2> INFO: Test took 3281ms.
[12:27:45.571] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:27:45.807] <TB2> INFO: PixTestAlive::maskTest() done
[12:27:45.807] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:27:45.812] <TB2> INFO: ----------------------------------------------------------------------
[12:27:45.812] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:27:45.812] <TB2> INFO: ----------------------------------------------------------------------
[12:27:46.056] <TB2> INFO: Expecting 41600 events.
[12:27:49.560] <TB2> INFO: 41600 events read in total (2913ms).
[12:27:49.561] <TB2> INFO: Test took 3747ms.
[12:27:49.795] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[12:27:49.795] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:27:49.795] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[12:27:49.795] <TB2> INFO: Decoding statistics:
[12:27:49.795] <TB2> INFO: General information:
[12:27:49.795] <TB2> INFO: 16bit words read: 0
[12:27:49.795] <TB2> INFO: valid events total: 0
[12:27:49.795] <TB2> INFO: empty events: 0
[12:27:49.795] <TB2> INFO: valid events with pixels: 0
[12:27:49.795] <TB2> INFO: valid pixel hits: 0
[12:27:49.795] <TB2> INFO: Event errors: 0
[12:27:49.796] <TB2> INFO: start marker: 0
[12:27:49.796] <TB2> INFO: stop marker: 0
[12:27:49.796] <TB2> INFO: overflow: 0
[12:27:49.796] <TB2> INFO: invalid 5bit words: 0
[12:27:49.796] <TB2> INFO: invalid XOR eye diagram: 0
[12:27:49.796] <TB2> INFO: frame (failed synchr.): 0
[12:27:49.796] <TB2> INFO: idle data (no TBM trl): 0
[12:27:49.796] <TB2> INFO: no data (only TBM hdr): 0
[12:27:49.796] <TB2> INFO: TBM errors: 0
[12:27:49.796] <TB2> INFO: flawed TBM headers: 0
[12:27:49.796] <TB2> INFO: flawed TBM trailers: 0
[12:27:49.796] <TB2> INFO: event ID mismatches: 0
[12:27:49.796] <TB2> INFO: ROC errors: 0
[12:27:49.796] <TB2> INFO: missing ROC header(s): 0
[12:27:49.796] <TB2> INFO: misplaced readback start: 0
[12:27:49.796] <TB2> INFO: Pixel decoding errors: 0
[12:27:49.796] <TB2> INFO: pixel data incomplete: 0
[12:27:49.796] <TB2> INFO: pixel address: 0
[12:27:49.796] <TB2> INFO: pulse height fill bit: 0
[12:27:49.796] <TB2> INFO: buffer corruption: 0
[12:27:49.804] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C15.dat
[12:27:49.805] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[12:27:49.805] <TB2> INFO: ######################################################################
[12:27:49.805] <TB2> INFO: PixTestReadback::doTest()
[12:27:49.805] <TB2> INFO: ######################################################################
[12:27:49.805] <TB2> INFO: ----------------------------------------------------------------------
[12:27:49.805] <TB2> INFO: PixTestReadback::CalibrateVd()
[12:27:49.805] <TB2> INFO: ----------------------------------------------------------------------
[12:27:59.763] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C0.dat
[12:27:59.763] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C1.dat
[12:27:59.763] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C2.dat
[12:27:59.764] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C3.dat
[12:27:59.764] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C4.dat
[12:27:59.764] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C5.dat
[12:27:59.764] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C6.dat
[12:27:59.764] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C7.dat
[12:27:59.764] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C8.dat
[12:27:59.764] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C9.dat
[12:27:59.764] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C10.dat
[12:27:59.764] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C11.dat
[12:27:59.764] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C12.dat
[12:27:59.765] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C13.dat
[12:27:59.765] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C14.dat
[12:27:59.765] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C15.dat
[12:27:59.798] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:27:59.798] <TB2> INFO: ----------------------------------------------------------------------
[12:27:59.798] <TB2> INFO: PixTestReadback::CalibrateVa()
[12:27:59.798] <TB2> INFO: ----------------------------------------------------------------------
[12:28:09.734] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C0.dat
[12:28:09.734] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C1.dat
[12:28:09.734] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C2.dat
[12:28:09.734] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C3.dat
[12:28:09.734] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C4.dat
[12:28:09.734] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C5.dat
[12:28:09.734] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C6.dat
[12:28:09.734] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C7.dat
[12:28:09.734] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C8.dat
[12:28:09.734] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C9.dat
[12:28:09.734] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C10.dat
[12:28:09.734] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C11.dat
[12:28:09.734] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C12.dat
[12:28:09.734] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C13.dat
[12:28:09.734] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C14.dat
[12:28:09.735] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C15.dat
[12:28:09.764] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:28:09.764] <TB2> INFO: ----------------------------------------------------------------------
[12:28:09.764] <TB2> INFO: PixTestReadback::readbackVbg()
[12:28:09.764] <TB2> INFO: ----------------------------------------------------------------------
[12:28:17.437] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:28:17.437] <TB2> INFO: ----------------------------------------------------------------------
[12:28:17.437] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[12:28:17.437] <TB2> INFO: ----------------------------------------------------------------------
[12:28:17.437] <TB2> INFO: Vbg will be calibrated using Vd calibration
[12:28:17.437] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 158.7calibrated Vbg = 1.18605 :::*/*/*/*/
[12:28:17.437] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 149.4calibrated Vbg = 1.17341 :::*/*/*/*/
[12:28:17.437] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 155.6calibrated Vbg = 1.17676 :::*/*/*/*/
[12:28:17.437] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 158calibrated Vbg = 1.17873 :::*/*/*/*/
[12:28:17.437] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 148.3calibrated Vbg = 1.16392 :::*/*/*/*/
[12:28:17.437] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 154.9calibrated Vbg = 1.18437 :::*/*/*/*/
[12:28:17.437] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 159.8calibrated Vbg = 1.18474 :::*/*/*/*/
[12:28:17.437] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 151.1calibrated Vbg = 1.187 :::*/*/*/*/
[12:28:17.437] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 153.6calibrated Vbg = 1.18074 :::*/*/*/*/
[12:28:17.437] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 154.1calibrated Vbg = 1.17596 :::*/*/*/*/
[12:28:17.437] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 158.6calibrated Vbg = 1.16802 :::*/*/*/*/
[12:28:17.437] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 158.1calibrated Vbg = 1.17133 :::*/*/*/*/
[12:28:17.437] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 153.8calibrated Vbg = 1.1738 :::*/*/*/*/
[12:28:17.437] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 152.6calibrated Vbg = 1.17612 :::*/*/*/*/
[12:28:17.437] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 157calibrated Vbg = 1.17837 :::*/*/*/*/
[12:28:17.437] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 154.6calibrated Vbg = 1.18197 :::*/*/*/*/
[12:28:17.440] <TB2> INFO: ----------------------------------------------------------------------
[12:28:17.440] <TB2> INFO: PixTestReadback::CalibrateIa()
[12:28:17.440] <TB2> INFO: ----------------------------------------------------------------------
[12:30:58.308] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C0.dat
[12:30:58.308] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C1.dat
[12:30:58.308] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C2.dat
[12:30:58.308] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C3.dat
[12:30:58.308] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C4.dat
[12:30:58.308] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C5.dat
[12:30:58.308] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C6.dat
[12:30:58.308] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C7.dat
[12:30:58.308] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C8.dat
[12:30:58.308] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C9.dat
[12:30:58.308] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C10.dat
[12:30:58.308] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C11.dat
[12:30:58.308] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C12.dat
[12:30:58.309] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C13.dat
[12:30:58.309] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C14.dat
[12:30:58.309] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C15.dat
[12:30:58.338] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:30:58.340] <TB2> INFO: PixTestReadback::doTest() done
[12:30:58.340] <TB2> INFO: Decoding statistics:
[12:30:58.340] <TB2> INFO: General information:
[12:30:58.340] <TB2> INFO: 16bit words read: 1536
[12:30:58.340] <TB2> INFO: valid events total: 256
[12:30:58.340] <TB2> INFO: empty events: 256
[12:30:58.340] <TB2> INFO: valid events with pixels: 0
[12:30:58.340] <TB2> INFO: valid pixel hits: 0
[12:30:58.340] <TB2> INFO: Event errors: 0
[12:30:58.341] <TB2> INFO: start marker: 0
[12:30:58.341] <TB2> INFO: stop marker: 0
[12:30:58.341] <TB2> INFO: overflow: 0
[12:30:58.341] <TB2> INFO: invalid 5bit words: 0
[12:30:58.341] <TB2> INFO: invalid XOR eye diagram: 0
[12:30:58.341] <TB2> INFO: frame (failed synchr.): 0
[12:30:58.341] <TB2> INFO: idle data (no TBM trl): 0
[12:30:58.341] <TB2> INFO: no data (only TBM hdr): 0
[12:30:58.341] <TB2> INFO: TBM errors: 0
[12:30:58.341] <TB2> INFO: flawed TBM headers: 0
[12:30:58.341] <TB2> INFO: flawed TBM trailers: 0
[12:30:58.341] <TB2> INFO: event ID mismatches: 0
[12:30:58.341] <TB2> INFO: ROC errors: 0
[12:30:58.341] <TB2> INFO: missing ROC header(s): 0
[12:30:58.341] <TB2> INFO: misplaced readback start: 0
[12:30:58.341] <TB2> INFO: Pixel decoding errors: 0
[12:30:58.341] <TB2> INFO: pixel data incomplete: 0
[12:30:58.341] <TB2> INFO: pixel address: 0
[12:30:58.341] <TB2> INFO: pulse height fill bit: 0
[12:30:58.341] <TB2> INFO: buffer corruption: 0
[12:30:58.392] <TB2> INFO: ######################################################################
[12:30:58.392] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:30:58.392] <TB2> INFO: ######################################################################
[12:30:58.394] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:30:58.408] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:30:58.408] <TB2> INFO: run 1 of 1
[12:30:58.657] <TB2> INFO: Expecting 3120000 events.
[12:31:29.558] <TB2> INFO: 661935 events read in total (30309ms).











[12:31:59.567] <TB2> INFO: 1320455 events read in total (60318ms).











[12:32:29.770] <TB2> INFO: 1976440 events read in total (90521ms).











[12:33:00.215] <TB2> INFO: 2634480 events read in total (120966ms).











[12:33:22.848] <TB2> INFO: 3120000 events read in total (143599ms).
[12:33:22.924] <TB2> INFO: Test took 144517ms.
[12:33:46.774] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 168 seconds
[12:33:46.774] <TB2> INFO: number of dead bumps (per ROC): 0 0 2 0 0 2 1 1 0 0 5 5 0 4 2 1
[12:33:46.774] <TB2> INFO: separation cut (per ROC): 108 109 109 98 116 104 98 109 110 108 111 110 108 119 106 91
[12:33:46.774] <TB2> INFO: Decoding statistics:
[12:33:46.774] <TB2> INFO: General information:
[12:33:46.774] <TB2> INFO: 16bit words read: 0
[12:33:46.774] <TB2> INFO: valid events total: 0
[12:33:46.774] <TB2> INFO: empty events: 0
[12:33:46.774] <TB2> INFO: valid events with pixels: 0
[12:33:46.774] <TB2> INFO: valid pixel hits: 0
[12:33:46.774] <TB2> INFO: Event errors: 0
[12:33:46.774] <TB2> INFO: start marker: 0
[12:33:46.774] <TB2> INFO: stop marker: 0
[12:33:46.774] <TB2> INFO: overflow: 0
[12:33:46.774] <TB2> INFO: invalid 5bit words: 0
[12:33:46.774] <TB2> INFO: invalid XOR eye diagram: 0
[12:33:46.774] <TB2> INFO: frame (failed synchr.): 0
[12:33:46.774] <TB2> INFO: idle data (no TBM trl): 0
[12:33:46.774] <TB2> INFO: no data (only TBM hdr): 0
[12:33:46.774] <TB2> INFO: TBM errors: 0
[12:33:46.774] <TB2> INFO: flawed TBM headers: 0
[12:33:46.774] <TB2> INFO: flawed TBM trailers: 0
[12:33:46.774] <TB2> INFO: event ID mismatches: 0
[12:33:46.774] <TB2> INFO: ROC errors: 0
[12:33:46.774] <TB2> INFO: missing ROC header(s): 0
[12:33:46.774] <TB2> INFO: misplaced readback start: 0
[12:33:46.774] <TB2> INFO: Pixel decoding errors: 0
[12:33:46.774] <TB2> INFO: pixel data incomplete: 0
[12:33:46.774] <TB2> INFO: pixel address: 0
[12:33:46.774] <TB2> INFO: pulse height fill bit: 0
[12:33:46.774] <TB2> INFO: buffer corruption: 0
[12:33:46.812] <TB2> INFO: ######################################################################
[12:33:46.812] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:33:46.812] <TB2> INFO: ######################################################################
[12:33:46.813] <TB2> INFO: ----------------------------------------------------------------------
[12:33:46.813] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:33:46.813] <TB2> INFO: ----------------------------------------------------------------------
[12:33:46.813] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:33:46.827] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[12:33:46.827] <TB2> INFO: run 1 of 1
[12:33:47.114] <TB2> INFO: Expecting 36608000 events.
[12:34:11.034] <TB2> INFO: 692200 events read in total (23328ms).
[12:34:34.413] <TB2> INFO: 1371250 events read in total (46707ms).
[12:34:57.914] <TB2> INFO: 2046750 events read in total (70208ms).
[12:35:20.967] <TB2> INFO: 2721550 events read in total (93261ms).
[12:35:43.950] <TB2> INFO: 3395950 events read in total (116244ms).
[12:36:07.027] <TB2> INFO: 4072200 events read in total (139321ms).
[12:36:30.312] <TB2> INFO: 4748000 events read in total (162606ms).
[12:36:53.547] <TB2> INFO: 5422650 events read in total (185841ms).
[12:37:16.866] <TB2> INFO: 6095250 events read in total (209160ms).
[12:37:40.060] <TB2> INFO: 6766800 events read in total (232354ms).
[12:38:03.282] <TB2> INFO: 7440350 events read in total (255576ms).
[12:38:26.409] <TB2> INFO: 8112100 events read in total (278703ms).
[12:38:49.468] <TB2> INFO: 8784000 events read in total (301762ms).
[12:39:12.445] <TB2> INFO: 9455300 events read in total (324739ms).
[12:39:35.523] <TB2> INFO: 10126500 events read in total (347817ms).
[12:39:58.379] <TB2> INFO: 10795900 events read in total (370673ms).
[12:40:21.069] <TB2> INFO: 11464900 events read in total (393363ms).
[12:40:43.681] <TB2> INFO: 12134650 events read in total (415975ms).
[12:41:06.606] <TB2> INFO: 12803600 events read in total (438900ms).
[12:41:29.398] <TB2> INFO: 13471050 events read in total (461692ms).
[12:41:52.194] <TB2> INFO: 14138850 events read in total (484488ms).
[12:42:15.011] <TB2> INFO: 14806800 events read in total (507305ms).
[12:42:38.003] <TB2> INFO: 15473050 events read in total (530297ms).
[12:43:00.765] <TB2> INFO: 16138100 events read in total (553059ms).
[12:43:23.498] <TB2> INFO: 16802950 events read in total (575792ms).
[12:43:46.284] <TB2> INFO: 17467700 events read in total (598578ms).
[12:44:09.347] <TB2> INFO: 18132650 events read in total (621641ms).
[12:44:32.114] <TB2> INFO: 18796950 events read in total (644408ms).
[12:44:55.133] <TB2> INFO: 19461850 events read in total (667427ms).
[12:45:17.813] <TB2> INFO: 20125950 events read in total (690107ms).
[12:45:40.795] <TB2> INFO: 20790500 events read in total (713089ms).
[12:46:03.988] <TB2> INFO: 21453650 events read in total (736282ms).
[12:46:26.666] <TB2> INFO: 22116850 events read in total (758960ms).
[12:46:49.580] <TB2> INFO: 22779850 events read in total (781874ms).
[12:47:12.708] <TB2> INFO: 23442250 events read in total (805002ms).
[12:47:35.787] <TB2> INFO: 24104150 events read in total (828081ms).
[12:47:58.570] <TB2> INFO: 24766000 events read in total (850864ms).
[12:48:21.644] <TB2> INFO: 25426050 events read in total (873938ms).
[12:48:44.263] <TB2> INFO: 26086550 events read in total (896557ms).
[12:49:07.149] <TB2> INFO: 26746500 events read in total (919443ms).
[12:49:29.918] <TB2> INFO: 27407150 events read in total (942212ms).
[12:49:52.846] <TB2> INFO: 28065850 events read in total (965140ms).
[12:50:15.437] <TB2> INFO: 28724650 events read in total (987731ms).
[12:50:38.415] <TB2> INFO: 29384600 events read in total (1010709ms).
[12:51:01.222] <TB2> INFO: 30042800 events read in total (1033516ms).
[12:51:23.753] <TB2> INFO: 30702250 events read in total (1056047ms).
[12:51:46.662] <TB2> INFO: 31360900 events read in total (1078956ms).
[12:52:09.430] <TB2> INFO: 32019750 events read in total (1101724ms).
[12:52:32.316] <TB2> INFO: 32679700 events read in total (1124610ms).
[12:52:55.109] <TB2> INFO: 33339500 events read in total (1147403ms).
[12:53:17.798] <TB2> INFO: 33999600 events read in total (1170092ms).
[12:53:40.775] <TB2> INFO: 34660050 events read in total (1193069ms).
[12:54:03.530] <TB2> INFO: 35320600 events read in total (1215824ms).
[12:54:26.197] <TB2> INFO: 35983500 events read in total (1238492ms).
[12:54:47.311] <TB2> INFO: 36608000 events read in total (1259605ms).
[12:54:47.412] <TB2> INFO: Test took 1260585ms.
[12:54:47.866] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:54:49.472] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:54:51.392] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:54:53.355] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:54:55.379] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:54:57.468] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:54:59.464] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:01.454] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:03.102] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:05.190] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:07.223] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:09.165] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:11.254] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:13.284] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:15.378] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:17.505] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:19.540] <TB2> INFO: PixTestScurves::scurves() done
[12:55:19.540] <TB2> INFO: Vcal mean: 120.35 125.87 122.58 121.66 122.15 112.30 114.71 117.97 115.38 111.40 119.76 120.49 113.78 123.37 126.76 105.54
[12:55:19.540] <TB2> INFO: Vcal RMS: 6.05 6.02 6.39 6.54 6.38 4.96 6.17 5.53 6.37 5.90 6.14 6.52 5.41 6.52 6.48 5.36
[12:55:19.540] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1292 seconds
[12:55:19.540] <TB2> INFO: Decoding statistics:
[12:55:19.540] <TB2> INFO: General information:
[12:55:19.540] <TB2> INFO: 16bit words read: 0
[12:55:19.540] <TB2> INFO: valid events total: 0
[12:55:19.540] <TB2> INFO: empty events: 0
[12:55:19.540] <TB2> INFO: valid events with pixels: 0
[12:55:19.540] <TB2> INFO: valid pixel hits: 0
[12:55:19.540] <TB2> INFO: Event errors: 0
[12:55:19.540] <TB2> INFO: start marker: 0
[12:55:19.540] <TB2> INFO: stop marker: 0
[12:55:19.540] <TB2> INFO: overflow: 0
[12:55:19.540] <TB2> INFO: invalid 5bit words: 0
[12:55:19.540] <TB2> INFO: invalid XOR eye diagram: 0
[12:55:19.540] <TB2> INFO: frame (failed synchr.): 0
[12:55:19.540] <TB2> INFO: idle data (no TBM trl): 0
[12:55:19.540] <TB2> INFO: no data (only TBM hdr): 0
[12:55:19.540] <TB2> INFO: TBM errors: 0
[12:55:19.540] <TB2> INFO: flawed TBM headers: 0
[12:55:19.540] <TB2> INFO: flawed TBM trailers: 0
[12:55:19.540] <TB2> INFO: event ID mismatches: 0
[12:55:19.540] <TB2> INFO: ROC errors: 0
[12:55:19.540] <TB2> INFO: missing ROC header(s): 0
[12:55:19.540] <TB2> INFO: misplaced readback start: 0
[12:55:19.540] <TB2> INFO: Pixel decoding errors: 0
[12:55:19.540] <TB2> INFO: pixel data incomplete: 0
[12:55:19.540] <TB2> INFO: pixel address: 0
[12:55:19.540] <TB2> INFO: pulse height fill bit: 0
[12:55:19.540] <TB2> INFO: buffer corruption: 0
[12:55:19.606] <TB2> INFO: ######################################################################
[12:55:19.606] <TB2> INFO: PixTestTrim::doTest()
[12:55:19.606] <TB2> INFO: ######################################################################
[12:55:19.607] <TB2> INFO: ----------------------------------------------------------------------
[12:55:19.607] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:55:19.607] <TB2> INFO: ----------------------------------------------------------------------
[12:55:19.669] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:55:19.669] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:55:19.682] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:55:19.682] <TB2> INFO: run 1 of 1
[12:55:19.920] <TB2> INFO: Expecting 5025280 events.
[12:55:50.745] <TB2> INFO: 830488 events read in total (30222ms).
[12:56:21.361] <TB2> INFO: 1659392 events read in total (60838ms).
[12:56:51.741] <TB2> INFO: 2484240 events read in total (91218ms).
[12:57:22.200] <TB2> INFO: 3306216 events read in total (121677ms).
[12:57:53.041] <TB2> INFO: 4123616 events read in total (152518ms).
[12:58:23.663] <TB2> INFO: 4939472 events read in total (183140ms).
[12:58:27.386] <TB2> INFO: 5025280 events read in total (186863ms).
[12:58:27.475] <TB2> INFO: Test took 187793ms.
[12:58:49.442] <TB2> INFO: ROC 0 VthrComp = 125
[12:58:49.443] <TB2> INFO: ROC 1 VthrComp = 132
[12:58:49.443] <TB2> INFO: ROC 2 VthrComp = 129
[12:58:49.443] <TB2> INFO: ROC 3 VthrComp = 122
[12:58:49.443] <TB2> INFO: ROC 4 VthrComp = 130
[12:58:49.443] <TB2> INFO: ROC 5 VthrComp = 117
[12:58:49.443] <TB2> INFO: ROC 6 VthrComp = 112
[12:58:49.443] <TB2> INFO: ROC 7 VthrComp = 119
[12:58:49.443] <TB2> INFO: ROC 8 VthrComp = 115
[12:58:49.444] <TB2> INFO: ROC 9 VthrComp = 112
[12:58:49.444] <TB2> INFO: ROC 10 VthrComp = 126
[12:58:49.444] <TB2> INFO: ROC 11 VthrComp = 122
[12:58:49.444] <TB2> INFO: ROC 12 VthrComp = 115
[12:58:49.444] <TB2> INFO: ROC 13 VthrComp = 126
[12:58:49.444] <TB2> INFO: ROC 14 VthrComp = 120
[12:58:49.445] <TB2> INFO: ROC 15 VthrComp = 102
[12:58:49.709] <TB2> INFO: Expecting 41600 events.
[12:58:53.272] <TB2> INFO: 41600 events read in total (2971ms).
[12:58:53.273] <TB2> INFO: Test took 3827ms.
[12:58:53.284] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:58:53.284] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:58:53.298] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:58:53.298] <TB2> INFO: run 1 of 1
[12:58:53.576] <TB2> INFO: Expecting 5025280 events.
[12:59:19.821] <TB2> INFO: 592704 events read in total (25653ms).
[12:59:45.416] <TB2> INFO: 1183064 events read in total (51248ms).
[13:00:11.261] <TB2> INFO: 1774248 events read in total (77093ms).
[13:00:36.772] <TB2> INFO: 2364248 events read in total (102604ms).
[13:01:02.495] <TB2> INFO: 2952408 events read in total (128327ms).
[13:01:28.636] <TB2> INFO: 3539280 events read in total (154468ms).
[13:01:54.624] <TB2> INFO: 4125168 events read in total (180456ms).
[13:02:20.225] <TB2> INFO: 4710576 events read in total (206057ms).
[13:02:34.475] <TB2> INFO: 5025280 events read in total (220307ms).
[13:02:34.744] <TB2> INFO: Test took 221445ms.
[13:03:01.828] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 61.1628 for pixel 19/2 mean/min/max = 46.524/31.6199/61.4281
[13:03:01.829] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 62.9612 for pixel 13/13 mean/min/max = 47.875/32.739/63.011
[13:03:01.829] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 64.9872 for pixel 16/10 mean/min/max = 48.2206/31.2927/65.1486
[13:03:01.829] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 63.3365 for pixel 32/16 mean/min/max = 47.5752/31.2828/63.8676
[13:03:01.830] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 63.765 for pixel 51/3 mean/min/max = 49.3706/34.9354/63.8059
[13:03:01.830] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 59.3574 for pixel 1/63 mean/min/max = 45.693/31.6275/59.7586
[13:03:01.830] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 64.0942 for pixel 0/16 mean/min/max = 47.5063/30.8851/64.1275
[13:03:01.831] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 60.9746 for pixel 30/2 mean/min/max = 46.1049/30.8819/61.3278
[13:03:01.831] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 62.4059 for pixel 29/14 mean/min/max = 46.8054/31.1708/62.4399
[13:03:01.831] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 61.1009 for pixel 3/74 mean/min/max = 46.5413/31.8809/61.2017
[13:03:01.832] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 59.8597 for pixel 0/11 mean/min/max = 45.4219/30.8982/59.9457
[13:03:01.832] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 63.8234 for pixel 17/75 mean/min/max = 47.2925/30.5651/64.0199
[13:03:01.833] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 60.32 for pixel 0/11 mean/min/max = 46.2241/32.0677/60.3804
[13:03:01.833] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 61.0702 for pixel 17/5 mean/min/max = 46.0695/30.9783/61.1606
[13:03:01.833] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 64.5444 for pixel 4/5 mean/min/max = 48.2463/31.8074/64.6852
[13:03:01.834] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 62.8293 for pixel 17/65 mean/min/max = 47.8591/32.8874/62.8307
[13:03:01.834] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:03:01.923] <TB2> INFO: Expecting 411648 events.
[13:03:11.324] <TB2> INFO: 411648 events read in total (8810ms).
[13:03:11.331] <TB2> INFO: Expecting 411648 events.
[13:03:20.585] <TB2> INFO: 411648 events read in total (8851ms).
[13:03:20.598] <TB2> INFO: Expecting 411648 events.
[13:03:29.914] <TB2> INFO: 411648 events read in total (8913ms).
[13:03:29.931] <TB2> INFO: Expecting 411648 events.
[13:03:39.173] <TB2> INFO: 411648 events read in total (8839ms).
[13:03:39.194] <TB2> INFO: Expecting 411648 events.
[13:03:48.503] <TB2> INFO: 411648 events read in total (8906ms).
[13:03:48.523] <TB2> INFO: Expecting 411648 events.
[13:03:57.850] <TB2> INFO: 411648 events read in total (8924ms).
[13:03:57.871] <TB2> INFO: Expecting 411648 events.
[13:04:07.203] <TB2> INFO: 411648 events read in total (8929ms).
[13:04:07.227] <TB2> INFO: Expecting 411648 events.
[13:04:16.609] <TB2> INFO: 411648 events read in total (8979ms).
[13:04:16.638] <TB2> INFO: Expecting 411648 events.
[13:04:25.951] <TB2> INFO: 411648 events read in total (8910ms).
[13:04:25.981] <TB2> INFO: Expecting 411648 events.
[13:04:35.257] <TB2> INFO: 411648 events read in total (8873ms).
[13:04:35.290] <TB2> INFO: Expecting 411648 events.
[13:04:44.645] <TB2> INFO: 411648 events read in total (8952ms).
[13:04:44.692] <TB2> INFO: Expecting 411648 events.
[13:04:54.076] <TB2> INFO: 411648 events read in total (8981ms).
[13:04:54.113] <TB2> INFO: Expecting 411648 events.
[13:05:03.395] <TB2> INFO: 411648 events read in total (8879ms).
[13:05:03.452] <TB2> INFO: Expecting 411648 events.
[13:05:12.803] <TB2> INFO: 411648 events read in total (8948ms).
[13:05:12.866] <TB2> INFO: Expecting 411648 events.
[13:05:22.204] <TB2> INFO: 411648 events read in total (8935ms).
[13:05:22.263] <TB2> INFO: Expecting 411648 events.
[13:05:31.507] <TB2> INFO: 411648 events read in total (8841ms).
[13:05:31.573] <TB2> INFO: Test took 149739ms.
[13:05:32.318] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:05:32.336] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:05:32.336] <TB2> INFO: run 1 of 1
[13:05:32.597] <TB2> INFO: Expecting 5025280 events.
[13:05:59.041] <TB2> INFO: 589888 events read in total (25853ms).
[13:06:25.014] <TB2> INFO: 1177672 events read in total (51826ms).
[13:06:50.914] <TB2> INFO: 1765944 events read in total (77726ms).
[13:07:16.989] <TB2> INFO: 2354120 events read in total (103801ms).
[13:07:43.198] <TB2> INFO: 2940280 events read in total (130010ms).
[13:08:09.317] <TB2> INFO: 3526792 events read in total (156129ms).
[13:08:35.199] <TB2> INFO: 4112112 events read in total (182011ms).
[13:09:01.151] <TB2> INFO: 4697464 events read in total (207963ms).
[13:09:16.111] <TB2> INFO: 5025280 events read in total (222923ms).
[13:09:16.317] <TB2> INFO: Test took 223982ms.
[13:09:39.784] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 2.025298 .. 144.409903
[13:09:40.021] <TB2> INFO: Expecting 208000 events.
[13:09:49.595] <TB2> INFO: 208000 events read in total (8982ms).
[13:09:49.597] <TB2> INFO: Test took 9812ms.
[13:09:49.672] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 154 (-1/-1) hits flags = 528 (plus default)
[13:09:49.685] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:09:49.685] <TB2> INFO: run 1 of 1
[13:09:49.963] <TB2> INFO: Expecting 5091840 events.
[13:10:15.893] <TB2> INFO: 582728 events read in total (25338ms).
[13:10:41.906] <TB2> INFO: 1166240 events read in total (51351ms).
[13:11:07.772] <TB2> INFO: 1749496 events read in total (77218ms).
[13:11:32.947] <TB2> INFO: 2332928 events read in total (102393ms).
[13:11:58.660] <TB2> INFO: 2916264 events read in total (128105ms).
[13:12:24.575] <TB2> INFO: 3499288 events read in total (154020ms).
[13:12:50.496] <TB2> INFO: 4081688 events read in total (179941ms).
[13:13:16.234] <TB2> INFO: 4663952 events read in total (205679ms).
[13:13:35.213] <TB2> INFO: 5091840 events read in total (224658ms).
[13:13:35.333] <TB2> INFO: Test took 225647ms.
[13:14:04.308] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.500000 .. 46.223619
[13:14:04.596] <TB2> INFO: Expecting 208000 events.
[13:14:14.927] <TB2> INFO: 208000 events read in total (9740ms).
[13:14:14.928] <TB2> INFO: Test took 10619ms.
[13:14:14.977] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[13:14:14.990] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:14:14.990] <TB2> INFO: run 1 of 1
[13:14:15.267] <TB2> INFO: Expecting 1331200 events.
[13:14:43.685] <TB2> INFO: 654896 events read in total (27826ms).
[13:15:11.192] <TB2> INFO: 1308072 events read in total (55333ms).
[13:15:12.644] <TB2> INFO: 1331200 events read in total (56786ms).
[13:15:12.680] <TB2> INFO: Test took 57691ms.
[13:15:28.302] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 26.613931 .. 47.654563
[13:15:28.541] <TB2> INFO: Expecting 208000 events.
[13:15:38.382] <TB2> INFO: 208000 events read in total (9246ms).
[13:15:38.383] <TB2> INFO: Test took 10079ms.
[13:15:38.440] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 57 (-1/-1) hits flags = 528 (plus default)
[13:15:38.452] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:15:38.453] <TB2> INFO: run 1 of 1
[13:15:38.731] <TB2> INFO: Expecting 1397760 events.
[13:16:06.825] <TB2> INFO: 655832 events read in total (27503ms).
[13:16:34.621] <TB2> INFO: 1310112 events read in total (55299ms).
[13:16:38.633] <TB2> INFO: 1397760 events read in total (59311ms).
[13:16:38.666] <TB2> INFO: Test took 60214ms.
[13:16:51.707] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 25.404329 .. 45.869812
[13:16:51.945] <TB2> INFO: Expecting 208000 events.
[13:17:01.791] <TB2> INFO: 208000 events read in total (9254ms).
[13:17:01.792] <TB2> INFO: Test took 10083ms.
[13:17:01.846] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[13:17:01.858] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:17:01.858] <TB2> INFO: run 1 of 1
[13:17:02.136] <TB2> INFO: Expecting 1364480 events.
[13:17:30.482] <TB2> INFO: 666952 events read in total (27754ms).
[13:17:58.031] <TB2> INFO: 1333504 events read in total (55303ms).
[13:17:59.793] <TB2> INFO: 1364480 events read in total (57065ms).
[13:17:59.822] <TB2> INFO: Test took 57964ms.
[13:18:14.022] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[13:18:14.022] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[13:18:14.039] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:18:14.039] <TB2> INFO: run 1 of 1
[13:18:14.280] <TB2> INFO: Expecting 1364480 events.
[13:18:42.581] <TB2> INFO: 667360 events read in total (27709ms).
[13:19:10.423] <TB2> INFO: 1334144 events read in total (55551ms).
[13:19:12.074] <TB2> INFO: 1364480 events read in total (57202ms).
[13:19:12.101] <TB2> INFO: Test took 58061ms.
[13:19:27.230] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C0.dat
[13:19:27.230] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C1.dat
[13:19:27.230] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C2.dat
[13:19:27.230] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C3.dat
[13:19:27.230] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C4.dat
[13:19:27.230] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C5.dat
[13:19:27.230] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C6.dat
[13:19:27.230] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C7.dat
[13:19:27.230] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C8.dat
[13:19:27.231] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C9.dat
[13:19:27.231] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C10.dat
[13:19:27.231] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C11.dat
[13:19:27.231] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C12.dat
[13:19:27.231] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C13.dat
[13:19:27.231] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C14.dat
[13:19:27.231] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C15.dat
[13:19:27.231] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C0.dat
[13:19:27.236] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C1.dat
[13:19:27.240] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C2.dat
[13:19:27.245] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C3.dat
[13:19:27.250] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C4.dat
[13:19:27.254] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C5.dat
[13:19:27.259] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C6.dat
[13:19:27.264] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C7.dat
[13:19:27.268] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C8.dat
[13:19:27.273] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C9.dat
[13:19:27.278] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C10.dat
[13:19:27.282] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C11.dat
[13:19:27.287] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C12.dat
[13:19:27.292] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C13.dat
[13:19:27.296] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C14.dat
[13:19:27.301] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C15.dat
[13:19:27.306] <TB2> INFO: PixTestTrim::trimTest() done
[13:19:27.306] <TB2> INFO: vtrim: 144 149 155 137 133 121 118 129 146 123 124 157 131 133 134 119
[13:19:27.306] <TB2> INFO: vthrcomp: 125 132 129 122 130 117 112 119 115 112 126 122 115 126 120 102
[13:19:27.306] <TB2> INFO: vcal mean: 34.95 35.04 35.06 34.98 34.99 34.92 34.92 34.90 34.95 35.02 34.90 35.08 34.94 34.95 35.19 35.00
[13:19:27.306] <TB2> INFO: vcal RMS: 1.09 1.14 1.19 1.21 1.02 1.03 1.15 1.12 1.15 1.05 1.19 1.36 1.04 1.08 1.42 1.15
[13:19:27.306] <TB2> INFO: bits mean: 9.48 9.35 9.68 9.62 7.63 9.62 8.98 9.42 9.77 9.45 9.40 9.87 9.52 9.90 9.45 9.16
[13:19:27.306] <TB2> INFO: bits RMS: 2.71 2.54 2.55 2.56 2.70 2.72 2.95 2.90 2.64 2.70 2.90 2.64 2.65 2.66 2.67 2.63
[13:19:27.315] <TB2> INFO: ----------------------------------------------------------------------
[13:19:27.315] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:19:27.315] <TB2> INFO: ----------------------------------------------------------------------
[13:19:27.318] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:19:27.330] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:19:27.330] <TB2> INFO: run 1 of 1
[13:19:27.607] <TB2> INFO: Expecting 4160000 events.
[13:20:00.007] <TB2> INFO: 764270 events read in total (31808ms).
[13:20:32.024] <TB2> INFO: 1518420 events read in total (63825ms).
[13:21:04.195] <TB2> INFO: 2265840 events read in total (95997ms).
[13:21:36.086] <TB2> INFO: 3008525 events read in total (127887ms).
[13:22:07.902] <TB2> INFO: 3747315 events read in total (159703ms).
[13:22:25.866] <TB2> INFO: 4160000 events read in total (177667ms).
[13:22:26.052] <TB2> INFO: Test took 178721ms.
[13:22:57.667] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[13:22:57.680] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:22:57.680] <TB2> INFO: run 1 of 1
[13:22:57.986] <TB2> INFO: Expecting 4264000 events.
[13:23:29.992] <TB2> INFO: 733225 events read in total (31414ms).
[13:24:01.089] <TB2> INFO: 1458685 events read in total (62511ms).
[13:24:32.283] <TB2> INFO: 2178185 events read in total (93705ms).
[13:25:03.631] <TB2> INFO: 2894245 events read in total (125053ms).
[13:25:34.631] <TB2> INFO: 3605620 events read in total (156053ms).
[13:26:03.136] <TB2> INFO: 4264000 events read in total (184558ms).
[13:26:03.241] <TB2> INFO: Test took 185560ms.
[13:26:32.991] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[13:26:33.005] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:26:33.005] <TB2> INFO: run 1 of 1
[13:26:33.256] <TB2> INFO: Expecting 4243200 events.
[13:27:06.243] <TB2> INFO: 735190 events read in total (32395ms).
[13:27:38.392] <TB2> INFO: 1462465 events read in total (64544ms).
[13:28:10.389] <TB2> INFO: 2183550 events read in total (96541ms).
[13:28:41.492] <TB2> INFO: 2900880 events read in total (127644ms).
[13:29:12.906] <TB2> INFO: 3613735 events read in total (159058ms).
[13:29:40.302] <TB2> INFO: 4243200 events read in total (186454ms).
[13:29:40.482] <TB2> INFO: Test took 187477ms.
[13:30:09.777] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[13:30:09.790] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:30:09.790] <TB2> INFO: run 1 of 1
[13:30:10.084] <TB2> INFO: Expecting 4243200 events.
[13:30:42.878] <TB2> INFO: 735270 events read in total (32202ms).
[13:31:14.546] <TB2> INFO: 1462625 events read in total (63870ms).
[13:31:46.157] <TB2> INFO: 2183810 events read in total (95481ms).
[13:32:18.221] <TB2> INFO: 2901280 events read in total (127545ms).
[13:32:48.902] <TB2> INFO: 3614280 events read in total (158226ms).
[13:33:16.069] <TB2> INFO: 4243200 events read in total (185393ms).
[13:33:16.166] <TB2> INFO: Test took 186376ms.
[13:33:47.806] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[13:33:47.820] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:33:47.820] <TB2> INFO: run 1 of 1
[13:33:48.099] <TB2> INFO: Expecting 4243200 events.
[13:34:20.540] <TB2> INFO: 735515 events read in total (31850ms).
[13:34:51.819] <TB2> INFO: 1463180 events read in total (63129ms).
[13:35:23.172] <TB2> INFO: 2184540 events read in total (94482ms).
[13:35:53.958] <TB2> INFO: 2902290 events read in total (125268ms).
[13:36:24.938] <TB2> INFO: 3615565 events read in total (156248ms).
[13:36:52.351] <TB2> INFO: 4243200 events read in total (183661ms).
[13:36:52.430] <TB2> INFO: Test took 184610ms.
[13:37:19.663] <TB2> INFO: PixTestTrim::trimBitTest() done
[13:37:19.664] <TB2> INFO: PixTestTrim::doTest() done, duration: 2520 seconds
[13:37:19.665] <TB2> INFO: Decoding statistics:
[13:37:19.665] <TB2> INFO: General information:
[13:37:19.665] <TB2> INFO: 16bit words read: 0
[13:37:19.665] <TB2> INFO: valid events total: 0
[13:37:19.665] <TB2> INFO: empty events: 0
[13:37:19.665] <TB2> INFO: valid events with pixels: 0
[13:37:19.665] <TB2> INFO: valid pixel hits: 0
[13:37:19.665] <TB2> INFO: Event errors: 0
[13:37:19.665] <TB2> INFO: start marker: 0
[13:37:19.665] <TB2> INFO: stop marker: 0
[13:37:19.665] <TB2> INFO: overflow: 0
[13:37:19.665] <TB2> INFO: invalid 5bit words: 0
[13:37:19.665] <TB2> INFO: invalid XOR eye diagram: 0
[13:37:19.665] <TB2> INFO: frame (failed synchr.): 0
[13:37:19.665] <TB2> INFO: idle data (no TBM trl): 0
[13:37:19.665] <TB2> INFO: no data (only TBM hdr): 0
[13:37:19.665] <TB2> INFO: TBM errors: 0
[13:37:19.665] <TB2> INFO: flawed TBM headers: 0
[13:37:19.665] <TB2> INFO: flawed TBM trailers: 0
[13:37:19.665] <TB2> INFO: event ID mismatches: 0
[13:37:19.665] <TB2> INFO: ROC errors: 0
[13:37:19.665] <TB2> INFO: missing ROC header(s): 0
[13:37:19.665] <TB2> INFO: misplaced readback start: 0
[13:37:19.665] <TB2> INFO: Pixel decoding errors: 0
[13:37:19.665] <TB2> INFO: pixel data incomplete: 0
[13:37:19.665] <TB2> INFO: pixel address: 0
[13:37:19.665] <TB2> INFO: pulse height fill bit: 0
[13:37:19.665] <TB2> INFO: buffer corruption: 0
[13:37:20.269] <TB2> INFO: ######################################################################
[13:37:20.269] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:37:20.269] <TB2> INFO: ######################################################################
[13:37:20.508] <TB2> INFO: Expecting 41600 events.
[13:37:23.932] <TB2> INFO: 41600 events read in total (2833ms).
[13:37:23.932] <TB2> INFO: Test took 3661ms.
[13:37:24.395] <TB2> INFO: Expecting 41600 events.
[13:37:27.864] <TB2> INFO: 41600 events read in total (2878ms).
[13:37:27.866] <TB2> INFO: Test took 3731ms.
[13:37:28.164] <TB2> INFO: Expecting 41600 events.
[13:37:31.675] <TB2> INFO: 41600 events read in total (2920ms).
[13:37:31.676] <TB2> INFO: Test took 3785ms.
[13:37:31.965] <TB2> INFO: Expecting 41600 events.
[13:37:35.554] <TB2> INFO: 41600 events read in total (2997ms).
[13:37:35.555] <TB2> INFO: Test took 3855ms.
[13:37:35.844] <TB2> INFO: Expecting 41600 events.
[13:37:39.334] <TB2> INFO: 41600 events read in total (2899ms).
[13:37:39.334] <TB2> INFO: Test took 3755ms.
[13:37:39.624] <TB2> INFO: Expecting 41600 events.
[13:37:43.093] <TB2> INFO: 41600 events read in total (2877ms).
[13:37:43.094] <TB2> INFO: Test took 3736ms.
[13:37:43.383] <TB2> INFO: Expecting 41600 events.
[13:37:46.864] <TB2> INFO: 41600 events read in total (2890ms).
[13:37:46.865] <TB2> INFO: Test took 3747ms.
[13:37:47.154] <TB2> INFO: Expecting 41600 events.
[13:37:50.623] <TB2> INFO: 41600 events read in total (2878ms).
[13:37:50.624] <TB2> INFO: Test took 3735ms.
[13:37:50.915] <TB2> INFO: Expecting 41600 events.
[13:37:54.702] <TB2> INFO: 41600 events read in total (3195ms).
[13:37:54.702] <TB2> INFO: Test took 4055ms.
[13:37:54.995] <TB2> INFO: Expecting 41600 events.
[13:37:58.460] <TB2> INFO: 41600 events read in total (2873ms).
[13:37:58.467] <TB2> INFO: Test took 3738ms.
[13:37:58.758] <TB2> INFO: Expecting 41600 events.
[13:38:02.302] <TB2> INFO: 41600 events read in total (2952ms).
[13:38:02.302] <TB2> INFO: Test took 3808ms.
[13:38:02.591] <TB2> INFO: Expecting 41600 events.
[13:38:06.234] <TB2> INFO: 41600 events read in total (3047ms).
[13:38:06.234] <TB2> INFO: Test took 3908ms.
[13:38:06.587] <TB2> INFO: Expecting 41600 events.
[13:38:10.170] <TB2> INFO: 41600 events read in total (2991ms).
[13:38:10.171] <TB2> INFO: Test took 3911ms.
[13:38:10.460] <TB2> INFO: Expecting 41600 events.
[13:38:14.028] <TB2> INFO: 41600 events read in total (2977ms).
[13:38:14.028] <TB2> INFO: Test took 3833ms.
[13:38:14.317] <TB2> INFO: Expecting 41600 events.
[13:38:17.879] <TB2> INFO: 41600 events read in total (2970ms).
[13:38:17.880] <TB2> INFO: Test took 3828ms.
[13:38:18.169] <TB2> INFO: Expecting 41600 events.
[13:38:21.725] <TB2> INFO: 41600 events read in total (2964ms).
[13:38:21.726] <TB2> INFO: Test took 3822ms.
[13:38:22.018] <TB2> INFO: Expecting 41600 events.
[13:38:25.604] <TB2> INFO: 41600 events read in total (2994ms).
[13:38:25.605] <TB2> INFO: Test took 3852ms.
[13:38:25.896] <TB2> INFO: Expecting 41600 events.
[13:38:29.436] <TB2> INFO: 41600 events read in total (2948ms).
[13:38:29.437] <TB2> INFO: Test took 3805ms.
[13:38:29.726] <TB2> INFO: Expecting 41600 events.
[13:38:33.377] <TB2> INFO: 41600 events read in total (3059ms).
[13:38:33.378] <TB2> INFO: Test took 3917ms.
[13:38:33.668] <TB2> INFO: Expecting 41600 events.
[13:38:37.226] <TB2> INFO: 41600 events read in total (2966ms).
[13:38:37.227] <TB2> INFO: Test took 3824ms.
[13:38:37.515] <TB2> INFO: Expecting 41600 events.
[13:38:41.070] <TB2> INFO: 41600 events read in total (2958ms).
[13:38:41.070] <TB2> INFO: Test took 3820ms.
[13:38:41.360] <TB2> INFO: Expecting 41600 events.
[13:38:45.005] <TB2> INFO: 41600 events read in total (3053ms).
[13:38:45.006] <TB2> INFO: Test took 3910ms.
[13:38:45.313] <TB2> INFO: Expecting 41600 events.
[13:38:48.970] <TB2> INFO: 41600 events read in total (3065ms).
[13:38:48.970] <TB2> INFO: Test took 3938ms.
[13:38:49.260] <TB2> INFO: Expecting 41600 events.
[13:38:52.790] <TB2> INFO: 41600 events read in total (2938ms).
[13:38:52.791] <TB2> INFO: Test took 3795ms.
[13:38:53.080] <TB2> INFO: Expecting 41600 events.
[13:38:56.620] <TB2> INFO: 41600 events read in total (2949ms).
[13:38:56.621] <TB2> INFO: Test took 3806ms.
[13:38:56.910] <TB2> INFO: Expecting 41600 events.
[13:39:00.439] <TB2> INFO: 41600 events read in total (2937ms).
[13:39:00.440] <TB2> INFO: Test took 3795ms.
[13:39:00.729] <TB2> INFO: Expecting 41600 events.
[13:39:04.260] <TB2> INFO: 41600 events read in total (2939ms).
[13:39:04.261] <TB2> INFO: Test took 3797ms.
[13:39:04.551] <TB2> INFO: Expecting 41600 events.
[13:39:08.081] <TB2> INFO: 41600 events read in total (2938ms).
[13:39:08.082] <TB2> INFO: Test took 3796ms.
[13:39:08.372] <TB2> INFO: Expecting 2560 events.
[13:39:09.260] <TB2> INFO: 2560 events read in total (296ms).
[13:39:09.261] <TB2> INFO: Test took 1167ms.
[13:39:09.567] <TB2> INFO: Expecting 2560 events.
[13:39:10.458] <TB2> INFO: 2560 events read in total (299ms).
[13:39:10.459] <TB2> INFO: Test took 1197ms.
[13:39:10.766] <TB2> INFO: Expecting 2560 events.
[13:39:11.650] <TB2> INFO: 2560 events read in total (292ms).
[13:39:11.650] <TB2> INFO: Test took 1190ms.
[13:39:11.959] <TB2> INFO: Expecting 2560 events.
[13:39:12.843] <TB2> INFO: 2560 events read in total (292ms).
[13:39:12.843] <TB2> INFO: Test took 1192ms.
[13:39:13.151] <TB2> INFO: Expecting 2560 events.
[13:39:14.042] <TB2> INFO: 2560 events read in total (299ms).
[13:39:14.042] <TB2> INFO: Test took 1199ms.
[13:39:14.350] <TB2> INFO: Expecting 2560 events.
[13:39:15.240] <TB2> INFO: 2560 events read in total (298ms).
[13:39:15.240] <TB2> INFO: Test took 1197ms.
[13:39:15.549] <TB2> INFO: Expecting 2560 events.
[13:39:16.430] <TB2> INFO: 2560 events read in total (290ms).
[13:39:16.430] <TB2> INFO: Test took 1189ms.
[13:39:16.738] <TB2> INFO: Expecting 2560 events.
[13:39:17.629] <TB2> INFO: 2560 events read in total (300ms).
[13:39:17.629] <TB2> INFO: Test took 1198ms.
[13:39:17.937] <TB2> INFO: Expecting 2560 events.
[13:39:18.830] <TB2> INFO: 2560 events read in total (301ms).
[13:39:18.830] <TB2> INFO: Test took 1200ms.
[13:39:19.137] <TB2> INFO: Expecting 2560 events.
[13:39:20.016] <TB2> INFO: 2560 events read in total (287ms).
[13:39:20.017] <TB2> INFO: Test took 1186ms.
[13:39:20.325] <TB2> INFO: Expecting 2560 events.
[13:39:21.205] <TB2> INFO: 2560 events read in total (289ms).
[13:39:21.205] <TB2> INFO: Test took 1188ms.
[13:39:21.514] <TB2> INFO: Expecting 2560 events.
[13:39:22.407] <TB2> INFO: 2560 events read in total (302ms).
[13:39:22.407] <TB2> INFO: Test took 1201ms.
[13:39:22.715] <TB2> INFO: Expecting 2560 events.
[13:39:23.602] <TB2> INFO: 2560 events read in total (296ms).
[13:39:23.602] <TB2> INFO: Test took 1194ms.
[13:39:23.910] <TB2> INFO: Expecting 2560 events.
[13:39:24.797] <TB2> INFO: 2560 events read in total (295ms).
[13:39:24.798] <TB2> INFO: Test took 1196ms.
[13:39:25.106] <TB2> INFO: Expecting 2560 events.
[13:39:25.998] <TB2> INFO: 2560 events read in total (300ms).
[13:39:25.998] <TB2> INFO: Test took 1200ms.
[13:39:26.306] <TB2> INFO: Expecting 2560 events.
[13:39:27.196] <TB2> INFO: 2560 events read in total (298ms).
[13:39:27.197] <TB2> INFO: Test took 1198ms.
[13:39:27.200] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:27.505] <TB2> INFO: Expecting 655360 events.
[13:39:42.497] <TB2> INFO: 655360 events read in total (14400ms).
[13:39:42.511] <TB2> INFO: Expecting 655360 events.
[13:39:57.391] <TB2> INFO: 655360 events read in total (14477ms).
[13:39:57.407] <TB2> INFO: Expecting 655360 events.
[13:40:12.085] <TB2> INFO: 655360 events read in total (14275ms).
[13:40:12.110] <TB2> INFO: Expecting 655360 events.
[13:40:26.907] <TB2> INFO: 655360 events read in total (14394ms).
[13:40:26.931] <TB2> INFO: Expecting 655360 events.
[13:40:41.504] <TB2> INFO: 655360 events read in total (14169ms).
[13:40:41.534] <TB2> INFO: Expecting 655360 events.
[13:40:56.359] <TB2> INFO: 655360 events read in total (14422ms).
[13:40:56.402] <TB2> INFO: Expecting 655360 events.
[13:41:11.293] <TB2> INFO: 655360 events read in total (14488ms).
[13:41:11.330] <TB2> INFO: Expecting 655360 events.
[13:41:25.983] <TB2> INFO: 655360 events read in total (14250ms).
[13:41:26.234] <TB2> INFO: Expecting 655360 events.
[13:41:40.862] <TB2> INFO: 655360 events read in total (14226ms).
[13:41:40.914] <TB2> INFO: Expecting 655360 events.
[13:41:55.791] <TB2> INFO: 655360 events read in total (14474ms).
[13:41:55.857] <TB2> INFO: Expecting 655360 events.
[13:42:10.633] <TB2> INFO: 655360 events read in total (14373ms).
[13:42:10.699] <TB2> INFO: Expecting 655360 events.
[13:42:25.379] <TB2> INFO: 655360 events read in total (14277ms).
[13:42:25.457] <TB2> INFO: Expecting 655360 events.
[13:42:40.165] <TB2> INFO: 655360 events read in total (14305ms).
[13:42:40.380] <TB2> INFO: Expecting 655360 events.
[13:42:55.022] <TB2> INFO: 655360 events read in total (14238ms).
[13:42:55.291] <TB2> INFO: Expecting 655360 events.
[13:43:10.125] <TB2> INFO: 655360 events read in total (14431ms).
[13:43:10.410] <TB2> INFO: Expecting 655360 events.
[13:43:25.098] <TB2> INFO: 655360 events read in total (14285ms).
[13:43:25.197] <TB2> INFO: Test took 237997ms.
[13:43:25.292] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:43:25.551] <TB2> INFO: Expecting 655360 events.
[13:43:40.344] <TB2> INFO: 655360 events read in total (14202ms).
[13:43:40.355] <TB2> INFO: Expecting 655360 events.
[13:43:54.872] <TB2> INFO: 655360 events read in total (14114ms).
[13:43:54.888] <TB2> INFO: Expecting 655360 events.
[13:44:09.114] <TB2> INFO: 655360 events read in total (13823ms).
[13:44:09.134] <TB2> INFO: Expecting 655360 events.
[13:44:23.703] <TB2> INFO: 655360 events read in total (14165ms).
[13:44:23.727] <TB2> INFO: Expecting 655360 events.
[13:44:38.501] <TB2> INFO: 655360 events read in total (14371ms).
[13:44:38.529] <TB2> INFO: Expecting 655360 events.
[13:44:53.386] <TB2> INFO: 655360 events read in total (14454ms).
[13:44:53.421] <TB2> INFO: Expecting 655360 events.
[13:45:08.269] <TB2> INFO: 655360 events read in total (14445ms).
[13:45:08.319] <TB2> INFO: Expecting 655360 events.
[13:45:23.065] <TB2> INFO: 655360 events read in total (14343ms).
[13:45:23.119] <TB2> INFO: Expecting 655360 events.
[13:45:37.604] <TB2> INFO: 655360 events read in total (14082ms).
[13:45:37.652] <TB2> INFO: Expecting 655360 events.
[13:45:52.303] <TB2> INFO: 655360 events read in total (14248ms).
[13:45:52.504] <TB2> INFO: Expecting 655360 events.
[13:46:07.177] <TB2> INFO: 655360 events read in total (14270ms).
[13:46:07.243] <TB2> INFO: Expecting 655360 events.
[13:46:21.844] <TB2> INFO: 655360 events read in total (14198ms).
[13:46:21.943] <TB2> INFO: Expecting 655360 events.
[13:46:36.722] <TB2> INFO: 655360 events read in total (14376ms).
[13:46:36.927] <TB2> INFO: Expecting 655360 events.
[13:46:51.395] <TB2> INFO: 655360 events read in total (14065ms).
[13:46:51.610] <TB2> INFO: Expecting 655360 events.
[13:47:05.910] <TB2> INFO: 655360 events read in total (13897ms).
[13:47:06.205] <TB2> INFO: Expecting 655360 events.
[13:47:20.379] <TB2> INFO: 655360 events read in total (13771ms).
[13:47:20.476] <TB2> INFO: Test took 235184ms.
[13:47:20.659] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:47:20.667] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:47:20.675] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:47:20.682] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:47:20.688] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:47:20.694] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[13:47:20.700] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[13:47:20.706] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[13:47:20.712] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:47:20.718] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:47:20.724] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:47:20.730] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:47:20.736] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:47:20.742] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:47:20.749] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:47:20.755] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:47:20.762] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:47:20.768] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:47:20.775] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:47:20.782] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:47:20.788] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:47:20.794] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[13:47:20.801] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:47:20.807] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:47:20.813] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:47:20.820] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:47:20.826] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:47:20.833] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:47:20.839] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:47:20.845] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:47:20.851] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:47:20.858] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:47:20.864] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:47:20.870] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:47:20.877] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:47:20.883] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[13:47:20.889] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[13:47:20.896] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[13:47:20.902] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[13:47:20.908] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[13:47:20.915] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:47:20.923] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:47:20.931] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:47:20.938] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:47:20.945] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:47:20.951] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:47:20.985] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C0.dat
[13:47:20.985] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C1.dat
[13:47:20.985] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C2.dat
[13:47:20.985] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C3.dat
[13:47:20.985] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C4.dat
[13:47:20.985] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C5.dat
[13:47:20.985] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C6.dat
[13:47:20.985] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C7.dat
[13:47:20.985] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C8.dat
[13:47:20.985] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C9.dat
[13:47:20.985] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C10.dat
[13:47:20.986] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C11.dat
[13:47:20.986] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C12.dat
[13:47:20.986] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C13.dat
[13:47:20.986] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C14.dat
[13:47:20.986] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C15.dat
[13:47:21.228] <TB2> INFO: Expecting 41600 events.
[13:47:24.354] <TB2> INFO: 41600 events read in total (2534ms).
[13:47:24.354] <TB2> INFO: Test took 3365ms.
[13:47:24.802] <TB2> INFO: Expecting 41600 events.
[13:47:27.815] <TB2> INFO: 41600 events read in total (2422ms).
[13:47:27.817] <TB2> INFO: Test took 3253ms.
[13:47:28.341] <TB2> INFO: Expecting 41600 events.
[13:47:31.434] <TB2> INFO: 41600 events read in total (2501ms).
[13:47:31.435] <TB2> INFO: Test took 3405ms.
[13:47:31.653] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:31.742] <TB2> INFO: Expecting 2560 events.
[13:47:32.628] <TB2> INFO: 2560 events read in total (294ms).
[13:47:32.628] <TB2> INFO: Test took 975ms.
[13:47:32.631] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:32.936] <TB2> INFO: Expecting 2560 events.
[13:47:33.822] <TB2> INFO: 2560 events read in total (295ms).
[13:47:33.822] <TB2> INFO: Test took 1192ms.
[13:47:33.824] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:34.130] <TB2> INFO: Expecting 2560 events.
[13:47:35.019] <TB2> INFO: 2560 events read in total (297ms).
[13:47:35.019] <TB2> INFO: Test took 1195ms.
[13:47:35.021] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:35.327] <TB2> INFO: Expecting 2560 events.
[13:47:36.210] <TB2> INFO: 2560 events read in total (291ms).
[13:47:36.211] <TB2> INFO: Test took 1190ms.
[13:47:36.214] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:36.519] <TB2> INFO: Expecting 2560 events.
[13:47:37.407] <TB2> INFO: 2560 events read in total (297ms).
[13:47:37.407] <TB2> INFO: Test took 1193ms.
[13:47:37.409] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:37.715] <TB2> INFO: Expecting 2560 events.
[13:47:38.599] <TB2> INFO: 2560 events read in total (292ms).
[13:47:38.599] <TB2> INFO: Test took 1190ms.
[13:47:38.602] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:38.907] <TB2> INFO: Expecting 2560 events.
[13:47:39.790] <TB2> INFO: 2560 events read in total (291ms).
[13:47:39.790] <TB2> INFO: Test took 1188ms.
[13:47:39.792] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:40.099] <TB2> INFO: Expecting 2560 events.
[13:47:40.982] <TB2> INFO: 2560 events read in total (292ms).
[13:47:40.982] <TB2> INFO: Test took 1190ms.
[13:47:40.985] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:41.290] <TB2> INFO: Expecting 2560 events.
[13:47:42.167] <TB2> INFO: 2560 events read in total (285ms).
[13:47:42.168] <TB2> INFO: Test took 1183ms.
[13:47:42.170] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:42.476] <TB2> INFO: Expecting 2560 events.
[13:47:43.356] <TB2> INFO: 2560 events read in total (288ms).
[13:47:43.356] <TB2> INFO: Test took 1186ms.
[13:47:43.358] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:43.664] <TB2> INFO: Expecting 2560 events.
[13:47:44.548] <TB2> INFO: 2560 events read in total (292ms).
[13:47:44.548] <TB2> INFO: Test took 1190ms.
[13:47:44.552] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:44.856] <TB2> INFO: Expecting 2560 events.
[13:47:45.747] <TB2> INFO: 2560 events read in total (299ms).
[13:47:45.747] <TB2> INFO: Test took 1196ms.
[13:47:45.750] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:46.055] <TB2> INFO: Expecting 2560 events.
[13:47:46.937] <TB2> INFO: 2560 events read in total (290ms).
[13:47:46.937] <TB2> INFO: Test took 1187ms.
[13:47:46.939] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:47.245] <TB2> INFO: Expecting 2560 events.
[13:47:48.135] <TB2> INFO: 2560 events read in total (298ms).
[13:47:48.135] <TB2> INFO: Test took 1196ms.
[13:47:48.139] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:48.443] <TB2> INFO: Expecting 2560 events.
[13:47:49.327] <TB2> INFO: 2560 events read in total (292ms).
[13:47:49.327] <TB2> INFO: Test took 1188ms.
[13:47:49.329] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:49.635] <TB2> INFO: Expecting 2560 events.
[13:47:50.513] <TB2> INFO: 2560 events read in total (286ms).
[13:47:50.513] <TB2> INFO: Test took 1184ms.
[13:47:50.516] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:50.822] <TB2> INFO: Expecting 2560 events.
[13:47:51.702] <TB2> INFO: 2560 events read in total (289ms).
[13:47:51.702] <TB2> INFO: Test took 1186ms.
[13:47:51.705] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:52.011] <TB2> INFO: Expecting 2560 events.
[13:47:52.894] <TB2> INFO: 2560 events read in total (292ms).
[13:47:52.895] <TB2> INFO: Test took 1190ms.
[13:47:52.898] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:53.203] <TB2> INFO: Expecting 2560 events.
[13:47:54.086] <TB2> INFO: 2560 events read in total (292ms).
[13:47:54.086] <TB2> INFO: Test took 1188ms.
[13:47:54.089] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:54.394] <TB2> INFO: Expecting 2560 events.
[13:47:55.285] <TB2> INFO: 2560 events read in total (299ms).
[13:47:55.285] <TB2> INFO: Test took 1197ms.
[13:47:55.288] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:55.593] <TB2> INFO: Expecting 2560 events.
[13:47:56.477] <TB2> INFO: 2560 events read in total (292ms).
[13:47:56.477] <TB2> INFO: Test took 1190ms.
[13:47:56.480] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:56.786] <TB2> INFO: Expecting 2560 events.
[13:47:57.671] <TB2> INFO: 2560 events read in total (294ms).
[13:47:57.671] <TB2> INFO: Test took 1191ms.
[13:47:57.675] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:57.979] <TB2> INFO: Expecting 2560 events.
[13:47:58.869] <TB2> INFO: 2560 events read in total (299ms).
[13:47:58.869] <TB2> INFO: Test took 1194ms.
[13:47:58.871] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:47:59.178] <TB2> INFO: Expecting 2560 events.
[13:48:00.063] <TB2> INFO: 2560 events read in total (293ms).
[13:48:00.063] <TB2> INFO: Test took 1192ms.
[13:48:00.065] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:00.371] <TB2> INFO: Expecting 2560 events.
[13:48:01.264] <TB2> INFO: 2560 events read in total (301ms).
[13:48:01.264] <TB2> INFO: Test took 1199ms.
[13:48:01.266] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:01.573] <TB2> INFO: Expecting 2560 events.
[13:48:02.459] <TB2> INFO: 2560 events read in total (294ms).
[13:48:02.460] <TB2> INFO: Test took 1194ms.
[13:48:02.462] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:02.768] <TB2> INFO: Expecting 2560 events.
[13:48:03.657] <TB2> INFO: 2560 events read in total (297ms).
[13:48:03.658] <TB2> INFO: Test took 1196ms.
[13:48:03.661] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:03.966] <TB2> INFO: Expecting 2560 events.
[13:48:04.851] <TB2> INFO: 2560 events read in total (293ms).
[13:48:04.851] <TB2> INFO: Test took 1190ms.
[13:48:04.854] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:05.160] <TB2> INFO: Expecting 2560 events.
[13:48:06.048] <TB2> INFO: 2560 events read in total (297ms).
[13:48:06.049] <TB2> INFO: Test took 1195ms.
[13:48:06.052] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:06.357] <TB2> INFO: Expecting 2560 events.
[13:48:07.244] <TB2> INFO: 2560 events read in total (295ms).
[13:48:07.245] <TB2> INFO: Test took 1193ms.
[13:48:07.248] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:07.552] <TB2> INFO: Expecting 2560 events.
[13:48:08.443] <TB2> INFO: 2560 events read in total (300ms).
[13:48:08.443] <TB2> INFO: Test took 1196ms.
[13:48:08.447] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:08.752] <TB2> INFO: Expecting 2560 events.
[13:48:09.640] <TB2> INFO: 2560 events read in total (296ms).
[13:48:09.640] <TB2> INFO: Test took 1193ms.
[13:48:10.108] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 649 seconds
[13:48:10.108] <TB2> INFO: PH scale (per ROC): 48 59 54 44 46 46 35 60 65 63 65 55 64 55 39 41
[13:48:10.108] <TB2> INFO: PH offset (per ROC): 112 134 129 105 109 82 97 121 126 129 112 144 122 128 115 92
[13:48:10.117] <TB2> INFO: Decoding statistics:
[13:48:10.117] <TB2> INFO: General information:
[13:48:10.117] <TB2> INFO: 16bit words read: 127884
[13:48:10.117] <TB2> INFO: valid events total: 20480
[13:48:10.117] <TB2> INFO: empty events: 17978
[13:48:10.117] <TB2> INFO: valid events with pixels: 2502
[13:48:10.117] <TB2> INFO: valid pixel hits: 2502
[13:48:10.117] <TB2> INFO: Event errors: 0
[13:48:10.117] <TB2> INFO: start marker: 0
[13:48:10.117] <TB2> INFO: stop marker: 0
[13:48:10.117] <TB2> INFO: overflow: 0
[13:48:10.117] <TB2> INFO: invalid 5bit words: 0
[13:48:10.117] <TB2> INFO: invalid XOR eye diagram: 0
[13:48:10.117] <TB2> INFO: frame (failed synchr.): 0
[13:48:10.117] <TB2> INFO: idle data (no TBM trl): 0
[13:48:10.117] <TB2> INFO: no data (only TBM hdr): 0
[13:48:10.117] <TB2> INFO: TBM errors: 0
[13:48:10.117] <TB2> INFO: flawed TBM headers: 0
[13:48:10.117] <TB2> INFO: flawed TBM trailers: 0
[13:48:10.117] <TB2> INFO: event ID mismatches: 0
[13:48:10.117] <TB2> INFO: ROC errors: 0
[13:48:10.117] <TB2> INFO: missing ROC header(s): 0
[13:48:10.117] <TB2> INFO: misplaced readback start: 0
[13:48:10.117] <TB2> INFO: Pixel decoding errors: 0
[13:48:10.117] <TB2> INFO: pixel data incomplete: 0
[13:48:10.117] <TB2> INFO: pixel address: 0
[13:48:10.117] <TB2> INFO: pulse height fill bit: 0
[13:48:10.117] <TB2> INFO: buffer corruption: 0
[13:48:10.276] <TB2> INFO: ######################################################################
[13:48:10.276] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:48:10.276] <TB2> INFO: ######################################################################
[13:48:10.292] <TB2> INFO: scanning low vcal = 10
[13:48:10.528] <TB2> INFO: Expecting 41600 events.
[13:48:14.123] <TB2> INFO: 41600 events read in total (3003ms).
[13:48:14.123] <TB2> INFO: Test took 3831ms.
[13:48:14.124] <TB2> INFO: scanning low vcal = 20
[13:48:14.420] <TB2> INFO: Expecting 41600 events.
[13:48:18.009] <TB2> INFO: 41600 events read in total (2997ms).
[13:48:18.010] <TB2> INFO: Test took 3885ms.
[13:48:18.011] <TB2> INFO: scanning low vcal = 30
[13:48:18.307] <TB2> INFO: Expecting 41600 events.
[13:48:21.966] <TB2> INFO: 41600 events read in total (3067ms).
[13:48:21.967] <TB2> INFO: Test took 3956ms.
[13:48:21.970] <TB2> INFO: scanning low vcal = 40
[13:48:22.246] <TB2> INFO: Expecting 41600 events.
[13:48:26.245] <TB2> INFO: 41600 events read in total (3408ms).
[13:48:26.246] <TB2> INFO: Test took 4276ms.
[13:48:26.249] <TB2> INFO: scanning low vcal = 50
[13:48:26.526] <TB2> INFO: Expecting 41600 events.
[13:48:30.518] <TB2> INFO: 41600 events read in total (3400ms).
[13:48:30.518] <TB2> INFO: Test took 4269ms.
[13:48:30.522] <TB2> INFO: scanning low vcal = 60
[13:48:30.798] <TB2> INFO: Expecting 41600 events.
[13:48:34.862] <TB2> INFO: 41600 events read in total (3472ms).
[13:48:34.863] <TB2> INFO: Test took 4341ms.
[13:48:34.866] <TB2> INFO: scanning low vcal = 70
[13:48:35.142] <TB2> INFO: Expecting 41600 events.
[13:48:39.199] <TB2> INFO: 41600 events read in total (3465ms).
[13:48:39.199] <TB2> INFO: Test took 4333ms.
[13:48:39.202] <TB2> INFO: scanning low vcal = 80
[13:48:39.479] <TB2> INFO: Expecting 41600 events.
[13:48:43.467] <TB2> INFO: 41600 events read in total (3397ms).
[13:48:43.468] <TB2> INFO: Test took 4265ms.
[13:48:43.471] <TB2> INFO: scanning low vcal = 90
[13:48:43.747] <TB2> INFO: Expecting 41600 events.
[13:48:47.782] <TB2> INFO: 41600 events read in total (3443ms).
[13:48:47.783] <TB2> INFO: Test took 4312ms.
[13:48:47.787] <TB2> INFO: scanning low vcal = 100
[13:48:48.063] <TB2> INFO: Expecting 41600 events.
[13:48:52.043] <TB2> INFO: 41600 events read in total (3389ms).
[13:48:52.044] <TB2> INFO: Test took 4257ms.
[13:48:52.047] <TB2> INFO: scanning low vcal = 110
[13:48:52.323] <TB2> INFO: Expecting 41600 events.
[13:48:56.391] <TB2> INFO: 41600 events read in total (3476ms).
[13:48:56.391] <TB2> INFO: Test took 4344ms.
[13:48:56.394] <TB2> INFO: scanning low vcal = 120
[13:48:56.671] <TB2> INFO: Expecting 41600 events.
[13:49:00.702] <TB2> INFO: 41600 events read in total (3439ms).
[13:49:00.702] <TB2> INFO: Test took 4308ms.
[13:49:00.705] <TB2> INFO: scanning low vcal = 130
[13:49:00.991] <TB2> INFO: Expecting 41600 events.
[13:49:05.013] <TB2> INFO: 41600 events read in total (3431ms).
[13:49:05.014] <TB2> INFO: Test took 4308ms.
[13:49:05.018] <TB2> INFO: scanning low vcal = 140
[13:49:05.294] <TB2> INFO: Expecting 41600 events.
[13:49:09.375] <TB2> INFO: 41600 events read in total (3489ms).
[13:49:09.376] <TB2> INFO: Test took 4358ms.
[13:49:09.379] <TB2> INFO: scanning low vcal = 150
[13:49:09.656] <TB2> INFO: Expecting 41600 events.
[13:49:13.760] <TB2> INFO: 41600 events read in total (3513ms).
[13:49:13.761] <TB2> INFO: Test took 4382ms.
[13:49:13.764] <TB2> INFO: scanning low vcal = 160
[13:49:14.040] <TB2> INFO: Expecting 41600 events.
[13:49:18.054] <TB2> INFO: 41600 events read in total (3422ms).
[13:49:18.054] <TB2> INFO: Test took 4290ms.
[13:49:18.057] <TB2> INFO: scanning low vcal = 170
[13:49:18.334] <TB2> INFO: Expecting 41600 events.
[13:49:22.356] <TB2> INFO: 41600 events read in total (3430ms).
[13:49:22.357] <TB2> INFO: Test took 4300ms.
[13:49:22.361] <TB2> INFO: scanning low vcal = 180
[13:49:22.636] <TB2> INFO: Expecting 41600 events.
[13:49:26.641] <TB2> INFO: 41600 events read in total (3413ms).
[13:49:26.642] <TB2> INFO: Test took 4280ms.
[13:49:26.644] <TB2> INFO: scanning low vcal = 190
[13:49:26.922] <TB2> INFO: Expecting 41600 events.
[13:49:30.936] <TB2> INFO: 41600 events read in total (3423ms).
[13:49:30.936] <TB2> INFO: Test took 4292ms.
[13:49:30.940] <TB2> INFO: scanning low vcal = 200
[13:49:31.216] <TB2> INFO: Expecting 41600 events.
[13:49:35.249] <TB2> INFO: 41600 events read in total (3441ms).
[13:49:35.250] <TB2> INFO: Test took 4310ms.
[13:49:35.253] <TB2> INFO: scanning low vcal = 210
[13:49:35.529] <TB2> INFO: Expecting 41600 events.
[13:49:39.520] <TB2> INFO: 41600 events read in total (3399ms).
[13:49:39.521] <TB2> INFO: Test took 4268ms.
[13:49:39.525] <TB2> INFO: scanning low vcal = 220
[13:49:39.803] <TB2> INFO: Expecting 41600 events.
[13:49:43.817] <TB2> INFO: 41600 events read in total (3423ms).
[13:49:43.818] <TB2> INFO: Test took 4293ms.
[13:49:43.821] <TB2> INFO: scanning low vcal = 230
[13:49:44.098] <TB2> INFO: Expecting 41600 events.
[13:49:48.095] <TB2> INFO: 41600 events read in total (3405ms).
[13:49:48.096] <TB2> INFO: Test took 4274ms.
[13:49:48.099] <TB2> INFO: scanning low vcal = 240
[13:49:48.376] <TB2> INFO: Expecting 41600 events.
[13:49:55.159] <TB2> INFO: 41600 events read in total (6192ms).
[13:49:55.164] <TB2> INFO: Test took 7065ms.
[13:49:55.287] <TB2> INFO: scanning low vcal = 250
[13:49:55.823] <TB2> INFO: Expecting 41600 events.
[13:50:00.424] <TB2> INFO: 41600 events read in total (3945ms).
[13:50:00.429] <TB2> INFO: Test took 5138ms.
[13:50:00.435] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[13:50:00.766] <TB2> INFO: Expecting 41600 events.
[13:50:08.975] <TB2> INFO: 41600 events read in total (7592ms).
[13:50:08.991] <TB2> INFO: Test took 8556ms.
[13:50:09.095] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[13:50:09.600] <TB2> INFO: Expecting 41600 events.
[13:50:24.385] <TB2> INFO: 41600 events read in total (14106ms).
[13:50:24.386] <TB2> INFO: Test took 15283ms.
[13:50:24.390] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[13:50:24.667] <TB2> INFO: Expecting 41600 events.
[13:50:45.258] <TB2> INFO: 41600 events read in total (20000ms).
[13:50:45.272] <TB2> INFO: Test took 20882ms.
[13:50:45.391] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[13:50:46.227] <TB2> INFO: Expecting 41600 events.
[13:50:50.448] <TB2> INFO: 41600 events read in total (3501ms).
[13:50:50.449] <TB2> INFO: Test took 5056ms.
[13:50:50.453] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:50:50.780] <TB2> INFO: Expecting 41600 events.
[13:50:54.779] <TB2> INFO: 41600 events read in total (3407ms).
[13:50:54.780] <TB2> INFO: Test took 4327ms.
[13:50:55.235] <TB2> INFO: PixTestGainPedestal::measure() done
[13:51:55.765] <TB2> INFO: PixTestGainPedestal::fit() done
[13:51:55.765] <TB2> INFO: non-linearity mean: 0.929 0.984 0.976 0.931 0.930 0.952 1.056 0.985 0.986 0.985 0.985 0.979 0.984 0.977 0.966 1.013
[13:51:55.765] <TB2> INFO: non-linearity RMS: 0.062 0.003 0.005 0.132 0.084 0.146 0.182 0.003 0.002 0.003 0.003 0.004 0.002 0.004 0.171 0.165
[13:51:55.765] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[13:51:55.780] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[13:51:55.795] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[13:51:55.809] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[13:51:55.824] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[13:51:55.839] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[13:51:55.858] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[13:51:55.879] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[13:51:55.900] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[13:51:55.921] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[13:51:55.935] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[13:51:55.949] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[13:51:55.964] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[13:51:55.978] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[13:51:55.991] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[13:51:56.005] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1054_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[13:51:56.020] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 225 seconds
[13:51:56.020] <TB2> INFO: Decoding statistics:
[13:51:56.020] <TB2> INFO: General information:
[13:51:56.020] <TB2> INFO: 16bit words read: 3327686
[13:51:56.020] <TB2> INFO: valid events total: 332800
[13:51:56.020] <TB2> INFO: empty events: 0
[13:51:56.020] <TB2> INFO: valid events with pixels: 332800
[13:51:56.020] <TB2> INFO: valid pixel hits: 665443
[13:51:56.020] <TB2> INFO: Event errors: 0
[13:51:56.020] <TB2> INFO: start marker: 0
[13:51:56.020] <TB2> INFO: stop marker: 0
[13:51:56.020] <TB2> INFO: overflow: 0
[13:51:56.020] <TB2> INFO: invalid 5bit words: 0
[13:51:56.020] <TB2> INFO: invalid XOR eye diagram: 0
[13:51:56.020] <TB2> INFO: frame (failed synchr.): 0
[13:51:56.020] <TB2> INFO: idle data (no TBM trl): 0
[13:51:56.020] <TB2> INFO: no data (only TBM hdr): 0
[13:51:56.020] <TB2> INFO: TBM errors: 0
[13:51:56.020] <TB2> INFO: flawed TBM headers: 0
[13:51:56.020] <TB2> INFO: flawed TBM trailers: 0
[13:51:56.020] <TB2> INFO: event ID mismatches: 0
[13:51:56.020] <TB2> INFO: ROC errors: 0
[13:51:56.020] <TB2> INFO: missing ROC header(s): 0
[13:51:56.020] <TB2> INFO: misplaced readback start: 0
[13:51:56.020] <TB2> INFO: Pixel decoding errors: 0
[13:51:56.020] <TB2> INFO: pixel data incomplete: 0
[13:51:56.020] <TB2> INFO: pixel address: 0
[13:51:56.020] <TB2> INFO: pulse height fill bit: 0
[13:51:56.020] <TB2> INFO: buffer corruption: 0
[13:51:56.036] <TB2> INFO: Decoding statistics:
[13:51:56.036] <TB2> INFO: General information:
[13:51:56.036] <TB2> INFO: 16bit words read: 3457106
[13:51:56.036] <TB2> INFO: valid events total: 353536
[13:51:56.036] <TB2> INFO: empty events: 18234
[13:51:56.036] <TB2> INFO: valid events with pixels: 335302
[13:51:56.036] <TB2> INFO: valid pixel hits: 667945
[13:51:56.036] <TB2> INFO: Event errors: 0
[13:51:56.036] <TB2> INFO: start marker: 0
[13:51:56.036] <TB2> INFO: stop marker: 0
[13:51:56.036] <TB2> INFO: overflow: 0
[13:51:56.036] <TB2> INFO: invalid 5bit words: 0
[13:51:56.036] <TB2> INFO: invalid XOR eye diagram: 0
[13:51:56.036] <TB2> INFO: frame (failed synchr.): 0
[13:51:56.036] <TB2> INFO: idle data (no TBM trl): 0
[13:51:56.036] <TB2> INFO: no data (only TBM hdr): 0
[13:51:56.036] <TB2> INFO: TBM errors: 0
[13:51:56.036] <TB2> INFO: flawed TBM headers: 0
[13:51:56.036] <TB2> INFO: flawed TBM trailers: 0
[13:51:56.036] <TB2> INFO: event ID mismatches: 0
[13:51:56.036] <TB2> INFO: ROC errors: 0
[13:51:56.036] <TB2> INFO: missing ROC header(s): 0
[13:51:56.036] <TB2> INFO: misplaced readback start: 0
[13:51:56.036] <TB2> INFO: Pixel decoding errors: 0
[13:51:56.036] <TB2> INFO: pixel data incomplete: 0
[13:51:56.036] <TB2> INFO: pixel address: 0
[13:51:56.036] <TB2> INFO: pulse height fill bit: 0
[13:51:56.036] <TB2> INFO: buffer corruption: 0
[13:51:56.036] <TB2> INFO: enter test to run
[13:51:56.036] <TB2> INFO: test: exit no parameter change
[13:51:56.159] <TB2> QUIET: Connection to board 149 closed.
[13:51:56.163] <TB2> INFO: pXar: this is the end, my friend