[14:03:43.918] <TB1> INFO: *** Welcome to pxar ***
[14:03:43.918] <TB1> INFO: *** Today: 2016/10/24
[14:03:43.927] <TB1> INFO: *** Version: c8ba-dirty
[14:03:43.927] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C15.dat
[14:03:43.927] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//tbmParameters_C1b.dat
[14:03:43.927] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//defaultMaskFile.dat
[14:03:43.927] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters_C15.dat
[14:03:43.989] <TB1> INFO: clk: 4
[14:03:43.989] <TB1> INFO: ctr: 4
[14:03:43.989] <TB1> INFO: sda: 19
[14:03:43.989] <TB1> INFO: tin: 9
[14:03:43.989] <TB1> INFO: level: 15
[14:03:43.989] <TB1> INFO: triggerdelay: 0
[14:03:43.989] <TB1> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[14:03:43.989] <TB1> INFO: Log level: INFO
[14:03:43.998] <TB1> INFO: Found DTB DTB_WXC03A
[14:03:44.009] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[14:03:44.011] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
------------------------------------------------------
[14:03:44.013] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[14:03:45.573] <TB1> INFO: DUT info:
[14:03:45.574] <TB1> INFO: The DUT currently contains the following objects:
[14:03:45.574] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[14:03:45.574] <TB1> INFO: TBM Core alpha (0): 7 registers set
[14:03:45.574] <TB1> INFO: TBM Core beta (1): 7 registers set
[14:03:45.574] <TB1> INFO: TBM Core alpha (2): 7 registers set
[14:03:45.574] <TB1> INFO: TBM Core beta (3): 7 registers set
[14:03:45.574] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[14:03:45.574] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:45.574] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:45.574] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:45.574] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:45.574] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:45.574] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:45.574] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:45.574] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:45.574] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:45.574] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:45.574] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:45.574] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:45.574] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:45.574] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:45.574] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:45.574] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[14:03:45.975] <TB1> INFO: enter 'restricted' command line mode
[14:03:45.975] <TB1> INFO: enter test to run
[14:03:45.975] <TB1> INFO: test: pretest no parameter change
[14:03:45.975] <TB1> INFO: running: pretest
[14:03:45.980] <TB1> INFO: ######################################################################
[14:03:45.980] <TB1> INFO: PixTestPretest::doTest()
[14:03:45.980] <TB1> INFO: ######################################################################
[14:03:45.981] <TB1> INFO: ----------------------------------------------------------------------
[14:03:45.981] <TB1> INFO: PixTestPretest::programROC()
[14:03:45.981] <TB1> INFO: ----------------------------------------------------------------------
[14:04:03.995] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[14:04:03.995] <TB1> INFO: IA differences per ROC: 20.9 17.7 18.5 17.7 19.3 20.1 20.1 20.1 18.5 18.5 20.1 16.9 20.1 17.7 19.3 17.7
[14:04:04.057] <TB1> INFO: ----------------------------------------------------------------------
[14:04:04.057] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[14:04:04.057] <TB1> INFO: ----------------------------------------------------------------------
[14:04:25.358] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 380.2 mA = 23.7625 mA/ROC
[14:04:25.358] <TB1> INFO: i(loss) [mA/ROC]: 18.4 20.1 18.4 19.3 19.3 18.4 18.4 19.3 19.3 19.3 18.4 19.3 18.4 18.4 18.4 17.6
[14:04:25.393] <TB1> INFO: ----------------------------------------------------------------------
[14:04:25.393] <TB1> INFO: PixTestPretest::findTiming()
[14:04:25.393] <TB1> INFO: ----------------------------------------------------------------------
[14:04:25.393] <TB1> INFO: PixTestCmd::init()

[14:04:57.781] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[14:04:57.781] <TB1> INFO: (success/tries = 100/100), width = 4
[14:04:59.293] <TB1> INFO: ----------------------------------------------------------------------
[14:04:59.293] <TB1> INFO: PixTestPretest::findWorkingPixel()
[14:04:59.293] <TB1> INFO: ----------------------------------------------------------------------
[14:04:59.386] <TB1> INFO: Expecting 231680 events.
[14:05:09.251] <TB1> INFO: 231680 events read in total (9274ms).
[14:05:09.262] <TB1> INFO: Test took 9966ms.
[14:05:09.509] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[14:05:09.539] <TB1> INFO: ----------------------------------------------------------------------
[14:05:09.539] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[14:05:09.539] <TB1> INFO: ----------------------------------------------------------------------
[14:05:09.633] <TB1> INFO: Expecting 231680 events.
[14:05:19.481] <TB1> INFO: 231680 events read in total (9256ms).
[14:05:19.495] <TB1> INFO: Test took 9951ms.
[14:05:19.766] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[14:05:19.766] <TB1> INFO: CalDel: 78 86 93 121 89 82 112 95 98 100 95 78 87 87 77 95
[14:05:19.766] <TB1> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 52 51 51 51 51
[14:05:19.770] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C0.dat
[14:05:19.771] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C1.dat
[14:05:19.771] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C2.dat
[14:05:19.771] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C3.dat
[14:05:19.771] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C4.dat
[14:05:19.771] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C5.dat
[14:05:19.771] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C6.dat
[14:05:19.772] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C7.dat
[14:05:19.772] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C8.dat
[14:05:19.772] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C9.dat
[14:05:19.772] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C10.dat
[14:05:19.772] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C11.dat
[14:05:19.772] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C12.dat
[14:05:19.772] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C13.dat
[14:05:19.772] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C14.dat
[14:05:19.773] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters_C15.dat
[14:05:19.773] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//tbmParameters_C0a.dat
[14:05:19.773] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//tbmParameters_C0b.dat
[14:05:19.773] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//tbmParameters_C1a.dat
[14:05:19.773] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//tbmParameters_C1b.dat
[14:05:19.773] <TB1> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[14:05:19.827] <TB1> INFO: enter test to run
[14:05:19.827] <TB1> INFO: test: FullTest no parameter change
[14:05:19.827] <TB1> INFO: running: fulltest
[14:05:19.827] <TB1> INFO: ######################################################################
[14:05:19.827] <TB1> INFO: PixTestFullTest::doTest()
[14:05:19.827] <TB1> INFO: ######################################################################
[14:05:19.829] <TB1> INFO: ######################################################################
[14:05:19.829] <TB1> INFO: PixTestAlive::doTest()
[14:05:19.829] <TB1> INFO: ######################################################################
[14:05:19.830] <TB1> INFO: ----------------------------------------------------------------------
[14:05:19.830] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:05:19.830] <TB1> INFO: ----------------------------------------------------------------------
[14:05:20.069] <TB1> INFO: Expecting 41600 events.
[14:05:23.695] <TB1> INFO: 41600 events read in total (3034ms).
[14:05:23.696] <TB1> INFO: Test took 3865ms.
[14:05:23.930] <TB1> INFO: PixTestAlive::aliveTest() done
[14:05:23.931] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:05:23.932] <TB1> INFO: ----------------------------------------------------------------------
[14:05:23.932] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:05:23.932] <TB1> INFO: ----------------------------------------------------------------------
[14:05:24.177] <TB1> INFO: Expecting 41600 events.
[14:05:27.133] <TB1> INFO: 41600 events read in total (2364ms).
[14:05:27.134] <TB1> INFO: Test took 3200ms.
[14:05:27.134] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[14:05:27.366] <TB1> INFO: PixTestAlive::maskTest() done
[14:05:27.366] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:05:27.367] <TB1> INFO: ----------------------------------------------------------------------
[14:05:27.367] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[14:05:27.367] <TB1> INFO: ----------------------------------------------------------------------
[14:05:27.607] <TB1> INFO: Expecting 41600 events.
[14:05:31.150] <TB1> INFO: 41600 events read in total (2951ms).
[14:05:31.150] <TB1> INFO: Test took 3781ms.
[14:05:31.383] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[14:05:31.383] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[14:05:31.383] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[14:05:31.384] <TB1> INFO: Decoding statistics:
[14:05:31.384] <TB1> INFO: General information:
[14:05:31.384] <TB1> INFO: 16bit words read: 0
[14:05:31.384] <TB1> INFO: valid events total: 0
[14:05:31.384] <TB1> INFO: empty events: 0
[14:05:31.384] <TB1> INFO: valid events with pixels: 0
[14:05:31.384] <TB1> INFO: valid pixel hits: 0
[14:05:31.384] <TB1> INFO: Event errors: 0
[14:05:31.384] <TB1> INFO: start marker: 0
[14:05:31.384] <TB1> INFO: stop marker: 0
[14:05:31.384] <TB1> INFO: overflow: 0
[14:05:31.384] <TB1> INFO: invalid 5bit words: 0
[14:05:31.384] <TB1> INFO: invalid XOR eye diagram: 0
[14:05:31.384] <TB1> INFO: frame (failed synchr.): 0
[14:05:31.384] <TB1> INFO: idle data (no TBM trl): 0
[14:05:31.384] <TB1> INFO: no data (only TBM hdr): 0
[14:05:31.384] <TB1> INFO: TBM errors: 0
[14:05:31.384] <TB1> INFO: flawed TBM headers: 0
[14:05:31.384] <TB1> INFO: flawed TBM trailers: 0
[14:05:31.384] <TB1> INFO: event ID mismatches: 0
[14:05:31.384] <TB1> INFO: ROC errors: 0
[14:05:31.384] <TB1> INFO: missing ROC header(s): 0
[14:05:31.384] <TB1> INFO: misplaced readback start: 0
[14:05:31.384] <TB1> INFO: Pixel decoding errors: 0
[14:05:31.384] <TB1> INFO: pixel data incomplete: 0
[14:05:31.384] <TB1> INFO: pixel address: 0
[14:05:31.384] <TB1> INFO: pulse height fill bit: 0
[14:05:31.384] <TB1> INFO: buffer corruption: 0
[14:05:31.392] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C15.dat
[14:05:31.393] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr_C15.dat

[14:05:31.393] <TB1> INFO: ######################################################################
[14:05:31.393] <TB1> INFO: PixTestReadback::doTest()
[14:05:31.393] <TB1> INFO: ######################################################################
[14:05:31.393] <TB1> INFO: ----------------------------------------------------------------------
[14:05:31.393] <TB1> INFO: PixTestReadback::CalibrateVd()
[14:05:31.393] <TB1> INFO: ----------------------------------------------------------------------
[14:05:41.344] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C0.dat
[14:05:41.344] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C1.dat
[14:05:41.344] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C2.dat
[14:05:41.345] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C3.dat
[14:05:41.345] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C4.dat
[14:05:41.345] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C5.dat
[14:05:41.345] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C6.dat
[14:05:41.345] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C7.dat
[14:05:41.345] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C8.dat
[14:05:41.345] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C9.dat
[14:05:41.345] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C10.dat
[14:05:41.345] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C11.dat
[14:05:41.345] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C12.dat
[14:05:41.345] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C13.dat
[14:05:41.346] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C14.dat
[14:05:41.346] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C15.dat
[14:05:41.375] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[14:05:41.375] <TB1> INFO: ----------------------------------------------------------------------
[14:05:41.375] <TB1> INFO: PixTestReadback::CalibrateVa()
[14:05:41.375] <TB1> INFO: ----------------------------------------------------------------------
[14:05:51.296] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C0.dat
[14:05:51.297] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C1.dat
[14:05:51.297] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C2.dat
[14:05:51.297] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C3.dat
[14:05:51.297] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C4.dat
[14:05:51.297] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C5.dat
[14:05:51.297] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C6.dat
[14:05:51.297] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C7.dat
[14:05:51.297] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C8.dat
[14:05:51.297] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C9.dat
[14:05:51.297] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C10.dat
[14:05:51.297] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C11.dat
[14:05:51.297] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C12.dat
[14:05:51.297] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C13.dat
[14:05:51.297] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C14.dat
[14:05:51.297] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C15.dat
[14:05:51.328] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[14:05:51.328] <TB1> INFO: ----------------------------------------------------------------------
[14:05:51.328] <TB1> INFO: PixTestReadback::readbackVbg()
[14:05:51.328] <TB1> INFO: ----------------------------------------------------------------------
[14:05:58.998] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[14:05:58.998] <TB1> INFO: ----------------------------------------------------------------------
[14:05:58.998] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[14:05:58.998] <TB1> INFO: ----------------------------------------------------------------------
[14:05:58.998] <TB1> INFO: Vbg will be calibrated using Vd calibration
[14:05:58.998] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 149.9calibrated Vbg = 1.19377 :::*/*/*/*/
[14:05:58.998] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 162calibrated Vbg = 1.19213 :::*/*/*/*/
[14:05:58.998] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 152calibrated Vbg = 1.19147 :::*/*/*/*/
[14:05:58.998] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 160.5calibrated Vbg = 1.19642 :::*/*/*/*/
[14:05:58.998] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 161.2calibrated Vbg = 1.19173 :::*/*/*/*/
[14:05:58.998] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 152.8calibrated Vbg = 1.19911 :::*/*/*/*/
[14:05:58.998] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 145.1calibrated Vbg = 1.19593 :::*/*/*/*/
[14:05:58.998] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 146.4calibrated Vbg = 1.20541 :::*/*/*/*/
[14:05:58.998] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 165.9calibrated Vbg = 1.18738 :::*/*/*/*/
[14:05:58.998] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 155.8calibrated Vbg = 1.18898 :::*/*/*/*/
[14:05:58.998] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 148.6calibrated Vbg = 1.18673 :::*/*/*/*/
[14:05:58.998] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 169.2calibrated Vbg = 1.17953 :::*/*/*/*/
[14:05:58.998] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 154calibrated Vbg = 1.19751 :::*/*/*/*/
[14:05:58.998] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 161.1calibrated Vbg = 1.19288 :::*/*/*/*/
[14:05:58.998] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 161.3calibrated Vbg = 1.1905 :::*/*/*/*/
[14:05:58.998] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 154calibrated Vbg = 1.1931 :::*/*/*/*/
[14:05:58.001] <TB1> INFO: ----------------------------------------------------------------------
[14:05:58.001] <TB1> INFO: PixTestReadback::CalibrateIa()
[14:05:58.001] <TB1> INFO: ----------------------------------------------------------------------
[14:08:39.850] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C0.dat
[14:08:39.850] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C1.dat
[14:08:39.850] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C2.dat
[14:08:39.850] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C3.dat
[14:08:39.850] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C4.dat
[14:08:39.850] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C5.dat
[14:08:39.850] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C6.dat
[14:08:39.850] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C7.dat
[14:08:39.850] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C8.dat
[14:08:39.851] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C9.dat
[14:08:39.851] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C10.dat
[14:08:39.851] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C11.dat
[14:08:39.851] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C12.dat
[14:08:39.851] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C13.dat
[14:08:39.851] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C14.dat
[14:08:39.851] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//readbackCal_C15.dat
[14:08:39.880] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[14:08:39.882] <TB1> INFO: PixTestReadback::doTest() done
[14:08:39.883] <TB1> INFO: Decoding statistics:
[14:08:39.883] <TB1> INFO: General information:
[14:08:39.883] <TB1> INFO: 16bit words read: 1536
[14:08:39.883] <TB1> INFO: valid events total: 256
[14:08:39.883] <TB1> INFO: empty events: 256
[14:08:39.883] <TB1> INFO: valid events with pixels: 0
[14:08:39.883] <TB1> INFO: valid pixel hits: 0
[14:08:39.883] <TB1> INFO: Event errors: 0
[14:08:39.883] <TB1> INFO: start marker: 0
[14:08:39.883] <TB1> INFO: stop marker: 0
[14:08:39.883] <TB1> INFO: overflow: 0
[14:08:39.883] <TB1> INFO: invalid 5bit words: 0
[14:08:39.883] <TB1> INFO: invalid XOR eye diagram: 0
[14:08:39.883] <TB1> INFO: frame (failed synchr.): 0
[14:08:39.883] <TB1> INFO: idle data (no TBM trl): 0
[14:08:39.883] <TB1> INFO: no data (only TBM hdr): 0
[14:08:39.883] <TB1> INFO: TBM errors: 0
[14:08:39.883] <TB1> INFO: flawed TBM headers: 0
[14:08:39.883] <TB1> INFO: flawed TBM trailers: 0
[14:08:39.883] <TB1> INFO: event ID mismatches: 0
[14:08:39.883] <TB1> INFO: ROC errors: 0
[14:08:39.883] <TB1> INFO: missing ROC header(s): 0
[14:08:39.883] <TB1> INFO: misplaced readback start: 0
[14:08:39.883] <TB1> INFO: Pixel decoding errors: 0
[14:08:39.883] <TB1> INFO: pixel data incomplete: 0
[14:08:39.883] <TB1> INFO: pixel address: 0
[14:08:39.883] <TB1> INFO: pulse height fill bit: 0
[14:08:39.883] <TB1> INFO: buffer corruption: 0
[14:08:39.938] <TB1> INFO: ######################################################################
[14:08:39.938] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[14:08:39.938] <TB1> INFO: ######################################################################
[14:08:39.940] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[14:08:39.959] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:08:39.959] <TB1> INFO: run 1 of 1
[14:08:40.204] <TB1> INFO: Expecting 3120000 events.
[14:09:11.288] <TB1> INFO: 673950 events read in total (30492ms).





















[14:09:41.211] <TB1> INFO: 1339885 events read in total (60415ms).











[14:10:11.215] <TB1> INFO: 2001570 events read in total (90419ms).
[14:10:41.339] <TB1> INFO: 2663205 events read in total (120543ms).











[14:11:02.450] <TB1> INFO: 3120000 events read in total (141654ms).
[14:11:02.517] <TB1> INFO: Test took 142559ms.
[14:11:30.177] <TB1> INFO: PixTestBBMap::doTest() done with 1 decoding errors: , duration: 170 seconds
[14:11:30.177] <TB1> INFO: number of dead bumps (per ROC): 0 14 2 0 1 0 0 0 0 0 1 0 6 5 6 11
[14:11:30.177] <TB1> INFO: separation cut (per ROC): 108 106 104 100 107 106 104 103 117 101 113 106 106 105 119 105
[14:11:30.177] <TB1> INFO: Decoding statistics:
[14:11:30.177] <TB1> INFO: General information:
[14:11:30.177] <TB1> INFO: 16bit words read: 0
[14:11:30.177] <TB1> INFO: valid events total: 0
[14:11:30.177] <TB1> INFO: empty events: 0
[14:11:30.177] <TB1> INFO: valid events with pixels: 0
[14:11:30.177] <TB1> INFO: valid pixel hits: 0
[14:11:30.177] <TB1> INFO: Event errors: 0
[14:11:30.177] <TB1> INFO: start marker: 0
[14:11:30.177] <TB1> INFO: stop marker: 0
[14:11:30.177] <TB1> INFO: overflow: 0
[14:11:30.177] <TB1> INFO: invalid 5bit words: 0
[14:11:30.177] <TB1> INFO: invalid XOR eye diagram: 0
[14:11:30.177] <TB1> INFO: frame (failed synchr.): 0
[14:11:30.177] <TB1> INFO: idle data (no TBM trl): 0
[14:11:30.177] <TB1> INFO: no data (only TBM hdr): 0
[14:11:30.177] <TB1> INFO: TBM errors: 0
[14:11:30.177] <TB1> INFO: flawed TBM headers: 0
[14:11:30.177] <TB1> INFO: flawed TBM trailers: 0
[14:11:30.177] <TB1> INFO: event ID mismatches: 0
[14:11:30.177] <TB1> INFO: ROC errors: 0
[14:11:30.177] <TB1> INFO: missing ROC header(s): 0
[14:11:30.177] <TB1> INFO: misplaced readback start: 0
[14:11:30.177] <TB1> INFO: Pixel decoding errors: 0
[14:11:30.177] <TB1> INFO: pixel data incomplete: 0
[14:11:30.177] <TB1> INFO: pixel address: 0
[14:11:30.177] <TB1> INFO: pulse height fill bit: 0
[14:11:30.177] <TB1> INFO: buffer corruption: 0
[14:11:30.224] <TB1> INFO: ######################################################################
[14:11:30.224] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[14:11:30.224] <TB1> INFO: ######################################################################
[14:11:30.225] <TB1> INFO: ----------------------------------------------------------------------
[14:11:30.225] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[14:11:30.225] <TB1> INFO: ----------------------------------------------------------------------
[14:11:30.225] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[14:11:30.239] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[14:11:30.239] <TB1> INFO: run 1 of 1
[14:11:30.533] <TB1> INFO: Expecting 36608000 events.
[14:11:53.740] <TB1> INFO: 683350 events read in total (22615ms).
[14:12:16.657] <TB1> INFO: 1352100 events read in total (45532ms).
[14:12:39.237] <TB1> INFO: 2021250 events read in total (68112ms).
[14:13:01.591] <TB1> INFO: 2689600 events read in total (90466ms).
[14:13:24.367] <TB1> INFO: 3357750 events read in total (113242ms).
[14:13:46.997] <TB1> INFO: 4025250 events read in total (135872ms).
[14:14:09.661] <TB1> INFO: 4691050 events read in total (158536ms).
[14:14:32.379] <TB1> INFO: 5357600 events read in total (181254ms).
[14:14:55.111] <TB1> INFO: 6024000 events read in total (203986ms).
[14:15:17.793] <TB1> INFO: 6690600 events read in total (226668ms).
[14:15:40.460] <TB1> INFO: 7355600 events read in total (249335ms).
[14:16:03.468] <TB1> INFO: 8021700 events read in total (272343ms).
[14:16:25.977] <TB1> INFO: 8686100 events read in total (294852ms).
[14:16:48.510] <TB1> INFO: 9351700 events read in total (317385ms).
[14:17:11.040] <TB1> INFO: 10014650 events read in total (339915ms).
[14:17:33.498] <TB1> INFO: 10679600 events read in total (362373ms).
[14:17:56.115] <TB1> INFO: 11341800 events read in total (384990ms).
[14:18:18.780] <TB1> INFO: 12003100 events read in total (407655ms).
[14:18:41.486] <TB1> INFO: 12663600 events read in total (430361ms).
[14:19:04.264] <TB1> INFO: 13326100 events read in total (453139ms).
[14:19:26.744] <TB1> INFO: 13987550 events read in total (475619ms).
[14:19:48.992] <TB1> INFO: 14647850 events read in total (497867ms).
[14:20:11.407] <TB1> INFO: 15307400 events read in total (520282ms).
[14:20:33.751] <TB1> INFO: 15967750 events read in total (542626ms).
[14:20:56.094] <TB1> INFO: 16627550 events read in total (564969ms).
[14:21:18.771] <TB1> INFO: 17287900 events read in total (587646ms).
[14:21:41.255] <TB1> INFO: 17947900 events read in total (610130ms).
[14:22:03.842] <TB1> INFO: 18605900 events read in total (632717ms).
[14:22:26.674] <TB1> INFO: 19262450 events read in total (655549ms).
[14:22:49.192] <TB1> INFO: 19919150 events read in total (678067ms).
[14:23:11.662] <TB1> INFO: 20574650 events read in total (700537ms).
[14:23:34.243] <TB1> INFO: 21230500 events read in total (723118ms).
[14:23:57.032] <TB1> INFO: 21886150 events read in total (745907ms).
[14:24:19.488] <TB1> INFO: 22541300 events read in total (768363ms).
[14:24:42.228] <TB1> INFO: 23195800 events read in total (791103ms).
[14:25:04.845] <TB1> INFO: 23852650 events read in total (813720ms).
[14:25:27.248] <TB1> INFO: 24508000 events read in total (836123ms).
[14:25:49.883] <TB1> INFO: 25164800 events read in total (858758ms).
[14:26:12.132] <TB1> INFO: 25820300 events read in total (881007ms).
[14:26:34.592] <TB1> INFO: 26475900 events read in total (903467ms).
[14:26:56.925] <TB1> INFO: 27130100 events read in total (925800ms).
[14:27:19.536] <TB1> INFO: 27784700 events read in total (948411ms).
[14:27:42.023] <TB1> INFO: 28439300 events read in total (970898ms).
[14:28:04.617] <TB1> INFO: 29092750 events read in total (993492ms).
[14:28:26.967] <TB1> INFO: 29746150 events read in total (1015842ms).
[14:28:49.714] <TB1> INFO: 30398800 events read in total (1038589ms).
[14:29:12.066] <TB1> INFO: 31049100 events read in total (1060941ms).
[14:29:34.742] <TB1> INFO: 31702200 events read in total (1083617ms).
[14:29:57.137] <TB1> INFO: 32354550 events read in total (1106012ms).
[14:30:19.825] <TB1> INFO: 33007900 events read in total (1128700ms).
[14:30:42.632] <TB1> INFO: 33662250 events read in total (1151507ms).
[14:31:05.161] <TB1> INFO: 34316800 events read in total (1174036ms).
[14:31:27.640] <TB1> INFO: 34969650 events read in total (1196515ms).
[14:31:50.257] <TB1> INFO: 35624700 events read in total (1219132ms).
[14:32:12.707] <TB1> INFO: 36286000 events read in total (1241582ms).
[14:32:24.164] <TB1> INFO: 36608000 events read in total (1253039ms).
[14:32:24.257] <TB1> INFO: Test took 1254018ms.
[14:32:24.754] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:32:27.085] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:32:28.915] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:32:31.032] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:32:33.217] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:32:34.806] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:32:37.003] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:32:39.394] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:32:41.446] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:32:43.341] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:32:45.330] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:32:47.320] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:32:49.542] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:32:51.549] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:32:53.524] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:32:55.539] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:32:57.189] <TB1> INFO: PixTestScurves::scurves() done
[14:32:57.189] <TB1> INFO: Vcal mean: 126.91 114.37 110.35 114.08 126.33 121.35 110.34 109.22 130.95 119.25 125.59 122.02 121.39 120.75 130.86 124.15
[14:32:57.189] <TB1> INFO: Vcal RMS: 6.11 5.65 4.67 4.86 6.74 6.21 5.29 5.13 6.03 5.89 6.68 6.51 5.94 6.07 6.30 6.67
[14:32:57.190] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1286 seconds
[14:32:57.190] <TB1> INFO: Decoding statistics:
[14:32:57.190] <TB1> INFO: General information:
[14:32:57.190] <TB1> INFO: 16bit words read: 0
[14:32:57.190] <TB1> INFO: valid events total: 0
[14:32:57.190] <TB1> INFO: empty events: 0
[14:32:57.190] <TB1> INFO: valid events with pixels: 0
[14:32:57.190] <TB1> INFO: valid pixel hits: 0
[14:32:57.190] <TB1> INFO: Event errors: 0
[14:32:57.190] <TB1> INFO: start marker: 0
[14:32:57.190] <TB1> INFO: stop marker: 0
[14:32:57.190] <TB1> INFO: overflow: 0
[14:32:57.190] <TB1> INFO: invalid 5bit words: 0
[14:32:57.190] <TB1> INFO: invalid XOR eye diagram: 0
[14:32:57.190] <TB1> INFO: frame (failed synchr.): 0
[14:32:57.190] <TB1> INFO: idle data (no TBM trl): 0
[14:32:57.190] <TB1> INFO: no data (only TBM hdr): 0
[14:32:57.190] <TB1> INFO: TBM errors: 0
[14:32:57.190] <TB1> INFO: flawed TBM headers: 0
[14:32:57.190] <TB1> INFO: flawed TBM trailers: 0
[14:32:57.190] <TB1> INFO: event ID mismatches: 0
[14:32:57.190] <TB1> INFO: ROC errors: 0
[14:32:57.190] <TB1> INFO: missing ROC header(s): 0
[14:32:57.190] <TB1> INFO: misplaced readback start: 0
[14:32:57.190] <TB1> INFO: Pixel decoding errors: 0
[14:32:57.190] <TB1> INFO: pixel data incomplete: 0
[14:32:57.190] <TB1> INFO: pixel address: 0
[14:32:57.190] <TB1> INFO: pulse height fill bit: 0
[14:32:57.190] <TB1> INFO: buffer corruption: 0
[14:32:57.277] <TB1> INFO: ######################################################################
[14:32:57.277] <TB1> INFO: PixTestTrim::doTest()
[14:32:57.277] <TB1> INFO: ######################################################################
[14:32:57.278] <TB1> INFO: ----------------------------------------------------------------------
[14:32:57.278] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[14:32:57.278] <TB1> INFO: ----------------------------------------------------------------------
[14:32:57.322] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:32:57.322] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:32:57.334] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:32:57.334] <TB1> INFO: run 1 of 1
[14:32:57.571] <TB1> INFO: Expecting 5025280 events.
[14:33:27.990] <TB1> INFO: 823824 events read in total (29818ms).
[14:33:57.774] <TB1> INFO: 1643472 events read in total (59603ms).
[14:34:27.609] <TB1> INFO: 2458560 events read in total (89437ms).
[14:34:57.022] <TB1> INFO: 3269176 events read in total (118850ms).
[14:35:26.559] <TB1> INFO: 4076536 events read in total (148388ms).
[14:35:56.258] <TB1> INFO: 4880392 events read in total (178086ms).
[14:36:01.948] <TB1> INFO: 5025280 events read in total (183776ms).
[14:36:01.997] <TB1> INFO: Test took 184662ms.
[14:36:20.004] <TB1> INFO: ROC 0 VthrComp = 136
[14:36:20.004] <TB1> INFO: ROC 1 VthrComp = 121
[14:36:20.004] <TB1> INFO: ROC 2 VthrComp = 112
[14:36:20.004] <TB1> INFO: ROC 3 VthrComp = 112
[14:36:20.004] <TB1> INFO: ROC 4 VthrComp = 128
[14:36:20.004] <TB1> INFO: ROC 5 VthrComp = 128
[14:36:20.005] <TB1> INFO: ROC 6 VthrComp = 115
[14:36:20.005] <TB1> INFO: ROC 7 VthrComp = 115
[14:36:20.005] <TB1> INFO: ROC 8 VthrComp = 132
[14:36:20.005] <TB1> INFO: ROC 9 VthrComp = 120
[14:36:20.005] <TB1> INFO: ROC 10 VthrComp = 130
[14:36:20.005] <TB1> INFO: ROC 11 VthrComp = 128
[14:36:20.005] <TB1> INFO: ROC 12 VthrComp = 123
[14:36:20.006] <TB1> INFO: ROC 13 VthrComp = 125
[14:36:20.006] <TB1> INFO: ROC 14 VthrComp = 135
[14:36:20.006] <TB1> INFO: ROC 15 VthrComp = 120
[14:36:20.276] <TB1> INFO: Expecting 41600 events.
[14:36:23.847] <TB1> INFO: 41600 events read in total (2979ms).
[14:36:23.848] <TB1> INFO: Test took 3841ms.
[14:36:23.859] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:36:23.859] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:36:23.873] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:36:23.873] <TB1> INFO: run 1 of 1
[14:36:24.151] <TB1> INFO: Expecting 5025280 events.
[14:36:50.090] <TB1> INFO: 593144 events read in total (25347ms).
[14:37:15.666] <TB1> INFO: 1184464 events read in total (50923ms).
[14:37:41.329] <TB1> INFO: 1774480 events read in total (76586ms).
[14:38:06.494] <TB1> INFO: 2363680 events read in total (101751ms).
[14:38:31.742] <TB1> INFO: 2950752 events read in total (126999ms).
[14:38:57.336] <TB1> INFO: 3536384 events read in total (152593ms).
[14:39:22.737] <TB1> INFO: 4121320 events read in total (177994ms).
[14:39:48.300] <TB1> INFO: 4705664 events read in total (203557ms).
[14:40:03.134] <TB1> INFO: 5025280 events read in total (218391ms).
[14:40:03.221] <TB1> INFO: Test took 219348ms.
[14:40:33.576] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 59.5595 for pixel 6/45 mean/min/max = 47.6712/35.7134/59.6291
[14:40:33.576] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 59.5507 for pixel 6/9 mean/min/max = 45.5785/31.6/59.557
[14:40:33.577] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 61.3632 for pixel 1/0 mean/min/max = 47.2609/32.9535/61.5683
[14:40:33.577] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 61.2225 for pixel 44/3 mean/min/max = 47.2806/33.3186/61.2427
[14:40:33.578] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 62.952 for pixel 9/75 mean/min/max = 47.3677/31.7412/62.9941
[14:40:33.578] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 58.7909 for pixel 15/65 mean/min/max = 45.7163/32.6028/58.8299
[14:40:33.579] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 57.9879 for pixel 0/26 mean/min/max = 45.2584/32.5191/57.9976
[14:40:33.579] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 58.5748 for pixel 4/3 mean/min/max = 45.7886/32.8905/58.6866
[14:40:33.580] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 60.6815 for pixel 0/11 mean/min/max = 47.9453/35.0186/60.8719
[14:40:33.580] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 60.1857 for pixel 1/77 mean/min/max = 46.6542/33.0949/60.2134
[14:40:33.581] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 61.4643 for pixel 2/69 mean/min/max = 47.0719/32.6038/61.5399
[14:40:33.581] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 60.3346 for pixel 12/5 mean/min/max = 46.214/32.0557/60.3722
[14:40:33.581] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 59.0764 for pixel 9/79 mean/min/max = 45.8177/32.4178/59.2176
[14:40:33.582] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 59.7274 for pixel 12/78 mean/min/max = 46.132/32.4993/59.7647
[14:40:33.582] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 60.6055 for pixel 9/0 mean/min/max = 47.3257/33.992/60.6595
[14:40:33.583] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 62.5456 for pixel 10/73 mean/min/max = 47.546/32.5377/62.5544
[14:40:33.583] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:40:33.671] <TB1> INFO: Expecting 411648 events.
[14:40:43.298] <TB1> INFO: 411648 events read in total (9035ms).
[14:40:43.309] <TB1> INFO: Expecting 411648 events.
[14:40:52.789] <TB1> INFO: 411648 events read in total (9077ms).
[14:40:52.807] <TB1> INFO: Expecting 411648 events.
[14:41:02.204] <TB1> INFO: 411648 events read in total (8994ms).
[14:41:02.224] <TB1> INFO: Expecting 411648 events.
[14:41:11.599] <TB1> INFO: 411648 events read in total (8972ms).
[14:41:11.620] <TB1> INFO: Expecting 411648 events.
[14:41:20.922] <TB1> INFO: 411648 events read in total (8899ms).
[14:41:20.941] <TB1> INFO: Expecting 411648 events.
[14:41:30.290] <TB1> INFO: 411648 events read in total (8946ms).
[14:41:30.313] <TB1> INFO: Expecting 411648 events.
[14:41:39.623] <TB1> INFO: 411648 events read in total (8906ms).
[14:41:39.657] <TB1> INFO: Expecting 411648 events.
[14:41:48.002] <TB1> INFO: 411648 events read in total (8942ms).
[14:41:49.029] <TB1> INFO: Expecting 411648 events.
[14:41:58.329] <TB1> INFO: 411648 events read in total (8897ms).
[14:41:58.359] <TB1> INFO: Expecting 411648 events.
[14:42:07.671] <TB1> INFO: 411648 events read in total (8909ms).
[14:42:07.703] <TB1> INFO: Expecting 411648 events.
[14:42:17.116] <TB1> INFO: 411648 events read in total (9010ms).
[14:42:17.150] <TB1> INFO: Expecting 411648 events.
[14:42:26.487] <TB1> INFO: 411648 events read in total (8934ms).
[14:42:26.526] <TB1> INFO: Expecting 411648 events.
[14:42:35.833] <TB1> INFO: 411648 events read in total (8904ms).
[14:42:35.883] <TB1> INFO: Expecting 411648 events.
[14:42:45.231] <TB1> INFO: 411648 events read in total (8944ms).
[14:42:45.275] <TB1> INFO: Expecting 411648 events.
[14:42:54.565] <TB1> INFO: 411648 events read in total (8887ms).
[14:42:54.614] <TB1> INFO: Expecting 411648 events.
[14:43:03.922] <TB1> INFO: 411648 events read in total (8905ms).
[14:43:03.973] <TB1> INFO: Test took 150390ms.
[14:43:04.719] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:43:04.731] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:43:04.731] <TB1> INFO: run 1 of 1
[14:43:04.998] <TB1> INFO: Expecting 5025280 events.
[14:43:31.121] <TB1> INFO: 587584 events read in total (25532ms).
[14:43:57.089] <TB1> INFO: 1173456 events read in total (51500ms).
[14:44:23.055] <TB1> INFO: 1758528 events read in total (77467ms).
[14:44:49.171] <TB1> INFO: 2342240 events read in total (103582ms).
[14:45:15.245] <TB1> INFO: 2925776 events read in total (129656ms).
[14:45:41.096] <TB1> INFO: 3508920 events read in total (155507ms).
[14:46:06.760] <TB1> INFO: 4091400 events read in total (181171ms).
[14:46:32.597] <TB1> INFO: 4673392 events read in total (207008ms).
[14:46:48.472] <TB1> INFO: 5025280 events read in total (222883ms).
[14:46:48.632] <TB1> INFO: Test took 223901ms.
[14:47:14.177] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 10.500000 .. 147.246238
[14:47:14.419] <TB1> INFO: Expecting 208000 events.
[14:47:24.017] <TB1> INFO: 208000 events read in total (9004ms).
[14:47:24.018] <TB1> INFO: Test took 9840ms.
[14:47:24.085] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 0 .. 157 (-1/-1) hits flags = 528 (plus default)
[14:47:24.098] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:47:24.098] <TB1> INFO: run 1 of 1
[14:47:24.377] <TB1> INFO: Expecting 5258240 events.
[14:47:50.863] <TB1> INFO: 584632 events read in total (25895ms).
[14:48:16.230] <TB1> INFO: 1169640 events read in total (51262ms).
[14:48:41.906] <TB1> INFO: 1754624 events read in total (76938ms).
[14:49:07.353] <TB1> INFO: 2339864 events read in total (102386ms).
[14:49:32.644] <TB1> INFO: 2924912 events read in total (127676ms).
[14:49:57.958] <TB1> INFO: 3509736 events read in total (152990ms).
[14:50:23.771] <TB1> INFO: 4094296 events read in total (178803ms).
[14:50:49.522] <TB1> INFO: 4678320 events read in total (204554ms).
[14:51:16.703] <TB1> INFO: 5258240 events read in total (231735ms).
[14:51:16.829] <TB1> INFO: Test took 232732ms.
[14:51:42.543] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.729719 .. 46.797190
[14:51:42.782] <TB1> INFO: Expecting 208000 events.
[14:51:52.476] <TB1> INFO: 208000 events read in total (9102ms).
[14:51:52.477] <TB1> INFO: Test took 9933ms.
[14:51:52.524] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[14:51:52.537] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:51:52.537] <TB1> INFO: run 1 of 1
[14:51:52.815] <TB1> INFO: Expecting 1331200 events.
[14:52:20.559] <TB1> INFO: 655040 events read in total (27152ms).
[14:52:48.467] <TB1> INFO: 1309496 events read in total (55060ms).
[14:52:49.784] <TB1> INFO: 1331200 events read in total (56377ms).
[14:52:49.815] <TB1> INFO: Test took 57278ms.
[14:53:05.716] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 25.984942 .. 48.302686
[14:53:05.953] <TB1> INFO: Expecting 208000 events.
[14:53:15.713] <TB1> INFO: 208000 events read in total (9168ms).
[14:53:15.714] <TB1> INFO: Test took 9997ms.
[14:53:15.761] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 58 (-1/-1) hits flags = 528 (plus default)
[14:53:15.774] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:53:15.774] <TB1> INFO: run 1 of 1
[14:53:16.052] <TB1> INFO: Expecting 1464320 events.
[14:53:44.921] <TB1> INFO: 656624 events read in total (28277ms).
[14:54:12.897] <TB1> INFO: 1312816 events read in total (56253ms).
[14:54:19.740] <TB1> INFO: 1464320 events read in total (63096ms).
[14:54:19.771] <TB1> INFO: Test took 63998ms.
[14:54:32.960] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 23.869231 .. 48.657722
[14:54:33.204] <TB1> INFO: Expecting 208000 events.
[14:54:43.109] <TB1> INFO: 208000 events read in total (9313ms).
[14:54:43.111] <TB1> INFO: Test took 10150ms.
[14:54:43.179] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 13 .. 58 (-1/-1) hits flags = 528 (plus default)
[14:54:43.193] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:54:43.193] <TB1> INFO: run 1 of 1
[14:54:43.471] <TB1> INFO: Expecting 1530880 events.
[14:55:11.790] <TB1> INFO: 663736 events read in total (27727ms).
[14:55:39.300] <TB1> INFO: 1327664 events read in total (55237ms).
[14:55:48.489] <TB1> INFO: 1530880 events read in total (64426ms).
[14:55:48.532] <TB1> INFO: Test took 65340ms.
[14:56:00.919] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:56:00.919] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:56:00.931] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:56:00.931] <TB1> INFO: run 1 of 1
[14:56:01.167] <TB1> INFO: Expecting 1364480 events.
[14:56:29.602] <TB1> INFO: 668776 events read in total (27843ms).
[14:56:58.146] <TB1> INFO: 1336848 events read in total (56387ms).
[14:56:59.719] <TB1> INFO: 1364480 events read in total (57960ms).
[14:56:59.752] <TB1> INFO: Test took 58821ms.
[14:57:13.382] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C0.dat
[14:57:13.382] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C1.dat
[14:57:13.382] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C2.dat
[14:57:13.382] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C3.dat
[14:57:13.382] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C4.dat
[14:57:13.382] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C5.dat
[14:57:13.383] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C6.dat
[14:57:13.383] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C7.dat
[14:57:13.383] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C8.dat
[14:57:13.383] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C9.dat
[14:57:13.383] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C10.dat
[14:57:13.383] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C11.dat
[14:57:13.383] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C12.dat
[14:57:13.383] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C13.dat
[14:57:13.383] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C14.dat
[14:57:13.383] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C15.dat
[14:57:13.383] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C0.dat
[14:57:13.390] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C1.dat
[14:57:13.396] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C2.dat
[14:57:13.401] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C3.dat
[14:57:13.406] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C4.dat
[14:57:13.410] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C5.dat
[14:57:13.415] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C6.dat
[14:57:13.420] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C7.dat
[14:57:13.424] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C8.dat
[14:57:13.429] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C9.dat
[14:57:13.434] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C10.dat
[14:57:13.439] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C11.dat
[14:57:13.443] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C12.dat
[14:57:13.448] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C13.dat
[14:57:13.453] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C14.dat
[14:57:13.457] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//trimParameters35_C15.dat
[14:57:13.462] <TB1> INFO: PixTestTrim::trimTest() done
[14:57:13.462] <TB1> INFO: vtrim: 139 125 128 124 142 132 101 120 119 124 126 155 111 125 126 131
[14:57:13.462] <TB1> INFO: vthrcomp: 136 121 112 112 128 128 115 115 132 120 130 128 123 125 135 120
[14:57:13.462] <TB1> INFO: vcal mean: 35.15 34.97 35.01 35.02 35.67 35.03 34.99 35.03 35.06 35.11 35.04 35.09 35.01 35.01 35.08 35.13
[14:57:13.462] <TB1> INFO: vcal RMS: 1.11 0.98 1.07 1.12 1.91 0.98 0.96 0.94 1.06 1.16 1.05 1.19 1.10 1.02 1.10 1.23
[14:57:13.462] <TB1> INFO: bits mean: 8.59 9.62 9.13 9.27 9.94 9.15 8.97 9.18 8.26 9.16 8.90 9.80 9.09 9.67 8.55 9.16
[14:57:13.462] <TB1> INFO: bits RMS: 2.47 2.72 2.73 2.58 2.65 2.82 2.93 2.80 2.70 2.73 2.84 2.59 2.84 2.56 2.76 2.72
[14:57:13.470] <TB1> INFO: ----------------------------------------------------------------------
[14:57:13.470] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:57:13.470] <TB1> INFO: ----------------------------------------------------------------------
[14:57:13.472] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:57:13.486] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:57:13.486] <TB1> INFO: run 1 of 1
[14:57:13.724] <TB1> INFO: Expecting 4160000 events.
[14:57:46.104] <TB1> INFO: 752845 events read in total (31788ms).
[14:58:17.583] <TB1> INFO: 1496885 events read in total (63267ms).
[14:58:48.950] <TB1> INFO: 2234750 events read in total (94634ms).
[14:59:20.321] <TB1> INFO: 2967590 events read in total (126005ms).
[14:59:51.479] <TB1> INFO: 3695995 events read in total (157163ms).
[15:00:11.948] <TB1> INFO: 4160000 events read in total (177632ms).
[15:00:12.085] <TB1> INFO: Test took 178599ms.
[15:00:39.473] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[15:00:39.485] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:00:39.485] <TB1> INFO: run 1 of 1
[15:00:39.721] <TB1> INFO: Expecting 4305600 events.
[15:01:11.459] <TB1> INFO: 720160 events read in total (31146ms).
[15:01:42.456] <TB1> INFO: 1432625 events read in total (62143ms).
[15:02:13.359] <TB1> INFO: 2140345 events read in total (93046ms).
[15:02:43.825] <TB1> INFO: 2842000 events read in total (123512ms).
[15:03:14.214] <TB1> INFO: 3541620 events read in total (153901ms).
[15:03:44.529] <TB1> INFO: 4240130 events read in total (184216ms).
[15:03:47.641] <TB1> INFO: 4305600 events read in total (187328ms).
[15:03:47.721] <TB1> INFO: Test took 188235ms.
[15:04:15.423] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[15:04:15.437] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:04:15.437] <TB1> INFO: run 1 of 1
[15:04:15.762] <TB1> INFO: Expecting 4160000 events.
[15:04:48.039] <TB1> INFO: 729840 events read in total (31686ms).
[15:05:18.929] <TB1> INFO: 1451085 events read in total (62576ms).
[15:05:49.540] <TB1> INFO: 2166525 events read in total (93187ms).
[15:06:19.879] <TB1> INFO: 2876300 events read in total (123526ms).
[15:06:50.690] <TB1> INFO: 3582410 events read in total (154337ms).
[15:07:16.061] <TB1> INFO: 4160000 events read in total (179708ms).
[15:07:16.142] <TB1> INFO: Test took 180705ms.
[15:07:39.809] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[15:07:39.822] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:07:39.822] <TB1> INFO: run 1 of 1
[15:07:40.058] <TB1> INFO: Expecting 4097600 events.
[15:08:12.254] <TB1> INFO: 733235 events read in total (31604ms).
[15:08:43.192] <TB1> INFO: 1457890 events read in total (62542ms).
[15:09:14.212] <TB1> INFO: 2176735 events read in total (93562ms).
[15:09:45.016] <TB1> INFO: 2889505 events read in total (124366ms).
[15:10:15.426] <TB1> INFO: 3599135 events read in total (154776ms).
[15:10:36.715] <TB1> INFO: 4097600 events read in total (176065ms).
[15:10:36.852] <TB1> INFO: Test took 177030ms.
[15:11:02.043] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[15:11:02.057] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:11:02.057] <TB1> INFO: run 1 of 1
[15:11:02.298] <TB1> INFO: Expecting 4160000 events.
[15:11:34.146] <TB1> INFO: 730060 events read in total (31256ms).
[15:12:05.878] <TB1> INFO: 1451085 events read in total (62988ms).
[15:12:36.289] <TB1> INFO: 2166720 events read in total (93399ms).
[15:13:07.892] <TB1> INFO: 2876405 events read in total (125002ms).
[15:13:39.161] <TB1> INFO: 3582535 events read in total (156271ms).
[15:14:04.738] <TB1> INFO: 4160000 events read in total (181848ms).
[15:14:04.844] <TB1> INFO: Test took 182787ms.
[15:14:31.298] <TB1> INFO: PixTestTrim::trimBitTest() done
[15:14:31.299] <TB1> INFO: PixTestTrim::doTest() done, duration: 2494 seconds
[15:14:31.299] <TB1> INFO: Decoding statistics:
[15:14:31.299] <TB1> INFO: General information:
[15:14:31.299] <TB1> INFO: 16bit words read: 0
[15:14:31.299] <TB1> INFO: valid events total: 0
[15:14:31.299] <TB1> INFO: empty events: 0
[15:14:31.299] <TB1> INFO: valid events with pixels: 0
[15:14:31.299] <TB1> INFO: valid pixel hits: 0
[15:14:31.299] <TB1> INFO: Event errors: 0
[15:14:31.299] <TB1> INFO: start marker: 0
[15:14:31.299] <TB1> INFO: stop marker: 0
[15:14:31.299] <TB1> INFO: overflow: 0
[15:14:31.299] <TB1> INFO: invalid 5bit words: 0
[15:14:31.299] <TB1> INFO: invalid XOR eye diagram: 0
[15:14:31.299] <TB1> INFO: frame (failed synchr.): 0
[15:14:31.299] <TB1> INFO: idle data (no TBM trl): 0
[15:14:31.299] <TB1> INFO: no data (only TBM hdr): 0
[15:14:31.299] <TB1> INFO: TBM errors: 0
[15:14:31.299] <TB1> INFO: flawed TBM headers: 0
[15:14:31.299] <TB1> INFO: flawed TBM trailers: 0
[15:14:31.299] <TB1> INFO: event ID mismatches: 0
[15:14:31.299] <TB1> INFO: ROC errors: 0
[15:14:31.299] <TB1> INFO: missing ROC header(s): 0
[15:14:31.299] <TB1> INFO: misplaced readback start: 0
[15:14:31.299] <TB1> INFO: Pixel decoding errors: 0
[15:14:31.299] <TB1> INFO: pixel data incomplete: 0
[15:14:31.299] <TB1> INFO: pixel address: 0
[15:14:31.299] <TB1> INFO: pulse height fill bit: 0
[15:14:31.299] <TB1> INFO: buffer corruption: 0
[15:14:31.908] <TB1> INFO: ######################################################################
[15:14:31.908] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[15:14:31.908] <TB1> INFO: ######################################################################
[15:14:32.145] <TB1> INFO: Expecting 41600 events.
[15:14:35.589] <TB1> INFO: 41600 events read in total (2853ms).
[15:14:35.590] <TB1> INFO: Test took 3681ms.
[15:14:36.077] <TB1> INFO: Expecting 41600 events.
[15:14:39.767] <TB1> INFO: 41600 events read in total (3098ms).
[15:14:39.768] <TB1> INFO: Test took 3974ms.
[15:14:40.070] <TB1> INFO: Expecting 41600 events.
[15:14:43.696] <TB1> INFO: 41600 events read in total (3034ms).
[15:14:43.697] <TB1> INFO: Test took 3904ms.
[15:14:43.986] <TB1> INFO: Expecting 41600 events.
[15:14:47.564] <TB1> INFO: 41600 events read in total (2986ms).
[15:14:47.565] <TB1> INFO: Test took 3843ms.
[15:14:47.854] <TB1> INFO: Expecting 41600 events.
[15:14:51.355] <TB1> INFO: 41600 events read in total (2909ms).
[15:14:51.356] <TB1> INFO: Test took 3767ms.
[15:14:51.645] <TB1> INFO: Expecting 41600 events.
[15:14:55.200] <TB1> INFO: 41600 events read in total (2964ms).
[15:14:55.201] <TB1> INFO: Test took 3821ms.
[15:14:55.491] <TB1> INFO: Expecting 41600 events.
[15:14:59.057] <TB1> INFO: 41600 events read in total (2974ms).
[15:14:59.058] <TB1> INFO: Test took 3833ms.
[15:14:59.348] <TB1> INFO: Expecting 41600 events.
[15:15:02.905] <TB1> INFO: 41600 events read in total (2965ms).
[15:15:02.906] <TB1> INFO: Test took 3824ms.
[15:15:03.197] <TB1> INFO: Expecting 41600 events.
[15:15:06.760] <TB1> INFO: 41600 events read in total (2972ms).
[15:15:06.761] <TB1> INFO: Test took 3830ms.
[15:15:07.052] <TB1> INFO: Expecting 41600 events.
[15:15:10.625] <TB1> INFO: 41600 events read in total (2981ms).
[15:15:10.626] <TB1> INFO: Test took 3839ms.
[15:15:10.945] <TB1> INFO: Expecting 41600 events.
[15:15:14.497] <TB1> INFO: 41600 events read in total (2961ms).
[15:15:14.498] <TB1> INFO: Test took 3847ms.
[15:15:14.791] <TB1> INFO: Expecting 41600 events.
[15:15:18.350] <TB1> INFO: 41600 events read in total (2968ms).
[15:15:18.351] <TB1> INFO: Test took 3828ms.
[15:15:18.640] <TB1> INFO: Expecting 41600 events.
[15:15:22.112] <TB1> INFO: 41600 events read in total (2881ms).
[15:15:22.113] <TB1> INFO: Test took 3738ms.
[15:15:22.448] <TB1> INFO: Expecting 41600 events.
[15:15:26.009] <TB1> INFO: 41600 events read in total (2970ms).
[15:15:26.010] <TB1> INFO: Test took 3871ms.
[15:15:26.299] <TB1> INFO: Expecting 41600 events.
[15:15:30.021] <TB1> INFO: 41600 events read in total (3130ms).
[15:15:30.022] <TB1> INFO: Test took 3988ms.
[15:15:30.330] <TB1> INFO: Expecting 41600 events.
[15:15:33.832] <TB1> INFO: 41600 events read in total (2911ms).
[15:15:33.833] <TB1> INFO: Test took 3784ms.
[15:15:34.147] <TB1> INFO: Expecting 41600 events.
[15:15:37.867] <TB1> INFO: 41600 events read in total (3129ms).
[15:15:37.869] <TB1> INFO: Test took 4011ms.
[15:15:38.175] <TB1> INFO: Expecting 41600 events.
[15:15:41.695] <TB1> INFO: 41600 events read in total (2928ms).
[15:15:41.696] <TB1> INFO: Test took 3801ms.
[15:15:41.000] <TB1> INFO: Expecting 41600 events.
[15:15:45.688] <TB1> INFO: 41600 events read in total (3097ms).
[15:15:45.689] <TB1> INFO: Test took 3968ms.
[15:15:45.981] <TB1> INFO: Expecting 41600 events.
[15:15:49.531] <TB1> INFO: 41600 events read in total (2957ms).
[15:15:49.532] <TB1> INFO: Test took 3816ms.
[15:15:49.862] <TB1> INFO: Expecting 41600 events.
[15:15:53.433] <TB1> INFO: 41600 events read in total (2979ms).
[15:15:53.434] <TB1> INFO: Test took 3878ms.
[15:15:53.723] <TB1> INFO: Expecting 41600 events.
[15:15:57.238] <TB1> INFO: 41600 events read in total (2923ms).
[15:15:57.239] <TB1> INFO: Test took 3781ms.
[15:15:57.528] <TB1> INFO: Expecting 41600 events.
[15:16:01.036] <TB1> INFO: 41600 events read in total (2916ms).
[15:16:01.037] <TB1> INFO: Test took 3774ms.
[15:16:01.326] <TB1> INFO: Expecting 41600 events.
[15:16:04.924] <TB1> INFO: 41600 events read in total (3007ms).
[15:16:04.925] <TB1> INFO: Test took 3864ms.
[15:16:05.217] <TB1> INFO: Expecting 41600 events.
[15:16:08.709] <TB1> INFO: 41600 events read in total (2901ms).
[15:16:08.710] <TB1> INFO: Test took 3758ms.
[15:16:09.055] <TB1> INFO: Expecting 41600 events.
[15:16:12.650] <TB1> INFO: 41600 events read in total (3004ms).
[15:16:12.651] <TB1> INFO: Test took 3905ms.
[15:16:12.941] <TB1> INFO: Expecting 41600 events.
[15:16:16.485] <TB1> INFO: 41600 events read in total (2953ms).
[15:16:16.486] <TB1> INFO: Test took 3810ms.
[15:16:16.775] <TB1> INFO: Expecting 41600 events.
[15:16:20.269] <TB1> INFO: 41600 events read in total (2903ms).
[15:16:20.270] <TB1> INFO: Test took 3760ms.
[15:16:20.561] <TB1> INFO: Expecting 41600 events.
[15:16:24.094] <TB1> INFO: 41600 events read in total (2942ms).
[15:16:24.095] <TB1> INFO: Test took 3799ms.
[15:16:24.409] <TB1> INFO: Expecting 41600 events.
[15:16:27.886] <TB1> INFO: 41600 events read in total (2885ms).
[15:16:27.887] <TB1> INFO: Test took 3766ms.
[15:16:28.234] <TB1> INFO: Expecting 41600 events.
[15:16:31.793] <TB1> INFO: 41600 events read in total (2968ms).
[15:16:31.795] <TB1> INFO: Test took 3879ms.
[15:16:32.086] <TB1> INFO: Expecting 2560 events.
[15:16:32.973] <TB1> INFO: 2560 events read in total (295ms).
[15:16:32.973] <TB1> INFO: Test took 1163ms.
[15:16:33.281] <TB1> INFO: Expecting 2560 events.
[15:16:34.164] <TB1> INFO: 2560 events read in total (292ms).
[15:16:34.165] <TB1> INFO: Test took 1192ms.
[15:16:34.473] <TB1> INFO: Expecting 2560 events.
[15:16:35.356] <TB1> INFO: 2560 events read in total (292ms).
[15:16:35.356] <TB1> INFO: Test took 1190ms.
[15:16:35.664] <TB1> INFO: Expecting 2560 events.
[15:16:36.552] <TB1> INFO: 2560 events read in total (296ms).
[15:16:36.552] <TB1> INFO: Test took 1194ms.
[15:16:36.860] <TB1> INFO: Expecting 2560 events.
[15:16:37.739] <TB1> INFO: 2560 events read in total (287ms).
[15:16:37.740] <TB1> INFO: Test took 1187ms.
[15:16:38.047] <TB1> INFO: Expecting 2560 events.
[15:16:38.929] <TB1> INFO: 2560 events read in total (290ms).
[15:16:38.929] <TB1> INFO: Test took 1189ms.
[15:16:39.238] <TB1> INFO: Expecting 2560 events.
[15:16:40.124] <TB1> INFO: 2560 events read in total (295ms).
[15:16:40.124] <TB1> INFO: Test took 1194ms.
[15:16:40.432] <TB1> INFO: Expecting 2560 events.
[15:16:41.311] <TB1> INFO: 2560 events read in total (288ms).
[15:16:41.311] <TB1> INFO: Test took 1186ms.
[15:16:41.619] <TB1> INFO: Expecting 2560 events.
[15:16:42.497] <TB1> INFO: 2560 events read in total (287ms).
[15:16:42.497] <TB1> INFO: Test took 1186ms.
[15:16:42.805] <TB1> INFO: Expecting 2560 events.
[15:16:43.690] <TB1> INFO: 2560 events read in total (293ms).
[15:16:43.690] <TB1> INFO: Test took 1192ms.
[15:16:43.998] <TB1> INFO: Expecting 2560 events.
[15:16:44.877] <TB1> INFO: 2560 events read in total (287ms).
[15:16:44.877] <TB1> INFO: Test took 1186ms.
[15:16:45.185] <TB1> INFO: Expecting 2560 events.
[15:16:46.065] <TB1> INFO: 2560 events read in total (288ms).
[15:16:46.065] <TB1> INFO: Test took 1188ms.
[15:16:46.373] <TB1> INFO: Expecting 2560 events.
[15:16:47.256] <TB1> INFO: 2560 events read in total (292ms).
[15:16:47.256] <TB1> INFO: Test took 1190ms.
[15:16:47.564] <TB1> INFO: Expecting 2560 events.
[15:16:48.451] <TB1> INFO: 2560 events read in total (295ms).
[15:16:48.451] <TB1> INFO: Test took 1194ms.
[15:16:48.759] <TB1> INFO: Expecting 2560 events.
[15:16:49.644] <TB1> INFO: 2560 events read in total (294ms).
[15:16:49.645] <TB1> INFO: Test took 1194ms.
[15:16:49.953] <TB1> INFO: Expecting 2560 events.
[15:16:50.836] <TB1> INFO: 2560 events read in total (292ms).
[15:16:50.837] <TB1> INFO: Test took 1192ms.
[15:16:50.840] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:16:51.145] <TB1> INFO: Expecting 655360 events.
[15:17:06.184] <TB1> INFO: 655360 events read in total (14447ms).
[15:17:06.200] <TB1> INFO: Expecting 655360 events.
[15:17:20.928] <TB1> INFO: 655360 events read in total (14325ms).
[15:17:20.953] <TB1> INFO: Expecting 655360 events.
[15:17:35.995] <TB1> INFO: 655360 events read in total (14638ms).
[15:17:36.026] <TB1> INFO: Expecting 655360 events.
[15:17:51.145] <TB1> INFO: 655360 events read in total (14716ms).
[15:17:51.174] <TB1> INFO: Expecting 655360 events.
[15:18:06.061] <TB1> INFO: 655360 events read in total (14484ms).
[15:18:06.094] <TB1> INFO: Expecting 655360 events.
[15:18:20.772] <TB1> INFO: 655360 events read in total (14275ms).
[15:18:20.809] <TB1> INFO: Expecting 655360 events.
[15:18:35.452] <TB1> INFO: 655360 events read in total (14240ms).
[15:18:35.504] <TB1> INFO: Expecting 655360 events.
[15:18:50.366] <TB1> INFO: 655360 events read in total (14459ms).
[15:18:50.413] <TB1> INFO: Expecting 655360 events.
[15:19:05.341] <TB1> INFO: 655360 events read in total (14525ms).
[15:19:05.400] <TB1> INFO: Expecting 655360 events.
[15:19:20.341] <TB1> INFO: 655360 events read in total (14538ms).
[15:19:20.406] <TB1> INFO: Expecting 655360 events.
[15:19:35.107] <TB1> INFO: 655360 events read in total (14298ms).
[15:19:35.274] <TB1> INFO: Expecting 655360 events.
[15:19:50.096] <TB1> INFO: 655360 events read in total (14419ms).
[15:19:50.174] <TB1> INFO: Expecting 655360 events.
[15:20:04.940] <TB1> INFO: 655360 events read in total (14363ms).
[15:20:05.022] <TB1> INFO: Expecting 655360 events.
[15:20:19.798] <TB1> INFO: 655360 events read in total (14373ms).
[15:20:19.923] <TB1> INFO: Expecting 655360 events.
[15:20:34.813] <TB1> INFO: 655360 events read in total (14487ms).
[15:20:34.934] <TB1> INFO: Expecting 655360 events.
[15:20:49.808] <TB1> INFO: 655360 events read in total (14471ms).
[15:20:49.909] <TB1> INFO: Test took 239069ms.
[15:20:50.015] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:20:50.272] <TB1> INFO: Expecting 655360 events.
[15:21:05.235] <TB1> INFO: 655360 events read in total (14371ms).
[15:21:05.251] <TB1> INFO: Expecting 655360 events.
[15:21:20.121] <TB1> INFO: 655360 events read in total (14467ms).
[15:21:20.142] <TB1> INFO: Expecting 655360 events.
[15:21:34.865] <TB1> INFO: 655360 events read in total (14320ms).
[15:21:34.888] <TB1> INFO: Expecting 655360 events.
[15:21:49.325] <TB1> INFO: 655360 events read in total (14034ms).
[15:21:49.350] <TB1> INFO: Expecting 655360 events.
[15:22:04.122] <TB1> INFO: 655360 events read in total (14369ms).
[15:22:04.153] <TB1> INFO: Expecting 655360 events.
[15:22:18.782] <TB1> INFO: 655360 events read in total (14226ms).
[15:22:18.819] <TB1> INFO: Expecting 655360 events.
[15:22:33.560] <TB1> INFO: 655360 events read in total (14338ms).
[15:22:33.611] <TB1> INFO: Expecting 655360 events.
[15:22:48.540] <TB1> INFO: 655360 events read in total (14526ms).
[15:22:48.597] <TB1> INFO: Expecting 655360 events.
[15:23:03.217] <TB1> INFO: 655360 events read in total (14218ms).
[15:23:03.318] <TB1> INFO: Expecting 655360 events.
[15:23:17.983] <TB1> INFO: 655360 events read in total (14262ms).
[15:23:18.050] <TB1> INFO: Expecting 655360 events.
[15:23:32.611] <TB1> INFO: 655360 events read in total (14157ms).
[15:23:32.828] <TB1> INFO: Expecting 655360 events.
[15:23:47.573] <TB1> INFO: 655360 events read in total (14342ms).
[15:23:47.650] <TB1> INFO: Expecting 655360 events.
[15:24:02.228] <TB1> INFO: 655360 events read in total (14174ms).
[15:24:02.322] <TB1> INFO: Expecting 655360 events.
[15:24:16.836] <TB1> INFO: 655360 events read in total (14111ms).
[15:24:16.984] <TB1> INFO: Expecting 655360 events.
[15:24:31.515] <TB1> INFO: 655360 events read in total (14128ms).
[15:24:31.674] <TB1> INFO: Expecting 655360 events.
[15:24:46.121] <TB1> INFO: 655360 events read in total (14044ms).
[15:24:46.221] <TB1> INFO: Test took 236206ms.
[15:24:46.395] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:24:46.401] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:24:46.407] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:24:46.412] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:24:46.419] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:24:46.424] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:24:46.430] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:24:46.436] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[15:24:46.441] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:24:46.447] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:24:46.453] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:24:46.458] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[15:24:46.464] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[15:24:46.470] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[15:24:46.476] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[15:24:46.482] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:24:46.487] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:24:46.493] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:24:46.498] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:24:46.504] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:24:46.509] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[15:24:46.515] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:24:46.521] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:24:46.526] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:24:46.533] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:24:46.539] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:24:46.544] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:24:46.550] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[15:24:46.556] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[15:24:46.561] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[15:24:46.568] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[15:24:46.573] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[15:24:46.579] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[15:24:46.585] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:24:46.590] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:24:46.596] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:24:46.602] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:24:46.636] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C0.dat
[15:24:46.636] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C1.dat
[15:24:46.636] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C2.dat
[15:24:46.636] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C3.dat
[15:24:46.636] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C4.dat
[15:24:46.636] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C5.dat
[15:24:46.636] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C6.dat
[15:24:46.636] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C7.dat
[15:24:46.637] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C8.dat
[15:24:46.637] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C9.dat
[15:24:46.637] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C10.dat
[15:24:46.637] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C11.dat
[15:24:46.637] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C12.dat
[15:24:46.637] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C13.dat
[15:24:46.637] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C14.dat
[15:24:46.637] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//dacParameters35_C15.dat
[15:24:46.880] <TB1> INFO: Expecting 41600 events.
[15:24:50.015] <TB1> INFO: 41600 events read in total (2543ms).
[15:24:50.016] <TB1> INFO: Test took 3376ms.
[15:24:50.476] <TB1> INFO: Expecting 41600 events.
[15:24:53.592] <TB1> INFO: 41600 events read in total (2524ms).
[15:24:53.593] <TB1> INFO: Test took 3361ms.
[15:24:54.053] <TB1> INFO: Expecting 41600 events.
[15:24:57.181] <TB1> INFO: 41600 events read in total (2537ms).
[15:24:57.182] <TB1> INFO: Test took 3374ms.
[15:24:57.404] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:24:57.494] <TB1> INFO: Expecting 2560 events.
[15:24:58.385] <TB1> INFO: 2560 events read in total (299ms).
[15:24:58.385] <TB1> INFO: Test took 981ms.
[15:24:58.388] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:24:58.693] <TB1> INFO: Expecting 2560 events.
[15:24:59.584] <TB1> INFO: 2560 events read in total (299ms).
[15:24:59.585] <TB1> INFO: Test took 1197ms.
[15:24:59.588] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:24:59.892] <TB1> INFO: Expecting 2560 events.
[15:25:00.776] <TB1> INFO: 2560 events read in total (292ms).
[15:25:00.776] <TB1> INFO: Test took 1188ms.
[15:25:00.778] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:01.085] <TB1> INFO: Expecting 2560 events.
[15:25:01.972] <TB1> INFO: 2560 events read in total (296ms).
[15:25:01.972] <TB1> INFO: Test took 1195ms.
[15:25:01.975] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:02.280] <TB1> INFO: Expecting 2560 events.
[15:25:03.168] <TB1> INFO: 2560 events read in total (297ms).
[15:25:03.169] <TB1> INFO: Test took 1194ms.
[15:25:03.175] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:03.477] <TB1> INFO: Expecting 2560 events.
[15:25:04.362] <TB1> INFO: 2560 events read in total (293ms).
[15:25:04.362] <TB1> INFO: Test took 1187ms.
[15:25:04.366] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:04.671] <TB1> INFO: Expecting 2560 events.
[15:25:05.558] <TB1> INFO: 2560 events read in total (295ms).
[15:25:05.559] <TB1> INFO: Test took 1193ms.
[15:25:05.561] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:05.866] <TB1> INFO: Expecting 2560 events.
[15:25:06.760] <TB1> INFO: 2560 events read in total (302ms).
[15:25:06.761] <TB1> INFO: Test took 1200ms.
[15:25:06.763] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:07.068] <TB1> INFO: Expecting 2560 events.
[15:25:07.960] <TB1> INFO: 2560 events read in total (300ms).
[15:25:07.960] <TB1> INFO: Test took 1197ms.
[15:25:07.965] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:08.268] <TB1> INFO: Expecting 2560 events.
[15:25:09.162] <TB1> INFO: 2560 events read in total (302ms).
[15:25:09.163] <TB1> INFO: Test took 1198ms.
[15:25:09.166] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:09.470] <TB1> INFO: Expecting 2560 events.
[15:25:10.360] <TB1> INFO: 2560 events read in total (298ms).
[15:25:10.360] <TB1> INFO: Test took 1195ms.
[15:25:10.363] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:10.668] <TB1> INFO: Expecting 2560 events.
[15:25:11.550] <TB1> INFO: 2560 events read in total (290ms).
[15:25:11.550] <TB1> INFO: Test took 1187ms.
[15:25:11.554] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:11.858] <TB1> INFO: Expecting 2560 events.
[15:25:12.738] <TB1> INFO: 2560 events read in total (288ms).
[15:25:12.738] <TB1> INFO: Test took 1184ms.
[15:25:12.740] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:13.046] <TB1> INFO: Expecting 2560 events.
[15:25:13.927] <TB1> INFO: 2560 events read in total (289ms).
[15:25:13.927] <TB1> INFO: Test took 1187ms.
[15:25:13.930] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:14.234] <TB1> INFO: Expecting 2560 events.
[15:25:15.115] <TB1> INFO: 2560 events read in total (289ms).
[15:25:15.115] <TB1> INFO: Test took 1185ms.
[15:25:15.117] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:15.423] <TB1> INFO: Expecting 2560 events.
[15:25:16.303] <TB1> INFO: 2560 events read in total (289ms).
[15:25:16.303] <TB1> INFO: Test took 1186ms.
[15:25:16.306] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:16.611] <TB1> INFO: Expecting 2560 events.
[15:25:17.493] <TB1> INFO: 2560 events read in total (290ms).
[15:25:17.494] <TB1> INFO: Test took 1188ms.
[15:25:17.497] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:17.801] <TB1> INFO: Expecting 2560 events.
[15:25:18.685] <TB1> INFO: 2560 events read in total (292ms).
[15:25:18.686] <TB1> INFO: Test took 1189ms.
[15:25:18.688] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:18.995] <TB1> INFO: Expecting 2560 events.
[15:25:19.880] <TB1> INFO: 2560 events read in total (293ms).
[15:25:19.880] <TB1> INFO: Test took 1193ms.
[15:25:19.884] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:20.188] <TB1> INFO: Expecting 2560 events.
[15:25:21.076] <TB1> INFO: 2560 events read in total (296ms).
[15:25:21.077] <TB1> INFO: Test took 1193ms.
[15:25:21.081] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:21.384] <TB1> INFO: Expecting 2560 events.
[15:25:22.276] <TB1> INFO: 2560 events read in total (300ms).
[15:25:22.277] <TB1> INFO: Test took 1196ms.
[15:25:22.280] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:22.585] <TB1> INFO: Expecting 2560 events.
[15:25:23.469] <TB1> INFO: 2560 events read in total (293ms).
[15:25:23.469] <TB1> INFO: Test took 1189ms.
[15:25:23.471] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:23.778] <TB1> INFO: Expecting 2560 events.
[15:25:24.666] <TB1> INFO: 2560 events read in total (296ms).
[15:25:24.667] <TB1> INFO: Test took 1196ms.
[15:25:24.670] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:24.975] <TB1> INFO: Expecting 2560 events.
[15:25:25.858] <TB1> INFO: 2560 events read in total (292ms).
[15:25:25.859] <TB1> INFO: Test took 1189ms.
[15:25:25.862] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:26.167] <TB1> INFO: Expecting 2560 events.
[15:25:27.057] <TB1> INFO: 2560 events read in total (298ms).
[15:25:27.057] <TB1> INFO: Test took 1195ms.
[15:25:27.061] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:27.365] <TB1> INFO: Expecting 2560 events.
[15:25:28.249] <TB1> INFO: 2560 events read in total (293ms).
[15:25:28.249] <TB1> INFO: Test took 1188ms.
[15:25:28.252] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:28.558] <TB1> INFO: Expecting 2560 events.
[15:25:29.443] <TB1> INFO: 2560 events read in total (293ms).
[15:25:29.444] <TB1> INFO: Test took 1193ms.
[15:25:29.446] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:29.751] <TB1> INFO: Expecting 2560 events.
[15:25:30.639] <TB1> INFO: 2560 events read in total (296ms).
[15:25:30.639] <TB1> INFO: Test took 1193ms.
[15:25:30.641] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:30.948] <TB1> INFO: Expecting 2560 events.
[15:25:31.837] <TB1> INFO: 2560 events read in total (298ms).
[15:25:31.837] <TB1> INFO: Test took 1196ms.
[15:25:31.839] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:32.146] <TB1> INFO: Expecting 2560 events.
[15:25:33.031] <TB1> INFO: 2560 events read in total (294ms).
[15:25:33.032] <TB1> INFO: Test took 1193ms.
[15:25:33.034] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:33.340] <TB1> INFO: Expecting 2560 events.
[15:25:34.231] <TB1> INFO: 2560 events read in total (299ms).
[15:25:34.232] <TB1> INFO: Test took 1198ms.
[15:25:34.234] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:25:34.540] <TB1> INFO: Expecting 2560 events.
[15:25:35.425] <TB1> INFO: 2560 events read in total (294ms).
[15:25:35.425] <TB1> INFO: Test took 1192ms.
[15:25:35.898] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 663 seconds
[15:25:35.898] <TB1> INFO: PH scale (per ROC): 37 47 47 37 48 33 48 37 41 40 52 48 40 43 53 39
[15:25:35.898] <TB1> INFO: PH offset (per ROC): 105 93 99 79 114 103 106 102 92 94 118 114 99 106 124 97
[15:25:35.907] <TB1> INFO: Decoding statistics:
[15:25:35.907] <TB1> INFO: General information:
[15:25:35.907] <TB1> INFO: 16bit words read: 127888
[15:25:35.907] <TB1> INFO: valid events total: 20480
[15:25:35.907] <TB1> INFO: empty events: 17976
[15:25:35.907] <TB1> INFO: valid events with pixels: 2504
[15:25:35.907] <TB1> INFO: valid pixel hits: 2504
[15:25:35.907] <TB1> INFO: Event errors: 0
[15:25:35.907] <TB1> INFO: start marker: 0
[15:25:35.907] <TB1> INFO: stop marker: 0
[15:25:35.907] <TB1> INFO: overflow: 0
[15:25:35.907] <TB1> INFO: invalid 5bit words: 0
[15:25:35.907] <TB1> INFO: invalid XOR eye diagram: 0
[15:25:35.907] <TB1> INFO: frame (failed synchr.): 0
[15:25:35.907] <TB1> INFO: idle data (no TBM trl): 0
[15:25:35.907] <TB1> INFO: no data (only TBM hdr): 0
[15:25:35.907] <TB1> INFO: TBM errors: 0
[15:25:35.907] <TB1> INFO: flawed TBM headers: 0
[15:25:35.907] <TB1> INFO: flawed TBM trailers: 0
[15:25:35.907] <TB1> INFO: event ID mismatches: 0
[15:25:35.907] <TB1> INFO: ROC errors: 0
[15:25:35.907] <TB1> INFO: missing ROC header(s): 0
[15:25:35.907] <TB1> INFO: misplaced readback start: 0
[15:25:35.907] <TB1> INFO: Pixel decoding errors: 0
[15:25:35.907] <TB1> INFO: pixel data incomplete: 0
[15:25:35.907] <TB1> INFO: pixel address: 0
[15:25:35.907] <TB1> INFO: pulse height fill bit: 0
[15:25:35.907] <TB1> INFO: buffer corruption: 0
[15:25:36.070] <TB1> INFO: ######################################################################
[15:25:36.070] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[15:25:36.070] <TB1> INFO: ######################################################################
[15:25:36.084] <TB1> INFO: scanning low vcal = 10
[15:25:36.367] <TB1> INFO: Expecting 41600 events.
[15:25:39.960] <TB1> INFO: 41600 events read in total (3002ms).
[15:25:39.960] <TB1> INFO: Test took 3876ms.
[15:25:39.962] <TB1> INFO: scanning low vcal = 20
[15:25:40.261] <TB1> INFO: Expecting 41600 events.
[15:25:43.872] <TB1> INFO: 41600 events read in total (3019ms).
[15:25:43.872] <TB1> INFO: Test took 3910ms.
[15:25:43.874] <TB1> INFO: scanning low vcal = 30
[15:25:44.172] <TB1> INFO: Expecting 41600 events.
[15:25:47.829] <TB1> INFO: 41600 events read in total (3066ms).
[15:25:47.830] <TB1> INFO: Test took 3956ms.
[15:25:47.833] <TB1> INFO: scanning low vcal = 40
[15:25:48.109] <TB1> INFO: Expecting 41600 events.
[15:25:52.119] <TB1> INFO: 41600 events read in total (3418ms).
[15:25:52.120] <TB1> INFO: Test took 4286ms.
[15:25:52.123] <TB1> INFO: scanning low vcal = 50
[15:25:52.401] <TB1> INFO: Expecting 41600 events.
[15:25:56.442] <TB1> INFO: 41600 events read in total (3449ms).
[15:25:56.443] <TB1> INFO: Test took 4320ms.
[15:25:56.447] <TB1> INFO: scanning low vcal = 60
[15:25:56.724] <TB1> INFO: Expecting 41600 events.
[15:26:00.696] <TB1> INFO: 41600 events read in total (3380ms).
[15:26:00.697] <TB1> INFO: Test took 4250ms.
[15:26:00.700] <TB1> INFO: scanning low vcal = 70
[15:26:00.978] <TB1> INFO: Expecting 41600 events.
[15:26:04.975] <TB1> INFO: 41600 events read in total (3406ms).
[15:26:04.975] <TB1> INFO: Test took 4275ms.
[15:26:04.978] <TB1> INFO: scanning low vcal = 80
[15:26:05.256] <TB1> INFO: Expecting 41600 events.
[15:26:09.284] <TB1> INFO: 41600 events read in total (3436ms).
[15:26:09.284] <TB1> INFO: Test took 4306ms.
[15:26:09.288] <TB1> INFO: scanning low vcal = 90
[15:26:09.565] <TB1> INFO: Expecting 41600 events.
[15:26:13.564] <TB1> INFO: 41600 events read in total (3407ms).
[15:26:13.565] <TB1> INFO: Test took 4277ms.
[15:26:13.569] <TB1> INFO: scanning low vcal = 100
[15:26:13.846] <TB1> INFO: Expecting 41600 events.
[15:26:17.872] <TB1> INFO: 41600 events read in total (3435ms).
[15:26:17.873] <TB1> INFO: Test took 4304ms.
[15:26:17.876] <TB1> INFO: scanning low vcal = 110
[15:26:18.154] <TB1> INFO: Expecting 41600 events.
[15:26:22.149] <TB1> INFO: 41600 events read in total (3403ms).
[15:26:22.149] <TB1> INFO: Test took 4273ms.
[15:26:22.153] <TB1> INFO: scanning low vcal = 120
[15:26:22.429] <TB1> INFO: Expecting 41600 events.
[15:26:26.434] <TB1> INFO: 41600 events read in total (3413ms).
[15:26:26.434] <TB1> INFO: Test took 4282ms.
[15:26:26.438] <TB1> INFO: scanning low vcal = 130
[15:26:26.715] <TB1> INFO: Expecting 41600 events.
[15:26:30.714] <TB1> INFO: 41600 events read in total (3407ms).
[15:26:30.715] <TB1> INFO: Test took 4277ms.
[15:26:30.719] <TB1> INFO: scanning low vcal = 140
[15:26:30.996] <TB1> INFO: Expecting 41600 events.
[15:26:35.038] <TB1> INFO: 41600 events read in total (3450ms).
[15:26:35.039] <TB1> INFO: Test took 4320ms.
[15:26:35.042] <TB1> INFO: scanning low vcal = 150
[15:26:35.319] <TB1> INFO: Expecting 41600 events.
[15:26:39.335] <TB1> INFO: 41600 events read in total (3424ms).
[15:26:39.336] <TB1> INFO: Test took 4294ms.
[15:26:39.340] <TB1> INFO: scanning low vcal = 160
[15:26:39.617] <TB1> INFO: Expecting 41600 events.
[15:26:43.610] <TB1> INFO: 41600 events read in total (3401ms).
[15:26:43.611] <TB1> INFO: Test took 4271ms.
[15:26:43.614] <TB1> INFO: scanning low vcal = 170
[15:26:43.891] <TB1> INFO: Expecting 41600 events.
[15:26:47.883] <TB1> INFO: 41600 events read in total (3400ms).
[15:26:47.884] <TB1> INFO: Test took 4269ms.
[15:26:47.888] <TB1> INFO: scanning low vcal = 180
[15:26:48.165] <TB1> INFO: Expecting 41600 events.
[15:26:52.211] <TB1> INFO: 41600 events read in total (3455ms).
[15:26:52.212] <TB1> INFO: Test took 4323ms.
[15:26:52.215] <TB1> INFO: scanning low vcal = 190
[15:26:52.537] <TB1> INFO: Expecting 41600 events.
[15:26:56.518] <TB1> INFO: 41600 events read in total (3389ms).
[15:26:56.519] <TB1> INFO: Test took 4303ms.
[15:26:56.522] <TB1> INFO: scanning low vcal = 200
[15:26:56.800] <TB1> INFO: Expecting 41600 events.
[15:27:00.822] <TB1> INFO: 41600 events read in total (3431ms).
[15:27:00.822] <TB1> INFO: Test took 4301ms.
[15:27:00.826] <TB1> INFO: scanning low vcal = 210
[15:27:01.103] <TB1> INFO: Expecting 41600 events.
[15:27:05.145] <TB1> INFO: 41600 events read in total (3450ms).
[15:27:05.146] <TB1> INFO: Test took 4320ms.
[15:27:05.149] <TB1> INFO: scanning low vcal = 220
[15:27:05.427] <TB1> INFO: Expecting 41600 events.
[15:27:09.493] <TB1> INFO: 41600 events read in total (3475ms).
[15:27:09.494] <TB1> INFO: Test took 4345ms.
[15:27:09.497] <TB1> INFO: scanning low vcal = 230
[15:27:09.782] <TB1> INFO: Expecting 41600 events.
[15:27:13.841] <TB1> INFO: 41600 events read in total (3467ms).
[15:27:13.843] <TB1> INFO: Test took 4346ms.
[15:27:13.846] <TB1> INFO: scanning low vcal = 240
[15:27:14.123] <TB1> INFO: Expecting 41600 events.
[15:27:18.181] <TB1> INFO: 41600 events read in total (3466ms).
[15:27:18.182] <TB1> INFO: Test took 4336ms.
[15:27:18.185] <TB1> INFO: scanning low vcal = 250
[15:27:18.463] <TB1> INFO: Expecting 41600 events.
[15:27:22.470] <TB1> INFO: 41600 events read in total (3416ms).
[15:27:22.471] <TB1> INFO: Test took 4286ms.
[15:27:22.475] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[15:27:22.752] <TB1> INFO: Expecting 41600 events.
[15:27:26.770] <TB1> INFO: 41600 events read in total (3427ms).
[15:27:26.771] <TB1> INFO: Test took 4296ms.
[15:27:26.774] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[15:27:27.052] <TB1> INFO: Expecting 41600 events.
[15:27:31.051] <TB1> INFO: 41600 events read in total (3408ms).
[15:27:31.052] <TB1> INFO: Test took 4278ms.
[15:27:31.055] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[15:27:31.332] <TB1> INFO: Expecting 41600 events.
[15:27:35.380] <TB1> INFO: 41600 events read in total (3456ms).
[15:27:35.381] <TB1> INFO: Test took 4326ms.
[15:27:35.385] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[15:27:35.662] <TB1> INFO: Expecting 41600 events.
[15:27:39.690] <TB1> INFO: 41600 events read in total (3436ms).
[15:27:39.691] <TB1> INFO: Test took 4306ms.
[15:27:39.694] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[15:27:39.971] <TB1> INFO: Expecting 41600 events.
[15:27:44.010] <TB1> INFO: 41600 events read in total (3447ms).
[15:27:44.011] <TB1> INFO: Test took 4317ms.
[15:27:44.410] <TB1> INFO: PixTestGainPedestal::measure() done
[15:28:17.142] <TB1> INFO: PixTestGainPedestal::fit() done
[15:28:17.142] <TB1> INFO: non-linearity mean: 0.917 0.931 0.954 0.926 0.965 0.912 0.961 0.923 0.931 0.945 0.968 0.973 0.946 0.933 0.983 0.926
[15:28:17.142] <TB1> INFO: non-linearity RMS: 0.111 0.062 0.028 0.129 0.021 0.161 0.045 0.154 0.155 0.165 0.014 0.007 0.049 0.095 0.004 0.094
[15:28:17.142] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C0.dat
[15:28:17.157] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C1.dat
[15:28:17.170] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C2.dat
[15:28:17.183] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C3.dat
[15:28:17.196] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C4.dat
[15:28:17.209] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C5.dat
[15:28:17.222] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C6.dat
[15:28:17.235] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C7.dat
[15:28:17.248] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C8.dat
[15:28:17.261] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C9.dat
[15:28:17.274] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C10.dat
[15:28:17.288] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C11.dat
[15:28:17.301] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C12.dat
[15:28:17.314] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C13.dat
[15:28:17.327] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C14.dat
[15:28:17.340] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//003_Fulltest_p17//phCalibrationFitErr35_C15.dat
[15:28:17.353] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 161 seconds
[15:28:17.353] <TB1> INFO: Decoding statistics:
[15:28:17.353] <TB1> INFO: General information:
[15:28:17.353] <TB1> INFO: 16bit words read: 3289066
[15:28:17.353] <TB1> INFO: valid events total: 332800
[15:28:17.353] <TB1> INFO: empty events: 197
[15:28:17.353] <TB1> INFO: valid events with pixels: 332603
[15:28:17.353] <TB1> INFO: valid pixel hits: 646133
[15:28:17.353] <TB1> INFO: Event errors: 0
[15:28:17.353] <TB1> INFO: start marker: 0
[15:28:17.353] <TB1> INFO: stop marker: 0
[15:28:17.353] <TB1> INFO: overflow: 0
[15:28:17.353] <TB1> INFO: invalid 5bit words: 0
[15:28:17.353] <TB1> INFO: invalid XOR eye diagram: 0
[15:28:17.353] <TB1> INFO: frame (failed synchr.): 0
[15:28:17.353] <TB1> INFO: idle data (no TBM trl): 0
[15:28:17.353] <TB1> INFO: no data (only TBM hdr): 0
[15:28:17.353] <TB1> INFO: TBM errors: 0
[15:28:17.353] <TB1> INFO: flawed TBM headers: 0
[15:28:17.353] <TB1> INFO: flawed TBM trailers: 0
[15:28:17.353] <TB1> INFO: event ID mismatches: 0
[15:28:17.353] <TB1> INFO: ROC errors: 0
[15:28:17.353] <TB1> INFO: missing ROC header(s): 0
[15:28:17.354] <TB1> INFO: misplaced readback start: 0
[15:28:17.354] <TB1> INFO: Pixel decoding errors: 0
[15:28:17.354] <TB1> INFO: pixel data incomplete: 0
[15:28:17.354] <TB1> INFO: pixel address: 0
[15:28:17.354] <TB1> INFO: pulse height fill bit: 0
[15:28:17.354] <TB1> INFO: buffer corruption: 0
[15:28:17.371] <TB1> INFO: Decoding statistics:
[15:28:17.371] <TB1> INFO: General information:
[15:28:17.371] <TB1> INFO: 16bit words read: 3418490
[15:28:17.371] <TB1> INFO: valid events total: 353536
[15:28:17.371] <TB1> INFO: empty events: 18429
[15:28:17.371] <TB1> INFO: valid events with pixels: 335107
[15:28:17.371] <TB1> INFO: valid pixel hits: 648637
[15:28:17.371] <TB1> INFO: Event errors: 0
[15:28:17.371] <TB1> INFO: start marker: 0
[15:28:17.371] <TB1> INFO: stop marker: 0
[15:28:17.372] <TB1> INFO: overflow: 0
[15:28:17.372] <TB1> INFO: invalid 5bit words: 0
[15:28:17.372] <TB1> INFO: invalid XOR eye diagram: 0
[15:28:17.372] <TB1> INFO: frame (failed synchr.): 0
[15:28:17.372] <TB1> INFO: idle data (no TBM trl): 0
[15:28:17.372] <TB1> INFO: no data (only TBM hdr): 0
[15:28:17.372] <TB1> INFO: TBM errors: 0
[15:28:17.372] <TB1> INFO: flawed TBM headers: 0
[15:28:17.372] <TB1> INFO: flawed TBM trailers: 0
[15:28:17.372] <TB1> INFO: event ID mismatches: 0
[15:28:17.372] <TB1> INFO: ROC errors: 0
[15:28:17.372] <TB1> INFO: missing ROC header(s): 0
[15:28:17.372] <TB1> INFO: misplaced readback start: 0
[15:28:17.372] <TB1> INFO: Pixel decoding errors: 0
[15:28:17.372] <TB1> INFO: pixel data incomplete: 0
[15:28:17.372] <TB1> INFO: pixel address: 0
[15:28:17.372] <TB1> INFO: pulse height fill bit: 0
[15:28:17.372] <TB1> INFO: buffer corruption: 0
[15:28:17.372] <TB1> INFO: enter test to run
[15:28:17.372] <TB1> INFO: test: exit no parameter change
[15:28:17.502] <TB1> QUIET: Connection to board 154 closed.
[15:28:17.503] <TB1> INFO: pXar: this is the end, my friend