[12:25:52.848] <TB1> INFO: *** Welcome to pxar ***
[12:25:52.848] <TB1> INFO: *** Today: 2016/10/24
[12:25:52.857] <TB1> INFO: *** Version: c8ba-dirty
[12:25:52.857] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C15.dat
[12:25:52.857] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C1b.dat
[12:25:52.857] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//defaultMaskFile.dat
[12:25:52.857] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters_C15.dat
[12:25:52.919] <TB1> INFO: clk: 4
[12:25:52.919] <TB1> INFO: ctr: 4
[12:25:52.919] <TB1> INFO: sda: 19
[12:25:52.919] <TB1> INFO: tin: 9
[12:25:52.919] <TB1> INFO: level: 15
[12:25:52.919] <TB1> INFO: triggerdelay: 0
[12:25:52.919] <TB1> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[12:25:52.919] <TB1> INFO: Log level: INFO
[12:25:52.927] <TB1> INFO: Found DTB DTB_WXC03A
[12:25:52.939] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[12:25:52.941] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
------------------------------------------------------
[12:25:52.943] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[12:25:54.435] <TB1> INFO: DUT info:
[12:25:54.435] <TB1> INFO: The DUT currently contains the following objects:
[12:25:54.435] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[12:25:54.435] <TB1> INFO: TBM Core alpha (0): 7 registers set
[12:25:54.435] <TB1> INFO: TBM Core beta (1): 7 registers set
[12:25:54.435] <TB1> INFO: TBM Core alpha (2): 7 registers set
[12:25:54.435] <TB1> INFO: TBM Core beta (3): 7 registers set
[12:25:54.435] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[12:25:54.435] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:54.435] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:54.435] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:54.435] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:54.435] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:54.435] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:54.435] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:54.435] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:54.435] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:54.435] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:54.435] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:54.435] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:54.435] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:54.435] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:54.435] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:54.435] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:54.836] <TB1> INFO: enter 'restricted' command line mode
[12:25:54.836] <TB1> INFO: enter test to run
[12:25:54.836] <TB1> INFO: test: pretest no parameter change
[12:25:54.836] <TB1> INFO: running: pretest
[12:25:54.842] <TB1> INFO: ######################################################################
[12:25:54.842] <TB1> INFO: PixTestPretest::doTest()
[12:25:54.842] <TB1> INFO: ######################################################################
[12:25:54.843] <TB1> INFO: ----------------------------------------------------------------------
[12:25:54.843] <TB1> INFO: PixTestPretest::programROC()
[12:25:54.843] <TB1> INFO: ----------------------------------------------------------------------
[12:26:12.857] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:26:12.857] <TB1> INFO: IA differences per ROC: 21.7 18.5 18.5 17.7 19.3 20.1 20.9 20.9 18.5 19.3 21.7 17.7 20.1 18.5 20.1 17.7
[12:26:12.916] <TB1> INFO: ----------------------------------------------------------------------
[12:26:12.916] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:26:12.916] <TB1> INFO: ----------------------------------------------------------------------
[12:26:34.203] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 385.1 mA = 24.0688 mA/ROC
[12:26:34.203] <TB1> INFO: i(loss) [mA/ROC]: 19.3 20.9 20.9 20.9 19.3 19.3 19.3 20.1 20.1 19.3 19.3 20.9 19.3 20.1 19.3 20.1
[12:26:34.237] <TB1> INFO: ----------------------------------------------------------------------
[12:26:34.237] <TB1> INFO: PixTestPretest::findTiming()
[12:26:34.237] <TB1> INFO: ----------------------------------------------------------------------
[12:26:34.237] <TB1> INFO: PixTestCmd::init()

[12:27:06.599] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[12:27:06.599] <TB1> INFO: (success/tries = 100/100), width = 4
[12:27:08.105] <TB1> INFO: ----------------------------------------------------------------------
[12:27:08.105] <TB1> INFO: PixTestPretest::findWorkingPixel()
[12:27:08.105] <TB1> INFO: ----------------------------------------------------------------------
[12:27:08.200] <TB1> INFO: Expecting 231680 events.
[12:27:18.005] <TB1> INFO: 231680 events read in total (9213ms).
[12:27:18.014] <TB1> INFO: Test took 9904ms.
[12:27:18.255] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:27:18.287] <TB1> INFO: ----------------------------------------------------------------------
[12:27:18.287] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[12:27:18.287] <TB1> INFO: ----------------------------------------------------------------------
[12:27:18.380] <TB1> INFO: Expecting 231680 events.
[12:27:28.139] <TB1> INFO: 231680 events read in total (9167ms).
[12:27:28.150] <TB1> INFO: Test took 9859ms.
[12:27:28.412] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[12:27:28.412] <TB1> INFO: CalDel: 87 98 106 133 101 94 125 108 111 113 108 88 98 98 86 106
[12:27:28.412] <TB1> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[12:27:28.418] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C0.dat
[12:27:28.419] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C1.dat
[12:27:28.419] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C2.dat
[12:27:28.419] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C3.dat
[12:27:28.419] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C4.dat
[12:27:28.419] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C5.dat
[12:27:28.419] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C6.dat
[12:27:28.420] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C7.dat
[12:27:28.420] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C8.dat
[12:27:28.420] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C9.dat
[12:27:28.420] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C10.dat
[12:27:28.420] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C11.dat
[12:27:28.420] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C12.dat
[12:27:28.420] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C13.dat
[12:27:28.421] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C14.dat
[12:27:28.421] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C15.dat
[12:27:28.421] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C0a.dat
[12:27:28.421] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C0b.dat
[12:27:28.421] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C1a.dat
[12:27:28.421] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C1b.dat
[12:27:28.421] <TB1> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[12:27:28.477] <TB1> INFO: enter test to run
[12:27:28.477] <TB1> INFO: test: FullTest no parameter change
[12:27:28.477] <TB1> INFO: running: fulltest
[12:27:28.477] <TB1> INFO: ######################################################################
[12:27:28.477] <TB1> INFO: PixTestFullTest::doTest()
[12:27:28.477] <TB1> INFO: ######################################################################
[12:27:28.478] <TB1> INFO: ######################################################################
[12:27:28.478] <TB1> INFO: PixTestAlive::doTest()
[12:27:28.478] <TB1> INFO: ######################################################################
[12:27:28.479] <TB1> INFO: ----------------------------------------------------------------------
[12:27:28.480] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:27:28.480] <TB1> INFO: ----------------------------------------------------------------------
[12:27:28.725] <TB1> INFO: Expecting 41600 events.
[12:27:32.278] <TB1> INFO: 41600 events read in total (2961ms).
[12:27:32.278] <TB1> INFO: Test took 3797ms.
[12:27:32.507] <TB1> INFO: PixTestAlive::aliveTest() done
[12:27:32.507] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:27:32.508] <TB1> INFO: ----------------------------------------------------------------------
[12:27:32.509] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:27:32.509] <TB1> INFO: ----------------------------------------------------------------------
[12:27:32.759] <TB1> INFO: Expecting 41600 events.
[12:27:35.713] <TB1> INFO: 41600 events read in total (2363ms).
[12:27:35.713] <TB1> INFO: Test took 3203ms.
[12:27:35.714] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:27:35.953] <TB1> INFO: PixTestAlive::maskTest() done
[12:27:35.953] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:27:35.954] <TB1> INFO: ----------------------------------------------------------------------
[12:27:35.954] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:27:35.955] <TB1> INFO: ----------------------------------------------------------------------
[12:27:36.198] <TB1> INFO: Expecting 41600 events.
[12:27:39.702] <TB1> INFO: 41600 events read in total (2912ms).
[12:27:39.703] <TB1> INFO: Test took 3747ms.
[12:27:39.937] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[12:27:39.937] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:27:39.938] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[12:27:39.938] <TB1> INFO: Decoding statistics:
[12:27:39.938] <TB1> INFO: General information:
[12:27:39.938] <TB1> INFO: 16bit words read: 0
[12:27:39.938] <TB1> INFO: valid events total: 0
[12:27:39.938] <TB1> INFO: empty events: 0
[12:27:39.938] <TB1> INFO: valid events with pixels: 0
[12:27:39.938] <TB1> INFO: valid pixel hits: 0
[12:27:39.938] <TB1> INFO: Event errors: 0
[12:27:39.938] <TB1> INFO: start marker: 0
[12:27:39.938] <TB1> INFO: stop marker: 0
[12:27:39.938] <TB1> INFO: overflow: 0
[12:27:39.938] <TB1> INFO: invalid 5bit words: 0
[12:27:39.938] <TB1> INFO: invalid XOR eye diagram: 0
[12:27:39.938] <TB1> INFO: frame (failed synchr.): 0
[12:27:39.938] <TB1> INFO: idle data (no TBM trl): 0
[12:27:39.938] <TB1> INFO: no data (only TBM hdr): 0
[12:27:39.938] <TB1> INFO: TBM errors: 0
[12:27:39.938] <TB1> INFO: flawed TBM headers: 0
[12:27:39.938] <TB1> INFO: flawed TBM trailers: 0
[12:27:39.938] <TB1> INFO: event ID mismatches: 0
[12:27:39.938] <TB1> INFO: ROC errors: 0
[12:27:39.938] <TB1> INFO: missing ROC header(s): 0
[12:27:39.938] <TB1> INFO: misplaced readback start: 0
[12:27:39.938] <TB1> INFO: Pixel decoding errors: 0
[12:27:39.938] <TB1> INFO: pixel data incomplete: 0
[12:27:39.938] <TB1> INFO: pixel address: 0
[12:27:39.938] <TB1> INFO: pulse height fill bit: 0
[12:27:39.938] <TB1> INFO: buffer corruption: 0
[12:27:39.945] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C15.dat
[12:27:39.945] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[12:27:39.945] <TB1> INFO: ######################################################################
[12:27:39.945] <TB1> INFO: PixTestReadback::doTest()
[12:27:39.945] <TB1> INFO: ######################################################################
[12:27:39.945] <TB1> INFO: ----------------------------------------------------------------------
[12:27:39.945] <TB1> INFO: PixTestReadback::CalibrateVd()
[12:27:39.945] <TB1> INFO: ----------------------------------------------------------------------
[12:27:49.900] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C0.dat
[12:27:49.901] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C1.dat
[12:27:49.901] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C2.dat
[12:27:49.901] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C3.dat
[12:27:49.901] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C4.dat
[12:27:49.901] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C5.dat
[12:27:49.901] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C6.dat
[12:27:49.901] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C7.dat
[12:27:49.901] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C8.dat
[12:27:49.901] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C9.dat
[12:27:49.901] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C10.dat
[12:27:49.901] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C11.dat
[12:27:49.901] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C12.dat
[12:27:49.901] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C13.dat
[12:27:49.901] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C14.dat
[12:27:49.901] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C15.dat
[12:27:49.930] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:27:49.930] <TB1> INFO: ----------------------------------------------------------------------
[12:27:49.930] <TB1> INFO: PixTestReadback::CalibrateVa()
[12:27:49.930] <TB1> INFO: ----------------------------------------------------------------------
[12:27:59.847] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C0.dat
[12:27:59.847] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C1.dat
[12:27:59.847] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C2.dat
[12:27:59.847] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C3.dat
[12:27:59.847] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C4.dat
[12:27:59.847] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C5.dat
[12:27:59.847] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C6.dat
[12:27:59.847] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C7.dat
[12:27:59.847] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C8.dat
[12:27:59.847] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C9.dat
[12:27:59.847] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C10.dat
[12:27:59.847] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C11.dat
[12:27:59.847] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C12.dat
[12:27:59.848] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C13.dat
[12:27:59.848] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C14.dat
[12:27:59.848] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C15.dat
[12:27:59.876] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:27:59.877] <TB1> INFO: ----------------------------------------------------------------------
[12:27:59.877] <TB1> INFO: PixTestReadback::readbackVbg()
[12:27:59.877] <TB1> INFO: ----------------------------------------------------------------------
[12:28:07.554] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:28:07.554] <TB1> INFO: ----------------------------------------------------------------------
[12:28:07.554] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[12:28:07.554] <TB1> INFO: ----------------------------------------------------------------------
[12:28:07.554] <TB1> INFO: Vbg will be calibrated using Vd calibration
[12:28:07.554] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 149.2calibrated Vbg = 1.1756 :::*/*/*/*/
[12:28:07.554] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 161.1calibrated Vbg = 1.17126 :::*/*/*/*/
[12:28:07.554] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 150.9calibrated Vbg = 1.17625 :::*/*/*/*/
[12:28:07.555] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 160.8calibrated Vbg = 1.17965 :::*/*/*/*/
[12:28:07.555] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 161.2calibrated Vbg = 1.17024 :::*/*/*/*/
[12:28:07.555] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 152.1calibrated Vbg = 1.18458 :::*/*/*/*/
[12:28:07.555] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 144.6calibrated Vbg = 1.1828 :::*/*/*/*/
[12:28:07.555] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 145.6calibrated Vbg = 1.18642 :::*/*/*/*/
[12:28:07.555] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 166.5calibrated Vbg = 1.17153 :::*/*/*/*/
[12:28:07.555] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 155.1calibrated Vbg = 1.17159 :::*/*/*/*/
[12:28:07.555] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 147.1calibrated Vbg = 1.16661 :::*/*/*/*/
[12:28:07.555] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 170.3calibrated Vbg = 1.16645 :::*/*/*/*/
[12:28:07.555] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 152.9calibrated Vbg = 1.17266 :::*/*/*/*/
[12:28:07.555] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 161.4calibrated Vbg = 1.17998 :::*/*/*/*/
[12:28:07.555] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 161calibrated Vbg = 1.16893 :::*/*/*/*/
[12:28:07.555] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 153.8calibrated Vbg = 1.17945 :::*/*/*/*/
[12:28:07.557] <TB1> INFO: ----------------------------------------------------------------------
[12:28:07.557] <TB1> INFO: PixTestReadback::CalibrateIa()
[12:28:07.557] <TB1> INFO: ----------------------------------------------------------------------
[12:30:48.412] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C0.dat
[12:30:48.412] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C1.dat
[12:30:48.412] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C2.dat
[12:30:48.412] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C3.dat
[12:30:48.412] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C4.dat
[12:30:48.412] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C5.dat
[12:30:48.412] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C6.dat
[12:30:48.412] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C7.dat
[12:30:48.412] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C8.dat
[12:30:48.413] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C9.dat
[12:30:48.413] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C10.dat
[12:30:48.413] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C11.dat
[12:30:48.413] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C12.dat
[12:30:48.413] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C13.dat
[12:30:48.413] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C14.dat
[12:30:48.413] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C15.dat
[12:30:48.443] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:30:48.444] <TB1> INFO: PixTestReadback::doTest() done
[12:30:48.445] <TB1> INFO: Decoding statistics:
[12:30:48.445] <TB1> INFO: General information:
[12:30:48.445] <TB1> INFO: 16bit words read: 1536
[12:30:48.445] <TB1> INFO: valid events total: 256
[12:30:48.445] <TB1> INFO: empty events: 256
[12:30:48.445] <TB1> INFO: valid events with pixels: 0
[12:30:48.445] <TB1> INFO: valid pixel hits: 0
[12:30:48.445] <TB1> INFO: Event errors: 0
[12:30:48.445] <TB1> INFO: start marker: 0
[12:30:48.445] <TB1> INFO: stop marker: 0
[12:30:48.445] <TB1> INFO: overflow: 0
[12:30:48.445] <TB1> INFO: invalid 5bit words: 0
[12:30:48.445] <TB1> INFO: invalid XOR eye diagram: 0
[12:30:48.445] <TB1> INFO: frame (failed synchr.): 0
[12:30:48.445] <TB1> INFO: idle data (no TBM trl): 0
[12:30:48.445] <TB1> INFO: no data (only TBM hdr): 0
[12:30:48.445] <TB1> INFO: TBM errors: 0
[12:30:48.445] <TB1> INFO: flawed TBM headers: 0
[12:30:48.445] <TB1> INFO: flawed TBM trailers: 0
[12:30:48.445] <TB1> INFO: event ID mismatches: 0
[12:30:48.445] <TB1> INFO: ROC errors: 0
[12:30:48.445] <TB1> INFO: missing ROC header(s): 0
[12:30:48.445] <TB1> INFO: misplaced readback start: 0
[12:30:48.445] <TB1> INFO: Pixel decoding errors: 0
[12:30:48.445] <TB1> INFO: pixel data incomplete: 0
[12:30:48.445] <TB1> INFO: pixel address: 0
[12:30:48.445] <TB1> INFO: pulse height fill bit: 0
[12:30:48.445] <TB1> INFO: buffer corruption: 0
[12:30:48.497] <TB1> INFO: ######################################################################
[12:30:48.498] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:30:48.498] <TB1> INFO: ######################################################################
[12:30:48.500] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:30:48.514] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:30:48.514] <TB1> INFO: run 1 of 1
[12:30:48.754] <TB1> INFO: Expecting 3120000 events.
[12:31:19.568] <TB1> INFO: 663030 events read in total (30222ms).











[12:31:49.591] <TB1> INFO: 1318025 events read in total (60245ms).











[12:32:19.592] <TB1> INFO: 1968735 events read in total (90246ms).











[12:32:49.658] <TB1> INFO: 2619675 events read in total (120312ms).











[12:33:13.053] <TB1> INFO: 3120000 events read in total (143707ms).
[12:33:13.119] <TB1> INFO: Test took 144606ms.
[12:33:39.678] <TB1> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 171 seconds
[12:33:39.678] <TB1> INFO: number of dead bumps (per ROC): 9 14 2 0 0 0 0 0 0 0 1 0 6 5 7 6
[12:33:39.678] <TB1> INFO: separation cut (per ROC): 106 103 103 97 105 104 97 99 109 99 109 108 105 104 116 108
[12:33:39.678] <TB1> INFO: Decoding statistics:
[12:33:39.678] <TB1> INFO: General information:
[12:33:39.678] <TB1> INFO: 16bit words read: 0
[12:33:39.678] <TB1> INFO: valid events total: 0
[12:33:39.678] <TB1> INFO: empty events: 0
[12:33:39.678] <TB1> INFO: valid events with pixels: 0
[12:33:39.678] <TB1> INFO: valid pixel hits: 0
[12:33:39.678] <TB1> INFO: Event errors: 0
[12:33:39.678] <TB1> INFO: start marker: 0
[12:33:39.678] <TB1> INFO: stop marker: 0
[12:33:39.678] <TB1> INFO: overflow: 0
[12:33:39.678] <TB1> INFO: invalid 5bit words: 0
[12:33:39.678] <TB1> INFO: invalid XOR eye diagram: 0
[12:33:39.678] <TB1> INFO: frame (failed synchr.): 0
[12:33:39.678] <TB1> INFO: idle data (no TBM trl): 0
[12:33:39.678] <TB1> INFO: no data (only TBM hdr): 0
[12:33:39.678] <TB1> INFO: TBM errors: 0
[12:33:39.678] <TB1> INFO: flawed TBM headers: 0
[12:33:39.678] <TB1> INFO: flawed TBM trailers: 0
[12:33:39.678] <TB1> INFO: event ID mismatches: 0
[12:33:39.678] <TB1> INFO: ROC errors: 0
[12:33:39.678] <TB1> INFO: missing ROC header(s): 0
[12:33:39.678] <TB1> INFO: misplaced readback start: 0
[12:33:39.678] <TB1> INFO: Pixel decoding errors: 0
[12:33:39.678] <TB1> INFO: pixel data incomplete: 0
[12:33:39.678] <TB1> INFO: pixel address: 0
[12:33:39.678] <TB1> INFO: pulse height fill bit: 0
[12:33:39.678] <TB1> INFO: buffer corruption: 0
[12:33:39.731] <TB1> INFO: ######################################################################
[12:33:39.731] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:33:39.731] <TB1> INFO: ######################################################################
[12:33:39.731] <TB1> INFO: ----------------------------------------------------------------------
[12:33:39.731] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:33:39.731] <TB1> INFO: ----------------------------------------------------------------------
[12:33:39.731] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:33:39.745] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[12:33:39.745] <TB1> INFO: run 1 of 1
[12:33:40.016] <TB1> INFO: Expecting 36608000 events.
[12:34:03.467] <TB1> INFO: 661400 events read in total (22859ms).
[12:34:26.121] <TB1> INFO: 1310650 events read in total (45513ms).
[12:34:49.108] <TB1> INFO: 1960950 events read in total (68500ms).
[12:35:11.778] <TB1> INFO: 2611000 events read in total (91170ms).
[12:35:34.713] <TB1> INFO: 3260550 events read in total (114105ms).
[12:35:57.322] <TB1> INFO: 3908550 events read in total (136714ms).
[12:36:19.998] <TB1> INFO: 4555250 events read in total (159390ms).
[12:36:42.644] <TB1> INFO: 5202750 events read in total (182036ms).
[12:37:05.507] <TB1> INFO: 5849100 events read in total (204899ms).
[12:37:28.408] <TB1> INFO: 6497100 events read in total (227800ms).
[12:37:51.018] <TB1> INFO: 7143400 events read in total (250410ms).
[12:38:13.727] <TB1> INFO: 7789300 events read in total (273119ms).
[12:38:36.532] <TB1> INFO: 8436150 events read in total (295924ms).
[12:38:59.180] <TB1> INFO: 9080300 events read in total (318572ms).
[12:39:21.535] <TB1> INFO: 9724550 events read in total (340927ms).
[12:39:43.981] <TB1> INFO: 10369800 events read in total (363373ms).
[12:40:06.647] <TB1> INFO: 11013350 events read in total (386039ms).
[12:40:29.034] <TB1> INFO: 11656400 events read in total (408426ms).
[12:40:51.230] <TB1> INFO: 12298600 events read in total (430622ms).
[12:41:13.587] <TB1> INFO: 12941100 events read in total (452979ms).
[12:41:36.022] <TB1> INFO: 13583750 events read in total (475414ms).
[12:41:58.494] <TB1> INFO: 14225800 events read in total (497886ms).
[12:42:21.031] <TB1> INFO: 14867000 events read in total (520423ms).
[12:42:43.309] <TB1> INFO: 15508050 events read in total (542701ms).
[12:43:05.609] <TB1> INFO: 16147650 events read in total (565001ms).
[12:43:28.042] <TB1> INFO: 16788200 events read in total (587434ms).
[12:43:50.433] <TB1> INFO: 17430000 events read in total (609825ms).
[12:44:12.811] <TB1> INFO: 18070900 events read in total (632203ms).
[12:44:35.302] <TB1> INFO: 18709750 events read in total (654694ms).
[12:44:57.489] <TB1> INFO: 19347900 events read in total (676881ms).
[12:45:20.036] <TB1> INFO: 19984550 events read in total (699428ms).
[12:45:42.416] <TB1> INFO: 20622500 events read in total (721808ms).
[12:46:04.670] <TB1> INFO: 21258500 events read in total (744062ms).
[12:46:27.101] <TB1> INFO: 21896300 events read in total (766493ms).
[12:46:49.295] <TB1> INFO: 22532050 events read in total (788687ms).
[12:47:11.605] <TB1> INFO: 23167750 events read in total (810997ms).
[12:47:34.109] <TB1> INFO: 23804700 events read in total (833501ms).
[12:47:56.240] <TB1> INFO: 24442400 events read in total (855632ms).
[12:48:18.718] <TB1> INFO: 25079600 events read in total (878110ms).
[12:48:41.083] <TB1> INFO: 25717250 events read in total (900475ms).
[12:49:03.462] <TB1> INFO: 26353850 events read in total (922854ms).
[12:49:25.759] <TB1> INFO: 26989400 events read in total (945151ms).
[12:49:48.138] <TB1> INFO: 27626300 events read in total (967530ms).
[12:50:10.744] <TB1> INFO: 28262000 events read in total (990136ms).
[12:50:33.025] <TB1> INFO: 28897850 events read in total (1012417ms).
[12:50:55.443] <TB1> INFO: 29532150 events read in total (1034835ms).
[12:51:17.740] <TB1> INFO: 30167200 events read in total (1057132ms).
[12:51:40.286] <TB1> INFO: 30799900 events read in total (1079678ms).
[12:52:02.805] <TB1> INFO: 31434950 events read in total (1102197ms).
[12:52:25.172] <TB1> INFO: 32070700 events read in total (1124564ms).
[12:52:47.639] <TB1> INFO: 32706050 events read in total (1147031ms).
[12:53:10.040] <TB1> INFO: 33342200 events read in total (1169432ms).
[12:53:32.309] <TB1> INFO: 33978950 events read in total (1191701ms).
[12:53:54.540] <TB1> INFO: 34615450 events read in total (1213932ms).
[12:54:16.831] <TB1> INFO: 35250350 events read in total (1236223ms).
[12:54:39.233] <TB1> INFO: 35887550 events read in total (1258626ms).
[12:55:01.735] <TB1> INFO: 36534400 events read in total (1281127ms).
[12:55:04.822] <TB1> INFO: 36608000 events read in total (1284214ms).
[12:55:04.936] <TB1> INFO: Test took 1285190ms.
[12:55:05.569] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:55:07.726] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:55:10.134] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:55:12.397] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:55:14.558] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:55:16.788] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:55:18.648] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:55:20.984] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:55:23.513] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:55:26.042] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:55:28.583] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:55:31.099] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:55:33.701] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:55:35.880] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:55:37.632] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:55:39.394] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:55:41.460] <TB1> INFO: PixTestScurves::scurves() done
[12:55:41.460] <TB1> INFO: Vcal mean: 114.47 102.10 103.88 105.93 113.30 110.47 98.95 99.64 121.37 108.54 114.77 114.14 108.48 108.96 119.96 117.76
[12:55:41.461] <TB1> INFO: Vcal RMS: 5.10 5.46 5.00 4.97 5.82 5.01 5.24 5.44 5.88 5.17 6.00 5.53 5.10 5.22 5.93 6.17
[12:55:41.461] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1321 seconds
[12:55:41.461] <TB1> INFO: Decoding statistics:
[12:55:41.461] <TB1> INFO: General information:
[12:55:41.461] <TB1> INFO: 16bit words read: 0
[12:55:41.461] <TB1> INFO: valid events total: 0
[12:55:41.461] <TB1> INFO: empty events: 0
[12:55:41.461] <TB1> INFO: valid events with pixels: 0
[12:55:41.461] <TB1> INFO: valid pixel hits: 0
[12:55:41.461] <TB1> INFO: Event errors: 0
[12:55:41.461] <TB1> INFO: start marker: 0
[12:55:41.461] <TB1> INFO: stop marker: 0
[12:55:41.461] <TB1> INFO: overflow: 0
[12:55:41.461] <TB1> INFO: invalid 5bit words: 0
[12:55:41.461] <TB1> INFO: invalid XOR eye diagram: 0
[12:55:41.461] <TB1> INFO: frame (failed synchr.): 0
[12:55:41.461] <TB1> INFO: idle data (no TBM trl): 0
[12:55:41.461] <TB1> INFO: no data (only TBM hdr): 0
[12:55:41.461] <TB1> INFO: TBM errors: 0
[12:55:41.461] <TB1> INFO: flawed TBM headers: 0
[12:55:41.461] <TB1> INFO: flawed TBM trailers: 0
[12:55:41.461] <TB1> INFO: event ID mismatches: 0
[12:55:41.461] <TB1> INFO: ROC errors: 0
[12:55:41.461] <TB1> INFO: missing ROC header(s): 0
[12:55:41.461] <TB1> INFO: misplaced readback start: 0
[12:55:41.461] <TB1> INFO: Pixel decoding errors: 0
[12:55:41.461] <TB1> INFO: pixel data incomplete: 0
[12:55:41.461] <TB1> INFO: pixel address: 0
[12:55:41.461] <TB1> INFO: pulse height fill bit: 0
[12:55:41.461] <TB1> INFO: buffer corruption: 0
[12:55:41.529] <TB1> INFO: ######################################################################
[12:55:41.529] <TB1> INFO: PixTestTrim::doTest()
[12:55:41.529] <TB1> INFO: ######################################################################
[12:55:41.530] <TB1> INFO: ----------------------------------------------------------------------
[12:55:41.530] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:55:41.530] <TB1> INFO: ----------------------------------------------------------------------
[12:55:41.574] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:55:41.574] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:55:41.586] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:55:41.586] <TB1> INFO: run 1 of 1
[12:55:41.823] <TB1> INFO: Expecting 5025280 events.
[12:56:12.013] <TB1> INFO: 812176 events read in total (29590ms).
[12:56:41.841] <TB1> INFO: 1619496 events read in total (59418ms).
[12:57:11.546] <TB1> INFO: 2422016 events read in total (89124ms).
[12:57:41.012] <TB1> INFO: 3221272 events read in total (118589ms).
[12:58:10.584] <TB1> INFO: 4016760 events read in total (148161ms).
[12:58:40.800] <TB1> INFO: 4808776 events read in total (178377ms).
[12:58:49.465] <TB1> INFO: 5025280 events read in total (187042ms).
[12:58:49.535] <TB1> INFO: Test took 187950ms.
[12:59:07.845] <TB1> INFO: ROC 0 VthrComp = 131
[12:59:07.845] <TB1> INFO: ROC 1 VthrComp = 112
[12:59:07.845] <TB1> INFO: ROC 2 VthrComp = 113
[12:59:07.845] <TB1> INFO: ROC 3 VthrComp = 111
[12:59:07.845] <TB1> INFO: ROC 4 VthrComp = 119
[12:59:07.845] <TB1> INFO: ROC 5 VthrComp = 122
[12:59:07.845] <TB1> INFO: ROC 6 VthrComp = 108
[12:59:07.846] <TB1> INFO: ROC 7 VthrComp = 110
[12:59:07.846] <TB1> INFO: ROC 8 VthrComp = 131
[12:59:07.846] <TB1> INFO: ROC 9 VthrComp = 112
[12:59:07.846] <TB1> INFO: ROC 10 VthrComp = 127
[12:59:07.846] <TB1> INFO: ROC 11 VthrComp = 126
[12:59:07.846] <TB1> INFO: ROC 12 VthrComp = 115
[12:59:07.846] <TB1> INFO: ROC 13 VthrComp = 120
[12:59:07.846] <TB1> INFO: ROC 14 VthrComp = 131
[12:59:07.846] <TB1> INFO: ROC 15 VthrComp = 123
[12:59:08.084] <TB1> INFO: Expecting 41600 events.
[12:59:11.768] <TB1> INFO: 41600 events read in total (3092ms).
[12:59:11.768] <TB1> INFO: Test took 3920ms.
[12:59:11.778] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:59:11.778] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:59:11.789] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:59:11.789] <TB1> INFO: run 1 of 1
[12:59:12.067] <TB1> INFO: Expecting 5025280 events.
[12:59:38.135] <TB1> INFO: 591080 events read in total (25476ms).
[13:00:03.928] <TB1> INFO: 1179856 events read in total (51269ms).
[13:00:29.646] <TB1> INFO: 1768968 events read in total (76987ms).
[13:00:55.366] <TB1> INFO: 2357112 events read in total (102707ms).
[13:01:21.188] <TB1> INFO: 2942520 events read in total (128529ms).
[13:01:46.732] <TB1> INFO: 3526568 events read in total (154073ms).
[13:02:12.492] <TB1> INFO: 4109272 events read in total (179833ms).
[13:02:38.348] <TB1> INFO: 4690744 events read in total (205689ms).
[13:02:54.664] <TB1> INFO: 5025280 events read in total (222005ms).
[13:02:55.022] <TB1> INFO: Test took 223233ms.
[13:03:22.009] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 56.95 for pixel 33/74 mean/min/max = 44.3791/31.7925/56.9658
[13:03:22.009] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 59.0765 for pixel 4/78 mean/min/max = 45.3519/31.5573/59.1465
[13:03:22.010] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 59.8115 for pixel 0/6 mean/min/max = 45.7529/31.6566/59.8492
[13:03:22.010] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 60.8711 for pixel 16/16 mean/min/max = 47.254/33.5506/60.9574
[13:03:22.011] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 61.6678 for pixel 13/5 mean/min/max = 46.1401/30.4215/61.8587
[13:03:22.011] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 57.7167 for pixel 0/8 mean/min/max = 44.8483/31.9684/57.7282
[13:03:22.011] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 58.18 for pixel 0/8 mean/min/max = 46.2902/34.3844/58.1961
[13:03:22.012] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 58.8994 for pixel 30/79 mean/min/max = 46.4454/33.9137/58.9771
[13:03:22.012] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 58.6781 for pixel 50/74 mean/min/max = 45.6656/32.4944/58.8368
[13:03:22.013] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 59.7026 for pixel 11/0 mean/min/max = 46.0317/32.2228/59.8406
[13:03:22.013] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 59.5513 for pixel 0/20 mean/min/max = 44.8109/30.0498/59.572
[13:03:22.013] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 58.9927 for pixel 0/1 mean/min/max = 44.7394/30.4105/59.0682
[13:03:22.014] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 57.9683 for pixel 21/19 mean/min/max = 44.8522/31.6494/58.0551
[13:03:22.014] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 58.2895 for pixel 13/79 mean/min/max = 45.1804/31.8601/58.5007
[13:03:22.014] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 59.4736 for pixel 7/10 mean/min/max = 46.142/32.6799/59.6041
[13:03:22.015] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 60.1923 for pixel 10/73 mean/min/max = 45.9919/31.5206/60.4633
[13:03:22.015] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:03:22.105] <TB1> INFO: Expecting 411648 events.
[13:03:31.608] <TB1> INFO: 411648 events read in total (8911ms).
[13:03:31.616] <TB1> INFO: Expecting 411648 events.
[13:03:40.996] <TB1> INFO: 411648 events read in total (8977ms).
[13:03:41.007] <TB1> INFO: Expecting 411648 events.
[13:03:50.315] <TB1> INFO: 411648 events read in total (8904ms).
[13:03:50.332] <TB1> INFO: Expecting 411648 events.
[13:03:59.673] <TB1> INFO: 411648 events read in total (8938ms).
[13:03:59.690] <TB1> INFO: Expecting 411648 events.
[13:04:08.996] <TB1> INFO: 411648 events read in total (8903ms).
[13:04:09.015] <TB1> INFO: Expecting 411648 events.
[13:04:18.324] <TB1> INFO: 411648 events read in total (8906ms).
[13:04:18.347] <TB1> INFO: Expecting 411648 events.
[13:04:27.621] <TB1> INFO: 411648 events read in total (8871ms).
[13:04:27.645] <TB1> INFO: Expecting 411648 events.
[13:04:36.918] <TB1> INFO: 411648 events read in total (8870ms).
[13:04:36.945] <TB1> INFO: Expecting 411648 events.
[13:04:46.235] <TB1> INFO: 411648 events read in total (8887ms).
[13:04:46.265] <TB1> INFO: Expecting 411648 events.
[13:04:55.611] <TB1> INFO: 411648 events read in total (8943ms).
[13:04:55.645] <TB1> INFO: Expecting 411648 events.
[13:05:04.962] <TB1> INFO: 411648 events read in total (8914ms).
[13:05:04.997] <TB1> INFO: Expecting 411648 events.
[13:05:14.352] <TB1> INFO: 411648 events read in total (8952ms).
[13:05:14.391] <TB1> INFO: Expecting 411648 events.
[13:05:23.781] <TB1> INFO: 411648 events read in total (8987ms).
[13:05:23.821] <TB1> INFO: Expecting 411648 events.
[13:05:33.069] <TB1> INFO: 411648 events read in total (8845ms).
[13:05:33.112] <TB1> INFO: Expecting 411648 events.
[13:05:42.521] <TB1> INFO: 411648 events read in total (9006ms).
[13:05:42.583] <TB1> INFO: Expecting 411648 events.
[13:05:51.810] <TB1> INFO: 411648 events read in total (8824ms).
[13:05:51.860] <TB1> INFO: Test took 149845ms.
[13:05:52.773] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:05:52.786] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:05:52.786] <TB1> INFO: run 1 of 1
[13:05:53.069] <TB1> INFO: Expecting 5025280 events.
[13:06:19.057] <TB1> INFO: 584888 events read in total (25396ms).
[13:06:44.956] <TB1> INFO: 1168720 events read in total (51295ms).
[13:07:10.781] <TB1> INFO: 1752440 events read in total (77121ms).
[13:07:36.732] <TB1> INFO: 2334720 events read in total (103071ms).
[13:08:02.945] <TB1> INFO: 2916960 events read in total (129284ms).
[13:08:28.773] <TB1> INFO: 3498376 events read in total (155112ms).
[13:08:54.323] <TB1> INFO: 4079080 events read in total (180662ms).
[13:09:20.402] <TB1> INFO: 4659624 events read in total (206741ms).
[13:09:37.553] <TB1> INFO: 5025280 events read in total (223892ms).
[13:09:37.663] <TB1> INFO: Test took 224877ms.
[13:10:01.828] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 2.234843 .. 134.230468
[13:10:02.069] <TB1> INFO: Expecting 208000 events.
[13:10:11.748] <TB1> INFO: 208000 events read in total (9088ms).
[13:10:11.749] <TB1> INFO: Test took 9919ms.
[13:10:11.802] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 144 (-1/-1) hits flags = 528 (plus default)
[13:10:11.814] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:10:11.814] <TB1> INFO: run 1 of 1
[13:10:12.092] <TB1> INFO: Expecting 4759040 events.
[13:10:37.899] <TB1> INFO: 587352 events read in total (25215ms).
[13:11:03.889] <TB1> INFO: 1174712 events read in total (51205ms).
[13:11:29.703] <TB1> INFO: 1762272 events read in total (77020ms).
[13:11:55.185] <TB1> INFO: 2349680 events read in total (102501ms).
[13:12:21.285] <TB1> INFO: 2936176 events read in total (128601ms).
[13:12:47.098] <TB1> INFO: 3522048 events read in total (154414ms).
[13:13:12.973] <TB1> INFO: 4106952 events read in total (180289ms).
[13:13:38.779] <TB1> INFO: 4691864 events read in total (206095ms).
[13:13:42.141] <TB1> INFO: 4759040 events read in total (209457ms).
[13:13:42.228] <TB1> INFO: Test took 210413ms.
[13:14:10.423] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 28.046203 .. 43.922824
[13:14:10.701] <TB1> INFO: Expecting 208000 events.
[13:14:20.314] <TB1> INFO: 208000 events read in total (9022ms).
[13:14:20.315] <TB1> INFO: Test took 9890ms.
[13:14:20.370] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 18 .. 53 (-1/-1) hits flags = 528 (plus default)
[13:14:20.384] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:14:20.384] <TB1> INFO: run 1 of 1
[13:14:20.662] <TB1> INFO: Expecting 1198080 events.
[13:14:49.079] <TB1> INFO: 661816 events read in total (27825ms).
[13:15:12.130] <TB1> INFO: 1198080 events read in total (50876ms).
[13:15:12.159] <TB1> INFO: Test took 51775ms.
[13:15:25.268] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 24.554481 .. 45.169059
[13:15:25.592] <TB1> INFO: Expecting 208000 events.
[13:15:36.007] <TB1> INFO: 208000 events read in total (9824ms).
[13:15:36.008] <TB1> INFO: Test took 10738ms.
[13:15:36.087] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 14 .. 55 (-1/-1) hits flags = 528 (plus default)
[13:15:36.100] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:15:36.100] <TB1> INFO: run 1 of 1
[13:15:36.424] <TB1> INFO: Expecting 1397760 events.
[13:16:05.104] <TB1> INFO: 671552 events read in total (28088ms).
[13:16:32.458] <TB1> INFO: 1340240 events read in total (55442ms).
[13:16:35.241] <TB1> INFO: 1397760 events read in total (58226ms).
[13:16:35.269] <TB1> INFO: Test took 59169ms.
[13:16:51.056] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 23.660823 .. 42.919689
[13:16:51.346] <TB1> INFO: Expecting 208000 events.
[13:17:01.207] <TB1> INFO: 208000 events read in total (9269ms).
[13:17:01.208] <TB1> INFO: Test took 10150ms.
[13:17:01.258] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 13 .. 52 (-1/-1) hits flags = 528 (plus default)
[13:17:01.271] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:17:01.271] <TB1> INFO: run 1 of 1
[13:17:01.572] <TB1> INFO: Expecting 1331200 events.
[13:17:30.064] <TB1> INFO: 689208 events read in total (27899ms).
[13:17:56.255] <TB1> INFO: 1331200 events read in total (54090ms).
[13:17:56.288] <TB1> INFO: Test took 55017ms.
[13:18:09.455] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[13:18:09.455] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[13:18:09.468] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:18:09.468] <TB1> INFO: run 1 of 1
[13:18:09.704] <TB1> INFO: Expecting 1364480 events.
[13:18:38.150] <TB1> INFO: 667232 events read in total (27854ms).
[13:19:05.731] <TB1> INFO: 1333456 events read in total (55435ms).
[13:19:07.505] <TB1> INFO: 1364480 events read in total (57210ms).
[13:19:07.539] <TB1> INFO: Test took 58070ms.
[13:19:20.475] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C0.dat
[13:19:20.475] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C1.dat
[13:19:20.475] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C2.dat
[13:19:20.475] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C3.dat
[13:19:20.475] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C4.dat
[13:19:20.475] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C5.dat
[13:19:20.475] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C6.dat
[13:19:20.475] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C7.dat
[13:19:20.475] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C8.dat
[13:19:20.476] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C9.dat
[13:19:20.476] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C10.dat
[13:19:20.476] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C11.dat
[13:19:20.476] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C12.dat
[13:19:20.476] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C13.dat
[13:19:20.476] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C14.dat
[13:19:20.476] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C15.dat
[13:19:20.476] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C0.dat
[13:19:20.482] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C1.dat
[13:19:20.487] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C2.dat
[13:19:20.491] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C3.dat
[13:19:20.496] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C4.dat
[13:19:20.501] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C5.dat
[13:19:20.506] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C6.dat
[13:19:20.510] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C7.dat
[13:19:20.515] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C8.dat
[13:19:20.520] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C9.dat
[13:19:20.524] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C10.dat
[13:19:20.529] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C11.dat
[13:19:20.534] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C12.dat
[13:19:20.539] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C13.dat
[13:19:20.544] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C14.dat
[13:19:20.548] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C15.dat
[13:19:20.553] <TB1> INFO: PixTestTrim::trimTest() done
[13:19:20.553] <TB1> INFO: vtrim: 128 140 127 136 131 130 108 131 125 134 128 144 123 114 132 138
[13:19:20.553] <TB1> INFO: vthrcomp: 131 112 113 111 119 122 108 110 131 112 127 126 115 120 131 123
[13:19:20.553] <TB1> INFO: vcal mean: 34.96 34.96 34.96 34.95 35.02 34.96 35.01 35.00 35.01 35.03 34.98 34.87 34.96 34.99 34.97 34.94
[13:19:20.553] <TB1> INFO: vcal RMS: 1.03 0.98 0.97 1.02 1.26 0.96 0.86 0.93 1.03 1.08 1.03 1.13 1.03 0.94 1.03 1.09
[13:19:20.553] <TB1> INFO: bits mean: 9.92 10.11 9.29 9.34 9.79 9.37 8.45 9.02 9.44 9.75 9.89 9.77 10.04 9.41 9.35 9.49
[13:19:20.553] <TB1> INFO: bits RMS: 2.57 2.48 2.87 2.43 2.75 2.85 2.75 2.61 2.64 2.54 2.83 2.84 2.53 2.77 2.61 2.73
[13:19:20.562] <TB1> INFO: ----------------------------------------------------------------------
[13:19:20.562] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:19:20.562] <TB1> INFO: ----------------------------------------------------------------------
[13:19:20.566] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:19:20.579] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:19:20.579] <TB1> INFO: run 1 of 1
[13:19:20.855] <TB1> INFO: Expecting 4160000 events.
[13:19:51.974] <TB1> INFO: 724885 events read in total (30528ms).
[13:20:22.663] <TB1> INFO: 1441675 events read in total (61217ms).
[13:20:53.243] <TB1> INFO: 2152845 events read in total (91797ms).
[13:21:23.667] <TB1> INFO: 2858725 events read in total (122221ms).
[13:21:54.269] <TB1> INFO: 3562310 events read in total (152823ms).
[13:22:20.505] <TB1> INFO: 4160000 events read in total (179059ms).
[13:22:20.594] <TB1> INFO: Test took 180015ms.
[13:22:46.459] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[13:22:46.473] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:22:46.473] <TB1> INFO: run 1 of 1
[13:22:46.762] <TB1> INFO: Expecting 4243200 events.
[13:23:16.934] <TB1> INFO: 697330 events read in total (29580ms).
[13:23:47.146] <TB1> INFO: 1388925 events read in total (59792ms).
[13:24:16.939] <TB1> INFO: 2075920 events read in total (89585ms).
[13:24:47.173] <TB1> INFO: 2758970 events read in total (119819ms).
[13:25:17.317] <TB1> INFO: 3441100 events read in total (149963ms).
[13:25:47.208] <TB1> INFO: 4121870 events read in total (179854ms).
[13:25:52.814] <TB1> INFO: 4243200 events read in total (185460ms).
[13:25:52.000] <TB1> INFO: Test took 186527ms.
[13:26:20.808] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 185 (-1/-1) hits flags = 528 (plus default)
[13:26:20.821] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:26:20.821] <TB1> INFO: run 1 of 1
[13:26:21.060] <TB1> INFO: Expecting 3868800 events.
[13:26:52.540] <TB1> INFO: 718670 events read in total (30888ms).
[13:27:23.314] <TB1> INFO: 1429925 events read in total (61662ms).
[13:27:53.851] <TB1> INFO: 2135625 events read in total (92199ms).
[13:28:24.290] <TB1> INFO: 2837680 events read in total (122638ms).
[13:28:55.047] <TB1> INFO: 3537545 events read in total (153395ms).
[13:29:09.468] <TB1> INFO: 3868800 events read in total (167816ms).
[13:29:09.551] <TB1> INFO: Test took 168730ms.
[13:29:34.878] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 186 (-1/-1) hits flags = 528 (plus default)
[13:29:34.891] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:29:34.891] <TB1> INFO: run 1 of 1
[13:29:35.129] <TB1> INFO: Expecting 3889600 events.
[13:30:07.150] <TB1> INFO: 717290 events read in total (31429ms).
[13:30:38.168] <TB1> INFO: 1427140 events read in total (62447ms).
[13:31:08.742] <TB1> INFO: 2131480 events read in total (93021ms).
[13:31:39.006] <TB1> INFO: 2832035 events read in total (123285ms).
[13:32:09.631] <TB1> INFO: 3530710 events read in total (153910ms).
[13:32:25.292] <TB1> INFO: 3889600 events read in total (169571ms).
[13:32:25.504] <TB1> INFO: Test took 170613ms.
[13:32:49.538] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 186 (-1/-1) hits flags = 528 (plus default)
[13:32:49.551] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:32:49.551] <TB1> INFO: run 1 of 1
[13:32:49.818] <TB1> INFO: Expecting 3889600 events.
[13:33:21.740] <TB1> INFO: 717405 events read in total (31331ms).
[13:33:52.735] <TB1> INFO: 1427105 events read in total (62326ms).
[13:34:23.051] <TB1> INFO: 2131505 events read in total (92642ms).
[13:34:53.528] <TB1> INFO: 2832000 events read in total (123119ms).
[13:35:23.951] <TB1> INFO: 3530545 events read in total (153542ms).
[13:35:39.667] <TB1> INFO: 3889600 events read in total (169259ms).
[13:35:39.831] <TB1> INFO: Test took 170280ms.
[13:36:07.300] <TB1> INFO: PixTestTrim::trimBitTest() done
[13:36:07.301] <TB1> INFO: PixTestTrim::doTest() done, duration: 2425 seconds
[13:36:07.301] <TB1> INFO: Decoding statistics:
[13:36:07.301] <TB1> INFO: General information:
[13:36:07.301] <TB1> INFO: 16bit words read: 0
[13:36:07.301] <TB1> INFO: valid events total: 0
[13:36:07.301] <TB1> INFO: empty events: 0
[13:36:07.301] <TB1> INFO: valid events with pixels: 0
[13:36:07.301] <TB1> INFO: valid pixel hits: 0
[13:36:07.301] <TB1> INFO: Event errors: 0
[13:36:07.301] <TB1> INFO: start marker: 0
[13:36:07.301] <TB1> INFO: stop marker: 0
[13:36:07.301] <TB1> INFO: overflow: 0
[13:36:07.301] <TB1> INFO: invalid 5bit words: 0
[13:36:07.301] <TB1> INFO: invalid XOR eye diagram: 0
[13:36:07.301] <TB1> INFO: frame (failed synchr.): 0
[13:36:07.301] <TB1> INFO: idle data (no TBM trl): 0
[13:36:07.301] <TB1> INFO: no data (only TBM hdr): 0
[13:36:07.301] <TB1> INFO: TBM errors: 0
[13:36:07.301] <TB1> INFO: flawed TBM headers: 0
[13:36:07.301] <TB1> INFO: flawed TBM trailers: 0
[13:36:07.301] <TB1> INFO: event ID mismatches: 0
[13:36:07.301] <TB1> INFO: ROC errors: 0
[13:36:07.301] <TB1> INFO: missing ROC header(s): 0
[13:36:07.301] <TB1> INFO: misplaced readback start: 0
[13:36:07.301] <TB1> INFO: Pixel decoding errors: 0
[13:36:07.301] <TB1> INFO: pixel data incomplete: 0
[13:36:07.301] <TB1> INFO: pixel address: 0
[13:36:07.301] <TB1> INFO: pulse height fill bit: 0
[13:36:07.301] <TB1> INFO: buffer corruption: 0
[13:36:07.980] <TB1> INFO: ######################################################################
[13:36:07.980] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:36:07.980] <TB1> INFO: ######################################################################
[13:36:08.234] <TB1> INFO: Expecting 41600 events.
[13:36:11.845] <TB1> INFO: 41600 events read in total (3019ms).
[13:36:11.846] <TB1> INFO: Test took 3865ms.
[13:36:12.302] <TB1> INFO: Expecting 41600 events.
[13:36:15.905] <TB1> INFO: 41600 events read in total (3012ms).
[13:36:15.906] <TB1> INFO: Test took 3853ms.
[13:36:16.195] <TB1> INFO: Expecting 41600 events.
[13:36:19.685] <TB1> INFO: 41600 events read in total (2898ms).
[13:36:19.686] <TB1> INFO: Test took 3756ms.
[13:36:19.993] <TB1> INFO: Expecting 41600 events.
[13:36:23.458] <TB1> INFO: 41600 events read in total (2874ms).
[13:36:23.459] <TB1> INFO: Test took 3746ms.
[13:36:23.748] <TB1> INFO: Expecting 41600 events.
[13:36:27.247] <TB1> INFO: 41600 events read in total (2908ms).
[13:36:27.248] <TB1> INFO: Test took 3765ms.
[13:36:27.549] <TB1> INFO: Expecting 41600 events.
[13:36:31.058] <TB1> INFO: 41600 events read in total (2918ms).
[13:36:31.059] <TB1> INFO: Test took 3786ms.
[13:36:31.352] <TB1> INFO: Expecting 41600 events.
[13:36:34.866] <TB1> INFO: 41600 events read in total (2923ms).
[13:36:34.867] <TB1> INFO: Test took 3781ms.
[13:36:35.158] <TB1> INFO: Expecting 41600 events.
[13:36:38.729] <TB1> INFO: 41600 events read in total (2979ms).
[13:36:38.729] <TB1> INFO: Test took 3836ms.
[13:36:39.019] <TB1> INFO: Expecting 41600 events.
[13:36:42.552] <TB1> INFO: 41600 events read in total (2942ms).
[13:36:42.553] <TB1> INFO: Test took 3799ms.
[13:36:42.841] <TB1> INFO: Expecting 41600 events.
[13:36:46.347] <TB1> INFO: 41600 events read in total (2914ms).
[13:36:46.348] <TB1> INFO: Test took 3771ms.
[13:36:46.639] <TB1> INFO: Expecting 41600 events.
[13:36:50.104] <TB1> INFO: 41600 events read in total (2873ms).
[13:36:50.105] <TB1> INFO: Test took 3731ms.
[13:36:50.396] <TB1> INFO: Expecting 41600 events.
[13:36:53.906] <TB1> INFO: 41600 events read in total (2919ms).
[13:36:53.907] <TB1> INFO: Test took 3776ms.
[13:36:54.196] <TB1> INFO: Expecting 41600 events.
[13:36:57.663] <TB1> INFO: 41600 events read in total (2875ms).
[13:36:57.663] <TB1> INFO: Test took 3732ms.
[13:36:57.963] <TB1> INFO: Expecting 41600 events.
[13:37:01.525] <TB1> INFO: 41600 events read in total (2970ms).
[13:37:01.525] <TB1> INFO: Test took 3838ms.
[13:37:01.814] <TB1> INFO: Expecting 41600 events.
[13:37:05.378] <TB1> INFO: 41600 events read in total (2972ms).
[13:37:05.379] <TB1> INFO: Test took 3830ms.
[13:37:05.669] <TB1> INFO: Expecting 41600 events.
[13:37:09.317] <TB1> INFO: 41600 events read in total (3057ms).
[13:37:09.318] <TB1> INFO: Test took 3914ms.
[13:37:09.611] <TB1> INFO: Expecting 41600 events.
[13:37:13.312] <TB1> INFO: 41600 events read in total (3110ms).
[13:37:13.314] <TB1> INFO: Test took 3968ms.
[13:37:13.634] <TB1> INFO: Expecting 41600 events.
[13:37:17.287] <TB1> INFO: 41600 events read in total (3061ms).
[13:37:17.288] <TB1> INFO: Test took 3945ms.
[13:37:17.579] <TB1> INFO: Expecting 41600 events.
[13:37:21.554] <TB1> INFO: 41600 events read in total (3383ms).
[13:37:21.555] <TB1> INFO: Test took 4240ms.
[13:37:21.909] <TB1> INFO: Expecting 41600 events.
[13:37:25.412] <TB1> INFO: 41600 events read in total (2912ms).
[13:37:25.413] <TB1> INFO: Test took 3830ms.
[13:37:25.702] <TB1> INFO: Expecting 41600 events.
[13:37:29.259] <TB1> INFO: 41600 events read in total (2965ms).
[13:37:29.259] <TB1> INFO: Test took 3821ms.
[13:37:29.549] <TB1> INFO: Expecting 41600 events.
[13:37:33.112] <TB1> INFO: 41600 events read in total (2971ms).
[13:37:33.113] <TB1> INFO: Test took 3829ms.
[13:37:33.404] <TB1> INFO: Expecting 41600 events.
[13:37:36.922] <TB1> INFO: 41600 events read in total (2926ms).
[13:37:36.923] <TB1> INFO: Test took 3783ms.
[13:37:37.214] <TB1> INFO: Expecting 41600 events.
[13:37:40.770] <TB1> INFO: 41600 events read in total (2964ms).
[13:37:40.771] <TB1> INFO: Test took 3821ms.
[13:37:41.126] <TB1> INFO: Expecting 41600 events.
[13:37:44.589] <TB1> INFO: 41600 events read in total (2871ms).
[13:37:44.590] <TB1> INFO: Test took 3790ms.
[13:37:44.879] <TB1> INFO: Expecting 41600 events.
[13:37:48.392] <TB1> INFO: 41600 events read in total (2921ms).
[13:37:48.393] <TB1> INFO: Test took 3779ms.
[13:37:48.686] <TB1> INFO: Expecting 41600 events.
[13:37:52.222] <TB1> INFO: 41600 events read in total (2944ms).
[13:37:52.223] <TB1> INFO: Test took 3803ms.
[13:37:52.512] <TB1> INFO: Expecting 41600 events.
[13:37:56.057] <TB1> INFO: 41600 events read in total (2954ms).
[13:37:56.058] <TB1> INFO: Test took 3811ms.
[13:37:56.347] <TB1> INFO: Expecting 41600 events.
[13:37:59.852] <TB1> INFO: 41600 events read in total (2914ms).
[13:37:59.853] <TB1> INFO: Test took 3771ms.
[13:38:00.142] <TB1> INFO: Expecting 41600 events.
[13:38:03.710] <TB1> INFO: 41600 events read in total (2976ms).
[13:38:03.711] <TB1> INFO: Test took 3833ms.
[13:38:03.000] <TB1> INFO: Expecting 41600 events.
[13:38:07.536] <TB1> INFO: 41600 events read in total (2942ms).
[13:38:07.537] <TB1> INFO: Test took 3802ms.
[13:38:07.826] <TB1> INFO: Expecting 41600 events.
[13:38:11.338] <TB1> INFO: 41600 events read in total (2920ms).
[13:38:11.339] <TB1> INFO: Test took 3777ms.
[13:38:11.628] <TB1> INFO: Expecting 41600 events.
[13:38:15.124] <TB1> INFO: 41600 events read in total (2904ms).
[13:38:15.125] <TB1> INFO: Test took 3762ms.
[13:38:15.415] <TB1> INFO: Expecting 41600 events.
[13:38:18.998] <TB1> INFO: 41600 events read in total (2992ms).
[13:38:18.998] <TB1> INFO: Test took 3848ms.
[13:38:19.291] <TB1> INFO: Expecting 41600 events.
[13:38:22.893] <TB1> INFO: 41600 events read in total (3011ms).
[13:38:22.894] <TB1> INFO: Test took 3869ms.
[13:38:23.186] <TB1> INFO: Expecting 41600 events.
[13:38:26.748] <TB1> INFO: 41600 events read in total (2970ms).
[13:38:26.748] <TB1> INFO: Test took 3827ms.
[13:38:27.040] <TB1> INFO: Expecting 41600 events.
[13:38:30.571] <TB1> INFO: 41600 events read in total (2939ms).
[13:38:30.572] <TB1> INFO: Test took 3798ms.
[13:38:30.863] <TB1> INFO: Expecting 41600 events.
[13:38:34.386] <TB1> INFO: 41600 events read in total (2931ms).
[13:38:34.387] <TB1> INFO: Test took 3791ms.
[13:38:34.676] <TB1> INFO: Expecting 41600 events.
[13:38:38.263] <TB1> INFO: 41600 events read in total (2995ms).
[13:38:38.264] <TB1> INFO: Test took 3853ms.
[13:38:38.557] <TB1> INFO: Expecting 41600 events.
[13:38:42.081] <TB1> INFO: 41600 events read in total (2932ms).
[13:38:42.082] <TB1> INFO: Test took 3791ms.
[13:38:42.372] <TB1> INFO: Expecting 41600 events.
[13:38:45.863] <TB1> INFO: 41600 events read in total (2900ms).
[13:38:45.864] <TB1> INFO: Test took 3758ms.
[13:38:46.154] <TB1> INFO: Expecting 41600 events.
[13:38:49.648] <TB1> INFO: 41600 events read in total (2903ms).
[13:38:49.649] <TB1> INFO: Test took 3761ms.
[13:38:49.938] <TB1> INFO: Expecting 41600 events.
[13:38:53.455] <TB1> INFO: 41600 events read in total (2925ms).
[13:38:53.456] <TB1> INFO: Test took 3783ms.
[13:38:53.744] <TB1> INFO: Expecting 41600 events.
[13:38:57.239] <TB1> INFO: 41600 events read in total (2903ms).
[13:38:57.239] <TB1> INFO: Test took 3759ms.
[13:38:57.528] <TB1> INFO: Expecting 41600 events.
[13:39:01.061] <TB1> INFO: 41600 events read in total (2941ms).
[13:39:01.061] <TB1> INFO: Test took 3797ms.
[13:39:01.352] <TB1> INFO: Expecting 41600 events.
[13:39:04.915] <TB1> INFO: 41600 events read in total (2971ms).
[13:39:04.915] <TB1> INFO: Test took 3828ms.
[13:39:05.209] <TB1> INFO: Expecting 41600 events.
[13:39:08.694] <TB1> INFO: 41600 events read in total (2893ms).
[13:39:08.695] <TB1> INFO: Test took 3755ms.
[13:39:08.984] <TB1> INFO: Expecting 41600 events.
[13:39:12.624] <TB1> INFO: 41600 events read in total (3048ms).
[13:39:12.624] <TB1> INFO: Test took 3905ms.
[13:39:12.927] <TB1> INFO: Expecting 41600 events.
[13:39:16.434] <TB1> INFO: 41600 events read in total (2916ms).
[13:39:16.435] <TB1> INFO: Test took 3787ms.
[13:39:16.724] <TB1> INFO: Expecting 41600 events.
[13:39:20.340] <TB1> INFO: 41600 events read in total (3025ms).
[13:39:20.341] <TB1> INFO: Test took 3882ms.
[13:39:20.632] <TB1> INFO: Expecting 41600 events.
[13:39:24.188] <TB1> INFO: 41600 events read in total (2964ms).
[13:39:24.189] <TB1> INFO: Test took 3822ms.
[13:39:24.481] <TB1> INFO: Expecting 41600 events.
[13:39:28.027] <TB1> INFO: 41600 events read in total (2954ms).
[13:39:28.028] <TB1> INFO: Test took 3812ms.
[13:39:28.320] <TB1> INFO: Expecting 41600 events.
[13:39:31.856] <TB1> INFO: 41600 events read in total (2944ms).
[13:39:31.857] <TB1> INFO: Test took 3802ms.
[13:39:32.151] <TB1> INFO: Expecting 41600 events.
[13:39:35.832] <TB1> INFO: 41600 events read in total (3089ms).
[13:39:35.833] <TB1> INFO: Test took 3947ms.
[13:39:36.126] <TB1> INFO: Expecting 2560 events.
[13:39:37.015] <TB1> INFO: 2560 events read in total (297ms).
[13:39:37.015] <TB1> INFO: Test took 1166ms.
[13:39:37.323] <TB1> INFO: Expecting 2560 events.
[13:39:38.213] <TB1> INFO: 2560 events read in total (299ms).
[13:39:38.213] <TB1> INFO: Test took 1197ms.
[13:39:38.520] <TB1> INFO: Expecting 2560 events.
[13:39:39.408] <TB1> INFO: 2560 events read in total (296ms).
[13:39:39.408] <TB1> INFO: Test took 1194ms.
[13:39:39.716] <TB1> INFO: Expecting 2560 events.
[13:39:40.606] <TB1> INFO: 2560 events read in total (298ms).
[13:39:40.606] <TB1> INFO: Test took 1198ms.
[13:39:40.913] <TB1> INFO: Expecting 2560 events.
[13:39:41.800] <TB1> INFO: 2560 events read in total (295ms).
[13:39:41.800] <TB1> INFO: Test took 1193ms.
[13:39:42.107] <TB1> INFO: Expecting 2560 events.
[13:39:42.986] <TB1> INFO: 2560 events read in total (287ms).
[13:39:42.987] <TB1> INFO: Test took 1186ms.
[13:39:43.295] <TB1> INFO: Expecting 2560 events.
[13:39:44.186] <TB1> INFO: 2560 events read in total (299ms).
[13:39:44.186] <TB1> INFO: Test took 1199ms.
[13:39:44.495] <TB1> INFO: Expecting 2560 events.
[13:39:45.385] <TB1> INFO: 2560 events read in total (298ms).
[13:39:45.385] <TB1> INFO: Test took 1198ms.
[13:39:45.692] <TB1> INFO: Expecting 2560 events.
[13:39:46.580] <TB1> INFO: 2560 events read in total (296ms).
[13:39:46.580] <TB1> INFO: Test took 1194ms.
[13:39:46.888] <TB1> INFO: Expecting 2560 events.
[13:39:47.770] <TB1> INFO: 2560 events read in total (290ms).
[13:39:47.771] <TB1> INFO: Test took 1191ms.
[13:39:48.077] <TB1> INFO: Expecting 2560 events.
[13:39:48.962] <TB1> INFO: 2560 events read in total (293ms).
[13:39:48.962] <TB1> INFO: Test took 1190ms.
[13:39:49.271] <TB1> INFO: Expecting 2560 events.
[13:39:50.152] <TB1> INFO: 2560 events read in total (290ms).
[13:39:50.153] <TB1> INFO: Test took 1190ms.
[13:39:50.459] <TB1> INFO: Expecting 2560 events.
[13:39:51.349] <TB1> INFO: 2560 events read in total (298ms).
[13:39:51.349] <TB1> INFO: Test took 1196ms.
[13:39:51.657] <TB1> INFO: Expecting 2560 events.
[13:39:52.550] <TB1> INFO: 2560 events read in total (303ms).
[13:39:52.551] <TB1> INFO: Test took 1202ms.
[13:39:52.865] <TB1> INFO: Expecting 2560 events.
[13:39:53.750] <TB1> INFO: 2560 events read in total (293ms).
[13:39:53.750] <TB1> INFO: Test took 1199ms.
[13:39:54.059] <TB1> INFO: Expecting 2560 events.
[13:39:54.945] <TB1> INFO: 2560 events read in total (294ms).
[13:39:54.946] <TB1> INFO: Test took 1194ms.
[13:39:55.253] <TB1> INFO: Expecting 655360 events.
[13:40:16.322] <TB1> INFO: 531260 events read in total (20477ms).
[13:40:21.395] <TB1> INFO: 655360 events read in total (25550ms).
[13:40:21.413] <TB1> INFO: Test took 26464ms.
[13:40:21.445] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:40:21.704] <TB1> INFO: Expecting 655360 events.
[13:40:36.401] <TB1> INFO: 655360 events read in total (14105ms).
[13:40:36.414] <TB1> INFO: Expecting 655360 events.
[13:40:50.557] <TB1> INFO: 655360 events read in total (13740ms).
[13:40:50.573] <TB1> INFO: Expecting 655360 events.
[13:41:05.181] <TB1> INFO: 655360 events read in total (14205ms).
[13:41:05.202] <TB1> INFO: Expecting 655360 events.
[13:41:19.839] <TB1> INFO: 655360 events read in total (14234ms).
[13:41:19.862] <TB1> INFO: Expecting 655360 events.
[13:41:34.318] <TB1> INFO: 655360 events read in total (14052ms).
[13:41:34.354] <TB1> INFO: Expecting 655360 events.
[13:41:49.134] <TB1> INFO: 655360 events read in total (14377ms).
[13:41:49.169] <TB1> INFO: Expecting 655360 events.
[13:42:03.634] <TB1> INFO: 655360 events read in total (14062ms).
[13:42:03.685] <TB1> INFO: Expecting 655360 events.
[13:42:18.191] <TB1> INFO: 655360 events read in total (14103ms).
[13:42:18.232] <TB1> INFO: Expecting 655360 events.
[13:42:32.588] <TB1> INFO: 655360 events read in total (13953ms).
[13:42:32.772] <TB1> INFO: Expecting 655360 events.
[13:42:47.286] <TB1> INFO: 655360 events read in total (14111ms).
[13:42:47.357] <TB1> INFO: Expecting 655360 events.
[13:43:01.893] <TB1> INFO: 655360 events read in total (14133ms).
[13:43:02.092] <TB1> INFO: Expecting 655360 events.
[13:43:16.361] <TB1> INFO: 655360 events read in total (13866ms).
[13:43:16.435] <TB1> INFO: Expecting 655360 events.
[13:43:30.545] <TB1> INFO: 655360 events read in total (13707ms).
[13:43:30.696] <TB1> INFO: Expecting 655360 events.
[13:43:45.019] <TB1> INFO: 655360 events read in total (13920ms).
[13:43:45.102] <TB1> INFO: Expecting 655360 events.
[13:43:59.575] <TB1> INFO: 655360 events read in total (14070ms).
[13:43:59.661] <TB1> INFO: Expecting 655360 events.
[13:44:14.104] <TB1> INFO: 655360 events read in total (14040ms).
[13:44:14.256] <TB1> INFO: Test took 232811ms.
[13:44:14.435] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:44:14.441] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:44:14.447] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:44:14.452] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:44:14.458] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:44:14.464] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:44:14.469] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:44:14.475] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[13:44:14.481] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[13:44:14.487] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[13:44:14.492] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[13:44:14.498] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:44:14.504] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:44:14.510] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:44:14.516] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:44:14.522] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:44:14.530] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:44:14.536] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:44:14.542] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:44:14.547] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:44:14.553] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:44:14.560] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:44:14.565] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:44:14.571] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:44:14.578] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:44:14.585] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:44:14.591] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:44:14.597] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:44:14.602] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[13:44:14.608] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:44:14.614] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:44:14.619] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:44:14.625] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:44:14.631] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:44:14.637] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:44:14.642] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:44:14.648] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:44:14.682] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C0.dat
[13:44:14.682] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C1.dat
[13:44:14.682] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C2.dat
[13:44:14.682] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C3.dat
[13:44:14.682] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C4.dat
[13:44:14.682] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C5.dat
[13:44:14.682] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C6.dat
[13:44:14.682] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C7.dat
[13:44:14.683] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C8.dat
[13:44:14.683] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C9.dat
[13:44:14.683] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C10.dat
[13:44:14.683] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C11.dat
[13:44:14.683] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C12.dat
[13:44:14.683] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C13.dat
[13:44:14.683] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C14.dat
[13:44:14.683] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C15.dat
[13:44:14.929] <TB1> INFO: Expecting 41600 events.
[13:44:18.074] <TB1> INFO: 41600 events read in total (2553ms).
[13:44:18.075] <TB1> INFO: Test took 3389ms.
[13:44:18.525] <TB1> INFO: Expecting 41600 events.
[13:44:21.570] <TB1> INFO: 41600 events read in total (2453ms).
[13:44:21.570] <TB1> INFO: Test took 3284ms.
[13:44:22.016] <TB1> INFO: Expecting 41600 events.
[13:44:25.134] <TB1> INFO: 41600 events read in total (2526ms).
[13:44:25.135] <TB1> INFO: Test took 3355ms.
[13:44:25.356] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:25.445] <TB1> INFO: Expecting 2560 events.
[13:44:26.334] <TB1> INFO: 2560 events read in total (296ms).
[13:44:26.334] <TB1> INFO: Test took 978ms.
[13:44:26.336] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:26.643] <TB1> INFO: Expecting 2560 events.
[13:44:27.528] <TB1> INFO: 2560 events read in total (293ms).
[13:44:27.528] <TB1> INFO: Test took 1192ms.
[13:44:27.531] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:27.837] <TB1> INFO: Expecting 2560 events.
[13:44:28.726] <TB1> INFO: 2560 events read in total (297ms).
[13:44:28.727] <TB1> INFO: Test took 1196ms.
[13:44:28.732] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:29.035] <TB1> INFO: Expecting 2560 events.
[13:44:29.923] <TB1> INFO: 2560 events read in total (296ms).
[13:44:29.923] <TB1> INFO: Test took 1191ms.
[13:44:29.926] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:30.231] <TB1> INFO: Expecting 2560 events.
[13:44:31.118] <TB1> INFO: 2560 events read in total (296ms).
[13:44:31.119] <TB1> INFO: Test took 1193ms.
[13:44:31.121] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:31.427] <TB1> INFO: Expecting 2560 events.
[13:44:32.316] <TB1> INFO: 2560 events read in total (297ms).
[13:44:32.316] <TB1> INFO: Test took 1195ms.
[13:44:32.319] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:32.624] <TB1> INFO: Expecting 2560 events.
[13:44:33.510] <TB1> INFO: 2560 events read in total (294ms).
[13:44:33.511] <TB1> INFO: Test took 1192ms.
[13:44:33.516] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:33.817] <TB1> INFO: Expecting 2560 events.
[13:44:34.705] <TB1> INFO: 2560 events read in total (296ms).
[13:44:34.706] <TB1> INFO: Test took 1190ms.
[13:44:34.707] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:35.014] <TB1> INFO: Expecting 2560 events.
[13:44:35.894] <TB1> INFO: 2560 events read in total (289ms).
[13:44:35.895] <TB1> INFO: Test took 1188ms.
[13:44:35.897] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:36.202] <TB1> INFO: Expecting 2560 events.
[13:44:37.083] <TB1> INFO: 2560 events read in total (289ms).
[13:44:37.083] <TB1> INFO: Test took 1186ms.
[13:44:37.085] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:37.392] <TB1> INFO: Expecting 2560 events.
[13:44:38.272] <TB1> INFO: 2560 events read in total (288ms).
[13:44:38.273] <TB1> INFO: Test took 1189ms.
[13:44:38.276] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:38.581] <TB1> INFO: Expecting 2560 events.
[13:44:39.460] <TB1> INFO: 2560 events read in total (287ms).
[13:44:39.460] <TB1> INFO: Test took 1185ms.
[13:44:39.463] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:39.769] <TB1> INFO: Expecting 2560 events.
[13:44:40.653] <TB1> INFO: 2560 events read in total (293ms).
[13:44:40.653] <TB1> INFO: Test took 1190ms.
[13:44:40.657] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:40.963] <TB1> INFO: Expecting 2560 events.
[13:44:41.843] <TB1> INFO: 2560 events read in total (288ms).
[13:44:41.843] <TB1> INFO: Test took 1186ms.
[13:44:41.846] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:42.151] <TB1> INFO: Expecting 2560 events.
[13:44:43.038] <TB1> INFO: 2560 events read in total (295ms).
[13:44:43.038] <TB1> INFO: Test took 1192ms.
[13:44:43.041] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:43.346] <TB1> INFO: Expecting 2560 events.
[13:44:44.229] <TB1> INFO: 2560 events read in total (292ms).
[13:44:44.229] <TB1> INFO: Test took 1188ms.
[13:44:44.233] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:44.537] <TB1> INFO: Expecting 2560 events.
[13:44:45.418] <TB1> INFO: 2560 events read in total (289ms).
[13:44:45.419] <TB1> INFO: Test took 1186ms.
[13:44:45.422] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:45.726] <TB1> INFO: Expecting 2560 events.
[13:44:46.609] <TB1> INFO: 2560 events read in total (291ms).
[13:44:46.609] <TB1> INFO: Test took 1188ms.
[13:44:46.613] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:46.917] <TB1> INFO: Expecting 2560 events.
[13:44:47.800] <TB1> INFO: 2560 events read in total (291ms).
[13:44:47.800] <TB1> INFO: Test took 1187ms.
[13:44:47.804] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:48.107] <TB1> INFO: Expecting 2560 events.
[13:44:48.995] <TB1> INFO: 2560 events read in total (296ms).
[13:44:48.995] <TB1> INFO: Test took 1191ms.
[13:44:48.998] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:49.304] <TB1> INFO: Expecting 2560 events.
[13:44:50.187] <TB1> INFO: 2560 events read in total (292ms).
[13:44:50.187] <TB1> INFO: Test took 1189ms.
[13:44:50.189] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:50.496] <TB1> INFO: Expecting 2560 events.
[13:44:51.383] <TB1> INFO: 2560 events read in total (296ms).
[13:44:51.384] <TB1> INFO: Test took 1195ms.
[13:44:51.389] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:51.692] <TB1> INFO: Expecting 2560 events.
[13:44:52.575] <TB1> INFO: 2560 events read in total (291ms).
[13:44:52.576] <TB1> INFO: Test took 1187ms.
[13:44:52.578] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:52.884] <TB1> INFO: Expecting 2560 events.
[13:44:53.765] <TB1> INFO: 2560 events read in total (289ms).
[13:44:53.765] <TB1> INFO: Test took 1187ms.
[13:44:53.768] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:54.073] <TB1> INFO: Expecting 2560 events.
[13:44:54.956] <TB1> INFO: 2560 events read in total (291ms).
[13:44:54.957] <TB1> INFO: Test took 1189ms.
[13:44:54.959] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:55.265] <TB1> INFO: Expecting 2560 events.
[13:44:56.154] <TB1> INFO: 2560 events read in total (297ms).
[13:44:56.154] <TB1> INFO: Test took 1195ms.
[13:44:56.157] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:56.461] <TB1> INFO: Expecting 2560 events.
[13:44:57.347] <TB1> INFO: 2560 events read in total (294ms).
[13:44:57.348] <TB1> INFO: Test took 1191ms.
[13:44:57.350] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:57.656] <TB1> INFO: Expecting 2560 events.
[13:44:58.551] <TB1> INFO: 2560 events read in total (304ms).
[13:44:58.551] <TB1> INFO: Test took 1201ms.
[13:44:58.554] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:58.859] <TB1> INFO: Expecting 2560 events.
[13:44:59.746] <TB1> INFO: 2560 events read in total (296ms).
[13:44:59.746] <TB1> INFO: Test took 1192ms.
[13:44:59.749] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:45:00.055] <TB1> INFO: Expecting 2560 events.
[13:45:00.942] <TB1> INFO: 2560 events read in total (295ms).
[13:45:00.943] <TB1> INFO: Test took 1194ms.
[13:45:00.945] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:45:01.250] <TB1> INFO: Expecting 2560 events.
[13:45:02.136] <TB1> INFO: 2560 events read in total (294ms).
[13:45:02.137] <TB1> INFO: Test took 1192ms.
[13:45:02.140] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:45:02.445] <TB1> INFO: Expecting 2560 events.
[13:45:03.330] <TB1> INFO: 2560 events read in total (293ms).
[13:45:03.330] <TB1> INFO: Test took 1191ms.
[13:45:03.806] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 535 seconds
[13:45:03.806] <TB1> INFO: PH scale (per ROC): 51 48 48 41 42 54 39 55 40 38 48 43 39 45 49 42
[13:45:03.806] <TB1> INFO: PH offset (per ROC): 123 106 110 84 132 123 122 121 105 105 142 134 110 113 141 106
[13:45:03.815] <TB1> INFO: Decoding statistics:
[13:45:03.815] <TB1> INFO: General information:
[13:45:03.815] <TB1> INFO: 16bit words read: 127894
[13:45:03.815] <TB1> INFO: valid events total: 20480
[13:45:03.815] <TB1> INFO: empty events: 17973
[13:45:03.815] <TB1> INFO: valid events with pixels: 2507
[13:45:03.815] <TB1> INFO: valid pixel hits: 2507
[13:45:03.815] <TB1> INFO: Event errors: 0
[13:45:03.815] <TB1> INFO: start marker: 0
[13:45:03.815] <TB1> INFO: stop marker: 0
[13:45:03.815] <TB1> INFO: overflow: 0
[13:45:03.815] <TB1> INFO: invalid 5bit words: 0
[13:45:03.815] <TB1> INFO: invalid XOR eye diagram: 0
[13:45:03.815] <TB1> INFO: frame (failed synchr.): 0
[13:45:03.815] <TB1> INFO: idle data (no TBM trl): 0
[13:45:03.815] <TB1> INFO: no data (only TBM hdr): 0
[13:45:03.815] <TB1> INFO: TBM errors: 0
[13:45:03.815] <TB1> INFO: flawed TBM headers: 0
[13:45:03.815] <TB1> INFO: flawed TBM trailers: 0
[13:45:03.815] <TB1> INFO: event ID mismatches: 0
[13:45:03.815] <TB1> INFO: ROC errors: 0
[13:45:03.815] <TB1> INFO: missing ROC header(s): 0
[13:45:03.815] <TB1> INFO: misplaced readback start: 0
[13:45:03.815] <TB1> INFO: Pixel decoding errors: 0
[13:45:03.815] <TB1> INFO: pixel data incomplete: 0
[13:45:03.815] <TB1> INFO: pixel address: 0
[13:45:03.815] <TB1> INFO: pulse height fill bit: 0
[13:45:03.815] <TB1> INFO: buffer corruption: 0
[13:45:03.974] <TB1> INFO: ######################################################################
[13:45:03.974] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:45:03.974] <TB1> INFO: ######################################################################
[13:45:03.990] <TB1> INFO: scanning low vcal = 10
[13:45:04.241] <TB1> INFO: Expecting 41600 events.
[13:45:07.826] <TB1> INFO: 41600 events read in total (2994ms).
[13:45:07.826] <TB1> INFO: Test took 3836ms.
[13:45:07.829] <TB1> INFO: scanning low vcal = 20
[13:45:08.126] <TB1> INFO: Expecting 41600 events.
[13:45:11.733] <TB1> INFO: 41600 events read in total (3015ms).
[13:45:11.733] <TB1> INFO: Test took 3904ms.
[13:45:11.735] <TB1> INFO: scanning low vcal = 30
[13:45:12.026] <TB1> INFO: Expecting 41600 events.
[13:45:15.660] <TB1> INFO: 41600 events read in total (3042ms).
[13:45:15.661] <TB1> INFO: Test took 3926ms.
[13:45:15.664] <TB1> INFO: scanning low vcal = 40
[13:45:15.941] <TB1> INFO: Expecting 41600 events.
[13:45:19.895] <TB1> INFO: 41600 events read in total (3362ms).
[13:45:19.896] <TB1> INFO: Test took 4232ms.
[13:45:19.899] <TB1> INFO: scanning low vcal = 50
[13:45:20.176] <TB1> INFO: Expecting 41600 events.
[13:45:24.156] <TB1> INFO: 41600 events read in total (3388ms).
[13:45:24.157] <TB1> INFO: Test took 4258ms.
[13:45:24.161] <TB1> INFO: scanning low vcal = 60
[13:45:24.437] <TB1> INFO: Expecting 41600 events.
[13:45:28.427] <TB1> INFO: 41600 events read in total (3398ms).
[13:45:28.427] <TB1> INFO: Test took 4266ms.
[13:45:28.431] <TB1> INFO: scanning low vcal = 70
[13:45:28.708] <TB1> INFO: Expecting 41600 events.
[13:45:32.682] <TB1> INFO: 41600 events read in total (3382ms).
[13:45:32.682] <TB1> INFO: Test took 4251ms.
[13:45:32.686] <TB1> INFO: scanning low vcal = 80
[13:45:32.963] <TB1> INFO: Expecting 41600 events.
[13:45:36.940] <TB1> INFO: 41600 events read in total (3385ms).
[13:45:36.941] <TB1> INFO: Test took 4255ms.
[13:45:36.943] <TB1> INFO: scanning low vcal = 90
[13:45:37.220] <TB1> INFO: Expecting 41600 events.
[13:45:41.162] <TB1> INFO: 41600 events read in total (3350ms).
[13:45:41.162] <TB1> INFO: Test took 4219ms.
[13:45:41.166] <TB1> INFO: scanning low vcal = 100
[13:45:41.442] <TB1> INFO: Expecting 41600 events.
[13:45:45.389] <TB1> INFO: 41600 events read in total (3356ms).
[13:45:45.389] <TB1> INFO: Test took 4223ms.
[13:45:45.392] <TB1> INFO: scanning low vcal = 110
[13:45:45.669] <TB1> INFO: Expecting 41600 events.
[13:45:49.645] <TB1> INFO: 41600 events read in total (3384ms).
[13:45:49.646] <TB1> INFO: Test took 4253ms.
[13:45:49.649] <TB1> INFO: scanning low vcal = 120
[13:45:49.926] <TB1> INFO: Expecting 41600 events.
[13:45:53.909] <TB1> INFO: 41600 events read in total (3391ms).
[13:45:53.910] <TB1> INFO: Test took 4261ms.
[13:45:53.913] <TB1> INFO: scanning low vcal = 130
[13:45:54.190] <TB1> INFO: Expecting 41600 events.
[13:45:58.171] <TB1> INFO: 41600 events read in total (3390ms).
[13:45:58.172] <TB1> INFO: Test took 4259ms.
[13:45:58.175] <TB1> INFO: scanning low vcal = 140
[13:45:58.452] <TB1> INFO: Expecting 41600 events.
[13:46:02.458] <TB1> INFO: 41600 events read in total (3414ms).
[13:46:02.459] <TB1> INFO: Test took 4284ms.
[13:46:02.462] <TB1> INFO: scanning low vcal = 150
[13:46:02.738] <TB1> INFO: Expecting 41600 events.
[13:46:06.728] <TB1> INFO: 41600 events read in total (3398ms).
[13:46:06.729] <TB1> INFO: Test took 4267ms.
[13:46:06.733] <TB1> INFO: scanning low vcal = 160
[13:46:07.010] <TB1> INFO: Expecting 41600 events.
[13:46:10.966] <TB1> INFO: 41600 events read in total (3365ms).
[13:46:10.967] <TB1> INFO: Test took 4234ms.
[13:46:10.970] <TB1> INFO: scanning low vcal = 170
[13:46:11.248] <TB1> INFO: Expecting 41600 events.
[13:46:15.199] <TB1> INFO: 41600 events read in total (3360ms).
[13:46:15.200] <TB1> INFO: Test took 4229ms.
[13:46:15.206] <TB1> INFO: scanning low vcal = 180
[13:46:15.480] <TB1> INFO: Expecting 41600 events.
[13:46:19.445] <TB1> INFO: 41600 events read in total (3373ms).
[13:46:19.446] <TB1> INFO: Test took 4239ms.
[13:46:19.449] <TB1> INFO: scanning low vcal = 190
[13:46:19.726] <TB1> INFO: Expecting 41600 events.
[13:46:23.697] <TB1> INFO: 41600 events read in total (3380ms).
[13:46:23.698] <TB1> INFO: Test took 4249ms.
[13:46:23.701] <TB1> INFO: scanning low vcal = 200
[13:46:23.978] <TB1> INFO: Expecting 41600 events.
[13:46:27.964] <TB1> INFO: 41600 events read in total (3394ms).
[13:46:27.964] <TB1> INFO: Test took 4263ms.
[13:46:27.967] <TB1> INFO: scanning low vcal = 210
[13:46:28.244] <TB1> INFO: Expecting 41600 events.
[13:46:32.240] <TB1> INFO: 41600 events read in total (3404ms).
[13:46:32.241] <TB1> INFO: Test took 4273ms.
[13:46:32.244] <TB1> INFO: scanning low vcal = 220
[13:46:32.521] <TB1> INFO: Expecting 41600 events.
[13:46:36.489] <TB1> INFO: 41600 events read in total (3377ms).
[13:46:36.490] <TB1> INFO: Test took 4246ms.
[13:46:36.494] <TB1> INFO: scanning low vcal = 230
[13:46:36.770] <TB1> INFO: Expecting 41600 events.
[13:46:40.762] <TB1> INFO: 41600 events read in total (3400ms).
[13:46:40.762] <TB1> INFO: Test took 4268ms.
[13:46:40.765] <TB1> INFO: scanning low vcal = 240
[13:46:41.043] <TB1> INFO: Expecting 41600 events.
[13:46:45.016] <TB1> INFO: 41600 events read in total (3382ms).
[13:46:45.017] <TB1> INFO: Test took 4252ms.
[13:46:45.021] <TB1> INFO: scanning low vcal = 250
[13:46:45.297] <TB1> INFO: Expecting 41600 events.
[13:46:49.283] <TB1> INFO: 41600 events read in total (3394ms).
[13:46:49.284] <TB1> INFO: Test took 4263ms.
[13:46:49.288] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[13:46:49.564] <TB1> INFO: Expecting 41600 events.
[13:46:53.551] <TB1> INFO: 41600 events read in total (3396ms).
[13:46:53.551] <TB1> INFO: Test took 4263ms.
[13:46:53.554] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[13:46:53.832] <TB1> INFO: Expecting 41600 events.
[13:46:57.812] <TB1> INFO: 41600 events read in total (3389ms).
[13:46:57.812] <TB1> INFO: Test took 4257ms.
[13:46:57.816] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[13:46:58.092] <TB1> INFO: Expecting 41600 events.
[13:47:02.122] <TB1> INFO: 41600 events read in total (3438ms).
[13:47:02.123] <TB1> INFO: Test took 4307ms.
[13:47:02.126] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[13:47:02.403] <TB1> INFO: Expecting 41600 events.
[13:47:06.375] <TB1> INFO: 41600 events read in total (3380ms).
[13:47:06.375] <TB1> INFO: Test took 4249ms.
[13:47:06.379] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:47:06.655] <TB1> INFO: Expecting 41600 events.
[13:47:10.651] <TB1> INFO: 41600 events read in total (3404ms).
[13:47:10.652] <TB1> INFO: Test took 4273ms.
[13:47:11.051] <TB1> INFO: PixTestGainPedestal::measure() done
[13:47:44.012] <TB1> INFO: PixTestGainPedestal::fit() done
[13:47:44.012] <TB1> INFO: non-linearity mean: 0.970 0.931 0.941 0.911 0.945 0.977 0.928 0.976 0.907 0.915 0.965 0.957 0.938 0.912 0.971 0.907
[13:47:44.012] <TB1> INFO: non-linearity RMS: 0.004 0.044 0.030 0.130 0.032 0.003 0.047 0.004 0.149 0.169 0.006 0.008 0.047 0.091 0.005 0.103
[13:47:44.012] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[13:47:44.026] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[13:47:44.039] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[13:47:44.052] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[13:47:44.065] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[13:47:44.079] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[13:47:44.092] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[13:47:44.105] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[13:47:44.118] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[13:47:44.132] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[13:47:44.145] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[13:47:44.158] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[13:47:44.171] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[13:47:44.185] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[13:47:44.198] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[13:47:44.211] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1053_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[13:47:44.224] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 160 seconds
[13:47:44.224] <TB1> INFO: Decoding statistics:
[13:47:44.224] <TB1> INFO: General information:
[13:47:44.224] <TB1> INFO: 16bit words read: 3327840
[13:47:44.224] <TB1> INFO: valid events total: 332800
[13:47:44.224] <TB1> INFO: empty events: 0
[13:47:44.224] <TB1> INFO: valid events with pixels: 332800
[13:47:44.224] <TB1> INFO: valid pixel hits: 665520
[13:47:44.224] <TB1> INFO: Event errors: 0
[13:47:44.224] <TB1> INFO: start marker: 0
[13:47:44.224] <TB1> INFO: stop marker: 0
[13:47:44.224] <TB1> INFO: overflow: 0
[13:47:44.224] <TB1> INFO: invalid 5bit words: 0
[13:47:44.224] <TB1> INFO: invalid XOR eye diagram: 0
[13:47:44.224] <TB1> INFO: frame (failed synchr.): 0
[13:47:44.224] <TB1> INFO: idle data (no TBM trl): 0
[13:47:44.224] <TB1> INFO: no data (only TBM hdr): 0
[13:47:44.224] <TB1> INFO: TBM errors: 0
[13:47:44.224] <TB1> INFO: flawed TBM headers: 0
[13:47:44.225] <TB1> INFO: flawed TBM trailers: 0
[13:47:44.225] <TB1> INFO: event ID mismatches: 0
[13:47:44.225] <TB1> INFO: ROC errors: 0
[13:47:44.225] <TB1> INFO: missing ROC header(s): 0
[13:47:44.225] <TB1> INFO: misplaced readback start: 0
[13:47:44.225] <TB1> INFO: Pixel decoding errors: 0
[13:47:44.225] <TB1> INFO: pixel data incomplete: 0
[13:47:44.225] <TB1> INFO: pixel address: 0
[13:47:44.225] <TB1> INFO: pulse height fill bit: 0
[13:47:44.225] <TB1> INFO: buffer corruption: 0
[13:47:44.241] <TB1> INFO: Decoding statistics:
[13:47:44.241] <TB1> INFO: General information:
[13:47:44.241] <TB1> INFO: 16bit words read: 3457270
[13:47:44.241] <TB1> INFO: valid events total: 353536
[13:47:44.241] <TB1> INFO: empty events: 18229
[13:47:44.241] <TB1> INFO: valid events with pixels: 335307
[13:47:44.241] <TB1> INFO: valid pixel hits: 668027
[13:47:44.241] <TB1> INFO: Event errors: 0
[13:47:44.241] <TB1> INFO: start marker: 0
[13:47:44.241] <TB1> INFO: stop marker: 0
[13:47:44.241] <TB1> INFO: overflow: 0
[13:47:44.241] <TB1> INFO: invalid 5bit words: 0
[13:47:44.241] <TB1> INFO: invalid XOR eye diagram: 0
[13:47:44.241] <TB1> INFO: frame (failed synchr.): 0
[13:47:44.241] <TB1> INFO: idle data (no TBM trl): 0
[13:47:44.241] <TB1> INFO: no data (only TBM hdr): 0
[13:47:44.241] <TB1> INFO: TBM errors: 0
[13:47:44.242] <TB1> INFO: flawed TBM headers: 0
[13:47:44.242] <TB1> INFO: flawed TBM trailers: 0
[13:47:44.242] <TB1> INFO: event ID mismatches: 0
[13:47:44.242] <TB1> INFO: ROC errors: 0
[13:47:44.242] <TB1> INFO: missing ROC header(s): 0
[13:47:44.242] <TB1> INFO: misplaced readback start: 0
[13:47:44.242] <TB1> INFO: Pixel decoding errors: 0
[13:47:44.242] <TB1> INFO: pixel data incomplete: 0
[13:47:44.242] <TB1> INFO: pixel address: 0
[13:47:44.242] <TB1> INFO: pulse height fill bit: 0
[13:47:44.242] <TB1> INFO: buffer corruption: 0
[13:47:44.242] <TB1> INFO: enter test to run
[13:47:44.242] <TB1> INFO: test: exit no parameter change
[13:47:44.369] <TB1> QUIET: Connection to board 154 closed.
[13:47:44.370] <TB1> INFO: pXar: this is the end, my friend