[12:25:42.833] <TB0> INFO: *** Welcome to pxar ***
[12:25:42.833] <TB0> INFO: *** Today: 2016/10/24
[12:25:42.839] <TB0> INFO: *** Version: c8ba-dirty
[12:25:42.839] <TB0> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C15.dat
[12:25:42.840] <TB0> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C1b.dat
[12:25:42.840] <TB0> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//defaultMaskFile.dat
[12:25:42.840] <TB0> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters_C15.dat
[12:25:42.902] <TB0> INFO: clk: 4
[12:25:42.902] <TB0> INFO: ctr: 4
[12:25:42.902] <TB0> INFO: sda: 19
[12:25:42.902] <TB0> INFO: tin: 9
[12:25:42.903] <TB0> INFO: level: 15
[12:25:42.903] <TB0> INFO: triggerdelay: 0
[12:25:42.903] <TB0> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[12:25:42.903] <TB0> INFO: Log level: INFO
[12:25:42.911] <TB0> INFO: Found DTB DTB_WRQ4OZ
[12:25:42.930] <TB0> QUIET: Connection to board DTB_WRQ4OZ opened.
[12:25:42.932] <TB0> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 71
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WRQ4OZ
MAC address: 40D855118047
Hostname: pixelDTB071
Comment:
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[12:25:42.934] <TB0> INFO: RPC call hashes of host and DTB match: 486171790
[12:25:44.423] <TB0> INFO: DUT info:
[12:25:44.423] <TB0> INFO: The DUT currently contains the following objects:
[12:25:44.423] <TB0> INFO: 4 TBM Cores tbm10c (4 ON)
[12:25:44.423] <TB0> INFO: TBM Core alpha (0): 7 registers set
[12:25:44.423] <TB0> INFO: TBM Core beta (1): 7 registers set
[12:25:44.423] <TB0> INFO: TBM Core alpha (2): 7 registers set
[12:25:44.423] <TB0> INFO: TBM Core beta (3): 7 registers set
[12:25:44.423] <TB0> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[12:25:44.423] <TB0> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:44.423] <TB0> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:44.423] <TB0> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:44.423] <TB0> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:44.423] <TB0> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:44.423] <TB0> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:44.423] <TB0> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:44.423] <TB0> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:44.423] <TB0> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:44.423] <TB0> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:44.423] <TB0> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:44.423] <TB0> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:44.423] <TB0> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:44.423] <TB0> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:44.423] <TB0> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:44.423] <TB0> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:25:44.824] <TB0> INFO: enter 'restricted' command line mode
[12:25:44.824] <TB0> INFO: enter test to run
[12:25:44.824] <TB0> INFO: test: pretest no parameter change
[12:25:44.824] <TB0> INFO: running: pretest
[12:25:44.829] <TB0> INFO: ######################################################################
[12:25:44.829] <TB0> INFO: PixTestPretest::doTest()
[12:25:44.829] <TB0> INFO: ######################################################################
[12:25:44.830] <TB0> INFO: ----------------------------------------------------------------------
[12:25:44.830] <TB0> INFO: PixTestPretest::programROC()
[12:25:44.830] <TB0> INFO: ----------------------------------------------------------------------
[12:26:02.844] <TB0> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:26:02.845] <TB0> INFO: IA differences per ROC: 16.1 20.9 17.7 18.5 21.7 20.1 16.9 20.9 19.3 16.9 19.3 16.9 20.1 19.3 18.5 16.9
[12:26:02.911] <TB0> INFO: ----------------------------------------------------------------------
[12:26:02.911] <TB0> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:26:02.911] <TB0> INFO: ----------------------------------------------------------------------
[12:26:24.184] <TB0> INFO: PixTestPretest::setVana() done, Module Ia 388.3 mA = 24.2687 mA/ROC
[12:26:24.184] <TB0> INFO: i(loss) [mA/ROC]: 19.3 18.5 20.1 19.3 17.7 18.5 18.5 19.3 19.3 19.3 19.3 18.5 18.5 19.3 19.3 19.3
[12:26:24.218] <TB0> INFO: ----------------------------------------------------------------------
[12:26:24.218] <TB0> INFO: PixTestPretest::findTiming()
[12:26:24.218] <TB0> INFO: ----------------------------------------------------------------------
[12:26:24.218] <TB0> INFO: PixTestCmd::init()

[12:26:56.711] <TB0> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[12:26:56.711] <TB0> INFO: (success/tries = 100/100), width = 3
[12:26:58.207] <TB0> INFO: ----------------------------------------------------------------------
[12:26:58.207] <TB0> INFO: PixTestPretest::findWorkingPixel()
[12:26:58.207] <TB0> INFO: ----------------------------------------------------------------------
[12:26:58.303] <TB0> INFO: Expecting 231680 events.
[12:27:08.247] <TB0> INFO: 231680 events read in total (9352ms).
[12:27:08.256] <TB0> INFO: Test took 10043ms.
[12:27:08.503] <TB0> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:27:08.541] <TB0> INFO: ----------------------------------------------------------------------
[12:27:08.541] <TB0> INFO: PixTestPretest::setVthrCompCalDel()
[12:27:08.541] <TB0> INFO: ----------------------------------------------------------------------
[12:27:08.637] <TB0> INFO: Expecting 231680 events.
[12:27:18.503] <TB0> INFO: 231680 events read in total (9274ms).
[12:27:18.513] <TB0> INFO: Test took 9965ms.
[12:27:18.780] <TB0> INFO: PixTestPretest::setVthrCompCalDel() done
[12:27:18.780] <TB0> INFO: CalDel: 109 111 100 95 111 113 101 90 111 101 98 104 110 116 91 88
[12:27:18.780] <TB0> INFO: VthrComp: 51 51 52 60 51 51 51 51 51 51 51 51 51 51 51 51
[12:27:18.784] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C0.dat
[12:27:18.784] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C1.dat
[12:27:18.784] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C2.dat
[12:27:18.785] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C3.dat
[12:27:18.785] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C4.dat
[12:27:18.785] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C5.dat
[12:27:18.785] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C6.dat
[12:27:18.785] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C7.dat
[12:27:18.786] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C8.dat
[12:27:18.786] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C9.dat
[12:27:18.786] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C10.dat
[12:27:18.786] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C11.dat
[12:27:18.786] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C12.dat
[12:27:18.786] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C13.dat
[12:27:18.787] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C14.dat
[12:27:18.787] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters_C15.dat
[12:27:18.787] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C0a.dat
[12:27:18.787] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C0b.dat
[12:27:18.787] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C1a.dat
[12:27:18.787] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//tbmParameters_C1b.dat
[12:27:18.787] <TB0> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[12:27:18.841] <TB0> INFO: enter test to run
[12:27:18.841] <TB0> INFO: test: FullTest no parameter change
[12:27:18.841] <TB0> INFO: running: fulltest
[12:27:18.841] <TB0> INFO: ######################################################################
[12:27:18.841] <TB0> INFO: PixTestFullTest::doTest()
[12:27:18.841] <TB0> INFO: ######################################################################
[12:27:18.842] <TB0> INFO: ######################################################################
[12:27:18.842] <TB0> INFO: PixTestAlive::doTest()
[12:27:18.842] <TB0> INFO: ######################################################################
[12:27:18.843] <TB0> INFO: ----------------------------------------------------------------------
[12:27:18.843] <TB0> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:27:18.843] <TB0> INFO: ----------------------------------------------------------------------
[12:27:19.085] <TB0> INFO: Expecting 41600 events.
[12:27:22.702] <TB0> INFO: 41600 events read in total (3026ms).
[12:27:22.702] <TB0> INFO: Test took 3857ms.
[12:27:22.930] <TB0> INFO: PixTestAlive::aliveTest() done
[12:27:22.931] <TB0> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
[12:27:22.932] <TB0> INFO: ----------------------------------------------------------------------
[12:27:22.932] <TB0> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:27:22.932] <TB0> INFO: ----------------------------------------------------------------------
[12:27:23.193] <TB0> INFO: Expecting 41600 events.
[12:27:26.210] <TB0> INFO: 41600 events read in total (2425ms).
[12:27:26.210] <TB0> INFO: Test took 3277ms.
[12:27:26.211] <TB0> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:27:26.448] <TB0> INFO: PixTestAlive::maskTest() done
[12:27:26.448] <TB0> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:27:26.449] <TB0> INFO: ----------------------------------------------------------------------
[12:27:26.449] <TB0> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:27:26.449] <TB0> INFO: ----------------------------------------------------------------------
[12:27:26.694] <TB0> INFO: Expecting 41600 events.
[12:27:30.209] <TB0> INFO: 41600 events read in total (2924ms).
[12:27:30.210] <TB0> INFO: Test took 3759ms.
[12:27:30.443] <TB0> INFO: PixTestAlive::addressDecodingTest() done
[12:27:30.443] <TB0> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:27:30.443] <TB0> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[12:27:30.443] <TB0> INFO: Decoding statistics:
[12:27:30.443] <TB0> INFO: General information:
[12:27:30.443] <TB0> INFO: 16bit words read: 0
[12:27:30.443] <TB0> INFO: valid events total: 0
[12:27:30.443] <TB0> INFO: empty events: 0
[12:27:30.443] <TB0> INFO: valid events with pixels: 0
[12:27:30.443] <TB0> INFO: valid pixel hits: 0
[12:27:30.443] <TB0> INFO: Event errors: 0
[12:27:30.443] <TB0> INFO: start marker: 0
[12:27:30.443] <TB0> INFO: stop marker: 0
[12:27:30.443] <TB0> INFO: overflow: 0
[12:27:30.443] <TB0> INFO: invalid 5bit words: 0
[12:27:30.443] <TB0> INFO: invalid XOR eye diagram: 0
[12:27:30.443] <TB0> INFO: frame (failed synchr.): 0
[12:27:30.444] <TB0> INFO: idle data (no TBM trl): 0
[12:27:30.444] <TB0> INFO: no data (only TBM hdr): 0
[12:27:30.444] <TB0> INFO: TBM errors: 0
[12:27:30.444] <TB0> INFO: flawed TBM headers: 0
[12:27:30.444] <TB0> INFO: flawed TBM trailers: 0
[12:27:30.444] <TB0> INFO: event ID mismatches: 0
[12:27:30.444] <TB0> INFO: ROC errors: 0
[12:27:30.444] <TB0> INFO: missing ROC header(s): 0
[12:27:30.444] <TB0> INFO: misplaced readback start: 0
[12:27:30.444] <TB0> INFO: Pixel decoding errors: 0
[12:27:30.444] <TB0> INFO: pixel data incomplete: 0
[12:27:30.444] <TB0> INFO: pixel address: 0
[12:27:30.444] <TB0> INFO: pulse height fill bit: 0
[12:27:30.444] <TB0> INFO: buffer corruption: 0
[12:27:30.448] <TB0> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C15.dat
[12:27:30.448] <TB0> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[12:27:30.448] <TB0> INFO: ######################################################################
[12:27:30.448] <TB0> INFO: PixTestReadback::doTest()
[12:27:30.448] <TB0> INFO: ######################################################################
[12:27:30.449] <TB0> INFO: ----------------------------------------------------------------------
[12:27:30.449] <TB0> INFO: PixTestReadback::CalibrateVd()
[12:27:30.449] <TB0> INFO: ----------------------------------------------------------------------
[12:27:40.414] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C0.dat
[12:27:40.414] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C1.dat
[12:27:40.414] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C2.dat
[12:27:40.415] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C3.dat
[12:27:40.415] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C4.dat
[12:27:40.415] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C5.dat
[12:27:40.415] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C6.dat
[12:27:40.415] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C7.dat
[12:27:40.415] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C8.dat
[12:27:40.415] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C9.dat
[12:27:40.415] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C10.dat
[12:27:40.415] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C11.dat
[12:27:40.416] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C12.dat
[12:27:40.416] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C13.dat
[12:27:40.416] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C14.dat
[12:27:40.416] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C15.dat
[12:27:40.448] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[12:27:40.448] <TB0> INFO: ----------------------------------------------------------------------
[12:27:40.448] <TB0> INFO: PixTestReadback::CalibrateVa()
[12:27:40.448] <TB0> INFO: ----------------------------------------------------------------------
[12:27:50.376] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C0.dat
[12:27:50.376] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C1.dat
[12:27:50.376] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C2.dat
[12:27:50.376] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C3.dat
[12:27:50.376] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C4.dat
[12:27:50.376] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C5.dat
[12:27:50.376] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C6.dat
[12:27:50.376] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C7.dat
[12:27:50.376] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C8.dat
[12:27:50.376] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C9.dat
[12:27:50.376] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C10.dat
[12:27:50.376] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C11.dat
[12:27:50.376] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C12.dat
[12:27:50.376] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C13.dat
[12:27:50.376] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C14.dat
[12:27:50.377] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C15.dat
[12:27:50.406] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[12:27:50.406] <TB0> INFO: ----------------------------------------------------------------------
[12:27:50.406] <TB0> INFO: PixTestReadback::readbackVbg()
[12:27:50.406] <TB0> INFO: ----------------------------------------------------------------------
[12:27:58.070] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[12:27:58.071] <TB0> INFO: ----------------------------------------------------------------------
[12:27:58.071] <TB0> INFO: PixTestReadback::getCalibratedVbg()
[12:27:58.071] <TB0> INFO: ----------------------------------------------------------------------
[12:27:58.071] <TB0> INFO: Vbg will be calibrated using Vd calibration
[12:27:58.071] <TB0> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 152calibrated Vbg = 1.17307 :::*/*/*/*/
[12:27:58.071] <TB0> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 148.9calibrated Vbg = 1.1711 :::*/*/*/*/
[12:27:58.071] <TB0> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 154.2calibrated Vbg = 1.16895 :::*/*/*/*/
[12:27:58.071] <TB0> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 161.1calibrated Vbg = 1.16294 :::*/*/*/*/
[12:27:58.071] <TB0> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 148.6calibrated Vbg = 1.16548 :::*/*/*/*/
[12:27:58.071] <TB0> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 172.3calibrated Vbg = 1.16916 :::*/*/*/*/
[12:27:58.071] <TB0> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 154.9calibrated Vbg = 1.17553 :::*/*/*/*/
[12:27:58.071] <TB0> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 157.9calibrated Vbg = 1.17108 :::*/*/*/*/
[12:27:58.071] <TB0> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 161.2calibrated Vbg = 1.16838 :::*/*/*/*/
[12:27:58.071] <TB0> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 153.3calibrated Vbg = 1.16321 :::*/*/*/*/
[12:27:58.071] <TB0> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 162.1calibrated Vbg = 1.16474 :::*/*/*/*/
[12:27:58.071] <TB0> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 149.2calibrated Vbg = 1.16216 :::*/*/*/*/
[12:27:58.071] <TB0> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 160.6calibrated Vbg = 1.16144 :::*/*/*/*/
[12:27:58.071] <TB0> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 151.7calibrated Vbg = 1.17138 :::*/*/*/*/
[12:27:58.071] <TB0> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 159.2calibrated Vbg = 1.16884 :::*/*/*/*/
[12:27:58.071] <TB0> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 148.4calibrated Vbg = 1.16247 :::*/*/*/*/
[12:27:58.074] <TB0> INFO: ----------------------------------------------------------------------
[12:27:58.074] <TB0> INFO: PixTestReadback::CalibrateIa()
[12:27:58.074] <TB0> INFO: ----------------------------------------------------------------------
[12:30:38.944] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C0.dat
[12:30:38.944] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C1.dat
[12:30:38.944] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C2.dat
[12:30:38.944] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C3.dat
[12:30:38.944] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C4.dat
[12:30:38.944] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C5.dat
[12:30:38.944] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C6.dat
[12:30:38.944] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C7.dat
[12:30:38.944] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C8.dat
[12:30:38.944] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C9.dat
[12:30:38.945] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C10.dat
[12:30:38.945] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C11.dat
[12:30:38.945] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C12.dat
[12:30:38.945] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C13.dat
[12:30:38.945] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C14.dat
[12:30:38.945] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//readbackCal_C15.dat
[12:30:38.977] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[12:30:38.979] <TB0> INFO: PixTestReadback::doTest() done
[12:30:38.979] <TB0> INFO: Decoding statistics:
[12:30:38.979] <TB0> INFO: General information:
[12:30:38.979] <TB0> INFO: 16bit words read: 1536
[12:30:38.979] <TB0> INFO: valid events total: 256
[12:30:38.979] <TB0> INFO: empty events: 256
[12:30:38.979] <TB0> INFO: valid events with pixels: 0
[12:30:38.979] <TB0> INFO: valid pixel hits: 0
[12:30:38.979] <TB0> INFO: Event errors: 0
[12:30:38.979] <TB0> INFO: start marker: 0
[12:30:38.979] <TB0> INFO: stop marker: 0
[12:30:38.979] <TB0> INFO: overflow: 0
[12:30:38.979] <TB0> INFO: invalid 5bit words: 0
[12:30:38.979] <TB0> INFO: invalid XOR eye diagram: 0
[12:30:38.979] <TB0> INFO: frame (failed synchr.): 0
[12:30:38.980] <TB0> INFO: idle data (no TBM trl): 0
[12:30:38.980] <TB0> INFO: no data (only TBM hdr): 0
[12:30:38.980] <TB0> INFO: TBM errors: 0
[12:30:38.980] <TB0> INFO: flawed TBM headers: 0
[12:30:38.980] <TB0> INFO: flawed TBM trailers: 0
[12:30:38.980] <TB0> INFO: event ID mismatches: 0
[12:30:38.980] <TB0> INFO: ROC errors: 0
[12:30:38.980] <TB0> INFO: missing ROC header(s): 0
[12:30:38.980] <TB0> INFO: misplaced readback start: 0
[12:30:38.980] <TB0> INFO: Pixel decoding errors: 0
[12:30:38.980] <TB0> INFO: pixel data incomplete: 0
[12:30:38.980] <TB0> INFO: pixel address: 0
[12:30:38.980] <TB0> INFO: pulse height fill bit: 0
[12:30:38.980] <TB0> INFO: buffer corruption: 0
[12:30:39.030] <TB0> INFO: ######################################################################
[12:30:39.030] <TB0> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:30:39.030] <TB0> INFO: ######################################################################
[12:30:39.032] <TB0> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:30:39.045] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[12:30:39.045] <TB0> INFO: run 1 of 1
[12:30:39.283] <TB0> INFO: Expecting 3120000 events.
[12:31:10.709] <TB0> INFO: 671075 events read in total (30834ms).











[12:31:41.024] <TB0> INFO: 1336440 events read in total (61149ms).











[12:32:11.327] <TB0> INFO: 1998635 events read in total (91452ms).











[12:32:41.692] <TB0> INFO: 2660280 events read in total (121817ms).











[12:33:02.753] <TB0> INFO: 3120000 events read in total (142878ms).
[12:33:02.815] <TB0> INFO: Test took 143771ms.
[12:33:29.177] <TB0> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 170 seconds
[12:33:29.178] <TB0> INFO: number of dead bumps (per ROC): 0 1 0 2 0 0 0 0 0 0 0 0 0 0 1 0
[12:33:29.178] <TB0> INFO: separation cut (per ROC): 107 105 105 123 110 103 101 119 106 108 114 119 106 105 106 107
[12:33:29.178] <TB0> INFO: Decoding statistics:
[12:33:29.178] <TB0> INFO: General information:
[12:33:29.178] <TB0> INFO: 16bit words read: 0
[12:33:29.178] <TB0> INFO: valid events total: 0
[12:33:29.178] <TB0> INFO: empty events: 0
[12:33:29.178] <TB0> INFO: valid events with pixels: 0
[12:33:29.178] <TB0> INFO: valid pixel hits: 0
[12:33:29.178] <TB0> INFO: Event errors: 0
[12:33:29.178] <TB0> INFO: start marker: 0
[12:33:29.178] <TB0> INFO: stop marker: 0
[12:33:29.178] <TB0> INFO: overflow: 0
[12:33:29.178] <TB0> INFO: invalid 5bit words: 0
[12:33:29.178] <TB0> INFO: invalid XOR eye diagram: 0
[12:33:29.178] <TB0> INFO: frame (failed synchr.): 0
[12:33:29.178] <TB0> INFO: idle data (no TBM trl): 0
[12:33:29.178] <TB0> INFO: no data (only TBM hdr): 0
[12:33:29.178] <TB0> INFO: TBM errors: 0
[12:33:29.178] <TB0> INFO: flawed TBM headers: 0
[12:33:29.178] <TB0> INFO: flawed TBM trailers: 0
[12:33:29.178] <TB0> INFO: event ID mismatches: 0
[12:33:29.178] <TB0> INFO: ROC errors: 0
[12:33:29.178] <TB0> INFO: missing ROC header(s): 0
[12:33:29.178] <TB0> INFO: misplaced readback start: 0
[12:33:29.178] <TB0> INFO: Pixel decoding errors: 0
[12:33:29.178] <TB0> INFO: pixel data incomplete: 0
[12:33:29.178] <TB0> INFO: pixel address: 0
[12:33:29.178] <TB0> INFO: pulse height fill bit: 0
[12:33:29.178] <TB0> INFO: buffer corruption: 0
[12:33:29.214] <TB0> INFO: ######################################################################
[12:33:29.214] <TB0> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:33:29.214] <TB0> INFO: ######################################################################
[12:33:29.214] <TB0> INFO: ----------------------------------------------------------------------
[12:33:29.214] <TB0> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:33:29.214] <TB0> INFO: ----------------------------------------------------------------------
[12:33:29.215] <TB0> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:33:29.229] <TB0> INFO: dacScan split into 1 runs with ntrig = 50
[12:33:29.229] <TB0> INFO: run 1 of 1
[12:33:29.472] <TB0> INFO: Expecting 36608000 events.
[12:33:53.415] <TB0> INFO: 671300 events read in total (23351ms).
[12:34:16.432] <TB0> INFO: 1328250 events read in total (46368ms).
[12:34:39.333] <TB0> INFO: 1987500 events read in total (69269ms).
[12:35:02.478] <TB0> INFO: 2646000 events read in total (92414ms).
[12:35:25.272] <TB0> INFO: 3304850 events read in total (115208ms).
[12:35:48.012] <TB0> INFO: 3961100 events read in total (137948ms).
[12:36:11.066] <TB0> INFO: 4619550 events read in total (161002ms).
[12:36:34.087] <TB0> INFO: 5279050 events read in total (184023ms).
[12:36:57.296] <TB0> INFO: 5938750 events read in total (207232ms).
[12:37:20.468] <TB0> INFO: 6597700 events read in total (230404ms).
[12:37:43.458] <TB0> INFO: 7254150 events read in total (253394ms).
[12:38:06.224] <TB0> INFO: 7910200 events read in total (276160ms).
[12:38:29.358] <TB0> INFO: 8566400 events read in total (299294ms).
[12:38:52.485] <TB0> INFO: 9227650 events read in total (322421ms).
[12:39:15.211] <TB0> INFO: 9885150 events read in total (345147ms).
[12:39:38.150] <TB0> INFO: 10542400 events read in total (368086ms).
[12:40:01.138] <TB0> INFO: 11199500 events read in total (391074ms).
[12:40:23.881] <TB0> INFO: 11857300 events read in total (413817ms).
[12:40:46.540] <TB0> INFO: 12513050 events read in total (436476ms).
[12:41:09.164] <TB0> INFO: 13170700 events read in total (459100ms).
[12:41:31.882] <TB0> INFO: 13826750 events read in total (481818ms).
[12:41:54.281] <TB0> INFO: 14482950 events read in total (504217ms).
[12:42:16.938] <TB0> INFO: 15138250 events read in total (526874ms).
[12:42:39.653] <TB0> INFO: 15793900 events read in total (549589ms).
[12:43:02.557] <TB0> INFO: 16451550 events read in total (572493ms).
[12:43:25.229] <TB0> INFO: 17105650 events read in total (595165ms).
[12:43:48.133] <TB0> INFO: 17762050 events read in total (618069ms).
[12:44:10.939] <TB0> INFO: 18416500 events read in total (640875ms).
[12:44:33.871] <TB0> INFO: 19070400 events read in total (663807ms).
[12:44:56.754] <TB0> INFO: 19723800 events read in total (686690ms).
[12:45:19.791] <TB0> INFO: 20376850 events read in total (709727ms).
[12:45:42.468] <TB0> INFO: 21028650 events read in total (732404ms).
[12:46:05.314] <TB0> INFO: 21683000 events read in total (755250ms).
[12:46:28.278] <TB0> INFO: 22337750 events read in total (778214ms).
[12:46:50.888] <TB0> INFO: 22991650 events read in total (800824ms).
[12:47:13.798] <TB0> INFO: 23644600 events read in total (823734ms).
[12:47:36.536] <TB0> INFO: 24297150 events read in total (846472ms).
[12:47:59.524] <TB0> INFO: 24950550 events read in total (869460ms).
[12:48:22.667] <TB0> INFO: 25603150 events read in total (892603ms).
[12:48:45.504] <TB0> INFO: 26255200 events read in total (915440ms).
[12:49:08.280] <TB0> INFO: 26906650 events read in total (938216ms).
[12:49:31.467] <TB0> INFO: 27558350 events read in total (961403ms).
[12:49:54.126] <TB0> INFO: 28208600 events read in total (984062ms).
[12:50:17.250] <TB0> INFO: 28860200 events read in total (1007186ms).
[12:50:40.084] <TB0> INFO: 29508450 events read in total (1030020ms).
[12:51:02.959] <TB0> INFO: 30158050 events read in total (1052895ms).
[12:51:25.650] <TB0> INFO: 30807100 events read in total (1075586ms).
[12:51:48.668] <TB0> INFO: 31457650 events read in total (1098604ms).
[12:52:11.590] <TB0> INFO: 32109050 events read in total (1121526ms).
[12:52:34.128] <TB0> INFO: 32760500 events read in total (1144064ms).
[12:52:56.847] <TB0> INFO: 33411750 events read in total (1166783ms).
[12:53:19.478] <TB0> INFO: 34064650 events read in total (1189414ms).
[12:53:42.561] <TB0> INFO: 34717950 events read in total (1212497ms).
[12:54:05.450] <TB0> INFO: 35370500 events read in total (1235386ms).
[12:54:28.410] <TB0> INFO: 36026700 events read in total (1258346ms).
[12:54:48.807] <TB0> INFO: 36608000 events read in total (1278743ms).
[12:54:48.878] <TB0> INFO: Test took 1279649ms.
[12:54:49.342] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:54:51.179] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:54:53.148] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:54:55.073] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:54:57.092] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:54:59.162] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:55:01.194] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:55:03.242] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:55:04.813] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:55:06.614] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:55:08.980] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:55:11.456] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:55:13.589] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:55:15.661] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:55:17.776] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:55:20.010] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[12:55:21.608] <TB0> INFO: PixTestScurves::scurves() done
[12:55:21.608] <TB0> INFO: Vcal mean: 110.19 113.12 114.95 125.64 115.85 118.25 112.84 126.32 108.44 120.68 110.89 106.37 112.56 115.68 108.89 106.18
[12:55:21.608] <TB0> INFO: Vcal RMS: 5.37 5.31 6.41 8.39 5.64 5.83 5.39 6.43 5.04 6.69 5.76 5.41 5.02 6.55 4.67 4.82
[12:55:21.608] <TB0> INFO: PixTestScurves::fullTest() done, duration: 1312 seconds
[12:55:21.608] <TB0> INFO: Decoding statistics:
[12:55:21.608] <TB0> INFO: General information:
[12:55:21.608] <TB0> INFO: 16bit words read: 0
[12:55:21.608] <TB0> INFO: valid events total: 0
[12:55:21.608] <TB0> INFO: empty events: 0
[12:55:21.608] <TB0> INFO: valid events with pixels: 0
[12:55:21.608] <TB0> INFO: valid pixel hits: 0
[12:55:21.608] <TB0> INFO: Event errors: 0
[12:55:21.608] <TB0> INFO: start marker: 0
[12:55:21.608] <TB0> INFO: stop marker: 0
[12:55:21.608] <TB0> INFO: overflow: 0
[12:55:21.608] <TB0> INFO: invalid 5bit words: 0
[12:55:21.608] <TB0> INFO: invalid XOR eye diagram: 0
[12:55:21.608] <TB0> INFO: frame (failed synchr.): 0
[12:55:21.608] <TB0> INFO: idle data (no TBM trl): 0
[12:55:21.608] <TB0> INFO: no data (only TBM hdr): 0
[12:55:21.608] <TB0> INFO: TBM errors: 0
[12:55:21.608] <TB0> INFO: flawed TBM headers: 0
[12:55:21.608] <TB0> INFO: flawed TBM trailers: 0
[12:55:21.608] <TB0> INFO: event ID mismatches: 0
[12:55:21.608] <TB0> INFO: ROC errors: 0
[12:55:21.608] <TB0> INFO: missing ROC header(s): 0
[12:55:21.608] <TB0> INFO: misplaced readback start: 0
[12:55:21.608] <TB0> INFO: Pixel decoding errors: 0
[12:55:21.608] <TB0> INFO: pixel data incomplete: 0
[12:55:21.608] <TB0> INFO: pixel address: 0
[12:55:21.608] <TB0> INFO: pulse height fill bit: 0
[12:55:21.608] <TB0> INFO: buffer corruption: 0
[12:55:21.674] <TB0> INFO: ######################################################################
[12:55:21.674] <TB0> INFO: PixTestTrim::doTest()
[12:55:21.674] <TB0> INFO: ######################################################################
[12:55:21.675] <TB0> INFO: ----------------------------------------------------------------------
[12:55:21.675] <TB0> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:55:21.675] <TB0> INFO: ----------------------------------------------------------------------
[12:55:21.716] <TB0> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:55:21.716] <TB0> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:55:21.729] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:55:21.729] <TB0> INFO: run 1 of 1
[12:55:21.966] <TB0> INFO: Expecting 5025280 events.
[12:55:52.569] <TB0> INFO: 816480 events read in total (30000ms).
[12:56:22.409] <TB0> INFO: 1630616 events read in total (59840ms).
[12:56:52.487] <TB0> INFO: 2442568 events read in total (89918ms).
[12:57:22.332] <TB0> INFO: 3251776 events read in total (119763ms).
[12:57:52.170] <TB0> INFO: 4057936 events read in total (149601ms).
[12:58:22.328] <TB0> INFO: 4863008 events read in total (179759ms).
[12:58:28.681] <TB0> INFO: 5025280 events read in total (186112ms).
[12:58:28.732] <TB0> INFO: Test took 187003ms.
[12:58:49.371] <TB0> INFO: ROC 0 VthrComp = 115
[12:58:49.372] <TB0> INFO: ROC 1 VthrComp = 114
[12:58:49.372] <TB0> INFO: ROC 2 VthrComp = 117
[12:58:49.372] <TB0> INFO: ROC 3 VthrComp = 130
[12:58:49.372] <TB0> INFO: ROC 4 VthrComp = 120
[12:58:49.372] <TB0> INFO: ROC 5 VthrComp = 116
[12:58:49.372] <TB0> INFO: ROC 6 VthrComp = 107
[12:58:49.372] <TB0> INFO: ROC 7 VthrComp = 132
[12:58:49.376] <TB0> INFO: ROC 8 VthrComp = 110
[12:58:49.376] <TB0> INFO: ROC 9 VthrComp = 120
[12:58:49.376] <TB0> INFO: ROC 10 VthrComp = 120
[12:58:49.376] <TB0> INFO: ROC 11 VthrComp = 115
[12:58:49.377] <TB0> INFO: ROC 12 VthrComp = 112
[12:58:49.377] <TB0> INFO: ROC 13 VthrComp = 111
[12:58:49.377] <TB0> INFO: ROC 14 VthrComp = 118
[12:58:49.377] <TB0> INFO: ROC 15 VthrComp = 111
[12:58:49.632] <TB0> INFO: Expecting 41600 events.
[12:58:53.163] <TB0> INFO: 41600 events read in total (2939ms).
[12:58:53.164] <TB0> INFO: Test took 3785ms.
[12:58:53.175] <TB0> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:58:53.175] <TB0> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:58:53.189] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[12:58:53.189] <TB0> INFO: run 1 of 1
[12:58:53.474] <TB0> INFO: Expecting 5025280 events.
[12:59:19.665] <TB0> INFO: 590808 events read in total (25599ms).
[12:59:44.997] <TB0> INFO: 1181184 events read in total (50931ms).
[13:00:10.878] <TB0> INFO: 1771496 events read in total (76812ms).
[13:00:36.614] <TB0> INFO: 2361408 events read in total (102548ms).
[13:01:02.518] <TB0> INFO: 2949176 events read in total (128452ms).
[13:01:28.181] <TB0> INFO: 3534856 events read in total (154115ms).
[13:01:53.572] <TB0> INFO: 4118440 events read in total (179506ms).
[13:02:18.827] <TB0> INFO: 4701032 events read in total (204761ms).
[13:02:33.330] <TB0> INFO: 5025280 events read in total (219264ms).
[13:02:33.407] <TB0> INFO: Test took 220218ms.
[13:03:02.368] <TB0> INFO: roc 0 with ID = 0 has maximal Vcal 60.4418 for pixel 27/75 mean/min/max = 46.0089/31.2995/60.7183
[13:03:02.369] <TB0> INFO: roc 1 with ID = 1 has maximal Vcal 61.0817 for pixel 17/17 mean/min/max = 46.5748/31.9251/61.2244
[13:03:02.369] <TB0> INFO: roc 2 with ID = 2 has maximal Vcal 60.6055 for pixel 0/13 mean/min/max = 45.9178/31.0623/60.7734
[13:03:02.369] <TB0> INFO: roc 3 with ID = 3 has maximal Vcal 66.7776 for pixel 1/74 mean/min/max = 49.04/31.2161/66.864
[13:03:02.370] <TB0> INFO: roc 4 with ID = 4 has maximal Vcal 60.9807 for pixel 44/67 mean/min/max = 46.2944/31.5015/61.0874
[13:03:02.370] <TB0> INFO: roc 5 with ID = 5 has maximal Vcal 59.9216 for pixel 9/11 mean/min/max = 46.0374/32.1202/59.9545
[13:03:02.370] <TB0> INFO: roc 6 with ID = 6 has maximal Vcal 65.9687 for pixel 1/17 mean/min/max = 50.0978/33.7788/66.4169
[13:03:02.371] <TB0> INFO: roc 7 with ID = 7 has maximal Vcal 59.6185 for pixel 16/0 mean/min/max = 45.5882/31.4161/59.7603
[13:03:02.371] <TB0> INFO: roc 8 with ID = 8 has maximal Vcal 62.3614 for pixel 20/1 mean/min/max = 48.4283/34.4498/62.4069
[13:03:02.371] <TB0> INFO: roc 9 with ID = 9 has maximal Vcal 63.8763 for pixel 23/73 mean/min/max = 47.8914/31.5598/64.223
[13:03:02.372] <TB0> INFO: roc 10 with ID = 10 has maximal Vcal 60.8149 for pixel 18/75 mean/min/max = 45.6153/30.319/60.9117
[13:03:02.372] <TB0> INFO: roc 11 with ID = 11 has maximal Vcal 60.3979 for pixel 12/17 mean/min/max = 46.0497/31.5345/60.5649
[13:03:02.372] <TB0> INFO: roc 12 with ID = 12 has maximal Vcal 60.723 for pixel 25/79 mean/min/max = 46.728/32.6899/60.766
[13:03:02.373] <TB0> INFO: roc 13 with ID = 13 has maximal Vcal 65.0867 for pixel 8/79 mean/min/max = 49.4919/33.687/65.2967
[13:03:02.373] <TB0> INFO: roc 14 with ID = 14 has maximal Vcal 58.0917 for pixel 12/23 mean/min/max = 45.0731/31.8536/58.2926
[13:03:02.373] <TB0> INFO: roc 15 with ID = 15 has maximal Vcal 60.3723 for pixel 51/8 mean/min/max = 47.4344/34.3553/60.5135
[13:03:02.374] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:03:02.462] <TB0> INFO: Expecting 411648 events.
[13:03:11.764] <TB0> INFO: 411648 events read in total (8710ms).
[13:03:11.772] <TB0> INFO: Expecting 411648 events.
[13:03:20.808] <TB0> INFO: 411648 events read in total (8633ms).
[13:03:20.818] <TB0> INFO: Expecting 411648 events.
[13:03:30.034] <TB0> INFO: 411648 events read in total (8813ms).
[13:03:30.046] <TB0> INFO: Expecting 411648 events.
[13:03:39.404] <TB0> INFO: 411648 events read in total (8955ms).
[13:03:39.419] <TB0> INFO: Expecting 411648 events.
[13:03:48.756] <TB0> INFO: 411648 events read in total (8934ms).
[13:03:48.774] <TB0> INFO: Expecting 411648 events.
[13:03:58.083] <TB0> INFO: 411648 events read in total (8906ms).
[13:03:58.108] <TB0> INFO: Expecting 411648 events.
[13:04:07.457] <TB0> INFO: 411648 events read in total (8946ms).
[13:04:07.479] <TB0> INFO: Expecting 411648 events.
[13:04:16.794] <TB0> INFO: 411648 events read in total (8912ms).
[13:04:16.820] <TB0> INFO: Expecting 411648 events.
[13:04:26.114] <TB0> INFO: 411648 events read in total (8891ms).
[13:04:26.142] <TB0> INFO: Expecting 411648 events.
[13:04:35.386] <TB0> INFO: 411648 events read in total (8841ms).
[13:04:35.417] <TB0> INFO: Expecting 411648 events.
[13:04:44.685] <TB0> INFO: 411648 events read in total (8865ms).
[13:04:44.724] <TB0> INFO: Expecting 411648 events.
[13:04:54.017] <TB0> INFO: 411648 events read in total (8890ms).
[13:04:54.058] <TB0> INFO: Expecting 411648 events.
[13:05:03.375] <TB0> INFO: 411648 events read in total (8914ms).
[13:05:03.473] <TB0> INFO: Expecting 411648 events.
[13:05:12.848] <TB0> INFO: 411648 events read in total (8972ms).
[13:05:12.908] <TB0> INFO: Expecting 411648 events.
[13:05:22.229] <TB0> INFO: 411648 events read in total (8918ms).
[13:05:22.454] <TB0> INFO: Expecting 411648 events.
[13:05:31.686] <TB0> INFO: 411648 events read in total (8829ms).
[13:05:31.793] <TB0> INFO: Test took 149419ms.
[13:05:32.555] <TB0> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:05:32.569] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:05:32.569] <TB0> INFO: run 1 of 1
[13:05:32.850] <TB0> INFO: Expecting 5025280 events.
[13:05:59.295] <TB0> INFO: 587088 events read in total (25853ms).
[13:06:25.047] <TB0> INFO: 1171920 events read in total (51605ms).
[13:06:51.106] <TB0> INFO: 1757104 events read in total (77664ms).
[13:07:17.135] <TB0> INFO: 2342208 events read in total (103693ms).
[13:07:43.153] <TB0> INFO: 2925696 events read in total (129711ms).
[13:08:08.925] <TB0> INFO: 3510904 events read in total (155483ms).
[13:08:34.912] <TB0> INFO: 4094024 events read in total (181470ms).
[13:09:00.561] <TB0> INFO: 4678888 events read in total (207119ms).
[13:09:16.164] <TB0> INFO: 5025280 events read in total (222722ms).
[13:09:16.318] <TB0> INFO: Test took 223749ms.
[13:09:43.506] <TB0> INFO: ---> TrimStepCorr4 extremal thresholds: 2.328320 .. 145.005870
[13:09:43.747] <TB0> INFO: Expecting 208000 events.
[13:09:53.710] <TB0> INFO: 208000 events read in total (9371ms).
[13:09:53.711] <TB0> INFO: Test took 10203ms.
[13:09:53.759] <TB0> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 155 (-1/-1) hits flags = 528 (plus default)
[13:09:53.772] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:09:53.772] <TB0> INFO: run 1 of 1
[13:09:54.050] <TB0> INFO: Expecting 5125120 events.
[13:10:20.301] <TB0> INFO: 583216 events read in total (25659ms).
[13:10:46.087] <TB0> INFO: 1166488 events read in total (51445ms).
[13:11:12.065] <TB0> INFO: 1749336 events read in total (77423ms).
[13:11:37.675] <TB0> INFO: 2332600 events read in total (103033ms).
[13:12:03.799] <TB0> INFO: 2916072 events read in total (129158ms).
[13:12:29.622] <TB0> INFO: 3498656 events read in total (154980ms).
[13:12:55.907] <TB0> INFO: 4080616 events read in total (181265ms).
[13:13:21.908] <TB0> INFO: 4660720 events read in total (207266ms).
[13:13:42.808] <TB0> INFO: 5125120 events read in total (228166ms).
[13:13:42.910] <TB0> INFO: Test took 229139ms.
[13:14:10.432] <TB0> INFO: ---> TrimStepCorr2 extremal thresholds: 26.500000 .. 46.834338
[13:14:10.674] <TB0> INFO: Expecting 208000 events.
[13:14:20.418] <TB0> INFO: 208000 events read in total (9152ms).
[13:14:20.419] <TB0> INFO: Test took 9986ms.
[13:14:20.465] <TB0> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 56 (-1/-1) hits flags = 528 (plus default)
[13:14:20.478] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:14:20.478] <TB0> INFO: run 1 of 1
[13:14:20.756] <TB0> INFO: Expecting 1364480 events.
[13:14:49.018] <TB0> INFO: 658456 events read in total (27670ms).
[13:15:17.061] <TB0> INFO: 1315024 events read in total (55714ms).
[13:15:19.643] <TB0> INFO: 1364480 events read in total (58296ms).
[13:15:19.682] <TB0> INFO: Test took 59205ms.
[13:15:34.664] <TB0> INFO: ---> TrimStepCorr1a extremal thresholds: 26.012593 .. 49.782853
[13:15:34.922] <TB0> INFO: Expecting 208000 events.
[13:15:44.530] <TB0> INFO: 208000 events read in total (9016ms).
[13:15:44.531] <TB0> INFO: Test took 9865ms.
[13:15:44.577] <TB0> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 59 (-1/-1) hits flags = 528 (plus default)
[13:15:44.590] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:15:44.590] <TB0> INFO: run 1 of 1
[13:15:44.869] <TB0> INFO: Expecting 1464320 events.
[13:16:13.370] <TB0> INFO: 648640 events read in total (27909ms).
[13:16:41.097] <TB0> INFO: 1296048 events read in total (55636ms).
[13:16:48.750] <TB0> INFO: 1464320 events read in total (63290ms).
[13:16:48.782] <TB0> INFO: Test took 64192ms.
[13:17:02.434] <TB0> INFO: ---> TrimStepCorr1b extremal thresholds: 25.489791 .. 47.500967
[13:17:02.672] <TB0> INFO: Expecting 208000 events.
[13:17:12.176] <TB0> INFO: 208000 events read in total (8912ms).
[13:17:12.177] <TB0> INFO: Test took 9741ms.
[13:17:12.247] <TB0> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 57 (-1/-1) hits flags = 528 (plus default)
[13:17:12.261] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:17:12.261] <TB0> INFO: run 1 of 1
[13:17:12.540] <TB0> INFO: Expecting 1431040 events.
[13:17:40.747] <TB0> INFO: 659512 events read in total (27615ms).
[13:18:09.207] <TB0> INFO: 1319064 events read in total (56075ms).
[13:18:14.122] <TB0> INFO: 1431040 events read in total (60990ms).
[13:18:14.151] <TB0> INFO: Test took 61890ms.
[13:18:26.491] <TB0> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[13:18:26.491] <TB0> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[13:18:26.504] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:18:26.504] <TB0> INFO: run 1 of 1
[13:18:26.747] <TB0> INFO: Expecting 1364480 events.
[13:18:55.225] <TB0> INFO: 667248 events read in total (27887ms).
[13:19:23.402] <TB0> INFO: 1334200 events read in total (56064ms).
[13:19:25.052] <TB0> INFO: 1364480 events read in total (57715ms).
[13:19:25.080] <TB0> INFO: Test took 58576ms.
[13:19:37.930] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C0.dat
[13:19:37.930] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C1.dat
[13:19:37.930] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C2.dat
[13:19:37.930] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C3.dat
[13:19:37.930] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C4.dat
[13:19:37.930] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C5.dat
[13:19:37.930] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C6.dat
[13:19:37.930] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C7.dat
[13:19:37.931] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C8.dat
[13:19:37.931] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C9.dat
[13:19:37.931] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C10.dat
[13:19:37.931] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C11.dat
[13:19:37.931] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C12.dat
[13:19:37.931] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C13.dat
[13:19:37.931] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C14.dat
[13:19:37.931] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C15.dat
[13:19:37.931] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C0.dat
[13:19:37.938] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C1.dat
[13:19:37.944] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C2.dat
[13:19:37.950] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C3.dat
[13:19:37.957] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C4.dat
[13:19:37.963] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C5.dat
[13:19:37.969] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C6.dat
[13:19:37.975] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C7.dat
[13:19:37.982] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C8.dat
[13:19:37.989] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C9.dat
[13:19:37.995] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C10.dat
[13:19:37.002] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C11.dat
[13:19:38.006] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C12.dat
[13:19:38.011] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C13.dat
[13:19:38.016] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C14.dat
[13:19:38.021] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//trimParameters35_C15.dat
[13:19:38.025] <TB0> INFO: PixTestTrim::trimTest() done
[13:19:38.025] <TB0> INFO: vtrim: 129 129 106 145 135 106 133 133 132 127 136 130 115 122 121 130
[13:19:38.025] <TB0> INFO: vthrcomp: 115 114 117 130 120 116 107 132 110 120 120 115 112 111 118 111
[13:19:38.025] <TB0> INFO: vcal mean: 34.94 34.91 34.94 35.07 34.96 34.92 35.53 34.94 35.01 35.18 34.94 34.97 34.98 34.99 34.99 34.97
[13:19:38.025] <TB0> INFO: vcal RMS: 1.05 1.15 1.09 1.25 1.09 1.11 1.78 1.17 1.05 1.41 1.20 1.03 1.11 1.09 1.04 1.00
[13:19:38.025] <TB0> INFO: bits mean: 9.65 9.70 9.21 9.47 9.72 9.48 9.31 10.04 8.66 9.67 9.86 9.54 9.48 8.53 9.28 8.52
[13:19:38.025] <TB0> INFO: bits RMS: 2.70 2.56 2.93 2.57 2.64 2.68 2.56 2.55 2.56 2.60 2.71 2.74 2.66 2.68 2.87 2.63
[13:19:38.033] <TB0> INFO: ----------------------------------------------------------------------
[13:19:38.033] <TB0> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:19:38.033] <TB0> INFO: ----------------------------------------------------------------------
[13:19:38.036] <TB0> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:19:38.050] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:19:38.050] <TB0> INFO: run 1 of 1
[13:19:38.290] <TB0> INFO: Expecting 4160000 events.
[13:20:10.710] <TB0> INFO: 738180 events read in total (31829ms).
[13:20:42.231] <TB0> INFO: 1472630 events read in total (63350ms).
[13:21:13.670] <TB0> INFO: 2203725 events read in total (94789ms).
[13:21:45.129] <TB0> INFO: 2932630 events read in total (126248ms).
[13:22:16.739] <TB0> INFO: 3657060 events read in total (157859ms).
[13:22:38.605] <TB0> INFO: 4160000 events read in total (179724ms).
[13:22:38.896] <TB0> INFO: Test took 180846ms.
[13:23:05.077] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[13:23:05.090] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:23:05.090] <TB0> INFO: run 1 of 1
[13:23:05.326] <TB0> INFO: Expecting 4430400 events.
[13:23:36.830] <TB0> INFO: 700700 events read in total (30912ms).
[13:24:07.675] <TB0> INFO: 1398510 events read in total (61757ms).
[13:24:38.316] <TB0> INFO: 2094265 events read in total (92398ms).
[13:25:08.862] <TB0> INFO: 2787355 events read in total (122944ms).
[13:25:39.586] <TB0> INFO: 3477175 events read in total (153668ms).
[13:26:10.196] <TB0> INFO: 4165730 events read in total (184278ms).
[13:26:22.374] <TB0> INFO: 4430400 events read in total (196456ms).
[13:26:22.470] <TB0> INFO: Test took 197380ms.
[13:26:52.195] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[13:26:52.209] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:26:52.209] <TB0> INFO: run 1 of 1
[13:26:52.488] <TB0> INFO: Expecting 4284800 events.
[13:27:24.039] <TB0> INFO: 708630 events read in total (30960ms).
[13:27:54.961] <TB0> INFO: 1414425 events read in total (61882ms).
[13:28:25.931] <TB0> INFO: 2117500 events read in total (92852ms).
[13:28:56.581] <TB0> INFO: 2817510 events read in total (123502ms).
[13:29:27.160] <TB0> INFO: 3513650 events read in total (154081ms).
[13:29:57.981] <TB0> INFO: 4210520 events read in total (184902ms).
[13:30:01.727] <TB0> INFO: 4284800 events read in total (188648ms).
[13:30:01.942] <TB0> INFO: Test took 189732ms.
[13:30:29.145] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[13:30:29.159] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:30:29.159] <TB0> INFO: run 1 of 1
[13:30:29.406] <TB0> INFO: Expecting 4430400 events.
[13:31:00.831] <TB0> INFO: 701285 events read in total (30834ms).
[13:31:31.662] <TB0> INFO: 1399355 events read in total (61665ms).
[13:32:02.417] <TB0> INFO: 2095545 events read in total (92420ms).
[13:32:32.854] <TB0> INFO: 2788915 events read in total (122857ms).
[13:33:03.247] <TB0> INFO: 3479030 events read in total (153250ms).
[13:33:33.924] <TB0> INFO: 4168015 events read in total (183927ms).
[13:33:45.880] <TB0> INFO: 4430400 events read in total (195883ms).
[13:33:46.128] <TB0> INFO: Test took 196968ms.
[13:34:13.587] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 216 (-1/-1) hits flags = 528 (plus default)
[13:34:13.600] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:34:13.600] <TB0> INFO: run 1 of 1
[13:34:13.840] <TB0> INFO: Expecting 4513600 events.
[13:34:45.455] <TB0> INFO: 697340 events read in total (31023ms).
[13:35:16.163] <TB0> INFO: 1391895 events read in total (61731ms).
[13:35:46.976] <TB0> INFO: 2084385 events read in total (92544ms).
[13:36:17.897] <TB0> INFO: 2774310 events read in total (123465ms).
[13:36:48.239] <TB0> INFO: 3461020 events read in total (153807ms).
[13:37:19.238] <TB0> INFO: 4145765 events read in total (184806ms).
[13:37:35.936] <TB0> INFO: 4513600 events read in total (201504ms).
[13:37:36.017] <TB0> INFO: Test took 202416ms.
[13:38:02.781] <TB0> INFO: PixTestTrim::trimBitTest() done
[13:38:02.783] <TB0> INFO: PixTestTrim::doTest() done, duration: 2561 seconds
[13:38:02.783] <TB0> INFO: Decoding statistics:
[13:38:02.783] <TB0> INFO: General information:
[13:38:02.783] <TB0> INFO: 16bit words read: 0
[13:38:02.783] <TB0> INFO: valid events total: 0
[13:38:02.783] <TB0> INFO: empty events: 0
[13:38:02.783] <TB0> INFO: valid events with pixels: 0
[13:38:02.783] <TB0> INFO: valid pixel hits: 0
[13:38:02.783] <TB0> INFO: Event errors: 0
[13:38:02.783] <TB0> INFO: start marker: 0
[13:38:02.783] <TB0> INFO: stop marker: 0
[13:38:02.783] <TB0> INFO: overflow: 0
[13:38:02.783] <TB0> INFO: invalid 5bit words: 0
[13:38:02.783] <TB0> INFO: invalid XOR eye diagram: 0
[13:38:02.783] <TB0> INFO: frame (failed synchr.): 0
[13:38:02.783] <TB0> INFO: idle data (no TBM trl): 0
[13:38:02.783] <TB0> INFO: no data (only TBM hdr): 0
[13:38:02.783] <TB0> INFO: TBM errors: 0
[13:38:02.783] <TB0> INFO: flawed TBM headers: 0
[13:38:02.783] <TB0> INFO: flawed TBM trailers: 0
[13:38:02.783] <TB0> INFO: event ID mismatches: 0
[13:38:02.783] <TB0> INFO: ROC errors: 0
[13:38:02.783] <TB0> INFO: missing ROC header(s): 0
[13:38:02.783] <TB0> INFO: misplaced readback start: 0
[13:38:02.783] <TB0> INFO: Pixel decoding errors: 0
[13:38:02.783] <TB0> INFO: pixel data incomplete: 0
[13:38:02.783] <TB0> INFO: pixel address: 0
[13:38:02.783] <TB0> INFO: pulse height fill bit: 0
[13:38:02.783] <TB0> INFO: buffer corruption: 0
[13:38:03.398] <TB0> INFO: ######################################################################
[13:38:03.398] <TB0> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:38:03.398] <TB0> INFO: ######################################################################
[13:38:03.645] <TB0> INFO: Expecting 41600 events.
[13:38:07.188] <TB0> INFO: 41600 events read in total (2951ms).
[13:38:07.189] <TB0> INFO: Test took 3790ms.
[13:38:07.627] <TB0> INFO: Expecting 41600 events.
[13:38:11.142] <TB0> INFO: 41600 events read in total (2923ms).
[13:38:11.143] <TB0> INFO: Test took 3752ms.
[13:38:11.431] <TB0> INFO: Expecting 41600 events.
[13:38:14.937] <TB0> INFO: 41600 events read in total (2914ms).
[13:38:14.938] <TB0> INFO: Test took 3771ms.
[13:38:15.229] <TB0> INFO: Expecting 41600 events.
[13:38:18.847] <TB0> INFO: 41600 events read in total (3026ms).
[13:38:18.848] <TB0> INFO: Test took 3883ms.
[13:38:19.178] <TB0> INFO: Expecting 41600 events.
[13:38:22.790] <TB0> INFO: 41600 events read in total (3021ms).
[13:38:22.791] <TB0> INFO: Test took 3914ms.
[13:38:23.080] <TB0> INFO: Expecting 41600 events.
[13:38:26.598] <TB0> INFO: 41600 events read in total (2927ms).
[13:38:26.599] <TB0> INFO: Test took 3784ms.
[13:38:26.888] <TB0> INFO: Expecting 41600 events.
[13:38:30.421] <TB0> INFO: 41600 events read in total (2942ms).
[13:38:30.422] <TB0> INFO: Test took 3799ms.
[13:38:30.711] <TB0> INFO: Expecting 41600 events.
[13:38:34.346] <TB0> INFO: 41600 events read in total (3043ms).
[13:38:34.347] <TB0> INFO: Test took 3901ms.
[13:38:34.673] <TB0> INFO: Expecting 41600 events.
[13:38:38.212] <TB0> INFO: 41600 events read in total (2948ms).
[13:38:38.213] <TB0> INFO: Test took 3837ms.
[13:38:38.505] <TB0> INFO: Expecting 41600 events.
[13:38:41.999] <TB0> INFO: 41600 events read in total (2903ms).
[13:38:41.000] <TB0> INFO: Test took 3760ms.
[13:38:42.289] <TB0> INFO: Expecting 41600 events.
[13:38:45.791] <TB0> INFO: 41600 events read in total (2910ms).
[13:38:45.792] <TB0> INFO: Test took 3767ms.
[13:38:46.080] <TB0> INFO: Expecting 41600 events.
[13:38:49.622] <TB0> INFO: 41600 events read in total (2950ms).
[13:38:49.622] <TB0> INFO: Test took 3806ms.
[13:38:49.912] <TB0> INFO: Expecting 41600 events.
[13:38:53.440] <TB0> INFO: 41600 events read in total (2936ms).
[13:38:53.441] <TB0> INFO: Test took 3794ms.
[13:38:53.732] <TB0> INFO: Expecting 41600 events.
[13:38:57.328] <TB0> INFO: 41600 events read in total (3004ms).
[13:38:57.328] <TB0> INFO: Test took 3860ms.
[13:38:57.620] <TB0> INFO: Expecting 41600 events.
[13:39:01.205] <TB0> INFO: 41600 events read in total (2994ms).
[13:39:01.206] <TB0> INFO: Test took 3851ms.
[13:39:01.495] <TB0> INFO: Expecting 41600 events.
[13:39:04.990] <TB0> INFO: 41600 events read in total (2903ms).
[13:39:04.991] <TB0> INFO: Test took 3761ms.
[13:39:05.280] <TB0> INFO: Expecting 41600 events.
[13:39:08.784] <TB0> INFO: 41600 events read in total (2913ms).
[13:39:08.785] <TB0> INFO: Test took 3770ms.
[13:39:09.073] <TB0> INFO: Expecting 41600 events.
[13:39:12.696] <TB0> INFO: 41600 events read in total (3031ms).
[13:39:12.697] <TB0> INFO: Test took 3889ms.
[13:39:12.986] <TB0> INFO: Expecting 41600 events.
[13:39:16.489] <TB0> INFO: 41600 events read in total (2912ms).
[13:39:16.490] <TB0> INFO: Test took 3769ms.
[13:39:16.779] <TB0> INFO: Expecting 41600 events.
[13:39:20.316] <TB0> INFO: 41600 events read in total (2946ms).
[13:39:20.316] <TB0> INFO: Test took 3802ms.
[13:39:20.605] <TB0> INFO: Expecting 41600 events.
[13:39:24.145] <TB0> INFO: 41600 events read in total (2948ms).
[13:39:24.146] <TB0> INFO: Test took 3805ms.
[13:39:24.435] <TB0> INFO: Expecting 41600 events.
[13:39:27.949] <TB0> INFO: 41600 events read in total (2922ms).
[13:39:27.950] <TB0> INFO: Test took 3780ms.
[13:39:28.240] <TB0> INFO: Expecting 41600 events.
[13:39:31.848] <TB0> INFO: 41600 events read in total (3016ms).
[13:39:31.849] <TB0> INFO: Test took 3875ms.
[13:39:32.139] <TB0> INFO: Expecting 41600 events.
[13:39:35.802] <TB0> INFO: 41600 events read in total (3071ms).
[13:39:35.803] <TB0> INFO: Test took 3929ms.
[13:39:36.100] <TB0> INFO: Expecting 41600 events.
[13:39:39.676] <TB0> INFO: 41600 events read in total (2984ms).
[13:39:39.677] <TB0> INFO: Test took 3847ms.
[13:39:40.027] <TB0> INFO: Expecting 41600 events.
[13:39:43.551] <TB0> INFO: 41600 events read in total (2931ms).
[13:39:43.551] <TB0> INFO: Test took 3850ms.
[13:39:43.840] <TB0> INFO: Expecting 41600 events.
[13:39:47.398] <TB0> INFO: 41600 events read in total (2966ms).
[13:39:47.398] <TB0> INFO: Test took 3823ms.
[13:39:47.688] <TB0> INFO: Expecting 41600 events.
[13:39:51.199] <TB0> INFO: 41600 events read in total (2920ms).
[13:39:51.200] <TB0> INFO: Test took 3778ms.
[13:39:51.490] <TB0> INFO: Expecting 41600 events.
[13:39:55.013] <TB0> INFO: 41600 events read in total (2931ms).
[13:39:55.014] <TB0> INFO: Test took 3789ms.
[13:39:55.331] <TB0> INFO: Expecting 41600 events.
[13:39:58.903] <TB0> INFO: 41600 events read in total (2981ms).
[13:39:58.904] <TB0> INFO: Test took 3866ms.
[13:39:59.196] <TB0> INFO: Expecting 41600 events.
[13:40:02.790] <TB0> INFO: 41600 events read in total (3003ms).
[13:40:02.791] <TB0> INFO: Test took 3861ms.
[13:40:03.085] <TB0> INFO: Expecting 2560 events.
[13:40:03.971] <TB0> INFO: 2560 events read in total (294ms).
[13:40:03.971] <TB0> INFO: Test took 1163ms.
[13:40:04.279] <TB0> INFO: Expecting 2560 events.
[13:40:05.172] <TB0> INFO: 2560 events read in total (301ms).
[13:40:05.172] <TB0> INFO: Test took 1200ms.
[13:40:05.480] <TB0> INFO: Expecting 2560 events.
[13:40:06.368] <TB0> INFO: 2560 events read in total (296ms).
[13:40:06.368] <TB0> INFO: Test took 1195ms.
[13:40:06.676] <TB0> INFO: Expecting 2560 events.
[13:40:07.561] <TB0> INFO: 2560 events read in total (293ms).
[13:40:07.562] <TB0> INFO: Test took 1193ms.
[13:40:07.868] <TB0> INFO: Expecting 2560 events.
[13:40:08.753] <TB0> INFO: 2560 events read in total (293ms).
[13:40:08.753] <TB0> INFO: Test took 1190ms.
[13:40:09.061] <TB0> INFO: Expecting 2560 events.
[13:40:09.947] <TB0> INFO: 2560 events read in total (292ms).
[13:40:09.947] <TB0> INFO: Test took 1193ms.
[13:40:10.254] <TB0> INFO: Expecting 2560 events.
[13:40:11.134] <TB0> INFO: 2560 events read in total (288ms).
[13:40:11.134] <TB0> INFO: Test took 1187ms.
[13:40:11.442] <TB0> INFO: Expecting 2560 events.
[13:40:12.322] <TB0> INFO: 2560 events read in total (288ms).
[13:40:12.322] <TB0> INFO: Test took 1188ms.
[13:40:12.629] <TB0> INFO: Expecting 2560 events.
[13:40:13.517] <TB0> INFO: 2560 events read in total (297ms).
[13:40:13.517] <TB0> INFO: Test took 1194ms.
[13:40:13.826] <TB0> INFO: Expecting 2560 events.
[13:40:14.707] <TB0> INFO: 2560 events read in total (289ms).
[13:40:14.708] <TB0> INFO: Test took 1191ms.
[13:40:15.015] <TB0> INFO: Expecting 2560 events.
[13:40:15.895] <TB0> INFO: 2560 events read in total (288ms).
[13:40:15.895] <TB0> INFO: Test took 1187ms.
[13:40:16.203] <TB0> INFO: Expecting 2560 events.
[13:40:17.094] <TB0> INFO: 2560 events read in total (299ms).
[13:40:17.095] <TB0> INFO: Test took 1200ms.
[13:40:17.402] <TB0> INFO: Expecting 2560 events.
[13:40:18.290] <TB0> INFO: 2560 events read in total (297ms).
[13:40:18.291] <TB0> INFO: Test took 1196ms.
[13:40:18.599] <TB0> INFO: Expecting 2560 events.
[13:40:19.492] <TB0> INFO: 2560 events read in total (301ms).
[13:40:19.493] <TB0> INFO: Test took 1202ms.
[13:40:19.799] <TB0> INFO: Expecting 2560 events.
[13:40:20.689] <TB0> INFO: 2560 events read in total (298ms).
[13:40:20.690] <TB0> INFO: Test took 1196ms.
[13:40:20.996] <TB0> INFO: Expecting 2560 events.
[13:40:21.881] <TB0> INFO: 2560 events read in total (293ms).
[13:40:21.882] <TB0> INFO: Test took 1192ms.
[13:40:21.885] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:40:22.189] <TB0> INFO: Expecting 655360 events.
[13:40:37.148] <TB0> INFO: 655360 events read in total (14367ms).
[13:40:37.163] <TB0> INFO: Expecting 655360 events.
[13:40:51.813] <TB0> INFO: 655360 events read in total (14247ms).
[13:40:51.828] <TB0> INFO: Expecting 655360 events.
[13:41:06.542] <TB0> INFO: 655360 events read in total (14312ms).
[13:41:06.563] <TB0> INFO: Expecting 655360 events.
[13:41:21.304] <TB0> INFO: 655360 events read in total (14338ms).
[13:41:21.335] <TB0> INFO: Expecting 655360 events.
[13:41:35.839] <TB0> INFO: 655360 events read in total (14101ms).
[13:41:35.879] <TB0> INFO: Expecting 655360 events.
[13:41:50.705] <TB0> INFO: 655360 events read in total (14423ms).
[13:41:50.754] <TB0> INFO: Expecting 655360 events.
[13:42:05.349] <TB0> INFO: 655360 events read in total (14192ms).
[13:42:05.387] <TB0> INFO: Expecting 655360 events.
[13:42:19.973] <TB0> INFO: 655360 events read in total (14183ms).
[13:42:20.171] <TB0> INFO: Expecting 655360 events.
[13:42:34.796] <TB0> INFO: 655360 events read in total (14222ms).
[13:42:34.847] <TB0> INFO: Expecting 655360 events.
[13:42:49.639] <TB0> INFO: 655360 events read in total (14389ms).
[13:42:49.702] <TB0> INFO: Expecting 655360 events.
[13:43:04.248] <TB0> INFO: 655360 events read in total (14143ms).
[13:43:04.331] <TB0> INFO: Expecting 655360 events.
[13:43:18.929] <TB0> INFO: 655360 events read in total (14194ms).
[13:43:19.031] <TB0> INFO: Expecting 655360 events.
[13:43:33.647] <TB0> INFO: 655360 events read in total (14212ms).
[13:43:33.804] <TB0> INFO: Expecting 655360 events.
[13:43:48.487] <TB0> INFO: 655360 events read in total (14280ms).
[13:43:48.679] <TB0> INFO: Expecting 655360 events.
[13:44:03.348] <TB0> INFO: 655360 events read in total (14266ms).
[13:44:03.449] <TB0> INFO: Expecting 655360 events.
[13:44:18.051] <TB0> INFO: 655360 events read in total (14199ms).
[13:44:18.289] <TB0> INFO: Test took 236404ms.
[13:44:18.395] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:18.647] <TB0> INFO: Expecting 655360 events.
[13:44:33.444] <TB0> INFO: 655360 events read in total (14205ms).
[13:44:33.456] <TB0> INFO: Expecting 655360 events.
[13:44:48.121] <TB0> INFO: 655360 events read in total (14261ms).
[13:44:48.138] <TB0> INFO: Expecting 655360 events.
[13:45:02.887] <TB0> INFO: 655360 events read in total (14346ms).
[13:45:02.908] <TB0> INFO: Expecting 655360 events.
[13:45:17.189] <TB0> INFO: 655360 events read in total (13878ms).
[13:45:17.221] <TB0> INFO: Expecting 655360 events.
[13:45:31.735] <TB0> INFO: 655360 events read in total (14111ms).
[13:45:31.772] <TB0> INFO: Expecting 655360 events.
[13:45:46.397] <TB0> INFO: 655360 events read in total (14222ms).
[13:45:46.444] <TB0> INFO: Expecting 655360 events.
[13:46:00.712] <TB0> INFO: 655360 events read in total (13865ms).
[13:46:00.748] <TB0> INFO: Expecting 655360 events.
[13:46:15.293] <TB0> INFO: 655360 events read in total (14141ms).
[13:46:15.479] <TB0> INFO: Expecting 655360 events.
[13:46:29.819] <TB0> INFO: 655360 events read in total (13937ms).
[13:46:29.868] <TB0> INFO: Expecting 655360 events.
[13:46:44.260] <TB0> INFO: 655360 events read in total (13988ms).
[13:46:44.507] <TB0> INFO: Expecting 655360 events.
[13:46:59.067] <TB0> INFO: 655360 events read in total (14157ms).
[13:46:59.125] <TB0> INFO: Expecting 655360 events.
[13:47:13.741] <TB0> INFO: 655360 events read in total (14213ms).
[13:47:13.815] <TB0> INFO: Expecting 655360 events.
[13:47:27.979] <TB0> INFO: 655360 events read in total (13761ms).
[13:47:28.237] <TB0> INFO: Expecting 655360 events.
[13:47:42.544] <TB0> INFO: 655360 events read in total (13904ms).
[13:47:42.630] <TB0> INFO: Expecting 655360 events.
[13:47:57.503] <TB0> INFO: 655360 events read in total (14470ms).
[13:47:57.580] <TB0> INFO: Expecting 655360 events.
[13:48:12.436] <TB0> INFO: 655360 events read in total (14453ms).
[13:48:12.514] <TB0> INFO: Test took 234119ms.
[13:48:12.743] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:48:12.751] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:48:12.759] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:48:12.768] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:48:12.777] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:48:12.786] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:48:12.795] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:48:12.804] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[13:48:12.813] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[13:48:12.822] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[13:48:12.831] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[13:48:12.840] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[13:48:12.849] <TB0> INFO: safety margin for low PH: adding 6, margin is now 26
[13:48:12.858] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:48:12.867] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[13:48:12.876] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[13:48:12.885] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[13:48:12.894] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[13:48:12.903] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:48:12.912] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[13:48:12.921] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[13:48:12.930] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:48:12.940] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:48:12.949] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:48:12.959] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:48:12.968] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:48:12.977] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:48:12.987] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[13:48:12.996] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[13:48:13.006] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[13:48:13.015] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[13:48:13.025] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[13:48:13.035] <TB0> INFO: safety margin for low PH: adding 6, margin is now 26
[13:48:13.044] <TB0> INFO: safety margin for low PH: adding 7, margin is now 27
[13:48:13.054] <TB0> INFO: safety margin for low PH: adding 8, margin is now 28
[13:48:13.064] <TB0> INFO: safety margin for low PH: adding 9, margin is now 29
[13:48:13.074] <TB0> INFO: safety margin for low PH: adding 10, margin is now 30
[13:48:13.083] <TB0> INFO: safety margin for low PH: adding 11, margin is now 31
[13:48:13.092] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[13:48:13.133] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C0.dat
[13:48:13.133] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C1.dat
[13:48:13.133] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C2.dat
[13:48:13.133] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C3.dat
[13:48:13.133] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C4.dat
[13:48:13.133] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C5.dat
[13:48:13.134] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C6.dat
[13:48:13.134] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C7.dat
[13:48:13.134] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C8.dat
[13:48:13.134] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C9.dat
[13:48:13.134] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C10.dat
[13:48:13.134] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C11.dat
[13:48:13.134] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C12.dat
[13:48:13.134] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C13.dat
[13:48:13.134] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C14.dat
[13:48:13.135] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//dacParameters35_C15.dat
[13:48:13.376] <TB0> INFO: Expecting 41600 events.
[13:48:16.543] <TB0> INFO: 41600 events read in total (2576ms).
[13:48:16.543] <TB0> INFO: Test took 3405ms.
[13:48:17.054] <TB0> INFO: Expecting 41600 events.
[13:48:20.136] <TB0> INFO: 41600 events read in total (2490ms).
[13:48:20.137] <TB0> INFO: Test took 3381ms.
[13:48:20.590] <TB0> INFO: Expecting 41600 events.
[13:48:23.787] <TB0> INFO: 41600 events read in total (2606ms).
[13:48:23.788] <TB0> INFO: Test took 3437ms.
[13:48:24.005] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:24.094] <TB0> INFO: Expecting 2560 events.
[13:48:24.984] <TB0> INFO: 2560 events read in total (298ms).
[13:48:24.984] <TB0> INFO: Test took 979ms.
[13:48:24.987] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:25.292] <TB0> INFO: Expecting 2560 events.
[13:48:26.177] <TB0> INFO: 2560 events read in total (293ms).
[13:48:26.177] <TB0> INFO: Test took 1190ms.
[13:48:26.182] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:26.485] <TB0> INFO: Expecting 2560 events.
[13:48:27.379] <TB0> INFO: 2560 events read in total (302ms).
[13:48:27.379] <TB0> INFO: Test took 1198ms.
[13:48:27.382] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:27.687] <TB0> INFO: Expecting 2560 events.
[13:48:28.576] <TB0> INFO: 2560 events read in total (297ms).
[13:48:28.576] <TB0> INFO: Test took 1194ms.
[13:48:28.579] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:28.884] <TB0> INFO: Expecting 2560 events.
[13:48:29.779] <TB0> INFO: 2560 events read in total (304ms).
[13:48:29.780] <TB0> INFO: Test took 1201ms.
[13:48:29.784] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:30.088] <TB0> INFO: Expecting 2560 events.
[13:48:30.980] <TB0> INFO: 2560 events read in total (300ms).
[13:48:30.981] <TB0> INFO: Test took 1197ms.
[13:48:30.983] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:31.289] <TB0> INFO: Expecting 2560 events.
[13:48:32.181] <TB0> INFO: 2560 events read in total (300ms).
[13:48:32.181] <TB0> INFO: Test took 1198ms.
[13:48:32.184] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:32.488] <TB0> INFO: Expecting 2560 events.
[13:48:33.380] <TB0> INFO: 2560 events read in total (300ms).
[13:48:33.380] <TB0> INFO: Test took 1196ms.
[13:48:33.382] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:33.689] <TB0> INFO: Expecting 2560 events.
[13:48:34.574] <TB0> INFO: 2560 events read in total (293ms).
[13:48:34.575] <TB0> INFO: Test took 1193ms.
[13:48:34.577] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:34.883] <TB0> INFO: Expecting 2560 events.
[13:48:35.763] <TB0> INFO: 2560 events read in total (289ms).
[13:48:35.764] <TB0> INFO: Test took 1187ms.
[13:48:35.768] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:36.071] <TB0> INFO: Expecting 2560 events.
[13:48:36.957] <TB0> INFO: 2560 events read in total (294ms).
[13:48:36.957] <TB0> INFO: Test took 1189ms.
[13:48:36.961] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:37.265] <TB0> INFO: Expecting 2560 events.
[13:48:38.155] <TB0> INFO: 2560 events read in total (298ms).
[13:48:38.155] <TB0> INFO: Test took 1194ms.
[13:48:38.159] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:38.464] <TB0> INFO: Expecting 2560 events.
[13:48:39.344] <TB0> INFO: 2560 events read in total (289ms).
[13:48:39.345] <TB0> INFO: Test took 1187ms.
[13:48:39.347] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:39.653] <TB0> INFO: Expecting 2560 events.
[13:48:40.538] <TB0> INFO: 2560 events read in total (293ms).
[13:48:40.539] <TB0> INFO: Test took 1192ms.
[13:48:40.541] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:40.847] <TB0> INFO: Expecting 2560 events.
[13:48:41.733] <TB0> INFO: 2560 events read in total (294ms).
[13:48:41.734] <TB0> INFO: Test took 1193ms.
[13:48:41.737] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:42.042] <TB0> INFO: Expecting 2560 events.
[13:48:42.918] <TB0> INFO: 2560 events read in total (284ms).
[13:48:42.919] <TB0> INFO: Test took 1182ms.
[13:48:42.921] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:43.228] <TB0> INFO: Expecting 2560 events.
[13:48:44.116] <TB0> INFO: 2560 events read in total (297ms).
[13:48:44.116] <TB0> INFO: Test took 1195ms.
[13:48:44.118] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:44.425] <TB0> INFO: Expecting 2560 events.
[13:48:45.308] <TB0> INFO: 2560 events read in total (292ms).
[13:48:45.308] <TB0> INFO: Test took 1190ms.
[13:48:45.311] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:45.617] <TB0> INFO: Expecting 2560 events.
[13:48:46.507] <TB0> INFO: 2560 events read in total (298ms).
[13:48:46.507] <TB0> INFO: Test took 1196ms.
[13:48:46.510] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:46.816] <TB0> INFO: Expecting 2560 events.
[13:48:47.698] <TB0> INFO: 2560 events read in total (291ms).
[13:48:47.698] <TB0> INFO: Test took 1188ms.
[13:48:47.701] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:48.007] <TB0> INFO: Expecting 2560 events.
[13:48:48.896] <TB0> INFO: 2560 events read in total (297ms).
[13:48:48.896] <TB0> INFO: Test took 1195ms.
[13:48:48.900] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:49.204] <TB0> INFO: Expecting 2560 events.
[13:48:50.090] <TB0> INFO: 2560 events read in total (295ms).
[13:48:50.090] <TB0> INFO: Test took 1190ms.
[13:48:50.094] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:50.399] <TB0> INFO: Expecting 2560 events.
[13:48:51.279] <TB0> INFO: 2560 events read in total (288ms).
[13:48:51.279] <TB0> INFO: Test took 1185ms.
[13:48:51.283] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:51.588] <TB0> INFO: Expecting 2560 events.
[13:48:52.473] <TB0> INFO: 2560 events read in total (294ms).
[13:48:52.473] <TB0> INFO: Test took 1190ms.
[13:48:52.476] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:52.782] <TB0> INFO: Expecting 2560 events.
[13:48:53.671] <TB0> INFO: 2560 events read in total (298ms).
[13:48:53.671] <TB0> INFO: Test took 1196ms.
[13:48:53.674] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:53.980] <TB0> INFO: Expecting 2560 events.
[13:48:54.868] <TB0> INFO: 2560 events read in total (297ms).
[13:48:54.869] <TB0> INFO: Test took 1195ms.
[13:48:54.872] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:55.178] <TB0> INFO: Expecting 2560 events.
[13:48:56.065] <TB0> INFO: 2560 events read in total (296ms).
[13:48:56.066] <TB0> INFO: Test took 1194ms.
[13:48:56.068] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:56.374] <TB0> INFO: Expecting 2560 events.
[13:48:57.268] <TB0> INFO: 2560 events read in total (303ms).
[13:48:57.269] <TB0> INFO: Test took 1201ms.
[13:48:57.271] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:57.577] <TB0> INFO: Expecting 2560 events.
[13:48:58.466] <TB0> INFO: 2560 events read in total (298ms).
[13:48:58.466] <TB0> INFO: Test took 1195ms.
[13:48:58.469] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:58.774] <TB0> INFO: Expecting 2560 events.
[13:48:59.667] <TB0> INFO: 2560 events read in total (301ms).
[13:48:59.667] <TB0> INFO: Test took 1199ms.
[13:48:59.670] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:48:59.975] <TB0> INFO: Expecting 2560 events.
[13:49:00.861] <TB0> INFO: 2560 events read in total (294ms).
[13:49:00.862] <TB0> INFO: Test took 1192ms.
[13:49:00.864] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:49:01.170] <TB0> INFO: Expecting 2560 events.
[13:49:02.055] <TB0> INFO: 2560 events read in total (294ms).
[13:49:02.056] <TB0> INFO: Test took 1192ms.
[13:49:02.525] <TB0> INFO: PixTestPhOptimization::doTest() done, duration: 659 seconds
[13:49:02.525] <TB0> INFO: PH scale (per ROC): 54 57 60 59 53 42 47 48 61 57 45 58 64 55 66 61
[13:49:02.525] <TB0> INFO: PH offset (per ROC): 119 116 129 112 126 95 111 112 114 132 113 131 123 123 112 121
[13:49:02.536] <TB0> INFO: Decoding statistics:
[13:49:02.536] <TB0> INFO: General information:
[13:49:02.536] <TB0> INFO: 16bit words read: 127882
[13:49:02.536] <TB0> INFO: valid events total: 20480
[13:49:02.536] <TB0> INFO: empty events: 17979
[13:49:02.536] <TB0> INFO: valid events with pixels: 2501
[13:49:02.536] <TB0> INFO: valid pixel hits: 2501
[13:49:02.536] <TB0> INFO: Event errors: 0
[13:49:02.536] <TB0> INFO: start marker: 0
[13:49:02.536] <TB0> INFO: stop marker: 0
[13:49:02.536] <TB0> INFO: overflow: 0
[13:49:02.537] <TB0> INFO: invalid 5bit words: 0
[13:49:02.537] <TB0> INFO: invalid XOR eye diagram: 0
[13:49:02.537] <TB0> INFO: frame (failed synchr.): 0
[13:49:02.537] <TB0> INFO: idle data (no TBM trl): 0
[13:49:02.537] <TB0> INFO: no data (only TBM hdr): 0
[13:49:02.537] <TB0> INFO: TBM errors: 0
[13:49:02.537] <TB0> INFO: flawed TBM headers: 0
[13:49:02.537] <TB0> INFO: flawed TBM trailers: 0
[13:49:02.537] <TB0> INFO: event ID mismatches: 0
[13:49:02.537] <TB0> INFO: ROC errors: 0
[13:49:02.537] <TB0> INFO: missing ROC header(s): 0
[13:49:02.537] <TB0> INFO: misplaced readback start: 0
[13:49:02.537] <TB0> INFO: Pixel decoding errors: 0
[13:49:02.537] <TB0> INFO: pixel data incomplete: 0
[13:49:02.537] <TB0> INFO: pixel address: 0
[13:49:02.537] <TB0> INFO: pulse height fill bit: 0
[13:49:02.537] <TB0> INFO: buffer corruption: 0
[13:49:02.767] <TB0> INFO: ######################################################################
[13:49:02.767] <TB0> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:49:02.767] <TB0> INFO: ######################################################################
[13:49:02.783] <TB0> INFO: scanning low vcal = 10
[13:49:03.019] <TB0> INFO: Expecting 41600 events.
[13:49:06.637] <TB0> INFO: 41600 events read in total (3026ms).
[13:49:06.638] <TB0> INFO: Test took 3855ms.
[13:49:06.640] <TB0> INFO: scanning low vcal = 20
[13:49:06.931] <TB0> INFO: Expecting 41600 events.
[13:49:10.556] <TB0> INFO: 41600 events read in total (3033ms).
[13:49:10.557] <TB0> INFO: Test took 3917ms.
[13:49:10.559] <TB0> INFO: scanning low vcal = 30
[13:49:10.853] <TB0> INFO: Expecting 41600 events.
[13:49:14.521] <TB0> INFO: 41600 events read in total (3077ms).
[13:49:14.522] <TB0> INFO: Test took 3963ms.
[13:49:14.524] <TB0> INFO: scanning low vcal = 40
[13:49:14.801] <TB0> INFO: Expecting 41600 events.
[13:49:18.758] <TB0> INFO: 41600 events read in total (3365ms).
[13:49:18.759] <TB0> INFO: Test took 4235ms.
[13:49:18.762] <TB0> INFO: scanning low vcal = 50
[13:49:19.039] <TB0> INFO: Expecting 41600 events.
[13:49:23.083] <TB0> INFO: 41600 events read in total (3452ms).
[13:49:23.084] <TB0> INFO: Test took 4322ms.
[13:49:23.088] <TB0> INFO: scanning low vcal = 60
[13:49:23.364] <TB0> INFO: Expecting 41600 events.
[13:49:27.420] <TB0> INFO: 41600 events read in total (3464ms).
[13:49:27.421] <TB0> INFO: Test took 4333ms.
[13:49:27.424] <TB0> INFO: scanning low vcal = 70
[13:49:27.701] <TB0> INFO: Expecting 41600 events.
[13:49:31.709] <TB0> INFO: 41600 events read in total (3416ms).
[13:49:31.710] <TB0> INFO: Test took 4285ms.
[13:49:31.713] <TB0> INFO: scanning low vcal = 80
[13:49:32.021] <TB0> INFO: Expecting 41600 events.
[13:49:36.104] <TB0> INFO: 41600 events read in total (3491ms).
[13:49:36.105] <TB0> INFO: Test took 4392ms.
[13:49:36.108] <TB0> INFO: scanning low vcal = 90
[13:49:36.385] <TB0> INFO: Expecting 41600 events.
[13:49:40.397] <TB0> INFO: 41600 events read in total (3420ms).
[13:49:40.398] <TB0> INFO: Test took 4290ms.
[13:49:40.402] <TB0> INFO: scanning low vcal = 100
[13:49:40.678] <TB0> INFO: Expecting 41600 events.
[13:49:44.693] <TB0> INFO: 41600 events read in total (3423ms).
[13:49:44.694] <TB0> INFO: Test took 4292ms.
[13:49:44.697] <TB0> INFO: scanning low vcal = 110
[13:49:44.974] <TB0> INFO: Expecting 41600 events.
[13:49:48.936] <TB0> INFO: 41600 events read in total (3370ms).
[13:49:48.937] <TB0> INFO: Test took 4240ms.
[13:49:48.941] <TB0> INFO: scanning low vcal = 120
[13:49:49.217] <TB0> INFO: Expecting 41600 events.
[13:49:55.034] <TB0> INFO: 41600 events read in total (5225ms).
[13:49:55.035] <TB0> INFO: Test took 6094ms.
[13:49:55.039] <TB0> INFO: scanning low vcal = 130
[13:49:55.393] <TB0> INFO: Expecting 41600 events.
[13:50:01.931] <TB0> INFO: 41600 events read in total (5904ms).
[13:50:01.933] <TB0> INFO: Test took 6894ms.
[13:50:01.936] <TB0> INFO: scanning low vcal = 140
[13:50:02.427] <TB0> INFO: Expecting 41600 events.
[13:50:22.229] <TB0> INFO: 41600 events read in total (19130ms).
[13:50:22.230] <TB0> INFO: Test took 20293ms.
[13:50:22.233] <TB0> INFO: scanning low vcal = 150
[13:50:22.893] <TB0> INFO: Expecting 41600 events.
[13:50:26.988] <TB0> INFO: 41600 events read in total (3452ms).
[13:50:26.000] <TB0> INFO: Test took 4767ms.
[13:50:27.091] <TB0> INFO: scanning low vcal = 160
[13:50:27.926] <TB0> INFO: Expecting 41600 events.
[13:50:49.236] <TB0> INFO: 41600 events read in total (20665ms).
[13:50:49.238] <TB0> INFO: Test took 22139ms.
[13:50:49.241] <TB0> INFO: scanning low vcal = 170
[13:50:49.565] <TB0> INFO: Expecting 41600 events.
[13:50:53.544] <TB0> INFO: 41600 events read in total (3387ms).
[13:50:53.545] <TB0> INFO: Test took 4304ms.
[13:50:53.550] <TB0> INFO: scanning low vcal = 180
[13:50:53.825] <TB0> INFO: Expecting 41600 events.
[13:50:57.854] <TB0> INFO: 41600 events read in total (3438ms).
[13:50:57.854] <TB0> INFO: Test took 4304ms.
[13:50:57.857] <TB0> INFO: scanning low vcal = 190
[13:50:58.134] <TB0> INFO: Expecting 41600 events.
[13:51:02.108] <TB0> INFO: 41600 events read in total (3382ms).
[13:51:02.110] <TB0> INFO: Test took 4252ms.
[13:51:02.113] <TB0> INFO: scanning low vcal = 200
[13:51:02.389] <TB0> INFO: Expecting 41600 events.
[13:51:06.424] <TB0> INFO: 41600 events read in total (3443ms).
[13:51:06.425] <TB0> INFO: Test took 4311ms.
[13:51:06.428] <TB0> INFO: scanning low vcal = 210
[13:51:06.721] <TB0> INFO: Expecting 41600 events.
[13:51:10.760] <TB0> INFO: 41600 events read in total (3448ms).
[13:51:10.761] <TB0> INFO: Test took 4333ms.
[13:51:10.764] <TB0> INFO: scanning low vcal = 220
[13:51:11.041] <TB0> INFO: Expecting 41600 events.
[13:51:15.404] <TB0> INFO: 41600 events read in total (3772ms).
[13:51:15.416] <TB0> INFO: Test took 4652ms.
[13:51:15.551] <TB0> INFO: scanning low vcal = 230
[13:51:15.916] <TB0> INFO: Expecting 41600 events.
[13:51:20.234] <TB0> INFO: 41600 events read in total (3727ms).
[13:51:20.244] <TB0> INFO: Test took 4689ms.
[13:51:20.383] <TB0> INFO: scanning low vcal = 240
[13:51:21.283] <TB0> INFO: Expecting 41600 events.
[13:51:26.663] <TB0> INFO: 41600 events read in total (4728ms).
[13:51:26.676] <TB0> INFO: Test took 6281ms.
[13:51:26.687] <TB0> INFO: scanning low vcal = 250
[13:51:27.050] <TB0> INFO: Expecting 41600 events.
[13:51:35.059] <TB0> INFO: 41600 events read in total (7409ms).
[13:51:35.070] <TB0> INFO: Test took 8383ms.
[13:51:35.204] <TB0> INFO: scanning high vcal = 30 (= 210 in low range)
[13:51:35.599] <TB0> INFO: Expecting 41600 events.
[13:51:53.788] <TB0> INFO: 41600 events read in total (17581ms).
[13:51:53.789] <TB0> INFO: Test took 18584ms.
[13:51:53.797] <TB0> INFO: scanning high vcal = 50 (= 350 in low range)
[13:51:54.195] <TB0> INFO: Expecting 41600 events.
[13:52:12.185] <TB0> INFO: 41600 events read in total (17334ms).
[13:52:12.186] <TB0> INFO: Test took 18389ms.
[13:52:12.190] <TB0> INFO: scanning high vcal = 70 (= 490 in low range)
[13:52:12.663] <TB0> INFO: Expecting 41600 events.
[13:52:19.320] <TB0> INFO: 41600 events read in total (6065ms).
[13:52:19.322] <TB0> INFO: Test took 7132ms.
[13:52:19.329] <TB0> INFO: scanning high vcal = 90 (= 630 in low range)
[13:52:19.648] <TB0> INFO: Expecting 41600 events.
[13:52:23.514] <TB0> INFO: 41600 events read in total (3274ms).
[13:52:23.515] <TB0> INFO: Test took 4186ms.
[13:52:23.518] <TB0> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:52:23.818] <TB0> INFO: Expecting 41600 events.
[13:52:27.878] <TB0> INFO: 41600 events read in total (3468ms).
[13:52:27.880] <TB0> INFO: Test took 4362ms.
[13:52:28.431] <TB0> INFO: PixTestGainPedestal::measure() done
[13:53:12.428] <TB0> INFO: PixTestGainPedestal::fit() done
[13:53:12.435] <TB0> INFO: non-linearity mean: 0.978 0.975 0.982 0.961 0.982 0.948 0.947 0.963 0.984 0.983 0.899 0.982 0.984 0.979 0.968 0.984
[13:53:12.435] <TB0> INFO: non-linearity RMS: 0.004 0.006 0.003 0.036 0.004 0.163 0.064 0.042 0.002 0.003 0.115 0.005 0.003 0.006 0.023 0.003
[13:53:12.435] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[13:53:12.465] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[13:53:12.501] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[13:53:12.533] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[13:53:12.579] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[13:53:12.606] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[13:53:12.649] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[13:53:12.684] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[13:53:12.723] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[13:53:12.754] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[13:53:12.789] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[13:53:12.823] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[13:53:12.859] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[13:53:12.894] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[13:53:12.919] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[13:53:12.952] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1052_FullQualification_2016-10-24_11h34m_1477301645//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[13:53:12.989] <TB0> INFO: PixTestGainPedestal::fullTest() done, duration: 250 seconds
[13:53:12.989] <TB0> INFO: Decoding statistics:
[13:53:12.989] <TB0> INFO: General information:
[13:53:12.989] <TB0> INFO: 16bit words read: 3327700
[13:53:12.989] <TB0> INFO: valid events total: 332800
[13:53:12.989] <TB0> INFO: empty events: 0
[13:53:12.989] <TB0> INFO: valid events with pixels: 332800
[13:53:12.989] <TB0> INFO: valid pixel hits: 665450
[13:53:12.989] <TB0> INFO: Event errors: 0
[13:53:12.989] <TB0> INFO: start marker: 0
[13:53:12.989] <TB0> INFO: stop marker: 0
[13:53:12.989] <TB0> INFO: overflow: 0
[13:53:12.989] <TB0> INFO: invalid 5bit words: 0
[13:53:12.989] <TB0> INFO: invalid XOR eye diagram: 0
[13:53:12.989] <TB0> INFO: frame (failed synchr.): 0
[13:53:12.989] <TB0> INFO: idle data (no TBM trl): 0
[13:53:12.989] <TB0> INFO: no data (only TBM hdr): 0
[13:53:12.989] <TB0> INFO: TBM errors: 0
[13:53:12.989] <TB0> INFO: flawed TBM headers: 0
[13:53:12.989] <TB0> INFO: flawed TBM trailers: 0
[13:53:12.989] <TB0> INFO: event ID mismatches: 0
[13:53:12.989] <TB0> INFO: ROC errors: 0
[13:53:12.989] <TB0> INFO: missing ROC header(s): 0
[13:53:12.989] <TB0> INFO: misplaced readback start: 0
[13:53:12.989] <TB0> INFO: Pixel decoding errors: 0
[13:53:12.989] <TB0> INFO: pixel data incomplete: 0
[13:53:12.989] <TB0> INFO: pixel address: 0
[13:53:12.989] <TB0> INFO: pulse height fill bit: 0
[13:53:12.989] <TB0> INFO: buffer corruption: 0
[13:53:13.017] <TB0> INFO: Decoding statistics:
[13:53:13.023] <TB0> INFO: General information:
[13:53:13.023] <TB0> INFO: 16bit words read: 3457118
[13:53:13.023] <TB0> INFO: valid events total: 353536
[13:53:13.023] <TB0> INFO: empty events: 18235
[13:53:13.023] <TB0> INFO: valid events with pixels: 335301
[13:53:13.023] <TB0> INFO: valid pixel hits: 667951
[13:53:13.023] <TB0> INFO: Event errors: 0
[13:53:13.023] <TB0> INFO: start marker: 0
[13:53:13.023] <TB0> INFO: stop marker: 0
[13:53:13.023] <TB0> INFO: overflow: 0
[13:53:13.023] <TB0> INFO: invalid 5bit words: 0
[13:53:13.023] <TB0> INFO: invalid XOR eye diagram: 0
[13:53:13.023] <TB0> INFO: frame (failed synchr.): 0
[13:53:13.023] <TB0> INFO: idle data (no TBM trl): 0
[13:53:13.023] <TB0> INFO: no data (only TBM hdr): 0
[13:53:13.023] <TB0> INFO: TBM errors: 0
[13:53:13.023] <TB0> INFO: flawed TBM headers: 0
[13:53:13.023] <TB0> INFO: flawed TBM trailers: 0
[13:53:13.023] <TB0> INFO: event ID mismatches: 0
[13:53:13.023] <TB0> INFO: ROC errors: 0
[13:53:13.023] <TB0> INFO: missing ROC header(s): 0
[13:53:13.023] <TB0> INFO: misplaced readback start: 0
[13:53:13.023] <TB0> INFO: Pixel decoding errors: 0
[13:53:13.023] <TB0> INFO: pixel data incomplete: 0
[13:53:13.023] <TB0> INFO: pixel address: 0
[13:53:13.023] <TB0> INFO: pulse height fill bit: 0
[13:53:13.023] <TB0> INFO: buffer corruption: 0
[13:53:13.023] <TB0> INFO: enter test to run
[13:53:13.023] <TB0> INFO: test: exit no parameter change
[13:53:13.283] <TB0> QUIET: Connection to board 71 closed.
[13:53:13.295] <TB0> INFO: pXar: this is the end, my friend