[15:45:48.453] <TB3> INFO: *** Welcome to pxar ***
[15:45:48.453] <TB3> INFO: *** Today: 2016/10/23
[15:45:48.460] <TB3> INFO: *** Version: c8ba-dirty
[15:45:48.460] <TB3> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C15.dat
[15:45:48.461] <TB3> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//tbmParameters_C1b.dat
[15:45:48.461] <TB3> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//defaultMaskFile.dat
[15:45:48.461] <TB3> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters_C15.dat
[15:45:48.523] <TB3> INFO: clk: 4
[15:45:48.523] <TB3> INFO: ctr: 4
[15:45:48.523] <TB3> INFO: sda: 19
[15:45:48.523] <TB3> INFO: tin: 9
[15:45:48.523] <TB3> INFO: level: 15
[15:45:48.523] <TB3> INFO: triggerdelay: 0
[15:45:48.523] <TB3> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[15:45:48.523] <TB3> INFO: Log level: INFO
[15:45:48.532] <TB3> INFO: Found DTB DTB_WWVASW
[15:45:48.547] <TB3> QUIET: Connection to board DTB_WWVASW opened.
[15:45:48.549] <TB3> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 126
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWVASW
MAC address: 40D85511807E
Hostname: pixelDTB126
Comment:
------------------------------------------------------
[15:45:48.552] <TB3> INFO: RPC call hashes of host and DTB match: 486171790
[15:45:50.054] <TB3> INFO: DUT info:
[15:45:50.054] <TB3> INFO: The DUT currently contains the following objects:
[15:45:50.054] <TB3> INFO: 4 TBM Cores tbm10c (4 ON)
[15:45:50.054] <TB3> INFO: TBM Core alpha (0): 7 registers set
[15:45:50.054] <TB3> INFO: TBM Core beta (1): 7 registers set
[15:45:50.054] <TB3> INFO: TBM Core alpha (2): 7 registers set
[15:45:50.054] <TB3> INFO: TBM Core beta (3): 7 registers set
[15:45:50.054] <TB3> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[15:45:50.054] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:50.054] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:50.054] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:50.054] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:50.054] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:50.054] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:50.054] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:50.054] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:50.054] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:50.055] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:50.055] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:50.055] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:50.055] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:50.055] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:50.055] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:50.055] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:50.456] <TB3> INFO: enter 'restricted' command line mode
[15:45:50.457] <TB3> INFO: enter test to run
[15:45:50.457] <TB3> INFO: test: pretest no parameter change
[15:45:50.457] <TB3> INFO: running: pretest
[15:45:50.465] <TB3> INFO: ######################################################################
[15:45:50.465] <TB3> INFO: PixTestPretest::doTest()
[15:45:50.465] <TB3> INFO: ######################################################################
[15:45:50.466] <TB3> INFO: ----------------------------------------------------------------------
[15:45:50.466] <TB3> INFO: PixTestPretest::programROC()
[15:45:50.466] <TB3> INFO: ----------------------------------------------------------------------
[15:46:08.481] <TB3> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[15:46:08.481] <TB3> INFO: IA differences per ROC: 19.3 17.7 17.7 15.3 17.7 20.9 20.1 20.1 19.3 20.9 20.1 17.7 20.9 20.1 18.5 18.5
[15:46:08.547] <TB3> INFO: ----------------------------------------------------------------------
[15:46:08.547] <TB3> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[15:46:08.547] <TB3> INFO: ----------------------------------------------------------------------
[15:46:29.845] <TB3> INFO: PixTestPretest::setVana() done, Module Ia 379.4 mA = 23.7125 mA/ROC
[15:46:29.845] <TB3> INFO: i(loss) [mA/ROC]: 20.1 19.3 19.3 19.3 20.1 20.1 20.1 19.3 20.9 19.3 20.1 20.1 19.3 19.3 20.1 19.3
[15:46:29.878] <TB3> INFO: ----------------------------------------------------------------------
[15:46:29.878] <TB3> INFO: PixTestPretest::findTiming()
[15:46:29.878] <TB3> INFO: ----------------------------------------------------------------------
[15:46:29.879] <TB3> INFO: PixTestCmd::init()

[15:47:02.038] <TB3> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[15:47:02.038] <TB3> INFO: (success/tries = 100/100), width = 3
[15:47:03.547] <TB3> INFO: ----------------------------------------------------------------------
[15:47:03.547] <TB3> INFO: PixTestPretest::findWorkingPixel()
[15:47:03.547] <TB3> INFO: ----------------------------------------------------------------------
[15:47:03.640] <TB3> INFO: Expecting 231680 events.
[15:47:13.557] <TB3> INFO: 231680 events read in total (9325ms).
[15:47:13.566] <TB3> INFO: Test took 10016ms.
[15:47:13.814] <TB3> INFO: Found working pixel in all ROCs: col/row = 12/22
[15:47:13.851] <TB3> INFO: ----------------------------------------------------------------------
[15:47:13.851] <TB3> INFO: PixTestPretest::setVthrCompCalDel()
[15:47:13.851] <TB3> INFO: ----------------------------------------------------------------------
[15:47:13.946] <TB3> INFO: Expecting 231680 events.
[15:47:24.020] <TB3> INFO: 231680 events read in total (9482ms).
[15:47:24.027] <TB3> INFO: Test took 10170ms.
[15:47:24.291] <TB3> INFO: PixTestPretest::setVthrCompCalDel() done
[15:47:24.291] <TB3> INFO: CalDel: 90 94 103 112 95 116 106 84 85 98 90 114 105 112 111 93
[15:47:24.291] <TB3> INFO: VthrComp: 52 51 53 51 51 51 51 51 51 51 52 51 51 51 51 51
[15:47:24.297] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C0.dat
[15:47:24.297] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C1.dat
[15:47:24.298] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C2.dat
[15:47:24.298] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C3.dat
[15:47:24.298] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C4.dat
[15:47:24.298] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C5.dat
[15:47:24.298] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C6.dat
[15:47:24.298] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C7.dat
[15:47:24.298] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C8.dat
[15:47:24.299] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C9.dat
[15:47:24.299] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C10.dat
[15:47:24.299] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C11.dat
[15:47:24.299] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C12.dat
[15:47:24.299] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C13.dat
[15:47:24.299] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C14.dat
[15:47:24.299] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C15.dat
[15:47:24.299] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//tbmParameters_C0a.dat
[15:47:24.300] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//tbmParameters_C0b.dat
[15:47:24.300] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//tbmParameters_C1a.dat
[15:47:24.300] <TB3> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//tbmParameters_C1b.dat
[15:47:24.300] <TB3> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[15:47:24.353] <TB3> INFO: enter test to run
[15:47:24.353] <TB3> INFO: test: FullTest no parameter change
[15:47:24.353] <TB3> INFO: running: fulltest
[15:47:24.353] <TB3> INFO: ######################################################################
[15:47:24.353] <TB3> INFO: PixTestFullTest::doTest()
[15:47:24.353] <TB3> INFO: ######################################################################
[15:47:24.354] <TB3> INFO: ######################################################################
[15:47:24.354] <TB3> INFO: PixTestAlive::doTest()
[15:47:24.354] <TB3> INFO: ######################################################################
[15:47:24.355] <TB3> INFO: ----------------------------------------------------------------------
[15:47:24.355] <TB3> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:47:24.355] <TB3> INFO: ----------------------------------------------------------------------
[15:47:24.594] <TB3> INFO: Expecting 41600 events.
[15:47:28.264] <TB3> INFO: 41600 events read in total (3078ms).
[15:47:28.265] <TB3> INFO: Test took 3908ms.
[15:47:28.501] <TB3> INFO: PixTestAlive::aliveTest() done
[15:47:28.501] <TB3> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
[15:47:28.503] <TB3> INFO: ----------------------------------------------------------------------
[15:47:28.503] <TB3> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:47:28.503] <TB3> INFO: ----------------------------------------------------------------------
[15:47:28.744] <TB3> INFO: Expecting 41600 events.
[15:47:31.772] <TB3> INFO: 41600 events read in total (2436ms).
[15:47:31.772] <TB3> INFO: Test took 3267ms.
[15:47:31.773] <TB3> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[15:47:32.011] <TB3> INFO: PixTestAlive::maskTest() done
[15:47:32.012] <TB3> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:47:32.013] <TB3> INFO: ----------------------------------------------------------------------
[15:47:32.013] <TB3> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:47:32.013] <TB3> INFO: ----------------------------------------------------------------------
[15:47:32.259] <TB3> INFO: Expecting 41600 events.
[15:47:35.812] <TB3> INFO: 41600 events read in total (2961ms).
[15:47:35.813] <TB3> INFO: Test took 3797ms.
[15:47:36.047] <TB3> INFO: PixTestAlive::addressDecodingTest() done
[15:47:36.047] <TB3> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:47:36.047] <TB3> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[15:47:36.047] <TB3> INFO: Decoding statistics:
[15:47:36.047] <TB3> INFO: General information:
[15:47:36.047] <TB3> INFO: 16bit words read: 0
[15:47:36.047] <TB3> INFO: valid events total: 0
[15:47:36.047] <TB3> INFO: empty events: 0
[15:47:36.047] <TB3> INFO: valid events with pixels: 0
[15:47:36.047] <TB3> INFO: valid pixel hits: 0
[15:47:36.047] <TB3> INFO: Event errors: 0
[15:47:36.047] <TB3> INFO: start marker: 0
[15:47:36.047] <TB3> INFO: stop marker: 0
[15:47:36.047] <TB3> INFO: overflow: 0
[15:47:36.047] <TB3> INFO: invalid 5bit words: 0
[15:47:36.047] <TB3> INFO: invalid XOR eye diagram: 0
[15:47:36.047] <TB3> INFO: frame (failed synchr.): 0
[15:47:36.047] <TB3> INFO: idle data (no TBM trl): 0
[15:47:36.048] <TB3> INFO: no data (only TBM hdr): 0
[15:47:36.048] <TB3> INFO: TBM errors: 0
[15:47:36.048] <TB3> INFO: flawed TBM headers: 0
[15:47:36.048] <TB3> INFO: flawed TBM trailers: 0
[15:47:36.048] <TB3> INFO: event ID mismatches: 0
[15:47:36.048] <TB3> INFO: ROC errors: 0
[15:47:36.048] <TB3> INFO: missing ROC header(s): 0
[15:47:36.048] <TB3> INFO: misplaced readback start: 0
[15:47:36.048] <TB3> INFO: Pixel decoding errors: 0
[15:47:36.048] <TB3> INFO: pixel data incomplete: 0
[15:47:36.048] <TB3> INFO: pixel address: 0
[15:47:36.048] <TB3> INFO: pulse height fill bit: 0
[15:47:36.048] <TB3> INFO: buffer corruption: 0
[15:47:36.056] <TB3> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C15.dat
[15:47:36.056] <TB3> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[15:47:36.056] <TB3> INFO: ######################################################################
[15:47:36.056] <TB3> INFO: PixTestReadback::doTest()
[15:47:36.056] <TB3> INFO: ######################################################################
[15:47:36.056] <TB3> INFO: ----------------------------------------------------------------------
[15:47:36.056] <TB3> INFO: PixTestReadback::CalibrateVd()
[15:47:36.056] <TB3> INFO: ----------------------------------------------------------------------
[15:47:46.049] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C0.dat
[15:47:46.049] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C1.dat
[15:47:46.049] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C2.dat
[15:47:46.049] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C3.dat
[15:47:46.049] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C4.dat
[15:47:46.049] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C5.dat
[15:47:46.049] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C6.dat
[15:47:46.050] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C7.dat
[15:47:46.050] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C8.dat
[15:47:46.050] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C9.dat
[15:47:46.050] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C10.dat
[15:47:46.050] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C11.dat
[15:47:46.050] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C12.dat
[15:47:46.050] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C13.dat
[15:47:46.050] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C14.dat
[15:47:46.050] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C15.dat
[15:47:46.081] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[15:47:46.081] <TB3> INFO: ----------------------------------------------------------------------
[15:47:46.081] <TB3> INFO: PixTestReadback::CalibrateVa()
[15:47:46.081] <TB3> INFO: ----------------------------------------------------------------------
[15:47:56.020] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C0.dat
[15:47:56.020] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C1.dat
[15:47:56.020] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C2.dat
[15:47:56.020] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C3.dat
[15:47:56.021] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C4.dat
[15:47:56.021] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C5.dat
[15:47:56.021] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C6.dat
[15:47:56.021] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C7.dat
[15:47:56.021] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C8.dat
[15:47:56.021] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C9.dat
[15:47:56.021] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C10.dat
[15:47:56.021] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C11.dat
[15:47:56.021] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C12.dat
[15:47:56.021] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C13.dat
[15:47:56.021] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C14.dat
[15:47:56.022] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C15.dat
[15:47:56.051] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[15:47:56.051] <TB3> INFO: ----------------------------------------------------------------------
[15:47:56.051] <TB3> INFO: PixTestReadback::readbackVbg()
[15:47:56.051] <TB3> INFO: ----------------------------------------------------------------------
[15:48:03.727] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[15:48:03.727] <TB3> INFO: ----------------------------------------------------------------------
[15:48:03.727] <TB3> INFO: PixTestReadback::getCalibratedVbg()
[15:48:03.727] <TB3> INFO: ----------------------------------------------------------------------
[15:48:03.727] <TB3> INFO: Vbg will be calibrated using Vd calibration
[15:48:03.727] <TB3> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 156.6calibrated Vbg = 1.19386 :::*/*/*/*/
[15:48:03.727] <TB3> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 154.2calibrated Vbg = 1.19503 :::*/*/*/*/
[15:48:03.727] <TB3> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 155.2calibrated Vbg = 1.19339 :::*/*/*/*/
[15:48:03.727] <TB3> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 157.1calibrated Vbg = 1.19355 :::*/*/*/*/
[15:48:03.727] <TB3> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 152.9calibrated Vbg = 1.19198 :::*/*/*/*/
[15:48:03.727] <TB3> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 151calibrated Vbg = 1.19867 :::*/*/*/*/
[15:48:03.727] <TB3> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 157.4calibrated Vbg = 1.19688 :::*/*/*/*/
[15:48:03.727] <TB3> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 158calibrated Vbg = 1.19521 :::*/*/*/*/
[15:48:03.727] <TB3> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 153.8calibrated Vbg = 1.19312 :::*/*/*/*/
[15:48:03.727] <TB3> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 159.6calibrated Vbg = 1.18626 :::*/*/*/*/
[15:48:03.727] <TB3> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 162.2calibrated Vbg = 1.18643 :::*/*/*/*/
[15:48:03.727] <TB3> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 150.3calibrated Vbg = 1.17907 :::*/*/*/*/
[15:48:03.727] <TB3> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 154.2calibrated Vbg = 1.19215 :::*/*/*/*/
[15:48:03.728] <TB3> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 154.9calibrated Vbg = 1.19078 :::*/*/*/*/
[15:48:03.728] <TB3> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 158.9calibrated Vbg = 1.19218 :::*/*/*/*/
[15:48:03.728] <TB3> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 153.4calibrated Vbg = 1.19467 :::*/*/*/*/
[15:48:03.731] <TB3> INFO: ----------------------------------------------------------------------
[15:48:03.731] <TB3> INFO: PixTestReadback::CalibrateIa()
[15:48:03.731] <TB3> INFO: ----------------------------------------------------------------------
[15:50:44.524] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C0.dat
[15:50:44.524] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C1.dat
[15:50:44.524] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C2.dat
[15:50:44.524] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C3.dat
[15:50:44.524] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C4.dat
[15:50:44.524] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C5.dat
[15:50:44.524] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C6.dat
[15:50:44.524] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C7.dat
[15:50:44.525] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C8.dat
[15:50:44.525] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C9.dat
[15:50:44.525] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C10.dat
[15:50:44.525] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C11.dat
[15:50:44.525] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C12.dat
[15:50:44.525] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C13.dat
[15:50:44.525] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C14.dat
[15:50:44.525] <TB3> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C15.dat
[15:50:44.556] <TB3> INFO: PixTestPattern:: pg_setup set to default.
[15:50:44.557] <TB3> INFO: PixTestReadback::doTest() done
[15:50:44.557] <TB3> INFO: Decoding statistics:
[15:50:44.557] <TB3> INFO: General information:
[15:50:44.557] <TB3> INFO: 16bit words read: 1536
[15:50:44.557] <TB3> INFO: valid events total: 256
[15:50:44.557] <TB3> INFO: empty events: 256
[15:50:44.557] <TB3> INFO: valid events with pixels: 0
[15:50:44.557] <TB3> INFO: valid pixel hits: 0
[15:50:44.557] <TB3> INFO: Event errors: 0
[15:50:44.557] <TB3> INFO: start marker: 0
[15:50:44.557] <TB3> INFO: stop marker: 0
[15:50:44.558] <TB3> INFO: overflow: 0
[15:50:44.558] <TB3> INFO: invalid 5bit words: 0
[15:50:44.558] <TB3> INFO: invalid XOR eye diagram: 0
[15:50:44.558] <TB3> INFO: frame (failed synchr.): 0
[15:50:44.558] <TB3> INFO: idle data (no TBM trl): 0
[15:50:44.558] <TB3> INFO: no data (only TBM hdr): 0
[15:50:44.558] <TB3> INFO: TBM errors: 0
[15:50:44.558] <TB3> INFO: flawed TBM headers: 0
[15:50:44.558] <TB3> INFO: flawed TBM trailers: 0
[15:50:44.558] <TB3> INFO: event ID mismatches: 0
[15:50:44.558] <TB3> INFO: ROC errors: 0
[15:50:44.558] <TB3> INFO: missing ROC header(s): 0
[15:50:44.558] <TB3> INFO: misplaced readback start: 0
[15:50:44.558] <TB3> INFO: Pixel decoding errors: 0
[15:50:44.558] <TB3> INFO: pixel data incomplete: 0
[15:50:44.558] <TB3> INFO: pixel address: 0
[15:50:44.558] <TB3> INFO: pulse height fill bit: 0
[15:50:44.558] <TB3> INFO: buffer corruption: 0
[15:50:44.607] <TB3> INFO: ######################################################################
[15:50:44.607] <TB3> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[15:50:44.607] <TB3> INFO: ######################################################################
[15:50:44.610] <TB3> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[15:50:44.624] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[15:50:44.624] <TB3> INFO: run 1 of 1
[15:50:44.865] <TB3> INFO: Expecting 3120000 events.
[15:51:16.134] <TB3> INFO: 658110 events read in total (30676ms).





















[15:51:46.303] <TB3> INFO: 1308480 events read in total (60845ms).











[15:52:16.806] <TB3> INFO: 1957320 events read in total (91348ms).
[15:52:46.704] <TB3> INFO: 2608290 events read in total (121246ms).
[15:53:09.534] <TB3> INFO: 3120000 events read in total (144076ms).
[15:53:09.598] <TB3> INFO: Test took 144975ms.
[15:53:32.640] <TB3> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 168 seconds
[15:53:32.640] <TB3> INFO: number of dead bumps (per ROC): 1 0 1 0 0 1 1 1 0 0 0 0 0 10 0 0
[15:53:32.640] <TB3> INFO: separation cut (per ROC): 105 98 102 87 98 101 97 102 107 106 109 111 99 107 104 100
[15:53:32.640] <TB3> INFO: Decoding statistics:
[15:53:32.640] <TB3> INFO: General information:
[15:53:32.640] <TB3> INFO: 16bit words read: 0
[15:53:32.640] <TB3> INFO: valid events total: 0
[15:53:32.640] <TB3> INFO: empty events: 0
[15:53:32.640] <TB3> INFO: valid events with pixels: 0
[15:53:32.640] <TB3> INFO: valid pixel hits: 0
[15:53:32.640] <TB3> INFO: Event errors: 0
[15:53:32.640] <TB3> INFO: start marker: 0
[15:53:32.640] <TB3> INFO: stop marker: 0
[15:53:32.640] <TB3> INFO: overflow: 0
[15:53:32.640] <TB3> INFO: invalid 5bit words: 0
[15:53:32.640] <TB3> INFO: invalid XOR eye diagram: 0
[15:53:32.640] <TB3> INFO: frame (failed synchr.): 0
[15:53:32.640] <TB3> INFO: idle data (no TBM trl): 0
[15:53:32.640] <TB3> INFO: no data (only TBM hdr): 0
[15:53:32.640] <TB3> INFO: TBM errors: 0
[15:53:32.640] <TB3> INFO: flawed TBM headers: 0
[15:53:32.640] <TB3> INFO: flawed TBM trailers: 0
[15:53:32.640] <TB3> INFO: event ID mismatches: 0
[15:53:32.640] <TB3> INFO: ROC errors: 0
[15:53:32.640] <TB3> INFO: missing ROC header(s): 0
[15:53:32.640] <TB3> INFO: misplaced readback start: 0
[15:53:32.640] <TB3> INFO: Pixel decoding errors: 0
[15:53:32.640] <TB3> INFO: pixel data incomplete: 0
[15:53:32.640] <TB3> INFO: pixel address: 0
[15:53:32.640] <TB3> INFO: pulse height fill bit: 0
[15:53:32.640] <TB3> INFO: buffer corruption: 0
[15:53:32.676] <TB3> INFO: ######################################################################
[15:53:32.676] <TB3> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[15:53:32.676] <TB3> INFO: ######################################################################
[15:53:32.676] <TB3> INFO: ----------------------------------------------------------------------
[15:53:32.676] <TB3> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[15:53:32.676] <TB3> INFO: ----------------------------------------------------------------------
[15:53:32.676] <TB3> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[15:53:32.690] <TB3> INFO: dacScan split into 1 runs with ntrig = 50
[15:53:32.690] <TB3> INFO: run 1 of 1
[15:53:32.965] <TB3> INFO: Expecting 36608000 events.
[15:53:56.578] <TB3> INFO: 675800 events read in total (23021ms).
[15:54:19.455] <TB3> INFO: 1336550 events read in total (45898ms).
[15:54:42.317] <TB3> INFO: 1997400 events read in total (68760ms).
[15:55:04.913] <TB3> INFO: 2656950 events read in total (91356ms).
[15:55:27.630] <TB3> INFO: 3316500 events read in total (114073ms).
[15:55:50.448] <TB3> INFO: 3975350 events read in total (136891ms).
[15:56:13.093] <TB3> INFO: 4634800 events read in total (159536ms).
[15:56:35.868] <TB3> INFO: 5294150 events read in total (182311ms).
[15:56:59.026] <TB3> INFO: 5952400 events read in total (205469ms).
[15:57:21.875] <TB3> INFO: 6609450 events read in total (228318ms).
[15:57:44.762] <TB3> INFO: 7268100 events read in total (251205ms).
[15:58:07.714] <TB3> INFO: 7925150 events read in total (274157ms).
[15:58:30.589] <TB3> INFO: 8581050 events read in total (297032ms).
[15:58:53.531] <TB3> INFO: 9237350 events read in total (319974ms).
[15:59:16.340] <TB3> INFO: 9893400 events read in total (342783ms).
[15:59:39.428] <TB3> INFO: 10550900 events read in total (365871ms).
[16:00:02.401] <TB3> INFO: 11207150 events read in total (388844ms).
[16:00:25.466] <TB3> INFO: 11862300 events read in total (411909ms).
[16:00:48.355] <TB3> INFO: 12517350 events read in total (434798ms).
[16:01:11.488] <TB3> INFO: 13173450 events read in total (457931ms).
[16:01:34.382] <TB3> INFO: 13829900 events read in total (480825ms).
[16:01:57.173] <TB3> INFO: 14484750 events read in total (503616ms).
[16:02:19.918] <TB3> INFO: 15141550 events read in total (526361ms).
[16:02:42.806] <TB3> INFO: 15795450 events read in total (549249ms).
[16:03:05.774] <TB3> INFO: 16451000 events read in total (572217ms).
[16:03:28.520] <TB3> INFO: 17104550 events read in total (594963ms).
[16:03:51.426] <TB3> INFO: 17759750 events read in total (617869ms).
[16:04:14.084] <TB3> INFO: 18413650 events read in total (640527ms).
[16:04:36.981] <TB3> INFO: 19066600 events read in total (663424ms).
[16:04:59.734] <TB3> INFO: 19717100 events read in total (686177ms).
[16:05:22.430] <TB3> INFO: 20369300 events read in total (708873ms).
[16:05:45.161] <TB3> INFO: 21021400 events read in total (731604ms).
[16:06:07.942] <TB3> INFO: 21674200 events read in total (754385ms).
[16:06:30.755] <TB3> INFO: 22325850 events read in total (777198ms).
[16:06:53.508] <TB3> INFO: 22979750 events read in total (799951ms).
[16:07:16.217] <TB3> INFO: 23632600 events read in total (822660ms).
[16:07:38.001] <TB3> INFO: 24283850 events read in total (845444ms).
[16:08:01.847] <TB3> INFO: 24934950 events read in total (868290ms).
[16:08:24.378] <TB3> INFO: 25587350 events read in total (890821ms).
[16:08:47.195] <TB3> INFO: 26237800 events read in total (913638ms).
[16:09:09.877] <TB3> INFO: 26888750 events read in total (936320ms).
[16:09:32.896] <TB3> INFO: 27539900 events read in total (959339ms).
[16:09:55.621] <TB3> INFO: 28188800 events read in total (982064ms).
[16:10:18.360] <TB3> INFO: 28839350 events read in total (1004803ms).
[16:10:41.089] <TB3> INFO: 29488250 events read in total (1027532ms).
[16:11:03.993] <TB3> INFO: 30139100 events read in total (1050436ms).
[16:11:26.730] <TB3> INFO: 30790200 events read in total (1073173ms).
[16:11:49.663] <TB3> INFO: 31440800 events read in total (1096106ms).
[16:12:12.264] <TB3> INFO: 32092000 events read in total (1118707ms).
[16:12:34.974] <TB3> INFO: 32743100 events read in total (1141417ms).
[16:12:57.738] <TB3> INFO: 33396500 events read in total (1164181ms).
[16:13:20.492] <TB3> INFO: 34051800 events read in total (1186935ms).
[16:13:43.517] <TB3> INFO: 34705000 events read in total (1209960ms).
[16:14:06.133] <TB3> INFO: 35357650 events read in total (1232576ms).
[16:14:29.981] <TB3> INFO: 36012450 events read in total (1256424ms).
[16:14:51.306] <TB3> INFO: 36608000 events read in total (1277749ms).
[16:14:51.382] <TB3> INFO: Test took 1278692ms.
[16:14:51.817] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:14:53.379] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:14:54.916] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:14:56.475] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:14:58.028] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:14:59.580] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:15:01.106] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:15:02.684] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:15:04.263] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:15:05.840] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:15:07.389] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:15:08.920] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:15:10.478] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:15:12.017] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:15:13.519] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:15:15.027] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[16:15:16.623] <TB3> INFO: PixTestScurves::scurves() done
[16:15:16.623] <TB3> INFO: Vcal mean: 122.50 110.61 125.43 118.97 110.63 114.15 105.56 108.59 112.22 115.55 124.36 121.31 112.48 104.92 118.93 111.74
[16:15:16.623] <TB3> INFO: Vcal RMS: 6.59 5.69 8.49 8.57 5.25 5.45 5.50 5.00 4.63 5.37 6.52 6.49 5.18 5.68 6.13 5.09
[16:15:16.623] <TB3> INFO: PixTestScurves::fullTest() done, duration: 1303 seconds
[16:15:16.623] <TB3> INFO: Decoding statistics:
[16:15:16.623] <TB3> INFO: General information:
[16:15:16.623] <TB3> INFO: 16bit words read: 0
[16:15:16.623] <TB3> INFO: valid events total: 0
[16:15:16.623] <TB3> INFO: empty events: 0
[16:15:16.623] <TB3> INFO: valid events with pixels: 0
[16:15:16.623] <TB3> INFO: valid pixel hits: 0
[16:15:16.623] <TB3> INFO: Event errors: 0
[16:15:16.623] <TB3> INFO: start marker: 0
[16:15:16.623] <TB3> INFO: stop marker: 0
[16:15:16.623] <TB3> INFO: overflow: 0
[16:15:16.623] <TB3> INFO: invalid 5bit words: 0
[16:15:16.623] <TB3> INFO: invalid XOR eye diagram: 0
[16:15:16.623] <TB3> INFO: frame (failed synchr.): 0
[16:15:16.623] <TB3> INFO: idle data (no TBM trl): 0
[16:15:16.623] <TB3> INFO: no data (only TBM hdr): 0
[16:15:16.623] <TB3> INFO: TBM errors: 0
[16:15:16.623] <TB3> INFO: flawed TBM headers: 0
[16:15:16.623] <TB3> INFO: flawed TBM trailers: 0
[16:15:16.623] <TB3> INFO: event ID mismatches: 0
[16:15:16.624] <TB3> INFO: ROC errors: 0
[16:15:16.624] <TB3> INFO: missing ROC header(s): 0
[16:15:16.624] <TB3> INFO: misplaced readback start: 0
[16:15:16.624] <TB3> INFO: Pixel decoding errors: 0
[16:15:16.624] <TB3> INFO: pixel data incomplete: 0
[16:15:16.624] <TB3> INFO: pixel address: 0
[16:15:16.624] <TB3> INFO: pulse height fill bit: 0
[16:15:16.624] <TB3> INFO: buffer corruption: 0
[16:15:16.691] <TB3> INFO: ######################################################################
[16:15:16.691] <TB3> INFO: PixTestTrim::doTest()
[16:15:16.691] <TB3> INFO: ######################################################################
[16:15:16.692] <TB3> INFO: ----------------------------------------------------------------------
[16:15:16.692] <TB3> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[16:15:16.692] <TB3> INFO: ----------------------------------------------------------------------
[16:15:16.756] <TB3> INFO: ---> VthrComp thr map (minimal VthrComp)
[16:15:16.756] <TB3> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[16:15:16.769] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[16:15:16.769] <TB3> INFO: run 1 of 1
[16:15:17.007] <TB3> INFO: Expecting 5025280 events.
[16:15:48.530] <TB3> INFO: 821256 events read in total (30919ms).
[16:16:19.343] <TB3> INFO: 1639264 events read in total (61732ms).
[16:16:50.274] <TB3> INFO: 2454472 events read in total (92663ms).
[16:17:21.043] <TB3> INFO: 3268056 events read in total (123432ms).
[16:17:51.564] <TB3> INFO: 4078896 events read in total (153953ms).
[16:18:22.067] <TB3> INFO: 4888568 events read in total (184456ms).
[16:18:27.360] <TB3> INFO: 5025280 events read in total (189749ms).
[16:18:27.413] <TB3> INFO: Test took 190643ms.
[16:18:43.340] <TB3> INFO: ROC 0 VthrComp = 122
[16:18:43.340] <TB3> INFO: ROC 1 VthrComp = 113
[16:18:43.340] <TB3> INFO: ROC 2 VthrComp = 117
[16:18:43.340] <TB3> INFO: ROC 3 VthrComp = 108
[16:18:43.340] <TB3> INFO: ROC 4 VthrComp = 115
[16:18:43.341] <TB3> INFO: ROC 5 VthrComp = 114
[16:18:43.341] <TB3> INFO: ROC 6 VthrComp = 105
[16:18:43.341] <TB3> INFO: ROC 7 VthrComp = 114
[16:18:43.341] <TB3> INFO: ROC 8 VthrComp = 124
[16:18:43.341] <TB3> INFO: ROC 9 VthrComp = 118
[16:18:43.341] <TB3> INFO: ROC 10 VthrComp = 123
[16:18:43.341] <TB3> INFO: ROC 11 VthrComp = 125
[16:18:43.342] <TB3> INFO: ROC 12 VthrComp = 115
[16:18:43.342] <TB3> INFO: ROC 13 VthrComp = 108
[16:18:43.342] <TB3> INFO: ROC 14 VthrComp = 112
[16:18:43.342] <TB3> INFO: ROC 15 VthrComp = 112
[16:18:43.582] <TB3> INFO: Expecting 41600 events.
[16:18:47.084] <TB3> INFO: 41600 events read in total (2910ms).
[16:18:47.085] <TB3> INFO: Test took 3741ms.
[16:18:47.094] <TB3> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[16:18:47.095] <TB3> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[16:18:47.106] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[16:18:47.106] <TB3> INFO: run 1 of 1
[16:18:47.384] <TB3> INFO: Expecting 5025280 events.
[16:19:14.051] <TB3> INFO: 591752 events read in total (26075ms).
[16:19:40.117] <TB3> INFO: 1181952 events read in total (52141ms).
[16:20:06.405] <TB3> INFO: 1772696 events read in total (78429ms).
[16:20:32.656] <TB3> INFO: 2362368 events read in total (104680ms).
[16:20:58.944] <TB3> INFO: 2950344 events read in total (130968ms).
[16:21:24.944] <TB3> INFO: 3536696 events read in total (156968ms).
[16:21:51.761] <TB3> INFO: 4122616 events read in total (183785ms).
[16:22:17.726] <TB3> INFO: 4708408 events read in total (209750ms).
[16:22:31.931] <TB3> INFO: 5025280 events read in total (223955ms).
[16:22:31.997] <TB3> INFO: Test took 224891ms.
[16:22:54.076] <TB3> INFO: roc 0 with ID = 0 has maximal Vcal 63.7646 for pixel 50/0 mean/min/max = 47.2879/30.5368/64.0391
[16:22:54.077] <TB3> INFO: roc 1 with ID = 1 has maximal Vcal 61.515 for pixel 15/73 mean/min/max = 46.8313/31.7144/61.9483
[16:22:54.077] <TB3> INFO: roc 2 with ID = 2 has maximal Vcal 71.7285 for pixel 0/15 mean/min/max = 49.9977/28.1589/71.8366
[16:22:54.077] <TB3> INFO: roc 3 with ID = 3 has maximal Vcal 74.3275 for pixel 0/15 mean/min/max = 54.1243/33.9028/74.3458
[16:22:54.078] <TB3> INFO: roc 4 with ID = 4 has maximal Vcal 60.399 for pixel 20/69 mean/min/max = 45.8399/31.1864/60.4935
[16:22:54.078] <TB3> INFO: roc 5 with ID = 5 has maximal Vcal 61.8564 for pixel 49/9 mean/min/max = 47.0657/32.2369/61.8946
[16:22:54.079] <TB3> INFO: roc 6 with ID = 6 has maximal Vcal 64.6755 for pixel 12/3 mean/min/max = 48.8024/32.8387/64.7661
[16:22:54.079] <TB3> INFO: roc 7 with ID = 7 has maximal Vcal 58.3432 for pixel 1/2 mean/min/max = 45.1418/31.8881/58.3955
[16:22:54.080] <TB3> INFO: roc 8 with ID = 8 has maximal Vcal 58.4804 for pixel 40/78 mean/min/max = 44.9484/31.3833/58.5135
[16:22:54.080] <TB3> INFO: roc 9 with ID = 9 has maximal Vcal 62.0729 for pixel 15/0 mean/min/max = 46.7381/31.1522/62.3239
[16:22:54.081] <TB3> INFO: roc 10 with ID = 10 has maximal Vcal 62.8787 for pixel 8/13 mean/min/max = 47.1652/31.3993/62.9312
[16:22:54.081] <TB3> INFO: roc 11 with ID = 11 has maximal Vcal 61.2826 for pixel 45/1 mean/min/max = 46.2678/31.1535/61.3821
[16:22:54.082] <TB3> INFO: roc 12 with ID = 12 has maximal Vcal 60.8349 for pixel 3/4 mean/min/max = 46.4549/31.968/60.9417
[16:22:54.083] <TB3> INFO: roc 13 with ID = 13 has maximal Vcal 60.97 for pixel 15/62 mean/min/max = 47.3215/33.669/60.9739
[16:22:54.083] <TB3> INFO: roc 14 with ID = 14 has maximal Vcal 64.9076 for pixel 0/76 mean/min/max = 48.4206/31.7179/65.1233
[16:22:54.083] <TB3> INFO: roc 15 with ID = 15 has maximal Vcal 60.785 for pixel 0/76 mean/min/max = 46.5379/31.9703/61.1054
[16:22:54.084] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:22:54.179] <TB3> INFO: Expecting 411648 events.
[16:23:03.931] <TB3> INFO: 411648 events read in total (9160ms).
[16:23:03.939] <TB3> INFO: Expecting 411648 events.
[16:23:13.485] <TB3> INFO: 411648 events read in total (9143ms).
[16:23:13.495] <TB3> INFO: Expecting 411648 events.
[16:23:22.981] <TB3> INFO: 411648 events read in total (9083ms).
[16:23:22.999] <TB3> INFO: Expecting 411648 events.
[16:23:32.463] <TB3> INFO: 411648 events read in total (9061ms).
[16:23:32.483] <TB3> INFO: Expecting 411648 events.
[16:23:41.989] <TB3> INFO: 411648 events read in total (9103ms).
[16:23:42.009] <TB3> INFO: Expecting 411648 events.
[16:23:51.524] <TB3> INFO: 411648 events read in total (9112ms).
[16:23:51.552] <TB3> INFO: Expecting 411648 events.
[16:24:01.038] <TB3> INFO: 411648 events read in total (9084ms).
[16:24:01.070] <TB3> INFO: Expecting 411648 events.
[16:24:10.599] <TB3> INFO: 411648 events read in total (9126ms).
[16:24:10.627] <TB3> INFO: Expecting 411648 events.
[16:24:20.099] <TB3> INFO: 411648 events read in total (9069ms).
[16:24:20.129] <TB3> INFO: Expecting 411648 events.
[16:24:29.580] <TB3> INFO: 411648 events read in total (9048ms).
[16:24:29.614] <TB3> INFO: Expecting 411648 events.
[16:24:39.119] <TB3> INFO: 411648 events read in total (9102ms).
[16:24:39.165] <TB3> INFO: Expecting 411648 events.
[16:24:48.886] <TB3> INFO: 411648 events read in total (9318ms).
[16:24:48.925] <TB3> INFO: Expecting 411648 events.
[16:24:58.114] <TB3> INFO: 411648 events read in total (8786ms).
[16:24:58.158] <TB3> INFO: Expecting 411648 events.
[16:25:07.416] <TB3> INFO: 411648 events read in total (8855ms).
[16:25:07.472] <TB3> INFO: Expecting 411648 events.
[16:25:17.158] <TB3> INFO: 411648 events read in total (9283ms).
[16:25:17.205] <TB3> INFO: Expecting 411648 events.
[16:25:26.409] <TB3> INFO: 411648 events read in total (8801ms).
[16:25:26.471] <TB3> INFO: Test took 152387ms.
[16:25:27.229] <TB3> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[16:25:27.239] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[16:25:27.239] <TB3> INFO: run 1 of 1
[16:25:27.479] <TB3> INFO: Expecting 5025280 events.
[16:25:54.351] <TB3> INFO: 590248 events read in total (26280ms).
[16:26:20.933] <TB3> INFO: 1178984 events read in total (52862ms).
[16:26:47.459] <TB3> INFO: 1769320 events read in total (79388ms).
[16:27:13.739] <TB3> INFO: 2357568 events read in total (105668ms).
[16:27:40.136] <TB3> INFO: 2945072 events read in total (132065ms).
[16:28:06.374] <TB3> INFO: 3533728 events read in total (158303ms).
[16:28:32.244] <TB3> INFO: 4122688 events read in total (184173ms).
[16:28:58.462] <TB3> INFO: 4709304 events read in total (210391ms).
[16:29:13.262] <TB3> INFO: 5025280 events read in total (225191ms).
[16:29:13.376] <TB3> INFO: Test took 226138ms.
[16:29:33.633] <TB3> INFO: ---> TrimStepCorr4 extremal thresholds: 0.892690 .. 145.502522
[16:29:33.871] <TB3> INFO: Expecting 208000 events.
[16:29:43.509] <TB3> INFO: 208000 events read in total (9047ms).
[16:29:43.511] <TB3> INFO: Test took 9877ms.
[16:29:43.594] <TB3> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 0 .. 155 (-1/-1) hits flags = 528 (plus default)
[16:29:43.607] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[16:29:43.607] <TB3> INFO: run 1 of 1
[16:29:43.886] <TB3> INFO: Expecting 5191680 events.
[16:30:10.354] <TB3> INFO: 586520 events read in total (25877ms).
[16:30:36.874] <TB3> INFO: 1173072 events read in total (52398ms).
[16:31:03.294] <TB3> INFO: 1759128 events read in total (78818ms).
[16:31:29.424] <TB3> INFO: 2344984 events read in total (104947ms).
[16:31:55.738] <TB3> INFO: 2931072 events read in total (131261ms).
[16:32:21.895] <TB3> INFO: 3515480 events read in total (157418ms).
[16:32:48.233] <TB3> INFO: 4100632 events read in total (183756ms).
[16:33:13.875] <TB3> INFO: 4685512 events read in total (209399ms).
[16:33:36.717] <TB3> INFO: 5191680 events read in total (232240ms).
[16:33:36.819] <TB3> INFO: Test took 233213ms.
[16:33:58.930] <TB3> INFO: ---> TrimStepCorr2 extremal thresholds: 26.268992 .. 47.566644
[16:33:59.172] <TB3> INFO: Expecting 208000 events.
[16:34:09.135] <TB3> INFO: 208000 events read in total (9371ms).
[16:34:09.136] <TB3> INFO: Test took 10205ms.
[16:34:09.185] <TB3> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 57 (-1/-1) hits flags = 528 (plus default)
[16:34:09.196] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[16:34:09.196] <TB3> INFO: run 1 of 1
[16:34:09.474] <TB3> INFO: Expecting 1397760 events.
[16:34:37.537] <TB3> INFO: 655144 events read in total (27471ms).
[16:35:05.610] <TB3> INFO: 1309208 events read in total (55545ms).
[16:35:09.803] <TB3> INFO: 1397760 events read in total (59737ms).
[16:35:09.837] <TB3> INFO: Test took 60642ms.
[16:35:22.202] <TB3> INFO: ---> TrimStepCorr1a extremal thresholds: 26.240682 .. 49.667708
[16:35:22.443] <TB3> INFO: Expecting 208000 events.
[16:35:32.702] <TB3> INFO: 208000 events read in total (9668ms).
[16:35:32.703] <TB3> INFO: Test took 10499ms.
[16:35:32.752] <TB3> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 59 (-1/-1) hits flags = 528 (plus default)
[16:35:32.765] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[16:35:32.765] <TB3> INFO: run 1 of 1
[16:35:33.043] <TB3> INFO: Expecting 1464320 events.
[16:36:01.770] <TB3> INFO: 649216 events read in total (28135ms).
[16:36:29.684] <TB3> INFO: 1297472 events read in total (56049ms).
[16:36:37.038] <TB3> INFO: 1464320 events read in total (63404ms).
[16:36:37.077] <TB3> INFO: Test took 64313ms.
[16:36:49.599] <TB3> INFO: ---> TrimStepCorr1b extremal thresholds: 23.815817 .. 51.625792
[16:36:49.837] <TB3> INFO: Expecting 208000 events.
[16:36:59.869] <TB3> INFO: 208000 events read in total (9440ms).
[16:36:59.869] <TB3> INFO: Test took 10269ms.
[16:36:59.918] <TB3> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 13 .. 61 (-1/-1) hits flags = 528 (plus default)
[16:36:59.931] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[16:36:59.931] <TB3> INFO: run 1 of 1
[16:37:00.209] <TB3> INFO: Expecting 1630720 events.
[16:37:29.553] <TB3> INFO: 653080 events read in total (28752ms).
[16:37:57.139] <TB3> INFO: 1306232 events read in total (56338ms).
[16:38:10.792] <TB3> INFO: 1630720 events read in total (69991ms).
[16:38:10.831] <TB3> INFO: Test took 70901ms.
[16:38:27.348] <TB3> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[16:38:27.348] <TB3> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[16:38:27.363] <TB3> INFO: dacScan split into 1 runs with ntrig = 8
[16:38:27.363] <TB3> INFO: run 1 of 1
[16:38:27.687] <TB3> INFO: Expecting 1364480 events.
[16:38:56.693] <TB3> INFO: 668096 events read in total (28414ms).
[16:39:25.600] <TB3> INFO: 1335264 events read in total (57321ms).
[16:39:27.358] <TB3> INFO: 1364480 events read in total (59080ms).
[16:39:27.386] <TB3> INFO: Test took 60023ms.
[16:39:39.902] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C0.dat
[16:39:39.902] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C1.dat
[16:39:39.902] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C2.dat
[16:39:39.902] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C3.dat
[16:39:39.903] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C4.dat
[16:39:39.903] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C5.dat
[16:39:39.903] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C6.dat
[16:39:39.903] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C7.dat
[16:39:39.904] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C8.dat
[16:39:39.904] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C9.dat
[16:39:39.904] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C10.dat
[16:39:39.904] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C11.dat
[16:39:39.905] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C12.dat
[16:39:39.905] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C13.dat
[16:39:39.905] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C14.dat
[16:39:39.905] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C15.dat
[16:39:39.906] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C0.dat
[16:39:39.919] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C1.dat
[16:39:39.927] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C2.dat
[16:39:39.935] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C3.dat
[16:39:39.944] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C4.dat
[16:39:39.952] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C5.dat
[16:39:39.960] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C6.dat
[16:39:39.968] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C7.dat
[16:39:39.976] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C8.dat
[16:39:39.985] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C9.dat
[16:39:39.993] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C10.dat
[16:39:39.001] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C11.dat
[16:39:40.009] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C12.dat
[16:39:40.017] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C13.dat
[16:39:40.026] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C14.dat
[16:39:40.034] <TB3> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C15.dat
[16:39:40.042] <TB3> INFO: PixTestTrim::trimTest() done
[16:39:40.042] <TB3> INFO: vtrim: 152 118 138 122 138 146 133 131 131 147 134 132 127 121 109 116
[16:39:40.042] <TB3> INFO: vthrcomp: 122 113 117 108 115 114 105 114 124 118 123 125 115 108 112 112
[16:39:40.042] <TB3> INFO: vcal mean: 35.06 34.95 35.19 36.05 34.94 35.03 34.99 34.98 34.99 35.04 35.06 35.01 34.94 35.02 35.25 34.98
[16:39:40.042] <TB3> INFO: vcal RMS: 1.27 1.12 1.60 2.37 1.06 1.04 1.06 0.98 1.08 1.19 1.21 1.38 1.11 0.95 1.50 1.16
[16:39:40.042] <TB3> INFO: bits mean: 9.93 9.20 8.93 7.87 10.08 9.80 9.26 9.43 10.00 9.77 9.54 9.97 9.49 8.91 8.92 8.97
[16:39:40.042] <TB3> INFO: bits RMS: 2.57 2.80 3.12 2.99 2.51 2.45 2.46 2.79 2.61 2.66 2.69 2.57 2.66 2.61 2.97 2.84
[16:39:40.050] <TB3> INFO: ----------------------------------------------------------------------
[16:39:40.050] <TB3> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[16:39:40.050] <TB3> INFO: ----------------------------------------------------------------------
[16:39:40.052] <TB3> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[16:39:40.065] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[16:39:40.065] <TB3> INFO: run 1 of 1
[16:39:40.346] <TB3> INFO: Expecting 4160000 events.
[16:40:12.808] <TB3> INFO: 744255 events read in total (31870ms).
[16:40:44.678] <TB3> INFO: 1481745 events read in total (63740ms).
[16:41:16.951] <TB3> INFO: 2216080 events read in total (96013ms).
[16:41:48.805] <TB3> INFO: 2947270 events read in total (127867ms).
[16:42:21.114] <TB3> INFO: 3675350 events read in total (160176ms).
[16:42:42.867] <TB3> INFO: 4160000 events read in total (181929ms).
[16:42:42.941] <TB3> INFO: Test took 182876ms.
[16:43:07.260] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[16:43:07.274] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[16:43:07.274] <TB3> INFO: run 1 of 1
[16:43:07.513] <TB3> INFO: Expecting 4284800 events.
[16:43:39.797] <TB3> INFO: 712895 events read in total (31692ms).
[16:44:11.848] <TB3> INFO: 1420300 events read in total (63743ms).
[16:44:43.709] <TB3> INFO: 2124930 events read in total (95604ms).
[16:45:15.122] <TB3> INFO: 2826990 events read in total (127017ms).
[16:45:46.285] <TB3> INFO: 3526630 events read in total (158180ms).
[16:46:17.368] <TB3> INFO: 4227085 events read in total (189263ms).
[16:46:20.279] <TB3> INFO: 4284800 events read in total (192174ms).
[16:46:20.355] <TB3> INFO: Test took 193081ms.
[16:46:45.808] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[16:46:45.821] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[16:46:45.821] <TB3> INFO: run 1 of 1
[16:46:46.062] <TB3> INFO: Expecting 4160000 events.
[16:47:18.015] <TB3> INFO: 720450 events read in total (31361ms).
[16:47:49.227] <TB3> INFO: 1434710 events read in total (62573ms).
[16:48:20.268] <TB3> INFO: 2146560 events read in total (93614ms).
[16:48:51.385] <TB3> INFO: 2855130 events read in total (124731ms).
[16:49:22.104] <TB3> INFO: 3561200 events read in total (155450ms).
[16:49:49.145] <TB3> INFO: 4160000 events read in total (182491ms).
[16:49:49.287] <TB3> INFO: Test took 183466ms.
[16:50:14.209] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[16:50:14.223] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[16:50:14.223] <TB3> INFO: run 1 of 1
[16:50:14.517] <TB3> INFO: Expecting 4160000 events.
[16:50:46.941] <TB3> INFO: 720535 events read in total (31832ms).
[16:51:18.870] <TB3> INFO: 1434875 events read in total (63761ms).
[16:51:50.581] <TB3> INFO: 2146805 events read in total (95472ms).
[16:52:21.243] <TB3> INFO: 2855520 events read in total (126134ms).
[16:52:52.016] <TB3> INFO: 3561600 events read in total (156907ms).
[16:53:18.637] <TB3> INFO: 4160000 events read in total (183528ms).
[16:53:18.718] <TB3> INFO: Test took 184495ms.
[16:53:42.094] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[16:53:42.107] <TB3> INFO: dacScan split into 1 runs with ntrig = 5
[16:53:42.107] <TB3> INFO: run 1 of 1
[16:53:42.344] <TB3> INFO: Expecting 4139200 events.
[16:54:14.570] <TB3> INFO: 722050 events read in total (31634ms).
[16:54:45.608] <TB3> INFO: 1437730 events read in total (62672ms).
[16:55:16.796] <TB3> INFO: 2151060 events read in total (93860ms).
[16:55:48.300] <TB3> INFO: 2861005 events read in total (125364ms).
[16:56:19.679] <TB3> INFO: 3568020 events read in total (156743ms).
[16:56:44.683] <TB3> INFO: 4139200 events read in total (181747ms).
[16:56:44.763] <TB3> INFO: Test took 182656ms.
[16:57:09.108] <TB3> INFO: PixTestTrim::trimBitTest() done
[16:57:09.109] <TB3> INFO: PixTestTrim::doTest() done, duration: 2512 seconds
[16:57:09.109] <TB3> INFO: Decoding statistics:
[16:57:09.109] <TB3> INFO: General information:
[16:57:09.109] <TB3> INFO: 16bit words read: 0
[16:57:09.109] <TB3> INFO: valid events total: 0
[16:57:09.109] <TB3> INFO: empty events: 0
[16:57:09.109] <TB3> INFO: valid events with pixels: 0
[16:57:09.109] <TB3> INFO: valid pixel hits: 0
[16:57:09.109] <TB3> INFO: Event errors: 0
[16:57:09.109] <TB3> INFO: start marker: 0
[16:57:09.109] <TB3> INFO: stop marker: 0
[16:57:09.109] <TB3> INFO: overflow: 0
[16:57:09.109] <TB3> INFO: invalid 5bit words: 0
[16:57:09.109] <TB3> INFO: invalid XOR eye diagram: 0
[16:57:09.109] <TB3> INFO: frame (failed synchr.): 0
[16:57:09.109] <TB3> INFO: idle data (no TBM trl): 0
[16:57:09.109] <TB3> INFO: no data (only TBM hdr): 0
[16:57:09.109] <TB3> INFO: TBM errors: 0
[16:57:09.109] <TB3> INFO: flawed TBM headers: 0
[16:57:09.109] <TB3> INFO: flawed TBM trailers: 0
[16:57:09.109] <TB3> INFO: event ID mismatches: 0
[16:57:09.109] <TB3> INFO: ROC errors: 0
[16:57:09.109] <TB3> INFO: missing ROC header(s): 0
[16:57:09.109] <TB3> INFO: misplaced readback start: 0
[16:57:09.109] <TB3> INFO: Pixel decoding errors: 0
[16:57:09.109] <TB3> INFO: pixel data incomplete: 0
[16:57:09.109] <TB3> INFO: pixel address: 0
[16:57:09.109] <TB3> INFO: pulse height fill bit: 0
[16:57:09.109] <TB3> INFO: buffer corruption: 0
[16:57:09.886] <TB3> INFO: ######################################################################
[16:57:09.886] <TB3> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[16:57:09.886] <TB3> INFO: ######################################################################
[16:57:10.124] <TB3> INFO: Expecting 41600 events.
[16:57:13.662] <TB3> INFO: 41600 events read in total (2946ms).
[16:57:13.663] <TB3> INFO: Test took 3776ms.
[16:57:14.106] <TB3> INFO: Expecting 41600 events.
[16:57:17.685] <TB3> INFO: 41600 events read in total (2988ms).
[16:57:17.685] <TB3> INFO: Test took 3818ms.
[16:57:17.974] <TB3> INFO: Expecting 41600 events.
[16:57:21.511] <TB3> INFO: 41600 events read in total (2945ms).
[16:57:21.511] <TB3> INFO: Test took 3802ms.
[16:57:21.817] <TB3> INFO: Expecting 41600 events.
[16:57:25.463] <TB3> INFO: 41600 events read in total (3055ms).
[16:57:25.463] <TB3> INFO: Test took 3928ms.
[16:57:25.753] <TB3> INFO: Expecting 41600 events.
[16:57:29.332] <TB3> INFO: 41600 events read in total (2988ms).
[16:57:29.333] <TB3> INFO: Test took 3846ms.
[16:57:29.622] <TB3> INFO: Expecting 41600 events.
[16:57:33.305] <TB3> INFO: 41600 events read in total (3091ms).
[16:57:33.305] <TB3> INFO: Test took 3948ms.
[16:57:33.595] <TB3> INFO: Expecting 41600 events.
[16:57:37.158] <TB3> INFO: 41600 events read in total (2971ms).
[16:57:37.159] <TB3> INFO: Test took 3829ms.
[16:57:37.449] <TB3> INFO: Expecting 41600 events.
[16:57:41.030] <TB3> INFO: 41600 events read in total (2989ms).
[16:57:41.031] <TB3> INFO: Test took 3848ms.
[16:57:41.323] <TB3> INFO: Expecting 41600 events.
[16:57:44.882] <TB3> INFO: 41600 events read in total (2968ms).
[16:57:44.883] <TB3> INFO: Test took 3826ms.
[16:57:45.176] <TB3> INFO: Expecting 41600 events.
[16:57:48.764] <TB3> INFO: 41600 events read in total (2996ms).
[16:57:48.765] <TB3> INFO: Test took 3855ms.
[16:57:49.056] <TB3> INFO: Expecting 41600 events.
[16:57:52.706] <TB3> INFO: 41600 events read in total (3058ms).
[16:57:52.707] <TB3> INFO: Test took 3917ms.
[16:57:52.997] <TB3> INFO: Expecting 41600 events.
[16:57:56.548] <TB3> INFO: 41600 events read in total (2959ms).
[16:57:56.549] <TB3> INFO: Test took 3818ms.
[16:57:56.839] <TB3> INFO: Expecting 41600 events.
[16:58:00.403] <TB3> INFO: 41600 events read in total (2972ms).
[16:58:00.404] <TB3> INFO: Test took 3831ms.
[16:58:00.694] <TB3> INFO: Expecting 41600 events.
[16:58:04.267] <TB3> INFO: 41600 events read in total (2981ms).
[16:58:04.268] <TB3> INFO: Test took 3840ms.
[16:58:04.558] <TB3> INFO: Expecting 41600 events.
[16:58:08.183] <TB3> INFO: 41600 events read in total (3033ms).
[16:58:08.184] <TB3> INFO: Test took 3892ms.
[16:58:08.474] <TB3> INFO: Expecting 41600 events.
[16:58:12.110] <TB3> INFO: 41600 events read in total (3044ms).
[16:58:12.111] <TB3> INFO: Test took 3902ms.
[16:58:12.404] <TB3> INFO: Expecting 41600 events.
[16:58:15.982] <TB3> INFO: 41600 events read in total (2986ms).
[16:58:15.983] <TB3> INFO: Test took 3843ms.
[16:58:16.272] <TB3> INFO: Expecting 41600 events.
[16:58:19.815] <TB3> INFO: 41600 events read in total (2951ms).
[16:58:19.816] <TB3> INFO: Test took 3809ms.
[16:58:20.105] <TB3> INFO: Expecting 41600 events.
[16:58:23.765] <TB3> INFO: 41600 events read in total (3068ms).
[16:58:23.766] <TB3> INFO: Test took 3926ms.
[16:58:24.055] <TB3> INFO: Expecting 41600 events.
[16:58:27.598] <TB3> INFO: 41600 events read in total (2951ms).
[16:58:27.599] <TB3> INFO: Test took 3809ms.
[16:58:27.888] <TB3> INFO: Expecting 41600 events.
[16:58:31.449] <TB3> INFO: 41600 events read in total (2969ms).
[16:58:31.450] <TB3> INFO: Test took 3826ms.
[16:58:31.739] <TB3> INFO: Expecting 41600 events.
[16:58:35.322] <TB3> INFO: 41600 events read in total (2991ms).
[16:58:35.322] <TB3> INFO: Test took 3849ms.
[16:58:35.636] <TB3> INFO: Expecting 41600 events.
[16:58:39.214] <TB3> INFO: 41600 events read in total (2986ms).
[16:58:39.215] <TB3> INFO: Test took 3865ms.
[16:58:39.507] <TB3> INFO: Expecting 41600 events.
[16:58:43.063] <TB3> INFO: 41600 events read in total (2964ms).
[16:58:43.064] <TB3> INFO: Test took 3822ms.
[16:58:43.353] <TB3> INFO: Expecting 41600 events.
[16:58:46.938] <TB3> INFO: 41600 events read in total (2993ms).
[16:58:46.939] <TB3> INFO: Test took 3850ms.
[16:58:47.228] <TB3> INFO: Expecting 41600 events.
[16:58:50.797] <TB3> INFO: 41600 events read in total (2977ms).
[16:58:50.797] <TB3> INFO: Test took 3834ms.
[16:58:51.087] <TB3> INFO: Expecting 41600 events.
[16:58:54.618] <TB3> INFO: 41600 events read in total (2940ms).
[16:58:54.619] <TB3> INFO: Test took 3797ms.
[16:58:54.908] <TB3> INFO: Expecting 41600 events.
[16:58:58.459] <TB3> INFO: 41600 events read in total (2959ms).
[16:58:58.460] <TB3> INFO: Test took 3816ms.
[16:58:58.749] <TB3> INFO: Expecting 41600 events.
[16:59:02.281] <TB3> INFO: 41600 events read in total (2940ms).
[16:59:02.282] <TB3> INFO: Test took 3797ms.
[16:59:02.571] <TB3> INFO: Expecting 41600 events.
[16:59:06.138] <TB3> INFO: 41600 events read in total (2975ms).
[16:59:06.139] <TB3> INFO: Test took 3832ms.
[16:59:06.433] <TB3> INFO: Expecting 41600 events.
[16:59:10.007] <TB3> INFO: 41600 events read in total (2982ms).
[16:59:10.008] <TB3> INFO: Test took 3844ms.
[16:59:10.297] <TB3> INFO: Expecting 41600 events.
[16:59:13.918] <TB3> INFO: 41600 events read in total (3029ms).
[16:59:13.919] <TB3> INFO: Test took 3886ms.
[16:59:14.212] <TB3> INFO: Expecting 41600 events.
[16:59:17.778] <TB3> INFO: 41600 events read in total (2975ms).
[16:59:17.779] <TB3> INFO: Test took 3833ms.
[16:59:18.131] <TB3> INFO: Expecting 41600 events.
[16:59:21.805] <TB3> INFO: 41600 events read in total (3082ms).
[16:59:21.805] <TB3> INFO: Test took 4001ms.
[16:59:22.095] <TB3> INFO: Expecting 41600 events.
[16:59:25.767] <TB3> INFO: 41600 events read in total (3080ms).
[16:59:25.768] <TB3> INFO: Test took 3938ms.
[16:59:26.058] <TB3> INFO: Expecting 41600 events.
[16:59:29.615] <TB3> INFO: 41600 events read in total (2965ms).
[16:59:29.616] <TB3> INFO: Test took 3823ms.
[16:59:29.907] <TB3> INFO: Expecting 41600 events.
[16:59:33.455] <TB3> INFO: 41600 events read in total (2957ms).
[16:59:33.457] <TB3> INFO: Test took 3816ms.
[16:59:33.749] <TB3> INFO: Expecting 41600 events.
[16:59:37.308] <TB3> INFO: 41600 events read in total (2967ms).
[16:59:37.309] <TB3> INFO: Test took 3825ms.
[16:59:37.601] <TB3> INFO: Expecting 41600 events.
[16:59:41.225] <TB3> INFO: 41600 events read in total (3032ms).
[16:59:41.226] <TB3> INFO: Test took 3890ms.
[16:59:41.516] <TB3> INFO: Expecting 41600 events.
[16:59:45.105] <TB3> INFO: 41600 events read in total (2998ms).
[16:59:45.106] <TB3> INFO: Test took 3855ms.
[16:59:45.408] <TB3> INFO: Expecting 41600 events.
[16:59:48.992] <TB3> INFO: 41600 events read in total (2992ms).
[16:59:48.993] <TB3> INFO: Test took 3862ms.
[16:59:49.282] <TB3> INFO: Expecting 41600 events.
[16:59:52.853] <TB3> INFO: 41600 events read in total (2979ms).
[16:59:52.854] <TB3> INFO: Test took 3837ms.
[16:59:53.143] <TB3> INFO: Expecting 41600 events.
[16:59:56.705] <TB3> INFO: 41600 events read in total (2970ms).
[16:59:56.705] <TB3> INFO: Test took 3827ms.
[16:59:56.994] <TB3> INFO: Expecting 41600 events.
[17:00:00.564] <TB3> INFO: 41600 events read in total (2978ms).
[17:00:00.565] <TB3> INFO: Test took 3836ms.
[17:00:00.855] <TB3> INFO: Expecting 41600 events.
[17:00:04.381] <TB3> INFO: 41600 events read in total (2934ms).
[17:00:04.381] <TB3> INFO: Test took 3791ms.
[17:00:04.670] <TB3> INFO: Expecting 41600 events.
[17:00:08.225] <TB3> INFO: 41600 events read in total (2963ms).
[17:00:08.225] <TB3> INFO: Test took 3819ms.
[17:00:08.514] <TB3> INFO: Expecting 41600 events.
[17:00:12.064] <TB3> INFO: 41600 events read in total (2958ms).
[17:00:12.065] <TB3> INFO: Test took 3815ms.
[17:00:12.354] <TB3> INFO: Expecting 41600 events.
[17:00:15.886] <TB3> INFO: 41600 events read in total (2941ms).
[17:00:15.886] <TB3> INFO: Test took 3797ms.
[17:00:16.177] <TB3> INFO: Expecting 41600 events.
[17:00:19.720] <TB3> INFO: 41600 events read in total (2952ms).
[17:00:19.721] <TB3> INFO: Test took 3810ms.
[17:00:20.015] <TB3> INFO: Expecting 41600 events.
[17:00:23.703] <TB3> INFO: 41600 events read in total (3096ms).
[17:00:23.703] <TB3> INFO: Test took 3954ms.
[17:00:23.994] <TB3> INFO: Expecting 41600 events.
[17:00:27.582] <TB3> INFO: 41600 events read in total (2996ms).
[17:00:27.582] <TB3> INFO: Test took 3853ms.
[17:00:27.872] <TB3> INFO: Expecting 41600 events.
[17:00:31.420] <TB3> INFO: 41600 events read in total (2956ms).
[17:00:31.420] <TB3> INFO: Test took 3813ms.
[17:00:31.710] <TB3> INFO: Expecting 41600 events.
[17:00:35.251] <TB3> INFO: 41600 events read in total (2949ms).
[17:00:35.252] <TB3> INFO: Test took 3808ms.
[17:00:35.544] <TB3> INFO: Expecting 41600 events.
[17:00:39.147] <TB3> INFO: 41600 events read in total (3011ms).
[17:00:39.148] <TB3> INFO: Test took 3869ms.
[17:00:39.439] <TB3> INFO: Expecting 2560 events.
[17:00:40.334] <TB3> INFO: 2560 events read in total (303ms).
[17:00:40.335] <TB3> INFO: Test took 1173ms.
[17:00:40.642] <TB3> INFO: Expecting 2560 events.
[17:00:41.539] <TB3> INFO: 2560 events read in total (305ms).
[17:00:41.539] <TB3> INFO: Test took 1205ms.
[17:00:41.847] <TB3> INFO: Expecting 2560 events.
[17:00:42.736] <TB3> INFO: 2560 events read in total (297ms).
[17:00:42.736] <TB3> INFO: Test took 1196ms.
[17:00:43.044] <TB3> INFO: Expecting 2560 events.
[17:00:43.933] <TB3> INFO: 2560 events read in total (298ms).
[17:00:43.933] <TB3> INFO: Test took 1196ms.
[17:00:44.242] <TB3> INFO: Expecting 2560 events.
[17:00:45.127] <TB3> INFO: 2560 events read in total (292ms).
[17:00:45.128] <TB3> INFO: Test took 1194ms.
[17:00:45.436] <TB3> INFO: Expecting 2560 events.
[17:00:46.318] <TB3> INFO: 2560 events read in total (290ms).
[17:00:46.318] <TB3> INFO: Test took 1190ms.
[17:00:46.627] <TB3> INFO: Expecting 2560 events.
[17:00:47.511] <TB3> INFO: 2560 events read in total (293ms).
[17:00:47.511] <TB3> INFO: Test took 1192ms.
[17:00:47.819] <TB3> INFO: Expecting 2560 events.
[17:00:48.700] <TB3> INFO: 2560 events read in total (290ms).
[17:00:48.701] <TB3> INFO: Test took 1189ms.
[17:00:49.008] <TB3> INFO: Expecting 2560 events.
[17:00:49.896] <TB3> INFO: 2560 events read in total (296ms).
[17:00:49.897] <TB3> INFO: Test took 1196ms.
[17:00:50.204] <TB3> INFO: Expecting 2560 events.
[17:00:51.087] <TB3> INFO: 2560 events read in total (291ms).
[17:00:51.088] <TB3> INFO: Test took 1190ms.
[17:00:51.394] <TB3> INFO: Expecting 2560 events.
[17:00:52.287] <TB3> INFO: 2560 events read in total (301ms).
[17:00:52.287] <TB3> INFO: Test took 1199ms.
[17:00:52.595] <TB3> INFO: Expecting 2560 events.
[17:00:53.486] <TB3> INFO: 2560 events read in total (299ms).
[17:00:53.487] <TB3> INFO: Test took 1199ms.
[17:00:53.795] <TB3> INFO: Expecting 2560 events.
[17:00:54.692] <TB3> INFO: 2560 events read in total (305ms).
[17:00:54.692] <TB3> INFO: Test took 1205ms.
[17:00:54.000] <TB3> INFO: Expecting 2560 events.
[17:00:55.892] <TB3> INFO: 2560 events read in total (301ms).
[17:00:55.892] <TB3> INFO: Test took 1199ms.
[17:00:56.200] <TB3> INFO: Expecting 2560 events.
[17:00:57.088] <TB3> INFO: 2560 events read in total (297ms).
[17:00:57.089] <TB3> INFO: Test took 1196ms.
[17:00:57.396] <TB3> INFO: Expecting 2560 events.
[17:00:58.281] <TB3> INFO: 2560 events read in total (293ms).
[17:00:58.281] <TB3> INFO: Test took 1192ms.
[17:00:58.285] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:00:58.589] <TB3> INFO: Expecting 655360 events.
[17:01:13.836] <TB3> INFO: 655360 events read in total (14655ms).
[17:01:13.851] <TB3> INFO: Expecting 655360 events.
[17:01:28.713] <TB3> INFO: 655360 events read in total (14456ms).
[17:01:28.731] <TB3> INFO: Expecting 655360 events.
[17:01:43.659] <TB3> INFO: 655360 events read in total (14525ms).
[17:01:43.692] <TB3> INFO: Expecting 655360 events.
[17:01:58.623] <TB3> INFO: 655360 events read in total (14528ms).
[17:01:58.651] <TB3> INFO: Expecting 655360 events.
[17:02:13.609] <TB3> INFO: 655360 events read in total (14555ms).
[17:02:13.650] <TB3> INFO: Expecting 655360 events.
[17:02:28.583] <TB3> INFO: 655360 events read in total (14530ms).
[17:02:28.630] <TB3> INFO: Expecting 655360 events.
[17:02:43.627] <TB3> INFO: 655360 events read in total (14594ms).
[17:02:43.680] <TB3> INFO: Expecting 655360 events.
[17:02:58.624] <TB3> INFO: 655360 events read in total (14541ms).
[17:02:58.670] <TB3> INFO: Expecting 655360 events.
[17:03:13.592] <TB3> INFO: 655360 events read in total (14519ms).
[17:03:13.693] <TB3> INFO: Expecting 655360 events.
[17:03:28.142] <TB3> INFO: 655360 events read in total (14046ms).
[17:03:28.219] <TB3> INFO: Expecting 655360 events.
[17:03:43.015] <TB3> INFO: 655360 events read in total (14393ms).
[17:03:43.100] <TB3> INFO: Expecting 655360 events.
[17:03:58.020] <TB3> INFO: 655360 events read in total (14517ms).
[17:03:58.095] <TB3> INFO: Expecting 655360 events.
[17:04:13.272] <TB3> INFO: 655360 events read in total (14774ms).
[17:04:13.475] <TB3> INFO: Expecting 655360 events.
[17:04:28.733] <TB3> INFO: 655360 events read in total (14855ms).
[17:04:28.820] <TB3> INFO: Expecting 655360 events.
[17:04:43.844] <TB3> INFO: 655360 events read in total (14621ms).
[17:04:43.944] <TB3> INFO: Expecting 655360 events.
[17:04:58.847] <TB3> INFO: 655360 events read in total (14500ms).
[17:04:58.987] <TB3> INFO: Test took 240702ms.
[17:04:59.101] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:59.359] <TB3> INFO: Expecting 655360 events.
[17:05:14.219] <TB3> INFO: 655360 events read in total (14269ms).
[17:05:14.234] <TB3> INFO: Expecting 655360 events.
[17:05:28.912] <TB3> INFO: 655360 events read in total (14275ms).
[17:05:28.935] <TB3> INFO: Expecting 655360 events.
[17:05:43.820] <TB3> INFO: 655360 events read in total (14482ms).
[17:05:43.843] <TB3> INFO: Expecting 655360 events.
[17:05:58.468] <TB3> INFO: 655360 events read in total (14222ms).
[17:05:58.495] <TB3> INFO: Expecting 655360 events.
[17:06:13.326] <TB3> INFO: 655360 events read in total (14428ms).
[17:06:13.359] <TB3> INFO: Expecting 655360 events.
[17:06:28.217] <TB3> INFO: 655360 events read in total (14454ms).
[17:06:28.253] <TB3> INFO: Expecting 655360 events.
[17:06:43.105] <TB3> INFO: 655360 events read in total (14449ms).
[17:06:43.146] <TB3> INFO: Expecting 655360 events.
[17:06:57.079] <TB3> INFO: 655360 events read in total (13530ms).
[17:06:57.125] <TB3> INFO: Expecting 655360 events.
[17:07:11.391] <TB3> INFO: 655360 events read in total (13863ms).
[17:07:11.450] <TB3> INFO: Expecting 655360 events.
[17:07:25.841] <TB3> INFO: 655360 events read in total (13988ms).
[17:07:25.896] <TB3> INFO: Expecting 655360 events.
[17:07:40.784] <TB3> INFO: 655360 events read in total (14485ms).
[17:07:40.840] <TB3> INFO: Expecting 655360 events.
[17:07:55.788] <TB3> INFO: 655360 events read in total (14545ms).
[17:07:55.876] <TB3> INFO: Expecting 655360 events.
[17:08:10.794] <TB3> INFO: 655360 events read in total (14514ms).
[17:08:10.859] <TB3> INFO: Expecting 655360 events.
[17:08:25.817] <TB3> INFO: 655360 events read in total (14555ms).
[17:08:25.887] <TB3> INFO: Expecting 655360 events.
[17:08:40.827] <TB3> INFO: 655360 events read in total (14537ms).
[17:08:40.900] <TB3> INFO: Expecting 655360 events.
[17:08:55.840] <TB3> INFO: 655360 events read in total (14537ms).
[17:08:55.919] <TB3> INFO: Test took 236818ms.
[17:08:56.084] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:08:56.090] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:08:56.096] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[17:08:56.101] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:08:56.108] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:08:56.114] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[17:08:56.120] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[17:08:56.125] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[17:08:56.131] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[17:08:56.137] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[17:08:56.143] <TB3> INFO: safety margin for low PH: adding 6, margin is now 26
[17:08:56.149] <TB3> INFO: safety margin for low PH: adding 7, margin is now 27
[17:08:56.154] <TB3> INFO: safety margin for low PH: adding 8, margin is now 28
[17:08:56.160] <TB3> INFO: safety margin for low PH: adding 9, margin is now 29
[17:08:56.166] <TB3> INFO: safety margin for low PH: adding 10, margin is now 30
[17:08:56.171] <TB3> INFO: safety margin for low PH: adding 11, margin is now 31
[17:08:56.177] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:08:56.183] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[17:08:56.188] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[17:08:56.194] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[17:08:56.200] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:08:56.206] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:08:56.211] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:08:56.217] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[17:08:56.223] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[17:08:56.229] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[17:08:56.234] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[17:08:56.240] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[17:08:56.246] <TB3> INFO: safety margin for low PH: adding 6, margin is now 26
[17:08:56.252] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:08:56.257] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[17:08:56.263] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[17:08:56.269] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[17:08:56.275] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[17:08:56.281] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[17:08:56.287] <TB3> INFO: safety margin for low PH: adding 6, margin is now 26
[17:08:56.292] <TB3> INFO: safety margin for low PH: adding 7, margin is now 27
[17:08:56.298] <TB3> INFO: safety margin for low PH: adding 8, margin is now 28
[17:08:56.304] <TB3> INFO: safety margin for low PH: adding 9, margin is now 29
[17:08:56.310] <TB3> INFO: safety margin for low PH: adding 10, margin is now 30
[17:08:56.316] <TB3> INFO: safety margin for low PH: adding 11, margin is now 31
[17:08:56.321] <TB3> INFO: safety margin for low PH: adding 12, margin is now 32
[17:08:56.327] <TB3> INFO: safety margin for low PH: adding 13, margin is now 33
[17:08:56.333] <TB3> INFO: safety margin for low PH: adding 14, margin is now 34
[17:08:56.339] <TB3> INFO: safety margin for low PH: adding 15, margin is now 35
[17:08:56.345] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:08:56.351] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[17:08:56.357] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[17:08:56.363] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[17:08:56.369] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[17:08:56.375] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[17:08:56.380] <TB3> INFO: safety margin for low PH: adding 6, margin is now 26
[17:08:56.386] <TB3> INFO: safety margin for low PH: adding 7, margin is now 27
[17:08:56.391] <TB3> INFO: safety margin for low PH: adding 8, margin is now 28
[17:08:56.397] <TB3> INFO: safety margin for low PH: adding 9, margin is now 29
[17:08:56.403] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:08:56.408] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[17:08:56.414] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[17:08:56.419] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:08:56.425] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[17:08:56.431] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[17:08:56.436] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[17:08:56.442] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[17:08:56.447] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[17:08:56.453] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:08:56.458] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:08:56.464] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:08:56.469] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[17:08:56.506] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C0.dat
[17:08:56.506] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C1.dat
[17:08:56.506] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C2.dat
[17:08:56.506] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C3.dat
[17:08:56.507] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C4.dat
[17:08:56.507] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C5.dat
[17:08:56.507] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C6.dat
[17:08:56.507] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C7.dat
[17:08:56.508] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C8.dat
[17:08:56.508] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C9.dat
[17:08:56.509] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C10.dat
[17:08:56.509] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C11.dat
[17:08:56.509] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C12.dat
[17:08:56.509] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C13.dat
[17:08:56.510] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C14.dat
[17:08:56.510] <TB3> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C15.dat
[17:08:56.755] <TB3> INFO: Expecting 41600 events.
[17:08:59.990] <TB3> INFO: 41600 events read in total (2644ms).
[17:08:59.991] <TB3> INFO: Test took 3478ms.
[17:09:00.479] <TB3> INFO: Expecting 41600 events.
[17:09:03.572] <TB3> INFO: 41600 events read in total (2502ms).
[17:09:03.573] <TB3> INFO: Test took 3367ms.
[17:09:04.027] <TB3> INFO: Expecting 41600 events.
[17:09:07.214] <TB3> INFO: 41600 events read in total (2595ms).
[17:09:07.215] <TB3> INFO: Test took 3431ms.
[17:09:07.440] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:07.529] <TB3> INFO: Expecting 2560 events.
[17:09:08.413] <TB3> INFO: 2560 events read in total (292ms).
[17:09:08.413] <TB3> INFO: Test took 973ms.
[17:09:08.415] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:08.724] <TB3> INFO: Expecting 2560 events.
[17:09:09.618] <TB3> INFO: 2560 events read in total (303ms).
[17:09:09.618] <TB3> INFO: Test took 1203ms.
[17:09:09.623] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:09.926] <TB3> INFO: Expecting 2560 events.
[17:09:10.815] <TB3> INFO: 2560 events read in total (297ms).
[17:09:10.816] <TB3> INFO: Test took 1193ms.
[17:09:10.818] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:11.124] <TB3> INFO: Expecting 2560 events.
[17:09:12.010] <TB3> INFO: 2560 events read in total (294ms).
[17:09:12.010] <TB3> INFO: Test took 1192ms.
[17:09:12.013] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:12.318] <TB3> INFO: Expecting 2560 events.
[17:09:13.209] <TB3> INFO: 2560 events read in total (299ms).
[17:09:13.209] <TB3> INFO: Test took 1196ms.
[17:09:13.212] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:13.517] <TB3> INFO: Expecting 2560 events.
[17:09:14.407] <TB3> INFO: 2560 events read in total (298ms).
[17:09:14.408] <TB3> INFO: Test took 1196ms.
[17:09:14.410] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:14.716] <TB3> INFO: Expecting 2560 events.
[17:09:15.606] <TB3> INFO: 2560 events read in total (298ms).
[17:09:15.607] <TB3> INFO: Test took 1197ms.
[17:09:15.609] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:15.914] <TB3> INFO: Expecting 2560 events.
[17:09:16.808] <TB3> INFO: 2560 events read in total (302ms).
[17:09:16.808] <TB3> INFO: Test took 1199ms.
[17:09:16.810] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:17.116] <TB3> INFO: Expecting 2560 events.
[17:09:17.001] <TB3> INFO: 2560 events read in total (293ms).
[17:09:17.002] <TB3> INFO: Test took 1192ms.
[17:09:17.004] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:18.310] <TB3> INFO: Expecting 2560 events.
[17:09:19.193] <TB3> INFO: 2560 events read in total (292ms).
[17:09:19.194] <TB3> INFO: Test took 1190ms.
[17:09:19.196] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:19.501] <TB3> INFO: Expecting 2560 events.
[17:09:20.386] <TB3> INFO: 2560 events read in total (293ms).
[17:09:20.387] <TB3> INFO: Test took 1191ms.
[17:09:20.389] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:20.694] <TB3> INFO: Expecting 2560 events.
[17:09:21.578] <TB3> INFO: 2560 events read in total (292ms).
[17:09:21.578] <TB3> INFO: Test took 1189ms.
[17:09:21.581] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:21.887] <TB3> INFO: Expecting 2560 events.
[17:09:22.772] <TB3> INFO: 2560 events read in total (293ms).
[17:09:22.773] <TB3> INFO: Test took 1192ms.
[17:09:22.776] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:23.081] <TB3> INFO: Expecting 2560 events.
[17:09:23.967] <TB3> INFO: 2560 events read in total (294ms).
[17:09:23.968] <TB3> INFO: Test took 1193ms.
[17:09:23.972] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:24.276] <TB3> INFO: Expecting 2560 events.
[17:09:25.164] <TB3> INFO: 2560 events read in total (296ms).
[17:09:25.164] <TB3> INFO: Test took 1193ms.
[17:09:25.167] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:25.472] <TB3> INFO: Expecting 2560 events.
[17:09:26.358] <TB3> INFO: 2560 events read in total (294ms).
[17:09:26.358] <TB3> INFO: Test took 1191ms.
[17:09:26.362] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:26.667] <TB3> INFO: Expecting 2560 events.
[17:09:27.553] <TB3> INFO: 2560 events read in total (294ms).
[17:09:27.553] <TB3> INFO: Test took 1191ms.
[17:09:27.556] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:27.862] <TB3> INFO: Expecting 2560 events.
[17:09:28.744] <TB3> INFO: 2560 events read in total (291ms).
[17:09:28.744] <TB3> INFO: Test took 1188ms.
[17:09:28.748] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:29.052] <TB3> INFO: Expecting 2560 events.
[17:09:29.936] <TB3> INFO: 2560 events read in total (292ms).
[17:09:29.937] <TB3> INFO: Test took 1189ms.
[17:09:29.940] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:30.245] <TB3> INFO: Expecting 2560 events.
[17:09:31.130] <TB3> INFO: 2560 events read in total (293ms).
[17:09:31.130] <TB3> INFO: Test took 1190ms.
[17:09:31.133] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:31.439] <TB3> INFO: Expecting 2560 events.
[17:09:32.324] <TB3> INFO: 2560 events read in total (293ms).
[17:09:32.325] <TB3> INFO: Test took 1192ms.
[17:09:32.328] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:32.633] <TB3> INFO: Expecting 2560 events.
[17:09:33.518] <TB3> INFO: 2560 events read in total (293ms).
[17:09:33.518] <TB3> INFO: Test took 1191ms.
[17:09:33.522] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:33.827] <TB3> INFO: Expecting 2560 events.
[17:09:34.712] <TB3> INFO: 2560 events read in total (293ms).
[17:09:34.712] <TB3> INFO: Test took 1190ms.
[17:09:34.715] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:35.021] <TB3> INFO: Expecting 2560 events.
[17:09:35.906] <TB3> INFO: 2560 events read in total (293ms).
[17:09:35.906] <TB3> INFO: Test took 1192ms.
[17:09:35.909] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:36.214] <TB3> INFO: Expecting 2560 events.
[17:09:37.110] <TB3> INFO: 2560 events read in total (304ms).
[17:09:37.110] <TB3> INFO: Test took 1201ms.
[17:09:37.115] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:37.419] <TB3> INFO: Expecting 2560 events.
[17:09:38.313] <TB3> INFO: 2560 events read in total (302ms).
[17:09:38.313] <TB3> INFO: Test took 1199ms.
[17:09:38.316] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:38.621] <TB3> INFO: Expecting 2560 events.
[17:09:39.512] <TB3> INFO: 2560 events read in total (299ms).
[17:09:39.512] <TB3> INFO: Test took 1196ms.
[17:09:39.515] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:39.820] <TB3> INFO: Expecting 2560 events.
[17:09:40.710] <TB3> INFO: 2560 events read in total (298ms).
[17:09:40.710] <TB3> INFO: Test took 1195ms.
[17:09:40.713] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:41.019] <TB3> INFO: Expecting 2560 events.
[17:09:41.908] <TB3> INFO: 2560 events read in total (297ms).
[17:09:41.908] <TB3> INFO: Test took 1195ms.
[17:09:41.910] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:42.217] <TB3> INFO: Expecting 2560 events.
[17:09:43.106] <TB3> INFO: 2560 events read in total (298ms).
[17:09:43.106] <TB3> INFO: Test took 1196ms.
[17:09:43.110] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:43.415] <TB3> INFO: Expecting 2560 events.
[17:09:44.306] <TB3> INFO: 2560 events read in total (299ms).
[17:09:44.307] <TB3> INFO: Test took 1197ms.
[17:09:44.310] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:09:44.615] <TB3> INFO: Expecting 2560 events.
[17:09:45.504] <TB3> INFO: 2560 events read in total (298ms).
[17:09:45.505] <TB3> INFO: Test took 1195ms.
[17:09:45.970] <TB3> INFO: PixTestPhOptimization::doTest() done, duration: 756 seconds
[17:09:45.970] <TB3> INFO: PH scale (per ROC): 35 37 36 34 64 47 43 44 48 37 33 48 44 41 32 32
[17:09:45.970] <TB3> INFO: PH offset (per ROC): 102 81 113 86 137 130 141 142 113 141 102 130 118 149 114 100
[17:09:45.979] <TB3> INFO: Decoding statistics:
[17:09:45.979] <TB3> INFO: General information:
[17:09:45.979] <TB3> INFO: 16bit words read: 127880
[17:09:45.979] <TB3> INFO: valid events total: 20480
[17:09:45.979] <TB3> INFO: empty events: 17980
[17:09:45.979] <TB3> INFO: valid events with pixels: 2500
[17:09:45.979] <TB3> INFO: valid pixel hits: 2500
[17:09:45.979] <TB3> INFO: Event errors: 0
[17:09:45.979] <TB3> INFO: start marker: 0
[17:09:45.979] <TB3> INFO: stop marker: 0
[17:09:45.979] <TB3> INFO: overflow: 0
[17:09:45.979] <TB3> INFO: invalid 5bit words: 0
[17:09:45.979] <TB3> INFO: invalid XOR eye diagram: 0
[17:09:45.979] <TB3> INFO: frame (failed synchr.): 0
[17:09:45.979] <TB3> INFO: idle data (no TBM trl): 0
[17:09:45.979] <TB3> INFO: no data (only TBM hdr): 0
[17:09:45.979] <TB3> INFO: TBM errors: 0
[17:09:45.979] <TB3> INFO: flawed TBM headers: 0
[17:09:45.979] <TB3> INFO: flawed TBM trailers: 0
[17:09:45.979] <TB3> INFO: event ID mismatches: 0
[17:09:45.979] <TB3> INFO: ROC errors: 0
[17:09:45.979] <TB3> INFO: missing ROC header(s): 0
[17:09:45.979] <TB3> INFO: misplaced readback start: 0
[17:09:45.979] <TB3> INFO: Pixel decoding errors: 0
[17:09:45.979] <TB3> INFO: pixel data incomplete: 0
[17:09:45.979] <TB3> INFO: pixel address: 0
[17:09:45.979] <TB3> INFO: pulse height fill bit: 0
[17:09:45.979] <TB3> INFO: buffer corruption: 0
[17:09:46.214] <TB3> INFO: ######################################################################
[17:09:46.214] <TB3> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[17:09:46.214] <TB3> INFO: ######################################################################
[17:09:46.228] <TB3> INFO: scanning low vcal = 10
[17:09:46.465] <TB3> INFO: Expecting 41600 events.
[17:09:50.099] <TB3> INFO: 41600 events read in total (3042ms).
[17:09:50.099] <TB3> INFO: Test took 3871ms.
[17:09:50.101] <TB3> INFO: scanning low vcal = 20
[17:09:50.396] <TB3> INFO: Expecting 41600 events.
[17:09:53.981] <TB3> INFO: 41600 events read in total (2993ms).
[17:09:53.982] <TB3> INFO: Test took 3880ms.
[17:09:53.984] <TB3> INFO: scanning low vcal = 30
[17:09:54.282] <TB3> INFO: Expecting 41600 events.
[17:09:57.991] <TB3> INFO: 41600 events read in total (3118ms).
[17:09:57.992] <TB3> INFO: Test took 4008ms.
[17:09:57.994] <TB3> INFO: scanning low vcal = 40
[17:09:58.271] <TB3> INFO: Expecting 41600 events.
[17:10:02.284] <TB3> INFO: 41600 events read in total (3421ms).
[17:10:02.285] <TB3> INFO: Test took 4291ms.
[17:10:02.288] <TB3> INFO: scanning low vcal = 50
[17:10:02.588] <TB3> INFO: Expecting 41600 events.
[17:10:06.622] <TB3> INFO: 41600 events read in total (3443ms).
[17:10:06.623] <TB3> INFO: Test took 4334ms.
[17:10:06.626] <TB3> INFO: scanning low vcal = 60
[17:10:06.925] <TB3> INFO: Expecting 41600 events.
[17:10:10.967] <TB3> INFO: 41600 events read in total (3450ms).
[17:10:10.968] <TB3> INFO: Test took 4342ms.
[17:10:10.971] <TB3> INFO: scanning low vcal = 70
[17:10:11.248] <TB3> INFO: Expecting 41600 events.
[17:10:15.279] <TB3> INFO: 41600 events read in total (3439ms).
[17:10:15.279] <TB3> INFO: Test took 4307ms.
[17:10:15.283] <TB3> INFO: scanning low vcal = 80
[17:10:15.583] <TB3> INFO: Expecting 41600 events.
[17:10:19.568] <TB3> INFO: 41600 events read in total (3394ms).
[17:10:19.569] <TB3> INFO: Test took 4285ms.
[17:10:19.572] <TB3> INFO: scanning low vcal = 90
[17:10:19.848] <TB3> INFO: Expecting 41600 events.
[17:10:23.881] <TB3> INFO: 41600 events read in total (3441ms).
[17:10:23.882] <TB3> INFO: Test took 4310ms.
[17:10:23.886] <TB3> INFO: scanning low vcal = 100
[17:10:24.161] <TB3> INFO: Expecting 41600 events.
[17:10:28.156] <TB3> INFO: 41600 events read in total (3403ms).
[17:10:28.157] <TB3> INFO: Test took 4271ms.
[17:10:28.160] <TB3> INFO: scanning low vcal = 110
[17:10:28.436] <TB3> INFO: Expecting 41600 events.
[17:10:32.538] <TB3> INFO: 41600 events read in total (3510ms).
[17:10:32.539] <TB3> INFO: Test took 4379ms.
[17:10:32.542] <TB3> INFO: scanning low vcal = 120
[17:10:32.819] <TB3> INFO: Expecting 41600 events.
[17:10:36.886] <TB3> INFO: 41600 events read in total (3476ms).
[17:10:36.887] <TB3> INFO: Test took 4345ms.
[17:10:36.889] <TB3> INFO: scanning low vcal = 130
[17:10:37.189] <TB3> INFO: Expecting 41600 events.
[17:10:41.204] <TB3> INFO: 41600 events read in total (3423ms).
[17:10:41.205] <TB3> INFO: Test took 4315ms.
[17:10:41.208] <TB3> INFO: scanning low vcal = 140
[17:10:41.485] <TB3> INFO: Expecting 41600 events.
[17:10:45.483] <TB3> INFO: 41600 events read in total (3407ms).
[17:10:45.484] <TB3> INFO: Test took 4276ms.
[17:10:45.487] <TB3> INFO: scanning low vcal = 150
[17:10:45.764] <TB3> INFO: Expecting 41600 events.
[17:10:49.815] <TB3> INFO: 41600 events read in total (3460ms).
[17:10:49.816] <TB3> INFO: Test took 4329ms.
[17:10:49.819] <TB3> INFO: scanning low vcal = 160
[17:10:50.096] <TB3> INFO: Expecting 41600 events.
[17:10:54.135] <TB3> INFO: 41600 events read in total (3448ms).
[17:10:54.136] <TB3> INFO: Test took 4317ms.
[17:10:54.139] <TB3> INFO: scanning low vcal = 170
[17:10:54.415] <TB3> INFO: Expecting 41600 events.
[17:10:58.473] <TB3> INFO: 41600 events read in total (3466ms).
[17:10:58.474] <TB3> INFO: Test took 4335ms.
[17:10:58.479] <TB3> INFO: scanning low vcal = 180
[17:10:58.754] <TB3> INFO: Expecting 41600 events.
[17:11:02.757] <TB3> INFO: 41600 events read in total (3412ms).
[17:11:02.758] <TB3> INFO: Test took 4279ms.
[17:11:02.761] <TB3> INFO: scanning low vcal = 190
[17:11:03.038] <TB3> INFO: Expecting 41600 events.
[17:11:07.062] <TB3> INFO: 41600 events read in total (3433ms).
[17:11:07.063] <TB3> INFO: Test took 4302ms.
[17:11:07.066] <TB3> INFO: scanning low vcal = 200
[17:11:07.366] <TB3> INFO: Expecting 41600 events.
[17:11:11.411] <TB3> INFO: 41600 events read in total (3453ms).
[17:11:11.412] <TB3> INFO: Test took 4346ms.
[17:11:11.415] <TB3> INFO: scanning low vcal = 210
[17:11:11.692] <TB3> INFO: Expecting 41600 events.
[17:11:15.686] <TB3> INFO: 41600 events read in total (3403ms).
[17:11:15.686] <TB3> INFO: Test took 4271ms.
[17:11:15.689] <TB3> INFO: scanning low vcal = 220
[17:11:15.989] <TB3> INFO: Expecting 41600 events.
[17:11:19.955] <TB3> INFO: 41600 events read in total (3374ms).
[17:11:19.956] <TB3> INFO: Test took 4266ms.
[17:11:19.959] <TB3> INFO: scanning low vcal = 230
[17:11:20.235] <TB3> INFO: Expecting 41600 events.
[17:11:24.221] <TB3> INFO: 41600 events read in total (3394ms).
[17:11:24.222] <TB3> INFO: Test took 4263ms.
[17:11:24.225] <TB3> INFO: scanning low vcal = 240
[17:11:24.501] <TB3> INFO: Expecting 41600 events.
[17:11:28.462] <TB3> INFO: 41600 events read in total (3369ms).
[17:11:28.463] <TB3> INFO: Test took 4238ms.
[17:11:28.467] <TB3> INFO: scanning low vcal = 250
[17:11:28.743] <TB3> INFO: Expecting 41600 events.
[17:11:32.783] <TB3> INFO: 41600 events read in total (3448ms).
[17:11:32.784] <TB3> INFO: Test took 4317ms.
[17:11:32.789] <TB3> INFO: scanning high vcal = 30 (= 210 in low range)
[17:11:33.064] <TB3> INFO: Expecting 41600 events.
[17:11:37.117] <TB3> INFO: 41600 events read in total (3461ms).
[17:11:37.118] <TB3> INFO: Test took 4329ms.
[17:11:37.121] <TB3> INFO: scanning high vcal = 50 (= 350 in low range)
[17:11:37.398] <TB3> INFO: Expecting 41600 events.
[17:11:41.401] <TB3> INFO: 41600 events read in total (3412ms).
[17:11:41.402] <TB3> INFO: Test took 4281ms.
[17:11:41.405] <TB3> INFO: scanning high vcal = 70 (= 490 in low range)
[17:11:41.704] <TB3> INFO: Expecting 41600 events.
[17:11:45.665] <TB3> INFO: 41600 events read in total (3369ms).
[17:11:45.666] <TB3> INFO: Test took 4261ms.
[17:11:45.670] <TB3> INFO: scanning high vcal = 90 (= 630 in low range)
[17:11:45.969] <TB3> INFO: Expecting 41600 events.
[17:11:49.998] <TB3> INFO: 41600 events read in total (3438ms).
[17:11:49.999] <TB3> INFO: Test took 4329ms.
[17:11:49.002] <TB3> INFO: scanning high vcal = 200 (= 1400 in low range)
[17:11:50.318] <TB3> INFO: Expecting 41600 events.
[17:11:54.340] <TB3> INFO: 41600 events read in total (3430ms).
[17:11:54.341] <TB3> INFO: Test took 4339ms.
[17:11:54.753] <TB3> INFO: PixTestGainPedestal::measure() done
[17:12:29.330] <TB3> INFO: PixTestGainPedestal::fit() done
[17:12:29.330] <TB3> INFO: non-linearity mean: 0.977 1.013 0.935 1.036 0.978 0.973 0.965 0.962 0.937 0.963 0.921 0.975 0.972 0.969 0.925 0.910
[17:12:29.330] <TB3> INFO: non-linearity RMS: 0.187 0.172 0.054 0.166 0.004 0.003 0.005 0.006 0.051 0.007 0.141 0.003 0.004 0.007 0.102 0.108
[17:12:29.330] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[17:12:29.346] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[17:12:29.361] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[17:12:29.375] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[17:12:29.389] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[17:12:29.404] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[17:12:29.418] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[17:12:29.432] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[17:12:29.447] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[17:12:29.461] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[17:12:29.475] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[17:12:29.489] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[17:12:29.505] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[17:12:29.530] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[17:12:29.554] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[17:12:29.579] <TB3> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1051_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[17:12:29.604] <TB3> INFO: PixTestGainPedestal::fullTest() done, duration: 163 seconds
[17:12:29.604] <TB3> INFO: Decoding statistics:
[17:12:29.604] <TB3> INFO: General information:
[17:12:29.604] <TB3> INFO: 16bit words read: 3326754
[17:12:29.604] <TB3> INFO: valid events total: 332800
[17:12:29.604] <TB3> INFO: empty events: 0
[17:12:29.604] <TB3> INFO: valid events with pixels: 332800
[17:12:29.604] <TB3> INFO: valid pixel hits: 664977
[17:12:29.604] <TB3> INFO: Event errors: 0
[17:12:29.604] <TB3> INFO: start marker: 0
[17:12:29.604] <TB3> INFO: stop marker: 0
[17:12:29.604] <TB3> INFO: overflow: 0
[17:12:29.604] <TB3> INFO: invalid 5bit words: 0
[17:12:29.604] <TB3> INFO: invalid XOR eye diagram: 0
[17:12:29.604] <TB3> INFO: frame (failed synchr.): 0
[17:12:29.604] <TB3> INFO: idle data (no TBM trl): 0
[17:12:29.604] <TB3> INFO: no data (only TBM hdr): 0
[17:12:29.604] <TB3> INFO: TBM errors: 0
[17:12:29.604] <TB3> INFO: flawed TBM headers: 0
[17:12:29.604] <TB3> INFO: flawed TBM trailers: 0
[17:12:29.604] <TB3> INFO: event ID mismatches: 0
[17:12:29.604] <TB3> INFO: ROC errors: 0
[17:12:29.604] <TB3> INFO: missing ROC header(s): 0
[17:12:29.604] <TB3> INFO: misplaced readback start: 0
[17:12:29.604] <TB3> INFO: Pixel decoding errors: 0
[17:12:29.604] <TB3> INFO: pixel data incomplete: 0
[17:12:29.604] <TB3> INFO: pixel address: 0
[17:12:29.604] <TB3> INFO: pulse height fill bit: 0
[17:12:29.604] <TB3> INFO: buffer corruption: 0
[17:12:29.630] <TB3> INFO: Decoding statistics:
[17:12:29.630] <TB3> INFO: General information:
[17:12:29.630] <TB3> INFO: 16bit words read: 3456170
[17:12:29.630] <TB3> INFO: valid events total: 353536
[17:12:29.630] <TB3> INFO: empty events: 18236
[17:12:29.630] <TB3> INFO: valid events with pixels: 335300
[17:12:29.630] <TB3> INFO: valid pixel hits: 667477
[17:12:29.630] <TB3> INFO: Event errors: 0
[17:12:29.630] <TB3> INFO: start marker: 0
[17:12:29.630] <TB3> INFO: stop marker: 0
[17:12:29.630] <TB3> INFO: overflow: 0
[17:12:29.630] <TB3> INFO: invalid 5bit words: 0
[17:12:29.630] <TB3> INFO: invalid XOR eye diagram: 0
[17:12:29.630] <TB3> INFO: frame (failed synchr.): 0
[17:12:29.630] <TB3> INFO: idle data (no TBM trl): 0
[17:12:29.630] <TB3> INFO: no data (only TBM hdr): 0
[17:12:29.630] <TB3> INFO: TBM errors: 0
[17:12:29.630] <TB3> INFO: flawed TBM headers: 0
[17:12:29.630] <TB3> INFO: flawed TBM trailers: 0
[17:12:29.630] <TB3> INFO: event ID mismatches: 0
[17:12:29.630] <TB3> INFO: ROC errors: 0
[17:12:29.630] <TB3> INFO: missing ROC header(s): 0
[17:12:29.630] <TB3> INFO: misplaced readback start: 0
[17:12:29.630] <TB3> INFO: Pixel decoding errors: 0
[17:12:29.630] <TB3> INFO: pixel data incomplete: 0
[17:12:29.630] <TB3> INFO: pixel address: 0
[17:12:29.630] <TB3> INFO: pulse height fill bit: 0
[17:12:29.630] <TB3> INFO: buffer corruption: 0
[17:12:29.630] <TB3> INFO: enter test to run
[17:12:29.630] <TB3> INFO: test: exit no parameter change
[17:12:29.797] <TB3> QUIET: Connection to board 126 closed.
[17:12:29.797] <TB3> INFO: pXar: this is the end, my friend