[09:51:53.653] <TB2> INFO: *** Welcome to pxar ***
[09:51:53.653] <TB2> INFO: *** Today: 2016/10/24
[09:51:53.662] <TB2> INFO: *** Version: c8ba-dirty
[09:51:53.662] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C15.dat
[09:51:53.662] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//tbmParameters_C1b.dat
[09:51:53.662] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//defaultMaskFile.dat
[09:51:53.662] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters_C15.dat
[09:51:53.726] <TB2> INFO: clk: 4
[09:51:53.726] <TB2> INFO: ctr: 4
[09:51:53.726] <TB2> INFO: sda: 19
[09:51:53.726] <TB2> INFO: tin: 9
[09:51:53.726] <TB2> INFO: level: 15
[09:51:53.726] <TB2> INFO: triggerdelay: 0
[09:51:53.726] <TB2> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[09:51:53.726] <TB2> INFO: Log level: INFO
[09:51:53.732] <TB2> INFO: Found DTB DTB_WWXUD2
[09:51:53.740] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[09:51:53.742] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[09:51:53.744] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[09:51:55.235] <TB2> INFO: DUT info:
[09:51:55.235] <TB2> INFO: The DUT currently contains the following objects:
[09:51:55.235] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[09:51:55.235] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:51:55.235] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:51:55.235] <TB2> INFO: TBM Core alpha (2): 7 registers set
[09:51:55.235] <TB2> INFO: TBM Core beta (3): 7 registers set
[09:51:55.235] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[09:51:55.235] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[09:51:55.235] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[09:51:55.235] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[09:51:55.236] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[09:51:55.236] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[09:51:55.236] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[09:51:55.236] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[09:51:55.236] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[09:51:55.236] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[09:51:55.236] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[09:51:55.236] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[09:51:55.236] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[09:51:55.236] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[09:51:55.236] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[09:51:55.236] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[09:51:55.236] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[09:51:55.637] <TB2> INFO: enter 'restricted' command line mode
[09:51:55.637] <TB2> INFO: enter test to run
[09:51:55.637] <TB2> INFO: test: pretest no parameter change
[09:51:55.637] <TB2> INFO: running: pretest
[09:51:55.642] <TB2> INFO: ######################################################################
[09:51:55.642] <TB2> INFO: PixTestPretest::doTest()
[09:51:55.642] <TB2> INFO: ######################################################################
[09:51:55.643] <TB2> INFO: ----------------------------------------------------------------------
[09:51:55.643] <TB2> INFO: PixTestPretest::programROC()
[09:51:55.643] <TB2> INFO: ----------------------------------------------------------------------
[09:52:13.656] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[09:52:13.656] <TB2> INFO: IA differences per ROC: 18.5 20.9 18.5 18.5 18.5 18.5 19.3 19.3 20.1 19.3 19.3 20.1 20.9 20.1 19.3 18.5
[09:52:13.730] <TB2> INFO: ----------------------------------------------------------------------
[09:52:13.730] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[09:52:13.730] <TB2> INFO: ----------------------------------------------------------------------
[09:52:21.420] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 390.7 mA = 24.4187 mA/ROC
[09:52:21.420] <TB2> INFO: i(loss) [mA/ROC]: 19.3 20.1 20.1 19.3 19.3 20.1 19.3 19.3 19.3 19.3 19.3 19.3 20.1 20.1 19.3 20.1
[09:52:21.454] <TB2> INFO: ----------------------------------------------------------------------
[09:52:21.455] <TB2> INFO: PixTestPretest::findTiming()
[09:52:21.455] <TB2> INFO: ----------------------------------------------------------------------
[09:52:21.455] <TB2> INFO: PixTestCmd::init()

[09:52:53.071] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[09:52:53.071] <TB2> INFO: (success/tries = 100/100), width = 4
[09:52:54.577] <TB2> INFO: ----------------------------------------------------------------------
[09:52:54.577] <TB2> INFO: PixTestPretest::findWorkingPixel()
[09:52:54.577] <TB2> INFO: ----------------------------------------------------------------------
[09:52:54.671] <TB2> INFO: Expecting 231680 events.
[09:53:04.681] <TB2> INFO: 231680 events read in total (9418ms).
[09:53:04.689] <TB2> INFO: Test took 10108ms.
[09:53:04.937] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[09:53:04.970] <TB2> INFO: ----------------------------------------------------------------------
[09:53:04.970] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[09:53:04.970] <TB2> INFO: ----------------------------------------------------------------------
[09:53:05.065] <TB2> INFO: Expecting 231680 events.
[09:53:15.129] <TB2> INFO: 231680 events read in total (9473ms).
[09:53:15.141] <TB2> INFO: Test took 10165ms.
[09:53:15.401] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[09:53:15.401] <TB2> INFO: CalDel: 78 102 101 72 88 98 80 101 84 95 95 102 103 109 83 79
[09:53:15.401] <TB2> INFO: VthrComp: 51 53 51 51 51 51 51 51 60 51 53 51 51 51 53 55
[09:53:15.404] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C0.dat
[09:53:15.404] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C1.dat
[09:53:15.404] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C2.dat
[09:53:15.404] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C3.dat
[09:53:15.404] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C4.dat
[09:53:15.404] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C5.dat
[09:53:15.404] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C6.dat
[09:53:15.404] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C7.dat
[09:53:15.405] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C8.dat
[09:53:15.405] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C9.dat
[09:53:15.405] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C10.dat
[09:53:15.405] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C11.dat
[09:53:15.405] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C12.dat
[09:53:15.405] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C13.dat
[09:53:15.405] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C14.dat
[09:53:15.405] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters_C15.dat
[09:53:15.405] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//tbmParameters_C0a.dat
[09:53:15.405] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//tbmParameters_C0b.dat
[09:53:15.405] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//tbmParameters_C1a.dat
[09:53:15.405] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//tbmParameters_C1b.dat
[09:53:15.405] <TB2> INFO: PixTestPretest::doTest() done, duration: 79 seconds
[09:53:15.457] <TB2> INFO: enter test to run
[09:53:15.457] <TB2> INFO: test: FullTest no parameter change
[09:53:15.457] <TB2> INFO: running: fulltest
[09:53:15.457] <TB2> INFO: ######################################################################
[09:53:15.457] <TB2> INFO: PixTestFullTest::doTest()
[09:53:15.457] <TB2> INFO: ######################################################################
[09:53:15.458] <TB2> INFO: ######################################################################
[09:53:15.458] <TB2> INFO: PixTestAlive::doTest()
[09:53:15.458] <TB2> INFO: ######################################################################
[09:53:15.459] <TB2> INFO: ----------------------------------------------------------------------
[09:53:15.459] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:53:15.459] <TB2> INFO: ----------------------------------------------------------------------
[09:53:15.757] <TB2> INFO: Expecting 41600 events.
[09:53:19.243] <TB2> INFO: 41600 events read in total (2894ms).
[09:53:19.244] <TB2> INFO: Test took 3783ms.
[09:53:19.472] <TB2> INFO: PixTestAlive::aliveTest() done
[09:53:19.472] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:53:19.473] <TB2> INFO: ----------------------------------------------------------------------
[09:53:19.473] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:53:19.473] <TB2> INFO: ----------------------------------------------------------------------
[09:53:19.714] <TB2> INFO: Expecting 41600 events.
[09:53:22.664] <TB2> INFO: 41600 events read in total (2358ms).
[09:53:22.665] <TB2> INFO: Test took 3190ms.
[09:53:22.665] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[09:53:22.902] <TB2> INFO: PixTestAlive::maskTest() done
[09:53:22.902] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:53:22.904] <TB2> INFO: ----------------------------------------------------------------------
[09:53:22.904] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:53:22.904] <TB2> INFO: ----------------------------------------------------------------------
[09:53:23.146] <TB2> INFO: Expecting 41600 events.
[09:53:26.672] <TB2> INFO: 41600 events read in total (2935ms).
[09:53:26.672] <TB2> INFO: Test took 3766ms.
[09:53:26.907] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[09:53:26.907] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:53:26.908] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[09:53:26.908] <TB2> INFO: Decoding statistics:
[09:53:26.908] <TB2> INFO: General information:
[09:53:26.908] <TB2> INFO: 16bit words read: 0
[09:53:26.908] <TB2> INFO: valid events total: 0
[09:53:26.908] <TB2> INFO: empty events: 0
[09:53:26.908] <TB2> INFO: valid events with pixels: 0
[09:53:26.908] <TB2> INFO: valid pixel hits: 0
[09:53:26.908] <TB2> INFO: Event errors: 0
[09:53:26.908] <TB2> INFO: start marker: 0
[09:53:26.908] <TB2> INFO: stop marker: 0
[09:53:26.908] <TB2> INFO: overflow: 0
[09:53:26.908] <TB2> INFO: invalid 5bit words: 0
[09:53:26.908] <TB2> INFO: invalid XOR eye diagram: 0
[09:53:26.908] <TB2> INFO: frame (failed synchr.): 0
[09:53:26.908] <TB2> INFO: idle data (no TBM trl): 0
[09:53:26.908] <TB2> INFO: no data (only TBM hdr): 0
[09:53:26.908] <TB2> INFO: TBM errors: 0
[09:53:26.908] <TB2> INFO: flawed TBM headers: 0
[09:53:26.908] <TB2> INFO: flawed TBM trailers: 0
[09:53:26.908] <TB2> INFO: event ID mismatches: 0
[09:53:26.908] <TB2> INFO: ROC errors: 0
[09:53:26.908] <TB2> INFO: missing ROC header(s): 0
[09:53:26.908] <TB2> INFO: misplaced readback start: 0
[09:53:26.908] <TB2> INFO: Pixel decoding errors: 0
[09:53:26.908] <TB2> INFO: pixel data incomplete: 0
[09:53:26.908] <TB2> INFO: pixel address: 0
[09:53:26.908] <TB2> INFO: pulse height fill bit: 0
[09:53:26.908] <TB2> INFO: buffer corruption: 0
[09:53:26.915] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C15.dat
[09:53:26.916] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr_C15.dat

[09:53:26.916] <TB2> INFO: ######################################################################
[09:53:26.916] <TB2> INFO: PixTestReadback::doTest()
[09:53:26.916] <TB2> INFO: ######################################################################
[09:53:26.916] <TB2> INFO: ----------------------------------------------------------------------
[09:53:26.916] <TB2> INFO: PixTestReadback::CalibrateVd()
[09:53:26.916] <TB2> INFO: ----------------------------------------------------------------------
[09:53:36.856] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C0.dat
[09:53:36.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C1.dat
[09:53:36.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C2.dat
[09:53:36.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C3.dat
[09:53:36.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C4.dat
[09:53:36.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C5.dat
[09:53:36.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C6.dat
[09:53:36.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C7.dat
[09:53:36.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C8.dat
[09:53:36.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C9.dat
[09:53:36.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C10.dat
[09:53:36.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C11.dat
[09:53:36.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C12.dat
[09:53:36.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C13.dat
[09:53:36.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C14.dat
[09:53:36.857] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C15.dat
[09:53:36.885] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[09:53:36.885] <TB2> INFO: ----------------------------------------------------------------------
[09:53:36.885] <TB2> INFO: PixTestReadback::CalibrateVa()
[09:53:36.886] <TB2> INFO: ----------------------------------------------------------------------
[09:53:46.788] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C0.dat
[09:53:46.788] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C1.dat
[09:53:46.788] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C2.dat
[09:53:46.788] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C3.dat
[09:53:46.788] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C4.dat
[09:53:46.788] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C5.dat
[09:53:46.788] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C6.dat
[09:53:46.789] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C7.dat
[09:53:46.789] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C8.dat
[09:53:46.789] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C9.dat
[09:53:46.789] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C10.dat
[09:53:46.789] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C11.dat
[09:53:46.789] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C12.dat
[09:53:46.789] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C13.dat
[09:53:46.789] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C14.dat
[09:53:46.789] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C15.dat
[09:53:46.819] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[09:53:46.819] <TB2> INFO: ----------------------------------------------------------------------
[09:53:46.819] <TB2> INFO: PixTestReadback::readbackVbg()
[09:53:46.819] <TB2> INFO: ----------------------------------------------------------------------
[09:53:54.467] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[09:53:54.467] <TB2> INFO: ----------------------------------------------------------------------
[09:53:54.467] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[09:53:54.467] <TB2> INFO: ----------------------------------------------------------------------
[09:53:54.467] <TB2> INFO: Vbg will be calibrated using Vd calibration
[09:53:54.467] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 159.8calibrated Vbg = 1.19129 :::*/*/*/*/
[09:53:54.467] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 164.7calibrated Vbg = 1.19523 :::*/*/*/*/
[09:53:54.467] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 159calibrated Vbg = 1.19272 :::*/*/*/*/
[09:53:54.467] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 151.7calibrated Vbg = 1.19201 :::*/*/*/*/
[09:53:54.467] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 154.4calibrated Vbg = 1.19212 :::*/*/*/*/
[09:53:54.467] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 155.3calibrated Vbg = 1.19856 :::*/*/*/*/
[09:53:54.467] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 155.1calibrated Vbg = 1.20001 :::*/*/*/*/
[09:53:54.467] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 152.5calibrated Vbg = 1.19766 :::*/*/*/*/
[09:53:54.467] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 156.4calibrated Vbg = 1.18612 :::*/*/*/*/
[09:53:54.467] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 156.1calibrated Vbg = 1.18657 :::*/*/*/*/
[09:53:54.467] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 154.6calibrated Vbg = 1.18753 :::*/*/*/*/
[09:53:54.467] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 162.1calibrated Vbg = 1.18285 :::*/*/*/*/
[09:53:54.467] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 150calibrated Vbg = 1.19218 :::*/*/*/*/
[09:53:54.467] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 156.8calibrated Vbg = 1.195 :::*/*/*/*/
[09:53:54.468] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 155.7calibrated Vbg = 1.19389 :::*/*/*/*/
[09:53:54.468] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 155calibrated Vbg = 1.1943 :::*/*/*/*/
[09:53:54.470] <TB2> INFO: ----------------------------------------------------------------------
[09:53:54.470] <TB2> INFO: PixTestReadback::CalibrateIa()
[09:53:54.470] <TB2> INFO: ----------------------------------------------------------------------
[09:56:34.948] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C0.dat
[09:56:34.948] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C1.dat
[09:56:34.948] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C2.dat
[09:56:34.948] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C3.dat
[09:56:34.948] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C4.dat
[09:56:34.948] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C5.dat
[09:56:34.948] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C6.dat
[09:56:34.948] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C7.dat
[09:56:34.948] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C8.dat
[09:56:34.949] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C9.dat
[09:56:34.949] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C10.dat
[09:56:34.949] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C11.dat
[09:56:34.949] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C12.dat
[09:56:34.949] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C13.dat
[09:56:34.949] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C14.dat
[09:56:34.949] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//readbackCal_C15.dat
[09:56:34.976] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[09:56:34.978] <TB2> INFO: PixTestReadback::doTest() done
[09:56:34.978] <TB2> INFO: Decoding statistics:
[09:56:34.978] <TB2> INFO: General information:
[09:56:34.978] <TB2> INFO: 16bit words read: 1536
[09:56:34.978] <TB2> INFO: valid events total: 256
[09:56:34.978] <TB2> INFO: empty events: 256
[09:56:34.978] <TB2> INFO: valid events with pixels: 0
[09:56:34.978] <TB2> INFO: valid pixel hits: 0
[09:56:34.978] <TB2> INFO: Event errors: 0
[09:56:34.978] <TB2> INFO: start marker: 0
[09:56:34.978] <TB2> INFO: stop marker: 0
[09:56:34.978] <TB2> INFO: overflow: 0
[09:56:34.978] <TB2> INFO: invalid 5bit words: 0
[09:56:34.978] <TB2> INFO: invalid XOR eye diagram: 0
[09:56:34.978] <TB2> INFO: frame (failed synchr.): 0
[09:56:34.978] <TB2> INFO: idle data (no TBM trl): 0
[09:56:34.978] <TB2> INFO: no data (only TBM hdr): 0
[09:56:34.978] <TB2> INFO: TBM errors: 0
[09:56:34.978] <TB2> INFO: flawed TBM headers: 0
[09:56:34.978] <TB2> INFO: flawed TBM trailers: 0
[09:56:34.978] <TB2> INFO: event ID mismatches: 0
[09:56:34.978] <TB2> INFO: ROC errors: 0
[09:56:34.978] <TB2> INFO: missing ROC header(s): 0
[09:56:34.978] <TB2> INFO: misplaced readback start: 0
[09:56:34.978] <TB2> INFO: Pixel decoding errors: 0
[09:56:34.978] <TB2> INFO: pixel data incomplete: 0
[09:56:34.978] <TB2> INFO: pixel address: 0
[09:56:34.978] <TB2> INFO: pulse height fill bit: 0
[09:56:34.978] <TB2> INFO: buffer corruption: 0
[09:56:35.045] <TB2> INFO: ######################################################################
[09:56:35.045] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[09:56:35.045] <TB2> INFO: ######################################################################
[09:56:35.048] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[09:56:35.061] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[09:56:35.061] <TB2> INFO: run 1 of 1
[09:56:35.296] <TB2> INFO: Expecting 3120000 events.
[09:57:07.654] <TB2> INFO: 678525 events read in total (31766ms).




















[09:57:38.647] <TB2> INFO: 1353885 events read in total (62759ms).




















[09:58:09.393] <TB2> INFO: 2025775 events read in total (93505ms).











[09:58:40.695] <TB2> INFO: 2698470 events read in total (124807ms).











[09:59:00.239] <TB2> INFO: 3120000 events read in total (144351ms).
[09:59:00.303] <TB2> INFO: Test took 145243ms.
[09:59:21.731] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 166 seconds
[09:59:21.731] <TB2> INFO: number of dead bumps (per ROC): 0 0 1 0 0 2 0 0 0 4 0 1 0 0 2 1
[09:59:21.731] <TB2> INFO: separation cut (per ROC): 107 111 108 106 112 103 107 108 120 107 125 118 106 105 110 111
[09:59:21.731] <TB2> INFO: Decoding statistics:
[09:59:21.731] <TB2> INFO: General information:
[09:59:21.731] <TB2> INFO: 16bit words read: 0
[09:59:21.731] <TB2> INFO: valid events total: 0
[09:59:21.731] <TB2> INFO: empty events: 0
[09:59:21.731] <TB2> INFO: valid events with pixels: 0
[09:59:21.731] <TB2> INFO: valid pixel hits: 0
[09:59:21.731] <TB2> INFO: Event errors: 0
[09:59:21.731] <TB2> INFO: start marker: 0
[09:59:21.731] <TB2> INFO: stop marker: 0
[09:59:21.731] <TB2> INFO: overflow: 0
[09:59:21.731] <TB2> INFO: invalid 5bit words: 0
[09:59:21.731] <TB2> INFO: invalid XOR eye diagram: 0
[09:59:21.731] <TB2> INFO: frame (failed synchr.): 0
[09:59:21.731] <TB2> INFO: idle data (no TBM trl): 0
[09:59:21.731] <TB2> INFO: no data (only TBM hdr): 0
[09:59:21.731] <TB2> INFO: TBM errors: 0
[09:59:21.731] <TB2> INFO: flawed TBM headers: 0
[09:59:21.731] <TB2> INFO: flawed TBM trailers: 0
[09:59:21.731] <TB2> INFO: event ID mismatches: 0
[09:59:21.731] <TB2> INFO: ROC errors: 0
[09:59:21.731] <TB2> INFO: missing ROC header(s): 0
[09:59:21.731] <TB2> INFO: misplaced readback start: 0
[09:59:21.731] <TB2> INFO: Pixel decoding errors: 0
[09:59:21.731] <TB2> INFO: pixel data incomplete: 0
[09:59:21.731] <TB2> INFO: pixel address: 0
[09:59:21.731] <TB2> INFO: pulse height fill bit: 0
[09:59:21.731] <TB2> INFO: buffer corruption: 0
[09:59:21.774] <TB2> INFO: ######################################################################
[09:59:21.774] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[09:59:21.774] <TB2> INFO: ######################################################################
[09:59:21.774] <TB2> INFO: ----------------------------------------------------------------------
[09:59:21.774] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[09:59:21.774] <TB2> INFO: ----------------------------------------------------------------------
[09:59:21.774] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[09:59:21.788] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[09:59:21.788] <TB2> INFO: run 1 of 1
[09:59:22.024] <TB2> INFO: Expecting 36608000 events.
[09:59:46.957] <TB2> INFO: 703950 events read in total (24341ms).
[10:00:10.600] <TB2> INFO: 1389150 events read in total (47984ms).
[10:00:33.889] <TB2> INFO: 2075900 events read in total (71273ms).
[10:00:57.532] <TB2> INFO: 2761000 events read in total (94916ms).
[10:01:21.156] <TB2> INFO: 3442700 events read in total (118540ms).
[10:01:44.672] <TB2> INFO: 4124300 events read in total (142056ms).
[10:02:08.754] <TB2> INFO: 4805600 events read in total (166138ms).
[10:02:32.682] <TB2> INFO: 5488200 events read in total (190066ms).
[10:02:56.190] <TB2> INFO: 6170250 events read in total (213574ms).
[10:03:19.829] <TB2> INFO: 6850450 events read in total (237213ms).
[10:03:43.545] <TB2> INFO: 7530500 events read in total (260929ms).
[10:04:07.129] <TB2> INFO: 8210600 events read in total (284513ms).
[10:04:30.711] <TB2> INFO: 8893400 events read in total (308095ms).
[10:04:54.468] <TB2> INFO: 9574000 events read in total (331852ms).
[10:05:18.310] <TB2> INFO: 10253950 events read in total (355694ms).
[10:05:42.058] <TB2> INFO: 10932550 events read in total (379442ms).
[10:06:05.572] <TB2> INFO: 11610350 events read in total (402956ms).
[10:06:29.221] <TB2> INFO: 12287550 events read in total (426605ms).
[10:06:52.766] <TB2> INFO: 12963750 events read in total (450150ms).
[10:07:16.630] <TB2> INFO: 13643150 events read in total (474014ms).
[10:07:40.308] <TB2> INFO: 14320550 events read in total (497692ms).
[10:08:03.932] <TB2> INFO: 14996000 events read in total (521316ms).
[10:08:27.784] <TB2> INFO: 15672300 events read in total (545168ms).
[10:08:51.443] <TB2> INFO: 16347100 events read in total (568827ms).
[10:09:15.099] <TB2> INFO: 17020850 events read in total (592483ms).
[10:09:38.534] <TB2> INFO: 17695400 events read in total (615918ms).
[10:10:01.988] <TB2> INFO: 18367850 events read in total (639372ms).
[10:10:25.608] <TB2> INFO: 19042100 events read in total (662992ms).
[10:10:49.411] <TB2> INFO: 19716000 events read in total (686795ms).
[10:11:13.177] <TB2> INFO: 20387200 events read in total (710561ms).
[10:11:36.670] <TB2> INFO: 21058050 events read in total (734054ms).
[10:12:00.069] <TB2> INFO: 21728450 events read in total (757453ms).
[10:12:23.642] <TB2> INFO: 22397700 events read in total (781026ms).
[10:12:47.337] <TB2> INFO: 23067150 events read in total (804721ms).
[10:13:11.146] <TB2> INFO: 23735750 events read in total (828530ms).
[10:13:34.552] <TB2> INFO: 24406600 events read in total (851936ms).
[10:13:58.479] <TB2> INFO: 25076650 events read in total (875863ms).
[10:14:21.556] <TB2> INFO: 25746950 events read in total (898940ms).
[10:14:45.107] <TB2> INFO: 26416100 events read in total (922491ms).
[10:15:08.984] <TB2> INFO: 27084300 events read in total (946368ms).
[10:15:32.677] <TB2> INFO: 27753450 events read in total (970061ms).
[10:15:56.246] <TB2> INFO: 28421350 events read in total (993630ms).
[10:16:19.843] <TB2> INFO: 29088450 events read in total (1017227ms).
[10:16:43.416] <TB2> INFO: 29753150 events read in total (1040800ms).
[10:17:06.651] <TB2> INFO: 30419400 events read in total (1064035ms).
[10:17:30.248] <TB2> INFO: 31084800 events read in total (1087632ms).
[10:17:53.692] <TB2> INFO: 31751200 events read in total (1111076ms).
[10:18:17.272] <TB2> INFO: 32417250 events read in total (1134656ms).
[10:18:40.679] <TB2> INFO: 33083950 events read in total (1158063ms).
[10:19:04.110] <TB2> INFO: 33748500 events read in total (1181494ms).
[10:19:27.921] <TB2> INFO: 34419350 events read in total (1205305ms).
[10:19:51.534] <TB2> INFO: 35085150 events read in total (1228918ms).
[10:20:14.901] <TB2> INFO: 35754750 events read in total (1252285ms).
[10:20:38.886] <TB2> INFO: 36434000 events read in total (1276270ms).
[10:20:44.998] <TB2> INFO: 36608000 events read in total (1282382ms).
[10:20:45.091] <TB2> INFO: Test took 1283303ms.
[10:20:45.473] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:20:46.927] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:20:48.487] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:20:49.942] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:20:51.527] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:20:52.969] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:20:54.400] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:20:55.807] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:20:57.213] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:20:58.729] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:21:00.192] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:21:01.604] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:21:02.994] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:21:04.457] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:21:05.863] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:21:07.548] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:21:09.225] <TB2> INFO: PixTestScurves::scurves() done
[10:21:09.225] <TB2> INFO: Vcal mean: 121.59 136.90 124.54 110.61 124.21 119.11 121.22 121.40 129.44 127.57 135.79 129.26 130.62 128.91 133.44 128.39
[10:21:09.225] <TB2> INFO: Vcal RMS: 6.07 7.20 6.72 5.31 5.76 5.99 5.98 6.38 6.86 6.56 6.71 6.02 6.05 6.18 6.22 5.71
[10:21:09.225] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1307 seconds
[10:21:09.225] <TB2> INFO: Decoding statistics:
[10:21:09.225] <TB2> INFO: General information:
[10:21:09.225] <TB2> INFO: 16bit words read: 0
[10:21:09.225] <TB2> INFO: valid events total: 0
[10:21:09.225] <TB2> INFO: empty events: 0
[10:21:09.225] <TB2> INFO: valid events with pixels: 0
[10:21:09.225] <TB2> INFO: valid pixel hits: 0
[10:21:09.225] <TB2> INFO: Event errors: 0
[10:21:09.225] <TB2> INFO: start marker: 0
[10:21:09.225] <TB2> INFO: stop marker: 0
[10:21:09.225] <TB2> INFO: overflow: 0
[10:21:09.225] <TB2> INFO: invalid 5bit words: 0
[10:21:09.225] <TB2> INFO: invalid XOR eye diagram: 0
[10:21:09.225] <TB2> INFO: frame (failed synchr.): 0
[10:21:09.225] <TB2> INFO: idle data (no TBM trl): 0
[10:21:09.225] <TB2> INFO: no data (only TBM hdr): 0
[10:21:09.225] <TB2> INFO: TBM errors: 0
[10:21:09.225] <TB2> INFO: flawed TBM headers: 0
[10:21:09.225] <TB2> INFO: flawed TBM trailers: 0
[10:21:09.225] <TB2> INFO: event ID mismatches: 0
[10:21:09.225] <TB2> INFO: ROC errors: 0
[10:21:09.225] <TB2> INFO: missing ROC header(s): 0
[10:21:09.225] <TB2> INFO: misplaced readback start: 0
[10:21:09.225] <TB2> INFO: Pixel decoding errors: 0
[10:21:09.225] <TB2> INFO: pixel data incomplete: 0
[10:21:09.225] <TB2> INFO: pixel address: 0
[10:21:09.225] <TB2> INFO: pulse height fill bit: 0
[10:21:09.225] <TB2> INFO: buffer corruption: 0
[10:21:09.290] <TB2> INFO: ######################################################################
[10:21:09.290] <TB2> INFO: PixTestTrim::doTest()
[10:21:09.290] <TB2> INFO: ######################################################################
[10:21:09.291] <TB2> INFO: ----------------------------------------------------------------------
[10:21:09.291] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[10:21:09.291] <TB2> INFO: ----------------------------------------------------------------------
[10:21:09.355] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[10:21:09.355] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[10:21:09.369] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:21:09.369] <TB2> INFO: run 1 of 1
[10:21:09.604] <TB2> INFO: Expecting 5025280 events.
[10:21:41.513] <TB2> INFO: 832704 events read in total (31307ms).
[10:22:12.162] <TB2> INFO: 1661832 events read in total (61956ms).
[10:22:42.518] <TB2> INFO: 2486776 events read in total (92312ms).
[10:23:13.096] <TB2> INFO: 3307448 events read in total (122890ms).
[10:23:43.940] <TB2> INFO: 4124136 events read in total (153734ms).
[10:24:14.928] <TB2> INFO: 4938952 events read in total (184722ms).
[10:24:18.642] <TB2> INFO: 5025280 events read in total (188436ms).
[10:24:18.716] <TB2> INFO: Test took 189347ms.
[10:24:35.136] <TB2> INFO: ROC 0 VthrComp = 121
[10:24:35.136] <TB2> INFO: ROC 1 VthrComp = 130
[10:24:35.136] <TB2> INFO: ROC 2 VthrComp = 125
[10:24:35.136] <TB2> INFO: ROC 3 VthrComp = 115
[10:24:35.137] <TB2> INFO: ROC 4 VthrComp = 126
[10:24:35.138] <TB2> INFO: ROC 5 VthrComp = 118
[10:24:35.138] <TB2> INFO: ROC 6 VthrComp = 126
[10:24:35.139] <TB2> INFO: ROC 7 VthrComp = 125
[10:24:35.139] <TB2> INFO: ROC 8 VthrComp = 132
[10:24:35.139] <TB2> INFO: ROC 9 VthrComp = 126
[10:24:35.139] <TB2> INFO: ROC 10 VthrComp = 132
[10:24:35.139] <TB2> INFO: ROC 11 VthrComp = 128
[10:24:35.139] <TB2> INFO: ROC 12 VthrComp = 129
[10:24:35.139] <TB2> INFO: ROC 13 VthrComp = 121
[10:24:35.139] <TB2> INFO: ROC 14 VthrComp = 130
[10:24:35.140] <TB2> INFO: ROC 15 VthrComp = 131
[10:24:35.419] <TB2> INFO: Expecting 41600 events.
[10:24:38.994] <TB2> INFO: 41600 events read in total (2983ms).
[10:24:38.995] <TB2> INFO: Test took 3853ms.
[10:24:39.006] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[10:24:39.006] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[10:24:39.022] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:24:39.022] <TB2> INFO: run 1 of 1
[10:24:39.318] <TB2> INFO: Expecting 5025280 events.
[10:25:06.432] <TB2> INFO: 591280 events read in total (26523ms).
[10:25:32.781] <TB2> INFO: 1181600 events read in total (52872ms).
[10:25:59.303] <TB2> INFO: 1771984 events read in total (79394ms).
[10:26:25.284] <TB2> INFO: 2361648 events read in total (105375ms).
[10:26:51.783] <TB2> INFO: 2949320 events read in total (131874ms).
[10:27:17.920] <TB2> INFO: 3534904 events read in total (158011ms).
[10:27:44.124] <TB2> INFO: 4119928 events read in total (184215ms).
[10:28:10.457] <TB2> INFO: 4703608 events read in total (210548ms).
[10:28:25.144] <TB2> INFO: 5025280 events read in total (225235ms).
[10:28:25.227] <TB2> INFO: Test took 226205ms.
[10:28:50.287] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 62.3316 for pixel 0/4 mean/min/max = 47.9148/33.4103/62.4192
[10:28:50.288] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 70.6158 for pixel 0/4 mean/min/max = 51.3636/32.0213/70.7059
[10:28:50.289] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 62.6682 for pixel 15/2 mean/min/max = 47.1593/31.3995/62.9192
[10:28:50.290] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 60.1566 for pixel 1/79 mean/min/max = 45.9731/31.6014/60.3448
[10:28:50.291] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 59.7466 for pixel 17/6 mean/min/max = 45.6062/31.4249/59.7876
[10:28:50.292] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 61.6214 for pixel 0/13 mean/min/max = 46.4937/31.2903/61.6971
[10:28:50.292] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 58.9338 for pixel 23/1 mean/min/max = 45.3276/31.6583/58.9969
[10:28:50.293] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 59.8048 for pixel 4/58 mean/min/max = 45.8731/31.9069/59.8393
[10:28:50.293] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 68.5215 for pixel 16/12 mean/min/max = 51.3469/33.9907/68.7031
[10:28:50.294] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 62.7983 for pixel 0/7 mean/min/max = 46.9702/30.956/62.9844
[10:28:50.294] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 65.6184 for pixel 0/79 mean/min/max = 49.4854/33.0733/65.8976
[10:28:50.294] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 61.9796 for pixel 13/4 mean/min/max = 46.6785/31.2865/62.0705
[10:28:50.295] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 60.7705 for pixel 51/35 mean/min/max = 46.2716/31.7501/60.7932
[10:28:50.295] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 62.7347 for pixel 50/29 mean/min/max = 47.9991/33.2291/62.7692
[10:28:50.295] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 64.1502 for pixel 15/15 mean/min/max = 48.4384/32.6525/64.2243
[10:28:50.296] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 62.1738 for pixel 16/12 mean/min/max = 47.5174/32.7578/62.277
[10:28:50.296] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:28:50.385] <TB2> INFO: Expecting 411648 events.
[10:28:59.799] <TB2> INFO: 411648 events read in total (8822ms).
[10:28:59.806] <TB2> INFO: Expecting 411648 events.
[10:29:08.993] <TB2> INFO: 411648 events read in total (8784ms).
[10:29:09.003] <TB2> INFO: Expecting 411648 events.
[10:29:18.628] <TB2> INFO: 411648 events read in total (9222ms).
[10:29:18.641] <TB2> INFO: Expecting 411648 events.
[10:29:28.069] <TB2> INFO: 411648 events read in total (9025ms).
[10:29:28.085] <TB2> INFO: Expecting 411648 events.
[10:29:37.528] <TB2> INFO: 411648 events read in total (9040ms).
[10:29:37.547] <TB2> INFO: Expecting 411648 events.
[10:29:47.129] <TB2> INFO: 411648 events read in total (9179ms).
[10:29:47.149] <TB2> INFO: Expecting 411648 events.
[10:29:56.647] <TB2> INFO: 411648 events read in total (9095ms).
[10:29:56.671] <TB2> INFO: Expecting 411648 events.
[10:30:06.201] <TB2> INFO: 411648 events read in total (9127ms).
[10:30:06.227] <TB2> INFO: Expecting 411648 events.
[10:30:15.779] <TB2> INFO: 411648 events read in total (9149ms).
[10:30:15.814] <TB2> INFO: Expecting 411648 events.
[10:30:25.348] <TB2> INFO: 411648 events read in total (9131ms).
[10:30:25.391] <TB2> INFO: Expecting 411648 events.
[10:30:34.822] <TB2> INFO: 411648 events read in total (9028ms).
[10:30:34.857] <TB2> INFO: Expecting 411648 events.
[10:30:44.299] <TB2> INFO: 411648 events read in total (9039ms).
[10:30:44.336] <TB2> INFO: Expecting 411648 events.
[10:30:53.840] <TB2> INFO: 411648 events read in total (9101ms).
[10:30:53.880] <TB2> INFO: Expecting 411648 events.
[10:31:03.376] <TB2> INFO: 411648 events read in total (9093ms).
[10:31:03.419] <TB2> INFO: Expecting 411648 events.
[10:31:12.932] <TB2> INFO: 411648 events read in total (9110ms).
[10:31:12.989] <TB2> INFO: Expecting 411648 events.
[10:31:22.541] <TB2> INFO: 411648 events read in total (9150ms).
[10:31:22.635] <TB2> INFO: Test took 152339ms.
[10:31:23.274] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[10:31:23.289] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:31:23.289] <TB2> INFO: run 1 of 1
[10:31:23.585] <TB2> INFO: Expecting 5025280 events.
[10:31:50.503] <TB2> INFO: 588976 events read in total (26327ms).
[10:32:17.136] <TB2> INFO: 1176944 events read in total (52960ms).
[10:32:43.293] <TB2> INFO: 1765824 events read in total (79118ms).
[10:33:09.914] <TB2> INFO: 2353448 events read in total (105738ms).
[10:33:36.645] <TB2> INFO: 2943584 events read in total (132469ms).
[10:34:03.644] <TB2> INFO: 3530744 events read in total (159468ms).
[10:34:30.417] <TB2> INFO: 4119792 events read in total (186241ms).
[10:34:57.384] <TB2> INFO: 4710144 events read in total (213208ms).
[10:35:11.679] <TB2> INFO: 5025280 events read in total (227503ms).
[10:35:11.872] <TB2> INFO: Test took 228583ms.
[10:35:34.536] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 5.556517 .. 143.756818
[10:35:34.821] <TB2> INFO: Expecting 208000 events.
[10:35:44.606] <TB2> INFO: 208000 events read in total (9193ms).
[10:35:44.607] <TB2> INFO: Test took 10069ms.
[10:35:44.686] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 5 .. 153 (-1/-1) hits flags = 528 (plus default)
[10:35:44.700] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:35:44.700] <TB2> INFO: run 1 of 1
[10:35:44.978] <TB2> INFO: Expecting 4958720 events.
[10:36:11.084] <TB2> INFO: 580408 events read in total (25514ms).
[10:36:37.048] <TB2> INFO: 1160920 events read in total (51478ms).
[10:37:02.910] <TB2> INFO: 1741336 events read in total (77340ms).
[10:37:28.942] <TB2> INFO: 2321504 events read in total (103372ms).
[10:37:55.087] <TB2> INFO: 2901600 events read in total (129517ms).
[10:38:21.729] <TB2> INFO: 3480952 events read in total (156159ms).
[10:38:48.026] <TB2> INFO: 4059792 events read in total (182456ms).
[10:39:14.059] <TB2> INFO: 4637864 events read in total (208489ms).
[10:39:28.895] <TB2> INFO: 4958720 events read in total (223325ms).
[10:39:28.989] <TB2> INFO: Test took 224289ms.
[10:39:55.413] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.723114 .. 46.603805
[10:39:55.712] <TB2> INFO: Expecting 208000 events.
[10:40:05.684] <TB2> INFO: 208000 events read in total (9381ms).
[10:40:05.685] <TB2> INFO: Test took 10271ms.
[10:40:05.764] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[10:40:05.776] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:40:05.777] <TB2> INFO: run 1 of 1
[10:40:06.054] <TB2> INFO: Expecting 1331200 events.
[10:40:35.282] <TB2> INFO: 657248 events read in total (28636ms).
[10:41:03.565] <TB2> INFO: 1310816 events read in total (56920ms).
[10:41:04.852] <TB2> INFO: 1331200 events read in total (58207ms).
[10:41:04.888] <TB2> INFO: Test took 59111ms.
[10:41:16.808] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 28.909233 .. 52.359386
[10:41:17.046] <TB2> INFO: Expecting 208000 events.
[10:41:26.730] <TB2> INFO: 208000 events read in total (9092ms).
[10:41:26.730] <TB2> INFO: Test took 9921ms.
[10:41:26.805] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 18 .. 62 (-1/-1) hits flags = 528 (plus default)
[10:41:26.819] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:41:26.820] <TB2> INFO: run 1 of 1
[10:41:27.097] <TB2> INFO: Expecting 1497600 events.
[10:41:55.203] <TB2> INFO: 633448 events read in total (27514ms).
[10:42:22.723] <TB2> INFO: 1265536 events read in total (55035ms).
[10:42:33.353] <TB2> INFO: 1497600 events read in total (65665ms).
[10:42:33.386] <TB2> INFO: Test took 66567ms.
[10:42:46.763] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 25.565367 .. 53.266979
[10:42:47.064] <TB2> INFO: Expecting 208000 events.
[10:42:56.995] <TB2> INFO: 208000 events read in total (9340ms).
[10:42:56.996] <TB2> INFO: Test took 10232ms.
[10:42:57.079] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 63 (-1/-1) hits flags = 528 (plus default)
[10:42:57.093] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:42:57.093] <TB2> INFO: run 1 of 1
[10:42:57.393] <TB2> INFO: Expecting 1630720 events.
[10:43:25.385] <TB2> INFO: 641192 events read in total (27400ms).
[10:43:52.985] <TB2> INFO: 1282928 events read in total (55000ms).
[10:44:08.005] <TB2> INFO: 1630720 events read in total (70020ms).
[10:44:08.037] <TB2> INFO: Test took 70944ms.
[10:44:21.788] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[10:44:21.788] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[10:44:21.801] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:44:21.801] <TB2> INFO: run 1 of 1
[10:44:22.097] <TB2> INFO: Expecting 1364480 events.
[10:44:50.948] <TB2> INFO: 668968 events read in total (28260ms).
[10:45:19.656] <TB2> INFO: 1337368 events read in total (56968ms).
[10:45:21.303] <TB2> INFO: 1364480 events read in total (58616ms).
[10:45:21.338] <TB2> INFO: Test took 59538ms.
[10:45:33.839] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C0.dat
[10:45:33.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C1.dat
[10:45:33.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C2.dat
[10:45:33.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C3.dat
[10:45:33.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C4.dat
[10:45:33.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C5.dat
[10:45:33.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C6.dat
[10:45:33.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C7.dat
[10:45:33.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C8.dat
[10:45:33.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C9.dat
[10:45:33.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C10.dat
[10:45:33.840] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C11.dat
[10:45:33.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C12.dat
[10:45:33.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C13.dat
[10:45:33.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C14.dat
[10:45:33.841] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C15.dat
[10:45:33.841] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters35_C0.dat
[10:45:33.846] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters35_C1.dat
[10:45:33.851] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters35_C2.dat
[10:45:33.856] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters35_C3.dat
[10:45:33.860] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters35_C4.dat
[10:45:33.865] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters35_C5.dat
[10:45:33.870] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters35_C6.dat
[10:45:33.875] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters35_C7.dat
[10:45:33.879] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters35_C8.dat
[10:45:33.884] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters35_C9.dat
[10:45:33.889] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters35_C10.dat
[10:45:33.893] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters35_C11.dat
[10:45:33.898] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters35_C12.dat
[10:45:33.903] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters35_C13.dat
[10:45:33.907] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters35_C14.dat
[10:45:33.912] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//trimParameters35_C15.dat
[10:45:33.917] <TB2> INFO: PixTestTrim::trimTest() done
[10:45:33.917] <TB2> INFO: vtrim: 135 150 152 122 129 119 141 119 164 125 125 120 126 128 134 126
[10:45:33.917] <TB2> INFO: vthrcomp: 121 130 125 115 126 118 126 125 132 126 132 128 129 121 130 131
[10:45:33.917] <TB2> INFO: vcal mean: 35.07 35.37 35.07 35.01 35.10 34.98 35.00 35.03 35.73 35.08 35.17 35.01 35.01 35.20 35.33 35.24
[10:45:33.917] <TB2> INFO: vcal RMS: 1.07 1.59 1.15 1.04 1.19 1.10 1.05 1.05 1.91 1.17 1.24 1.14 1.07 1.30 1.55 1.29
[10:45:33.917] <TB2> INFO: bits mean: 8.33 8.99 9.49 9.36 10.30 9.35 9.88 9.24 9.10 9.34 8.11 9.39 9.43 9.47 8.77 9.20
[10:45:33.917] <TB2> INFO: bits RMS: 2.88 2.68 2.75 2.84 2.48 2.85 2.65 2.81 2.48 2.83 2.97 2.83 2.76 2.55 2.94 2.74
[10:45:33.924] <TB2> INFO: ----------------------------------------------------------------------
[10:45:33.924] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[10:45:33.924] <TB2> INFO: ----------------------------------------------------------------------
[10:45:33.927] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[10:45:33.938] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[10:45:33.938] <TB2> INFO: run 1 of 1
[10:45:34.175] <TB2> INFO: Expecting 4160000 events.
[10:46:07.868] <TB2> INFO: 770080 events read in total (33102ms).
[10:46:40.654] <TB2> INFO: 1532475 events read in total (65888ms).
[10:47:13.520] <TB2> INFO: 2288665 events read in total (98755ms).
[10:47:46.545] <TB2> INFO: 3039940 events read in total (131779ms).
[10:48:18.835] <TB2> INFO: 3786935 events read in total (164069ms).
[10:48:35.496] <TB2> INFO: 4160000 events read in total (180730ms).
[10:48:35.591] <TB2> INFO: Test took 181653ms.
[10:48:56.940] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 224 (-1/-1) hits flags = 528 (plus default)
[10:48:56.953] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[10:48:56.953] <TB2> INFO: run 1 of 1
[10:48:57.191] <TB2> INFO: Expecting 4680000 events.
[10:49:30.036] <TB2> INFO: 713645 events read in total (32254ms).
[10:50:01.875] <TB2> INFO: 1421910 events read in total (64093ms).
[10:50:33.438] <TB2> INFO: 2126755 events read in total (95656ms).
[10:51:05.122] <TB2> INFO: 2828205 events read in total (127340ms).
[10:51:36.674] <TB2> INFO: 3527145 events read in total (158892ms).
[10:52:08.408] <TB2> INFO: 4223885 events read in total (190626ms).
[10:52:28.848] <TB2> INFO: 4680000 events read in total (211067ms).
[10:52:28.933] <TB2> INFO: Test took 211980ms.
[10:52:54.886] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[10:52:54.901] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[10:52:54.901] <TB2> INFO: run 1 of 1
[10:52:55.192] <TB2> INFO: Expecting 4284800 events.
[10:53:28.180] <TB2> INFO: 737225 events read in total (32396ms).
[10:54:00.083] <TB2> INFO: 1467515 events read in total (64299ms).
[10:54:32.046] <TB2> INFO: 2193570 events read in total (96262ms).
[10:55:03.819] <TB2> INFO: 2915605 events read in total (128035ms).
[10:55:36.124] <TB2> INFO: 3634625 events read in total (160340ms).
[10:56:05.657] <TB2> INFO: 4284800 events read in total (189873ms).
[10:56:05.737] <TB2> INFO: Test took 190836ms.
[10:56:29.691] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[10:56:29.703] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[10:56:29.703] <TB2> INFO: run 1 of 1
[10:56:29.940] <TB2> INFO: Expecting 4305600 events.
[10:57:02.695] <TB2> INFO: 735965 events read in total (32165ms).
[10:57:34.647] <TB2> INFO: 1465410 events read in total (64116ms).
[10:58:06.983] <TB2> INFO: 2190605 events read in total (96452ms).
[10:58:38.815] <TB2> INFO: 2911935 events read in total (128284ms).
[10:59:11.170] <TB2> INFO: 3629750 events read in total (160639ms).
[10:59:41.869] <TB2> INFO: 4305600 events read in total (191338ms).
[10:59:41.947] <TB2> INFO: Test took 192244ms.
[11:00:05.824] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 208 (-1/-1) hits flags = 528 (plus default)
[11:00:05.839] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:00:05.839] <TB2> INFO: run 1 of 1
[11:00:06.096] <TB2> INFO: Expecting 4347200 events.
[11:00:39.335] <TB2> INFO: 733570 events read in total (32647ms).
[11:01:11.672] <TB2> INFO: 1460800 events read in total (64985ms).
[11:01:44.021] <TB2> INFO: 2183810 events read in total (97333ms).
[11:02:16.442] <TB2> INFO: 2902785 events read in total (129754ms).
[11:02:48.753] <TB2> INFO: 3619090 events read in total (162065ms).
[11:03:20.006] <TB2> INFO: 4336635 events read in total (193318ms).
[11:03:20.854] <TB2> INFO: 4347200 events read in total (194166ms).
[11:03:21.065] <TB2> INFO: Test took 195226ms.
[11:03:44.509] <TB2> INFO: PixTestTrim::trimBitTest() done
[11:03:44.510] <TB2> INFO: PixTestTrim::doTest() done, duration: 2555 seconds
[11:03:44.510] <TB2> INFO: Decoding statistics:
[11:03:44.510] <TB2> INFO: General information:
[11:03:44.510] <TB2> INFO: 16bit words read: 0
[11:03:44.510] <TB2> INFO: valid events total: 0
[11:03:44.510] <TB2> INFO: empty events: 0
[11:03:44.510] <TB2> INFO: valid events with pixels: 0
[11:03:44.510] <TB2> INFO: valid pixel hits: 0
[11:03:44.510] <TB2> INFO: Event errors: 0
[11:03:44.510] <TB2> INFO: start marker: 0
[11:03:44.510] <TB2> INFO: stop marker: 0
[11:03:44.510] <TB2> INFO: overflow: 0
[11:03:44.510] <TB2> INFO: invalid 5bit words: 0
[11:03:44.510] <TB2> INFO: invalid XOR eye diagram: 0
[11:03:44.510] <TB2> INFO: frame (failed synchr.): 0
[11:03:44.510] <TB2> INFO: idle data (no TBM trl): 0
[11:03:44.510] <TB2> INFO: no data (only TBM hdr): 0
[11:03:44.511] <TB2> INFO: TBM errors: 0
[11:03:44.511] <TB2> INFO: flawed TBM headers: 0
[11:03:44.511] <TB2> INFO: flawed TBM trailers: 0
[11:03:44.511] <TB2> INFO: event ID mismatches: 0
[11:03:44.511] <TB2> INFO: ROC errors: 0
[11:03:44.511] <TB2> INFO: missing ROC header(s): 0
[11:03:44.511] <TB2> INFO: misplaced readback start: 0
[11:03:44.511] <TB2> INFO: Pixel decoding errors: 0
[11:03:44.511] <TB2> INFO: pixel data incomplete: 0
[11:03:44.511] <TB2> INFO: pixel address: 0
[11:03:44.511] <TB2> INFO: pulse height fill bit: 0
[11:03:44.511] <TB2> INFO: buffer corruption: 0
[11:03:45.109] <TB2> INFO: ######################################################################
[11:03:45.109] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[11:03:45.109] <TB2> INFO: ######################################################################
[11:03:45.354] <TB2> INFO: Expecting 41600 events.
[11:03:48.838] <TB2> INFO: 41600 events read in total (2893ms).
[11:03:48.839] <TB2> INFO: Test took 3729ms.
[11:03:49.284] <TB2> INFO: Expecting 41600 events.
[11:03:52.872] <TB2> INFO: 41600 events read in total (2996ms).
[11:03:52.872] <TB2> INFO: Test took 3827ms.
[11:03:53.161] <TB2> INFO: Expecting 41600 events.
[11:03:56.757] <TB2> INFO: 41600 events read in total (3004ms).
[11:03:56.757] <TB2> INFO: Test took 3861ms.
[11:03:57.048] <TB2> INFO: Expecting 41600 events.
[11:04:00.651] <TB2> INFO: 41600 events read in total (3011ms).
[11:04:00.652] <TB2> INFO: Test took 3869ms.
[11:04:00.944] <TB2> INFO: Expecting 41600 events.
[11:04:04.472] <TB2> INFO: 41600 events read in total (2936ms).
[11:04:04.473] <TB2> INFO: Test took 3794ms.
[11:04:04.762] <TB2> INFO: Expecting 41600 events.
[11:04:08.406] <TB2> INFO: 41600 events read in total (3052ms).
[11:04:08.407] <TB2> INFO: Test took 3910ms.
[11:04:08.736] <TB2> INFO: Expecting 41600 events.
[11:04:12.358] <TB2> INFO: 41600 events read in total (3030ms).
[11:04:12.359] <TB2> INFO: Test took 3929ms.
[11:04:12.648] <TB2> INFO: Expecting 41600 events.
[11:04:16.279] <TB2> INFO: 41600 events read in total (3040ms).
[11:04:16.280] <TB2> INFO: Test took 3897ms.
[11:04:16.570] <TB2> INFO: Expecting 41600 events.
[11:04:20.274] <TB2> INFO: 41600 events read in total (3113ms).
[11:04:20.275] <TB2> INFO: Test took 3970ms.
[11:04:20.567] <TB2> INFO: Expecting 41600 events.
[11:04:24.218] <TB2> INFO: 41600 events read in total (3059ms).
[11:04:24.219] <TB2> INFO: Test took 3917ms.
[11:04:24.511] <TB2> INFO: Expecting 41600 events.
[11:04:28.108] <TB2> INFO: 41600 events read in total (3005ms).
[11:04:28.109] <TB2> INFO: Test took 3862ms.
[11:04:28.397] <TB2> INFO: Expecting 41600 events.
[11:04:32.057] <TB2> INFO: 41600 events read in total (3068ms).
[11:04:32.058] <TB2> INFO: Test took 3925ms.
[11:04:32.346] <TB2> INFO: Expecting 41600 events.
[11:04:35.980] <TB2> INFO: 41600 events read in total (3042ms).
[11:04:35.980] <TB2> INFO: Test took 3898ms.
[11:04:36.269] <TB2> INFO: Expecting 41600 events.
[11:04:39.805] <TB2> INFO: 41600 events read in total (2944ms).
[11:04:39.806] <TB2> INFO: Test took 3802ms.
[11:04:40.095] <TB2> INFO: Expecting 41600 events.
[11:04:43.742] <TB2> INFO: 41600 events read in total (3055ms).
[11:04:43.743] <TB2> INFO: Test took 3913ms.
[11:04:44.032] <TB2> INFO: Expecting 41600 events.
[11:04:47.591] <TB2> INFO: 41600 events read in total (2968ms).
[11:04:47.591] <TB2> INFO: Test took 3824ms.
[11:04:47.880] <TB2> INFO: Expecting 41600 events.
[11:04:51.403] <TB2> INFO: 41600 events read in total (2931ms).
[11:04:51.404] <TB2> INFO: Test took 3788ms.
[11:04:51.696] <TB2> INFO: Expecting 41600 events.
[11:04:55.318] <TB2> INFO: 41600 events read in total (3030ms).
[11:04:55.319] <TB2> INFO: Test took 3887ms.
[11:04:55.622] <TB2> INFO: Expecting 41600 events.
[11:04:59.083] <TB2> INFO: 41600 events read in total (2869ms).
[11:04:59.084] <TB2> INFO: Test took 3738ms.
[11:04:59.372] <TB2> INFO: Expecting 41600 events.
[11:05:02.980] <TB2> INFO: 41600 events read in total (3016ms).
[11:05:02.981] <TB2> INFO: Test took 3873ms.
[11:05:03.269] <TB2> INFO: Expecting 41600 events.
[11:05:06.884] <TB2> INFO: 41600 events read in total (3023ms).
[11:05:06.885] <TB2> INFO: Test took 3880ms.
[11:05:07.178] <TB2> INFO: Expecting 41600 events.
[11:05:10.656] <TB2> INFO: 41600 events read in total (2887ms).
[11:05:10.657] <TB2> INFO: Test took 3744ms.
[11:05:10.946] <TB2> INFO: Expecting 41600 events.
[11:05:14.427] <TB2> INFO: 41600 events read in total (2889ms).
[11:05:14.428] <TB2> INFO: Test took 3746ms.
[11:05:14.718] <TB2> INFO: Expecting 41600 events.
[11:05:18.325] <TB2> INFO: 41600 events read in total (3015ms).
[11:05:18.325] <TB2> INFO: Test took 3871ms.
[11:05:18.618] <TB2> INFO: Expecting 41600 events.
[11:05:22.104] <TB2> INFO: 41600 events read in total (2894ms).
[11:05:22.105] <TB2> INFO: Test took 3753ms.
[11:05:22.426] <TB2> INFO: Expecting 41600 events.
[11:05:25.996] <TB2> INFO: 41600 events read in total (2979ms).
[11:05:25.997] <TB2> INFO: Test took 3864ms.
[11:05:26.288] <TB2> INFO: Expecting 41600 events.
[11:05:29.829] <TB2> INFO: 41600 events read in total (2950ms).
[11:05:29.830] <TB2> INFO: Test took 3807ms.
[11:05:30.152] <TB2> INFO: Expecting 41600 events.
[11:05:33.666] <TB2> INFO: 41600 events read in total (2922ms).
[11:05:33.666] <TB2> INFO: Test took 3812ms.
[11:05:33.956] <TB2> INFO: Expecting 41600 events.
[11:05:37.646] <TB2> INFO: 41600 events read in total (3099ms).
[11:05:37.647] <TB2> INFO: Test took 3956ms.
[11:05:37.937] <TB2> INFO: Expecting 41600 events.
[11:05:41.442] <TB2> INFO: 41600 events read in total (2914ms).
[11:05:41.443] <TB2> INFO: Test took 3771ms.
[11:05:41.734] <TB2> INFO: Expecting 41600 events.
[11:05:45.256] <TB2> INFO: 41600 events read in total (2930ms).
[11:05:45.257] <TB2> INFO: Test took 3788ms.
[11:05:45.547] <TB2> INFO: Expecting 2560 events.
[11:05:46.442] <TB2> INFO: 2560 events read in total (304ms).
[11:05:46.442] <TB2> INFO: Test took 1171ms.
[11:05:46.750] <TB2> INFO: Expecting 2560 events.
[11:05:47.645] <TB2> INFO: 2560 events read in total (303ms).
[11:05:47.645] <TB2> INFO: Test took 1202ms.
[11:05:47.952] <TB2> INFO: Expecting 2560 events.
[11:05:48.837] <TB2> INFO: 2560 events read in total (294ms).
[11:05:48.838] <TB2> INFO: Test took 1193ms.
[11:05:49.145] <TB2> INFO: Expecting 2560 events.
[11:05:50.033] <TB2> INFO: 2560 events read in total (297ms).
[11:05:50.033] <TB2> INFO: Test took 1195ms.
[11:05:50.341] <TB2> INFO: Expecting 2560 events.
[11:05:51.229] <TB2> INFO: 2560 events read in total (296ms).
[11:05:51.229] <TB2> INFO: Test took 1195ms.
[11:05:51.537] <TB2> INFO: Expecting 2560 events.
[11:05:52.424] <TB2> INFO: 2560 events read in total (296ms).
[11:05:52.424] <TB2> INFO: Test took 1195ms.
[11:05:52.732] <TB2> INFO: Expecting 2560 events.
[11:05:53.613] <TB2> INFO: 2560 events read in total (289ms).
[11:05:53.613] <TB2> INFO: Test took 1188ms.
[11:05:53.921] <TB2> INFO: Expecting 2560 events.
[11:05:54.808] <TB2> INFO: 2560 events read in total (296ms).
[11:05:54.808] <TB2> INFO: Test took 1194ms.
[11:05:55.117] <TB2> INFO: Expecting 2560 events.
[11:05:55.001] <TB2> INFO: 2560 events read in total (293ms).
[11:05:55.001] <TB2> INFO: Test took 1192ms.
[11:05:56.308] <TB2> INFO: Expecting 2560 events.
[11:05:57.192] <TB2> INFO: 2560 events read in total (292ms).
[11:05:57.192] <TB2> INFO: Test took 1191ms.
[11:05:57.500] <TB2> INFO: Expecting 2560 events.
[11:05:58.384] <TB2> INFO: 2560 events read in total (292ms).
[11:05:58.384] <TB2> INFO: Test took 1191ms.
[11:05:58.691] <TB2> INFO: Expecting 2560 events.
[11:05:59.578] <TB2> INFO: 2560 events read in total (295ms).
[11:05:59.578] <TB2> INFO: Test took 1193ms.
[11:05:59.885] <TB2> INFO: Expecting 2560 events.
[11:06:00.779] <TB2> INFO: 2560 events read in total (303ms).
[11:06:00.779] <TB2> INFO: Test took 1201ms.
[11:06:01.087] <TB2> INFO: Expecting 2560 events.
[11:06:01.974] <TB2> INFO: 2560 events read in total (296ms).
[11:06:01.974] <TB2> INFO: Test took 1194ms.
[11:06:02.282] <TB2> INFO: Expecting 2560 events.
[11:06:03.169] <TB2> INFO: 2560 events read in total (295ms).
[11:06:03.170] <TB2> INFO: Test took 1195ms.
[11:06:03.478] <TB2> INFO: Expecting 2560 events.
[11:06:04.366] <TB2> INFO: 2560 events read in total (297ms).
[11:06:04.366] <TB2> INFO: Test took 1196ms.
[11:06:04.369] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:06:04.674] <TB2> INFO: Expecting 655360 events.
[11:06:19.945] <TB2> INFO: 655360 events read in total (14679ms).
[11:06:19.957] <TB2> INFO: Expecting 655360 events.
[11:06:34.762] <TB2> INFO: 655360 events read in total (14402ms).
[11:06:34.777] <TB2> INFO: Expecting 655360 events.
[11:06:49.813] <TB2> INFO: 655360 events read in total (14633ms).
[11:06:49.833] <TB2> INFO: Expecting 655360 events.
[11:07:04.521] <TB2> INFO: 655360 events read in total (14285ms).
[11:07:04.546] <TB2> INFO: Expecting 655360 events.
[11:07:19.230] <TB2> INFO: 655360 events read in total (14281ms).
[11:07:19.263] <TB2> INFO: Expecting 655360 events.
[11:07:34.258] <TB2> INFO: 655360 events read in total (14592ms).
[11:07:34.298] <TB2> INFO: Expecting 655360 events.
[11:07:48.997] <TB2> INFO: 655360 events read in total (14296ms).
[11:07:49.048] <TB2> INFO: Expecting 655360 events.
[11:08:03.961] <TB2> INFO: 655360 events read in total (14510ms).
[11:08:04.015] <TB2> INFO: Expecting 655360 events.
[11:08:19.106] <TB2> INFO: 655360 events read in total (14688ms).
[11:08:19.154] <TB2> INFO: Expecting 655360 events.
[11:08:34.348] <TB2> INFO: 655360 events read in total (14791ms).
[11:08:34.414] <TB2> INFO: Expecting 655360 events.
[11:08:49.387] <TB2> INFO: 655360 events read in total (14570ms).
[11:08:49.465] <TB2> INFO: Expecting 655360 events.
[11:09:04.441] <TB2> INFO: 655360 events read in total (14573ms).
[11:09:04.516] <TB2> INFO: Expecting 655360 events.
[11:09:19.711] <TB2> INFO: 655360 events read in total (14792ms).
[11:09:19.790] <TB2> INFO: Expecting 655360 events.
[11:09:34.983] <TB2> INFO: 655360 events read in total (14790ms).
[11:09:35.197] <TB2> INFO: Expecting 655360 events.
[11:09:50.063] <TB2> INFO: 655360 events read in total (14463ms).
[11:09:50.275] <TB2> INFO: Expecting 655360 events.
[11:10:05.143] <TB2> INFO: 655360 events read in total (14465ms).
[11:10:05.271] <TB2> INFO: Test took 240902ms.
[11:10:05.386] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:10:05.638] <TB2> INFO: Expecting 655360 events.
[11:10:20.589] <TB2> INFO: 655360 events read in total (14359ms).
[11:10:20.601] <TB2> INFO: Expecting 655360 events.
[11:10:35.146] <TB2> INFO: 655360 events read in total (14141ms).
[11:10:35.162] <TB2> INFO: Expecting 655360 events.
[11:10:50.048] <TB2> INFO: 655360 events read in total (14483ms).
[11:10:50.068] <TB2> INFO: Expecting 655360 events.
[11:11:04.888] <TB2> INFO: 655360 events read in total (14417ms).
[11:11:04.926] <TB2> INFO: Expecting 655360 events.
[11:11:19.827] <TB2> INFO: 655360 events read in total (14497ms).
[11:11:19.875] <TB2> INFO: Expecting 655360 events.
[11:11:34.307] <TB2> INFO: 655360 events read in total (14029ms).
[11:11:34.342] <TB2> INFO: Expecting 655360 events.
[11:11:48.978] <TB2> INFO: 655360 events read in total (14233ms).
[11:11:49.016] <TB2> INFO: Expecting 655360 events.
[11:12:04.054] <TB2> INFO: 655360 events read in total (14635ms).
[11:12:04.259] <TB2> INFO: Expecting 655360 events.
[11:12:18.897] <TB2> INFO: 655360 events read in total (14235ms).
[11:12:18.946] <TB2> INFO: Expecting 655360 events.
[11:12:33.433] <TB2> INFO: 655360 events read in total (14084ms).
[11:12:33.593] <TB2> INFO: Expecting 655360 events.
[11:12:48.181] <TB2> INFO: 655360 events read in total (14185ms).
[11:12:48.283] <TB2> INFO: Expecting 655360 events.
[11:13:03.106] <TB2> INFO: 655360 events read in total (14420ms).
[11:13:03.179] <TB2> INFO: Expecting 655360 events.
[11:13:17.771] <TB2> INFO: 655360 events read in total (14189ms).
[11:13:17.937] <TB2> INFO: Expecting 655360 events.
[11:13:32.705] <TB2> INFO: 655360 events read in total (14365ms).
[11:13:32.789] <TB2> INFO: Expecting 655360 events.
[11:13:47.655] <TB2> INFO: 655360 events read in total (14463ms).
[11:13:47.746] <TB2> INFO: Expecting 655360 events.
[11:14:02.427] <TB2> INFO: 655360 events read in total (14278ms).
[11:14:02.553] <TB2> INFO: Test took 237167ms.
[11:14:02.788] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:14:02.794] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:14:02.800] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:14:02.806] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:14:02.813] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:14:02.821] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:14:02.831] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:14:02.839] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[11:14:02.848] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[11:14:02.857] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:14:02.866] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:14:02.874] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:14:02.883] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:14:02.892] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:14:02.901] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:14:02.910] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:14:02.919] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:14:02.928] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:14:02.938] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:14:02.947] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:14:02.956] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:14:02.965] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:14:02.974] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:14:02.983] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:14:02.992] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:14:02.001] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:14:03.010] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:14:03.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C0.dat
[11:14:03.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C1.dat
[11:14:03.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C2.dat
[11:14:03.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C3.dat
[11:14:03.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C4.dat
[11:14:03.049] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C5.dat
[11:14:03.050] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C6.dat
[11:14:03.050] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C7.dat
[11:14:03.050] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C8.dat
[11:14:03.051] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C9.dat
[11:14:03.051] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C10.dat
[11:14:03.051] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C11.dat
[11:14:03.051] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C12.dat
[11:14:03.051] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C13.dat
[11:14:03.051] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C14.dat
[11:14:03.052] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//dacParameters35_C15.dat
[11:14:03.295] <TB2> INFO: Expecting 41600 events.
[11:14:06.438] <TB2> INFO: 41600 events read in total (2551ms).
[11:14:06.438] <TB2> INFO: Test took 3383ms.
[11:14:06.895] <TB2> INFO: Expecting 41600 events.
[11:14:09.959] <TB2> INFO: 41600 events read in total (2472ms).
[11:14:09.960] <TB2> INFO: Test took 3308ms.
[11:14:10.469] <TB2> INFO: Expecting 41600 events.
[11:14:13.722] <TB2> INFO: 41600 events read in total (2662ms).
[11:14:13.723] <TB2> INFO: Test took 3551ms.
[11:14:13.945] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:14.033] <TB2> INFO: Expecting 2560 events.
[11:14:14.921] <TB2> INFO: 2560 events read in total (296ms).
[11:14:14.921] <TB2> INFO: Test took 976ms.
[11:14:14.923] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:15.230] <TB2> INFO: Expecting 2560 events.
[11:14:16.122] <TB2> INFO: 2560 events read in total (301ms).
[11:14:16.123] <TB2> INFO: Test took 1200ms.
[11:14:16.126] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:16.431] <TB2> INFO: Expecting 2560 events.
[11:14:17.320] <TB2> INFO: 2560 events read in total (297ms).
[11:14:17.321] <TB2> INFO: Test took 1195ms.
[11:14:17.323] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:17.629] <TB2> INFO: Expecting 2560 events.
[11:14:18.517] <TB2> INFO: 2560 events read in total (297ms).
[11:14:18.517] <TB2> INFO: Test took 1194ms.
[11:14:18.520] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:18.824] <TB2> INFO: Expecting 2560 events.
[11:14:19.710] <TB2> INFO: 2560 events read in total (294ms).
[11:14:19.710] <TB2> INFO: Test took 1190ms.
[11:14:19.713] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:20.017] <TB2> INFO: Expecting 2560 events.
[11:14:20.912] <TB2> INFO: 2560 events read in total (303ms).
[11:14:20.912] <TB2> INFO: Test took 1199ms.
[11:14:20.914] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:21.220] <TB2> INFO: Expecting 2560 events.
[11:14:22.117] <TB2> INFO: 2560 events read in total (305ms).
[11:14:22.117] <TB2> INFO: Test took 1203ms.
[11:14:22.120] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:22.426] <TB2> INFO: Expecting 2560 events.
[11:14:23.321] <TB2> INFO: 2560 events read in total (303ms).
[11:14:23.322] <TB2> INFO: Test took 1202ms.
[11:14:23.325] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:23.629] <TB2> INFO: Expecting 2560 events.
[11:14:24.520] <TB2> INFO: 2560 events read in total (299ms).
[11:14:24.520] <TB2> INFO: Test took 1196ms.
[11:14:24.522] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:24.829] <TB2> INFO: Expecting 2560 events.
[11:14:25.713] <TB2> INFO: 2560 events read in total (293ms).
[11:14:25.714] <TB2> INFO: Test took 1192ms.
[11:14:25.717] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:26.023] <TB2> INFO: Expecting 2560 events.
[11:14:26.906] <TB2> INFO: 2560 events read in total (291ms).
[11:14:26.906] <TB2> INFO: Test took 1189ms.
[11:14:26.908] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:27.213] <TB2> INFO: Expecting 2560 events.
[11:14:28.093] <TB2> INFO: 2560 events read in total (288ms).
[11:14:28.093] <TB2> INFO: Test took 1185ms.
[11:14:28.095] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:28.402] <TB2> INFO: Expecting 2560 events.
[11:14:29.289] <TB2> INFO: 2560 events read in total (295ms).
[11:14:29.289] <TB2> INFO: Test took 1194ms.
[11:14:29.292] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:29.597] <TB2> INFO: Expecting 2560 events.
[11:14:30.487] <TB2> INFO: 2560 events read in total (298ms).
[11:14:30.487] <TB2> INFO: Test took 1196ms.
[11:14:30.490] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:30.796] <TB2> INFO: Expecting 2560 events.
[11:14:31.681] <TB2> INFO: 2560 events read in total (295ms).
[11:14:31.682] <TB2> INFO: Test took 1193ms.
[11:14:31.684] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:31.989] <TB2> INFO: Expecting 2560 events.
[11:14:32.871] <TB2> INFO: 2560 events read in total (290ms).
[11:14:32.871] <TB2> INFO: Test took 1187ms.
[11:14:32.875] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:33.179] <TB2> INFO: Expecting 2560 events.
[11:14:34.067] <TB2> INFO: 2560 events read in total (296ms).
[11:14:34.067] <TB2> INFO: Test took 1193ms.
[11:14:34.069] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:34.375] <TB2> INFO: Expecting 2560 events.
[11:14:35.259] <TB2> INFO: 2560 events read in total (292ms).
[11:14:35.260] <TB2> INFO: Test took 1191ms.
[11:14:35.262] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:35.568] <TB2> INFO: Expecting 2560 events.
[11:14:36.453] <TB2> INFO: 2560 events read in total (294ms).
[11:14:36.453] <TB2> INFO: Test took 1191ms.
[11:14:36.455] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:36.763] <TB2> INFO: Expecting 2560 events.
[11:14:37.644] <TB2> INFO: 2560 events read in total (289ms).
[11:14:37.644] <TB2> INFO: Test took 1189ms.
[11:14:37.647] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:37.953] <TB2> INFO: Expecting 2560 events.
[11:14:38.833] <TB2> INFO: 2560 events read in total (289ms).
[11:14:38.833] <TB2> INFO: Test took 1186ms.
[11:14:38.835] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:39.141] <TB2> INFO: Expecting 2560 events.
[11:14:40.024] <TB2> INFO: 2560 events read in total (291ms).
[11:14:40.025] <TB2> INFO: Test took 1190ms.
[11:14:40.028] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:40.333] <TB2> INFO: Expecting 2560 events.
[11:14:41.225] <TB2> INFO: 2560 events read in total (300ms).
[11:14:41.225] <TB2> INFO: Test took 1197ms.
[11:14:41.227] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:41.533] <TB2> INFO: Expecting 2560 events.
[11:14:42.414] <TB2> INFO: 2560 events read in total (289ms).
[11:14:42.414] <TB2> INFO: Test took 1187ms.
[11:14:42.416] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:42.723] <TB2> INFO: Expecting 2560 events.
[11:14:43.611] <TB2> INFO: 2560 events read in total (297ms).
[11:14:43.611] <TB2> INFO: Test took 1195ms.
[11:14:43.613] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:43.920] <TB2> INFO: Expecting 2560 events.
[11:14:44.813] <TB2> INFO: 2560 events read in total (301ms).
[11:14:44.813] <TB2> INFO: Test took 1200ms.
[11:14:44.816] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:45.122] <TB2> INFO: Expecting 2560 events.
[11:14:46.007] <TB2> INFO: 2560 events read in total (294ms).
[11:14:46.007] <TB2> INFO: Test took 1191ms.
[11:14:46.010] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:46.316] <TB2> INFO: Expecting 2560 events.
[11:14:47.205] <TB2> INFO: 2560 events read in total (298ms).
[11:14:47.205] <TB2> INFO: Test took 1195ms.
[11:14:47.208] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:47.514] <TB2> INFO: Expecting 2560 events.
[11:14:48.401] <TB2> INFO: 2560 events read in total (295ms).
[11:14:48.401] <TB2> INFO: Test took 1193ms.
[11:14:48.404] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:48.709] <TB2> INFO: Expecting 2560 events.
[11:14:49.593] <TB2> INFO: 2560 events read in total (292ms).
[11:14:49.593] <TB2> INFO: Test took 1189ms.
[11:14:49.595] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:49.902] <TB2> INFO: Expecting 2560 events.
[11:14:50.789] <TB2> INFO: 2560 events read in total (295ms).
[11:14:50.790] <TB2> INFO: Test took 1195ms.
[11:14:50.792] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:51.099] <TB2> INFO: Expecting 2560 events.
[11:14:51.993] <TB2> INFO: 2560 events read in total (303ms).
[11:14:51.993] <TB2> INFO: Test took 1201ms.
[11:14:52.464] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 667 seconds
[11:14:52.464] <TB2> INFO: PH scale (per ROC): 38 31 33 42 36 33 50 50 37 33 37 52 40 46 33 36
[11:14:52.464] <TB2> INFO: PH offset (per ROC): 108 83 97 110 103 96 114 108 86 110 86 121 103 125 90 109
[11:14:52.471] <TB2> INFO: Decoding statistics:
[11:14:52.471] <TB2> INFO: General information:
[11:14:52.471] <TB2> INFO: 16bit words read: 127882
[11:14:52.471] <TB2> INFO: valid events total: 20480
[11:14:52.471] <TB2> INFO: empty events: 17979
[11:14:52.471] <TB2> INFO: valid events with pixels: 2501
[11:14:52.471] <TB2> INFO: valid pixel hits: 2501
[11:14:52.471] <TB2> INFO: Event errors: 0
[11:14:52.471] <TB2> INFO: start marker: 0
[11:14:52.471] <TB2> INFO: stop marker: 0
[11:14:52.471] <TB2> INFO: overflow: 0
[11:14:52.471] <TB2> INFO: invalid 5bit words: 0
[11:14:52.471] <TB2> INFO: invalid XOR eye diagram: 0
[11:14:52.471] <TB2> INFO: frame (failed synchr.): 0
[11:14:52.471] <TB2> INFO: idle data (no TBM trl): 0
[11:14:52.471] <TB2> INFO: no data (only TBM hdr): 0
[11:14:52.471] <TB2> INFO: TBM errors: 0
[11:14:52.471] <TB2> INFO: flawed TBM headers: 0
[11:14:52.471] <TB2> INFO: flawed TBM trailers: 0
[11:14:52.471] <TB2> INFO: event ID mismatches: 0
[11:14:52.471] <TB2> INFO: ROC errors: 0
[11:14:52.471] <TB2> INFO: missing ROC header(s): 0
[11:14:52.471] <TB2> INFO: misplaced readback start: 0
[11:14:52.471] <TB2> INFO: Pixel decoding errors: 0
[11:14:52.471] <TB2> INFO: pixel data incomplete: 0
[11:14:52.471] <TB2> INFO: pixel address: 0
[11:14:52.471] <TB2> INFO: pulse height fill bit: 0
[11:14:52.471] <TB2> INFO: buffer corruption: 0
[11:14:52.632] <TB2> INFO: ######################################################################
[11:14:52.632] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[11:14:52.632] <TB2> INFO: ######################################################################
[11:14:52.646] <TB2> INFO: scanning low vcal = 10
[11:14:52.883] <TB2> INFO: Expecting 41600 events.
[11:14:56.468] <TB2> INFO: 41600 events read in total (2993ms).
[11:14:56.468] <TB2> INFO: Test took 3822ms.
[11:14:56.471] <TB2> INFO: scanning low vcal = 20
[11:14:56.769] <TB2> INFO: Expecting 41600 events.
[11:15:00.372] <TB2> INFO: 41600 events read in total (3011ms).
[11:15:00.373] <TB2> INFO: Test took 3902ms.
[11:15:00.375] <TB2> INFO: scanning low vcal = 30
[11:15:00.673] <TB2> INFO: Expecting 41600 events.
[11:15:04.343] <TB2> INFO: 41600 events read in total (3078ms).
[11:15:04.344] <TB2> INFO: Test took 3969ms.
[11:15:04.347] <TB2> INFO: scanning low vcal = 40
[11:15:04.624] <TB2> INFO: Expecting 41600 events.
[11:15:08.634] <TB2> INFO: 41600 events read in total (3419ms).
[11:15:08.635] <TB2> INFO: Test took 4288ms.
[11:15:08.638] <TB2> INFO: scanning low vcal = 50
[11:15:08.935] <TB2> INFO: Expecting 41600 events.
[11:15:12.912] <TB2> INFO: 41600 events read in total (3385ms).
[11:15:12.913] <TB2> INFO: Test took 4275ms.
[11:15:12.916] <TB2> INFO: scanning low vcal = 60
[11:15:13.192] <TB2> INFO: Expecting 41600 events.
[11:15:17.209] <TB2> INFO: 41600 events read in total (3425ms).
[11:15:17.210] <TB2> INFO: Test took 4294ms.
[11:15:17.214] <TB2> INFO: scanning low vcal = 70
[11:15:17.490] <TB2> INFO: Expecting 41600 events.
[11:15:21.528] <TB2> INFO: 41600 events read in total (3446ms).
[11:15:21.529] <TB2> INFO: Test took 4315ms.
[11:15:21.532] <TB2> INFO: scanning low vcal = 80
[11:15:21.815] <TB2> INFO: Expecting 41600 events.
[11:15:25.812] <TB2> INFO: 41600 events read in total (3405ms).
[11:15:25.812] <TB2> INFO: Test took 4280ms.
[11:15:25.815] <TB2> INFO: scanning low vcal = 90
[11:15:26.092] <TB2> INFO: Expecting 41600 events.
[11:15:30.079] <TB2> INFO: 41600 events read in total (3395ms).
[11:15:30.079] <TB2> INFO: Test took 4263ms.
[11:15:30.084] <TB2> INFO: scanning low vcal = 100
[11:15:30.359] <TB2> INFO: Expecting 41600 events.
[11:15:34.365] <TB2> INFO: 41600 events read in total (3414ms).
[11:15:34.366] <TB2> INFO: Test took 4281ms.
[11:15:34.369] <TB2> INFO: scanning low vcal = 110
[11:15:34.666] <TB2> INFO: Expecting 41600 events.
[11:15:38.705] <TB2> INFO: 41600 events read in total (3448ms).
[11:15:38.705] <TB2> INFO: Test took 4336ms.
[11:15:38.708] <TB2> INFO: scanning low vcal = 120
[11:15:38.985] <TB2> INFO: Expecting 41600 events.
[11:15:43.015] <TB2> INFO: 41600 events read in total (3438ms).
[11:15:43.016] <TB2> INFO: Test took 4308ms.
[11:15:43.019] <TB2> INFO: scanning low vcal = 130
[11:15:43.296] <TB2> INFO: Expecting 41600 events.
[11:15:47.329] <TB2> INFO: 41600 events read in total (3441ms).
[11:15:47.329] <TB2> INFO: Test took 4309ms.
[11:15:47.334] <TB2> INFO: scanning low vcal = 140
[11:15:47.609] <TB2> INFO: Expecting 41600 events.
[11:15:51.631] <TB2> INFO: 41600 events read in total (3430ms).
[11:15:51.632] <TB2> INFO: Test took 4298ms.
[11:15:51.635] <TB2> INFO: scanning low vcal = 150
[11:15:51.912] <TB2> INFO: Expecting 41600 events.
[11:15:55.949] <TB2> INFO: 41600 events read in total (3445ms).
[11:15:55.950] <TB2> INFO: Test took 4315ms.
[11:15:55.953] <TB2> INFO: scanning low vcal = 160
[11:15:56.230] <TB2> INFO: Expecting 41600 events.
[11:16:00.251] <TB2> INFO: 41600 events read in total (3430ms).
[11:16:00.251] <TB2> INFO: Test took 4298ms.
[11:16:00.255] <TB2> INFO: scanning low vcal = 170
[11:16:00.531] <TB2> INFO: Expecting 41600 events.
[11:16:04.533] <TB2> INFO: 41600 events read in total (3410ms).
[11:16:04.534] <TB2> INFO: Test took 4279ms.
[11:16:04.539] <TB2> INFO: scanning low vcal = 180
[11:16:04.814] <TB2> INFO: Expecting 41600 events.
[11:16:08.856] <TB2> INFO: 41600 events read in total (3451ms).
[11:16:08.857] <TB2> INFO: Test took 4318ms.
[11:16:08.860] <TB2> INFO: scanning low vcal = 190
[11:16:09.137] <TB2> INFO: Expecting 41600 events.
[11:16:13.090] <TB2> INFO: 41600 events read in total (3361ms).
[11:16:13.091] <TB2> INFO: Test took 4231ms.
[11:16:13.094] <TB2> INFO: scanning low vcal = 200
[11:16:13.371] <TB2> INFO: Expecting 41600 events.
[11:16:17.389] <TB2> INFO: 41600 events read in total (3426ms).
[11:16:17.390] <TB2> INFO: Test took 4296ms.
[11:16:17.392] <TB2> INFO: scanning low vcal = 210
[11:16:17.669] <TB2> INFO: Expecting 41600 events.
[11:16:21.730] <TB2> INFO: 41600 events read in total (3469ms).
[11:16:21.731] <TB2> INFO: Test took 4338ms.
[11:16:21.734] <TB2> INFO: scanning low vcal = 220
[11:16:22.011] <TB2> INFO: Expecting 41600 events.
[11:16:26.057] <TB2> INFO: 41600 events read in total (3455ms).
[11:16:26.058] <TB2> INFO: Test took 4324ms.
[11:16:26.061] <TB2> INFO: scanning low vcal = 230
[11:16:26.337] <TB2> INFO: Expecting 41600 events.
[11:16:30.360] <TB2> INFO: 41600 events read in total (3431ms).
[11:16:30.361] <TB2> INFO: Test took 4300ms.
[11:16:30.364] <TB2> INFO: scanning low vcal = 240
[11:16:30.641] <TB2> INFO: Expecting 41600 events.
[11:16:34.701] <TB2> INFO: 41600 events read in total (3468ms).
[11:16:34.701] <TB2> INFO: Test took 4337ms.
[11:16:34.704] <TB2> INFO: scanning low vcal = 250
[11:16:34.981] <TB2> INFO: Expecting 41600 events.
[11:16:38.994] <TB2> INFO: 41600 events read in total (3421ms).
[11:16:38.995] <TB2> INFO: Test took 4290ms.
[11:16:38.999] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[11:16:39.297] <TB2> INFO: Expecting 41600 events.
[11:16:43.335] <TB2> INFO: 41600 events read in total (3446ms).
[11:16:43.336] <TB2> INFO: Test took 4337ms.
[11:16:43.339] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[11:16:43.616] <TB2> INFO: Expecting 41600 events.
[11:16:47.616] <TB2> INFO: 41600 events read in total (3408ms).
[11:16:47.617] <TB2> INFO: Test took 4278ms.
[11:16:47.620] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[11:16:47.896] <TB2> INFO: Expecting 41600 events.
[11:16:51.892] <TB2> INFO: 41600 events read in total (3404ms).
[11:16:51.893] <TB2> INFO: Test took 4273ms.
[11:16:51.897] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[11:16:52.173] <TB2> INFO: Expecting 41600 events.
[11:16:56.164] <TB2> INFO: 41600 events read in total (3399ms).
[11:16:56.165] <TB2> INFO: Test took 4268ms.
[11:16:56.168] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[11:16:56.445] <TB2> INFO: Expecting 41600 events.
[11:17:00.451] <TB2> INFO: 41600 events read in total (3415ms).
[11:17:00.452] <TB2> INFO: Test took 4284ms.
[11:17:00.869] <TB2> INFO: PixTestGainPedestal::measure() done
[11:17:33.551] <TB2> INFO: PixTestGainPedestal::fit() done
[11:17:33.551] <TB2> INFO: non-linearity mean: 0.922 0.978 0.943 0.931 0.938 0.992 0.982 0.945 0.904 0.919 0.949 0.984 0.941 0.979 0.969 0.930
[11:17:33.551] <TB2> INFO: non-linearity RMS: 0.099 0.189 0.168 0.082 0.080 0.159 0.003 0.070 0.085 0.116 0.136 0.003 0.139 0.004 0.158 0.117
[11:17:33.551] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr35_C0.dat
[11:17:33.565] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr35_C1.dat
[11:17:33.578] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr35_C2.dat
[11:17:33.592] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr35_C3.dat
[11:17:33.606] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr35_C4.dat
[11:17:33.619] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr35_C5.dat
[11:17:33.633] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr35_C6.dat
[11:17:33.646] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr35_C7.dat
[11:17:33.660] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr35_C8.dat
[11:17:33.673] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr35_C9.dat
[11:17:33.687] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr35_C10.dat
[11:17:33.700] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr35_C11.dat
[11:17:33.714] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr35_C12.dat
[11:17:33.727] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr35_C13.dat
[11:17:33.741] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr35_C14.dat
[11:17:33.754] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//003_Fulltest_p17//phCalibrationFitErr35_C15.dat
[11:17:33.768] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 161 seconds
[11:17:33.768] <TB2> INFO: Decoding statistics:
[11:17:33.768] <TB2> INFO: General information:
[11:17:33.768] <TB2> INFO: 16bit words read: 3289252
[11:17:33.768] <TB2> INFO: valid events total: 332800
[11:17:33.768] <TB2> INFO: empty events: 1133
[11:17:33.768] <TB2> INFO: valid events with pixels: 331667
[11:17:33.768] <TB2> INFO: valid pixel hits: 646226
[11:17:33.768] <TB2> INFO: Event errors: 0
[11:17:33.768] <TB2> INFO: start marker: 0
[11:17:33.768] <TB2> INFO: stop marker: 0
[11:17:33.768] <TB2> INFO: overflow: 0
[11:17:33.768] <TB2> INFO: invalid 5bit words: 0
[11:17:33.768] <TB2> INFO: invalid XOR eye diagram: 0
[11:17:33.768] <TB2> INFO: frame (failed synchr.): 0
[11:17:33.768] <TB2> INFO: idle data (no TBM trl): 0
[11:17:33.768] <TB2> INFO: no data (only TBM hdr): 0
[11:17:33.768] <TB2> INFO: TBM errors: 0
[11:17:33.768] <TB2> INFO: flawed TBM headers: 0
[11:17:33.768] <TB2> INFO: flawed TBM trailers: 0
[11:17:33.768] <TB2> INFO: event ID mismatches: 0
[11:17:33.768] <TB2> INFO: ROC errors: 0
[11:17:33.768] <TB2> INFO: missing ROC header(s): 0
[11:17:33.768] <TB2> INFO: misplaced readback start: 0
[11:17:33.768] <TB2> INFO: Pixel decoding errors: 0
[11:17:33.768] <TB2> INFO: pixel data incomplete: 0
[11:17:33.768] <TB2> INFO: pixel address: 0
[11:17:33.768] <TB2> INFO: pulse height fill bit: 0
[11:17:33.768] <TB2> INFO: buffer corruption: 0
[11:17:33.784] <TB2> INFO: Decoding statistics:
[11:17:33.784] <TB2> INFO: General information:
[11:17:33.784] <TB2> INFO: 16bit words read: 3418670
[11:17:33.784] <TB2> INFO: valid events total: 353536
[11:17:33.784] <TB2> INFO: empty events: 19368
[11:17:33.784] <TB2> INFO: valid events with pixels: 334168
[11:17:33.784] <TB2> INFO: valid pixel hits: 648727
[11:17:33.784] <TB2> INFO: Event errors: 0
[11:17:33.784] <TB2> INFO: start marker: 0
[11:17:33.784] <TB2> INFO: stop marker: 0
[11:17:33.784] <TB2> INFO: overflow: 0
[11:17:33.784] <TB2> INFO: invalid 5bit words: 0
[11:17:33.784] <TB2> INFO: invalid XOR eye diagram: 0
[11:17:33.784] <TB2> INFO: frame (failed synchr.): 0
[11:17:33.784] <TB2> INFO: idle data (no TBM trl): 0
[11:17:33.784] <TB2> INFO: no data (only TBM hdr): 0
[11:17:33.784] <TB2> INFO: TBM errors: 0
[11:17:33.784] <TB2> INFO: flawed TBM headers: 0
[11:17:33.784] <TB2> INFO: flawed TBM trailers: 0
[11:17:33.784] <TB2> INFO: event ID mismatches: 0
[11:17:33.784] <TB2> INFO: ROC errors: 0
[11:17:33.784] <TB2> INFO: missing ROC header(s): 0
[11:17:33.784] <TB2> INFO: misplaced readback start: 0
[11:17:33.784] <TB2> INFO: Pixel decoding errors: 0
[11:17:33.784] <TB2> INFO: pixel data incomplete: 0
[11:17:33.784] <TB2> INFO: pixel address: 0
[11:17:33.784] <TB2> INFO: pulse height fill bit: 0
[11:17:33.784] <TB2> INFO: buffer corruption: 0
[11:17:33.784] <TB2> INFO: enter test to run
[11:17:33.784] <TB2> INFO: test: exit no parameter change
[11:17:33.901] <TB2> QUIET: Connection to board 149 closed.
[11:17:33.902] <TB2> INFO: pXar: this is the end, my friend