[15:45:38.434] <TB2> INFO: *** Welcome to pxar ***
[15:45:38.434] <TB2> INFO: *** Today: 2016/10/23
[15:45:38.440] <TB2> INFO: *** Version: c8ba-dirty
[15:45:38.440] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C15.dat
[15:45:38.441] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//tbmParameters_C1b.dat
[15:45:38.441] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//defaultMaskFile.dat
[15:45:38.441] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters_C15.dat
[15:45:38.538] <TB2> INFO: clk: 4
[15:45:38.538] <TB2> INFO: ctr: 4
[15:45:38.538] <TB2> INFO: sda: 19
[15:45:38.538] <TB2> INFO: tin: 9
[15:45:38.538] <TB2> INFO: level: 15
[15:45:38.538] <TB2> INFO: triggerdelay: 0
[15:45:38.538] <TB2> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[15:45:38.538] <TB2> INFO: Log level: INFO
[15:45:38.548] <TB2> INFO: Found DTB DTB_WWXUD2
[15:45:38.558] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[15:45:38.560] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[15:45:38.562] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[15:45:40.115] <TB2> INFO: DUT info:
[15:45:40.115] <TB2> INFO: The DUT currently contains the following objects:
[15:45:40.115] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[15:45:40.115] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:45:40.115] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:45:40.115] <TB2> INFO: TBM Core alpha (2): 7 registers set
[15:45:40.115] <TB2> INFO: TBM Core beta (3): 7 registers set
[15:45:40.115] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[15:45:40.115] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:40.115] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:40.115] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:40.115] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:40.115] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:40.115] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:40.115] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:40.115] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:40.115] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:40.115] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:40.115] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:40.115] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:40.115] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:40.116] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:40.116] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:40.116] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[15:45:40.517] <TB2> INFO: enter 'restricted' command line mode
[15:45:40.517] <TB2> INFO: enter test to run
[15:45:40.517] <TB2> INFO: test: pretest no parameter change
[15:45:40.517] <TB2> INFO: running: pretest
[15:45:40.523] <TB2> INFO: ######################################################################
[15:45:40.523] <TB2> INFO: PixTestPretest::doTest()
[15:45:40.523] <TB2> INFO: ######################################################################
[15:45:40.524] <TB2> INFO: ----------------------------------------------------------------------
[15:45:40.524] <TB2> INFO: PixTestPretest::programROC()
[15:45:40.524] <TB2> INFO: ----------------------------------------------------------------------
[15:45:58.538] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[15:45:58.538] <TB2> INFO: IA differences per ROC: 18.5 20.1 18.5 18.5 17.7 17.7 19.3 19.3 20.1 18.5 18.5 20.1 20.9 20.1 19.3 17.7
[15:45:58.603] <TB2> INFO: ----------------------------------------------------------------------
[15:45:58.603] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[15:45:58.603] <TB2> INFO: ----------------------------------------------------------------------
[15:46:05.104] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 385.1 mA = 24.0688 mA/ROC
[15:46:05.104] <TB2> INFO: i(loss) [mA/ROC]: 18.5 19.3 18.5 18.5 19.3 20.1 19.3 19.3 19.3 18.5 19.3 19.3 18.5 19.3 19.3 19.3
[15:46:05.142] <TB2> INFO: ----------------------------------------------------------------------
[15:46:05.143] <TB2> INFO: PixTestPretest::findTiming()
[15:46:05.143] <TB2> INFO: ----------------------------------------------------------------------
[15:46:05.143] <TB2> INFO: PixTestCmd::init()

[15:46:37.314] <TB2> INFO: TBM phases: 160MHz: 7, 400MHz: 6, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[15:46:37.314] <TB2> INFO: (success/tries = 100/100), width = 3
[15:46:38.822] <TB2> INFO: ----------------------------------------------------------------------
[15:46:38.822] <TB2> INFO: PixTestPretest::findWorkingPixel()
[15:46:38.822] <TB2> INFO: ----------------------------------------------------------------------
[15:46:38.918] <TB2> INFO: Expecting 231680 events.
[15:46:48.929] <TB2> INFO: 231680 events read in total (9419ms).
[15:46:48.940] <TB2> INFO: Test took 10112ms.
[15:46:49.186] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[15:46:49.225] <TB2> INFO: ----------------------------------------------------------------------
[15:46:49.225] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[15:46:49.225] <TB2> INFO: ----------------------------------------------------------------------
[15:46:49.320] <TB2> INFO: Expecting 231680 events.
[15:46:59.381] <TB2> INFO: 231680 events read in total (9469ms).
[15:46:59.388] <TB2> INFO: Test took 10158ms.
[15:46:59.653] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[15:46:59.653] <TB2> INFO: CalDel: 87 112 114 81 97 110 89 112 94 107 108 112 113 119 94 86
[15:46:59.653] <TB2> INFO: VthrComp: 51 52 51 51 51 51 51 51 58 51 51 51 51 51 51 52
[15:46:59.660] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C0.dat
[15:46:59.660] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C1.dat
[15:46:59.660] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C2.dat
[15:46:59.661] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C3.dat
[15:46:59.661] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C4.dat
[15:46:59.661] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C5.dat
[15:46:59.662] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C6.dat
[15:46:59.662] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C7.dat
[15:46:59.662] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C8.dat
[15:46:59.662] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C9.dat
[15:46:59.663] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C10.dat
[15:46:59.663] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C11.dat
[15:46:59.663] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C12.dat
[15:46:59.663] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C13.dat
[15:46:59.663] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C14.dat
[15:46:59.664] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters_C15.dat
[15:46:59.664] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//tbmParameters_C0a.dat
[15:46:59.664] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//tbmParameters_C0b.dat
[15:46:59.664] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//tbmParameters_C1a.dat
[15:46:59.664] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//tbmParameters_C1b.dat
[15:46:59.664] <TB2> INFO: PixTestPretest::doTest() done, duration: 79 seconds
[15:46:59.717] <TB2> INFO: enter test to run
[15:46:59.718] <TB2> INFO: test: FullTest no parameter change
[15:46:59.718] <TB2> INFO: running: fulltest
[15:46:59.718] <TB2> INFO: ######################################################################
[15:46:59.718] <TB2> INFO: PixTestFullTest::doTest()
[15:46:59.718] <TB2> INFO: ######################################################################
[15:46:59.719] <TB2> INFO: ######################################################################
[15:46:59.719] <TB2> INFO: PixTestAlive::doTest()
[15:46:59.719] <TB2> INFO: ######################################################################
[15:46:59.720] <TB2> INFO: ----------------------------------------------------------------------
[15:46:59.720] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:46:59.720] <TB2> INFO: ----------------------------------------------------------------------
[15:46:59.004] <TB2> INFO: Expecting 41600 events.
[15:47:03.447] <TB2> INFO: 41600 events read in total (2851ms).
[15:47:03.448] <TB2> INFO: Test took 3726ms.
[15:47:03.678] <TB2> INFO: PixTestAlive::aliveTest() done
[15:47:03.678] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:47:03.679] <TB2> INFO: ----------------------------------------------------------------------
[15:47:03.679] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:47:03.679] <TB2> INFO: ----------------------------------------------------------------------
[15:47:03.925] <TB2> INFO: Expecting 41600 events.
[15:47:06.896] <TB2> INFO: 41600 events read in total (2379ms).
[15:47:06.896] <TB2> INFO: Test took 3215ms.
[15:47:06.896] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[15:47:07.136] <TB2> INFO: PixTestAlive::maskTest() done
[15:47:07.136] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:47:07.137] <TB2> INFO: ----------------------------------------------------------------------
[15:47:07.137] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:47:07.137] <TB2> INFO: ----------------------------------------------------------------------
[15:47:07.383] <TB2> INFO: Expecting 41600 events.
[15:47:10.893] <TB2> INFO: 41600 events read in total (2918ms).
[15:47:10.893] <TB2> INFO: Test took 3752ms.
[15:47:11.120] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[15:47:11.120] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:47:11.121] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[15:47:11.121] <TB2> INFO: Decoding statistics:
[15:47:11.121] <TB2> INFO: General information:
[15:47:11.121] <TB2> INFO: 16bit words read: 0
[15:47:11.121] <TB2> INFO: valid events total: 0
[15:47:11.121] <TB2> INFO: empty events: 0
[15:47:11.121] <TB2> INFO: valid events with pixels: 0
[15:47:11.121] <TB2> INFO: valid pixel hits: 0
[15:47:11.121] <TB2> INFO: Event errors: 0
[15:47:11.121] <TB2> INFO: start marker: 0
[15:47:11.121] <TB2> INFO: stop marker: 0
[15:47:11.121] <TB2> INFO: overflow: 0
[15:47:11.121] <TB2> INFO: invalid 5bit words: 0
[15:47:11.121] <TB2> INFO: invalid XOR eye diagram: 0
[15:47:11.121] <TB2> INFO: frame (failed synchr.): 0
[15:47:11.121] <TB2> INFO: idle data (no TBM trl): 0
[15:47:11.121] <TB2> INFO: no data (only TBM hdr): 0
[15:47:11.121] <TB2> INFO: TBM errors: 0
[15:47:11.121] <TB2> INFO: flawed TBM headers: 0
[15:47:11.121] <TB2> INFO: flawed TBM trailers: 0
[15:47:11.121] <TB2> INFO: event ID mismatches: 0
[15:47:11.121] <TB2> INFO: ROC errors: 0
[15:47:11.121] <TB2> INFO: missing ROC header(s): 0
[15:47:11.121] <TB2> INFO: misplaced readback start: 0
[15:47:11.121] <TB2> INFO: Pixel decoding errors: 0
[15:47:11.121] <TB2> INFO: pixel data incomplete: 0
[15:47:11.121] <TB2> INFO: pixel address: 0
[15:47:11.121] <TB2> INFO: pulse height fill bit: 0
[15:47:11.121] <TB2> INFO: buffer corruption: 0
[15:47:11.127] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C15.dat
[15:47:11.127] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[15:47:11.127] <TB2> INFO: ######################################################################
[15:47:11.127] <TB2> INFO: PixTestReadback::doTest()
[15:47:11.127] <TB2> INFO: ######################################################################
[15:47:11.127] <TB2> INFO: ----------------------------------------------------------------------
[15:47:11.127] <TB2> INFO: PixTestReadback::CalibrateVd()
[15:47:11.127] <TB2> INFO: ----------------------------------------------------------------------
[15:47:21.106] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C0.dat
[15:47:21.106] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C1.dat
[15:47:21.107] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C2.dat
[15:47:21.107] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C3.dat
[15:47:21.107] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C4.dat
[15:47:21.107] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C5.dat
[15:47:21.107] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C6.dat
[15:47:21.107] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C7.dat
[15:47:21.107] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C8.dat
[15:47:21.107] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C9.dat
[15:47:21.107] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C10.dat
[15:47:21.108] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C11.dat
[15:47:21.108] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C12.dat
[15:47:21.108] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C13.dat
[15:47:21.108] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C14.dat
[15:47:21.108] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C15.dat
[15:47:21.138] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[15:47:21.138] <TB2> INFO: ----------------------------------------------------------------------
[15:47:21.138] <TB2> INFO: PixTestReadback::CalibrateVa()
[15:47:21.138] <TB2> INFO: ----------------------------------------------------------------------
[15:47:31.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C0.dat
[15:47:31.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C1.dat
[15:47:31.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C2.dat
[15:47:31.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C3.dat
[15:47:31.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C4.dat
[15:47:31.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C5.dat
[15:47:31.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C6.dat
[15:47:31.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C7.dat
[15:47:31.063] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C8.dat
[15:47:31.063] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C9.dat
[15:47:31.063] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C10.dat
[15:47:31.063] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C11.dat
[15:47:31.063] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C12.dat
[15:47:31.063] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C13.dat
[15:47:31.063] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C14.dat
[15:47:31.063] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C15.dat
[15:47:31.090] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[15:47:31.090] <TB2> INFO: ----------------------------------------------------------------------
[15:47:31.090] <TB2> INFO: PixTestReadback::readbackVbg()
[15:47:31.090] <TB2> INFO: ----------------------------------------------------------------------
[15:47:38.759] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[15:47:38.759] <TB2> INFO: ----------------------------------------------------------------------
[15:47:38.759] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[15:47:38.759] <TB2> INFO: ----------------------------------------------------------------------
[15:47:38.759] <TB2> INFO: Vbg will be calibrated using Vd calibration
[15:47:38.759] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 159.1calibrated Vbg = 1.16997 :::*/*/*/*/
[15:47:38.759] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 164.4calibrated Vbg = 1.1791 :::*/*/*/*/
[15:47:38.759] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 158.6calibrated Vbg = 1.17903 :::*/*/*/*/
[15:47:38.759] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 150.4calibrated Vbg = 1.17645 :::*/*/*/*/
[15:47:38.759] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 153.2calibrated Vbg = 1.17436 :::*/*/*/*/
[15:47:38.759] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 153.1calibrated Vbg = 1.1794 :::*/*/*/*/
[15:47:38.759] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 153.8calibrated Vbg = 1.1824 :::*/*/*/*/
[15:47:38.759] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 151.6calibrated Vbg = 1.18009 :::*/*/*/*/
[15:47:38.759] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 155.6calibrated Vbg = 1.16824 :::*/*/*/*/
[15:47:38.759] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 154.6calibrated Vbg = 1.17119 :::*/*/*/*/
[15:47:38.759] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 153.6calibrated Vbg = 1.17122 :::*/*/*/*/
[15:47:38.759] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 162.7calibrated Vbg = 1.16636 :::*/*/*/*/
[15:47:38.759] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 150calibrated Vbg = 1.17261 :::*/*/*/*/
[15:47:38.759] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 156.8calibrated Vbg = 1.18013 :::*/*/*/*/
[15:47:38.759] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 154.8calibrated Vbg = 1.17305 :::*/*/*/*/
[15:47:38.760] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 154.1calibrated Vbg = 1.17704 :::*/*/*/*/
[15:47:38.763] <TB2> INFO: ----------------------------------------------------------------------
[15:47:38.763] <TB2> INFO: PixTestReadback::CalibrateIa()
[15:47:38.763] <TB2> INFO: ----------------------------------------------------------------------
[15:50:19.589] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C0.dat
[15:50:19.590] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C1.dat
[15:50:19.590] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C2.dat
[15:50:19.590] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C3.dat
[15:50:19.590] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C4.dat
[15:50:19.590] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C5.dat
[15:50:19.590] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C6.dat
[15:50:19.590] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C7.dat
[15:50:19.590] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C8.dat
[15:50:19.590] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C9.dat
[15:50:19.590] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C10.dat
[15:50:19.591] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C11.dat
[15:50:19.591] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C12.dat
[15:50:19.591] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C13.dat
[15:50:19.591] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C14.dat
[15:50:19.591] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//readbackCal_C15.dat
[15:50:19.623] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[15:50:19.625] <TB2> INFO: PixTestReadback::doTest() done
[15:50:19.626] <TB2> INFO: Decoding statistics:
[15:50:19.626] <TB2> INFO: General information:
[15:50:19.626] <TB2> INFO: 16bit words read: 1536
[15:50:19.626] <TB2> INFO: valid events total: 256
[15:50:19.626] <TB2> INFO: empty events: 256
[15:50:19.626] <TB2> INFO: valid events with pixels: 0
[15:50:19.626] <TB2> INFO: valid pixel hits: 0
[15:50:19.626] <TB2> INFO: Event errors: 0
[15:50:19.626] <TB2> INFO: start marker: 0
[15:50:19.626] <TB2> INFO: stop marker: 0
[15:50:19.626] <TB2> INFO: overflow: 0
[15:50:19.626] <TB2> INFO: invalid 5bit words: 0
[15:50:19.626] <TB2> INFO: invalid XOR eye diagram: 0
[15:50:19.626] <TB2> INFO: frame (failed synchr.): 0
[15:50:19.626] <TB2> INFO: idle data (no TBM trl): 0
[15:50:19.626] <TB2> INFO: no data (only TBM hdr): 0
[15:50:19.626] <TB2> INFO: TBM errors: 0
[15:50:19.626] <TB2> INFO: flawed TBM headers: 0
[15:50:19.626] <TB2> INFO: flawed TBM trailers: 0
[15:50:19.626] <TB2> INFO: event ID mismatches: 0
[15:50:19.626] <TB2> INFO: ROC errors: 0
[15:50:19.626] <TB2> INFO: missing ROC header(s): 0
[15:50:19.626] <TB2> INFO: misplaced readback start: 0
[15:50:19.626] <TB2> INFO: Pixel decoding errors: 0
[15:50:19.626] <TB2> INFO: pixel data incomplete: 0
[15:50:19.626] <TB2> INFO: pixel address: 0
[15:50:19.626] <TB2> INFO: pulse height fill bit: 0
[15:50:19.626] <TB2> INFO: buffer corruption: 0
[15:50:19.679] <TB2> INFO: ######################################################################
[15:50:19.679] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[15:50:19.679] <TB2> INFO: ######################################################################
[15:50:19.681] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[15:50:19.699] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:50:19.699] <TB2> INFO: run 1 of 1
[15:50:19.985] <TB2> INFO: Expecting 3120000 events.
[15:50:51.218] <TB2> INFO: 669140 events read in total (30641ms).











[15:51:21.414] <TB2> INFO: 1333835 events read in total (60837ms).











[15:51:51.360] <TB2> INFO: 1995580 events read in total (90783ms).











[15:52:21.495] <TB2> INFO: 2657335 events read in total (120918ms).











[15:52:42.328] <TB2> INFO: 3120000 events read in total (141751ms).
[15:52:42.405] <TB2> INFO: Test took 142706ms.
[15:53:05.668] <TB2> INFO: PixTestBBMap::doTest() done with 1 decoding errors: , duration: 165 seconds
[15:53:05.668] <TB2> INFO: number of dead bumps (per ROC): 0 0 1 0 0 4 0 0 0 4 0 1 1 0 2 1
[15:53:05.668] <TB2> INFO: separation cut (per ROC): 104 111 103 105 106 103 106 108 111 108 115 115 105 101 106 107
[15:53:05.669] <TB2> INFO: Decoding statistics:
[15:53:05.669] <TB2> INFO: General information:
[15:53:05.669] <TB2> INFO: 16bit words read: 0
[15:53:05.669] <TB2> INFO: valid events total: 0
[15:53:05.669] <TB2> INFO: empty events: 0
[15:53:05.669] <TB2> INFO: valid events with pixels: 0
[15:53:05.669] <TB2> INFO: valid pixel hits: 0
[15:53:05.669] <TB2> INFO: Event errors: 0
[15:53:05.669] <TB2> INFO: start marker: 0
[15:53:05.669] <TB2> INFO: stop marker: 0
[15:53:05.669] <TB2> INFO: overflow: 0
[15:53:05.669] <TB2> INFO: invalid 5bit words: 0
[15:53:05.669] <TB2> INFO: invalid XOR eye diagram: 0
[15:53:05.669] <TB2> INFO: frame (failed synchr.): 0
[15:53:05.669] <TB2> INFO: idle data (no TBM trl): 0
[15:53:05.669] <TB2> INFO: no data (only TBM hdr): 0
[15:53:05.669] <TB2> INFO: TBM errors: 0
[15:53:05.669] <TB2> INFO: flawed TBM headers: 0
[15:53:05.669] <TB2> INFO: flawed TBM trailers: 0
[15:53:05.669] <TB2> INFO: event ID mismatches: 0
[15:53:05.669] <TB2> INFO: ROC errors: 0
[15:53:05.669] <TB2> INFO: missing ROC header(s): 0
[15:53:05.669] <TB2> INFO: misplaced readback start: 0
[15:53:05.669] <TB2> INFO: Pixel decoding errors: 0
[15:53:05.669] <TB2> INFO: pixel data incomplete: 0
[15:53:05.669] <TB2> INFO: pixel address: 0
[15:53:05.669] <TB2> INFO: pulse height fill bit: 0
[15:53:05.669] <TB2> INFO: buffer corruption: 0
[15:53:05.715] <TB2> INFO: ######################################################################
[15:53:05.716] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[15:53:05.716] <TB2> INFO: ######################################################################
[15:53:05.716] <TB2> INFO: ----------------------------------------------------------------------
[15:53:05.716] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[15:53:05.716] <TB2> INFO: ----------------------------------------------------------------------
[15:53:05.716] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[15:53:05.731] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[15:53:05.731] <TB2> INFO: run 1 of 1
[15:53:05.972] <TB2> INFO: Expecting 36608000 events.
[15:53:28.775] <TB2> INFO: 673350 events read in total (22211ms).
[15:53:51.763] <TB2> INFO: 1332150 events read in total (45199ms).
[15:54:14.626] <TB2> INFO: 1992400 events read in total (68063ms).
[15:54:37.389] <TB2> INFO: 2650450 events read in total (90825ms).
[15:55:00.140] <TB2> INFO: 3307050 events read in total (113576ms).
[15:55:22.582] <TB2> INFO: 3962350 events read in total (136018ms).
[15:55:45.533] <TB2> INFO: 4618450 events read in total (158969ms).
[15:56:08.111] <TB2> INFO: 5275350 events read in total (181547ms).
[15:56:30.822] <TB2> INFO: 5930950 events read in total (204258ms).
[15:56:53.411] <TB2> INFO: 6588100 events read in total (226847ms).
[15:57:15.854] <TB2> INFO: 7242000 events read in total (249290ms).
[15:57:38.702] <TB2> INFO: 7898300 events read in total (272138ms).
[15:58:01.493] <TB2> INFO: 8552450 events read in total (294929ms).
[15:58:24.295] <TB2> INFO: 9210800 events read in total (317731ms).
[15:58:46.825] <TB2> INFO: 9864750 events read in total (340261ms).
[15:59:09.332] <TB2> INFO: 10519150 events read in total (362768ms).
[15:59:31.972] <TB2> INFO: 11171300 events read in total (385408ms).
[15:59:54.327] <TB2> INFO: 11824500 events read in total (407763ms).
[16:00:16.763] <TB2> INFO: 12475800 events read in total (430199ms).
[16:00:39.018] <TB2> INFO: 13128400 events read in total (452454ms).
[16:01:01.380] <TB2> INFO: 13782150 events read in total (474816ms).
[16:01:23.770] <TB2> INFO: 14434750 events read in total (497206ms).
[16:01:46.268] <TB2> INFO: 15086150 events read in total (519704ms).
[16:02:08.611] <TB2> INFO: 15737800 events read in total (542047ms).
[16:02:31.202] <TB2> INFO: 16387400 events read in total (564638ms).
[16:02:53.527] <TB2> INFO: 17036750 events read in total (586963ms).
[16:03:15.877] <TB2> INFO: 17687050 events read in total (609313ms).
[16:03:38.277] <TB2> INFO: 18335350 events read in total (631713ms).
[16:04:00.605] <TB2> INFO: 18985250 events read in total (654041ms).
[16:04:22.827] <TB2> INFO: 19633400 events read in total (676263ms).
[16:04:45.225] <TB2> INFO: 20282200 events read in total (698661ms).
[16:05:07.745] <TB2> INFO: 20929500 events read in total (721181ms).
[16:05:30.290] <TB2> INFO: 21577000 events read in total (743726ms).
[16:05:52.619] <TB2> INFO: 22223450 events read in total (766055ms).
[16:06:15.123] <TB2> INFO: 22869250 events read in total (788559ms).
[16:06:37.393] <TB2> INFO: 23514350 events read in total (810829ms).
[16:06:59.808] <TB2> INFO: 24161200 events read in total (833244ms).
[16:07:22.106] <TB2> INFO: 24807350 events read in total (855542ms).
[16:07:44.316] <TB2> INFO: 25455300 events read in total (877752ms).
[16:08:06.813] <TB2> INFO: 26100350 events read in total (900249ms).
[16:08:29.267] <TB2> INFO: 26745050 events read in total (922703ms).
[16:08:51.619] <TB2> INFO: 27390850 events read in total (945055ms).
[16:09:14.254] <TB2> INFO: 28035050 events read in total (967690ms).
[16:09:36.911] <TB2> INFO: 28679450 events read in total (990347ms).
[16:09:59.355] <TB2> INFO: 29323450 events read in total (1012791ms).
[16:10:21.533] <TB2> INFO: 29966650 events read in total (1034969ms).
[16:10:43.775] <TB2> INFO: 30608950 events read in total (1057211ms).
[16:11:06.119] <TB2> INFO: 31253350 events read in total (1079555ms).
[16:11:28.487] <TB2> INFO: 31897200 events read in total (1101923ms).
[16:11:51.010] <TB2> INFO: 32540200 events read in total (1124446ms).
[16:12:13.390] <TB2> INFO: 33183750 events read in total (1146826ms).
[16:12:35.457] <TB2> INFO: 33826500 events read in total (1168893ms).
[16:12:57.705] <TB2> INFO: 34474150 events read in total (1191141ms).
[16:13:19.998] <TB2> INFO: 35116900 events read in total (1213434ms).
[16:13:42.395] <TB2> INFO: 35762450 events read in total (1235831ms).
[16:14:05.067] <TB2> INFO: 36415300 events read in total (1258503ms).
[16:14:11.811] <TB2> INFO: 36608000 events read in total (1265247ms).
[16:14:11.876] <TB2> INFO: Test took 1266145ms.
[16:14:12.334] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:14:13.904] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:14:15.457] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:14:17.051] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:14:18.569] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:14:20.154] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:14:21.695] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:14:23.277] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:14:24.802] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:14:26.329] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:14:27.900] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:14:29.438] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:14:30.965] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:14:32.522] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:14:34.034] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:14:36.420] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[16:14:38.528] <TB2> INFO: PixTestScurves::scurves() done
[16:14:38.528] <TB2> INFO: Vcal mean: 110.98 125.52 109.34 99.78 110.24 106.77 108.24 110.49 120.09 116.51 126.73 116.18 114.58 114.64 121.97 119.34
[16:14:38.528] <TB2> INFO: Vcal RMS: 4.96 7.64 5.60 5.77 4.73 5.30 4.85 5.58 6.61 6.14 7.25 5.51 5.33 5.26 6.19 5.59
[16:14:38.528] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1292 seconds
[16:14:38.528] <TB2> INFO: Decoding statistics:
[16:14:38.528] <TB2> INFO: General information:
[16:14:38.528] <TB2> INFO: 16bit words read: 0
[16:14:38.528] <TB2> INFO: valid events total: 0
[16:14:38.528] <TB2> INFO: empty events: 0
[16:14:38.528] <TB2> INFO: valid events with pixels: 0
[16:14:38.528] <TB2> INFO: valid pixel hits: 0
[16:14:38.528] <TB2> INFO: Event errors: 0
[16:14:38.528] <TB2> INFO: start marker: 0
[16:14:38.528] <TB2> INFO: stop marker: 0
[16:14:38.528] <TB2> INFO: overflow: 0
[16:14:38.528] <TB2> INFO: invalid 5bit words: 0
[16:14:38.528] <TB2> INFO: invalid XOR eye diagram: 0
[16:14:38.528] <TB2> INFO: frame (failed synchr.): 0
[16:14:38.528] <TB2> INFO: idle data (no TBM trl): 0
[16:14:38.528] <TB2> INFO: no data (only TBM hdr): 0
[16:14:38.528] <TB2> INFO: TBM errors: 0
[16:14:38.528] <TB2> INFO: flawed TBM headers: 0
[16:14:38.528] <TB2> INFO: flawed TBM trailers: 0
[16:14:38.528] <TB2> INFO: event ID mismatches: 0
[16:14:38.528] <TB2> INFO: ROC errors: 0
[16:14:38.528] <TB2> INFO: missing ROC header(s): 0
[16:14:38.528] <TB2> INFO: misplaced readback start: 0
[16:14:38.528] <TB2> INFO: Pixel decoding errors: 0
[16:14:38.528] <TB2> INFO: pixel data incomplete: 0
[16:14:38.528] <TB2> INFO: pixel address: 0
[16:14:38.528] <TB2> INFO: pulse height fill bit: 0
[16:14:38.528] <TB2> INFO: buffer corruption: 0
[16:14:38.597] <TB2> INFO: ######################################################################
[16:14:38.597] <TB2> INFO: PixTestTrim::doTest()
[16:14:38.597] <TB2> INFO: ######################################################################
[16:14:38.598] <TB2> INFO: ----------------------------------------------------------------------
[16:14:38.598] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[16:14:38.598] <TB2> INFO: ----------------------------------------------------------------------
[16:14:38.640] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[16:14:38.640] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[16:14:38.653] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:14:38.653] <TB2> INFO: run 1 of 1
[16:14:38.892] <TB2> INFO: Expecting 5025280 events.
[16:15:09.706] <TB2> INFO: 818536 events read in total (30216ms).
[16:15:39.669] <TB2> INFO: 1633712 events read in total (60179ms).
[16:16:09.790] <TB2> INFO: 2445864 events read in total (90301ms).
[16:16:39.693] <TB2> INFO: 3256624 events read in total (120203ms).
[16:17:09.656] <TB2> INFO: 4063696 events read in total (150166ms).
[16:17:39.537] <TB2> INFO: 4871096 events read in total (180047ms).
[16:17:45.526] <TB2> INFO: 5025280 events read in total (186036ms).
[16:17:45.574] <TB2> INFO: Test took 186921ms.
[16:18:03.913] <TB2> INFO: ROC 0 VthrComp = 114
[16:18:03.913] <TB2> INFO: ROC 1 VthrComp = 125
[16:18:03.914] <TB2> INFO: ROC 2 VthrComp = 109
[16:18:03.914] <TB2> INFO: ROC 3 VthrComp = 105
[16:18:03.914] <TB2> INFO: ROC 4 VthrComp = 114
[16:18:03.914] <TB2> INFO: ROC 5 VthrComp = 107
[16:18:03.914] <TB2> INFO: ROC 6 VthrComp = 115
[16:18:03.914] <TB2> INFO: ROC 7 VthrComp = 118
[16:18:03.914] <TB2> INFO: ROC 8 VthrComp = 129
[16:18:03.915] <TB2> INFO: ROC 9 VthrComp = 118
[16:18:03.915] <TB2> INFO: ROC 10 VthrComp = 128
[16:18:03.915] <TB2> INFO: ROC 11 VthrComp = 121
[16:18:03.915] <TB2> INFO: ROC 12 VthrComp = 116
[16:18:03.915] <TB2> INFO: ROC 13 VthrComp = 112
[16:18:03.915] <TB2> INFO: ROC 14 VthrComp = 122
[16:18:03.916] <TB2> INFO: ROC 15 VthrComp = 123
[16:18:04.214] <TB2> INFO: Expecting 41600 events.
[16:18:07.711] <TB2> INFO: 41600 events read in total (2906ms).
[16:18:07.712] <TB2> INFO: Test took 3794ms.
[16:18:07.721] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[16:18:07.721] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[16:18:07.732] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:18:07.732] <TB2> INFO: run 1 of 1
[16:18:08.010] <TB2> INFO: Expecting 5025280 events.
[16:18:34.491] <TB2> INFO: 590216 events read in total (25889ms).
[16:19:00.400] <TB2> INFO: 1179544 events read in total (51799ms).
[16:19:25.741] <TB2> INFO: 1769024 events read in total (77139ms).
[16:19:51.540] <TB2> INFO: 2357792 events read in total (102938ms).
[16:20:17.117] <TB2> INFO: 2944896 events read in total (128515ms).
[16:20:42.393] <TB2> INFO: 3531160 events read in total (153791ms).
[16:21:07.849] <TB2> INFO: 4116048 events read in total (179247ms).
[16:21:33.186] <TB2> INFO: 4700800 events read in total (204584ms).
[16:21:47.289] <TB2> INFO: 5025280 events read in total (218687ms).
[16:21:47.361] <TB2> INFO: Test took 219630ms.
[16:22:10.070] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 60.5334 for pixel 15/4 mean/min/max = 46.2617/31.9301/60.5932
[16:22:10.070] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 67.1669 for pixel 0/18 mean/min/max = 48.3232/29.4334/67.2131
[16:22:10.071] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 65.1014 for pixel 10/0 mean/min/max = 49.2438/33.2189/65.2687
[16:22:10.071] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 62.3666 for pixel 2/75 mean/min/max = 48.0653/33.7506/62.3801
[16:22:10.072] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 59.4027 for pixel 7/61 mean/min/max = 45.6539/31.8836/59.4241
[16:22:10.072] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 63.8064 for pixel 0/78 mean/min/max = 49.2282/34.5327/63.9236
[16:22:10.073] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 58.7458 for pixel 15/14 mean/min/max = 45.5474/32.3443/58.7504
[16:22:10.073] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 59.0003 for pixel 12/73 mean/min/max = 45.0905/31.0945/59.0865
[16:22:10.074] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 64.5067 for pixel 13/24 mean/min/max = 47.8622/31.0909/64.6334
[16:22:10.074] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 62.7466 for pixel 2/73 mean/min/max = 46.803/30.6815/62.9244
[16:22:10.075] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 63.4186 for pixel 36/79 mean/min/max = 47.2554/30.8911/63.6197
[16:22:10.075] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 61.7187 for pixel 6/43 mean/min/max = 46.8226/31.8408/61.8044
[16:22:10.076] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 60.7085 for pixel 48/9 mean/min/max = 46.0303/31.3451/60.7155
[16:22:10.076] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 61.3949 for pixel 47/5 mean/min/max = 46.9655/32.3625/61.5684
[16:22:10.076] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 62.1594 for pixel 8/18 mean/min/max = 46.8439/31.4156/62.2722
[16:22:10.077] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 60.6788 for pixel 16/26 mean/min/max = 46.0099/31.3203/60.6996
[16:22:10.077] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:22:10.166] <TB2> INFO: Expecting 411648 events.
[16:22:19.725] <TB2> INFO: 411648 events read in total (8967ms).
[16:22:19.732] <TB2> INFO: Expecting 411648 events.
[16:22:28.994] <TB2> INFO: 411648 events read in total (8859ms).
[16:22:28.004] <TB2> INFO: Expecting 411648 events.
[16:22:38.339] <TB2> INFO: 411648 events read in total (8932ms).
[16:22:38.357] <TB2> INFO: Expecting 411648 events.
[16:22:47.541] <TB2> INFO: 411648 events read in total (8781ms).
[16:22:47.557] <TB2> INFO: Expecting 411648 events.
[16:22:56.864] <TB2> INFO: 411648 events read in total (8904ms).
[16:22:56.888] <TB2> INFO: Expecting 411648 events.
[16:23:06.281] <TB2> INFO: 411648 events read in total (8990ms).
[16:23:06.303] <TB2> INFO: Expecting 411648 events.
[16:23:15.756] <TB2> INFO: 411648 events read in total (9050ms).
[16:23:15.781] <TB2> INFO: Expecting 411648 events.
[16:23:25.199] <TB2> INFO: 411648 events read in total (9015ms).
[16:23:25.225] <TB2> INFO: Expecting 411648 events.
[16:23:34.634] <TB2> INFO: 411648 events read in total (9006ms).
[16:23:34.665] <TB2> INFO: Expecting 411648 events.
[16:23:44.048] <TB2> INFO: 411648 events read in total (8980ms).
[16:23:44.081] <TB2> INFO: Expecting 411648 events.
[16:23:53.604] <TB2> INFO: 411648 events read in total (9120ms).
[16:23:53.642] <TB2> INFO: Expecting 411648 events.
[16:24:03.075] <TB2> INFO: 411648 events read in total (9030ms).
[16:24:03.124] <TB2> INFO: Expecting 411648 events.
[16:24:12.475] <TB2> INFO: 411648 events read in total (8947ms).
[16:24:12.518] <TB2> INFO: Expecting 411648 events.
[16:24:21.894] <TB2> INFO: 411648 events read in total (8973ms).
[16:24:21.937] <TB2> INFO: Expecting 411648 events.
[16:24:31.364] <TB2> INFO: 411648 events read in total (9024ms).
[16:24:31.412] <TB2> INFO: Expecting 411648 events.
[16:24:40.904] <TB2> INFO: 411648 events read in total (9089ms).
[16:24:40.960] <TB2> INFO: Test took 150883ms.
[16:24:41.804] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[16:24:41.821] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:24:41.821] <TB2> INFO: run 1 of 1
[16:24:42.064] <TB2> INFO: Expecting 5025280 events.
[16:25:08.244] <TB2> INFO: 588352 events read in total (25588ms).
[16:25:34.067] <TB2> INFO: 1175272 events read in total (51411ms).
[16:25:59.860] <TB2> INFO: 1762144 events read in total (77205ms).
[16:26:25.684] <TB2> INFO: 2346280 events read in total (103028ms).
[16:26:51.435] <TB2> INFO: 2932400 events read in total (128779ms).
[16:27:17.119] <TB2> INFO: 3515944 events read in total (154463ms).
[16:27:43.020] <TB2> INFO: 4100752 events read in total (180364ms).
[16:28:08.752] <TB2> INFO: 4686016 events read in total (206096ms).
[16:28:24.097] <TB2> INFO: 5025280 events read in total (221441ms).
[16:28:24.220] <TB2> INFO: Test took 222400ms.
[16:28:47.547] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 0.339977 .. 146.925583
[16:28:47.789] <TB2> INFO: Expecting 208000 events.
[16:28:57.620] <TB2> INFO: 208000 events read in total (9239ms).
[16:28:57.622] <TB2> INFO: Test took 10074ms.
[16:28:57.692] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 0 .. 156 (-1/-1) hits flags = 528 (plus default)
[16:28:57.706] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:28:57.706] <TB2> INFO: run 1 of 1
[16:28:57.987] <TB2> INFO: Expecting 5224960 events.
[16:29:23.895] <TB2> INFO: 585104 events read in total (25317ms).
[16:29:49.461] <TB2> INFO: 1170960 events read in total (50883ms).
[16:30:15.306] <TB2> INFO: 1756328 events read in total (76728ms).
[16:30:40.927] <TB2> INFO: 2341024 events read in total (102349ms).
[16:31:06.868] <TB2> INFO: 2925960 events read in total (128290ms).
[16:31:32.882] <TB2> INFO: 3510912 events read in total (154304ms).
[16:31:58.812] <TB2> INFO: 4095168 events read in total (180234ms).
[16:32:24.367] <TB2> INFO: 4679216 events read in total (205789ms).
[16:32:48.190] <TB2> INFO: 5224960 events read in total (229612ms).
[16:32:48.285] <TB2> INFO: Test took 230580ms.
[16:33:12.185] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 28.445837 .. 46.129671
[16:33:12.446] <TB2> INFO: Expecting 208000 events.
[16:33:22.306] <TB2> INFO: 208000 events read in total (9269ms).
[16:33:22.307] <TB2> INFO: Test took 10120ms.
[16:33:22.355] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 18 .. 56 (-1/-1) hits flags = 528 (plus default)
[16:33:22.368] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:33:22.368] <TB2> INFO: run 1 of 1
[16:33:22.646] <TB2> INFO: Expecting 1297920 events.
[16:33:50.686] <TB2> INFO: 650032 events read in total (27449ms).
[16:34:18.241] <TB2> INFO: 1297920 events read in total (55005ms).
[16:34:18.280] <TB2> INFO: Test took 55913ms.
[16:34:32.505] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 26.058985 .. 47.182854
[16:34:32.747] <TB2> INFO: Expecting 208000 events.
[16:34:42.310] <TB2> INFO: 208000 events read in total (8971ms).
[16:34:42.310] <TB2> INFO: Test took 9804ms.
[16:34:42.359] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 57 (-1/-1) hits flags = 528 (plus default)
[16:34:42.372] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:34:42.372] <TB2> INFO: run 1 of 1
[16:34:42.651] <TB2> INFO: Expecting 1397760 events.
[16:35:10.429] <TB2> INFO: 655696 events read in total (27186ms).
[16:35:37.960] <TB2> INFO: 1310400 events read in total (54717ms).
[16:35:42.062] <TB2> INFO: 1397760 events read in total (58819ms).
[16:35:42.093] <TB2> INFO: Test took 59721ms.
[16:35:55.492] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 24.199419 .. 44.097765
[16:35:55.746] <TB2> INFO: Expecting 208000 events.
[16:36:05.663] <TB2> INFO: 208000 events read in total (9325ms).
[16:36:05.665] <TB2> INFO: Test took 10171ms.
[16:36:05.713] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 54 (-1/-1) hits flags = 528 (plus default)
[16:36:05.726] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:36:05.726] <TB2> INFO: run 1 of 1
[16:36:05.006] <TB2> INFO: Expecting 1364480 events.
[16:36:34.666] <TB2> INFO: 675656 events read in total (28068ms).
[16:37:02.736] <TB2> INFO: 1350920 events read in total (56139ms).
[16:37:03.754] <TB2> INFO: 1364480 events read in total (57157ms).
[16:37:03.783] <TB2> INFO: Test took 58056ms.
[16:37:16.653] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[16:37:16.653] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[16:37:16.667] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[16:37:16.667] <TB2> INFO: run 1 of 1
[16:37:16.962] <TB2> INFO: Expecting 1364480 events.
[16:37:45.263] <TB2> INFO: 667472 events read in total (27709ms).
[16:38:12.716] <TB2> INFO: 1333896 events read in total (55162ms).
[16:38:14.453] <TB2> INFO: 1364480 events read in total (56899ms).
[16:38:14.490] <TB2> INFO: Test took 57823ms.
[16:38:29.728] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C0.dat
[16:38:29.729] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C1.dat
[16:38:29.729] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C2.dat
[16:38:29.729] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C3.dat
[16:38:29.729] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C4.dat
[16:38:29.729] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C5.dat
[16:38:29.729] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C6.dat
[16:38:29.729] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C7.dat
[16:38:29.729] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C8.dat
[16:38:29.729] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C9.dat
[16:38:29.730] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C10.dat
[16:38:29.730] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C11.dat
[16:38:29.730] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C12.dat
[16:38:29.730] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C13.dat
[16:38:29.730] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C14.dat
[16:38:29.730] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C15.dat
[16:38:29.730] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C0.dat
[16:38:29.739] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C1.dat
[16:38:29.748] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C2.dat
[16:38:29.755] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C3.dat
[16:38:29.761] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C4.dat
[16:38:29.769] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C5.dat
[16:38:29.777] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C6.dat
[16:38:29.785] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C7.dat
[16:38:29.792] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C8.dat
[16:38:29.798] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C9.dat
[16:38:29.804] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C10.dat
[16:38:29.810] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C11.dat
[16:38:29.816] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C12.dat
[16:38:29.822] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C13.dat
[16:38:29.828] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C14.dat
[16:38:29.835] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//trimParameters35_C15.dat
[16:38:29.841] <TB2> INFO: PixTestTrim::trimTest() done
[16:38:29.841] <TB2> INFO: vtrim: 148 133 158 128 118 122 137 125 143 128 133 130 128 118 137 119
[16:38:29.841] <TB2> INFO: vthrcomp: 114 125 109 105 114 107 115 118 129 118 128 121 116 112 122 123
[16:38:29.841] <TB2> INFO: vcal mean: 34.92 34.96 35.05 34.97 34.94 35.01 34.90 34.90 34.99 34.93 35.01 34.97 34.92 34.96 34.97 34.96
[16:38:29.841] <TB2> INFO: vcal RMS: 1.11 1.19 1.11 0.96 1.05 0.98 0.98 1.04 1.17 1.13 1.14 1.05 1.06 1.06 1.19 1.09
[16:38:29.841] <TB2> INFO: bits mean: 9.68 9.21 9.01 8.66 9.90 8.16 9.45 9.85 9.38 9.53 9.47 9.53 9.70 9.48 9.42 9.65
[16:38:29.841] <TB2> INFO: bits RMS: 2.60 2.94 2.52 2.67 2.58 2.70 2.70 2.69 2.69 2.74 2.77 2.61 2.66 2.66 2.78 2.71
[16:38:29.848] <TB2> INFO: ----------------------------------------------------------------------
[16:38:29.848] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[16:38:29.848] <TB2> INFO: ----------------------------------------------------------------------
[16:38:29.851] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[16:38:29.864] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:38:29.864] <TB2> INFO: run 1 of 1
[16:38:30.101] <TB2> INFO: Expecting 4160000 events.
[16:39:02.181] <TB2> INFO: 738395 events read in total (31489ms).
[16:39:33.381] <TB2> INFO: 1469955 events read in total (62689ms).
[16:40:04.926] <TB2> INFO: 2197105 events read in total (94234ms).
[16:40:36.292] <TB2> INFO: 2920105 events read in total (125600ms).
[16:41:07.561] <TB2> INFO: 3639670 events read in total (156869ms).
[16:41:30.235] <TB2> INFO: 4160000 events read in total (179543ms).
[16:41:30.303] <TB2> INFO: Test took 180439ms.
[16:41:57.496] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[16:41:57.509] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:41:57.509] <TB2> INFO: run 1 of 1
[16:41:57.747] <TB2> INFO: Expecting 4430400 events.
[16:42:28.908] <TB2> INFO: 700715 events read in total (30569ms).
[16:42:59.134] <TB2> INFO: 1396695 events read in total (60795ms).
[16:43:29.642] <TB2> INFO: 2088760 events read in total (91303ms).
[16:44:00.027] <TB2> INFO: 2777485 events read in total (121688ms).
[16:44:30.458] <TB2> INFO: 3463995 events read in total (152119ms).
[16:45:00.440] <TB2> INFO: 4148320 events read in total (182101ms).
[16:45:12.882] <TB2> INFO: 4430400 events read in total (194543ms).
[16:45:13.019] <TB2> INFO: Test took 195510ms.
[16:45:41.583] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 191 (-1/-1) hits flags = 528 (plus default)
[16:45:41.597] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:45:41.597] <TB2> INFO: run 1 of 1
[16:45:41.875] <TB2> INFO: Expecting 3993600 events.
[16:46:13.996] <TB2> INFO: 726000 events read in total (31529ms).
[16:46:44.692] <TB2> INFO: 1445755 events read in total (62225ms).
[16:47:15.784] <TB2> INFO: 2160785 events read in total (93317ms).
[16:47:46.735] <TB2> INFO: 2871390 events read in total (124268ms).
[16:48:17.394] <TB2> INFO: 3578860 events read in total (154927ms).
[16:48:35.953] <TB2> INFO: 3993600 events read in total (173486ms).
[16:48:36.039] <TB2> INFO: Test took 174442ms.
[16:49:00.659] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 192 (-1/-1) hits flags = 528 (plus default)
[16:49:00.672] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:49:00.672] <TB2> INFO: run 1 of 1
[16:49:00.908] <TB2> INFO: Expecting 4014400 events.
[16:49:32.812] <TB2> INFO: 724845 events read in total (31312ms).
[16:50:03.221] <TB2> INFO: 1443425 events read in total (61721ms).
[16:50:34.180] <TB2> INFO: 2157565 events read in total (92680ms).
[16:51:05.206] <TB2> INFO: 2867450 events read in total (123706ms).
[16:51:35.996] <TB2> INFO: 3574135 events read in total (154496ms).
[16:51:55.150] <TB2> INFO: 4014400 events read in total (173650ms).
[16:51:55.215] <TB2> INFO: Test took 174543ms.
[16:52:19.007] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 191 (-1/-1) hits flags = 528 (plus default)
[16:52:19.021] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:52:19.021] <TB2> INFO: run 1 of 1
[16:52:19.257] <TB2> INFO: Expecting 3993600 events.
[16:52:50.656] <TB2> INFO: 726485 events read in total (30807ms).
[16:53:21.860] <TB2> INFO: 1446685 events read in total (62011ms).
[16:53:53.080] <TB2> INFO: 2162465 events read in total (93231ms).
[16:54:24.182] <TB2> INFO: 2873795 events read in total (124333ms).
[16:54:55.723] <TB2> INFO: 3581810 events read in total (155874ms).
[16:55:13.727] <TB2> INFO: 3993600 events read in total (173878ms).
[16:55:13.791] <TB2> INFO: Test took 174770ms.
[16:55:36.793] <TB2> INFO: PixTestTrim::trimBitTest() done
[16:55:36.795] <TB2> INFO: PixTestTrim::doTest() done, duration: 2458 seconds
[16:55:36.795] <TB2> INFO: Decoding statistics:
[16:55:36.795] <TB2> INFO: General information:
[16:55:36.795] <TB2> INFO: 16bit words read: 0
[16:55:36.795] <TB2> INFO: valid events total: 0
[16:55:36.795] <TB2> INFO: empty events: 0
[16:55:36.795] <TB2> INFO: valid events with pixels: 0
[16:55:36.795] <TB2> INFO: valid pixel hits: 0
[16:55:36.795] <TB2> INFO: Event errors: 0
[16:55:36.795] <TB2> INFO: start marker: 0
[16:55:36.795] <TB2> INFO: stop marker: 0
[16:55:36.795] <TB2> INFO: overflow: 0
[16:55:36.795] <TB2> INFO: invalid 5bit words: 0
[16:55:36.795] <TB2> INFO: invalid XOR eye diagram: 0
[16:55:36.795] <TB2> INFO: frame (failed synchr.): 0
[16:55:36.795] <TB2> INFO: idle data (no TBM trl): 0
[16:55:36.795] <TB2> INFO: no data (only TBM hdr): 0
[16:55:36.795] <TB2> INFO: TBM errors: 0
[16:55:36.795] <TB2> INFO: flawed TBM headers: 0
[16:55:36.795] <TB2> INFO: flawed TBM trailers: 0
[16:55:36.795] <TB2> INFO: event ID mismatches: 0
[16:55:36.795] <TB2> INFO: ROC errors: 0
[16:55:36.795] <TB2> INFO: missing ROC header(s): 0
[16:55:36.795] <TB2> INFO: misplaced readback start: 0
[16:55:36.795] <TB2> INFO: Pixel decoding errors: 0
[16:55:36.795] <TB2> INFO: pixel data incomplete: 0
[16:55:36.795] <TB2> INFO: pixel address: 0
[16:55:36.795] <TB2> INFO: pulse height fill bit: 0
[16:55:36.795] <TB2> INFO: buffer corruption: 0
[16:55:37.507] <TB2> INFO: ######################################################################
[16:55:37.507] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[16:55:37.507] <TB2> INFO: ######################################################################
[16:55:37.787] <TB2> INFO: Expecting 41600 events.
[16:55:41.289] <TB2> INFO: 41600 events read in total (2910ms).
[16:55:41.290] <TB2> INFO: Test took 3782ms.
[16:55:41.737] <TB2> INFO: Expecting 41600 events.
[16:55:45.242] <TB2> INFO: 41600 events read in total (2914ms).
[16:55:45.243] <TB2> INFO: Test took 3749ms.
[16:55:45.534] <TB2> INFO: Expecting 41600 events.
[16:55:49.049] <TB2> INFO: 41600 events read in total (2923ms).
[16:55:49.049] <TB2> INFO: Test took 3780ms.
[16:55:49.340] <TB2> INFO: Expecting 41600 events.
[16:55:53.014] <TB2> INFO: 41600 events read in total (3083ms).
[16:55:53.015] <TB2> INFO: Test took 3941ms.
[16:55:53.304] <TB2> INFO: Expecting 41600 events.
[16:55:56.856] <TB2> INFO: 41600 events read in total (2960ms).
[16:55:56.857] <TB2> INFO: Test took 3818ms.
[16:55:57.147] <TB2> INFO: Expecting 41600 events.
[16:56:00.654] <TB2> INFO: 41600 events read in total (2915ms).
[16:56:00.655] <TB2> INFO: Test took 3774ms.
[16:56:00.945] <TB2> INFO: Expecting 41600 events.
[16:56:04.497] <TB2> INFO: 41600 events read in total (2960ms).
[16:56:04.497] <TB2> INFO: Test took 3817ms.
[16:56:04.787] <TB2> INFO: Expecting 41600 events.
[16:56:08.342] <TB2> INFO: 41600 events read in total (2964ms).
[16:56:08.343] <TB2> INFO: Test took 3821ms.
[16:56:08.635] <TB2> INFO: Expecting 41600 events.
[16:56:12.161] <TB2> INFO: 41600 events read in total (2934ms).
[16:56:12.161] <TB2> INFO: Test took 3790ms.
[16:56:12.451] <TB2> INFO: Expecting 41600 events.
[16:56:16.025] <TB2> INFO: 41600 events read in total (2982ms).
[16:56:16.025] <TB2> INFO: Test took 3839ms.
[16:56:16.316] <TB2> INFO: Expecting 41600 events.
[16:56:19.869] <TB2> INFO: 41600 events read in total (2961ms).
[16:56:19.869] <TB2> INFO: Test took 3817ms.
[16:56:20.158] <TB2> INFO: Expecting 41600 events.
[16:56:23.626] <TB2> INFO: 41600 events read in total (2876ms).
[16:56:23.628] <TB2> INFO: Test took 3734ms.
[16:56:23.920] <TB2> INFO: Expecting 41600 events.
[16:56:27.386] <TB2> INFO: 41600 events read in total (2875ms).
[16:56:27.387] <TB2> INFO: Test took 3732ms.
[16:56:27.676] <TB2> INFO: Expecting 41600 events.
[16:56:31.142] <TB2> INFO: 41600 events read in total (2874ms).
[16:56:31.142] <TB2> INFO: Test took 3731ms.
[16:56:31.432] <TB2> INFO: Expecting 41600 events.
[16:56:34.907] <TB2> INFO: 41600 events read in total (2884ms).
[16:56:34.907] <TB2> INFO: Test took 3741ms.
[16:56:35.197] <TB2> INFO: Expecting 41600 events.
[16:56:38.773] <TB2> INFO: 41600 events read in total (2985ms).
[16:56:38.774] <TB2> INFO: Test took 3842ms.
[16:56:39.065] <TB2> INFO: Expecting 41600 events.
[16:56:42.565] <TB2> INFO: 41600 events read in total (2908ms).
[16:56:42.566] <TB2> INFO: Test took 3766ms.
[16:56:42.855] <TB2> INFO: Expecting 41600 events.
[16:56:46.423] <TB2> INFO: 41600 events read in total (2977ms).
[16:56:46.424] <TB2> INFO: Test took 3833ms.
[16:56:46.713] <TB2> INFO: Expecting 41600 events.
[16:56:50.284] <TB2> INFO: 41600 events read in total (2979ms).
[16:56:50.285] <TB2> INFO: Test took 3836ms.
[16:56:50.574] <TB2> INFO: Expecting 41600 events.
[16:56:54.045] <TB2> INFO: 41600 events read in total (2879ms).
[16:56:54.046] <TB2> INFO: Test took 3737ms.
[16:56:54.335] <TB2> INFO: Expecting 41600 events.
[16:56:57.814] <TB2> INFO: 41600 events read in total (2887ms).
[16:56:57.814] <TB2> INFO: Test took 3743ms.
[16:56:58.103] <TB2> INFO: Expecting 41600 events.
[16:57:01.568] <TB2> INFO: 41600 events read in total (2873ms).
[16:57:01.569] <TB2> INFO: Test took 3731ms.
[16:57:01.857] <TB2> INFO: Expecting 41600 events.
[16:57:05.343] <TB2> INFO: 41600 events read in total (2894ms).
[16:57:05.344] <TB2> INFO: Test took 3751ms.
[16:57:05.633] <TB2> INFO: Expecting 41600 events.
[16:57:09.097] <TB2> INFO: 41600 events read in total (2872ms).
[16:57:09.098] <TB2> INFO: Test took 3729ms.
[16:57:09.387] <TB2> INFO: Expecting 41600 events.
[16:57:12.944] <TB2> INFO: 41600 events read in total (2965ms).
[16:57:12.945] <TB2> INFO: Test took 3823ms.
[16:57:13.245] <TB2> INFO: Expecting 41600 events.
[16:57:16.828] <TB2> INFO: 41600 events read in total (2991ms).
[16:57:16.828] <TB2> INFO: Test took 3859ms.
[16:57:17.118] <TB2> INFO: Expecting 41600 events.
[16:57:20.708] <TB2> INFO: 41600 events read in total (2998ms).
[16:57:20.709] <TB2> INFO: Test took 3857ms.
[16:57:20.999] <TB2> INFO: Expecting 41600 events.
[16:57:24.532] <TB2> INFO: 41600 events read in total (2942ms).
[16:57:24.533] <TB2> INFO: Test took 3799ms.
[16:57:24.823] <TB2> INFO: Expecting 41600 events.
[16:57:28.396] <TB2> INFO: 41600 events read in total (2981ms).
[16:57:28.397] <TB2> INFO: Test took 3840ms.
[16:57:28.692] <TB2> INFO: Expecting 41600 events.
[16:57:32.372] <TB2> INFO: 41600 events read in total (3088ms).
[16:57:32.373] <TB2> INFO: Test took 3946ms.
[16:57:32.688] <TB2> INFO: Expecting 41600 events.
[16:57:36.264] <TB2> INFO: 41600 events read in total (2985ms).
[16:57:36.265] <TB2> INFO: Test took 3863ms.
[16:57:36.554] <TB2> INFO: Expecting 41600 events.
[16:57:40.139] <TB2> INFO: 41600 events read in total (2993ms).
[16:57:40.140] <TB2> INFO: Test took 3851ms.
[16:57:40.432] <TB2> INFO: Expecting 41600 events.
[16:57:44.053] <TB2> INFO: 41600 events read in total (3029ms).
[16:57:44.054] <TB2> INFO: Test took 3887ms.
[16:57:44.344] <TB2> INFO: Expecting 41600 events.
[16:57:47.894] <TB2> INFO: 41600 events read in total (2958ms).
[16:57:47.895] <TB2> INFO: Test took 3817ms.
[16:57:48.185] <TB2> INFO: Expecting 41600 events.
[16:57:51.805] <TB2> INFO: 41600 events read in total (3028ms).
[16:57:51.806] <TB2> INFO: Test took 3887ms.
[16:57:52.096] <TB2> INFO: Expecting 41600 events.
[16:57:55.719] <TB2> INFO: 41600 events read in total (3031ms).
[16:57:55.720] <TB2> INFO: Test took 3890ms.
[16:57:56.010] <TB2> INFO: Expecting 41600 events.
[16:57:59.554] <TB2> INFO: 41600 events read in total (2953ms).
[16:57:59.555] <TB2> INFO: Test took 3811ms.
[16:57:59.846] <TB2> INFO: Expecting 41600 events.
[16:58:03.470] <TB2> INFO: 41600 events read in total (3033ms).
[16:58:03.471] <TB2> INFO: Test took 3891ms.
[16:58:03.761] <TB2> INFO: Expecting 41600 events.
[16:58:07.305] <TB2> INFO: 41600 events read in total (2952ms).
[16:58:07.305] <TB2> INFO: Test took 3809ms.
[16:58:07.596] <TB2> INFO: Expecting 41600 events.
[16:58:11.153] <TB2> INFO: 41600 events read in total (2965ms).
[16:58:11.154] <TB2> INFO: Test took 3824ms.
[16:58:11.443] <TB2> INFO: Expecting 41600 events.
[16:58:15.019] <TB2> INFO: 41600 events read in total (2984ms).
[16:58:15.020] <TB2> INFO: Test took 3842ms.
[16:58:15.309] <TB2> INFO: Expecting 41600 events.
[16:58:18.887] <TB2> INFO: 41600 events read in total (2986ms).
[16:58:18.888] <TB2> INFO: Test took 3844ms.
[16:58:19.180] <TB2> INFO: Expecting 41600 events.
[16:58:22.734] <TB2> INFO: 41600 events read in total (2962ms).
[16:58:22.734] <TB2> INFO: Test took 3819ms.
[16:58:23.024] <TB2> INFO: Expecting 41600 events.
[16:58:26.588] <TB2> INFO: 41600 events read in total (2972ms).
[16:58:26.588] <TB2> INFO: Test took 3829ms.
[16:58:26.881] <TB2> INFO: Expecting 41600 events.
[16:58:30.459] <TB2> INFO: 41600 events read in total (2986ms).
[16:58:30.460] <TB2> INFO: Test took 3844ms.
[16:58:30.753] <TB2> INFO: Expecting 41600 events.
[16:58:34.378] <TB2> INFO: 41600 events read in total (3034ms).
[16:58:34.379] <TB2> INFO: Test took 3892ms.
[16:58:34.669] <TB2> INFO: Expecting 41600 events.
[16:58:38.248] <TB2> INFO: 41600 events read in total (2987ms).
[16:58:38.249] <TB2> INFO: Test took 3846ms.
[16:58:38.540] <TB2> INFO: Expecting 41600 events.
[16:58:42.169] <TB2> INFO: 41600 events read in total (3038ms).
[16:58:42.169] <TB2> INFO: Test took 3895ms.
[16:58:42.474] <TB2> INFO: Expecting 41600 events.
[16:58:46.066] <TB2> INFO: 41600 events read in total (3000ms).
[16:58:46.067] <TB2> INFO: Test took 3873ms.
[16:58:46.358] <TB2> INFO: Expecting 41600 events.
[16:58:49.963] <TB2> INFO: 41600 events read in total (3013ms).
[16:58:49.964] <TB2> INFO: Test took 3872ms.
[16:58:50.269] <TB2> INFO: Expecting 41600 events.
[16:58:53.895] <TB2> INFO: 41600 events read in total (3034ms).
[16:58:53.896] <TB2> INFO: Test took 3906ms.
[16:58:54.186] <TB2> INFO: Expecting 41600 events.
[16:58:57.768] <TB2> INFO: 41600 events read in total (2991ms).
[16:58:57.769] <TB2> INFO: Test took 3848ms.
[16:58:58.061] <TB2> INFO: Expecting 41600 events.
[16:59:01.649] <TB2> INFO: 41600 events read in total (2996ms).
[16:59:01.650] <TB2> INFO: Test took 3854ms.
[16:59:01.944] <TB2> INFO: Expecting 41600 events.
[16:59:05.476] <TB2> INFO: 41600 events read in total (2940ms).
[16:59:05.477] <TB2> INFO: Test took 3798ms.
[16:59:05.773] <TB2> INFO: Expecting 2560 events.
[16:59:06.658] <TB2> INFO: 2560 events read in total (294ms).
[16:59:06.659] <TB2> INFO: Test took 1163ms.
[16:59:06.965] <TB2> INFO: Expecting 2560 events.
[16:59:07.859] <TB2> INFO: 2560 events read in total (302ms).
[16:59:07.859] <TB2> INFO: Test took 1200ms.
[16:59:08.167] <TB2> INFO: Expecting 2560 events.
[16:59:09.052] <TB2> INFO: 2560 events read in total (293ms).
[16:59:09.053] <TB2> INFO: Test took 1193ms.
[16:59:09.360] <TB2> INFO: Expecting 2560 events.
[16:59:10.244] <TB2> INFO: 2560 events read in total (293ms).
[16:59:10.245] <TB2> INFO: Test took 1191ms.
[16:59:10.554] <TB2> INFO: Expecting 2560 events.
[16:59:11.435] <TB2> INFO: 2560 events read in total (289ms).
[16:59:11.435] <TB2> INFO: Test took 1189ms.
[16:59:11.743] <TB2> INFO: Expecting 2560 events.
[16:59:12.629] <TB2> INFO: 2560 events read in total (294ms).
[16:59:12.630] <TB2> INFO: Test took 1194ms.
[16:59:12.939] <TB2> INFO: Expecting 2560 events.
[16:59:13.822] <TB2> INFO: 2560 events read in total (291ms).
[16:59:13.822] <TB2> INFO: Test took 1192ms.
[16:59:14.129] <TB2> INFO: Expecting 2560 events.
[16:59:15.020] <TB2> INFO: 2560 events read in total (299ms).
[16:59:15.020] <TB2> INFO: Test took 1197ms.
[16:59:15.329] <TB2> INFO: Expecting 2560 events.
[16:59:16.218] <TB2> INFO: 2560 events read in total (296ms).
[16:59:16.219] <TB2> INFO: Test took 1198ms.
[16:59:16.525] <TB2> INFO: Expecting 2560 events.
[16:59:17.413] <TB2> INFO: 2560 events read in total (296ms).
[16:59:17.413] <TB2> INFO: Test took 1194ms.
[16:59:17.722] <TB2> INFO: Expecting 2560 events.
[16:59:18.603] <TB2> INFO: 2560 events read in total (289ms).
[16:59:18.603] <TB2> INFO: Test took 1190ms.
[16:59:18.909] <TB2> INFO: Expecting 2560 events.
[16:59:19.799] <TB2> INFO: 2560 events read in total (298ms).
[16:59:19.800] <TB2> INFO: Test took 1196ms.
[16:59:20.107] <TB2> INFO: Expecting 2560 events.
[16:59:20.000] <TB2> INFO: 2560 events read in total (301ms).
[16:59:20.000] <TB2> INFO: Test took 1199ms.
[16:59:21.309] <TB2> INFO: Expecting 2560 events.
[16:59:22.192] <TB2> INFO: 2560 events read in total (291ms).
[16:59:22.192] <TB2> INFO: Test took 1191ms.
[16:59:22.501] <TB2> INFO: Expecting 2560 events.
[16:59:23.393] <TB2> INFO: 2560 events read in total (301ms).
[16:59:23.393] <TB2> INFO: Test took 1201ms.
[16:59:23.701] <TB2> INFO: Expecting 2560 events.
[16:59:24.590] <TB2> INFO: 2560 events read in total (297ms).
[16:59:24.590] <TB2> INFO: Test took 1196ms.
[16:59:24.897] <TB2> INFO: Expecting 655360 events.
[16:59:45.971] <TB2> INFO: 531260 events read in total (20482ms).
[16:59:50.991] <TB2> INFO: 655360 events read in total (25502ms).
[16:59:51.007] <TB2> INFO: Test took 26413ms.
[16:59:51.036] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:59:51.298] <TB2> INFO: Expecting 655360 events.
[17:00:06.068] <TB2> INFO: 655360 events read in total (14178ms).
[17:00:06.082] <TB2> INFO: Expecting 655360 events.
[17:00:20.563] <TB2> INFO: 655360 events read in total (14078ms).
[17:00:20.581] <TB2> INFO: Expecting 655360 events.
[17:00:35.557] <TB2> INFO: 655360 events read in total (14573ms).
[17:00:35.579] <TB2> INFO: Expecting 655360 events.
[17:00:50.265] <TB2> INFO: 655360 events read in total (14283ms).
[17:00:50.292] <TB2> INFO: Expecting 655360 events.
[17:01:05.008] <TB2> INFO: 655360 events read in total (14313ms).
[17:01:05.042] <TB2> INFO: Expecting 655360 events.
[17:01:19.475] <TB2> INFO: 655360 events read in total (14030ms).
[17:01:19.512] <TB2> INFO: Expecting 655360 events.
[17:01:34.177] <TB2> INFO: 655360 events read in total (14262ms).
[17:01:34.221] <TB2> INFO: Expecting 655360 events.
[17:01:48.824] <TB2> INFO: 655360 events read in total (14200ms).
[17:01:48.870] <TB2> INFO: Expecting 655360 events.
[17:02:03.414] <TB2> INFO: 655360 events read in total (14141ms).
[17:02:03.475] <TB2> INFO: Expecting 655360 events.
[17:02:18.009] <TB2> INFO: 655360 events read in total (14131ms).
[17:02:18.067] <TB2> INFO: Expecting 655360 events.
[17:02:32.693] <TB2> INFO: 655360 events read in total (14223ms).
[17:02:32.765] <TB2> INFO: Expecting 655360 events.
[17:02:47.311] <TB2> INFO: 655360 events read in total (14143ms).
[17:02:47.380] <TB2> INFO: Expecting 655360 events.
[17:03:02.098] <TB2> INFO: 655360 events read in total (14314ms).
[17:03:02.203] <TB2> INFO: Expecting 655360 events.
[17:03:16.806] <TB2> INFO: 655360 events read in total (14200ms).
[17:03:16.898] <TB2> INFO: Expecting 655360 events.
[17:03:31.364] <TB2> INFO: 655360 events read in total (14063ms).
[17:03:31.529] <TB2> INFO: Expecting 655360 events.
[17:03:46.081] <TB2> INFO: 655360 events read in total (14148ms).
[17:03:46.186] <TB2> INFO: Test took 235150ms.
[17:03:46.351] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:46.357] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:03:46.363] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:46.369] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:03:46.374] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[17:03:46.380] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[17:03:46.386] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:46.392] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:46.398] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:03:46.404] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[17:03:46.410] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[17:03:46.416] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[17:03:46.422] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[17:03:46.428] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:46.434] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:46.440] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:46.446] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:46.452] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:03:46.457] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[17:03:46.463] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[17:03:46.469] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[17:03:46.475] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[17:03:46.481] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:46.487] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:46.493] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:03:46.499] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[17:03:46.505] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[17:03:46.510] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[17:03:46.517] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:46.523] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:03:46.529] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:46.535] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:46.541] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:46.547] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:46.553] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[17:03:46.558] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:46.598] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C0.dat
[17:03:46.598] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C1.dat
[17:03:46.598] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C2.dat
[17:03:46.599] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C3.dat
[17:03:46.599] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C4.dat
[17:03:46.599] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C5.dat
[17:03:46.600] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C6.dat
[17:03:46.600] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C7.dat
[17:03:46.600] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C8.dat
[17:03:46.600] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C9.dat
[17:03:46.601] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C10.dat
[17:03:46.601] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C11.dat
[17:03:46.601] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C12.dat
[17:03:46.602] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C13.dat
[17:03:46.602] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C14.dat
[17:03:46.602] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//dacParameters35_C15.dat
[17:03:46.845] <TB2> INFO: Expecting 41600 events.
[17:03:50.020] <TB2> INFO: 41600 events read in total (2584ms).
[17:03:50.021] <TB2> INFO: Test took 3415ms.
[17:03:50.479] <TB2> INFO: Expecting 41600 events.
[17:03:53.555] <TB2> INFO: 41600 events read in total (2484ms).
[17:03:53.556] <TB2> INFO: Test took 3321ms.
[17:03:54.011] <TB2> INFO: Expecting 41600 events.
[17:03:57.171] <TB2> INFO: 41600 events read in total (2568ms).
[17:03:57.172] <TB2> INFO: Test took 3402ms.
[17:03:57.388] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:03:57.477] <TB2> INFO: Expecting 2560 events.
[17:03:58.360] <TB2> INFO: 2560 events read in total (292ms).
[17:03:58.361] <TB2> INFO: Test took 973ms.
[17:03:58.364] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:03:58.669] <TB2> INFO: Expecting 2560 events.
[17:03:59.561] <TB2> INFO: 2560 events read in total (300ms).
[17:03:59.561] <TB2> INFO: Test took 1197ms.
[17:03:59.566] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:03:59.869] <TB2> INFO: Expecting 2560 events.
[17:04:00.754] <TB2> INFO: 2560 events read in total (294ms).
[17:04:00.755] <TB2> INFO: Test took 1189ms.
[17:04:00.760] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:01.063] <TB2> INFO: Expecting 2560 events.
[17:04:01.955] <TB2> INFO: 2560 events read in total (300ms).
[17:04:01.955] <TB2> INFO: Test took 1195ms.
[17:04:01.959] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:02.264] <TB2> INFO: Expecting 2560 events.
[17:04:03.159] <TB2> INFO: 2560 events read in total (304ms).
[17:04:03.160] <TB2> INFO: Test took 1201ms.
[17:04:03.163] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:03.467] <TB2> INFO: Expecting 2560 events.
[17:04:04.360] <TB2> INFO: 2560 events read in total (301ms).
[17:04:04.360] <TB2> INFO: Test took 1197ms.
[17:04:04.363] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:04.668] <TB2> INFO: Expecting 2560 events.
[17:04:05.559] <TB2> INFO: 2560 events read in total (299ms).
[17:04:05.559] <TB2> INFO: Test took 1196ms.
[17:04:05.561] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:05.868] <TB2> INFO: Expecting 2560 events.
[17:04:06.760] <TB2> INFO: 2560 events read in total (300ms).
[17:04:06.760] <TB2> INFO: Test took 1199ms.
[17:04:06.763] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:07.068] <TB2> INFO: Expecting 2560 events.
[17:04:07.953] <TB2> INFO: 2560 events read in total (294ms).
[17:04:07.954] <TB2> INFO: Test took 1191ms.
[17:04:07.957] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:08.262] <TB2> INFO: Expecting 2560 events.
[17:04:09.144] <TB2> INFO: 2560 events read in total (291ms).
[17:04:09.145] <TB2> INFO: Test took 1189ms.
[17:04:09.148] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:09.454] <TB2> INFO: Expecting 2560 events.
[17:04:10.337] <TB2> INFO: 2560 events read in total (291ms).
[17:04:10.338] <TB2> INFO: Test took 1190ms.
[17:04:10.340] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:10.646] <TB2> INFO: Expecting 2560 events.
[17:04:11.525] <TB2> INFO: 2560 events read in total (287ms).
[17:04:11.526] <TB2> INFO: Test took 1186ms.
[17:04:11.528] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:11.834] <TB2> INFO: Expecting 2560 events.
[17:04:12.719] <TB2> INFO: 2560 events read in total (293ms).
[17:04:12.720] <TB2> INFO: Test took 1192ms.
[17:04:12.723] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:13.028] <TB2> INFO: Expecting 2560 events.
[17:04:13.917] <TB2> INFO: 2560 events read in total (297ms).
[17:04:13.917] <TB2> INFO: Test took 1194ms.
[17:04:13.921] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:14.225] <TB2> INFO: Expecting 2560 events.
[17:04:15.113] <TB2> INFO: 2560 events read in total (296ms).
[17:04:15.113] <TB2> INFO: Test took 1193ms.
[17:04:15.117] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:15.420] <TB2> INFO: Expecting 2560 events.
[17:04:16.303] <TB2> INFO: 2560 events read in total (291ms).
[17:04:16.304] <TB2> INFO: Test took 1188ms.
[17:04:16.307] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:16.613] <TB2> INFO: Expecting 2560 events.
[17:04:17.501] <TB2> INFO: 2560 events read in total (296ms).
[17:04:17.501] <TB2> INFO: Test took 1195ms.
[17:04:17.505] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:17.809] <TB2> INFO: Expecting 2560 events.
[17:04:18.700] <TB2> INFO: 2560 events read in total (300ms).
[17:04:18.701] <TB2> INFO: Test took 1196ms.
[17:04:18.704] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:19.008] <TB2> INFO: Expecting 2560 events.
[17:04:19.899] <TB2> INFO: 2560 events read in total (300ms).
[17:04:19.899] <TB2> INFO: Test took 1195ms.
[17:04:19.901] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:20.208] <TB2> INFO: Expecting 2560 events.
[17:04:21.090] <TB2> INFO: 2560 events read in total (290ms).
[17:04:21.090] <TB2> INFO: Test took 1189ms.
[17:04:21.093] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:21.398] <TB2> INFO: Expecting 2560 events.
[17:04:22.288] <TB2> INFO: 2560 events read in total (298ms).
[17:04:22.288] <TB2> INFO: Test took 1195ms.
[17:04:22.291] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:22.596] <TB2> INFO: Expecting 2560 events.
[17:04:23.485] <TB2> INFO: 2560 events read in total (297ms).
[17:04:23.485] <TB2> INFO: Test took 1194ms.
[17:04:23.487] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:23.794] <TB2> INFO: Expecting 2560 events.
[17:04:24.679] <TB2> INFO: 2560 events read in total (293ms).
[17:04:24.680] <TB2> INFO: Test took 1193ms.
[17:04:24.683] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:24.988] <TB2> INFO: Expecting 2560 events.
[17:04:25.874] <TB2> INFO: 2560 events read in total (294ms).
[17:04:25.874] <TB2> INFO: Test took 1191ms.
[17:04:25.877] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:26.183] <TB2> INFO: Expecting 2560 events.
[17:04:27.066] <TB2> INFO: 2560 events read in total (292ms).
[17:04:27.066] <TB2> INFO: Test took 1189ms.
[17:04:27.070] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:27.374] <TB2> INFO: Expecting 2560 events.
[17:04:28.258] <TB2> INFO: 2560 events read in total (292ms).
[17:04:28.259] <TB2> INFO: Test took 1189ms.
[17:04:28.261] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:28.567] <TB2> INFO: Expecting 2560 events.
[17:04:29.463] <TB2> INFO: 2560 events read in total (304ms).
[17:04:29.463] <TB2> INFO: Test took 1202ms.
[17:04:29.466] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:29.772] <TB2> INFO: Expecting 2560 events.
[17:04:30.667] <TB2> INFO: 2560 events read in total (303ms).
[17:04:30.667] <TB2> INFO: Test took 1202ms.
[17:04:30.671] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:30.975] <TB2> INFO: Expecting 2560 events.
[17:04:31.862] <TB2> INFO: 2560 events read in total (295ms).
[17:04:31.862] <TB2> INFO: Test took 1191ms.
[17:04:31.867] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:32.171] <TB2> INFO: Expecting 2560 events.
[17:04:33.064] <TB2> INFO: 2560 events read in total (302ms).
[17:04:33.065] <TB2> INFO: Test took 1198ms.
[17:04:33.070] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:33.371] <TB2> INFO: Expecting 2560 events.
[17:04:34.262] <TB2> INFO: 2560 events read in total (299ms).
[17:04:34.262] <TB2> INFO: Test took 1193ms.
[17:04:34.265] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:34.572] <TB2> INFO: Expecting 2560 events.
[17:04:35.458] <TB2> INFO: 2560 events read in total (294ms).
[17:04:35.458] <TB2> INFO: Test took 1193ms.
[17:04:35.938] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 538 seconds
[17:04:35.938] <TB2> INFO: PH scale (per ROC): 50 37 39 41 49 56 56 44 39 51 37 57 48 47 34 48
[17:04:35.938] <TB2> INFO: PH offset (per ROC): 123 91 105 119 123 116 120 123 95 131 97 131 131 135 98 130
[17:04:35.948] <TB2> INFO: Decoding statistics:
[17:04:35.948] <TB2> INFO: General information:
[17:04:35.948] <TB2> INFO: 16bit words read: 127888
[17:04:35.948] <TB2> INFO: valid events total: 20480
[17:04:35.948] <TB2> INFO: empty events: 17976
[17:04:35.948] <TB2> INFO: valid events with pixels: 2504
[17:04:35.949] <TB2> INFO: valid pixel hits: 2504
[17:04:35.949] <TB2> INFO: Event errors: 0
[17:04:35.949] <TB2> INFO: start marker: 0
[17:04:35.949] <TB2> INFO: stop marker: 0
[17:04:35.949] <TB2> INFO: overflow: 0
[17:04:35.949] <TB2> INFO: invalid 5bit words: 0
[17:04:35.949] <TB2> INFO: invalid XOR eye diagram: 0
[17:04:35.949] <TB2> INFO: frame (failed synchr.): 0
[17:04:35.949] <TB2> INFO: idle data (no TBM trl): 0
[17:04:35.949] <TB2> INFO: no data (only TBM hdr): 0
[17:04:35.949] <TB2> INFO: TBM errors: 0
[17:04:35.949] <TB2> INFO: flawed TBM headers: 0
[17:04:35.949] <TB2> INFO: flawed TBM trailers: 0
[17:04:35.949] <TB2> INFO: event ID mismatches: 0
[17:04:35.949] <TB2> INFO: ROC errors: 0
[17:04:35.949] <TB2> INFO: missing ROC header(s): 0
[17:04:35.949] <TB2> INFO: misplaced readback start: 0
[17:04:35.949] <TB2> INFO: Pixel decoding errors: 0
[17:04:35.949] <TB2> INFO: pixel data incomplete: 0
[17:04:35.949] <TB2> INFO: pixel address: 0
[17:04:35.949] <TB2> INFO: pulse height fill bit: 0
[17:04:35.949] <TB2> INFO: buffer corruption: 0
[17:04:36.114] <TB2> INFO: ######################################################################
[17:04:36.114] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[17:04:36.114] <TB2> INFO: ######################################################################
[17:04:36.131] <TB2> INFO: scanning low vcal = 10
[17:04:36.371] <TB2> INFO: Expecting 41600 events.
[17:04:39.981] <TB2> INFO: 41600 events read in total (3018ms).
[17:04:39.982] <TB2> INFO: Test took 3851ms.
[17:04:39.984] <TB2> INFO: scanning low vcal = 20
[17:04:40.279] <TB2> INFO: Expecting 41600 events.
[17:04:43.860] <TB2> INFO: 41600 events read in total (2989ms).
[17:04:43.861] <TB2> INFO: Test took 3877ms.
[17:04:43.863] <TB2> INFO: scanning low vcal = 30
[17:04:44.157] <TB2> INFO: Expecting 41600 events.
[17:04:47.852] <TB2> INFO: 41600 events read in total (3103ms).
[17:04:47.853] <TB2> INFO: Test took 3990ms.
[17:04:47.856] <TB2> INFO: scanning low vcal = 40
[17:04:48.133] <TB2> INFO: Expecting 41600 events.
[17:04:52.121] <TB2> INFO: 41600 events read in total (3396ms).
[17:04:52.122] <TB2> INFO: Test took 4266ms.
[17:04:52.125] <TB2> INFO: scanning low vcal = 50
[17:04:52.403] <TB2> INFO: Expecting 41600 events.
[17:04:56.383] <TB2> INFO: 41600 events read in total (3388ms).
[17:04:56.383] <TB2> INFO: Test took 4257ms.
[17:04:56.387] <TB2> INFO: scanning low vcal = 60
[17:04:56.664] <TB2> INFO: Expecting 41600 events.
[17:05:00.656] <TB2> INFO: 41600 events read in total (3401ms).
[17:05:00.657] <TB2> INFO: Test took 4270ms.
[17:05:00.660] <TB2> INFO: scanning low vcal = 70
[17:05:00.937] <TB2> INFO: Expecting 41600 events.
[17:05:05.018] <TB2> INFO: 41600 events read in total (3489ms).
[17:05:05.019] <TB2> INFO: Test took 4359ms.
[17:05:05.022] <TB2> INFO: scanning low vcal = 80
[17:05:05.304] <TB2> INFO: Expecting 41600 events.
[17:05:09.335] <TB2> INFO: 41600 events read in total (3439ms).
[17:05:09.336] <TB2> INFO: Test took 4314ms.
[17:05:09.339] <TB2> INFO: scanning low vcal = 90
[17:05:09.616] <TB2> INFO: Expecting 41600 events.
[17:05:13.651] <TB2> INFO: 41600 events read in total (3443ms).
[17:05:13.652] <TB2> INFO: Test took 4313ms.
[17:05:13.656] <TB2> INFO: scanning low vcal = 100
[17:05:13.932] <TB2> INFO: Expecting 41600 events.
[17:05:17.949] <TB2> INFO: 41600 events read in total (3425ms).
[17:05:17.950] <TB2> INFO: Test took 4294ms.
[17:05:17.953] <TB2> INFO: scanning low vcal = 110
[17:05:18.230] <TB2> INFO: Expecting 41600 events.
[17:05:22.230] <TB2> INFO: 41600 events read in total (3408ms).
[17:05:22.230] <TB2> INFO: Test took 4277ms.
[17:05:22.234] <TB2> INFO: scanning low vcal = 120
[17:05:22.511] <TB2> INFO: Expecting 41600 events.
[17:05:26.529] <TB2> INFO: 41600 events read in total (3426ms).
[17:05:26.530] <TB2> INFO: Test took 4296ms.
[17:05:26.534] <TB2> INFO: scanning low vcal = 130
[17:05:26.814] <TB2> INFO: Expecting 41600 events.
[17:05:30.809] <TB2> INFO: 41600 events read in total (3403ms).
[17:05:30.810] <TB2> INFO: Test took 4276ms.
[17:05:30.814] <TB2> INFO: scanning low vcal = 140
[17:05:31.091] <TB2> INFO: Expecting 41600 events.
[17:05:35.111] <TB2> INFO: 41600 events read in total (3428ms).
[17:05:35.112] <TB2> INFO: Test took 4298ms.
[17:05:35.115] <TB2> INFO: scanning low vcal = 150
[17:05:35.392] <TB2> INFO: Expecting 41600 events.
[17:05:39.366] <TB2> INFO: 41600 events read in total (3382ms).
[17:05:39.367] <TB2> INFO: Test took 4252ms.
[17:05:39.370] <TB2> INFO: scanning low vcal = 160
[17:05:39.646] <TB2> INFO: Expecting 41600 events.
[17:05:43.617] <TB2> INFO: 41600 events read in total (3379ms).
[17:05:43.617] <TB2> INFO: Test took 4246ms.
[17:05:43.621] <TB2> INFO: scanning low vcal = 170
[17:05:43.898] <TB2> INFO: Expecting 41600 events.
[17:05:47.895] <TB2> INFO: 41600 events read in total (3406ms).
[17:05:47.896] <TB2> INFO: Test took 4275ms.
[17:05:47.901] <TB2> INFO: scanning low vcal = 180
[17:05:48.176] <TB2> INFO: Expecting 41600 events.
[17:05:52.178] <TB2> INFO: 41600 events read in total (3410ms).
[17:05:52.179] <TB2> INFO: Test took 4277ms.
[17:05:52.182] <TB2> INFO: scanning low vcal = 190
[17:05:52.459] <TB2> INFO: Expecting 41600 events.
[17:05:56.413] <TB2> INFO: 41600 events read in total (3363ms).
[17:05:56.414] <TB2> INFO: Test took 4232ms.
[17:05:56.417] <TB2> INFO: scanning low vcal = 200
[17:05:56.694] <TB2> INFO: Expecting 41600 events.
[17:06:00.707] <TB2> INFO: 41600 events read in total (3421ms).
[17:06:00.708] <TB2> INFO: Test took 4291ms.
[17:06:00.711] <TB2> INFO: scanning low vcal = 210
[17:06:00.989] <TB2> INFO: Expecting 41600 events.
[17:06:05.020] <TB2> INFO: 41600 events read in total (3439ms).
[17:06:05.021] <TB2> INFO: Test took 4309ms.
[17:06:05.024] <TB2> INFO: scanning low vcal = 220
[17:06:05.301] <TB2> INFO: Expecting 41600 events.
[17:06:09.287] <TB2> INFO: 41600 events read in total (3394ms).
[17:06:09.288] <TB2> INFO: Test took 4264ms.
[17:06:09.291] <TB2> INFO: scanning low vcal = 230
[17:06:09.568] <TB2> INFO: Expecting 41600 events.
[17:06:13.562] <TB2> INFO: 41600 events read in total (3402ms).
[17:06:13.562] <TB2> INFO: Test took 4271ms.
[17:06:13.565] <TB2> INFO: scanning low vcal = 240
[17:06:13.845] <TB2> INFO: Expecting 41600 events.
[17:06:17.868] <TB2> INFO: 41600 events read in total (3431ms).
[17:06:17.869] <TB2> INFO: Test took 4303ms.
[17:06:17.873] <TB2> INFO: scanning low vcal = 250
[17:06:18.150] <TB2> INFO: Expecting 41600 events.
[17:06:22.167] <TB2> INFO: 41600 events read in total (3425ms).
[17:06:22.168] <TB2> INFO: Test took 4295ms.
[17:06:22.172] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[17:06:22.453] <TB2> INFO: Expecting 41600 events.
[17:06:26.469] <TB2> INFO: 41600 events read in total (3424ms).
[17:06:26.470] <TB2> INFO: Test took 4297ms.
[17:06:26.474] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[17:06:26.750] <TB2> INFO: Expecting 41600 events.
[17:06:30.771] <TB2> INFO: 41600 events read in total (3429ms).
[17:06:30.772] <TB2> INFO: Test took 4298ms.
[17:06:30.776] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[17:06:31.052] <TB2> INFO: Expecting 41600 events.
[17:06:35.063] <TB2> INFO: 41600 events read in total (3419ms).
[17:06:35.063] <TB2> INFO: Test took 4287ms.
[17:06:35.067] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[17:06:35.344] <TB2> INFO: Expecting 41600 events.
[17:06:39.331] <TB2> INFO: 41600 events read in total (3395ms).
[17:06:39.332] <TB2> INFO: Test took 4265ms.
[17:06:39.335] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[17:06:39.611] <TB2> INFO: Expecting 41600 events.
[17:06:43.609] <TB2> INFO: 41600 events read in total (3406ms).
[17:06:43.609] <TB2> INFO: Test took 4274ms.
[17:06:44.064] <TB2> INFO: PixTestGainPedestal::measure() done
[17:07:18.917] <TB2> INFO: PixTestGainPedestal::fit() done
[17:07:18.917] <TB2> INFO: non-linearity mean: 0.972 0.950 0.930 0.920 0.978 0.978 0.980 0.917 0.886 0.979 0.929 0.979 0.971 0.973 0.965 0.976
[17:07:18.917] <TB2> INFO: non-linearity RMS: 0.004 0.189 0.156 0.080 0.003 0.004 0.005 0.069 0.097 0.003 0.142 0.003 0.006 0.006 0.170 0.003
[17:07:18.917] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[17:07:18.934] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[17:07:18.948] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[17:07:18.965] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[17:07:18.980] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[17:07:18.995] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[17:07:19.009] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[17:07:19.023] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[17:07:19.038] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[17:07:19.053] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[17:07:19.067] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[17:07:19.082] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[17:07:19.097] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[17:07:19.112] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[17:07:19.126] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[17:07:19.141] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1050_FullQualification_2016-10-23_14h52m_1477227153//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[17:07:19.155] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 163 seconds
[17:07:19.155] <TB2> INFO: Decoding statistics:
[17:07:19.155] <TB2> INFO: General information:
[17:07:19.155] <TB2> INFO: 16bit words read: 3327890
[17:07:19.155] <TB2> INFO: valid events total: 332800
[17:07:19.155] <TB2> INFO: empty events: 0
[17:07:19.155] <TB2> INFO: valid events with pixels: 332800
[17:07:19.156] <TB2> INFO: valid pixel hits: 665545
[17:07:19.156] <TB2> INFO: Event errors: 0
[17:07:19.156] <TB2> INFO: start marker: 0
[17:07:19.156] <TB2> INFO: stop marker: 0
[17:07:19.156] <TB2> INFO: overflow: 0
[17:07:19.156] <TB2> INFO: invalid 5bit words: 0
[17:07:19.156] <TB2> INFO: invalid XOR eye diagram: 0
[17:07:19.156] <TB2> INFO: frame (failed synchr.): 0
[17:07:19.156] <TB2> INFO: idle data (no TBM trl): 0
[17:07:19.156] <TB2> INFO: no data (only TBM hdr): 0
[17:07:19.156] <TB2> INFO: TBM errors: 0
[17:07:19.156] <TB2> INFO: flawed TBM headers: 0
[17:07:19.156] <TB2> INFO: flawed TBM trailers: 0
[17:07:19.156] <TB2> INFO: event ID mismatches: 0
[17:07:19.156] <TB2> INFO: ROC errors: 0
[17:07:19.156] <TB2> INFO: missing ROC header(s): 0
[17:07:19.156] <TB2> INFO: misplaced readback start: 0
[17:07:19.156] <TB2> INFO: Pixel decoding errors: 0
[17:07:19.156] <TB2> INFO: pixel data incomplete: 0
[17:07:19.156] <TB2> INFO: pixel address: 0
[17:07:19.156] <TB2> INFO: pulse height fill bit: 0
[17:07:19.156] <TB2> INFO: buffer corruption: 0
[17:07:19.180] <TB2> INFO: Decoding statistics:
[17:07:19.180] <TB2> INFO: General information:
[17:07:19.180] <TB2> INFO: 16bit words read: 3457314
[17:07:19.180] <TB2> INFO: valid events total: 353536
[17:07:19.180] <TB2> INFO: empty events: 18232
[17:07:19.180] <TB2> INFO: valid events with pixels: 335304
[17:07:19.180] <TB2> INFO: valid pixel hits: 668049
[17:07:19.180] <TB2> INFO: Event errors: 0
[17:07:19.180] <TB2> INFO: start marker: 0
[17:07:19.180] <TB2> INFO: stop marker: 0
[17:07:19.180] <TB2> INFO: overflow: 0
[17:07:19.180] <TB2> INFO: invalid 5bit words: 0
[17:07:19.180] <TB2> INFO: invalid XOR eye diagram: 0
[17:07:19.180] <TB2> INFO: frame (failed synchr.): 0
[17:07:19.180] <TB2> INFO: idle data (no TBM trl): 0
[17:07:19.180] <TB2> INFO: no data (only TBM hdr): 0
[17:07:19.180] <TB2> INFO: TBM errors: 0
[17:07:19.180] <TB2> INFO: flawed TBM headers: 0
[17:07:19.180] <TB2> INFO: flawed TBM trailers: 0
[17:07:19.180] <TB2> INFO: event ID mismatches: 0
[17:07:19.180] <TB2> INFO: ROC errors: 0
[17:07:19.180] <TB2> INFO: missing ROC header(s): 0
[17:07:19.180] <TB2> INFO: misplaced readback start: 0
[17:07:19.180] <TB2> INFO: Pixel decoding errors: 0
[17:07:19.180] <TB2> INFO: pixel data incomplete: 0
[17:07:19.180] <TB2> INFO: pixel address: 0
[17:07:19.180] <TB2> INFO: pulse height fill bit: 0
[17:07:19.181] <TB2> INFO: buffer corruption: 0
[17:07:19.181] <TB2> INFO: enter test to run
[17:07:19.181] <TB2> INFO: test: exit no parameter change
[17:07:19.322] <TB2> QUIET: Connection to board 149 closed.
[17:07:19.324] <TB2> INFO: pXar: this is the end, my friend