[09:44:20.531] <TB1> INFO: *** Welcome to pxar ***
[09:44:20.531] <TB1> INFO: *** Today: 2016/11/15
[09:44:20.538] <TB1> INFO: *** Version: c8ba-dirty
[09:44:20.538] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C15.dat
[09:44:20.538] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//tbmParameters_C1b.dat
[09:44:20.538] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//defaultMaskFile.dat
[09:44:20.538] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters_C15.dat
[09:44:20.601] <TB1> INFO: clk: 4
[09:44:20.601] <TB1> INFO: ctr: 4
[09:44:20.601] <TB1> INFO: sda: 19
[09:44:20.601] <TB1> INFO: tin: 9
[09:44:20.601] <TB1> INFO: level: 15
[09:44:20.601] <TB1> INFO: triggerdelay: 0
[09:44:20.601] <TB1> QUIET: Instanciating API for pxar v2.7.6+77~g4811f5c
[09:44:20.601] <TB1> INFO: Log level: INFO
[09:44:20.610] <TB1> INFO: Found DTB DTB_WXC03A
[09:44:20.621] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[09:44:20.623] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
------------------------------------------------------
[09:44:20.625] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[09:44:22.185] <TB1> INFO: DUT info:
[09:44:22.185] <TB1> INFO: The DUT currently contains the following objects:
[09:44:22.185] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[09:44:22.185] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:44:22.185] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:44:22.185] <TB1> INFO: TBM Core alpha (2): 7 registers set
[09:44:22.185] <TB1> INFO: TBM Core beta (3): 7 registers set
[09:44:22.185] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[09:44:22.185] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[09:44:22.185] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[09:44:22.185] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[09:44:22.185] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[09:44:22.185] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[09:44:22.185] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[09:44:22.185] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[09:44:22.185] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[09:44:22.185] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[09:44:22.185] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[09:44:22.185] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[09:44:22.185] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[09:44:22.185] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[09:44:22.185] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[09:44:22.185] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[09:44:22.185] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[09:44:22.586] <TB1> INFO: enter 'restricted' command line mode
[09:44:22.586] <TB1> INFO: enter test to run
[09:44:22.586] <TB1> INFO: test: pretest no parameter change
[09:44:22.586] <TB1> INFO: running: pretest
[09:44:22.591] <TB1> INFO: ######################################################################
[09:44:22.591] <TB1> INFO: PixTestPretest::doTest()
[09:44:22.591] <TB1> INFO: ######################################################################
[09:44:22.593] <TB1> INFO: ----------------------------------------------------------------------
[09:44:22.593] <TB1> INFO: PixTestPretest::programROC()
[09:44:22.593] <TB1> INFO: ----------------------------------------------------------------------
[09:44:40.606] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[09:44:40.606] <TB1> INFO: IA differences per ROC: 20.9 17.7 20.1 19.3 16.9 20.9 16.9 19.3 16.9 18.5 18.5 19.3 16.9 20.9 20.1 16.9
[09:44:40.669] <TB1> INFO: ----------------------------------------------------------------------
[09:44:40.669] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[09:44:40.669] <TB1> INFO: ----------------------------------------------------------------------
[09:45:01.968] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 389.9 mA = 24.3688 mA/ROC
[09:45:01.968] <TB1> INFO: i(loss) [mA/ROC]: 19.3 19.3 20.1 19.3 20.1 20.1 19.3 20.1 19.3 19.3 18.5 20.1 19.3 19.3 19.3 19.3
[09:45:01.002] <TB1> INFO: ----------------------------------------------------------------------
[09:45:01.002] <TB1> INFO: PixTestPretest::findTiming()
[09:45:01.002] <TB1> INFO: ----------------------------------------------------------------------
[09:45:01.002] <TB1> INFO: PixTestCmd::init()

[09:45:34.179] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[09:45:34.179] <TB1> INFO: (success/tries = 100/100), width = 4
[09:45:35.684] <TB1> INFO: ----------------------------------------------------------------------
[09:45:35.684] <TB1> INFO: PixTestPretest::findWorkingPixel()
[09:45:35.684] <TB1> INFO: ----------------------------------------------------------------------
[09:45:35.779] <TB1> INFO: Expecting 231680 events.
[09:45:45.764] <TB1> INFO: 231680 events read in total (9393ms).
[09:45:45.774] <TB1> INFO: Test took 10086ms.
[09:45:46.022] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[09:45:46.056] <TB1> INFO: ----------------------------------------------------------------------
[09:45:46.056] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[09:45:46.056] <TB1> INFO: ----------------------------------------------------------------------
[09:45:46.151] <TB1> INFO: Expecting 231680 events.
[09:45:56.036] <TB1> INFO: 231680 events read in total (9293ms).
[09:45:56.048] <TB1> INFO: Test took 9986ms.
[09:45:56.319] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[09:45:56.319] <TB1> INFO: CalDel: 94 95 84 92 76 96 78 81 79 100 77 94 83 96 91 83
[09:45:56.319] <TB1> INFO: VthrComp: 51 51 53 51 60 59 53 51 53 51 51 51 53 51 53 55
[09:45:56.322] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C0.dat
[09:45:56.323] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C1.dat
[09:45:56.323] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C2.dat
[09:45:56.323] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C3.dat
[09:45:56.323] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C4.dat
[09:45:56.323] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C5.dat
[09:45:56.323] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C6.dat
[09:45:56.324] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C7.dat
[09:45:56.324] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C8.dat
[09:45:56.324] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C9.dat
[09:45:56.324] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C10.dat
[09:45:56.324] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C11.dat
[09:45:56.324] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C12.dat
[09:45:56.324] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C13.dat
[09:45:56.324] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C14.dat
[09:45:56.324] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters_C15.dat
[09:45:56.324] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//tbmParameters_C0a.dat
[09:45:56.325] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//tbmParameters_C0b.dat
[09:45:56.325] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//tbmParameters_C1a.dat
[09:45:56.325] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//tbmParameters_C1b.dat
[09:45:56.325] <TB1> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[09:45:56.378] <TB1> INFO: enter test to run
[09:45:56.378] <TB1> INFO: test: FullTest no parameter change
[09:45:56.378] <TB1> INFO: running: fulltest
[09:45:56.378] <TB1> INFO: ######################################################################
[09:45:56.378] <TB1> INFO: PixTestFullTest::doTest()
[09:45:56.378] <TB1> INFO: ######################################################################
[09:45:56.379] <TB1> INFO: ######################################################################
[09:45:56.379] <TB1> INFO: PixTestAlive::doTest()
[09:45:56.379] <TB1> INFO: ######################################################################
[09:45:56.381] <TB1> INFO: ----------------------------------------------------------------------
[09:45:56.381] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:45:56.381] <TB1> INFO: ----------------------------------------------------------------------
[09:45:56.652] <TB1> INFO: Expecting 41600 events.
[09:46:00.196] <TB1> INFO: 41600 events read in total (2953ms).
[09:46:00.197] <TB1> INFO: Test took 3814ms.
[09:46:00.429] <TB1> INFO: PixTestAlive::aliveTest() done
[09:46:00.429] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:46:00.430] <TB1> INFO: ----------------------------------------------------------------------
[09:46:00.430] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:46:00.430] <TB1> INFO: ----------------------------------------------------------------------
[09:46:00.677] <TB1> INFO: Expecting 41600 events.
[09:46:03.721] <TB1> INFO: 41600 events read in total (2452ms).
[09:46:03.721] <TB1> INFO: Test took 3288ms.
[09:46:03.722] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[09:46:03.967] <TB1> INFO: PixTestAlive::maskTest() done
[09:46:03.967] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:46:03.968] <TB1> INFO: ----------------------------------------------------------------------
[09:46:03.968] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:46:03.968] <TB1> INFO: ----------------------------------------------------------------------
[09:46:04.208] <TB1> INFO: Expecting 41600 events.
[09:46:07.826] <TB1> INFO: 41600 events read in total (3026ms).
[09:46:07.827] <TB1> INFO: Test took 3856ms.


[09:46:08.063] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[09:46:08.063] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:46:08.063] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[09:46:08.063] <TB1> INFO: Decoding statistics:
[09:46:08.063] <TB1> INFO: General information:
[09:46:08.063] <TB1> INFO: 16bit words read: 0
[09:46:08.063] <TB1> INFO: valid events total: 0
[09:46:08.063] <TB1> INFO: empty events: 0
[09:46:08.063] <TB1> INFO: valid events with pixels: 0
[09:46:08.063] <TB1> INFO: valid pixel hits: 0
[09:46:08.063] <TB1> INFO: Event errors: 0
[09:46:08.063] <TB1> INFO: start marker: 0
[09:46:08.063] <TB1> INFO: stop marker: 0
[09:46:08.063] <TB1> INFO: overflow: 0
[09:46:08.063] <TB1> INFO: invalid 5bit words: 0
[09:46:08.063] <TB1> INFO: invalid XOR eye diagram: 0
[09:46:08.063] <TB1> INFO: frame (failed synchr.): 0
[09:46:08.063] <TB1> INFO: idle data (no TBM trl): 0
[09:46:08.063] <TB1> INFO: no data (only TBM hdr): 0
[09:46:08.063] <TB1> INFO: TBM errors: 0
[09:46:08.063] <TB1> INFO: flawed TBM headers: 0
[09:46:08.063] <TB1> INFO: flawed TBM trailers: 0
[09:46:08.063] <TB1> INFO: event ID mismatches: 0
[09:46:08.063] <TB1> INFO: ROC errors: 0
[09:46:08.063] <TB1> INFO: missing ROC header(s): 0
[09:46:08.063] <TB1> INFO: misplaced readback start: 0
[09:46:08.064] <TB1> INFO: Pixel decoding errors: 0
[09:46:08.064] <TB1> INFO: pixel data incomplete: 0
[09:46:08.064] <TB1> INFO: pixel address: 0
[09:46:08.064] <TB1> INFO: pulse height fill bit: 0
[09:46:08.064] <TB1> INFO: buffer corruption: 0
[09:46:08.071] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C15.dat
[09:46:08.071] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr_C15.dat

[09:46:08.071] <TB1> INFO: ######################################################################
[09:46:08.071] <TB1> INFO: PixTestReadback::doTest()
[09:46:08.071] <TB1> INFO: ######################################################################
[09:46:08.072] <TB1> INFO: ----------------------------------------------------------------------
[09:46:08.072] <TB1> INFO: PixTestReadback::CalibrateVd()
[09:46:08.072] <TB1> INFO: ----------------------------------------------------------------------
[09:46:18.037] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C0.dat
[09:46:18.037] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C1.dat
[09:46:18.037] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C2.dat
[09:46:18.037] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C3.dat
[09:46:18.037] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C4.dat
[09:46:18.037] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C5.dat
[09:46:18.037] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C6.dat
[09:46:18.037] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C7.dat
[09:46:18.038] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C8.dat
[09:46:18.038] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C9.dat
[09:46:18.038] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C10.dat
[09:46:18.038] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C11.dat
[09:46:18.038] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C12.dat
[09:46:18.038] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C13.dat
[09:46:18.038] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C14.dat
[09:46:18.038] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C15.dat
[09:46:18.068] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[09:46:18.068] <TB1> INFO: ----------------------------------------------------------------------
[09:46:18.068] <TB1> INFO: PixTestReadback::CalibrateVa()
[09:46:18.068] <TB1> INFO: ----------------------------------------------------------------------
[09:46:27.995] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C0.dat
[09:46:27.995] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C1.dat
[09:46:27.995] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C2.dat
[09:46:27.995] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C3.dat
[09:46:27.995] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C4.dat
[09:46:27.996] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C5.dat
[09:46:27.996] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C6.dat
[09:46:27.996] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C7.dat
[09:46:27.996] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C8.dat
[09:46:27.996] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C9.dat
[09:46:27.996] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C10.dat
[09:46:27.996] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C11.dat
[09:46:27.996] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C12.dat
[09:46:27.996] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C13.dat
[09:46:27.996] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C14.dat
[09:46:27.996] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C15.dat
[09:46:28.025] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[09:46:28.025] <TB1> INFO: ----------------------------------------------------------------------
[09:46:28.025] <TB1> INFO: PixTestReadback::readbackVbg()
[09:46:28.025] <TB1> INFO: ----------------------------------------------------------------------
[09:46:35.694] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[09:46:35.694] <TB1> INFO: ----------------------------------------------------------------------
[09:46:35.694] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[09:46:35.694] <TB1> INFO: ----------------------------------------------------------------------
[09:46:35.695] <TB1> INFO: Vbg will be calibrated using Vd calibration
[09:46:35.695] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 162.1calibrated Vbg = 1.20997 :::*/*/*/*/
[09:46:35.695] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 148.4calibrated Vbg = 1.19241 :::*/*/*/*/
[09:46:35.695] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 158.2calibrated Vbg = 1.1934 :::*/*/*/*/
[09:46:35.695] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 151.6calibrated Vbg = 1.19071 :::*/*/*/*/
[09:46:35.695] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 164calibrated Vbg = 1.19168 :::*/*/*/*/
[09:46:35.695] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 165.2calibrated Vbg = 1.20152 :::*/*/*/*/
[09:46:35.695] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 157.9calibrated Vbg = 1.20154 :::*/*/*/*/
[09:46:35.695] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 160.1calibrated Vbg = 1.19888 :::*/*/*/*/
[09:46:35.695] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 166calibrated Vbg = 1.19804 :::*/*/*/*/
[09:46:35.695] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 159calibrated Vbg = 1.19083 :::*/*/*/*/
[09:46:35.695] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 158.2calibrated Vbg = 1.1909 :::*/*/*/*/
[09:46:35.695] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 151.9calibrated Vbg = 1.17983 :::*/*/*/*/
[09:46:35.695] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 150.6calibrated Vbg = 1.1955 :::*/*/*/*/
[09:46:35.695] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 159calibrated Vbg = 1.19609 :::*/*/*/*/
[09:46:35.695] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 149.8calibrated Vbg = 1.19864 :::*/*/*/*/
[09:46:35.695] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 159.7calibrated Vbg = 1.19586 :::*/*/*/*/
[09:46:35.698] <TB1> INFO: ----------------------------------------------------------------------
[09:46:35.698] <TB1> INFO: PixTestReadback::CalibrateIa()
[09:46:35.698] <TB1> INFO: ----------------------------------------------------------------------
[09:49:16.538] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C0.dat
[09:49:16.538] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C1.dat
[09:49:16.538] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C2.dat
[09:49:16.538] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C3.dat
[09:49:16.538] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C4.dat
[09:49:16.538] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C5.dat
[09:49:16.538] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C6.dat
[09:49:16.538] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C7.dat
[09:49:16.538] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C8.dat
[09:49:16.538] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C9.dat
[09:49:16.538] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C10.dat
[09:49:16.538] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C11.dat
[09:49:16.538] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C12.dat
[09:49:16.538] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C13.dat
[09:49:16.539] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C14.dat
[09:49:16.539] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//readbackCal_C15.dat
[09:49:16.568] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[09:49:16.570] <TB1> INFO: PixTestReadback::doTest() done
[09:49:16.570] <TB1> INFO: Decoding statistics:
[09:49:16.570] <TB1> INFO: General information:
[09:49:16.570] <TB1> INFO: 16bit words read: 1536
[09:49:16.570] <TB1> INFO: valid events total: 256
[09:49:16.570] <TB1> INFO: empty events: 256
[09:49:16.570] <TB1> INFO: valid events with pixels: 0
[09:49:16.570] <TB1> INFO: valid pixel hits: 0
[09:49:16.570] <TB1> INFO: Event errors: 0
[09:49:16.570] <TB1> INFO: start marker: 0
[09:49:16.570] <TB1> INFO: stop marker: 0
[09:49:16.570] <TB1> INFO: overflow: 0
[09:49:16.570] <TB1> INFO: invalid 5bit words: 0
[09:49:16.570] <TB1> INFO: invalid XOR eye diagram: 0
[09:49:16.570] <TB1> INFO: frame (failed synchr.): 0
[09:49:16.570] <TB1> INFO: idle data (no TBM trl): 0
[09:49:16.570] <TB1> INFO: no data (only TBM hdr): 0
[09:49:16.570] <TB1> INFO: TBM errors: 0
[09:49:16.570] <TB1> INFO: flawed TBM headers: 0
[09:49:16.570] <TB1> INFO: flawed TBM trailers: 0
[09:49:16.570] <TB1> INFO: event ID mismatches: 0
[09:49:16.570] <TB1> INFO: ROC errors: 0
[09:49:16.570] <TB1> INFO: missing ROC header(s): 0
[09:49:16.570] <TB1> INFO: misplaced readback start: 0
[09:49:16.570] <TB1> INFO: Pixel decoding errors: 0
[09:49:16.570] <TB1> INFO: pixel data incomplete: 0
[09:49:16.570] <TB1> INFO: pixel address: 0
[09:49:16.570] <TB1> INFO: pulse height fill bit: 0
[09:49:16.570] <TB1> INFO: buffer corruption: 0
[09:49:16.621] <TB1> INFO: ######################################################################
[09:49:16.621] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[09:49:16.621] <TB1> INFO: ######################################################################
[09:49:16.623] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[09:49:16.669] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[09:49:16.669] <TB1> INFO: run 1 of 1
[09:49:16.908] <TB1> INFO: Expecting 3120000 events.
[09:49:48.256] <TB1> INFO: 671280 events read in total (30756ms).











[09:50:18.615] <TB1> INFO: 1339435 events read in total (61115ms).











[09:50:48.991] <TB1> INFO: 2006550 events read in total (91491ms).











[09:51:19.522] <TB1> INFO: 2672360 events read in total (122022ms).











[09:51:40.406] <TB1> INFO: 3120000 events read in total (142906ms).
[09:51:40.518] <TB1> INFO: Test took 143850ms.
[09:52:04.632] <TB1> INFO: PixTestBBMap::doTest() done with 1 decoding errors: , duration: 168 seconds
[09:52:04.632] <TB1> INFO: number of dead bumps (per ROC): 1 0 1 0 2 0 1 0 1 1 0 0 1 0 0 0
[09:52:04.632] <TB1> INFO: separation cut (per ROC): 103 104 114 115 114 127 106 107 105 102 110 110 105 101 108 106
[09:52:04.632] <TB1> INFO: Decoding statistics:
[09:52:04.632] <TB1> INFO: General information:
[09:52:04.632] <TB1> INFO: 16bit words read: 0
[09:52:04.632] <TB1> INFO: valid events total: 0
[09:52:04.632] <TB1> INFO: empty events: 0
[09:52:04.632] <TB1> INFO: valid events with pixels: 0
[09:52:04.632] <TB1> INFO: valid pixel hits: 0
[09:52:04.632] <TB1> INFO: Event errors: 0
[09:52:04.632] <TB1> INFO: start marker: 0
[09:52:04.632] <TB1> INFO: stop marker: 0
[09:52:04.632] <TB1> INFO: overflow: 0
[09:52:04.632] <TB1> INFO: invalid 5bit words: 0
[09:52:04.632] <TB1> INFO: invalid XOR eye diagram: 0
[09:52:04.632] <TB1> INFO: frame (failed synchr.): 0
[09:52:04.632] <TB1> INFO: idle data (no TBM trl): 0
[09:52:04.632] <TB1> INFO: no data (only TBM hdr): 0
[09:52:04.632] <TB1> INFO: TBM errors: 0
[09:52:04.632] <TB1> INFO: flawed TBM headers: 0
[09:52:04.632] <TB1> INFO: flawed TBM trailers: 0
[09:52:04.632] <TB1> INFO: event ID mismatches: 0
[09:52:04.632] <TB1> INFO: ROC errors: 0
[09:52:04.632] <TB1> INFO: missing ROC header(s): 0
[09:52:04.632] <TB1> INFO: misplaced readback start: 0
[09:52:04.632] <TB1> INFO: Pixel decoding errors: 0
[09:52:04.632] <TB1> INFO: pixel data incomplete: 0
[09:52:04.632] <TB1> INFO: pixel address: 0
[09:52:04.632] <TB1> INFO: pulse height fill bit: 0
[09:52:04.632] <TB1> INFO: buffer corruption: 0
[09:52:04.671] <TB1> INFO: ######################################################################
[09:52:04.671] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[09:52:04.671] <TB1> INFO: ######################################################################
[09:52:04.671] <TB1> INFO: ----------------------------------------------------------------------
[09:52:04.671] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[09:52:04.671] <TB1> INFO: ----------------------------------------------------------------------
[09:52:04.671] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[09:52:04.685] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[09:52:04.685] <TB1> INFO: run 1 of 1
[09:52:04.928] <TB1> INFO: Expecting 36608000 events.
[09:52:28.914] <TB1> INFO: 702000 events read in total (23394ms).
[09:52:52.388] <TB1> INFO: 1388250 events read in total (46868ms).
[09:53:15.476] <TB1> INFO: 2070850 events read in total (69956ms).
[09:53:38.744] <TB1> INFO: 2754400 events read in total (93224ms).
[09:54:01.832] <TB1> INFO: 3438950 events read in total (116312ms).
[09:54:24.878] <TB1> INFO: 4124650 events read in total (139358ms).
[09:54:48.041] <TB1> INFO: 4805300 events read in total (162521ms).
[09:55:11.452] <TB1> INFO: 5487350 events read in total (185932ms).
[09:55:34.628] <TB1> INFO: 6168300 events read in total (209108ms).
[09:55:58.015] <TB1> INFO: 6852050 events read in total (232495ms).
[09:56:21.104] <TB1> INFO: 7532650 events read in total (255584ms).
[09:56:44.336] <TB1> INFO: 8216450 events read in total (278816ms).
[09:57:07.621] <TB1> INFO: 8897950 events read in total (302101ms).
[09:57:30.681] <TB1> INFO: 9580650 events read in total (325161ms).
[09:57:53.885] <TB1> INFO: 10260550 events read in total (348365ms).
[09:58:16.792] <TB1> INFO: 10941900 events read in total (371272ms).
[09:58:39.752] <TB1> INFO: 11622050 events read in total (394232ms).
[09:59:03.010] <TB1> INFO: 12301900 events read in total (417490ms).
[09:59:26.156] <TB1> INFO: 12979600 events read in total (440636ms).
[09:59:49.211] <TB1> INFO: 13659450 events read in total (463691ms).
[10:00:12.572] <TB1> INFO: 14339150 events read in total (487052ms).
[10:00:35.838] <TB1> INFO: 15017850 events read in total (510318ms).
[10:00:59.076] <TB1> INFO: 15695600 events read in total (533556ms).
[10:01:22.199] <TB1> INFO: 16375250 events read in total (556679ms).
[10:01:45.326] <TB1> INFO: 17053250 events read in total (579806ms).
[10:02:08.073] <TB1> INFO: 17732100 events read in total (602553ms).
[10:02:31.111] <TB1> INFO: 18412150 events read in total (625591ms).
[10:02:54.144] <TB1> INFO: 19087050 events read in total (648624ms).
[10:03:17.263] <TB1> INFO: 19763750 events read in total (671743ms).
[10:03:40.109] <TB1> INFO: 20439650 events read in total (694589ms).
[10:04:02.970] <TB1> INFO: 21117250 events read in total (717450ms).
[10:04:25.887] <TB1> INFO: 21789600 events read in total (740367ms).
[10:04:49.091] <TB1> INFO: 22464850 events read in total (763571ms).
[10:05:12.064] <TB1> INFO: 23139800 events read in total (786544ms).
[10:05:34.933] <TB1> INFO: 23813900 events read in total (809413ms).
[10:05:58.016] <TB1> INFO: 24487350 events read in total (832496ms).
[10:06:21.032] <TB1> INFO: 25163800 events read in total (855512ms).
[10:06:44.263] <TB1> INFO: 25837400 events read in total (878743ms).
[10:07:06.969] <TB1> INFO: 26510900 events read in total (901449ms).
[10:07:29.889] <TB1> INFO: 27182600 events read in total (924369ms).
[10:07:52.776] <TB1> INFO: 27856400 events read in total (947256ms).
[10:08:15.706] <TB1> INFO: 28528300 events read in total (970186ms).
[10:08:38.752] <TB1> INFO: 29201250 events read in total (993232ms).
[10:09:01.923] <TB1> INFO: 29873750 events read in total (1016403ms).
[10:09:24.952] <TB1> INFO: 30544200 events read in total (1039432ms).
[10:09:48.026] <TB1> INFO: 31217050 events read in total (1062506ms).
[10:10:11.102] <TB1> INFO: 31889100 events read in total (1085582ms).
[10:10:33.861] <TB1> INFO: 32561700 events read in total (1108341ms).
[10:10:56.950] <TB1> INFO: 33236600 events read in total (1131430ms).
[10:11:20.035] <TB1> INFO: 33912000 events read in total (1154515ms).
[10:11:43.311] <TB1> INFO: 34585450 events read in total (1177791ms).
[10:12:06.543] <TB1> INFO: 35259150 events read in total (1201023ms).
[10:12:29.584] <TB1> INFO: 35936400 events read in total (1224064ms).
[10:12:52.431] <TB1> INFO: 36608000 events read in total (1246911ms).
[10:12:52.512] <TB1> INFO: Test took 1247827ms.
[10:12:52.964] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:12:54.581] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:12:56.550] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:12:58.533] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:13:00.516] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:13:02.340] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:13:04.137] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:13:06.153] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:13:08.046] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:13:09.907] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:13:11.685] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:13:13.571] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:13:15.242] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:13:16.824] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:13:18.274] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:13:20.042] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[10:13:21.609] <TB1> INFO: PixTestScurves::scurves() done
[10:13:21.609] <TB1> INFO: Vcal mean: 119.25 119.44 131.94 126.55 121.18 140.09 125.00 123.04 128.38 123.02 126.65 126.05 123.23 120.88 128.82 125.89
[10:13:21.609] <TB1> INFO: Vcal RMS: 5.47 5.99 6.58 6.07 7.27 8.50 6.34 6.37 6.10 7.02 6.44 6.57 6.41 6.55 7.44 6.12
[10:13:21.609] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1276 seconds
[10:13:21.609] <TB1> INFO: Decoding statistics:
[10:13:21.609] <TB1> INFO: General information:
[10:13:21.609] <TB1> INFO: 16bit words read: 0
[10:13:21.609] <TB1> INFO: valid events total: 0
[10:13:21.609] <TB1> INFO: empty events: 0
[10:13:21.609] <TB1> INFO: valid events with pixels: 0
[10:13:21.609] <TB1> INFO: valid pixel hits: 0
[10:13:21.609] <TB1> INFO: Event errors: 0
[10:13:21.609] <TB1> INFO: start marker: 0
[10:13:21.609] <TB1> INFO: stop marker: 0
[10:13:21.609] <TB1> INFO: overflow: 0
[10:13:21.609] <TB1> INFO: invalid 5bit words: 0
[10:13:21.609] <TB1> INFO: invalid XOR eye diagram: 0
[10:13:21.609] <TB1> INFO: frame (failed synchr.): 0
[10:13:21.609] <TB1> INFO: idle data (no TBM trl): 0
[10:13:21.609] <TB1> INFO: no data (only TBM hdr): 0
[10:13:21.609] <TB1> INFO: TBM errors: 0
[10:13:21.609] <TB1> INFO: flawed TBM headers: 0
[10:13:21.609] <TB1> INFO: flawed TBM trailers: 0
[10:13:21.609] <TB1> INFO: event ID mismatches: 0
[10:13:21.609] <TB1> INFO: ROC errors: 0
[10:13:21.609] <TB1> INFO: missing ROC header(s): 0
[10:13:21.609] <TB1> INFO: misplaced readback start: 0
[10:13:21.609] <TB1> INFO: Pixel decoding errors: 0
[10:13:21.609] <TB1> INFO: pixel data incomplete: 0
[10:13:21.610] <TB1> INFO: pixel address: 0
[10:13:21.610] <TB1> INFO: pulse height fill bit: 0
[10:13:21.610] <TB1> INFO: buffer corruption: 0
[10:13:21.679] <TB1> INFO: ######################################################################
[10:13:21.679] <TB1> INFO: PixTestTrim::doTest()
[10:13:21.679] <TB1> INFO: ######################################################################
[10:13:21.680] <TB1> INFO: ----------------------------------------------------------------------
[10:13:21.680] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[10:13:21.680] <TB1> INFO: ----------------------------------------------------------------------
[10:13:21.727] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[10:13:21.727] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[10:13:21.740] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:13:21.740] <TB1> INFO: run 1 of 1
[10:13:22.010] <TB1> INFO: Expecting 5025280 events.
[10:13:54.486] <TB1> INFO: 834960 events read in total (31861ms).
[10:14:25.451] <TB1> INFO: 1666088 events read in total (62826ms).
[10:14:56.221] <TB1> INFO: 2495056 events read in total (93596ms).
[10:15:27.285] <TB1> INFO: 3320536 events read in total (124660ms).
[10:15:57.852] <TB1> INFO: 4142880 events read in total (155227ms).
[10:16:28.460] <TB1> INFO: 4965000 events read in total (185835ms).
[10:16:31.190] <TB1> INFO: 5025280 events read in total (188565ms).
[10:16:31.271] <TB1> INFO: Test took 189531ms.
[10:16:49.262] <TB1> INFO: ROC 0 VthrComp = 120
[10:16:49.262] <TB1> INFO: ROC 1 VthrComp = 115
[10:16:49.262] <TB1> INFO: ROC 2 VthrComp = 131
[10:16:49.263] <TB1> INFO: ROC 3 VthrComp = 127
[10:16:49.263] <TB1> INFO: ROC 4 VthrComp = 128
[10:16:49.263] <TB1> INFO: ROC 5 VthrComp = 136
[10:16:49.263] <TB1> INFO: ROC 6 VthrComp = 126
[10:16:49.263] <TB1> INFO: ROC 7 VthrComp = 118
[10:16:49.263] <TB1> INFO: ROC 8 VthrComp = 125
[10:16:49.263] <TB1> INFO: ROC 9 VthrComp = 109
[10:16:49.263] <TB1> INFO: ROC 10 VthrComp = 123
[10:16:49.263] <TB1> INFO: ROC 11 VthrComp = 125
[10:16:49.264] <TB1> INFO: ROC 12 VthrComp = 125
[10:16:49.264] <TB1> INFO: ROC 13 VthrComp = 113
[10:16:49.264] <TB1> INFO: ROC 14 VthrComp = 126
[10:16:49.264] <TB1> INFO: ROC 15 VthrComp = 125
[10:16:49.503] <TB1> INFO: Expecting 41600 events.
[10:16:53.022] <TB1> INFO: 41600 events read in total (2927ms).
[10:16:53.022] <TB1> INFO: Test took 3756ms.
[10:16:53.031] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[10:16:53.031] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[10:16:53.043] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:16:53.043] <TB1> INFO: run 1 of 1
[10:16:53.320] <TB1> INFO: Expecting 5025280 events.
[10:17:20.011] <TB1> INFO: 593472 events read in total (26099ms).
[10:17:45.641] <TB1> INFO: 1185368 events read in total (51730ms).
[10:18:11.161] <TB1> INFO: 1777504 events read in total (77249ms).
[10:18:36.775] <TB1> INFO: 2369256 events read in total (102863ms).
[10:19:02.424] <TB1> INFO: 2958648 events read in total (128512ms).
[10:19:27.963] <TB1> INFO: 3546200 events read in total (154051ms).
[10:19:53.849] <TB1> INFO: 4132776 events read in total (179937ms).
[10:20:19.524] <TB1> INFO: 4718600 events read in total (205612ms).
[10:20:33.623] <TB1> INFO: 5025280 events read in total (219711ms).
[10:20:33.751] <TB1> INFO: Test took 220708ms.
[10:20:59.789] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 60.371 for pixel 4/21 mean/min/max = 47.1183/33.8614/60.3752
[10:20:59.790] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 62.9176 for pixel 0/62 mean/min/max = 47.4244/31.928/62.9208
[10:20:59.790] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 64.0403 for pixel 5/4 mean/min/max = 48.3807/32.7024/64.0589
[10:20:59.791] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 59.9456 for pixel 9/37 mean/min/max = 46.4871/32.9712/60.003
[10:20:59.791] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 63.6392 for pixel 0/69 mean/min/max = 47.5453/31.4259/63.6647
[10:20:59.792] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 70.7965 for pixel 25/79 mean/min/max = 52.5016/34.0978/70.9053
[10:20:59.792] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 61.2325 for pixel 12/17 mean/min/max = 46.9646/32.6899/61.2392
[10:20:59.793] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 62.5373 for pixel 0/16 mean/min/max = 47.0114/31.3118/62.711
[10:20:59.793] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 63.3582 for pixel 9/4 mean/min/max = 47.9142/32.3622/63.4662
[10:20:59.794] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 69.5793 for pixel 0/14 mean/min/max = 52.355/35.0857/69.6243
[10:20:59.794] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 62.1684 for pixel 0/22 mean/min/max = 47.1564/31.7625/62.5504
[10:20:59.795] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 61.6722 for pixel 12/10 mean/min/max = 47.1128/32.5183/61.7073
[10:20:59.795] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 61.0728 for pixel 51/5 mean/min/max = 46.2255/31.3142/61.1367
[10:20:59.796] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 61.2335 for pixel 22/76 mean/min/max = 46.9438/32.6036/61.284
[10:20:59.796] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 62.9461 for pixel 15/79 mean/min/max = 47.087/31.2042/62.9699
[10:20:59.796] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 62.9609 for pixel 16/6 mean/min/max = 47.14/31.2615/63.0184
[10:20:59.797] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:20:59.885] <TB1> INFO: Expecting 411648 events.
[10:21:09.337] <TB1> INFO: 411648 events read in total (8860ms).
[10:21:09.344] <TB1> INFO: Expecting 411648 events.
[10:21:18.547] <TB1> INFO: 411648 events read in total (8799ms).
[10:21:18.557] <TB1> INFO: Expecting 411648 events.
[10:21:27.672] <TB1> INFO: 411648 events read in total (8712ms).
[10:21:27.686] <TB1> INFO: Expecting 411648 events.
[10:21:36.840] <TB1> INFO: 411648 events read in total (8751ms).
[10:21:36.856] <TB1> INFO: Expecting 411648 events.
[10:21:46.274] <TB1> INFO: 411648 events read in total (9015ms).
[10:21:46.292] <TB1> INFO: Expecting 411648 events.
[10:21:55.688] <TB1> INFO: 411648 events read in total (8993ms).
[10:21:55.714] <TB1> INFO: Expecting 411648 events.
[10:22:04.900] <TB1> INFO: 411648 events read in total (8783ms).
[10:22:04.926] <TB1> INFO: Expecting 411648 events.
[10:22:14.188] <TB1> INFO: 411648 events read in total (8859ms).
[10:22:14.214] <TB1> INFO: Expecting 411648 events.
[10:22:23.506] <TB1> INFO: 411648 events read in total (8889ms).
[10:22:23.536] <TB1> INFO: Expecting 411648 events.
[10:22:32.891] <TB1> INFO: 411648 events read in total (8952ms).
[10:22:32.935] <TB1> INFO: Expecting 411648 events.
[10:22:42.235] <TB1> INFO: 411648 events read in total (8897ms).
[10:22:42.273] <TB1> INFO: Expecting 411648 events.
[10:22:51.635] <TB1> INFO: 411648 events read in total (8959ms).
[10:22:51.688] <TB1> INFO: Expecting 411648 events.
[10:23:01.060] <TB1> INFO: 411648 events read in total (8969ms).
[10:23:01.103] <TB1> INFO: Expecting 411648 events.
[10:23:10.345] <TB1> INFO: 411648 events read in total (8839ms).
[10:23:10.439] <TB1> INFO: Expecting 411648 events.
[10:23:19.698] <TB1> INFO: 411648 events read in total (8856ms).
[10:23:19.793] <TB1> INFO: Expecting 411648 events.
[10:23:29.019] <TB1> INFO: 411648 events read in total (8822ms).
[10:23:29.089] <TB1> INFO: Test took 149292ms.
[10:23:29.765] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[10:23:29.779] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:23:29.779] <TB1> INFO: run 1 of 1
[10:23:30.014] <TB1> INFO: Expecting 5025280 events.
[10:23:56.976] <TB1> INFO: 592904 events read in total (26370ms).
[10:24:23.580] <TB1> INFO: 1185432 events read in total (52974ms).
[10:24:49.520] <TB1> INFO: 1777280 events read in total (78915ms).
[10:25:15.468] <TB1> INFO: 2366392 events read in total (104862ms).
[10:25:42.066] <TB1> INFO: 2957544 events read in total (131460ms).
[10:26:08.742] <TB1> INFO: 3551512 events read in total (158136ms).
[10:26:35.255] <TB1> INFO: 4147960 events read in total (184649ms).
[10:27:01.774] <TB1> INFO: 4744672 events read in total (211168ms).
[10:27:14.565] <TB1> INFO: 5025280 events read in total (223959ms).
[10:27:14.704] <TB1> INFO: Test took 224926ms.
[10:27:37.987] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 9.534983 .. 146.543198
[10:27:38.241] <TB1> INFO: Expecting 208000 events.
[10:27:48.322] <TB1> INFO: 208000 events read in total (9490ms).
[10:27:48.323] <TB1> INFO: Test took 10334ms.
[10:27:48.405] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 9 .. 156 (-1/-1) hits flags = 528 (plus default)
[10:27:48.419] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:27:48.419] <TB1> INFO: run 1 of 1
[10:27:48.717] <TB1> INFO: Expecting 4925440 events.
[10:28:15.556] <TB1> INFO: 574384 events read in total (26247ms).
[10:28:41.506] <TB1> INFO: 1148696 events read in total (52198ms).
[10:29:07.447] <TB1> INFO: 1722704 events read in total (78138ms).
[10:29:33.384] <TB1> INFO: 2297416 events read in total (104075ms).
[10:29:59.354] <TB1> INFO: 2871128 events read in total (130045ms).
[10:30:25.079] <TB1> INFO: 3445144 events read in total (155770ms).
[10:30:51.212] <TB1> INFO: 4018840 events read in total (181903ms).
[10:31:16.936] <TB1> INFO: 4591480 events read in total (207627ms).
[10:31:31.856] <TB1> INFO: 4925440 events read in total (222547ms).
[10:31:32.040] <TB1> INFO: Test took 223620ms.
[10:31:56.384] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.294603 .. 47.402803
[10:31:56.623] <TB1> INFO: Expecting 208000 events.
[10:32:06.852] <TB1> INFO: 208000 events read in total (9638ms).
[10:32:06.853] <TB1> INFO: Test took 10467ms.
[10:32:06.904] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 57 (-1/-1) hits flags = 528 (plus default)
[10:32:06.918] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:32:06.918] <TB1> INFO: run 1 of 1
[10:32:07.196] <TB1> INFO: Expecting 1364480 events.
[10:32:35.687] <TB1> INFO: 651152 events read in total (27899ms).
[10:33:03.069] <TB1> INFO: 1300744 events read in total (55282ms).
[10:33:06.117] <TB1> INFO: 1364480 events read in total (58329ms).
[10:33:06.151] <TB1> INFO: Test took 59234ms.
[10:33:19.939] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 22.634346 .. 47.561142
[10:33:20.177] <TB1> INFO: Expecting 208000 events.
[10:33:30.252] <TB1> INFO: 208000 events read in total (9483ms).
[10:33:30.253] <TB1> INFO: Test took 10311ms.
[10:33:30.302] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 12 .. 57 (-1/-1) hits flags = 528 (plus default)
[10:33:30.315] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:33:30.315] <TB1> INFO: run 1 of 1
[10:33:30.552] <TB1> INFO: Expecting 1530880 events.
[10:33:59.054] <TB1> INFO: 670648 events read in total (27911ms).
[10:34:27.301] <TB1> INFO: 1340208 events read in total (56158ms).
[10:34:35.713] <TB1> INFO: 1530880 events read in total (64570ms).
[10:34:35.747] <TB1> INFO: Test took 65433ms.
[10:34:49.211] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 22.551153 .. 46.092477
[10:34:49.456] <TB1> INFO: Expecting 208000 events.
[10:34:59.502] <TB1> INFO: 208000 events read in total (9453ms).
[10:34:59.503] <TB1> INFO: Test took 10288ms.
[10:34:59.572] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 12 .. 56 (-1/-1) hits flags = 528 (plus default)
[10:34:59.586] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:34:59.586] <TB1> INFO: run 1 of 1
[10:34:59.870] <TB1> INFO: Expecting 1497600 events.
[10:35:28.570] <TB1> INFO: 674752 events read in total (28108ms).
[10:35:56.072] <TB1> INFO: 1350264 events read in total (55611ms).
[10:36:02.950] <TB1> INFO: 1497600 events read in total (62488ms).
[10:36:02.986] <TB1> INFO: Test took 63401ms.
[10:36:15.636] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[10:36:15.636] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[10:36:15.649] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[10:36:15.649] <TB1> INFO: run 1 of 1
[10:36:15.927] <TB1> INFO: Expecting 1364480 events.
[10:36:44.337] <TB1> INFO: 667928 events read in total (27818ms).
[10:37:12.128] <TB1> INFO: 1335560 events read in total (55609ms).
[10:37:13.813] <TB1> INFO: 1364480 events read in total (57294ms).
[10:37:13.842] <TB1> INFO: Test took 58194ms.
[10:37:28.353] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C0.dat
[10:37:28.353] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C1.dat
[10:37:28.353] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C2.dat
[10:37:28.353] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C3.dat
[10:37:28.353] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C4.dat
[10:37:28.354] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C5.dat
[10:37:28.354] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C6.dat
[10:37:28.354] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C7.dat
[10:37:28.354] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C8.dat
[10:37:28.354] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C9.dat
[10:37:28.354] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C10.dat
[10:37:28.354] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C11.dat
[10:37:28.354] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C12.dat
[10:37:28.354] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C13.dat
[10:37:28.354] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C14.dat
[10:37:28.354] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C15.dat
[10:37:28.355] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters35_C0.dat
[10:37:28.359] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters35_C1.dat
[10:37:28.364] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters35_C2.dat
[10:37:28.369] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters35_C3.dat
[10:37:28.373] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters35_C4.dat
[10:37:28.378] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters35_C5.dat
[10:37:28.383] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters35_C6.dat
[10:37:28.387] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters35_C7.dat
[10:37:28.392] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters35_C8.dat
[10:37:28.397] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters35_C9.dat
[10:37:28.401] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters35_C10.dat
[10:37:28.406] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters35_C11.dat
[10:37:28.411] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters35_C12.dat
[10:37:28.415] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters35_C13.dat
[10:37:28.420] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters35_C14.dat
[10:37:28.424] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//trimParameters35_C15.dat
[10:37:28.429] <TB1> INFO: PixTestTrim::trimTest() done
[10:37:28.429] <TB1> INFO: vtrim: 125 124 142 124 131 155 123 119 153 129 104 135 156 126 127 128
[10:37:28.429] <TB1> INFO: vthrcomp: 120 115 131 127 128 136 126 118 125 109 123 125 125 113 126 125
[10:37:28.429] <TB1> INFO: vcal mean: 34.97 34.93 34.99 34.96 34.96 34.98 34.94 34.95 34.93 35.00 34.95 34.96 34.95 34.93 34.97 34.95
[10:37:28.429] <TB1> INFO: vcal RMS: 1.04 1.25 1.18 1.06 1.18 1.21 1.12 1.18 1.12 1.20 1.21 1.13 1.10 1.09 1.15 1.20
[10:37:28.429] <TB1> INFO: bits mean: 8.99 8.74 9.11 9.61 8.85 8.10 9.42 8.83 9.71 7.80 8.71 9.55 9.33 9.55 9.76 9.40
[10:37:28.429] <TB1> INFO: bits RMS: 2.66 3.01 2.63 2.51 2.91 2.59 2.59 3.04 2.47 2.59 2.96 2.55 2.91 2.52 2.57 2.82
[10:37:28.438] <TB1> INFO: ----------------------------------------------------------------------
[10:37:28.438] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[10:37:28.438] <TB1> INFO: ----------------------------------------------------------------------
[10:37:28.441] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[10:37:28.454] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[10:37:28.454] <TB1> INFO: run 1 of 1
[10:37:28.691] <TB1> INFO: Expecting 4160000 events.
[10:38:01.720] <TB1> INFO: 772710 events read in total (32437ms).
[10:38:33.883] <TB1> INFO: 1539605 events read in total (64600ms).
[10:39:06.247] <TB1> INFO: 2303170 events read in total (96965ms).
[10:39:38.519] <TB1> INFO: 3061895 events read in total (129236ms).
[10:40:10.465] <TB1> INFO: 3817320 events read in total (161182ms).
[10:40:25.259] <TB1> INFO: 4160000 events read in total (175976ms).
[10:40:25.329] <TB1> INFO: Test took 176875ms.
[10:40:50.121] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[10:40:50.134] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[10:40:50.134] <TB1> INFO: run 1 of 1
[10:40:50.460] <TB1> INFO: Expecting 5324800 events.
[10:41:22.688] <TB1> INFO: 687760 events read in total (31636ms).
[10:41:52.739] <TB1> INFO: 1372415 events read in total (61687ms).
[10:42:23.028] <TB1> INFO: 2055405 events read in total (91976ms).
[10:42:53.516] <TB1> INFO: 2737570 events read in total (122464ms).
[10:43:24.016] <TB1> INFO: 3417585 events read in total (152964ms).
[10:43:54.369] <TB1> INFO: 4096195 events read in total (183318ms).
[10:44:25.081] <TB1> INFO: 4773955 events read in total (214029ms).
[10:44:49.907] <TB1> INFO: 5324800 events read in total (238855ms).
[10:44:50.017] <TB1> INFO: Test took 239882ms.
[10:45:19.528] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 230 (-1/-1) hits flags = 528 (plus default)
[10:45:19.542] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[10:45:19.542] <TB1> INFO: run 1 of 1
[10:45:19.788] <TB1> INFO: Expecting 4804800 events.
[10:45:51.855] <TB1> INFO: 710130 events read in total (31475ms).
[10:46:22.698] <TB1> INFO: 1416840 events read in total (62318ms).
[10:46:53.728] <TB1> INFO: 2121670 events read in total (93348ms).
[10:47:24.455] <TB1> INFO: 2824615 events read in total (124075ms).
[10:47:55.087] <TB1> INFO: 3524650 events read in total (154707ms).
[10:48:25.682] <TB1> INFO: 4223240 events read in total (185302ms).
[10:48:51.227] <TB1> INFO: 4804800 events read in total (210847ms).
[10:48:51.346] <TB1> INFO: Test took 211804ms.
[10:49:19.915] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 230 (-1/-1) hits flags = 528 (plus default)
[10:49:19.929] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[10:49:19.929] <TB1> INFO: run 1 of 1
[10:49:20.167] <TB1> INFO: Expecting 4804800 events.
[10:49:51.858] <TB1> INFO: 710675 events read in total (31099ms).
[10:50:23.586] <TB1> INFO: 1417905 events read in total (62827ms).
[10:50:55.099] <TB1> INFO: 2122325 events read in total (94340ms).
[10:51:27.253] <TB1> INFO: 2825570 events read in total (126494ms).
[10:51:58.277] <TB1> INFO: 3526185 events read in total (157518ms).
[10:52:29.376] <TB1> INFO: 4224910 events read in total (188617ms).
[10:52:55.072] <TB1> INFO: 4804800 events read in total (214313ms).
[10:52:55.197] <TB1> INFO: Test took 215268ms.
[10:53:28.207] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 232 (-1/-1) hits flags = 528 (plus default)
[10:53:28.220] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[10:53:28.220] <TB1> INFO: run 1 of 1
[10:53:28.458] <TB1> INFO: Expecting 4846400 events.
[10:54:00.259] <TB1> INFO: 708920 events read in total (31209ms).
[10:54:30.640] <TB1> INFO: 1414010 events read in total (61590ms).
[10:55:01.549] <TB1> INFO: 2116345 events read in total (92499ms).
[10:55:32.139] <TB1> INFO: 2818080 events read in total (123089ms).
[10:56:02.907] <TB1> INFO: 3516885 events read in total (153857ms).
[10:56:33.746] <TB1> INFO: 4213970 events read in total (184696ms).
[10:57:01.314] <TB1> INFO: 4846400 events read in total (212264ms).
[10:57:01.434] <TB1> INFO: Test took 213214ms.
[10:57:28.228] <TB1> INFO: PixTestTrim::trimBitTest() done
[10:57:28.229] <TB1> INFO: PixTestTrim::doTest() done, duration: 2646 seconds
[10:57:28.229] <TB1> INFO: Decoding statistics:
[10:57:28.229] <TB1> INFO: General information:
[10:57:28.229] <TB1> INFO: 16bit words read: 0
[10:57:28.229] <TB1> INFO: valid events total: 0
[10:57:28.229] <TB1> INFO: empty events: 0
[10:57:28.229] <TB1> INFO: valid events with pixels: 0
[10:57:28.229] <TB1> INFO: valid pixel hits: 0
[10:57:28.229] <TB1> INFO: Event errors: 0
[10:57:28.229] <TB1> INFO: start marker: 0
[10:57:28.229] <TB1> INFO: stop marker: 0
[10:57:28.229] <TB1> INFO: overflow: 0
[10:57:28.229] <TB1> INFO: invalid 5bit words: 0
[10:57:28.229] <TB1> INFO: invalid XOR eye diagram: 0
[10:57:28.230] <TB1> INFO: frame (failed synchr.): 0
[10:57:28.230] <TB1> INFO: idle data (no TBM trl): 0
[10:57:28.230] <TB1> INFO: no data (only TBM hdr): 0
[10:57:28.230] <TB1> INFO: TBM errors: 0
[10:57:28.230] <TB1> INFO: flawed TBM headers: 0
[10:57:28.230] <TB1> INFO: flawed TBM trailers: 0
[10:57:28.230] <TB1> INFO: event ID mismatches: 0
[10:57:28.230] <TB1> INFO: ROC errors: 0
[10:57:28.230] <TB1> INFO: missing ROC header(s): 0
[10:57:28.230] <TB1> INFO: misplaced readback start: 0
[10:57:28.230] <TB1> INFO: Pixel decoding errors: 0
[10:57:28.230] <TB1> INFO: pixel data incomplete: 0
[10:57:28.230] <TB1> INFO: pixel address: 0
[10:57:28.230] <TB1> INFO: pulse height fill bit: 0
[10:57:28.230] <TB1> INFO: buffer corruption: 0
[10:57:28.945] <TB1> INFO: ######################################################################
[10:57:28.945] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[10:57:28.945] <TB1> INFO: ######################################################################
[10:57:29.183] <TB1> INFO: Expecting 41600 events.
[10:57:32.747] <TB1> INFO: 41600 events read in total (2972ms).
[10:57:32.748] <TB1> INFO: Test took 3801ms.
[10:57:33.187] <TB1> INFO: Expecting 41600 events.
[10:57:36.707] <TB1> INFO: 41600 events read in total (2929ms).
[10:57:36.708] <TB1> INFO: Test took 3757ms.
[10:57:36.999] <TB1> INFO: Expecting 41600 events.
[10:57:40.579] <TB1> INFO: 41600 events read in total (2989ms).
[10:57:40.580] <TB1> INFO: Test took 3860ms.
[10:57:40.868] <TB1> INFO: Expecting 41600 events.
[10:57:44.486] <TB1> INFO: 41600 events read in total (3026ms).
[10:57:44.487] <TB1> INFO: Test took 3897ms.
[10:57:44.774] <TB1> INFO: Expecting 41600 events.
[10:57:48.367] <TB1> INFO: 41600 events read in total (3001ms).
[10:57:48.368] <TB1> INFO: Test took 3871ms.
[10:57:48.656] <TB1> INFO: Expecting 41600 events.
[10:57:52.284] <TB1> INFO: 41600 events read in total (3036ms).
[10:57:52.285] <TB1> INFO: Test took 3907ms.
[10:57:52.573] <TB1> INFO: Expecting 41600 events.
[10:57:56.120] <TB1> INFO: 41600 events read in total (2956ms).
[10:57:56.120] <TB1> INFO: Test took 3825ms.
[10:57:56.408] <TB1> INFO: Expecting 41600 events.
[10:57:59.914] <TB1> INFO: 41600 events read in total (2914ms).
[10:57:59.915] <TB1> INFO: Test took 3784ms.
[10:58:00.202] <TB1> INFO: Expecting 41600 events.
[10:58:03.775] <TB1> INFO: 41600 events read in total (2981ms).
[10:58:03.776] <TB1> INFO: Test took 3852ms.
[10:58:04.067] <TB1> INFO: Expecting 41600 events.
[10:58:07.563] <TB1> INFO: 41600 events read in total (2904ms).
[10:58:07.564] <TB1> INFO: Test took 3775ms.
[10:58:07.852] <TB1> INFO: Expecting 41600 events.
[10:58:11.353] <TB1> INFO: 41600 events read in total (2909ms).
[10:58:11.354] <TB1> INFO: Test took 3780ms.
[10:58:11.642] <TB1> INFO: Expecting 41600 events.
[10:58:15.172] <TB1> INFO: 41600 events read in total (2938ms).
[10:58:15.173] <TB1> INFO: Test took 3809ms.
[10:58:15.461] <TB1> INFO: Expecting 41600 events.
[10:58:19.057] <TB1> INFO: 41600 events read in total (3005ms).
[10:58:19.058] <TB1> INFO: Test took 3875ms.
[10:58:19.347] <TB1> INFO: Expecting 41600 events.
[10:58:22.892] <TB1> INFO: 41600 events read in total (2953ms).
[10:58:22.893] <TB1> INFO: Test took 3824ms.
[10:58:23.184] <TB1> INFO: Expecting 41600 events.
[10:58:26.749] <TB1> INFO: 41600 events read in total (2973ms).
[10:58:26.750] <TB1> INFO: Test took 3844ms.
[10:58:27.038] <TB1> INFO: Expecting 41600 events.
[10:58:30.568] <TB1> INFO: 41600 events read in total (2938ms).
[10:58:30.569] <TB1> INFO: Test took 3809ms.
[10:58:30.858] <TB1> INFO: Expecting 41600 events.
[10:58:34.325] <TB1> INFO: 41600 events read in total (2875ms).
[10:58:34.326] <TB1> INFO: Test took 3746ms.
[10:58:34.615] <TB1> INFO: Expecting 41600 events.
[10:58:38.103] <TB1> INFO: 41600 events read in total (2897ms).
[10:58:38.104] <TB1> INFO: Test took 3767ms.
[10:58:38.392] <TB1> INFO: Expecting 41600 events.
[10:58:41.884] <TB1> INFO: 41600 events read in total (2901ms).
[10:58:41.885] <TB1> INFO: Test took 3771ms.
[10:58:42.173] <TB1> INFO: Expecting 41600 events.
[10:58:45.677] <TB1> INFO: 41600 events read in total (2912ms).
[10:58:45.678] <TB1> INFO: Test took 3782ms.
[10:58:45.966] <TB1> INFO: Expecting 41600 events.
[10:58:49.429] <TB1> INFO: 41600 events read in total (2872ms).
[10:58:49.430] <TB1> INFO: Test took 3742ms.
[10:58:49.718] <TB1> INFO: Expecting 41600 events.
[10:58:53.228] <TB1> INFO: 41600 events read in total (2918ms).
[10:58:53.229] <TB1> INFO: Test took 3788ms.
[10:58:53.517] <TB1> INFO: Expecting 41600 events.
[10:58:56.001] <TB1> INFO: 41600 events read in total (2892ms).
[10:58:56.003] <TB1> INFO: Test took 3763ms.
[10:58:57.291] <TB1> INFO: Expecting 41600 events.
[10:59:00.948] <TB1> INFO: 41600 events read in total (3066ms).
[10:59:00.948] <TB1> INFO: Test took 3935ms.
[10:59:01.242] <TB1> INFO: Expecting 41600 events.
[10:59:04.757] <TB1> INFO: 41600 events read in total (2923ms).
[10:59:04.758] <TB1> INFO: Test took 3797ms.
[10:59:05.049] <TB1> INFO: Expecting 41600 events.
[10:59:08.605] <TB1> INFO: 41600 events read in total (2965ms).
[10:59:08.606] <TB1> INFO: Test took 3838ms.
[10:59:08.895] <TB1> INFO: Expecting 41600 events.
[10:59:12.516] <TB1> INFO: 41600 events read in total (3030ms).
[10:59:12.517] <TB1> INFO: Test took 3901ms.
[10:59:12.809] <TB1> INFO: Expecting 41600 events.
[10:59:16.345] <TB1> INFO: 41600 events read in total (2945ms).
[10:59:16.347] <TB1> INFO: Test took 3818ms.
[10:59:16.639] <TB1> INFO: Expecting 41600 events.
[10:59:20.219] <TB1> INFO: 41600 events read in total (2988ms).
[10:59:20.220] <TB1> INFO: Test took 3859ms.
[10:59:20.510] <TB1> INFO: Expecting 41600 events.
[10:59:24.032] <TB1> INFO: 41600 events read in total (2930ms).
[10:59:24.033] <TB1> INFO: Test took 3801ms.
[10:59:24.321] <TB1> INFO: Expecting 41600 events.
[10:59:27.873] <TB1> INFO: 41600 events read in total (2960ms).
[10:59:27.874] <TB1> INFO: Test took 3831ms.
[10:59:28.165] <TB1> INFO: Expecting 41600 events.
[10:59:31.700] <TB1> INFO: 41600 events read in total (2944ms).
[10:59:31.701] <TB1> INFO: Test took 3814ms.
[10:59:31.989] <TB1> INFO: Expecting 41600 events.
[10:59:35.589] <TB1> INFO: 41600 events read in total (3008ms).
[10:59:35.590] <TB1> INFO: Test took 3878ms.
[10:59:35.879] <TB1> INFO: Expecting 41600 events.
[10:59:39.376] <TB1> INFO: 41600 events read in total (2905ms).
[10:59:39.377] <TB1> INFO: Test took 3776ms.
[10:59:39.666] <TB1> INFO: Expecting 41600 events.
[10:59:43.156] <TB1> INFO: 41600 events read in total (2898ms).
[10:59:43.157] <TB1> INFO: Test took 3769ms.
[10:59:43.445] <TB1> INFO: Expecting 41600 events.
[10:59:47.045] <TB1> INFO: 41600 events read in total (3008ms).
[10:59:47.046] <TB1> INFO: Test took 3879ms.
[10:59:47.336] <TB1> INFO: Expecting 41600 events.
[10:59:50.918] <TB1> INFO: 41600 events read in total (2991ms).
[10:59:50.918] <TB1> INFO: Test took 3861ms.
[10:59:51.207] <TB1> INFO: Expecting 41600 events.
[10:59:54.796] <TB1> INFO: 41600 events read in total (2998ms).
[10:59:54.797] <TB1> INFO: Test took 3868ms.
[10:59:55.089] <TB1> INFO: Expecting 41600 events.
[10:59:58.697] <TB1> INFO: 41600 events read in total (3016ms).
[10:59:58.698] <TB1> INFO: Test took 3891ms.
[10:59:58.992] <TB1> INFO: Expecting 41600 events.
[11:00:02.527] <TB1> INFO: 41600 events read in total (2943ms).
[11:00:02.528] <TB1> INFO: Test took 3817ms.
[11:00:02.817] <TB1> INFO: Expecting 41600 events.
[11:00:06.336] <TB1> INFO: 41600 events read in total (2927ms).
[11:00:06.337] <TB1> INFO: Test took 3799ms.
[11:00:06.625] <TB1> INFO: Expecting 41600 events.
[11:00:10.131] <TB1> INFO: 41600 events read in total (2915ms).
[11:00:10.132] <TB1> INFO: Test took 3785ms.
[11:00:10.423] <TB1> INFO: Expecting 41600 events.
[11:00:13.984] <TB1> INFO: 41600 events read in total (2969ms).
[11:00:13.984] <TB1> INFO: Test took 3842ms.
[11:00:14.272] <TB1> INFO: Expecting 41600 events.
[11:00:17.833] <TB1> INFO: 41600 events read in total (2969ms).
[11:00:17.834] <TB1> INFO: Test took 3840ms.
[11:00:18.123] <TB1> INFO: Expecting 41600 events.
[11:00:21.653] <TB1> INFO: 41600 events read in total (2938ms).
[11:00:21.654] <TB1> INFO: Test took 3809ms.
[11:00:21.942] <TB1> INFO: Expecting 41600 events.
[11:00:25.425] <TB1> INFO: 41600 events read in total (2891ms).
[11:00:25.425] <TB1> INFO: Test took 3761ms.
[11:00:25.713] <TB1> INFO: Expecting 41600 events.
[11:00:29.218] <TB1> INFO: 41600 events read in total (2913ms).
[11:00:29.219] <TB1> INFO: Test took 3784ms.
[11:00:29.507] <TB1> INFO: Expecting 41600 events.
[11:00:33.125] <TB1> INFO: 41600 events read in total (3027ms).
[11:00:33.126] <TB1> INFO: Test took 3897ms.
[11:00:33.418] <TB1> INFO: Expecting 41600 events.
[11:00:36.002] <TB1> INFO: 41600 events read in total (2992ms).
[11:00:36.003] <TB1> INFO: Test took 3864ms.
[11:00:37.294] <TB1> INFO: Expecting 41600 events.
[11:00:40.807] <TB1> INFO: 41600 events read in total (2921ms).
[11:00:40.808] <TB1> INFO: Test took 3792ms.
[11:00:41.100] <TB1> INFO: Expecting 41600 events.
[11:00:44.645] <TB1> INFO: 41600 events read in total (2953ms).
[11:00:44.646] <TB1> INFO: Test took 3825ms.
[11:00:44.934] <TB1> INFO: Expecting 41600 events.
[11:00:48.485] <TB1> INFO: 41600 events read in total (2959ms).
[11:00:48.486] <TB1> INFO: Test took 3830ms.
[11:00:48.777] <TB1> INFO: Expecting 41600 events.
[11:00:52.306] <TB1> INFO: 41600 events read in total (2937ms).
[11:00:52.307] <TB1> INFO: Test took 3808ms.
[11:00:52.320] <TB1> INFO: Max pixel from chip 0 is [13 ,8] phvalue 151
[11:00:52.320] <TB1> INFO: Max pixel from chip 1 is [4 ,18] phvalue 47
[11:00:52.320] <TB1> INFO: Max pixel from chip 2 is [12 ,16] phvalue 108
[11:00:52.320] <TB1> INFO: Max pixel from chip 3 is [8 ,6] phvalue 159
[11:00:52.321] <TB1> INFO: Max pixel from chip 4 is [14 ,54] phvalue 239
[11:00:52.321] <TB1> INFO: Max pixel from chip 5 is [18 ,12] phvalue 116
[11:00:52.321] <TB1> INFO: Max pixel from chip 6 is [5 ,6] phvalue 144
[11:00:52.321] <TB1> INFO: Max pixel from chip 7 is [15 ,9] phvalue 118
[11:00:52.321] <TB1> INFO: Max pixel from chip 8 is [4 ,23] phvalue 124
[11:00:52.322] <TB1> INFO: Max pixel from chip 9 is [14 ,5] phvalue 90
[11:00:52.322] <TB1> INFO: Max pixel from chip 10 is [10 ,64] phvalue 148
[11:00:52.322] <TB1> INFO: Max pixel from chip 11 is [4 ,25] phvalue 86
[11:00:52.322] <TB1> INFO: Max pixel from chip 12 is [14 ,25] phvalue 111
[11:00:52.323] <TB1> INFO: Max pixel from chip 13 is [11 ,69] phvalue 147
[11:00:52.323] <TB1> INFO: Max pixel from chip 14 is [16 ,9] phvalue 103
[11:00:52.323] <TB1> INFO: Max pixel from chip 15 is [4 ,26] phvalue 224
[11:00:52.602] <TB1> INFO: Expecting 41600 events.
[11:00:56.116] <TB1> INFO: 41600 events read in total (2922ms).
[11:00:56.117] <TB1> INFO: Test took 3779ms.
[11:00:56.127] <TB1> INFO: Min pixel from chip 0 is [3 ,5] phvalue 255
[11:00:56.127] <TB1> INFO: Min pixel from chip 1 is [35 ,26] phvalue 241
[11:00:56.127] <TB1> INFO: Min pixel from chip 2 is [3 ,5] phvalue 255
[11:00:56.127] <TB1> INFO: Min pixel from chip 3 is [3 ,5] phvalue 255
[11:00:56.127] <TB1> INFO: Min pixel from chip 4 is [3 ,5] phvalue 255
[11:00:56.127] <TB1> INFO: Min pixel from chip 5 is [3 ,5] phvalue 255
[11:00:56.127] <TB1> INFO: Min pixel from chip 6 is [3 ,5] phvalue 255
[11:00:56.127] <TB1> INFO: Min pixel from chip 7 is [3 ,5] phvalue 255
[11:00:56.127] <TB1> INFO: Min pixel from chip 8 is [3 ,5] phvalue 255
[11:00:56.128] <TB1> INFO: Min pixel from chip 9 is [3 ,5] phvalue 255
[11:00:56.128] <TB1> INFO: Min pixel from chip 10 is [3 ,5] phvalue 255
[11:00:56.128] <TB1> INFO: Min pixel from chip 11 is [3 ,5] phvalue 255
[11:00:56.128] <TB1> INFO: Min pixel from chip 12 is [3 ,5] phvalue 255
[11:00:56.128] <TB1> INFO: Min pixel from chip 13 is [3 ,5] phvalue 255
[11:00:56.128] <TB1> INFO: Min pixel from chip 14 is [3 ,5] phvalue 255
[11:00:56.128] <TB1> INFO: Min pixel from chip 15 is [3 ,5] phvalue 255
[11:00:56.407] <TB1> INFO: Expecting 2560 events.
[11:00:57.290] <TB1> INFO: 2560 events read in total (291ms).
[11:00:57.290] <TB1> INFO: Test took 1160ms.
[11:00:57.598] <TB1> INFO: Expecting 2560 events.
[11:00:58.483] <TB1> INFO: 2560 events read in total (293ms).
[11:00:58.483] <TB1> INFO: Test took 1192ms.
[11:00:58.790] <TB1> INFO: Expecting 2560 events.
[11:00:59.678] <TB1> INFO: 2560 events read in total (296ms).
[11:00:59.678] <TB1> INFO: Test took 1194ms.
[11:00:59.986] <TB1> INFO: Expecting 2560 events.
[11:01:00.880] <TB1> INFO: 2560 events read in total (302ms).
[11:01:00.881] <TB1> INFO: Test took 1203ms.
[11:01:01.188] <TB1> INFO: Expecting 2560 events.
[11:01:02.074] <TB1> INFO: 2560 events read in total (295ms).
[11:01:02.075] <TB1> INFO: Test took 1192ms.
[11:01:02.383] <TB1> INFO: Expecting 2560 events.
[11:01:03.270] <TB1> INFO: 2560 events read in total (295ms).
[11:01:03.270] <TB1> INFO: Test took 1195ms.
[11:01:03.578] <TB1> INFO: Expecting 2560 events.
[11:01:04.460] <TB1> INFO: 2560 events read in total (290ms).
[11:01:04.460] <TB1> INFO: Test took 1189ms.
[11:01:04.768] <TB1> INFO: Expecting 2560 events.
[11:01:05.647] <TB1> INFO: 2560 events read in total (288ms).
[11:01:05.648] <TB1> INFO: Test took 1187ms.
[11:01:05.955] <TB1> INFO: Expecting 2560 events.
[11:01:06.842] <TB1> INFO: 2560 events read in total (295ms).
[11:01:06.842] <TB1> INFO: Test took 1193ms.
[11:01:07.150] <TB1> INFO: Expecting 2560 events.
[11:01:08.035] <TB1> INFO: 2560 events read in total (293ms).
[11:01:08.035] <TB1> INFO: Test took 1192ms.
[11:01:08.344] <TB1> INFO: Expecting 2560 events.
[11:01:09.233] <TB1> INFO: 2560 events read in total (298ms).
[11:01:09.233] <TB1> INFO: Test took 1197ms.
[11:01:09.541] <TB1> INFO: Expecting 2560 events.
[11:01:10.423] <TB1> INFO: 2560 events read in total (291ms).
[11:01:10.424] <TB1> INFO: Test took 1191ms.
[11:01:10.730] <TB1> INFO: Expecting 2560 events.
[11:01:11.614] <TB1> INFO: 2560 events read in total (292ms).
[11:01:11.614] <TB1> INFO: Test took 1190ms.
[11:01:11.921] <TB1> INFO: Expecting 2560 events.
[11:01:12.814] <TB1> INFO: 2560 events read in total (301ms).
[11:01:12.814] <TB1> INFO: Test took 1200ms.
[11:01:13.122] <TB1> INFO: Expecting 2560 events.
[11:01:14.013] <TB1> INFO: 2560 events read in total (299ms).
[11:01:14.013] <TB1> INFO: Test took 1198ms.
[11:01:14.321] <TB1> INFO: Expecting 2560 events.
[11:01:15.215] <TB1> INFO: 2560 events read in total (302ms).
[11:01:15.215] <TB1> INFO: Test took 1202ms.
[11:01:15.219] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:01:15.523] <TB1> INFO: Expecting 655360 events.
[11:01:30.243] <TB1> INFO: 655360 events read in total (14128ms).
[11:01:30.257] <TB1> INFO: Expecting 655360 events.
[11:01:44.755] <TB1> INFO: 655360 events read in total (14095ms).
[11:01:44.775] <TB1> INFO: Expecting 655360 events.
[11:01:59.359] <TB1> INFO: 655360 events read in total (14181ms).
[11:01:59.382] <TB1> INFO: Expecting 655360 events.
[11:02:13.945] <TB1> INFO: 655360 events read in total (14160ms).
[11:02:13.973] <TB1> INFO: Expecting 655360 events.
[11:02:28.468] <TB1> INFO: 655360 events read in total (14092ms).
[11:02:28.500] <TB1> INFO: Expecting 655360 events.
[11:02:43.195] <TB1> INFO: 655360 events read in total (14292ms).
[11:02:43.232] <TB1> INFO: Expecting 655360 events.
[11:02:57.892] <TB1> INFO: 655360 events read in total (14257ms).
[11:02:57.941] <TB1> INFO: Expecting 655360 events.
[11:03:12.577] <TB1> INFO: 655360 events read in total (14233ms).
[11:03:12.631] <TB1> INFO: Expecting 655360 events.
[11:03:27.184] <TB1> INFO: 655360 events read in total (14150ms).
[11:03:27.248] <TB1> INFO: Expecting 655360 events.
[11:03:41.836] <TB1> INFO: 655360 events read in total (14184ms).
[11:03:41.904] <TB1> INFO: Expecting 655360 events.
[11:03:56.501] <TB1> INFO: 655360 events read in total (14193ms).
[11:03:56.581] <TB1> INFO: Expecting 655360 events.
[11:04:11.232] <TB1> INFO: 655360 events read in total (14247ms).
[11:04:11.326] <TB1> INFO: Expecting 655360 events.
[11:04:25.003] <TB1> INFO: 655360 events read in total (14274ms).
[11:04:26.102] <TB1> INFO: Expecting 655360 events.
[11:04:40.748] <TB1> INFO: 655360 events read in total (14243ms).
[11:04:40.860] <TB1> INFO: Expecting 655360 events.
[11:04:55.460] <TB1> INFO: 655360 events read in total (14196ms).
[11:04:55.579] <TB1> INFO: Expecting 655360 events.
[11:05:10.198] <TB1> INFO: 655360 events read in total (14216ms).
[11:05:10.323] <TB1> INFO: Test took 235104ms.
[11:05:10.423] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:05:10.675] <TB1> INFO: Expecting 655360 events.
[11:05:25.440] <TB1> INFO: 655360 events read in total (14173ms).
[11:05:25.455] <TB1> INFO: Expecting 655360 events.
[11:05:39.893] <TB1> INFO: 655360 events read in total (14035ms).
[11:05:39.912] <TB1> INFO: Expecting 655360 events.
[11:05:54.544] <TB1> INFO: 655360 events read in total (14229ms).
[11:05:54.567] <TB1> INFO: Expecting 655360 events.
[11:06:09.144] <TB1> INFO: 655360 events read in total (14174ms).
[11:06:09.181] <TB1> INFO: Expecting 655360 events.
[11:06:23.509] <TB1> INFO: 655360 events read in total (13925ms).
[11:06:23.551] <TB1> INFO: Expecting 655360 events.
[11:06:37.726] <TB1> INFO: 655360 events read in total (13772ms).
[11:06:37.762] <TB1> INFO: Expecting 655360 events.
[11:06:51.906] <TB1> INFO: 655360 events read in total (13741ms).
[11:06:51.948] <TB1> INFO: Expecting 655360 events.
[11:07:06.001] <TB1> INFO: 655360 events read in total (14650ms).
[11:07:07.054] <TB1> INFO: Expecting 655360 events.
[11:07:21.784] <TB1> INFO: 655360 events read in total (14327ms).
[11:07:21.849] <TB1> INFO: Expecting 655360 events.
[11:07:36.770] <TB1> INFO: 655360 events read in total (14517ms).
[11:07:36.835] <TB1> INFO: Expecting 655360 events.
[11:07:51.650] <TB1> INFO: 655360 events read in total (14411ms).
[11:07:51.735] <TB1> INFO: Expecting 655360 events.
[11:08:06.728] <TB1> INFO: 655360 events read in total (14590ms).
[11:08:06.804] <TB1> INFO: Expecting 655360 events.
[11:08:21.877] <TB1> INFO: 655360 events read in total (14670ms).
[11:08:21.961] <TB1> INFO: Expecting 655360 events.
[11:08:36.864] <TB1> INFO: 655360 events read in total (14499ms).
[11:08:36.993] <TB1> INFO: Expecting 655360 events.
[11:08:51.749] <TB1> INFO: 655360 events read in total (14353ms).
[11:08:51.884] <TB1> INFO: Expecting 655360 events.
[11:09:06.883] <TB1> INFO: 655360 events read in total (14596ms).
[11:09:07.089] <TB1> INFO: Test took 236666ms.
[11:09:07.265] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:09:07.271] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:09:07.277] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:09:07.282] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:09:07.288] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:09:07.294] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:09:07.300] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[11:09:07.305] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[11:09:07.312] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[11:09:07.318] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:09:07.323] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:09:07.330] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:09:07.335] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:09:07.341] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:09:07.347] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[11:09:07.353] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[11:09:07.359] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[11:09:07.365] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[11:09:07.371] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[11:09:07.377] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[11:09:07.383] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[11:09:07.388] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:09:07.394] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:09:07.400] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[11:09:07.405] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:09:07.411] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:09:07.417] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:09:07.423] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[11:09:07.429] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[11:09:07.435] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[11:09:07.441] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:09:07.447] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:09:07.453] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:09:07.459] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:09:07.465] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[11:09:07.499] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C0.dat
[11:09:07.499] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C1.dat
[11:09:07.499] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C2.dat
[11:09:07.499] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C3.dat
[11:09:07.499] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C4.dat
[11:09:07.499] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C5.dat
[11:09:07.499] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C6.dat
[11:09:07.499] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C7.dat
[11:09:07.500] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C8.dat
[11:09:07.500] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C9.dat
[11:09:07.500] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C10.dat
[11:09:07.500] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C11.dat
[11:09:07.500] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C12.dat
[11:09:07.500] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C13.dat
[11:09:07.501] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C14.dat
[11:09:07.501] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//dacParameters35_C15.dat
[11:09:07.777] <TB1> INFO: Expecting 41600 events.
[11:09:10.937] <TB1> INFO: 41600 events read in total (2568ms).
[11:09:10.938] <TB1> INFO: Test took 3434ms.
[11:09:11.444] <TB1> INFO: Expecting 41600 events.
[11:09:14.530] <TB1> INFO: 41600 events read in total (2495ms).
[11:09:14.531] <TB1> INFO: Test took 3382ms.
[11:09:15.004] <TB1> INFO: Expecting 41600 events.
[11:09:18.198] <TB1> INFO: 41600 events read in total (2602ms).
[11:09:18.199] <TB1> INFO: Test took 3456ms.
[11:09:18.422] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:18.511] <TB1> INFO: Expecting 2560 events.
[11:09:19.400] <TB1> INFO: 2560 events read in total (297ms).
[11:09:19.400] <TB1> INFO: Test took 978ms.
[11:09:19.403] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:19.708] <TB1> INFO: Expecting 2560 events.
[11:09:20.601] <TB1> INFO: 2560 events read in total (301ms).
[11:09:20.602] <TB1> INFO: Test took 1199ms.
[11:09:20.604] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:20.910] <TB1> INFO: Expecting 2560 events.
[11:09:21.799] <TB1> INFO: 2560 events read in total (298ms).
[11:09:21.800] <TB1> INFO: Test took 1196ms.
[11:09:21.804] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:22.108] <TB1> INFO: Expecting 2560 events.
[11:09:22.996] <TB1> INFO: 2560 events read in total (296ms).
[11:09:22.997] <TB1> INFO: Test took 1193ms.
[11:09:22.999] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:23.305] <TB1> INFO: Expecting 2560 events.
[11:09:24.194] <TB1> INFO: 2560 events read in total (298ms).
[11:09:24.195] <TB1> INFO: Test took 1196ms.
[11:09:24.197] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:24.503] <TB1> INFO: Expecting 2560 events.
[11:09:25.398] <TB1> INFO: 2560 events read in total (303ms).
[11:09:25.398] <TB1> INFO: Test took 1201ms.
[11:09:25.401] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:25.706] <TB1> INFO: Expecting 2560 events.
[11:09:26.599] <TB1> INFO: 2560 events read in total (302ms).
[11:09:26.600] <TB1> INFO: Test took 1199ms.
[11:09:26.603] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:26.907] <TB1> INFO: Expecting 2560 events.
[11:09:27.794] <TB1> INFO: 2560 events read in total (295ms).
[11:09:27.795] <TB1> INFO: Test took 1193ms.
[11:09:27.797] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:28.104] <TB1> INFO: Expecting 2560 events.
[11:09:28.990] <TB1> INFO: 2560 events read in total (295ms).
[11:09:28.991] <TB1> INFO: Test took 1194ms.
[11:09:28.993] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:29.298] <TB1> INFO: Expecting 2560 events.
[11:09:30.189] <TB1> INFO: 2560 events read in total (299ms).
[11:09:30.190] <TB1> INFO: Test took 1197ms.
[11:09:30.192] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:30.498] <TB1> INFO: Expecting 2560 events.
[11:09:31.387] <TB1> INFO: 2560 events read in total (297ms).
[11:09:31.387] <TB1> INFO: Test took 1195ms.
[11:09:31.391] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:31.695] <TB1> INFO: Expecting 2560 events.
[11:09:32.578] <TB1> INFO: 2560 events read in total (291ms).
[11:09:32.578] <TB1> INFO: Test took 1187ms.
[11:09:32.581] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:32.885] <TB1> INFO: Expecting 2560 events.
[11:09:33.765] <TB1> INFO: 2560 events read in total (288ms).
[11:09:33.765] <TB1> INFO: Test took 1185ms.
[11:09:33.767] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:34.074] <TB1> INFO: Expecting 2560 events.
[11:09:34.956] <TB1> INFO: 2560 events read in total (291ms).
[11:09:34.956] <TB1> INFO: Test took 1189ms.
[11:09:34.958] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:35.265] <TB1> INFO: Expecting 2560 events.
[11:09:36.144] <TB1> INFO: 2560 events read in total (287ms).
[11:09:36.144] <TB1> INFO: Test took 1186ms.
[11:09:36.147] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:36.453] <TB1> INFO: Expecting 2560 events.
[11:09:37.336] <TB1> INFO: 2560 events read in total (291ms).
[11:09:37.337] <TB1> INFO: Test took 1190ms.
[11:09:37.339] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:37.645] <TB1> INFO: Expecting 2560 events.
[11:09:38.526] <TB1> INFO: 2560 events read in total (289ms).
[11:09:38.527] <TB1> INFO: Test took 1188ms.
[11:09:38.529] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:38.835] <TB1> INFO: Expecting 2560 events.
[11:09:39.714] <TB1> INFO: 2560 events read in total (287ms).
[11:09:39.714] <TB1> INFO: Test took 1185ms.
[11:09:39.717] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:40.023] <TB1> INFO: Expecting 2560 events.
[11:09:40.902] <TB1> INFO: 2560 events read in total (286ms).
[11:09:40.902] <TB1> INFO: Test took 1185ms.
[11:09:40.904] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:41.211] <TB1> INFO: Expecting 2560 events.
[11:09:42.091] <TB1> INFO: 2560 events read in total (289ms).
[11:09:42.092] <TB1> INFO: Test took 1188ms.
[11:09:42.094] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:42.399] <TB1> INFO: Expecting 2560 events.
[11:09:43.284] <TB1> INFO: 2560 events read in total (293ms).
[11:09:43.284] <TB1> INFO: Test took 1190ms.
[11:09:43.287] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:43.592] <TB1> INFO: Expecting 2560 events.
[11:09:44.473] <TB1> INFO: 2560 events read in total (289ms).
[11:09:44.473] <TB1> INFO: Test took 1186ms.
[11:09:44.476] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:44.782] <TB1> INFO: Expecting 2560 events.
[11:09:45.662] <TB1> INFO: 2560 events read in total (289ms).
[11:09:45.663] <TB1> INFO: Test took 1187ms.
[11:09:45.665] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:45.971] <TB1> INFO: Expecting 2560 events.
[11:09:46.850] <TB1> INFO: 2560 events read in total (288ms).
[11:09:46.851] <TB1> INFO: Test took 1186ms.
[11:09:46.853] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:47.159] <TB1> INFO: Expecting 2560 events.
[11:09:48.044] <TB1> INFO: 2560 events read in total (293ms).
[11:09:48.044] <TB1> INFO: Test took 1191ms.
[11:09:48.048] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:48.353] <TB1> INFO: Expecting 2560 events.
[11:09:49.240] <TB1> INFO: 2560 events read in total (296ms).
[11:09:49.240] <TB1> INFO: Test took 1193ms.
[11:09:49.243] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:49.549] <TB1> INFO: Expecting 2560 events.
[11:09:50.437] <TB1> INFO: 2560 events read in total (297ms).
[11:09:50.437] <TB1> INFO: Test took 1194ms.
[11:09:50.439] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:50.746] <TB1> INFO: Expecting 2560 events.
[11:09:51.634] <TB1> INFO: 2560 events read in total (297ms).
[11:09:51.634] <TB1> INFO: Test took 1195ms.
[11:09:51.638] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:51.943] <TB1> INFO: Expecting 2560 events.
[11:09:52.827] <TB1> INFO: 2560 events read in total (292ms).
[11:09:52.827] <TB1> INFO: Test took 1189ms.
[11:09:52.830] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:53.136] <TB1> INFO: Expecting 2560 events.
[11:09:54.019] <TB1> INFO: 2560 events read in total (292ms).
[11:09:54.019] <TB1> INFO: Test took 1190ms.
[11:09:54.022] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:54.328] <TB1> INFO: Expecting 2560 events.
[11:09:55.212] <TB1> INFO: 2560 events read in total (293ms).
[11:09:55.212] <TB1> INFO: Test took 1190ms.
[11:09:55.215] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:09:55.520] <TB1> INFO: Expecting 2560 events.
[11:09:56.405] <TB1> INFO: 2560 events read in total (293ms).
[11:09:56.405] <TB1> INFO: Test took 1191ms.
[11:09:56.869] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 747 seconds
[11:09:56.869] <TB1> INFO: PH scale (per ROC): 35 49 42 32 41 49 37 42 42 44 47 39 44 40 43 49
[11:09:56.869] <TB1> INFO: PH offset (per ROC): 93 128 110 85 75 110 96 107 102 114 102 110 108 95 107 81
[11:09:56.876] <TB1> INFO: Decoding statistics:
[11:09:56.876] <TB1> INFO: General information:
[11:09:56.876] <TB1> INFO: 16bit words read: 127872
[11:09:56.876] <TB1> INFO: valid events total: 20480
[11:09:56.876] <TB1> INFO: empty events: 17984
[11:09:56.876] <TB1> INFO: valid events with pixels: 2496
[11:09:56.876] <TB1> INFO: valid pixel hits: 2496
[11:09:56.876] <TB1> INFO: Event errors: 0
[11:09:56.876] <TB1> INFO: start marker: 0
[11:09:56.876] <TB1> INFO: stop marker: 0
[11:09:56.876] <TB1> INFO: overflow: 0
[11:09:56.876] <TB1> INFO: invalid 5bit words: 0
[11:09:56.876] <TB1> INFO: invalid XOR eye diagram: 0
[11:09:56.876] <TB1> INFO: frame (failed synchr.): 0
[11:09:56.876] <TB1> INFO: idle data (no TBM trl): 0
[11:09:56.876] <TB1> INFO: no data (only TBM hdr): 0
[11:09:56.876] <TB1> INFO: TBM errors: 0
[11:09:56.876] <TB1> INFO: flawed TBM headers: 0
[11:09:56.876] <TB1> INFO: flawed TBM trailers: 0
[11:09:56.876] <TB1> INFO: event ID mismatches: 0
[11:09:56.876] <TB1> INFO: ROC errors: 0
[11:09:56.876] <TB1> INFO: missing ROC header(s): 0
[11:09:56.876] <TB1> INFO: misplaced readback start: 0
[11:09:56.876] <TB1> INFO: Pixel decoding errors: 0
[11:09:56.876] <TB1> INFO: pixel data incomplete: 0
[11:09:56.876] <TB1> INFO: pixel address: 0
[11:09:56.876] <TB1> INFO: pulse height fill bit: 0
[11:09:56.876] <TB1> INFO: buffer corruption: 0
[11:09:57.042] <TB1> INFO: ######################################################################
[11:09:57.042] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[11:09:57.042] <TB1> INFO: ######################################################################
[11:09:57.057] <TB1> INFO: scanning low vcal = 10
[11:09:57.294] <TB1> INFO: Expecting 41600 events.
[11:10:00.884] <TB1> INFO: 41600 events read in total (2998ms).
[11:10:00.884] <TB1> INFO: Test took 3827ms.
[11:10:00.886] <TB1> INFO: scanning low vcal = 20
[11:10:01.184] <TB1> INFO: Expecting 41600 events.
[11:10:04.756] <TB1> INFO: 41600 events read in total (2980ms).
[11:10:04.757] <TB1> INFO: Test took 3871ms.
[11:10:04.759] <TB1> INFO: scanning low vcal = 30
[11:10:05.059] <TB1> INFO: Expecting 41600 events.
[11:10:08.778] <TB1> INFO: 41600 events read in total (3127ms).
[11:10:08.779] <TB1> INFO: Test took 4020ms.
[11:10:08.782] <TB1> INFO: scanning low vcal = 40
[11:10:09.094] <TB1> INFO: Expecting 41600 events.
[11:10:13.048] <TB1> INFO: 41600 events read in total (3362ms).
[11:10:13.049] <TB1> INFO: Test took 4267ms.
[11:10:13.052] <TB1> INFO: scanning low vcal = 50
[11:10:13.370] <TB1> INFO: Expecting 41600 events.
[11:10:17.407] <TB1> INFO: 41600 events read in total (3445ms).
[11:10:17.408] <TB1> INFO: Test took 4355ms.
[11:10:17.412] <TB1> INFO: scanning low vcal = 60
[11:10:17.687] <TB1> INFO: Expecting 41600 events.
[11:10:21.778] <TB1> INFO: 41600 events read in total (3499ms).
[11:10:21.779] <TB1> INFO: Test took 4367ms.
[11:10:21.783] <TB1> INFO: scanning low vcal = 70
[11:10:22.101] <TB1> INFO: Expecting 41600 events.
[11:10:26.129] <TB1> INFO: 41600 events read in total (3436ms).
[11:10:26.130] <TB1> INFO: Test took 4347ms.
[11:10:26.134] <TB1> INFO: scanning low vcal = 80
[11:10:26.449] <TB1> INFO: Expecting 41600 events.
[11:10:30.447] <TB1> INFO: 41600 events read in total (3406ms).
[11:10:30.447] <TB1> INFO: Test took 4313ms.
[11:10:30.451] <TB1> INFO: scanning low vcal = 90
[11:10:30.767] <TB1> INFO: Expecting 41600 events.
[11:10:34.765] <TB1> INFO: 41600 events read in total (3406ms).
[11:10:34.766] <TB1> INFO: Test took 4315ms.
[11:10:34.770] <TB1> INFO: scanning low vcal = 100
[11:10:35.045] <TB1> INFO: Expecting 41600 events.
[11:10:39.069] <TB1> INFO: 41600 events read in total (3432ms).
[11:10:39.070] <TB1> INFO: Test took 4300ms.
[11:10:39.074] <TB1> INFO: scanning low vcal = 110
[11:10:39.386] <TB1> INFO: Expecting 41600 events.
[11:10:43.482] <TB1> INFO: 41600 events read in total (3504ms).
[11:10:43.483] <TB1> INFO: Test took 4409ms.
[11:10:43.487] <TB1> INFO: scanning low vcal = 120
[11:10:43.802] <TB1> INFO: Expecting 41600 events.
[11:10:47.805] <TB1> INFO: 41600 events read in total (3411ms).
[11:10:47.806] <TB1> INFO: Test took 4319ms.
[11:10:47.809] <TB1> INFO: scanning low vcal = 130
[11:10:48.124] <TB1> INFO: Expecting 41600 events.
[11:10:52.092] <TB1> INFO: 41600 events read in total (3376ms).
[11:10:52.093] <TB1> INFO: Test took 4284ms.
[11:10:52.097] <TB1> INFO: scanning low vcal = 140
[11:10:52.373] <TB1> INFO: Expecting 41600 events.
[11:10:56.335] <TB1> INFO: 41600 events read in total (3370ms).
[11:10:56.336] <TB1> INFO: Test took 4239ms.
[11:10:56.339] <TB1> INFO: scanning low vcal = 150
[11:10:56.616] <TB1> INFO: Expecting 41600 events.
[11:11:00.574] <TB1> INFO: 41600 events read in total (3366ms).
[11:11:00.575] <TB1> INFO: Test took 4236ms.
[11:11:00.579] <TB1> INFO: scanning low vcal = 160
[11:11:00.855] <TB1> INFO: Expecting 41600 events.
[11:11:04.820] <TB1> INFO: 41600 events read in total (3373ms).
[11:11:04.820] <TB1> INFO: Test took 4242ms.
[11:11:04.824] <TB1> INFO: scanning low vcal = 170
[11:11:05.101] <TB1> INFO: Expecting 41600 events.
[11:11:09.094] <TB1> INFO: 41600 events read in total (3402ms).
[11:11:09.095] <TB1> INFO: Test took 4271ms.
[11:11:09.102] <TB1> INFO: scanning low vcal = 180
[11:11:09.376] <TB1> INFO: Expecting 41600 events.
[11:11:13.339] <TB1> INFO: 41600 events read in total (3371ms).
[11:11:13.340] <TB1> INFO: Test took 4238ms.
[11:11:13.343] <TB1> INFO: scanning low vcal = 190
[11:11:13.620] <TB1> INFO: Expecting 41600 events.
[11:11:17.620] <TB1> INFO: 41600 events read in total (3409ms).
[11:11:17.621] <TB1> INFO: Test took 4278ms.
[11:11:17.624] <TB1> INFO: scanning low vcal = 200
[11:11:17.901] <TB1> INFO: Expecting 41600 events.
[11:11:21.867] <TB1> INFO: 41600 events read in total (3374ms).
[11:11:21.868] <TB1> INFO: Test took 4244ms.
[11:11:21.871] <TB1> INFO: scanning low vcal = 210
[11:11:22.148] <TB1> INFO: Expecting 41600 events.
[11:11:26.105] <TB1> INFO: 41600 events read in total (3365ms).
[11:11:26.106] <TB1> INFO: Test took 4235ms.
[11:11:26.109] <TB1> INFO: scanning low vcal = 220
[11:11:26.386] <TB1> INFO: Expecting 41600 events.
[11:11:30.343] <TB1> INFO: 41600 events read in total (3365ms).
[11:11:30.344] <TB1> INFO: Test took 4235ms.
[11:11:30.348] <TB1> INFO: scanning low vcal = 230
[11:11:30.625] <TB1> INFO: Expecting 41600 events.
[11:11:34.588] <TB1> INFO: 41600 events read in total (3371ms).
[11:11:34.589] <TB1> INFO: Test took 4241ms.
[11:11:34.592] <TB1> INFO: scanning low vcal = 240
[11:11:34.869] <TB1> INFO: Expecting 41600 events.
[11:11:38.832] <TB1> INFO: 41600 events read in total (3371ms).
[11:11:38.833] <TB1> INFO: Test took 4240ms.
[11:11:38.836] <TB1> INFO: scanning low vcal = 250
[11:11:39.113] <TB1> INFO: Expecting 41600 events.
[11:11:43.078] <TB1> INFO: 41600 events read in total (3373ms).
[11:11:43.079] <TB1> INFO: Test took 4243ms.
[11:11:43.083] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[11:11:43.359] <TB1> INFO: Expecting 41600 events.
[11:11:47.324] <TB1> INFO: 41600 events read in total (3373ms).
[11:11:47.325] <TB1> INFO: Test took 4242ms.
[11:11:47.328] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[11:11:47.605] <TB1> INFO: Expecting 41600 events.
[11:11:51.563] <TB1> INFO: 41600 events read in total (3366ms).
[11:11:51.564] <TB1> INFO: Test took 4236ms.
[11:11:51.568] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[11:11:51.844] <TB1> INFO: Expecting 41600 events.
[11:11:55.806] <TB1> INFO: 41600 events read in total (3370ms).
[11:11:55.807] <TB1> INFO: Test took 4239ms.
[11:11:55.811] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[11:11:56.087] <TB1> INFO: Expecting 41600 events.
[11:12:00.041] <TB1> INFO: 41600 events read in total (3362ms).
[11:12:00.043] <TB1> INFO: Test took 4232ms.
[11:12:00.046] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[11:12:00.323] <TB1> INFO: Expecting 41600 events.
[11:12:04.273] <TB1> INFO: 41600 events read in total (3358ms).
[11:12:04.274] <TB1> INFO: Test took 4228ms.
[11:12:04.659] <TB1> INFO: PixTestGainPedestal::measure() done
[11:12:36.699] <TB1> INFO: PixTestGainPedestal::fit() done
[11:12:36.699] <TB1> INFO: non-linearity mean: 0.955 0.984 0.968 1.025 0.932 0.978 0.944 0.960 0.936 0.969 0.974 0.948 0.951 0.944 0.942 0.961
[11:12:36.699] <TB1> INFO: non-linearity RMS: 0.155 0.004 0.023 0.167 0.088 0.008 0.125 0.045 0.127 0.031 0.021 0.141 0.059 0.090 0.088 0.053
[11:12:36.699] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr35_C0.dat
[11:12:36.714] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr35_C1.dat
[11:12:36.727] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr35_C2.dat
[11:12:36.740] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr35_C3.dat
[11:12:36.754] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr35_C4.dat
[11:12:36.767] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr35_C5.dat
[11:12:36.780] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr35_C6.dat
[11:12:36.793] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr35_C7.dat
[11:12:36.807] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr35_C8.dat
[11:12:36.820] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr35_C9.dat
[11:12:36.832] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr35_C10.dat
[11:12:36.846] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr35_C11.dat
[11:12:36.859] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr35_C12.dat
[11:12:36.873] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr35_C13.dat
[11:12:36.886] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr35_C14.dat
[11:12:36.899] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-14_16h15m_1479136518//002_Fulltest_p17//phCalibrationFitErr35_C15.dat
[11:12:36.912] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 159 seconds
[11:12:36.912] <TB1> INFO: Decoding statistics:
[11:12:36.912] <TB1> INFO: General information:
[11:12:36.912] <TB1> INFO: 16bit words read: 3262610
[11:12:36.912] <TB1> INFO: valid events total: 332800
[11:12:36.912] <TB1> INFO: empty events: 792
[11:12:36.912] <TB1> INFO: valid events with pixels: 332008
[11:12:36.912] <TB1> INFO: valid pixel hits: 632884
[11:12:36.912] <TB1> INFO: Event errors: 0
[11:12:36.912] <TB1> INFO: start marker: 0
[11:12:36.912] <TB1> INFO: stop marker: 0
[11:12:36.912] <TB1> INFO: overflow: 0
[11:12:36.912] <TB1> INFO: invalid 5bit words: 0
[11:12:36.912] <TB1> INFO: invalid XOR eye diagram: 0
[11:12:36.912] <TB1> INFO: frame (failed synchr.): 0
[11:12:36.912] <TB1> INFO: idle data (no TBM trl): 0
[11:12:36.912] <TB1> INFO: no data (only TBM hdr): 0
[11:12:36.912] <TB1> INFO: TBM errors: 0
[11:12:36.912] <TB1> INFO: flawed TBM headers: 0
[11:12:36.912] <TB1> INFO: flawed TBM trailers: 0
[11:12:36.912] <TB1> INFO: event ID mismatches: 0
[11:12:36.912] <TB1> INFO: ROC errors: 0
[11:12:36.912] <TB1> INFO: missing ROC header(s): 0
[11:12:36.912] <TB1> INFO: misplaced readback start: 0
[11:12:36.912] <TB1> INFO: Pixel decoding errors: 21
[11:12:36.912] <TB1> INFO: pixel data incomplete: 0
[11:12:36.912] <TB1> INFO: pixel address: 0
[11:12:36.912] <TB1> INFO: pulse height fill bit: 0
[11:12:36.912] <TB1> INFO: buffer corruption: 21
[11:12:36.933] <TB1> INFO: Decoding statistics:
[11:12:36.933] <TB1> INFO: General information:
[11:12:36.933] <TB1> INFO: 16bit words read: 3392018
[11:12:36.933] <TB1> INFO: valid events total: 353536
[11:12:36.933] <TB1> INFO: empty events: 19032
[11:12:36.933] <TB1> INFO: valid events with pixels: 334504
[11:12:36.933] <TB1> INFO: valid pixel hits: 635380
[11:12:36.933] <TB1> INFO: Event errors: 0
[11:12:36.933] <TB1> INFO: start marker: 0
[11:12:36.933] <TB1> INFO: stop marker: 0
[11:12:36.933] <TB1> INFO: overflow: 0
[11:12:36.933] <TB1> INFO: invalid 5bit words: 0
[11:12:36.933] <TB1> INFO: invalid XOR eye diagram: 0
[11:12:36.933] <TB1> INFO: frame (failed synchr.): 0
[11:12:36.933] <TB1> INFO: idle data (no TBM trl): 0
[11:12:36.933] <TB1> INFO: no data (only TBM hdr): 0
[11:12:36.933] <TB1> INFO: TBM errors: 0
[11:12:36.933] <TB1> INFO: flawed TBM headers: 0
[11:12:36.933] <TB1> INFO: flawed TBM trailers: 0
[11:12:36.933] <TB1> INFO: event ID mismatches: 0
[11:12:36.933] <TB1> INFO: ROC errors: 0
[11:12:36.933] <TB1> INFO: missing ROC header(s): 0
[11:12:36.933] <TB1> INFO: misplaced readback start: 0
[11:12:36.933] <TB1> INFO: Pixel decoding errors: 21
[11:12:36.933] <TB1> INFO: pixel data incomplete: 0
[11:12:36.933] <TB1> INFO: pixel address: 0
[11:12:36.933] <TB1> INFO: pulse height fill bit: 0
[11:12:36.933] <TB1> INFO: buffer corruption: 21
[11:12:36.933] <TB1> INFO: enter test to run
[11:12:36.933] <TB1> INFO: test: exit no parameter change
[11:12:37.081] <TB1> QUIET: Connection to board 154 closed.
[11:12:37.083] <TB1> INFO: pXar: this is the end, my friend