[13:46:45.067] <TB1> INFO: *** Welcome to pxar ***
[13:46:45.067] <TB1> INFO: *** Today: 2016/11/15
[13:46:45.073] <TB1> INFO: *** Version: c8ba-dirty
[13:46:45.073] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C15.dat
[13:46:45.073] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//tbmParameters_C1b.dat
[13:46:45.073] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//defaultMaskFile.dat
[13:46:45.073] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters_C15.dat
[13:46:45.132] <TB1> INFO: clk: 4
[13:46:45.132] <TB1> INFO: ctr: 4
[13:46:45.132] <TB1> INFO: sda: 19
[13:46:45.132] <TB1> INFO: tin: 9
[13:46:45.132] <TB1> INFO: level: 15
[13:46:45.132] <TB1> INFO: triggerdelay: 0
[13:46:45.132] <TB1> QUIET: Instanciating API for pxar v2.7.6+77~g4811f5c
[13:46:45.133] <TB1> INFO: Log level: INFO
[13:46:45.142] <TB1> INFO: Found DTB DTB_WXC03A
[13:46:45.154] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[13:46:45.155] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
------------------------------------------------------
[13:46:45.157] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[13:46:46.641] <TB1> INFO: DUT info:
[13:46:46.641] <TB1> INFO: The DUT currently contains the following objects:
[13:46:46.641] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[13:46:46.641] <TB1> INFO: TBM Core alpha (0): 7 registers set
[13:46:46.641] <TB1> INFO: TBM Core beta (1): 7 registers set
[13:46:46.641] <TB1> INFO: TBM Core alpha (2): 7 registers set
[13:46:46.641] <TB1> INFO: TBM Core beta (3): 7 registers set
[13:46:46.641] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[13:46:46.641] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[13:46:46.641] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[13:46:46.641] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[13:46:46.641] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[13:46:46.641] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[13:46:46.641] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[13:46:46.641] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[13:46:46.641] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[13:46:46.642] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[13:46:46.642] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[13:46:46.642] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[13:46:46.642] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[13:46:46.642] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[13:46:46.642] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[13:46:46.642] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[13:46:46.642] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[13:46:47.042] <TB1> INFO: enter 'restricted' command line mode
[13:46:47.042] <TB1> INFO: enter test to run
[13:46:47.042] <TB1> INFO: test: pretest no parameter change
[13:46:47.042] <TB1> INFO: running: pretest
[13:46:47.048] <TB1> INFO: ######################################################################
[13:46:47.048] <TB1> INFO: PixTestPretest::doTest()
[13:46:47.048] <TB1> INFO: ######################################################################
[13:46:47.049] <TB1> INFO: ----------------------------------------------------------------------
[13:46:47.049] <TB1> INFO: PixTestPretest::programROC()
[13:46:47.049] <TB1> INFO: ----------------------------------------------------------------------
[13:47:05.063] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[13:47:05.063] <TB1> INFO: IA differences per ROC: 20.9 17.7 20.9 19.3 16.1 21.7 16.1 19.3 16.9 18.5 17.7 19.3 16.9 20.9 20.1 16.9
[13:47:05.116] <TB1> INFO: ----------------------------------------------------------------------
[13:47:05.116] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[13:47:05.116] <TB1> INFO: ----------------------------------------------------------------------
[13:47:26.347] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 387.5 mA = 24.2188 mA/ROC
[13:47:26.347] <TB1> INFO: i(loss) [mA/ROC]: 19.3 20.1 19.3 18.5 20.1 19.3 18.5 19.3 19.3 18.5 20.1 18.5 19.3 19.3 18.5 19.3
[13:47:26.373] <TB1> INFO: ----------------------------------------------------------------------
[13:47:26.373] <TB1> INFO: PixTestPretest::findTiming()
[13:47:26.373] <TB1> INFO: ----------------------------------------------------------------------
[13:47:26.373] <TB1> INFO: PixTestCmd::init()

[13:47:57.362] <TB1> INFO: TBM phases: 160MHz: 7, 400MHz: 6, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[13:47:57.362] <TB1> INFO: (success/tries = 100/100), width = 4
[13:47:58.870] <TB1> INFO: ----------------------------------------------------------------------
[13:47:58.870] <TB1> INFO: PixTestPretest::findWorkingPixel()
[13:47:58.870] <TB1> INFO: ----------------------------------------------------------------------
[13:47:58.962] <TB1> INFO: Expecting 231680 events.
[13:48:08.679] <TB1> INFO: 231680 events read in total (9125ms).
[13:48:08.688] <TB1> INFO: Test took 9815ms.
[13:48:08.934] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[13:48:08.962] <TB1> INFO: ----------------------------------------------------------------------
[13:48:08.962] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[13:48:08.962] <TB1> INFO: ----------------------------------------------------------------------
[13:48:09.054] <TB1> INFO: Expecting 231680 events.
[13:48:18.680] <TB1> INFO: 231680 events read in total (9034ms).
[13:48:18.692] <TB1> INFO: Test took 9726ms.
[13:48:18.940] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[13:48:18.940] <TB1> INFO: CalDel: 107 107 96 102 82 108 86 91 87 112 87 109 94 109 102 95
[13:48:18.940] <TB1> INFO: VthrComp: 51 51 51 51 57 56 51 51 51 51 51 51 51 51 51 54
[13:48:18.942] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C0.dat
[13:48:18.942] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C1.dat
[13:48:18.942] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C2.dat
[13:48:18.943] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C3.dat
[13:48:18.943] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C4.dat
[13:48:18.943] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C5.dat
[13:48:18.943] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C6.dat
[13:48:18.943] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C7.dat
[13:48:18.943] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C8.dat
[13:48:18.943] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C9.dat
[13:48:18.943] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C10.dat
[13:48:18.943] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C11.dat
[13:48:18.943] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C12.dat
[13:48:18.943] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C13.dat
[13:48:18.943] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C14.dat
[13:48:18.943] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters_C15.dat
[13:48:18.944] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//tbmParameters_C0a.dat
[13:48:18.944] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//tbmParameters_C0b.dat
[13:48:18.944] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//tbmParameters_C1a.dat
[13:48:18.944] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//tbmParameters_C1b.dat
[13:48:18.944] <TB1> INFO: PixTestPretest::doTest() done, duration: 91 seconds
[13:48:18.997] <TB1> INFO: enter test to run
[13:48:18.997] <TB1> INFO: test: FullTest no parameter change
[13:48:18.997] <TB1> INFO: running: fulltest
[13:48:18.997] <TB1> INFO: ######################################################################
[13:48:18.997] <TB1> INFO: PixTestFullTest::doTest()
[13:48:18.997] <TB1> INFO: ######################################################################
[13:48:18.998] <TB1> INFO: ######################################################################
[13:48:18.998] <TB1> INFO: PixTestAlive::doTest()
[13:48:18.998] <TB1> INFO: ######################################################################
[13:48:18.999] <TB1> INFO: ----------------------------------------------------------------------
[13:48:18.999] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:48:18.999] <TB1> INFO: ----------------------------------------------------------------------
[13:48:19.239] <TB1> INFO: Expecting 41600 events.
[13:48:22.700] <TB1> INFO: 41600 events read in total (2869ms).
[13:48:22.701] <TB1> INFO: Test took 3700ms.
[13:48:22.927] <TB1> INFO: PixTestAlive::aliveTest() done
[13:48:22.927] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:48:22.928] <TB1> INFO: ----------------------------------------------------------------------
[13:48:22.928] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:48:22.928] <TB1> INFO: ----------------------------------------------------------------------
[13:48:23.167] <TB1> INFO: Expecting 41600 events.
[13:48:26.106] <TB1> INFO: 41600 events read in total (2347ms).
[13:48:26.106] <TB1> INFO: Test took 3177ms.
[13:48:26.106] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[13:48:26.344] <TB1> INFO: PixTestAlive::maskTest() done
[13:48:26.344] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:48:26.346] <TB1> INFO: ----------------------------------------------------------------------
[13:48:26.346] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:48:26.346] <TB1> INFO: ----------------------------------------------------------------------
[13:48:26.578] <TB1> INFO: Expecting 41600 events.
[13:48:30.036] <TB1> INFO: 41600 events read in total (2866ms).
[13:48:30.037] <TB1> INFO: Test took 3690ms.
[13:48:30.265] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[13:48:30.265] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:48:30.265] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[13:48:30.265] <TB1> INFO: Decoding statistics:
[13:48:30.265] <TB1> INFO: General information:
[13:48:30.265] <TB1> INFO: 16bit words read: 0
[13:48:30.265] <TB1> INFO: valid events total: 0
[13:48:30.265] <TB1> INFO: empty events: 0
[13:48:30.265] <TB1> INFO: valid events with pixels: 0
[13:48:30.265] <TB1> INFO: valid pixel hits: 0
[13:48:30.265] <TB1> INFO: Event errors: 0
[13:48:30.265] <TB1> INFO: start marker: 0
[13:48:30.265] <TB1> INFO: stop marker: 0
[13:48:30.265] <TB1> INFO: overflow: 0
[13:48:30.265] <TB1> INFO: invalid 5bit words: 0
[13:48:30.265] <TB1> INFO: invalid XOR eye diagram: 0
[13:48:30.265] <TB1> INFO: frame (failed synchr.): 0
[13:48:30.265] <TB1> INFO: idle data (no TBM trl): 0
[13:48:30.265] <TB1> INFO: no data (only TBM hdr): 0
[13:48:30.265] <TB1> INFO: TBM errors: 0
[13:48:30.265] <TB1> INFO: flawed TBM headers: 0
[13:48:30.265] <TB1> INFO: flawed TBM trailers: 0
[13:48:30.265] <TB1> INFO: event ID mismatches: 0
[13:48:30.265] <TB1> INFO: ROC errors: 0
[13:48:30.265] <TB1> INFO: missing ROC header(s): 0
[13:48:30.265] <TB1> INFO: misplaced readback start: 0
[13:48:30.265] <TB1> INFO: Pixel decoding errors: 0
[13:48:30.265] <TB1> INFO: pixel data incomplete: 0
[13:48:30.265] <TB1> INFO: pixel address: 0
[13:48:30.265] <TB1> INFO: pulse height fill bit: 0
[13:48:30.265] <TB1> INFO: buffer corruption: 0
[13:48:30.270] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C15.dat
[13:48:30.271] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr_C15.dat

[13:48:30.271] <TB1> INFO: ######################################################################
[13:48:30.271] <TB1> INFO: PixTestReadback::doTest()
[13:48:30.271] <TB1> INFO: ######################################################################
[13:48:30.271] <TB1> INFO: ----------------------------------------------------------------------
[13:48:30.271] <TB1> INFO: PixTestReadback::CalibrateVd()
[13:48:30.271] <TB1> INFO: ----------------------------------------------------------------------
[13:48:40.194] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C0.dat
[13:48:40.195] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C1.dat
[13:48:40.195] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C2.dat
[13:48:40.195] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C3.dat
[13:48:40.195] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C4.dat
[13:48:40.195] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C5.dat
[13:48:40.195] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C6.dat
[13:48:40.195] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C7.dat
[13:48:40.195] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C8.dat
[13:48:40.195] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C9.dat
[13:48:40.195] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C10.dat
[13:48:40.195] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C11.dat
[13:48:40.195] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C12.dat
[13:48:40.195] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C13.dat
[13:48:40.196] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C14.dat
[13:48:40.196] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C15.dat
[13:48:40.223] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[13:48:40.223] <TB1> INFO: ----------------------------------------------------------------------
[13:48:40.223] <TB1> INFO: PixTestReadback::CalibrateVa()
[13:48:40.223] <TB1> INFO: ----------------------------------------------------------------------
[13:48:50.122] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C0.dat
[13:48:50.123] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C1.dat
[13:48:50.123] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C2.dat
[13:48:50.123] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C3.dat
[13:48:50.123] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C4.dat
[13:48:50.123] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C5.dat
[13:48:50.123] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C6.dat
[13:48:50.123] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C7.dat
[13:48:50.123] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C8.dat
[13:48:50.123] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C9.dat
[13:48:50.123] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C10.dat
[13:48:50.123] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C11.dat
[13:48:50.123] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C12.dat
[13:48:50.123] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C13.dat
[13:48:50.123] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C14.dat
[13:48:50.123] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C15.dat
[13:48:50.152] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[13:48:50.152] <TB1> INFO: ----------------------------------------------------------------------
[13:48:50.152] <TB1> INFO: PixTestReadback::readbackVbg()
[13:48:50.152] <TB1> INFO: ----------------------------------------------------------------------
[13:48:57.800] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[13:48:57.800] <TB1> INFO: ----------------------------------------------------------------------
[13:48:57.800] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[13:48:57.800] <TB1> INFO: ----------------------------------------------------------------------
[13:48:57.800] <TB1> INFO: Vbg will be calibrated using Vd calibration
[13:48:57.800] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 162.8calibrated Vbg = 1.19065 :::*/*/*/*/
[13:48:57.800] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 147.7calibrated Vbg = 1.17528 :::*/*/*/*/
[13:48:57.800] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 157.7calibrated Vbg = 1.17586 :::*/*/*/*/
[13:48:57.800] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 150.5calibrated Vbg = 1.17704 :::*/*/*/*/
[13:48:57.800] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 163.9calibrated Vbg = 1.17474 :::*/*/*/*/
[13:48:57.800] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 164.6calibrated Vbg = 1.18172 :::*/*/*/*/
[13:48:57.800] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 157.6calibrated Vbg = 1.18438 :::*/*/*/*/
[13:48:57.800] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 161calibrated Vbg = 1.18623 :::*/*/*/*/
[13:48:57.800] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 166calibrated Vbg = 1.18077 :::*/*/*/*/
[13:48:57.800] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 158.8calibrated Vbg = 1.17649 :::*/*/*/*/
[13:48:57.800] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 157.1calibrated Vbg = 1.17311 :::*/*/*/*/
[13:48:57.800] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 151.4calibrated Vbg = 1.16837 :::*/*/*/*/
[13:48:57.800] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 149calibrated Vbg = 1.17407 :::*/*/*/*/
[13:48:57.800] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 159.1calibrated Vbg = 1.18049 :::*/*/*/*/
[13:48:57.800] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 148.2calibrated Vbg = 1.1786 :::*/*/*/*/
[13:48:57.800] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 158.6calibrated Vbg = 1.17487 :::*/*/*/*/
[13:48:57.802] <TB1> INFO: ----------------------------------------------------------------------
[13:48:57.802] <TB1> INFO: PixTestReadback::CalibrateIa()
[13:48:57.802] <TB1> INFO: ----------------------------------------------------------------------
[13:51:38.162] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C0.dat
[13:51:38.163] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C1.dat
[13:51:38.163] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C2.dat
[13:51:38.163] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C3.dat
[13:51:38.163] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C4.dat
[13:51:38.163] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C5.dat
[13:51:38.163] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C6.dat
[13:51:38.163] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C7.dat
[13:51:38.163] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C8.dat
[13:51:38.163] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C9.dat
[13:51:38.163] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C10.dat
[13:51:38.164] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C11.dat
[13:51:38.164] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C12.dat
[13:51:38.164] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C13.dat
[13:51:38.164] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C14.dat
[13:51:38.164] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//readbackCal_C15.dat
[13:51:38.190] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[13:51:38.191] <TB1> INFO: PixTestReadback::doTest() done
[13:51:38.191] <TB1> INFO: Decoding statistics:
[13:51:38.191] <TB1> INFO: General information:
[13:51:38.191] <TB1> INFO: 16bit words read: 1536
[13:51:38.191] <TB1> INFO: valid events total: 256
[13:51:38.191] <TB1> INFO: empty events: 256
[13:51:38.191] <TB1> INFO: valid events with pixels: 0
[13:51:38.191] <TB1> INFO: valid pixel hits: 0
[13:51:38.191] <TB1> INFO: Event errors: 0
[13:51:38.191] <TB1> INFO: start marker: 0
[13:51:38.191] <TB1> INFO: stop marker: 0
[13:51:38.191] <TB1> INFO: overflow: 0
[13:51:38.191] <TB1> INFO: invalid 5bit words: 0
[13:51:38.191] <TB1> INFO: invalid XOR eye diagram: 0
[13:51:38.191] <TB1> INFO: frame (failed synchr.): 0
[13:51:38.192] <TB1> INFO: idle data (no TBM trl): 0
[13:51:38.192] <TB1> INFO: no data (only TBM hdr): 0
[13:51:38.192] <TB1> INFO: TBM errors: 0
[13:51:38.192] <TB1> INFO: flawed TBM headers: 0
[13:51:38.192] <TB1> INFO: flawed TBM trailers: 0
[13:51:38.192] <TB1> INFO: event ID mismatches: 0
[13:51:38.192] <TB1> INFO: ROC errors: 0
[13:51:38.192] <TB1> INFO: missing ROC header(s): 0
[13:51:38.192] <TB1> INFO: misplaced readback start: 0
[13:51:38.192] <TB1> INFO: Pixel decoding errors: 0
[13:51:38.192] <TB1> INFO: pixel data incomplete: 0
[13:51:38.192] <TB1> INFO: pixel address: 0
[13:51:38.192] <TB1> INFO: pulse height fill bit: 0
[13:51:38.192] <TB1> INFO: buffer corruption: 0
[13:51:38.243] <TB1> INFO: ######################################################################
[13:51:38.243] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[13:51:38.243] <TB1> INFO: ######################################################################
[13:51:38.246] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[13:51:38.268] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:51:38.268] <TB1> INFO: run 1 of 1
[13:51:38.508] <TB1> INFO: Expecting 3120000 events.
[13:52:08.947] <TB1> INFO: 664310 events read in total (29847ms).
[13:52:38.275] <TB1> INFO: 1324985 events read in total (59175ms).











[13:53:07.604] <TB1> INFO: 1984355 events read in total (88504ms).











[13:53:36.754] <TB1> INFO: 2642770 events read in total (117654ms).











[13:53:57.773] <TB1> INFO: 3120000 events read in total (138673ms).
[13:53:57.868] <TB1> INFO: Test took 139601ms.
[13:54:17.874] <TB1> INFO: PixTestBBMap::doTest() done, duration: 159 seconds
[13:54:17.874] <TB1> INFO: number of dead bumps (per ROC): 1 0 1 0 5 0 1 0 1 1 0 0 1 0 0 0
[13:54:17.874] <TB1> INFO: separation cut (per ROC): 103 104 111 108 110 114 105 101 105 94 112 106 102 93 105 107
[13:54:17.874] <TB1> INFO: Decoding statistics:
[13:54:17.874] <TB1> INFO: General information:
[13:54:17.874] <TB1> INFO: 16bit words read: 0
[13:54:17.874] <TB1> INFO: valid events total: 0
[13:54:17.874] <TB1> INFO: empty events: 0
[13:54:17.874] <TB1> INFO: valid events with pixels: 0
[13:54:17.874] <TB1> INFO: valid pixel hits: 0
[13:54:17.874] <TB1> INFO: Event errors: 0
[13:54:17.874] <TB1> INFO: start marker: 0
[13:54:17.874] <TB1> INFO: stop marker: 0
[13:54:17.874] <TB1> INFO: overflow: 0
[13:54:17.874] <TB1> INFO: invalid 5bit words: 0
[13:54:17.874] <TB1> INFO: invalid XOR eye diagram: 0
[13:54:17.874] <TB1> INFO: frame (failed synchr.): 0
[13:54:17.874] <TB1> INFO: idle data (no TBM trl): 0
[13:54:17.874] <TB1> INFO: no data (only TBM hdr): 0
[13:54:17.874] <TB1> INFO: TBM errors: 0
[13:54:17.874] <TB1> INFO: flawed TBM headers: 0
[13:54:17.874] <TB1> INFO: flawed TBM trailers: 0
[13:54:17.874] <TB1> INFO: event ID mismatches: 0
[13:54:17.874] <TB1> INFO: ROC errors: 0
[13:54:17.875] <TB1> INFO: missing ROC header(s): 0
[13:54:17.875] <TB1> INFO: misplaced readback start: 0
[13:54:17.875] <TB1> INFO: Pixel decoding errors: 0
[13:54:17.875] <TB1> INFO: pixel data incomplete: 0
[13:54:17.875] <TB1> INFO: pixel address: 0
[13:54:17.875] <TB1> INFO: pulse height fill bit: 0
[13:54:17.875] <TB1> INFO: buffer corruption: 0
[13:54:17.915] <TB1> INFO: ######################################################################
[13:54:17.915] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:54:17.915] <TB1> INFO: ######################################################################
[13:54:17.915] <TB1> INFO: ----------------------------------------------------------------------
[13:54:17.915] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:54:17.915] <TB1> INFO: ----------------------------------------------------------------------
[13:54:17.915] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[13:54:17.931] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[13:54:17.931] <TB1> INFO: run 1 of 1
[13:54:18.183] <TB1> INFO: Expecting 36608000 events.
[13:54:40.847] <TB1> INFO: 681950 events read in total (22072ms).
[13:55:02.855] <TB1> INFO: 1350850 events read in total (44080ms).
[13:55:24.442] <TB1> INFO: 2015800 events read in total (65667ms).
[13:55:46.253] <TB1> INFO: 2683000 events read in total (87478ms).
[13:56:07.763] <TB1> INFO: 3349500 events read in total (108988ms).
[13:56:29.456] <TB1> INFO: 4015900 events read in total (130681ms).
[13:56:51.208] <TB1> INFO: 4681550 events read in total (152433ms).
[13:57:13.211] <TB1> INFO: 5347450 events read in total (174436ms).
[13:57:34.863] <TB1> INFO: 6011600 events read in total (196088ms).
[13:57:56.492] <TB1> INFO: 6677700 events read in total (217717ms).
[13:58:18.158] <TB1> INFO: 7342050 events read in total (239383ms).
[13:58:39.825] <TB1> INFO: 8005300 events read in total (261050ms).
[13:59:01.579] <TB1> INFO: 8670300 events read in total (282804ms).
[13:59:23.323] <TB1> INFO: 9335450 events read in total (304548ms).
[13:59:45.067] <TB1> INFO: 10000850 events read in total (326292ms).
[14:00:06.761] <TB1> INFO: 10663950 events read in total (347986ms).
[14:00:28.550] <TB1> INFO: 11328650 events read in total (369775ms).
[14:00:50.232] <TB1> INFO: 11991850 events read in total (391457ms).
[14:01:11.915] <TB1> INFO: 12654150 events read in total (413140ms).
[14:01:33.625] <TB1> INFO: 13318400 events read in total (434850ms).
[14:01:55.364] <TB1> INFO: 13980900 events read in total (456589ms).
[14:02:17.091] <TB1> INFO: 14642850 events read in total (478316ms).
[14:02:38.809] <TB1> INFO: 15306900 events read in total (500034ms).
[14:03:00.490] <TB1> INFO: 15969050 events read in total (521715ms).
[14:03:22.724] <TB1> INFO: 16632400 events read in total (543949ms).
[14:03:44.412] <TB1> INFO: 17296150 events read in total (565637ms).
[14:04:06.089] <TB1> INFO: 17958900 events read in total (587314ms).
[14:04:27.902] <TB1> INFO: 18619850 events read in total (609127ms).
[14:04:50.040] <TB1> INFO: 19280700 events read in total (631265ms).
[14:05:11.635] <TB1> INFO: 19941850 events read in total (652860ms).
[14:05:33.738] <TB1> INFO: 20602400 events read in total (674963ms).
[14:05:56.029] <TB1> INFO: 21263050 events read in total (697254ms).
[14:06:17.723] <TB1> INFO: 21922050 events read in total (718949ms).
[14:06:39.385] <TB1> INFO: 22580350 events read in total (740610ms).
[14:07:01.015] <TB1> INFO: 23238550 events read in total (762240ms).
[14:07:23.046] <TB1> INFO: 23898650 events read in total (784271ms).
[14:07:44.668] <TB1> INFO: 24556550 events read in total (805893ms).
[14:08:06.310] <TB1> INFO: 25215750 events read in total (827535ms).
[14:08:28.372] <TB1> INFO: 25875400 events read in total (849597ms).
[14:08:49.965] <TB1> INFO: 26532750 events read in total (871190ms).
[14:09:11.618] <TB1> INFO: 27191200 events read in total (892843ms).
[14:09:33.548] <TB1> INFO: 27849550 events read in total (914773ms).
[14:09:55.212] <TB1> INFO: 28508350 events read in total (936437ms).
[14:10:16.626] <TB1> INFO: 29166700 events read in total (957851ms).
[14:10:38.229] <TB1> INFO: 29824050 events read in total (979454ms).
[14:10:59.971] <TB1> INFO: 30480500 events read in total (1001196ms).
[14:11:21.725] <TB1> INFO: 31137450 events read in total (1022950ms).
[14:11:43.335] <TB1> INFO: 31794400 events read in total (1044560ms).
[14:12:05.093] <TB1> INFO: 32452650 events read in total (1066318ms).
[14:12:26.705] <TB1> INFO: 33110800 events read in total (1087930ms).
[14:12:49.183] <TB1> INFO: 33769600 events read in total (1110408ms).
[14:13:10.839] <TB1> INFO: 34428350 events read in total (1132064ms).
[14:13:32.748] <TB1> INFO: 35087250 events read in total (1153973ms).
[14:13:54.448] <TB1> INFO: 35748700 events read in total (1175673ms).
[14:14:16.478] <TB1> INFO: 36419450 events read in total (1197703ms).
[14:14:22.861] <TB1> INFO: 36608000 events read in total (1204086ms).
[14:14:22.939] <TB1> INFO: Test took 1205008ms.
[14:14:23.282] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:14:24.749] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:14:26.285] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:14:27.792] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:14:29.269] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:14:30.761] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:14:32.224] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:14:33.680] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:14:35.162] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:14:36.655] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:14:38.137] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:14:39.619] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:14:41.140] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:14:42.683] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:14:44.156] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:14:45.671] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[14:14:47.206] <TB1> INFO: PixTestScurves::scurves() done
[14:14:47.206] <TB1> INFO: Vcal mean: 110.45 112.32 121.71 113.28 114.58 131.36 115.47 109.83 119.68 109.99 120.23 110.13 113.63 109.04 116.38 116.58
[14:14:47.206] <TB1> INFO: Vcal RMS: 4.68 5.20 6.55 5.20 6.49 8.33 5.62 5.43 5.91 6.19 6.27 5.27 5.26 5.33 6.77 5.56
[14:14:47.206] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1229 seconds
[14:14:47.206] <TB1> INFO: Decoding statistics:
[14:14:47.206] <TB1> INFO: General information:
[14:14:47.206] <TB1> INFO: 16bit words read: 0
[14:14:47.206] <TB1> INFO: valid events total: 0
[14:14:47.206] <TB1> INFO: empty events: 0
[14:14:47.206] <TB1> INFO: valid events with pixels: 0
[14:14:47.206] <TB1> INFO: valid pixel hits: 0
[14:14:47.206] <TB1> INFO: Event errors: 0
[14:14:47.206] <TB1> INFO: start marker: 0
[14:14:47.206] <TB1> INFO: stop marker: 0
[14:14:47.206] <TB1> INFO: overflow: 0
[14:14:47.206] <TB1> INFO: invalid 5bit words: 0
[14:14:47.206] <TB1> INFO: invalid XOR eye diagram: 0
[14:14:47.206] <TB1> INFO: frame (failed synchr.): 0
[14:14:47.206] <TB1> INFO: idle data (no TBM trl): 0
[14:14:47.206] <TB1> INFO: no data (only TBM hdr): 0
[14:14:47.206] <TB1> INFO: TBM errors: 0
[14:14:47.206] <TB1> INFO: flawed TBM headers: 0
[14:14:47.206] <TB1> INFO: flawed TBM trailers: 0
[14:14:47.206] <TB1> INFO: event ID mismatches: 0
[14:14:47.206] <TB1> INFO: ROC errors: 0
[14:14:47.206] <TB1> INFO: missing ROC header(s): 0
[14:14:47.206] <TB1> INFO: misplaced readback start: 0
[14:14:47.206] <TB1> INFO: Pixel decoding errors: 0
[14:14:47.206] <TB1> INFO: pixel data incomplete: 0
[14:14:47.206] <TB1> INFO: pixel address: 0
[14:14:47.206] <TB1> INFO: pulse height fill bit: 0
[14:14:47.206] <TB1> INFO: buffer corruption: 0
[14:14:47.274] <TB1> INFO: ######################################################################
[14:14:47.274] <TB1> INFO: PixTestTrim::doTest()
[14:14:47.274] <TB1> INFO: ######################################################################
[14:14:47.275] <TB1> INFO: ----------------------------------------------------------------------
[14:14:47.275] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[14:14:47.275] <TB1> INFO: ----------------------------------------------------------------------
[14:14:47.316] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:14:47.316] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:14:47.329] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:14:47.329] <TB1> INFO: run 1 of 1
[14:14:47.567] <TB1> INFO: Expecting 5025280 events.
[14:15:17.230] <TB1> INFO: 825760 events read in total (29065ms).
[14:15:46.063] <TB1> INFO: 1646904 events read in total (57898ms).
[14:16:17.750] <TB1> INFO: 2465488 events read in total (89585ms).
[14:16:46.595] <TB1> INFO: 3281608 events read in total (118430ms).
[14:17:15.464] <TB1> INFO: 4095040 events read in total (147300ms).
[14:17:44.330] <TB1> INFO: 4907896 events read in total (176165ms).
[14:17:48.805] <TB1> INFO: 5025280 events read in total (180640ms).
[14:17:48.870] <TB1> INFO: Test took 181540ms.
[14:18:04.654] <TB1> INFO: ROC 0 VthrComp = 113
[14:18:04.654] <TB1> INFO: ROC 1 VthrComp = 114
[14:18:04.654] <TB1> INFO: ROC 2 VthrComp = 124
[14:18:04.654] <TB1> INFO: ROC 3 VthrComp = 117
[14:18:04.654] <TB1> INFO: ROC 4 VthrComp = 122
[14:18:04.654] <TB1> INFO: ROC 5 VthrComp = 131
[14:18:04.655] <TB1> INFO: ROC 6 VthrComp = 115
[14:18:04.655] <TB1> INFO: ROC 7 VthrComp = 108
[14:18:04.655] <TB1> INFO: ROC 8 VthrComp = 119
[14:18:04.655] <TB1> INFO: ROC 9 VthrComp = 101
[14:18:04.655] <TB1> INFO: ROC 10 VthrComp = 126
[14:18:04.655] <TB1> INFO: ROC 11 VthrComp = 111
[14:18:04.656] <TB1> INFO: ROC 12 VthrComp = 117
[14:18:04.656] <TB1> INFO: ROC 13 VthrComp = 105
[14:18:04.656] <TB1> INFO: ROC 14 VthrComp = 113
[14:18:04.656] <TB1> INFO: ROC 15 VthrComp = 118
[14:18:04.891] <TB1> INFO: Expecting 41600 events.
[14:18:08.336] <TB1> INFO: 41600 events read in total (2853ms).
[14:18:08.337] <TB1> INFO: Test took 3680ms.
[14:18:08.346] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:18:08.346] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:18:08.358] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:18:08.358] <TB1> INFO: run 1 of 1
[14:18:08.636] <TB1> INFO: Expecting 5025280 events.
[14:18:34.092] <TB1> INFO: 592368 events read in total (24864ms).
[14:18:58.802] <TB1> INFO: 1183768 events read in total (49574ms).
[14:19:25.020] <TB1> INFO: 1775352 events read in total (75792ms).
[14:19:49.701] <TB1> INFO: 2365928 events read in total (100473ms).
[14:20:14.222] <TB1> INFO: 2954288 events read in total (124994ms).
[14:20:38.726] <TB1> INFO: 3541144 events read in total (149498ms).
[14:21:03.460] <TB1> INFO: 4126760 events read in total (174232ms).
[14:21:28.266] <TB1> INFO: 4711272 events read in total (199038ms).
[14:21:42.788] <TB1> INFO: 5025280 events read in total (213560ms).
[14:21:42.899] <TB1> INFO: Test took 214541ms.
[14:22:04.132] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 59.7502 for pixel 0/44 mean/min/max = 46.3363/32.8266/59.8459
[14:22:04.132] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 61.9896 for pixel 31/16 mean/min/max = 46.6967/31.3975/61.9958
[14:22:04.132] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 62.0515 for pixel 1/14 mean/min/max = 46.472/30.5118/62.4323
[14:22:04.133] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 59.6843 for pixel 21/2 mean/min/max = 46.0413/32.3178/59.7647
[14:22:04.133] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 61.859 for pixel 1/18 mean/min/max = 46.0355/30.1386/61.9324
[14:22:04.134] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 65.9231 for pixel 25/79 mean/min/max = 48.0558/30.0814/66.0301
[14:22:04.134] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 60.5953 for pixel 0/19 mean/min/max = 46.4/31.8714/60.9286
[14:22:04.134] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 64.6109 for pixel 16/71 mean/min/max = 49.3365/33.9632/64.7097
[14:22:04.135] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 61.7253 for pixel 9/4 mean/min/max = 46.2326/30.705/61.7603
[14:22:04.135] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 66.7364 for pixel 11/0 mean/min/max = 49.3771/31.8741/66.8802
[14:22:04.136] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 60.4887 for pixel 13/70 mean/min/max = 45.2472/29.4652/61.0292
[14:22:04.136] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 63.7535 for pixel 51/7 mean/min/max = 48.7721/33.7657/63.7786
[14:22:04.137] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 60.3699 for pixel 4/1 mean/min/max = 45.9203/31.3848/60.4558
[14:22:04.137] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 62.7303 for pixel 24/77 mean/min/max = 48.5502/34.3158/62.7846
[14:22:04.138] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 63.0105 for pixel 15/79 mean/min/max = 46.8672/30.6192/63.1151
[14:22:04.138] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 62.4517 for pixel 51/0 mean/min/max = 47.0668/31.5416/62.592
[14:22:04.139] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:22:04.228] <TB1> INFO: Expecting 411648 events.
[14:22:13.719] <TB1> INFO: 411648 events read in total (8899ms).
[14:22:13.725] <TB1> INFO: Expecting 411648 events.
[14:22:22.912] <TB1> INFO: 411648 events read in total (8783ms).
[14:22:22.923] <TB1> INFO: Expecting 411648 events.
[14:22:32.110] <TB1> INFO: 411648 events read in total (8784ms).
[14:22:32.124] <TB1> INFO: Expecting 411648 events.
[14:22:41.299] <TB1> INFO: 411648 events read in total (8772ms).
[14:22:41.314] <TB1> INFO: Expecting 411648 events.
[14:22:50.545] <TB1> INFO: 411648 events read in total (8827ms).
[14:22:50.564] <TB1> INFO: Expecting 411648 events.
[14:22:59.732] <TB1> INFO: 411648 events read in total (8765ms).
[14:22:59.754] <TB1> INFO: Expecting 411648 events.
[14:23:08.881] <TB1> INFO: 411648 events read in total (8724ms).
[14:23:08.904] <TB1> INFO: Expecting 411648 events.
[14:23:18.081] <TB1> INFO: 411648 events read in total (8774ms).
[14:23:18.108] <TB1> INFO: Expecting 411648 events.
[14:23:27.310] <TB1> INFO: 411648 events read in total (8799ms).
[14:23:27.341] <TB1> INFO: Expecting 411648 events.
[14:23:36.575] <TB1> INFO: 411648 events read in total (8831ms).
[14:23:36.607] <TB1> INFO: Expecting 411648 events.
[14:23:45.803] <TB1> INFO: 411648 events read in total (8793ms).
[14:23:45.838] <TB1> INFO: Expecting 411648 events.
[14:23:55.141] <TB1> INFO: 411648 events read in total (8900ms).
[14:23:55.179] <TB1> INFO: Expecting 411648 events.
[14:24:04.431] <TB1> INFO: 411648 events read in total (8849ms).
[14:24:04.471] <TB1> INFO: Expecting 411648 events.
[14:24:13.794] <TB1> INFO: 411648 events read in total (8920ms).
[14:24:13.846] <TB1> INFO: Expecting 411648 events.
[14:24:23.034] <TB1> INFO: 411648 events read in total (8784ms).
[14:24:23.081] <TB1> INFO: Expecting 411648 events.
[14:24:32.286] <TB1> INFO: 411648 events read in total (8802ms).
[14:24:32.368] <TB1> INFO: Test took 148229ms.
[14:24:33.050] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:24:33.063] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:24:33.063] <TB1> INFO: run 1 of 1
[14:24:33.302] <TB1> INFO: Expecting 5025280 events.
[14:24:59.183] <TB1> INFO: 590608 events read in total (25289ms).
[14:25:24.082] <TB1> INFO: 1180304 events read in total (50188ms).
[14:25:49.102] <TB1> INFO: 1770136 events read in total (75209ms).
[14:26:14.473] <TB1> INFO: 2357264 events read in total (100579ms).
[14:26:39.410] <TB1> INFO: 2944328 events read in total (125516ms).
[14:27:04.423] <TB1> INFO: 3535480 events read in total (150529ms).
[14:27:29.900] <TB1> INFO: 4126456 events read in total (176006ms).
[14:27:55.056] <TB1> INFO: 4716560 events read in total (201163ms).
[14:28:08.969] <TB1> INFO: 5025280 events read in total (215075ms).
[14:28:09.106] <TB1> INFO: Test took 216044ms.
[14:28:28.406] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 2.476387 .. 147.026957
[14:28:28.647] <TB1> INFO: Expecting 208000 events.
[14:28:37.994] <TB1> INFO: 208000 events read in total (8755ms).
[14:28:37.995] <TB1> INFO: Test took 9586ms.
[14:28:38.046] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 157 (-1/-1) hits flags = 528 (plus default)
[14:28:38.059] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:28:38.059] <TB1> INFO: run 1 of 1
[14:28:38.297] <TB1> INFO: Expecting 5191680 events.
[14:29:03.618] <TB1> INFO: 582688 events read in total (24729ms).
[14:29:29.660] <TB1> INFO: 1165144 events read in total (50771ms).
[14:29:54.452] <TB1> INFO: 1747736 events read in total (75563ms).
[14:30:19.255] <TB1> INFO: 2330552 events read in total (100367ms).
[14:30:44.476] <TB1> INFO: 2912904 events read in total (125587ms).
[14:31:09.302] <TB1> INFO: 3495040 events read in total (150413ms).
[14:31:34.077] <TB1> INFO: 4076776 events read in total (175188ms).
[14:31:58.965] <TB1> INFO: 4658816 events read in total (200076ms).
[14:32:21.605] <TB1> INFO: 5191680 events read in total (222716ms).
[14:32:21.737] <TB1> INFO: Test took 223678ms.
[14:32:43.664] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 26.535616 .. 46.200548
[14:32:43.902] <TB1> INFO: Expecting 208000 events.
[14:32:53.402] <TB1> INFO: 208000 events read in total (8908ms).
[14:32:53.403] <TB1> INFO: Test took 9736ms.
[14:32:53.452] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 56 (-1/-1) hits flags = 528 (plus default)
[14:32:53.466] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:32:53.466] <TB1> INFO: run 1 of 1
[14:32:53.707] <TB1> INFO: Expecting 1364480 events.
[14:33:20.991] <TB1> INFO: 657912 events read in total (26692ms).
[14:33:48.215] <TB1> INFO: 1313984 events read in total (53917ms).
[14:33:50.696] <TB1> INFO: 1364480 events read in total (56397ms).
[14:33:50.729] <TB1> INFO: Test took 57262ms.
[14:34:02.657] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 21.097446 .. 46.042299
[14:34:02.900] <TB1> INFO: Expecting 208000 events.
[14:34:12.404] <TB1> INFO: 208000 events read in total (8912ms).
[14:34:12.405] <TB1> INFO: Test took 9745ms.
[14:34:12.457] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 11 .. 56 (-1/-1) hits flags = 528 (plus default)
[14:34:12.470] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:34:12.470] <TB1> INFO: run 1 of 1
[14:34:12.708] <TB1> INFO: Expecting 1530880 events.
[14:34:41.279] <TB1> INFO: 677648 events read in total (27979ms).
[14:35:08.315] <TB1> INFO: 1354064 events read in total (55015ms).
[14:35:15.894] <TB1> INFO: 1530880 events read in total (62594ms).
[14:35:15.927] <TB1> INFO: Test took 63457ms.
[14:35:27.780] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 20.320020 .. 44.409217
[14:35:28.020] <TB1> INFO: Expecting 208000 events.
[14:35:37.520] <TB1> INFO: 208000 events read in total (8908ms).
[14:35:37.521] <TB1> INFO: Test took 9738ms.
[14:35:37.571] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 10 .. 54 (-1/-1) hits flags = 528 (plus default)
[14:35:37.585] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:35:37.585] <TB1> INFO: run 1 of 1
[14:35:37.824] <TB1> INFO: Expecting 1497600 events.
[14:36:05.684] <TB1> INFO: 690200 events read in total (27267ms).
[14:36:32.954] <TB1> INFO: 1379744 events read in total (54537ms).
[14:36:37.983] <TB1> INFO: 1497600 events read in total (59566ms).
[14:36:38.016] <TB1> INFO: Test took 60432ms.
[14:36:49.672] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:36:49.672] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:36:49.685] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:36:49.685] <TB1> INFO: run 1 of 1
[14:36:49.925] <TB1> INFO: Expecting 1364480 events.
[14:37:17.385] <TB1> INFO: 667080 events read in total (26868ms).
[14:37:45.668] <TB1> INFO: 1333600 events read in total (55151ms).
[14:37:47.343] <TB1> INFO: 1364480 events read in total (56827ms).
[14:37:47.372] <TB1> INFO: Test took 57688ms.
[14:37:59.021] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C0.dat
[14:37:59.022] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C1.dat
[14:37:59.022] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C2.dat
[14:37:59.022] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C3.dat
[14:37:59.022] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C4.dat
[14:37:59.022] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C5.dat
[14:37:59.022] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C6.dat
[14:37:59.022] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C7.dat
[14:37:59.022] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C8.dat
[14:37:59.023] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C9.dat
[14:37:59.023] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C10.dat
[14:37:59.023] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C11.dat
[14:37:59.023] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C12.dat
[14:37:59.023] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C13.dat
[14:37:59.023] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C14.dat
[14:37:59.023] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C15.dat
[14:37:59.024] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters35_C0.dat
[14:37:59.030] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters35_C1.dat
[14:37:59.035] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters35_C2.dat
[14:37:59.039] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters35_C3.dat
[14:37:59.044] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters35_C4.dat
[14:37:59.050] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters35_C5.dat
[14:37:59.054] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters35_C6.dat
[14:37:59.059] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters35_C7.dat
[14:37:59.064] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters35_C8.dat
[14:37:59.069] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters35_C9.dat
[14:37:59.074] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters35_C10.dat
[14:37:59.079] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters35_C11.dat
[14:37:59.083] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters35_C12.dat
[14:37:59.088] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters35_C13.dat
[14:37:59.093] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters35_C14.dat
[14:37:59.098] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//trimParameters35_C15.dat
[14:37:59.103] <TB1> INFO: PixTestTrim::trimTest() done
[14:37:59.103] <TB1> INFO: vtrim: 115 139 134 110 136 141 104 135 143 131 116 120 167 129 119 129
[14:37:59.103] <TB1> INFO: vthrcomp: 113 114 124 117 122 131 115 108 119 101 126 111 117 105 113 118
[14:37:59.103] <TB1> INFO: vcal mean: 35.04 34.93 34.91 34.96 34.95 34.96 34.98 35.03 35.01 35.11 34.95 35.03 34.95 35.00 34.97 34.93
[14:37:59.103] <TB1> INFO: vcal RMS: 1.03 1.14 1.25 1.01 1.15 1.21 1.08 1.07 1.12 1.33 1.32 1.08 1.11 1.05 1.17 1.18
[14:37:59.103] <TB1> INFO: bits mean: 8.94 9.27 9.70 9.25 9.61 9.23 9.06 8.48 9.90 9.35 9.97 8.37 9.72 8.92 9.81 9.35
[14:37:59.103] <TB1> INFO: bits RMS: 2.86 2.85 2.74 2.77 2.82 2.85 2.91 2.66 2.67 2.56 2.74 2.76 2.73 2.46 2.63 2.81
[14:37:59.111] <TB1> INFO: ----------------------------------------------------------------------
[14:37:59.111] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:37:59.111] <TB1> INFO: ----------------------------------------------------------------------
[14:37:59.114] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:37:59.127] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:37:59.127] <TB1> INFO: run 1 of 1
[14:37:59.366] <TB1> INFO: Expecting 4160000 events.
[14:38:30.622] <TB1> INFO: 751005 events read in total (30664ms).
[14:39:01.449] <TB1> INFO: 1496985 events read in total (61491ms).
[14:39:32.044] <TB1> INFO: 2240885 events read in total (92086ms).
[14:40:02.641] <TB1> INFO: 2981005 events read in total (122683ms).
[14:40:33.205] <TB1> INFO: 3718025 events read in total (153247ms).
[14:40:51.567] <TB1> INFO: 4160000 events read in total (171609ms).
[14:40:51.659] <TB1> INFO: Test took 172532ms.
[14:41:14.143] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 223 (-1/-1) hits flags = 528 (plus default)
[14:41:14.155] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:41:14.155] <TB1> INFO: run 1 of 1
[14:41:14.395] <TB1> INFO: Expecting 4659200 events.
[14:41:44.617] <TB1> INFO: 700850 events read in total (29630ms).
[14:42:14.887] <TB1> INFO: 1398640 events read in total (59900ms).
[14:42:44.435] <TB1> INFO: 2093910 events read in total (89448ms).
[14:43:13.977] <TB1> INFO: 2787555 events read in total (118990ms).
[14:43:43.220] <TB1> INFO: 3478550 events read in total (148233ms).
[14:44:12.694] <TB1> INFO: 4168210 events read in total (177707ms).
[14:44:34.234] <TB1> INFO: 4659200 events read in total (199247ms).
[14:44:34.327] <TB1> INFO: Test took 200171ms.
[14:44:59.686] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[14:44:59.699] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:44:59.699] <TB1> INFO: run 1 of 1
[14:44:59.937] <TB1> INFO: Expecting 4430400 events.
[14:45:30.616] <TB1> INFO: 712475 events read in total (30087ms).
[14:46:00.327] <TB1> INFO: 1421740 events read in total (59798ms).
[14:46:30.350] <TB1> INFO: 2128455 events read in total (89821ms).
[14:47:00.225] <TB1> INFO: 2832725 events read in total (119696ms).
[14:47:29.921] <TB1> INFO: 3534200 events read in total (149392ms).
[14:48:00.051] <TB1> INFO: 4235340 events read in total (179522ms).
[14:48:08.528] <TB1> INFO: 4430400 events read in total (187999ms).
[14:48:08.610] <TB1> INFO: Test took 188911ms.
[14:48:33.125] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[14:48:33.138] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:48:33.138] <TB1> INFO: run 1 of 1
[14:48:33.377] <TB1> INFO: Expecting 4430400 events.
[14:49:03.872] <TB1> INFO: 713075 events read in total (29903ms).
[14:49:33.784] <TB1> INFO: 1422630 events read in total (59815ms).
[14:50:04.321] <TB1> INFO: 2129625 events read in total (90352ms).
[14:50:35.531] <TB1> INFO: 2834160 events read in total (121562ms).
[14:51:05.253] <TB1> INFO: 3535865 events read in total (151284ms).
[14:51:35.094] <TB1> INFO: 4237595 events read in total (181125ms).
[14:51:43.500] <TB1> INFO: 4430400 events read in total (189531ms).
[14:51:43.608] <TB1> INFO: Test took 190470ms.
[14:52:08.199] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 211 (-1/-1) hits flags = 528 (plus default)
[14:52:08.213] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:52:08.213] <TB1> INFO: run 1 of 1
[14:52:08.455] <TB1> INFO: Expecting 4409600 events.
[14:52:39.874] <TB1> INFO: 714205 events read in total (30828ms).
[14:53:09.727] <TB1> INFO: 1425055 events read in total (60681ms).
[14:53:39.533] <TB1> INFO: 2133350 events read in total (90487ms).
[14:54:09.342] <TB1> INFO: 2838880 events read in total (120296ms).
[14:54:39.106] <TB1> INFO: 3541910 events read in total (150060ms).
[14:55:08.888] <TB1> INFO: 4244510 events read in total (179842ms).
[14:55:16.159] <TB1> INFO: 4409600 events read in total (187113ms).
[14:55:16.241] <TB1> INFO: Test took 188028ms.
[14:55:40.790] <TB1> INFO: PixTestTrim::trimBitTest() done
[14:55:40.791] <TB1> INFO: PixTestTrim::doTest() done, duration: 2453 seconds
[14:55:40.791] <TB1> INFO: Decoding statistics:
[14:55:40.791] <TB1> INFO: General information:
[14:55:40.791] <TB1> INFO: 16bit words read: 0
[14:55:40.791] <TB1> INFO: valid events total: 0
[14:55:40.791] <TB1> INFO: empty events: 0
[14:55:40.791] <TB1> INFO: valid events with pixels: 0
[14:55:40.791] <TB1> INFO: valid pixel hits: 0
[14:55:40.791] <TB1> INFO: Event errors: 0
[14:55:40.791] <TB1> INFO: start marker: 0
[14:55:40.791] <TB1> INFO: stop marker: 0
[14:55:40.791] <TB1> INFO: overflow: 0
[14:55:40.791] <TB1> INFO: invalid 5bit words: 0
[14:55:40.791] <TB1> INFO: invalid XOR eye diagram: 0
[14:55:40.791] <TB1> INFO: frame (failed synchr.): 0
[14:55:40.791] <TB1> INFO: idle data (no TBM trl): 0
[14:55:40.791] <TB1> INFO: no data (only TBM hdr): 0
[14:55:40.791] <TB1> INFO: TBM errors: 0
[14:55:40.791] <TB1> INFO: flawed TBM headers: 0
[14:55:40.791] <TB1> INFO: flawed TBM trailers: 0
[14:55:40.791] <TB1> INFO: event ID mismatches: 0
[14:55:40.791] <TB1> INFO: ROC errors: 0
[14:55:40.791] <TB1> INFO: missing ROC header(s): 0
[14:55:40.791] <TB1> INFO: misplaced readback start: 0
[14:55:40.791] <TB1> INFO: Pixel decoding errors: 0
[14:55:40.791] <TB1> INFO: pixel data incomplete: 0
[14:55:40.791] <TB1> INFO: pixel address: 0
[14:55:40.791] <TB1> INFO: pulse height fill bit: 0
[14:55:40.791] <TB1> INFO: buffer corruption: 0
[14:55:41.406] <TB1> INFO: ######################################################################
[14:55:41.406] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[14:55:41.406] <TB1> INFO: ######################################################################
[14:55:41.649] <TB1> INFO: Expecting 41600 events.
[14:55:45.093] <TB1> INFO: 41600 events read in total (2852ms).
[14:55:45.093] <TB1> INFO: Test took 3687ms.
[14:55:45.534] <TB1> INFO: Expecting 41600 events.
[14:55:49.023] <TB1> INFO: 41600 events read in total (2897ms).
[14:55:49.024] <TB1> INFO: Test took 3727ms.
[14:55:49.312] <TB1> INFO: Expecting 41600 events.
[14:55:52.823] <TB1> INFO: 41600 events read in total (2919ms).
[14:55:52.824] <TB1> INFO: Test took 3790ms.
[14:55:53.113] <TB1> INFO: Expecting 41600 events.
[14:55:56.596] <TB1> INFO: 41600 events read in total (2891ms).
[14:55:56.597] <TB1> INFO: Test took 3763ms.
[14:55:56.885] <TB1> INFO: Expecting 41600 events.
[14:56:00.380] <TB1> INFO: 41600 events read in total (2904ms).
[14:56:00.381] <TB1> INFO: Test took 3774ms.
[14:56:00.670] <TB1> INFO: Expecting 41600 events.
[14:56:04.150] <TB1> INFO: 41600 events read in total (2888ms).
[14:56:04.151] <TB1> INFO: Test took 3759ms.
[14:56:04.439] <TB1> INFO: Expecting 41600 events.
[14:56:07.918] <TB1> INFO: 41600 events read in total (2887ms).
[14:56:07.920] <TB1> INFO: Test took 3758ms.
[14:56:08.209] <TB1> INFO: Expecting 41600 events.
[14:56:11.697] <TB1> INFO: 41600 events read in total (2896ms).
[14:56:11.698] <TB1> INFO: Test took 3768ms.
[14:56:11.986] <TB1> INFO: Expecting 41600 events.
[14:56:15.471] <TB1> INFO: 41600 events read in total (2893ms).
[14:56:15.472] <TB1> INFO: Test took 3764ms.
[14:56:15.760] <TB1> INFO: Expecting 41600 events.
[14:56:19.245] <TB1> INFO: 41600 events read in total (2893ms).
[14:56:19.246] <TB1> INFO: Test took 3764ms.
[14:56:19.536] <TB1> INFO: Expecting 41600 events.
[14:56:23.027] <TB1> INFO: 41600 events read in total (2900ms).
[14:56:23.028] <TB1> INFO: Test took 3771ms.
[14:56:23.316] <TB1> INFO: Expecting 41600 events.
[14:56:26.823] <TB1> INFO: 41600 events read in total (2915ms).
[14:56:26.824] <TB1> INFO: Test took 3786ms.
[14:56:27.113] <TB1> INFO: Expecting 41600 events.
[14:56:30.589] <TB1> INFO: 41600 events read in total (2884ms).
[14:56:30.590] <TB1> INFO: Test took 3755ms.
[14:56:30.879] <TB1> INFO: Expecting 41600 events.
[14:56:34.362] <TB1> INFO: 41600 events read in total (2891ms).
[14:56:34.363] <TB1> INFO: Test took 3762ms.
[14:56:34.651] <TB1> INFO: Expecting 41600 events.
[14:56:38.134] <TB1> INFO: 41600 events read in total (2891ms).
[14:56:38.135] <TB1> INFO: Test took 3762ms.
[14:56:38.424] <TB1> INFO: Expecting 41600 events.
[14:56:41.919] <TB1> INFO: 41600 events read in total (2903ms).
[14:56:41.920] <TB1> INFO: Test took 3774ms.
[14:56:42.208] <TB1> INFO: Expecting 41600 events.
[14:56:45.694] <TB1> INFO: 41600 events read in total (2894ms).
[14:56:45.695] <TB1> INFO: Test took 3765ms.
[14:56:45.984] <TB1> INFO: Expecting 41600 events.
[14:56:49.468] <TB1> INFO: 41600 events read in total (2892ms).
[14:56:49.469] <TB1> INFO: Test took 3764ms.
[14:56:49.757] <TB1> INFO: Expecting 41600 events.
[14:56:53.248] <TB1> INFO: 41600 events read in total (2900ms).
[14:56:53.249] <TB1> INFO: Test took 3770ms.
[14:56:53.539] <TB1> INFO: Expecting 41600 events.
[14:56:57.017] <TB1> INFO: 41600 events read in total (2886ms).
[14:56:57.017] <TB1> INFO: Test took 3757ms.
[14:56:57.306] <TB1> INFO: Expecting 41600 events.
[14:57:00.800] <TB1> INFO: 41600 events read in total (2902ms).
[14:57:00.801] <TB1> INFO: Test took 3773ms.
[14:57:01.090] <TB1> INFO: Expecting 41600 events.
[14:57:04.565] <TB1> INFO: 41600 events read in total (2883ms).
[14:57:04.566] <TB1> INFO: Test took 3754ms.
[14:57:04.854] <TB1> INFO: Expecting 41600 events.
[14:57:08.336] <TB1> INFO: 41600 events read in total (2890ms).
[14:57:08.337] <TB1> INFO: Test took 3761ms.
[14:57:08.626] <TB1> INFO: Expecting 41600 events.
[14:57:12.124] <TB1> INFO: 41600 events read in total (2906ms).
[14:57:12.125] <TB1> INFO: Test took 3778ms.
[14:57:12.413] <TB1> INFO: Expecting 41600 events.
[14:57:15.896] <TB1> INFO: 41600 events read in total (2891ms).
[14:57:15.897] <TB1> INFO: Test took 3762ms.
[14:57:16.185] <TB1> INFO: Expecting 41600 events.
[14:57:19.671] <TB1> INFO: 41600 events read in total (2895ms).
[14:57:19.672] <TB1> INFO: Test took 3765ms.
[14:57:19.961] <TB1> INFO: Expecting 41600 events.
[14:57:23.451] <TB1> INFO: 41600 events read in total (2898ms).
[14:57:23.452] <TB1> INFO: Test took 3769ms.
[14:57:23.740] <TB1> INFO: Expecting 41600 events.
[14:57:27.223] <TB1> INFO: 41600 events read in total (2891ms).
[14:57:27.224] <TB1> INFO: Test took 3762ms.
[14:57:27.512] <TB1> INFO: Expecting 41600 events.
[14:57:30.995] <TB1> INFO: 41600 events read in total (2891ms).
[14:57:30.995] <TB1> INFO: Test took 3762ms.
[14:57:31.284] <TB1> INFO: Expecting 41600 events.
[14:57:34.761] <TB1> INFO: 41600 events read in total (2885ms).
[14:57:34.762] <TB1> INFO: Test took 3757ms.
[14:57:35.050] <TB1> INFO: Expecting 41600 events.
[14:57:38.534] <TB1> INFO: 41600 events read in total (2892ms).
[14:57:38.535] <TB1> INFO: Test took 3763ms.
[14:57:38.824] <TB1> INFO: Expecting 41600 events.
[14:57:42.321] <TB1> INFO: 41600 events read in total (2905ms).
[14:57:42.323] <TB1> INFO: Test took 3777ms.
[14:57:42.611] <TB1> INFO: Expecting 41600 events.
[14:57:46.093] <TB1> INFO: 41600 events read in total (2890ms).
[14:57:46.094] <TB1> INFO: Test took 3761ms.
[14:57:46.383] <TB1> INFO: Expecting 41600 events.
[14:57:49.867] <TB1> INFO: 41600 events read in total (2892ms).
[14:57:49.868] <TB1> INFO: Test took 3763ms.
[14:57:50.157] <TB1> INFO: Expecting 41600 events.
[14:57:53.638] <TB1> INFO: 41600 events read in total (2889ms).
[14:57:53.639] <TB1> INFO: Test took 3761ms.
[14:57:53.927] <TB1> INFO: Expecting 41600 events.
[14:57:57.409] <TB1> INFO: 41600 events read in total (2890ms).
[14:57:57.410] <TB1> INFO: Test took 3761ms.
[14:57:57.698] <TB1> INFO: Expecting 41600 events.
[14:58:01.189] <TB1> INFO: 41600 events read in total (2899ms).
[14:58:01.190] <TB1> INFO: Test took 3770ms.
[14:58:01.479] <TB1> INFO: Expecting 41600 events.
[14:58:04.957] <TB1> INFO: 41600 events read in total (2886ms).
[14:58:04.958] <TB1> INFO: Test took 3757ms.
[14:58:05.246] <TB1> INFO: Expecting 41600 events.
[14:58:08.723] <TB1> INFO: 41600 events read in total (2884ms).
[14:58:08.724] <TB1> INFO: Test took 3756ms.
[14:58:09.013] <TB1> INFO: Expecting 41600 events.
[14:58:12.521] <TB1> INFO: 41600 events read in total (2916ms).
[14:58:12.522] <TB1> INFO: Test took 3787ms.
[14:58:12.811] <TB1> INFO: Expecting 41600 events.
[14:58:16.295] <TB1> INFO: 41600 events read in total (2893ms).
[14:58:16.296] <TB1> INFO: Test took 3763ms.
[14:58:16.585] <TB1> INFO: Expecting 41600 events.
[14:58:20.068] <TB1> INFO: 41600 events read in total (2891ms).
[14:58:20.069] <TB1> INFO: Test took 3762ms.
[14:58:20.357] <TB1> INFO: Expecting 41600 events.
[14:58:23.833] <TB1> INFO: 41600 events read in total (2884ms).
[14:58:23.834] <TB1> INFO: Test took 3755ms.
[14:58:24.123] <TB1> INFO: Expecting 41600 events.
[14:58:27.607] <TB1> INFO: 41600 events read in total (2892ms).
[14:58:27.608] <TB1> INFO: Test took 3763ms.
[14:58:27.897] <TB1> INFO: Expecting 41600 events.
[14:58:31.375] <TB1> INFO: 41600 events read in total (2886ms).
[14:58:31.376] <TB1> INFO: Test took 3757ms.
[14:58:31.665] <TB1> INFO: Expecting 41600 events.
[14:58:35.141] <TB1> INFO: 41600 events read in total (2884ms).
[14:58:35.142] <TB1> INFO: Test took 3755ms.
[14:58:35.430] <TB1> INFO: Expecting 41600 events.
[14:58:38.908] <TB1> INFO: 41600 events read in total (2886ms).
[14:58:38.909] <TB1> INFO: Test took 3757ms.
[14:58:39.198] <TB1> INFO: Expecting 41600 events.
[14:58:42.697] <TB1> INFO: 41600 events read in total (2907ms).
[14:58:42.698] <TB1> INFO: Test took 3778ms.
[14:58:42.987] <TB1> INFO: Expecting 41600 events.
[14:58:46.481] <TB1> INFO: 41600 events read in total (2902ms).
[14:58:46.482] <TB1> INFO: Test took 3773ms.
[14:58:46.771] <TB1> INFO: Expecting 41600 events.
[14:58:50.253] <TB1> INFO: 41600 events read in total (2890ms).
[14:58:50.254] <TB1> INFO: Test took 3761ms.
[14:58:50.543] <TB1> INFO: Expecting 41600 events.
[14:58:54.020] <TB1> INFO: 41600 events read in total (2885ms).
[14:58:54.020] <TB1> INFO: Test took 3755ms.
[14:58:54.309] <TB1> INFO: Expecting 41600 events.
[14:58:57.778] <TB1> INFO: 41600 events read in total (2878ms).
[14:58:57.779] <TB1> INFO: Test took 3749ms.
[14:58:58.067] <TB1> INFO: Expecting 41600 events.
[14:59:01.545] <TB1> INFO: 41600 events read in total (2886ms).
[14:59:01.546] <TB1> INFO: Test took 3757ms.
[14:59:01.559] <TB1> INFO: Max pixel from chip 0 is [13 ,8] phvalue 139
[14:59:01.559] <TB1> INFO: Max pixel from chip 1 is [4 ,14] phvalue 26
[14:59:01.559] <TB1> INFO: Max pixel from chip 2 is [4 ,9] phvalue 91
[14:59:01.559] <TB1> INFO: Max pixel from chip 3 is [8 ,6] phvalue 146
[14:59:01.559] <TB1> INFO: Max pixel from chip 4 is [14 ,62] phvalue 233
[14:59:01.560] <TB1> INFO: Max pixel from chip 5 is [8 ,7] phvalue 94
[14:59:01.560] <TB1> INFO: Max pixel from chip 6 is [5 ,18] phvalue 127
[14:59:01.560] <TB1> INFO: Max pixel from chip 7 is [10 ,7] phvalue 98
[14:59:01.560] <TB1> INFO: Max pixel from chip 8 is [4 ,11] phvalue 109
[14:59:01.560] <TB1> INFO: Max pixel from chip 9 is [14 ,5] phvalue 68
[14:59:01.561] <TB1> INFO: Max pixel from chip 10 is [10 ,56] phvalue 132
[14:59:01.561] <TB1> INFO: Max pixel from chip 11 is [4 ,15] phvalue 62
[14:59:01.561] <TB1> INFO: Max pixel from chip 12 is [14 ,29] phvalue 94
[14:59:01.561] <TB1> INFO: Max pixel from chip 13 is [11 ,7] phvalue 134
[14:59:01.562] <TB1> INFO: Max pixel from chip 14 is [22 ,19] phvalue 83
[14:59:01.562] <TB1> INFO: Max pixel from chip 15 is [4 ,16] phvalue 222
[14:59:01.842] <TB1> INFO: Expecting 41600 events.
[14:59:05.322] <TB1> INFO: 41600 events read in total (2888ms).
[14:59:05.323] <TB1> INFO: Test took 3747ms.
[14:59:05.334] <TB1> INFO: Min pixel from chip 0 is [3 ,5] phvalue 255
[14:59:05.334] <TB1> INFO: Min pixel from chip 1 is [28 ,60] phvalue 232
[14:59:05.334] <TB1> INFO: Search for minph pixel failed in the fiducial region for chip 2, looking at the edges
[14:59:05.334] <TB1> INFO: min ph pixel determination failed on roc 2, setting pixel 0,0
[14:59:05.335] <TB1> INFO: Min pixel from chip 3 is [3 ,5] phvalue 255
[14:59:05.335] <TB1> INFO: Min pixel from chip 4 is [3 ,5] phvalue 255
[14:59:05.335] <TB1> INFO: Min pixel from chip 5 is [33 ,74] phvalue 250
[14:59:05.335] <TB1> INFO: Min pixel from chip 6 is [3 ,5] phvalue 255
[14:59:05.335] <TB1> INFO: Min pixel from chip 7 is [3 ,5] phvalue 255
[14:59:05.335] <TB1> INFO: Min pixel from chip 8 is [19 ,22] phvalue 246
[14:59:05.336] <TB1> INFO: Search for minph pixel failed in the fiducial region for chip 9, looking at the edges
[14:59:05.336] <TB1> INFO: min ph pixel determination failed on roc 9, setting pixel 0,0
[14:59:05.336] <TB1> INFO: Min pixel from chip 10 is [3 ,5] phvalue 255
[14:59:05.336] <TB1> INFO: Min pixel from chip 11 is [29 ,23] phvalue 241
[14:59:05.336] <TB1> INFO: Min pixel from chip 12 is [9 ,51] phvalue 249
[14:59:05.336] <TB1> INFO: Min pixel from chip 13 is [3 ,5] phvalue 255
[14:59:05.337] <TB1> INFO: Min pixel from chip 14 is [4 ,63] phvalue 245
[14:59:05.337] <TB1> INFO: Min pixel from chip 15 is [3 ,5] phvalue 255
[14:59:05.615] <TB1> INFO: Expecting 2560 events.
[14:59:06.500] <TB1> INFO: 2560 events read in total (293ms).
[14:59:06.501] <TB1> INFO: Test took 1163ms.
[14:59:06.809] <TB1> INFO: Expecting 2560 events.
[14:59:07.694] <TB1> INFO: 2560 events read in total (293ms).
[14:59:07.694] <TB1> INFO: Test took 1193ms.
[14:59:08.003] <TB1> INFO: Expecting 2560 events.
[14:59:08.887] <TB1> INFO: 2560 events read in total (292ms).
[14:59:08.887] <TB1> INFO: Test took 1193ms.
[14:59:09.196] <TB1> INFO: Expecting 2560 events.
[14:59:10.080] <TB1> INFO: 2560 events read in total (292ms).
[14:59:10.081] <TB1> INFO: Test took 1193ms.
[14:59:10.389] <TB1> INFO: Expecting 2560 events.
[14:59:11.269] <TB1> INFO: 2560 events read in total (288ms).
[14:59:11.270] <TB1> INFO: Test took 1189ms.
[14:59:11.578] <TB1> INFO: Expecting 2560 events.
[14:59:12.459] <TB1> INFO: 2560 events read in total (289ms).
[14:59:12.459] <TB1> INFO: Test took 1189ms.
[14:59:12.767] <TB1> INFO: Expecting 2560 events.
[14:59:13.653] <TB1> INFO: 2560 events read in total (294ms).
[14:59:13.653] <TB1> INFO: Test took 1193ms.
[14:59:13.962] <TB1> INFO: Expecting 2560 events.
[14:59:14.842] <TB1> INFO: 2560 events read in total (288ms).
[14:59:14.842] <TB1> INFO: Test took 1188ms.
[14:59:15.151] <TB1> INFO: Expecting 2560 events.
[14:59:16.031] <TB1> INFO: 2560 events read in total (288ms).
[14:59:16.031] <TB1> INFO: Test took 1188ms.
[14:59:16.340] <TB1> INFO: Expecting 2560 events.
[14:59:17.220] <TB1> INFO: 2560 events read in total (288ms).
[14:59:17.221] <TB1> INFO: Test took 1190ms.
[14:59:17.529] <TB1> INFO: Expecting 2560 events.
[14:59:18.409] <TB1> INFO: 2560 events read in total (288ms).
[14:59:18.409] <TB1> INFO: Test took 1188ms.
[14:59:18.718] <TB1> INFO: Expecting 2560 events.
[14:59:19.598] <TB1> INFO: 2560 events read in total (288ms).
[14:59:19.598] <TB1> INFO: Test took 1188ms.
[14:59:19.907] <TB1> INFO: Expecting 2560 events.
[14:59:20.792] <TB1> INFO: 2560 events read in total (293ms).
[14:59:20.792] <TB1> INFO: Test took 1193ms.
[14:59:21.100] <TB1> INFO: Expecting 2560 events.
[14:59:21.985] <TB1> INFO: 2560 events read in total (293ms).
[14:59:21.985] <TB1> INFO: Test took 1193ms.
[14:59:22.294] <TB1> INFO: Expecting 2560 events.
[14:59:23.178] <TB1> INFO: 2560 events read in total (292ms).
[14:59:23.178] <TB1> INFO: Test took 1193ms.
[14:59:23.487] <TB1> INFO: Expecting 2560 events.
[14:59:24.372] <TB1> INFO: 2560 events read in total (293ms).
[14:59:24.372] <TB1> INFO: Test took 1193ms.
[14:59:24.375] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:59:24.682] <TB1> INFO: Expecting 655360 events.
[14:59:39.184] <TB1> INFO: 655360 events read in total (13910ms).
[14:59:39.197] <TB1> INFO: Expecting 655360 events.
[14:59:53.483] <TB1> INFO: 655360 events read in total (13883ms).
[14:59:53.500] <TB1> INFO: Expecting 655360 events.
[15:00:07.874] <TB1> INFO: 655360 events read in total (13971ms).
[15:00:07.895] <TB1> INFO: Expecting 655360 events.
[15:00:22.187] <TB1> INFO: 655360 events read in total (13888ms).
[15:00:22.215] <TB1> INFO: Expecting 655360 events.
[15:00:36.550] <TB1> INFO: 655360 events read in total (13931ms).
[15:00:36.580] <TB1> INFO: Expecting 655360 events.
[15:00:50.832] <TB1> INFO: 655360 events read in total (13849ms).
[15:00:50.867] <TB1> INFO: Expecting 655360 events.
[15:01:05.109] <TB1> INFO: 655360 events read in total (13839ms).
[15:01:05.147] <TB1> INFO: Expecting 655360 events.
[15:01:19.465] <TB1> INFO: 655360 events read in total (13915ms).
[15:01:19.512] <TB1> INFO: Expecting 655360 events.
[15:01:33.796] <TB1> INFO: 655360 events read in total (13881ms).
[15:01:33.845] <TB1> INFO: Expecting 655360 events.
[15:01:48.166] <TB1> INFO: 655360 events read in total (13918ms).
[15:01:48.230] <TB1> INFO: Expecting 655360 events.
[15:02:02.537] <TB1> INFO: 655360 events read in total (13904ms).
[15:02:02.608] <TB1> INFO: Expecting 655360 events.
[15:02:16.908] <TB1> INFO: 655360 events read in total (13896ms).
[15:02:16.983] <TB1> INFO: Expecting 655360 events.
[15:02:31.276] <TB1> INFO: 655360 events read in total (13890ms).
[15:02:31.371] <TB1> INFO: Expecting 655360 events.
[15:02:45.662] <TB1> INFO: 655360 events read in total (13887ms).
[15:02:45.763] <TB1> INFO: Expecting 655360 events.
[15:03:00.061] <TB1> INFO: 655360 events read in total (13894ms).
[15:03:00.153] <TB1> INFO: Expecting 655360 events.
[15:03:14.489] <TB1> INFO: 655360 events read in total (13932ms).
[15:03:14.588] <TB1> INFO: Test took 230213ms.
[15:03:14.684] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:03:14.942] <TB1> INFO: Expecting 655360 events.
[15:03:29.401] <TB1> INFO: 655360 events read in total (13867ms).
[15:03:29.415] <TB1> INFO: Expecting 655360 events.
[15:03:43.678] <TB1> INFO: 655360 events read in total (13860ms).
[15:03:43.695] <TB1> INFO: Expecting 655360 events.
[15:03:57.904] <TB1> INFO: 655360 events read in total (13806ms).
[15:03:57.925] <TB1> INFO: Expecting 655360 events.
[15:04:12.212] <TB1> INFO: 655360 events read in total (13884ms).
[15:04:12.238] <TB1> INFO: Expecting 655360 events.
[15:04:26.255] <TB1> INFO: 655360 events read in total (13613ms).
[15:04:26.285] <TB1> INFO: Expecting 655360 events.
[15:04:40.482] <TB1> INFO: 655360 events read in total (13794ms).
[15:04:40.519] <TB1> INFO: Expecting 655360 events.
[15:04:54.812] <TB1> INFO: 655360 events read in total (13890ms).
[15:04:54.850] <TB1> INFO: Expecting 655360 events.
[15:05:09.083] <TB1> INFO: 655360 events read in total (13829ms).
[15:05:09.128] <TB1> INFO: Expecting 655360 events.
[15:05:23.501] <TB1> INFO: 655360 events read in total (13970ms).
[15:05:23.547] <TB1> INFO: Expecting 655360 events.
[15:05:37.564] <TB1> INFO: 655360 events read in total (13614ms).
[15:05:37.627] <TB1> INFO: Expecting 655360 events.
[15:05:51.683] <TB1> INFO: 655360 events read in total (13653ms).
[15:05:51.754] <TB1> INFO: Expecting 655360 events.
[15:06:05.795] <TB1> INFO: 655360 events read in total (13637ms).
[15:06:05.888] <TB1> INFO: Expecting 655360 events.
[15:06:19.910] <TB1> INFO: 655360 events read in total (13619ms).
[15:06:19.001] <TB1> INFO: Expecting 655360 events.
[15:06:34.153] <TB1> INFO: 655360 events read in total (13749ms).
[15:06:34.240] <TB1> INFO: Expecting 655360 events.
[15:06:48.383] <TB1> INFO: 655360 events read in total (13740ms).
[15:06:48.478] <TB1> INFO: Expecting 655360 events.
[15:07:02.763] <TB1> INFO: 655360 events read in total (13881ms).
[15:07:02.861] <TB1> INFO: Test took 228177ms.
[15:07:03.034] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:07:03.041] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:07:03.047] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:07:03.053] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:07:03.059] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:07:03.065] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:07:03.072] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:07:03.078] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:07:03.084] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:07:03.090] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:07:03.096] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:07:03.102] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[15:07:03.108] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[15:07:03.115] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[15:07:03.120] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[15:07:03.126] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:07:03.133] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:07:03.139] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:07:03.145] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:07:03.151] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:07:03.157] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[15:07:03.163] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:07:03.169] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:07:03.175] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:07:03.181] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:07:03.189] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[15:07:03.195] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[15:07:03.201] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[15:07:03.209] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[15:07:03.215] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[15:07:03.222] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[15:07:03.229] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[15:07:03.235] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[15:07:03.243] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[15:07:03.249] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:07:03.256] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[15:07:03.291] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C0.dat
[15:07:03.291] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C1.dat
[15:07:03.291] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C2.dat
[15:07:03.291] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C3.dat
[15:07:03.291] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C4.dat
[15:07:03.291] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C5.dat
[15:07:03.291] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C6.dat
[15:07:03.291] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C7.dat
[15:07:03.292] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C8.dat
[15:07:03.292] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C9.dat
[15:07:03.292] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C10.dat
[15:07:03.292] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C11.dat
[15:07:03.292] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C12.dat
[15:07:03.292] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C13.dat
[15:07:03.292] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C14.dat
[15:07:03.292] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//dacParameters35_C15.dat
[15:07:03.534] <TB1> INFO: Expecting 41600 events.
[15:07:06.655] <TB1> INFO: 41600 events read in total (2529ms).
[15:07:06.656] <TB1> INFO: Test took 3361ms.
[15:07:07.106] <TB1> INFO: Expecting 41600 events.
[15:07:10.117] <TB1> INFO: 41600 events read in total (2419ms).
[15:07:10.118] <TB1> INFO: Test took 3251ms.
[15:07:10.567] <TB1> INFO: Expecting 41600 events.
[15:07:13.688] <TB1> INFO: 41600 events read in total (2529ms).
[15:07:13.689] <TB1> INFO: Test took 3360ms.
[15:07:13.904] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:13.993] <TB1> INFO: Expecting 2560 events.
[15:07:14.877] <TB1> INFO: 2560 events read in total (292ms).
[15:07:14.878] <TB1> INFO: Test took 974ms.
[15:07:14.881] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:15.187] <TB1> INFO: Expecting 2560 events.
[15:07:16.072] <TB1> INFO: 2560 events read in total (293ms).
[15:07:16.072] <TB1> INFO: Test took 1191ms.
[15:07:16.075] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:16.381] <TB1> INFO: Expecting 2560 events.
[15:07:17.266] <TB1> INFO: 2560 events read in total (293ms).
[15:07:17.266] <TB1> INFO: Test took 1191ms.
[15:07:17.268] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:17.575] <TB1> INFO: Expecting 2560 events.
[15:07:18.459] <TB1> INFO: 2560 events read in total (292ms).
[15:07:18.460] <TB1> INFO: Test took 1192ms.
[15:07:18.462] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:18.769] <TB1> INFO: Expecting 2560 events.
[15:07:19.654] <TB1> INFO: 2560 events read in total (293ms).
[15:07:19.654] <TB1> INFO: Test took 1192ms.
[15:07:19.658] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:19.963] <TB1> INFO: Expecting 2560 events.
[15:07:20.848] <TB1> INFO: 2560 events read in total (293ms).
[15:07:20.848] <TB1> INFO: Test took 1190ms.
[15:07:20.851] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:21.157] <TB1> INFO: Expecting 2560 events.
[15:07:22.042] <TB1> INFO: 2560 events read in total (293ms).
[15:07:22.043] <TB1> INFO: Test took 1192ms.
[15:07:22.045] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:22.351] <TB1> INFO: Expecting 2560 events.
[15:07:23.236] <TB1> INFO: 2560 events read in total (293ms).
[15:07:23.236] <TB1> INFO: Test took 1191ms.
[15:07:23.238] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:23.545] <TB1> INFO: Expecting 2560 events.
[15:07:24.425] <TB1> INFO: 2560 events read in total (288ms).
[15:07:24.426] <TB1> INFO: Test took 1188ms.
[15:07:24.428] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:24.734] <TB1> INFO: Expecting 2560 events.
[15:07:25.615] <TB1> INFO: 2560 events read in total (289ms).
[15:07:25.615] <TB1> INFO: Test took 1187ms.
[15:07:25.617] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:25.924] <TB1> INFO: Expecting 2560 events.
[15:07:26.804] <TB1> INFO: 2560 events read in total (288ms).
[15:07:26.805] <TB1> INFO: Test took 1188ms.
[15:07:26.807] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:27.114] <TB1> INFO: Expecting 2560 events.
[15:07:27.994] <TB1> INFO: 2560 events read in total (288ms).
[15:07:27.995] <TB1> INFO: Test took 1188ms.
[15:07:27.996] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:28.304] <TB1> INFO: Expecting 2560 events.
[15:07:29.184] <TB1> INFO: 2560 events read in total (288ms).
[15:07:29.184] <TB1> INFO: Test took 1188ms.
[15:07:29.186] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:29.493] <TB1> INFO: Expecting 2560 events.
[15:07:30.373] <TB1> INFO: 2560 events read in total (288ms).
[15:07:30.374] <TB1> INFO: Test took 1188ms.
[15:07:30.376] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:30.682] <TB1> INFO: Expecting 2560 events.
[15:07:31.563] <TB1> INFO: 2560 events read in total (289ms).
[15:07:31.564] <TB1> INFO: Test took 1188ms.
[15:07:31.566] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:31.873] <TB1> INFO: Expecting 2560 events.
[15:07:32.753] <TB1> INFO: 2560 events read in total (288ms).
[15:07:32.754] <TB1> INFO: Test took 1188ms.
[15:07:32.756] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:33.063] <TB1> INFO: Expecting 2560 events.
[15:07:33.944] <TB1> INFO: 2560 events read in total (289ms).
[15:07:33.944] <TB1> INFO: Test took 1188ms.
[15:07:33.946] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:34.253] <TB1> INFO: Expecting 2560 events.
[15:07:35.134] <TB1> INFO: 2560 events read in total (289ms).
[15:07:35.134] <TB1> INFO: Test took 1188ms.
[15:07:35.136] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:35.443] <TB1> INFO: Expecting 2560 events.
[15:07:36.323] <TB1> INFO: 2560 events read in total (288ms).
[15:07:36.324] <TB1> INFO: Test took 1188ms.
[15:07:36.326] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:36.633] <TB1> INFO: Expecting 2560 events.
[15:07:37.513] <TB1> INFO: 2560 events read in total (288ms).
[15:07:37.514] <TB1> INFO: Test took 1188ms.
[15:07:37.516] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:37.823] <TB1> INFO: Expecting 2560 events.
[15:07:38.703] <TB1> INFO: 2560 events read in total (288ms).
[15:07:38.703] <TB1> INFO: Test took 1187ms.
[15:07:38.707] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:39.012] <TB1> INFO: Expecting 2560 events.
[15:07:39.893] <TB1> INFO: 2560 events read in total (289ms).
[15:07:39.893] <TB1> INFO: Test took 1186ms.
[15:07:39.895] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:40.202] <TB1> INFO: Expecting 2560 events.
[15:07:41.082] <TB1> INFO: 2560 events read in total (288ms).
[15:07:41.083] <TB1> INFO: Test took 1188ms.
[15:07:41.085] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:41.392] <TB1> INFO: Expecting 2560 events.
[15:07:42.273] <TB1> INFO: 2560 events read in total (289ms).
[15:07:42.273] <TB1> INFO: Test took 1188ms.
[15:07:42.275] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:42.582] <TB1> INFO: Expecting 2560 events.
[15:07:43.466] <TB1> INFO: 2560 events read in total (292ms).
[15:07:43.467] <TB1> INFO: Test took 1192ms.
[15:07:43.469] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:43.776] <TB1> INFO: Expecting 2560 events.
[15:07:44.661] <TB1> INFO: 2560 events read in total (294ms).
[15:07:44.661] <TB1> INFO: Test took 1192ms.
[15:07:44.663] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:44.970] <TB1> INFO: Expecting 2560 events.
[15:07:45.855] <TB1> INFO: 2560 events read in total (293ms).
[15:07:45.855] <TB1> INFO: Test took 1192ms.
[15:07:45.859] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:46.164] <TB1> INFO: Expecting 2560 events.
[15:07:47.048] <TB1> INFO: 2560 events read in total (292ms).
[15:07:47.049] <TB1> INFO: Test took 1190ms.
[15:07:47.052] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:47.358] <TB1> INFO: Expecting 2560 events.
[15:07:48.242] <TB1> INFO: 2560 events read in total (292ms).
[15:07:48.243] <TB1> INFO: Test took 1191ms.
[15:07:48.245] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:48.552] <TB1> INFO: Expecting 2560 events.
[15:07:49.436] <TB1> INFO: 2560 events read in total (292ms).
[15:07:49.437] <TB1> INFO: Test took 1192ms.
[15:07:49.440] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:49.745] <TB1> INFO: Expecting 2560 events.
[15:07:50.630] <TB1> INFO: 2560 events read in total (293ms).
[15:07:50.631] <TB1> INFO: Test took 1191ms.
[15:07:50.634] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:07:50.940] <TB1> INFO: Expecting 2560 events.
[15:07:51.826] <TB1> INFO: 2560 events read in total (294ms).
[15:07:51.826] <TB1> INFO: Test took 1192ms.
[15:07:52.291] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 730 seconds
[15:07:52.291] <TB1> INFO: PH scale (per ROC): 43 57 32 39 49 58 44 48 65 45 52 65 65 48 63 60
[15:07:52.291] <TB1> INFO: PH offset (per ROC): 97 134 102 90 78 117 101 111 117 114 109 127 121 102 124 85
[15:07:52.298] <TB1> INFO: Decoding statistics:
[15:07:52.298] <TB1> INFO: General information:
[15:07:52.298] <TB1> INFO: 16bit words read: 127880
[15:07:52.298] <TB1> INFO: valid events total: 20480
[15:07:52.298] <TB1> INFO: empty events: 17980
[15:07:52.298] <TB1> INFO: valid events with pixels: 2500
[15:07:52.299] <TB1> INFO: valid pixel hits: 2500
[15:07:52.299] <TB1> INFO: Event errors: 0
[15:07:52.299] <TB1> INFO: start marker: 0
[15:07:52.299] <TB1> INFO: stop marker: 0
[15:07:52.299] <TB1> INFO: overflow: 0
[15:07:52.299] <TB1> INFO: invalid 5bit words: 0
[15:07:52.299] <TB1> INFO: invalid XOR eye diagram: 0
[15:07:52.299] <TB1> INFO: frame (failed synchr.): 0
[15:07:52.299] <TB1> INFO: idle data (no TBM trl): 0
[15:07:52.299] <TB1> INFO: no data (only TBM hdr): 0
[15:07:52.299] <TB1> INFO: TBM errors: 0
[15:07:52.299] <TB1> INFO: flawed TBM headers: 0
[15:07:52.299] <TB1> INFO: flawed TBM trailers: 0
[15:07:52.299] <TB1> INFO: event ID mismatches: 0
[15:07:52.299] <TB1> INFO: ROC errors: 0
[15:07:52.299] <TB1> INFO: missing ROC header(s): 0
[15:07:52.299] <TB1> INFO: misplaced readback start: 0
[15:07:52.299] <TB1> INFO: Pixel decoding errors: 0
[15:07:52.299] <TB1> INFO: pixel data incomplete: 0
[15:07:52.299] <TB1> INFO: pixel address: 0
[15:07:52.299] <TB1> INFO: pulse height fill bit: 0
[15:07:52.299] <TB1> INFO: buffer corruption: 0
[15:07:52.474] <TB1> INFO: ######################################################################
[15:07:52.474] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[15:07:52.474] <TB1> INFO: ######################################################################
[15:07:52.489] <TB1> INFO: scanning low vcal = 10
[15:07:52.728] <TB1> INFO: Expecting 41600 events.
[15:07:56.299] <TB1> INFO: 41600 events read in total (2980ms).
[15:07:56.300] <TB1> INFO: Test took 3811ms.
[15:07:56.302] <TB1> INFO: scanning low vcal = 20
[15:07:56.601] <TB1> INFO: Expecting 41600 events.
[15:08:00.175] <TB1> INFO: 41600 events read in total (2982ms).
[15:08:00.176] <TB1> INFO: Test took 3874ms.
[15:08:00.178] <TB1> INFO: scanning low vcal = 30
[15:08:00.475] <TB1> INFO: Expecting 41600 events.
[15:08:04.123] <TB1> INFO: 41600 events read in total (3056ms).
[15:08:04.124] <TB1> INFO: Test took 3946ms.
[15:08:04.127] <TB1> INFO: scanning low vcal = 40
[15:08:04.403] <TB1> INFO: Expecting 41600 events.
[15:08:08.337] <TB1> INFO: 41600 events read in total (3342ms).
[15:08:08.338] <TB1> INFO: Test took 4211ms.
[15:08:08.342] <TB1> INFO: scanning low vcal = 50
[15:08:08.619] <TB1> INFO: Expecting 41600 events.
[15:08:12.586] <TB1> INFO: 41600 events read in total (3375ms).
[15:08:12.587] <TB1> INFO: Test took 4245ms.
[15:08:12.591] <TB1> INFO: scanning low vcal = 60
[15:08:12.867] <TB1> INFO: Expecting 41600 events.
[15:08:16.831] <TB1> INFO: 41600 events read in total (3372ms).
[15:08:16.832] <TB1> INFO: Test took 4241ms.
[15:08:16.835] <TB1> INFO: scanning low vcal = 70
[15:08:17.112] <TB1> INFO: Expecting 41600 events.
[15:08:21.072] <TB1> INFO: 41600 events read in total (3368ms).
[15:08:21.073] <TB1> INFO: Test took 4237ms.
[15:08:21.077] <TB1> INFO: scanning low vcal = 80
[15:08:21.353] <TB1> INFO: Expecting 41600 events.
[15:08:25.309] <TB1> INFO: 41600 events read in total (3364ms).
[15:08:25.310] <TB1> INFO: Test took 4233ms.
[15:08:25.313] <TB1> INFO: scanning low vcal = 90
[15:08:25.590] <TB1> INFO: Expecting 41600 events.
[15:08:29.550] <TB1> INFO: 41600 events read in total (3368ms).
[15:08:29.551] <TB1> INFO: Test took 4238ms.
[15:08:29.555] <TB1> INFO: scanning low vcal = 100
[15:08:29.832] <TB1> INFO: Expecting 41600 events.
[15:08:33.790] <TB1> INFO: 41600 events read in total (3366ms).
[15:08:33.791] <TB1> INFO: Test took 4235ms.
[15:08:33.794] <TB1> INFO: scanning low vcal = 110
[15:08:34.071] <TB1> INFO: Expecting 41600 events.
[15:08:38.031] <TB1> INFO: 41600 events read in total (3368ms).
[15:08:38.032] <TB1> INFO: Test took 4238ms.
[15:08:38.036] <TB1> INFO: scanning low vcal = 120
[15:08:38.313] <TB1> INFO: Expecting 41600 events.
[15:08:42.317] <TB1> INFO: 41600 events read in total (3412ms).
[15:08:42.318] <TB1> INFO: Test took 4282ms.
[15:08:42.321] <TB1> INFO: scanning low vcal = 130
[15:08:42.598] <TB1> INFO: Expecting 41600 events.
[15:08:46.653] <TB1> INFO: 41600 events read in total (3463ms).
[15:08:46.654] <TB1> INFO: Test took 4333ms.
[15:08:46.658] <TB1> INFO: scanning low vcal = 140
[15:08:46.979] <TB1> INFO: Expecting 41600 events.
[15:08:50.941] <TB1> INFO: 41600 events read in total (3370ms).
[15:08:50.942] <TB1> INFO: Test took 4284ms.
[15:08:50.946] <TB1> INFO: scanning low vcal = 150
[15:08:51.222] <TB1> INFO: Expecting 41600 events.
[15:08:55.182] <TB1> INFO: 41600 events read in total (3368ms).
[15:08:55.183] <TB1> INFO: Test took 4237ms.
[15:08:55.187] <TB1> INFO: scanning low vcal = 160
[15:08:55.464] <TB1> INFO: Expecting 41600 events.
[15:08:59.419] <TB1> INFO: 41600 events read in total (3363ms).
[15:08:59.420] <TB1> INFO: Test took 4233ms.
[15:08:59.423] <TB1> INFO: scanning low vcal = 170
[15:08:59.700] <TB1> INFO: Expecting 41600 events.
[15:09:03.662] <TB1> INFO: 41600 events read in total (3370ms).
[15:09:03.662] <TB1> INFO: Test took 4239ms.
[15:09:03.668] <TB1> INFO: scanning low vcal = 180
[15:09:03.943] <TB1> INFO: Expecting 41600 events.
[15:09:07.906] <TB1> INFO: 41600 events read in total (3371ms).
[15:09:07.907] <TB1> INFO: Test took 4239ms.
[15:09:07.910] <TB1> INFO: scanning low vcal = 190
[15:09:08.187] <TB1> INFO: Expecting 41600 events.
[15:09:12.158] <TB1> INFO: 41600 events read in total (3379ms).
[15:09:12.159] <TB1> INFO: Test took 4249ms.
[15:09:12.163] <TB1> INFO: scanning low vcal = 200
[15:09:12.439] <TB1> INFO: Expecting 41600 events.
[15:09:16.400] <TB1> INFO: 41600 events read in total (3369ms).
[15:09:16.401] <TB1> INFO: Test took 4237ms.
[15:09:16.404] <TB1> INFO: scanning low vcal = 210
[15:09:16.681] <TB1> INFO: Expecting 41600 events.
[15:09:20.638] <TB1> INFO: 41600 events read in total (3365ms).
[15:09:20.638] <TB1> INFO: Test took 4234ms.
[15:09:20.641] <TB1> INFO: scanning low vcal = 220
[15:09:20.918] <TB1> INFO: Expecting 41600 events.
[15:09:24.880] <TB1> INFO: 41600 events read in total (3370ms).
[15:09:24.881] <TB1> INFO: Test took 4240ms.
[15:09:24.885] <TB1> INFO: scanning low vcal = 230
[15:09:25.162] <TB1> INFO: Expecting 41600 events.
[15:09:29.122] <TB1> INFO: 41600 events read in total (3368ms).
[15:09:29.123] <TB1> INFO: Test took 4239ms.
[15:09:29.127] <TB1> INFO: scanning low vcal = 240
[15:09:29.404] <TB1> INFO: Expecting 41600 events.
[15:09:33.365] <TB1> INFO: 41600 events read in total (3369ms).
[15:09:33.366] <TB1> INFO: Test took 4239ms.
[15:09:33.369] <TB1> INFO: scanning low vcal = 250
[15:09:33.646] <TB1> INFO: Expecting 41600 events.
[15:09:37.608] <TB1> INFO: 41600 events read in total (3370ms).
[15:09:37.609] <TB1> INFO: Test took 4240ms.
[15:09:37.614] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[15:09:37.890] <TB1> INFO: Expecting 41600 events.
[15:09:41.866] <TB1> INFO: 41600 events read in total (3384ms).
[15:09:41.867] <TB1> INFO: Test took 4253ms.
[15:09:41.870] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[15:09:42.147] <TB1> INFO: Expecting 41600 events.
[15:09:46.103] <TB1> INFO: 41600 events read in total (3365ms).
[15:09:46.104] <TB1> INFO: Test took 4234ms.
[15:09:46.107] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[15:09:46.384] <TB1> INFO: Expecting 41600 events.
[15:09:50.337] <TB1> INFO: 41600 events read in total (3361ms).
[15:09:50.338] <TB1> INFO: Test took 4230ms.
[15:09:50.342] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[15:09:50.618] <TB1> INFO: Expecting 41600 events.
[15:09:54.568] <TB1> INFO: 41600 events read in total (3358ms).
[15:09:54.569] <TB1> INFO: Test took 4227ms.
[15:09:54.573] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[15:09:54.850] <TB1> INFO: Expecting 41600 events.
[15:09:58.809] <TB1> INFO: 41600 events read in total (3368ms).
[15:09:58.810] <TB1> INFO: Test took 4237ms.
[15:09:59.199] <TB1> INFO: PixTestGainPedestal::measure() done
[15:10:32.756] <TB1> INFO: PixTestGainPedestal::fit() done
[15:10:32.756] <TB1> INFO: non-linearity mean: 0.938 0.981 1.057 1.009 0.939 0.983 0.946 0.963 0.985 0.949 0.975 0.983 0.984 0.958 0.985 0.965
[15:10:32.756] <TB1> INFO: non-linearity RMS: 0.148 0.005 0.147 0.157 0.072 0.004 0.126 0.045 0.003 0.091 0.014 0.004 0.003 0.045 0.003 0.042
[15:10:32.756] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr35_C0.dat
[15:10:32.770] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr35_C1.dat
[15:10:32.783] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr35_C2.dat
[15:10:32.797] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr35_C3.dat
[15:10:32.811] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr35_C4.dat
[15:10:32.825] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr35_C5.dat
[15:10:32.838] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr35_C6.dat
[15:10:32.852] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr35_C7.dat
[15:10:32.865] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr35_C8.dat
[15:10:32.879] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr35_C9.dat
[15:10:32.893] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr35_C10.dat
[15:10:32.906] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr35_C11.dat
[15:10:32.920] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr35_C12.dat
[15:10:32.933] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr35_C13.dat
[15:10:32.947] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr35_C14.dat
[15:10:32.960] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1049_FullQualification_2016-11-15_13h36m_1479213374//000_Fulltest_m20//phCalibrationFitErr35_C15.dat
[15:10:32.974] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 160 seconds
[15:10:32.974] <TB1> INFO: Decoding statistics:
[15:10:32.974] <TB1> INFO: General information:
[15:10:32.974] <TB1> INFO: 16bit words read: 3329754
[15:10:32.974] <TB1> INFO: valid events total: 332800
[15:10:32.974] <TB1> INFO: empty events: 0
[15:10:32.974] <TB1> INFO: valid events with pixels: 332800
[15:10:32.974] <TB1> INFO: valid pixel hits: 666472
[15:10:32.974] <TB1> INFO: Event errors: 0
[15:10:32.974] <TB1> INFO: start marker: 0
[15:10:32.974] <TB1> INFO: stop marker: 0
[15:10:32.974] <TB1> INFO: overflow: 0
[15:10:32.974] <TB1> INFO: invalid 5bit words: 0
[15:10:32.974] <TB1> INFO: invalid XOR eye diagram: 0
[15:10:32.974] <TB1> INFO: frame (failed synchr.): 0
[15:10:32.974] <TB1> INFO: idle data (no TBM trl): 0
[15:10:32.974] <TB1> INFO: no data (only TBM hdr): 0
[15:10:32.974] <TB1> INFO: TBM errors: 0
[15:10:32.974] <TB1> INFO: flawed TBM headers: 0
[15:10:32.974] <TB1> INFO: flawed TBM trailers: 0
[15:10:32.974] <TB1> INFO: event ID mismatches: 0
[15:10:32.974] <TB1> INFO: ROC errors: 0
[15:10:32.974] <TB1> INFO: missing ROC header(s): 0
[15:10:32.974] <TB1> INFO: misplaced readback start: 0
[15:10:32.974] <TB1> INFO: Pixel decoding errors: 5
[15:10:32.974] <TB1> INFO: pixel data incomplete: 0
[15:10:32.974] <TB1> INFO: pixel address: 0
[15:10:32.974] <TB1> INFO: pulse height fill bit: 0
[15:10:32.974] <TB1> INFO: buffer corruption: 5
[15:10:32.993] <TB1> INFO: Decoding statistics:
[15:10:32.993] <TB1> INFO: General information:
[15:10:32.993] <TB1> INFO: 16bit words read: 3459170
[15:10:32.993] <TB1> INFO: valid events total: 353536
[15:10:32.993] <TB1> INFO: empty events: 18236
[15:10:32.993] <TB1> INFO: valid events with pixels: 335300
[15:10:32.993] <TB1> INFO: valid pixel hits: 668972
[15:10:32.993] <TB1> INFO: Event errors: 0
[15:10:32.993] <TB1> INFO: start marker: 0
[15:10:32.993] <TB1> INFO: stop marker: 0
[15:10:32.993] <TB1> INFO: overflow: 0
[15:10:32.993] <TB1> INFO: invalid 5bit words: 0
[15:10:32.993] <TB1> INFO: invalid XOR eye diagram: 0
[15:10:32.993] <TB1> INFO: frame (failed synchr.): 0
[15:10:32.993] <TB1> INFO: idle data (no TBM trl): 0
[15:10:32.993] <TB1> INFO: no data (only TBM hdr): 0
[15:10:32.993] <TB1> INFO: TBM errors: 0
[15:10:32.993] <TB1> INFO: flawed TBM headers: 0
[15:10:32.993] <TB1> INFO: flawed TBM trailers: 0
[15:10:32.993] <TB1> INFO: event ID mismatches: 0
[15:10:32.993] <TB1> INFO: ROC errors: 0
[15:10:32.993] <TB1> INFO: missing ROC header(s): 0
[15:10:32.993] <TB1> INFO: misplaced readback start: 0
[15:10:32.993] <TB1> INFO: Pixel decoding errors: 5
[15:10:32.993] <TB1> INFO: pixel data incomplete: 0
[15:10:32.993] <TB1> INFO: pixel address: 0
[15:10:32.993] <TB1> INFO: pulse height fill bit: 0
[15:10:32.993] <TB1> INFO: buffer corruption: 5
[15:10:32.993] <TB1> INFO: enter test to run
[15:10:32.993] <TB1> INFO: test: exit no parameter change
[15:10:33.135] <TB1> QUIET: Connection to board 154 closed.
[15:10:33.136] <TB1> INFO: pXar: this is the end, my friend