[13:08:08.576] <TB2> INFO: *** Welcome to pxar ***
[13:08:08.576] <TB2> INFO: *** Today: 2016/10/22
[13:08:08.582] <TB2> INFO: *** Version: c8ba-dirty
[13:08:08.582] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C15.dat
[13:08:08.582] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//tbmParameters_C1b.dat
[13:08:08.582] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//defaultMaskFile.dat
[13:08:08.583] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters_C15.dat
[13:08:08.649] <TB2> INFO: clk: 4
[13:08:08.649] <TB2> INFO: ctr: 4
[13:08:08.649] <TB2> INFO: sda: 19
[13:08:08.649] <TB2> INFO: tin: 9
[13:08:08.649] <TB2> INFO: level: 15
[13:08:08.649] <TB2> INFO: triggerdelay: 0
[13:08:08.649] <TB2> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[13:08:08.649] <TB2> INFO: Log level: INFO
[13:08:08.658] <TB2> INFO: Found DTB DTB_WWXUD2
[13:08:08.666] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[13:08:08.668] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[13:08:08.670] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[13:08:10.208] <TB2> INFO: DUT info:
[13:08:10.208] <TB2> INFO: The DUT currently contains the following objects:
[13:08:10.208] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[13:08:10.209] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:08:10.209] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:08:10.209] <TB2> INFO: TBM Core alpha (2): 7 registers set
[13:08:10.209] <TB2> INFO: TBM Core beta (3): 7 registers set
[13:08:10.209] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[13:08:10.209] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:10.209] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:10.209] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:10.209] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:10.209] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:10.209] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:10.209] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:10.209] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:10.209] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:10.209] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:10.209] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:10.209] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:10.209] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:10.209] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:10.209] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:10.209] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:10.610] <TB2> INFO: enter 'restricted' command line mode
[13:08:10.610] <TB2> INFO: enter test to run
[13:08:10.610] <TB2> INFO: test: pretest no parameter change
[13:08:10.610] <TB2> INFO: running: pretest
[13:08:10.617] <TB2> INFO: ######################################################################
[13:08:10.617] <TB2> INFO: PixTestPretest::doTest()
[13:08:10.617] <TB2> INFO: ######################################################################
[13:08:10.618] <TB2> INFO: ----------------------------------------------------------------------
[13:08:10.618] <TB2> INFO: PixTestPretest::programROC()
[13:08:10.618] <TB2> INFO: ----------------------------------------------------------------------
[13:08:28.632] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[13:08:28.632] <TB2> INFO: IA differences per ROC: 17.7 17.7 20.1 17.7 19.3 20.1 21.7 18.5 21.7 20.1 21.7 16.9 20.9 16.9 21.7 22.5
[13:08:28.691] <TB2> INFO: ----------------------------------------------------------------------
[13:08:28.691] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[13:08:28.691] <TB2> INFO: ----------------------------------------------------------------------
[13:08:37.307] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 382.7 mA = 23.9187 mA/ROC
[13:08:37.307] <TB2> INFO: i(loss) [mA/ROC]: 20.1 19.3 20.1 20.1 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3
[13:08:37.346] <TB2> INFO: ----------------------------------------------------------------------
[13:08:37.346] <TB2> INFO: PixTestPretest::findTiming()
[13:08:37.346] <TB2> INFO: ----------------------------------------------------------------------
[13:08:37.346] <TB2> INFO: PixTestCmd::init()

[13:09:09.429] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[13:09:09.429] <TB2> INFO: (success/tries = 100/100), width = 3
[13:09:10.932] <TB2> INFO: ----------------------------------------------------------------------
[13:09:10.932] <TB2> INFO: PixTestPretest::findWorkingPixel()
[13:09:10.932] <TB2> INFO: ----------------------------------------------------------------------
[13:09:11.027] <TB2> INFO: Expecting 231680 events.
[13:09:20.970] <TB2> INFO: 231680 events read in total (9350ms).
[13:09:20.980] <TB2> INFO: Test took 10043ms.
[13:09:21.222] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[13:09:21.257] <TB2> INFO: ----------------------------------------------------------------------
[13:09:21.257] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[13:09:21.257] <TB2> INFO: ----------------------------------------------------------------------
[13:09:21.352] <TB2> INFO: Expecting 231680 events.
[13:09:31.395] <TB2> INFO: 231680 events read in total (9451ms).
[13:09:31.404] <TB2> INFO: Test took 10141ms.
[13:09:31.659] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[13:09:31.659] <TB2> INFO: CalDel: 82 84 96 96 78 104 92 87 97 89 94 92 93 96 100 109
[13:09:31.659] <TB2> INFO: VthrComp: 51 52 51 51 52 51 51 51 51 51 51 52 51 51 51 52
[13:09:31.663] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C0.dat
[13:09:31.663] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C1.dat
[13:09:31.663] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C2.dat
[13:09:31.663] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C3.dat
[13:09:31.664] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C4.dat
[13:09:31.664] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C5.dat
[13:09:31.664] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C6.dat
[13:09:31.664] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C7.dat
[13:09:31.664] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C8.dat
[13:09:31.664] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C9.dat
[13:09:31.664] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C10.dat
[13:09:31.665] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C11.dat
[13:09:31.665] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C12.dat
[13:09:31.665] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C13.dat
[13:09:31.665] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C14.dat
[13:09:31.665] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C15.dat
[13:09:31.665] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//tbmParameters_C0a.dat
[13:09:31.665] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//tbmParameters_C0b.dat
[13:09:31.665] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//tbmParameters_C1a.dat
[13:09:31.665] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//tbmParameters_C1b.dat
[13:09:31.666] <TB2> INFO: PixTestPretest::doTest() done, duration: 81 seconds
[13:09:31.719] <TB2> INFO: enter test to run
[13:09:31.719] <TB2> INFO: test: FullTest no parameter change
[13:09:31.719] <TB2> INFO: running: fulltest
[13:09:31.719] <TB2> INFO: ######################################################################
[13:09:31.719] <TB2> INFO: PixTestFullTest::doTest()
[13:09:31.719] <TB2> INFO: ######################################################################
[13:09:31.721] <TB2> INFO: ######################################################################
[13:09:31.721] <TB2> INFO: PixTestAlive::doTest()
[13:09:31.721] <TB2> INFO: ######################################################################
[13:09:31.722] <TB2> INFO: ----------------------------------------------------------------------
[13:09:31.722] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:09:31.722] <TB2> INFO: ----------------------------------------------------------------------
[13:09:31.961] <TB2> INFO: Expecting 41600 events.
[13:09:35.491] <TB2> INFO: 41600 events read in total (2938ms).
[13:09:35.492] <TB2> INFO: Test took 3769ms.
[13:09:35.723] <TB2> INFO: PixTestAlive::aliveTest() done
[13:09:35.724] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:09:35.725] <TB2> INFO: ----------------------------------------------------------------------
[13:09:35.725] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:09:35.725] <TB2> INFO: ----------------------------------------------------------------------
[13:09:35.965] <TB2> INFO: Expecting 41600 events.
[13:09:39.091] <TB2> INFO: 41600 events read in total (2535ms).
[13:09:39.091] <TB2> INFO: Test took 3364ms.
[13:09:39.092] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[13:09:39.327] <TB2> INFO: PixTestAlive::maskTest() done
[13:09:39.327] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:09:39.328] <TB2> INFO: ----------------------------------------------------------------------
[13:09:39.328] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:09:39.329] <TB2> INFO: ----------------------------------------------------------------------
[13:09:39.576] <TB2> INFO: Expecting 41600 events.
[13:09:43.074] <TB2> INFO: 41600 events read in total (2907ms).
[13:09:43.074] <TB2> INFO: Test took 3744ms.
















[13:09:43.307] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[13:09:43.307] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:09:43.307] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[13:09:43.307] <TB2> INFO: Decoding statistics:
[13:09:43.307] <TB2> INFO: General information:
[13:09:43.307] <TB2> INFO: 16bit words read: 0
[13:09:43.307] <TB2> INFO: valid events total: 0
[13:09:43.307] <TB2> INFO: empty events: 0
[13:09:43.307] <TB2> INFO: valid events with pixels: 0
[13:09:43.307] <TB2> INFO: valid pixel hits: 0
[13:09:43.307] <TB2> INFO: Event errors: 0
[13:09:43.307] <TB2> INFO: start marker: 0
[13:09:43.307] <TB2> INFO: stop marker: 0
[13:09:43.307] <TB2> INFO: overflow: 0
[13:09:43.307] <TB2> INFO: invalid 5bit words: 0
[13:09:43.307] <TB2> INFO: invalid XOR eye diagram: 0
[13:09:43.308] <TB2> INFO: frame (failed synchr.): 0
[13:09:43.308] <TB2> INFO: idle data (no TBM trl): 0
[13:09:43.308] <TB2> INFO: no data (only TBM hdr): 0
[13:09:43.308] <TB2> INFO: TBM errors: 0
[13:09:43.308] <TB2> INFO: flawed TBM headers: 0
[13:09:43.308] <TB2> INFO: flawed TBM trailers: 0
[13:09:43.308] <TB2> INFO: event ID mismatches: 0
[13:09:43.308] <TB2> INFO: ROC errors: 0
[13:09:43.308] <TB2> INFO: missing ROC header(s): 0
[13:09:43.308] <TB2> INFO: misplaced readback start: 0
[13:09:43.308] <TB2> INFO: Pixel decoding errors: 0
[13:09:43.308] <TB2> INFO: pixel data incomplete: 0
[13:09:43.308] <TB2> INFO: pixel address: 0
[13:09:43.308] <TB2> INFO: pulse height fill bit: 0
[13:09:43.308] <TB2> INFO: buffer corruption: 0
[13:09:43.316] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C15.dat
[13:09:43.316] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr_C15.dat

[13:09:43.316] <TB2> INFO: ######################################################################
[13:09:43.316] <TB2> INFO: PixTestReadback::doTest()
[13:09:43.316] <TB2> INFO: ######################################################################
[13:09:43.316] <TB2> INFO: ----------------------------------------------------------------------
[13:09:43.316] <TB2> INFO: PixTestReadback::CalibrateVd()
[13:09:43.316] <TB2> INFO: ----------------------------------------------------------------------
[13:09:53.288] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C0.dat
[13:09:53.288] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C1.dat
[13:09:53.288] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C2.dat
[13:09:53.288] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C3.dat
[13:09:53.288] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C4.dat
[13:09:53.288] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C5.dat
[13:09:53.288] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C6.dat
[13:09:53.289] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C7.dat
[13:09:53.289] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C8.dat
[13:09:53.289] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C9.dat
[13:09:53.289] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C10.dat
[13:09:53.289] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C11.dat
[13:09:53.289] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C12.dat
[13:09:53.289] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C13.dat
[13:09:53.289] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C14.dat
[13:09:53.289] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C15.dat
[13:09:53.318] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:09:53.318] <TB2> INFO: ----------------------------------------------------------------------
[13:09:53.318] <TB2> INFO: PixTestReadback::CalibrateVa()
[13:09:53.318] <TB2> INFO: ----------------------------------------------------------------------
[13:10:03.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C0.dat
[13:10:03.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C1.dat
[13:10:03.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C2.dat
[13:10:03.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C3.dat
[13:10:03.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C4.dat
[13:10:03.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C5.dat
[13:10:03.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C6.dat
[13:10:03.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C7.dat
[13:10:03.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C8.dat
[13:10:03.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C9.dat
[13:10:03.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C10.dat
[13:10:03.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C11.dat
[13:10:03.248] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C12.dat
[13:10:03.249] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C13.dat
[13:10:03.249] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C14.dat
[13:10:03.249] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C15.dat
[13:10:03.279] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:10:03.279] <TB2> INFO: ----------------------------------------------------------------------
[13:10:03.279] <TB2> INFO: PixTestReadback::readbackVbg()
[13:10:03.279] <TB2> INFO: ----------------------------------------------------------------------
[13:10:10.950] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:10:10.950] <TB2> INFO: ----------------------------------------------------------------------
[13:10:10.950] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[13:10:10.950] <TB2> INFO: ----------------------------------------------------------------------
[13:10:10.950] <TB2> INFO: Vbg will be calibrated using Vd calibration
[13:10:10.950] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 153.5calibrated Vbg = 1.20113 :::*/*/*/*/
[13:10:10.950] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 159calibrated Vbg = 1.19278 :::*/*/*/*/
[13:10:10.950] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 151.1calibrated Vbg = 1.18909 :::*/*/*/*/
[13:10:10.950] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 155.3calibrated Vbg = 1.199 :::*/*/*/*/
[13:10:10.950] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 162.1calibrated Vbg = 1.1908 :::*/*/*/*/
[13:10:10.950] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 158.9calibrated Vbg = 1.20046 :::*/*/*/*/
[13:10:10.950] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 154.5calibrated Vbg = 1.20268 :::*/*/*/*/
[13:10:10.950] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 161.2calibrated Vbg = 1.19481 :::*/*/*/*/
[13:10:10.950] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 162.8calibrated Vbg = 1.19322 :::*/*/*/*/
[13:10:10.950] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 156.5calibrated Vbg = 1.19759 :::*/*/*/*/
[13:10:10.950] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 154.5calibrated Vbg = 1.18815 :::*/*/*/*/
[13:10:10.950] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 149.4calibrated Vbg = 1.18416 :::*/*/*/*/
[13:10:10.950] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 151.8calibrated Vbg = 1.19076 :::*/*/*/*/
[13:10:10.950] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 162.3calibrated Vbg = 1.19767 :::*/*/*/*/
[13:10:10.950] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 152.2calibrated Vbg = 1.19871 :::*/*/*/*/
[13:10:10.950] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 152.2calibrated Vbg = 1.19686 :::*/*/*/*/
[13:10:10.953] <TB2> INFO: ----------------------------------------------------------------------
[13:10:10.953] <TB2> INFO: PixTestReadback::CalibrateIa()
[13:10:10.953] <TB2> INFO: ----------------------------------------------------------------------
[13:12:51.776] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C0.dat
[13:12:51.776] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C1.dat
[13:12:51.776] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C2.dat
[13:12:51.776] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C3.dat
[13:12:51.776] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C4.dat
[13:12:51.776] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C5.dat
[13:12:51.776] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C6.dat
[13:12:51.776] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C7.dat
[13:12:51.776] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C8.dat
[13:12:51.776] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C9.dat
[13:12:51.776] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C10.dat
[13:12:51.776] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C11.dat
[13:12:51.776] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C12.dat
[13:12:51.776] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C13.dat
[13:12:51.776] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C14.dat
[13:12:51.777] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C15.dat
[13:12:51.803] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:12:51.805] <TB2> INFO: PixTestReadback::doTest() done
[13:12:51.805] <TB2> INFO: Decoding statistics:
[13:12:51.805] <TB2> INFO: General information:
[13:12:51.805] <TB2> INFO: 16bit words read: 1536
[13:12:51.805] <TB2> INFO: valid events total: 256
[13:12:51.805] <TB2> INFO: empty events: 256
[13:12:51.805] <TB2> INFO: valid events with pixels: 0
[13:12:51.805] <TB2> INFO: valid pixel hits: 0
[13:12:51.805] <TB2> INFO: Event errors: 0
[13:12:51.805] <TB2> INFO: start marker: 0
[13:12:51.805] <TB2> INFO: stop marker: 0
[13:12:51.805] <TB2> INFO: overflow: 0
[13:12:51.805] <TB2> INFO: invalid 5bit words: 0
[13:12:51.805] <TB2> INFO: invalid XOR eye diagram: 0
[13:12:51.805] <TB2> INFO: frame (failed synchr.): 0
[13:12:51.805] <TB2> INFO: idle data (no TBM trl): 0
[13:12:51.805] <TB2> INFO: no data (only TBM hdr): 0
[13:12:51.805] <TB2> INFO: TBM errors: 0
[13:12:51.805] <TB2> INFO: flawed TBM headers: 0
[13:12:51.805] <TB2> INFO: flawed TBM trailers: 0
[13:12:51.805] <TB2> INFO: event ID mismatches: 0
[13:12:51.805] <TB2> INFO: ROC errors: 0
[13:12:51.805] <TB2> INFO: missing ROC header(s): 0
[13:12:51.805] <TB2> INFO: misplaced readback start: 0
[13:12:51.805] <TB2> INFO: Pixel decoding errors: 0
[13:12:51.805] <TB2> INFO: pixel data incomplete: 0
[13:12:51.805] <TB2> INFO: pixel address: 0
[13:12:51.805] <TB2> INFO: pulse height fill bit: 0
[13:12:51.805] <TB2> INFO: buffer corruption: 0
[13:12:51.874] <TB2> INFO: ######################################################################
[13:12:51.874] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[13:12:51.874] <TB2> INFO: ######################################################################
[13:12:51.876] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[13:12:51.889] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:12:51.889] <TB2> INFO: run 1 of 1
[13:12:52.125] <TB2> INFO: Expecting 3120000 events.
[13:13:23.511] <TB2> INFO: 673640 events read in total (30794ms).











[13:13:53.499] <TB2> INFO: 1340170 events read in total (60782ms).











[13:14:23.645] <TB2> INFO: 2003400 events read in total (90928ms).











[13:14:53.704] <TB2> INFO: 2668400 events read in total (120987ms).











[13:15:14.656] <TB2> INFO: 3120000 events read in total (141939ms).
[13:15:14.720] <TB2> INFO: Test took 142832ms.
[13:15:41.282] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 169 seconds
[13:15:41.282] <TB2> INFO: number of dead bumps (per ROC): 14 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0
[13:15:41.282] <TB2> INFO: separation cut (per ROC): 104 104 109 100 119 104 115 106 109 106 103 109 100 101 103 104
[13:15:41.282] <TB2> INFO: Decoding statistics:
[13:15:41.282] <TB2> INFO: General information:
[13:15:41.282] <TB2> INFO: 16bit words read: 0
[13:15:41.282] <TB2> INFO: valid events total: 0
[13:15:41.283] <TB2> INFO: empty events: 0
[13:15:41.283] <TB2> INFO: valid events with pixels: 0
[13:15:41.283] <TB2> INFO: valid pixel hits: 0
[13:15:41.283] <TB2> INFO: Event errors: 0
[13:15:41.283] <TB2> INFO: start marker: 0
[13:15:41.283] <TB2> INFO: stop marker: 0
[13:15:41.283] <TB2> INFO: overflow: 0
[13:15:41.283] <TB2> INFO: invalid 5bit words: 0
[13:15:41.283] <TB2> INFO: invalid XOR eye diagram: 0
[13:15:41.283] <TB2> INFO: frame (failed synchr.): 0
[13:15:41.283] <TB2> INFO: idle data (no TBM trl): 0
[13:15:41.283] <TB2> INFO: no data (only TBM hdr): 0
[13:15:41.283] <TB2> INFO: TBM errors: 0
[13:15:41.283] <TB2> INFO: flawed TBM headers: 0
[13:15:41.283] <TB2> INFO: flawed TBM trailers: 0
[13:15:41.283] <TB2> INFO: event ID mismatches: 0
[13:15:41.283] <TB2> INFO: ROC errors: 0
[13:15:41.283] <TB2> INFO: missing ROC header(s): 0
[13:15:41.283] <TB2> INFO: misplaced readback start: 0
[13:15:41.283] <TB2> INFO: Pixel decoding errors: 0
[13:15:41.283] <TB2> INFO: pixel data incomplete: 0
[13:15:41.283] <TB2> INFO: pixel address: 0
[13:15:41.283] <TB2> INFO: pulse height fill bit: 0
[13:15:41.283] <TB2> INFO: buffer corruption: 0
[13:15:41.325] <TB2> INFO: ######################################################################
[13:15:41.325] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:15:41.325] <TB2> INFO: ######################################################################
[13:15:41.325] <TB2> INFO: ----------------------------------------------------------------------
[13:15:41.325] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:15:41.326] <TB2> INFO: ----------------------------------------------------------------------
[13:15:41.326] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[13:15:41.340] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[13:15:41.340] <TB2> INFO: run 1 of 1
[13:15:41.600] <TB2> INFO: Expecting 36608000 events.
[13:16:05.370] <TB2> INFO: 695850 events read in total (23179ms).
[13:16:28.360] <TB2> INFO: 1376700 events read in total (46169ms).
[13:16:51.109] <TB2> INFO: 2055600 events read in total (68918ms).
[13:17:13.965] <TB2> INFO: 2734100 events read in total (91774ms).
[13:17:36.997] <TB2> INFO: 3410900 events read in total (114806ms).
[13:18:00.206] <TB2> INFO: 4088400 events read in total (138015ms).
[13:18:23.153] <TB2> INFO: 4765600 events read in total (160962ms).
[13:18:45.906] <TB2> INFO: 5441550 events read in total (183715ms).
[13:19:08.588] <TB2> INFO: 6118800 events read in total (206397ms).
[13:19:31.557] <TB2> INFO: 6796150 events read in total (229366ms).
[13:19:54.221] <TB2> INFO: 7473250 events read in total (252030ms).
[13:20:17.154] <TB2> INFO: 8152700 events read in total (274963ms).
[13:20:39.993] <TB2> INFO: 8830400 events read in total (297802ms).
[13:21:03.025] <TB2> INFO: 9508850 events read in total (320834ms).
[13:21:26.238] <TB2> INFO: 10186300 events read in total (344047ms).
[13:21:49.216] <TB2> INFO: 10860950 events read in total (367025ms).
[13:22:12.159] <TB2> INFO: 11536250 events read in total (389968ms).
[13:22:35.183] <TB2> INFO: 12210850 events read in total (412992ms).
[13:22:58.197] <TB2> INFO: 12883950 events read in total (436006ms).
[13:23:21.119] <TB2> INFO: 13557550 events read in total (458928ms).
[13:23:44.104] <TB2> INFO: 14232050 events read in total (481913ms).
[13:24:06.970] <TB2> INFO: 14905700 events read in total (504779ms).
[13:24:29.834] <TB2> INFO: 15580150 events read in total (527643ms).
[13:24:52.869] <TB2> INFO: 16252150 events read in total (550678ms).
[13:25:15.975] <TB2> INFO: 16926300 events read in total (573784ms).
[13:25:38.987] <TB2> INFO: 17597450 events read in total (596796ms).
[13:26:01.948] <TB2> INFO: 18268800 events read in total (619757ms).
[13:26:24.894] <TB2> INFO: 18940850 events read in total (642703ms).
[13:26:47.788] <TB2> INFO: 19611950 events read in total (665597ms).
[13:27:10.795] <TB2> INFO: 20282000 events read in total (688604ms).
[13:27:33.749] <TB2> INFO: 20952900 events read in total (711558ms).
[13:27:56.507] <TB2> INFO: 21623500 events read in total (734316ms).
[13:28:19.264] <TB2> INFO: 22292900 events read in total (757073ms).
[13:28:41.929] <TB2> INFO: 22961000 events read in total (779738ms).
[13:29:04.707] <TB2> INFO: 23629400 events read in total (802516ms).
[13:29:27.588] <TB2> INFO: 24297900 events read in total (825397ms).
[13:29:50.267] <TB2> INFO: 24968550 events read in total (848076ms).
[13:30:13.143] <TB2> INFO: 25638700 events read in total (870952ms).
[13:30:36.011] <TB2> INFO: 26306150 events read in total (893820ms).
[13:30:58.662] <TB2> INFO: 26974450 events read in total (916471ms).
[13:31:21.418] <TB2> INFO: 27641600 events read in total (939227ms).
[13:31:44.320] <TB2> INFO: 28309600 events read in total (962129ms).
[13:32:06.925] <TB2> INFO: 28977000 events read in total (984734ms).
[13:32:29.684] <TB2> INFO: 29644700 events read in total (1007493ms).
[13:32:52.567] <TB2> INFO: 30313050 events read in total (1030376ms).
[13:33:15.272] <TB2> INFO: 30981300 events read in total (1053081ms).
[13:33:38.192] <TB2> INFO: 31648050 events read in total (1076002ms).
[13:34:00.989] <TB2> INFO: 32316550 events read in total (1098798ms).
[13:34:23.829] <TB2> INFO: 32984150 events read in total (1121638ms).
[13:34:46.797] <TB2> INFO: 33652700 events read in total (1144606ms).
[13:35:09.897] <TB2> INFO: 34320100 events read in total (1167706ms).
[13:35:32.707] <TB2> INFO: 34990650 events read in total (1190516ms).
[13:35:55.582] <TB2> INFO: 35660500 events read in total (1213391ms).
[13:36:19.070] <TB2> INFO: 36339850 events read in total (1236879ms).
[13:36:28.384] <TB2> INFO: 36608000 events read in total (1246193ms).
[13:36:28.464] <TB2> INFO: Test took 1247123ms.
[13:36:29.052] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:36:31.014] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:36:33.163] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:36:35.164] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:36:37.184] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:36:39.341] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:36:41.130] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:36:42.834] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:36:45.137] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:36:47.534] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:36:49.894] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:36:51.931] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:36:53.637] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:36:55.150] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:36:56.817] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:36:58.661] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:37:00.310] <TB2> INFO: PixTestScurves::scurves() done
[13:37:00.310] <TB2> INFO: Vcal mean: 122.38 121.85 129.02 111.80 135.76 133.54 130.76 126.12 128.46 124.08 121.02 128.96 120.14 113.22 112.94 124.68
[13:37:00.310] <TB2> INFO: Vcal RMS: 6.69 5.96 6.16 5.24 5.73 8.75 6.24 6.05 5.69 6.30 5.98 6.96 6.66 4.70 5.00 6.62
[13:37:00.310] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1278 seconds
[13:37:00.310] <TB2> INFO: Decoding statistics:
[13:37:00.310] <TB2> INFO: General information:
[13:37:00.310] <TB2> INFO: 16bit words read: 0
[13:37:00.310] <TB2> INFO: valid events total: 0
[13:37:00.310] <TB2> INFO: empty events: 0
[13:37:00.311] <TB2> INFO: valid events with pixels: 0
[13:37:00.311] <TB2> INFO: valid pixel hits: 0
[13:37:00.311] <TB2> INFO: Event errors: 0
[13:37:00.311] <TB2> INFO: start marker: 0
[13:37:00.311] <TB2> INFO: stop marker: 0
[13:37:00.311] <TB2> INFO: overflow: 0
[13:37:00.311] <TB2> INFO: invalid 5bit words: 0
[13:37:00.311] <TB2> INFO: invalid XOR eye diagram: 0
[13:37:00.311] <TB2> INFO: frame (failed synchr.): 0
[13:37:00.311] <TB2> INFO: idle data (no TBM trl): 0
[13:37:00.311] <TB2> INFO: no data (only TBM hdr): 0
[13:37:00.311] <TB2> INFO: TBM errors: 0
[13:37:00.311] <TB2> INFO: flawed TBM headers: 0
[13:37:00.311] <TB2> INFO: flawed TBM trailers: 0
[13:37:00.311] <TB2> INFO: event ID mismatches: 0
[13:37:00.311] <TB2> INFO: ROC errors: 0
[13:37:00.311] <TB2> INFO: missing ROC header(s): 0
[13:37:00.311] <TB2> INFO: misplaced readback start: 0
[13:37:00.311] <TB2> INFO: Pixel decoding errors: 0
[13:37:00.311] <TB2> INFO: pixel data incomplete: 0
[13:37:00.311] <TB2> INFO: pixel address: 0
[13:37:00.311] <TB2> INFO: pulse height fill bit: 0
[13:37:00.311] <TB2> INFO: buffer corruption: 0
[13:37:00.388] <TB2> INFO: ######################################################################
[13:37:00.388] <TB2> INFO: PixTestTrim::doTest()
[13:37:00.388] <TB2> INFO: ######################################################################
[13:37:00.389] <TB2> INFO: ----------------------------------------------------------------------
[13:37:00.389] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[13:37:00.389] <TB2> INFO: ----------------------------------------------------------------------
[13:37:00.447] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:37:00.447] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:37:00.461] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:37:00.461] <TB2> INFO: run 1 of 1
[13:37:00.701] <TB2> INFO: Expecting 5025280 events.
[13:37:31.690] <TB2> INFO: 828128 events read in total (30396ms).
[13:38:01.973] <TB2> INFO: 1654752 events read in total (60679ms).
[13:38:32.269] <TB2> INFO: 2477424 events read in total (90976ms).
[13:39:02.345] <TB2> INFO: 3298536 events read in total (121051ms).
[13:39:32.056] <TB2> INFO: 4116360 events read in total (150763ms).
[13:40:02.363] <TB2> INFO: 4932640 events read in total (181069ms).
[13:40:06.536] <TB2> INFO: 5025280 events read in total (185242ms).
[13:40:06.599] <TB2> INFO: Test took 186138ms.
[13:40:22.907] <TB2> INFO: ROC 0 VthrComp = 118
[13:40:22.907] <TB2> INFO: ROC 1 VthrComp = 122
[13:40:22.907] <TB2> INFO: ROC 2 VthrComp = 132
[13:40:22.907] <TB2> INFO: ROC 3 VthrComp = 110
[13:40:22.907] <TB2> INFO: ROC 4 VthrComp = 131
[13:40:22.908] <TB2> INFO: ROC 5 VthrComp = 124
[13:40:22.908] <TB2> INFO: ROC 6 VthrComp = 131
[13:40:22.908] <TB2> INFO: ROC 7 VthrComp = 122
[13:40:22.908] <TB2> INFO: ROC 8 VthrComp = 132
[13:40:22.908] <TB2> INFO: ROC 9 VthrComp = 122
[13:40:22.908] <TB2> INFO: ROC 10 VthrComp = 122
[13:40:22.909] <TB2> INFO: ROC 11 VthrComp = 127
[13:40:22.910] <TB2> INFO: ROC 12 VthrComp = 114
[13:40:22.910] <TB2> INFO: ROC 13 VthrComp = 113
[13:40:22.910] <TB2> INFO: ROC 14 VthrComp = 115
[13:40:22.910] <TB2> INFO: ROC 15 VthrComp = 120
[13:40:23.187] <TB2> INFO: Expecting 41600 events.
[13:40:26.727] <TB2> INFO: 41600 events read in total (2948ms).
[13:40:26.728] <TB2> INFO: Test took 3816ms.
[13:40:26.738] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:40:26.738] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:40:26.749] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:40:26.749] <TB2> INFO: run 1 of 1
[13:40:27.027] <TB2> INFO: Expecting 5025280 events.
[13:40:53.739] <TB2> INFO: 592376 events read in total (26120ms).
[13:41:19.422] <TB2> INFO: 1182936 events read in total (51803ms).
[13:41:45.083] <TB2> INFO: 1772880 events read in total (77464ms).
[13:42:10.622] <TB2> INFO: 2362400 events read in total (103003ms).
[13:42:36.261] <TB2> INFO: 2949904 events read in total (128642ms).
[13:43:02.470] <TB2> INFO: 3536400 events read in total (154851ms).
[13:43:28.447] <TB2> INFO: 4122576 events read in total (180828ms).
[13:43:54.645] <TB2> INFO: 4708336 events read in total (207026ms).
[13:44:08.717] <TB2> INFO: 5025280 events read in total (221098ms).
[13:44:08.805] <TB2> INFO: Test took 222056ms.
[13:44:36.049] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 62.5931 for pixel 2/8 mean/min/max = 47.4808/32.283/62.6787
[13:44:36.050] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 59.3791 for pixel 20/4 mean/min/max = 45.8944/32.3599/59.4289
[13:44:36.050] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 58.6305 for pixel 8/12 mean/min/max = 45.5802/32.4863/58.6742
[13:44:36.050] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 60.9339 for pixel 2/0 mean/min/max = 48.276/35.1392/61.4129
[13:44:36.051] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 66.5275 for pixel 10/75 mean/min/max = 51.5197/36.3926/66.6468
[13:44:36.051] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 63.0744 for pixel 17/75 mean/min/max = 47.0992/31.0079/63.1904
[13:44:36.052] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 59.9053 for pixel 2/0 mean/min/max = 46.4739/32.8593/60.0886
[13:44:36.052] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 62.5584 for pixel 12/1 mean/min/max = 48.2911/34.0081/62.5742
[13:44:36.053] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 58.1934 for pixel 34/14 mean/min/max = 44.9601/31.6802/58.24
[13:44:36.053] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 60.8082 for pixel 3/9 mean/min/max = 46.6478/32.3781/60.9175
[13:44:36.054] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 59.2183 for pixel 50/72 mean/min/max = 45.9804/32.7331/59.2276
[13:44:36.054] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 60.7993 for pixel 23/42 mean/min/max = 46.1788/31.4388/60.9187
[13:44:36.055] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 61.0778 for pixel 19/73 mean/min/max = 46.9789/32.8793/61.0786
[13:44:36.055] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 58.1258 for pixel 29/12 mean/min/max = 45.8739/33.316/58.4319
[13:44:36.056] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 58.6027 for pixel 19/71 mean/min/max = 45.4642/32.2205/58.7079
[13:44:36.056] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 61.2577 for pixel 21/77 mean/min/max = 47.0824/32.8921/61.2728
[13:44:36.057] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:36.146] <TB2> INFO: Expecting 411648 events.
[13:44:45.379] <TB2> INFO: 411648 events read in total (8641ms).
[13:44:45.385] <TB2> INFO: Expecting 411648 events.
[13:44:54.630] <TB2> INFO: 411648 events read in total (8841ms).
[13:44:54.644] <TB2> INFO: Expecting 411648 events.
[13:45:03.923] <TB2> INFO: 411648 events read in total (8876ms).
[13:45:03.936] <TB2> INFO: Expecting 411648 events.
[13:45:13.183] <TB2> INFO: 411648 events read in total (8844ms).
[13:45:13.200] <TB2> INFO: Expecting 411648 events.
[13:45:22.529] <TB2> INFO: 411648 events read in total (8926ms).
[13:45:22.548] <TB2> INFO: Expecting 411648 events.
[13:45:31.826] <TB2> INFO: 411648 events read in total (8875ms).
[13:45:31.848] <TB2> INFO: Expecting 411648 events.
[13:45:41.213] <TB2> INFO: 411648 events read in total (8962ms).
[13:45:41.237] <TB2> INFO: Expecting 411648 events.
[13:45:50.575] <TB2> INFO: 411648 events read in total (8935ms).
[13:45:50.603] <TB2> INFO: Expecting 411648 events.
[13:45:59.916] <TB2> INFO: 411648 events read in total (8911ms).
[13:45:59.945] <TB2> INFO: Expecting 411648 events.
[13:46:09.274] <TB2> INFO: 411648 events read in total (8925ms).
[13:46:09.307] <TB2> INFO: Expecting 411648 events.
[13:46:18.651] <TB2> INFO: 411648 events read in total (8941ms).
[13:46:18.685] <TB2> INFO: Expecting 411648 events.
[13:46:28.029] <TB2> INFO: 411648 events read in total (8941ms).
[13:46:28.067] <TB2> INFO: Expecting 411648 events.
[13:46:37.382] <TB2> INFO: 411648 events read in total (8912ms).
[13:46:37.422] <TB2> INFO: Expecting 411648 events.
[13:46:46.723] <TB2> INFO: 411648 events read in total (8898ms).
[13:46:46.765] <TB2> INFO: Expecting 411648 events.
[13:46:56.137] <TB2> INFO: 411648 events read in total (8969ms).
[13:46:56.185] <TB2> INFO: Expecting 411648 events.
[13:47:05.436] <TB2> INFO: 411648 events read in total (8848ms).
[13:47:05.500] <TB2> INFO: Test took 149443ms.
[13:47:06.238] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:47:06.252] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:47:06.252] <TB2> INFO: run 1 of 1
[13:47:06.502] <TB2> INFO: Expecting 5025280 events.
[13:47:32.944] <TB2> INFO: 590288 events read in total (25850ms).
[13:47:58.928] <TB2> INFO: 1179160 events read in total (51834ms).
[13:48:25.093] <TB2> INFO: 1766144 events read in total (77999ms).
[13:48:51.262] <TB2> INFO: 2353104 events read in total (104168ms).
[13:49:17.415] <TB2> INFO: 2940312 events read in total (130321ms).
[13:49:43.502] <TB2> INFO: 3527944 events read in total (156408ms).
[13:50:09.829] <TB2> INFO: 4115320 events read in total (182735ms).
[13:50:36.129] <TB2> INFO: 4703376 events read in total (209035ms).
[13:50:51.010] <TB2> INFO: 5025280 events read in total (223916ms).
[13:50:51.149] <TB2> INFO: Test took 224897ms.
[13:51:17.521] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 9.570754 .. 143.631757
[13:51:17.847] <TB2> INFO: Expecting 208000 events.
[13:51:27.626] <TB2> INFO: 208000 events read in total (9188ms).
[13:51:27.628] <TB2> INFO: Test took 10105ms.
[13:51:27.677] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 9 .. 153 (-1/-1) hits flags = 528 (plus default)
[13:51:27.690] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:51:27.690] <TB2> INFO: run 1 of 1
[13:51:27.968] <TB2> INFO: Expecting 4825600 events.
[13:51:54.142] <TB2> INFO: 574816 events read in total (25582ms).
[13:52:19.629] <TB2> INFO: 1149848 events read in total (51069ms).
[13:52:45.559] <TB2> INFO: 1724544 events read in total (76999ms).
[13:53:11.411] <TB2> INFO: 2299192 events read in total (102851ms).
[13:53:37.645] <TB2> INFO: 2873816 events read in total (129085ms).
[13:54:03.640] <TB2> INFO: 3448104 events read in total (155080ms).
[13:54:29.523] <TB2> INFO: 4022152 events read in total (180963ms).
[13:54:55.584] <TB2> INFO: 4595856 events read in total (207024ms).
[13:55:06.458] <TB2> INFO: 4825600 events read in total (217898ms).
[13:55:06.549] <TB2> INFO: Test took 218859ms.
[13:55:34.916] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 26.976740 .. 64.975243
[13:55:35.154] <TB2> INFO: Expecting 208000 events.
[13:55:45.118] <TB2> INFO: 208000 events read in total (9372ms).
[13:55:45.120] <TB2> INFO: Test took 10203ms.
[13:55:45.169] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 74 (-1/-1) hits flags = 528 (plus default)
[13:55:45.182] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:55:45.182] <TB2> INFO: run 1 of 1
[13:55:45.460] <TB2> INFO: Expecting 1963520 events.
[13:56:12.732] <TB2> INFO: 615416 events read in total (26681ms).
[13:56:39.214] <TB2> INFO: 1230504 events read in total (53163ms).
[13:57:06.467] <TB2> INFO: 1844840 events read in total (80416ms).
[13:57:11.959] <TB2> INFO: 1963520 events read in total (85908ms).
[13:57:12.012] <TB2> INFO: Test took 86830ms.
[13:57:26.511] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 28.560154 .. 48.989276
[13:57:26.752] <TB2> INFO: Expecting 208000 events.
[13:57:36.726] <TB2> INFO: 208000 events read in total (9383ms).
[13:57:36.727] <TB2> INFO: Test took 10215ms.
[13:57:36.796] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 18 .. 58 (-1/-1) hits flags = 528 (plus default)
[13:57:36.810] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:57:36.810] <TB2> INFO: run 1 of 1
[13:57:37.088] <TB2> INFO: Expecting 1364480 events.
[13:58:05.600] <TB2> INFO: 645624 events read in total (27920ms).
[13:58:33.889] <TB2> INFO: 1290168 events read in total (56209ms).
[13:58:37.511] <TB2> INFO: 1364480 events read in total (59831ms).
[13:58:37.544] <TB2> INFO: Test took 60733ms.
[13:58:49.900] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 26.153096 .. 54.668169
[13:58:50.189] <TB2> INFO: Expecting 208000 events.
[13:59:00.253] <TB2> INFO: 208000 events read in total (9473ms).
[13:59:00.254] <TB2> INFO: Test took 10353ms.
[13:59:00.306] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 64 (-1/-1) hits flags = 528 (plus default)
[13:59:00.322] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:59:00.322] <TB2> INFO: run 1 of 1
[13:59:00.600] <TB2> INFO: Expecting 1630720 events.
[13:59:28.371] <TB2> INFO: 634520 events read in total (27180ms).
[13:59:55.290] <TB2> INFO: 1269720 events read in total (54100ms).
[14:00:11.245] <TB2> INFO: 1630720 events read in total (70054ms).
[14:00:11.280] <TB2> INFO: Test took 70959ms.
[14:00:26.277] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:00:26.277] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:00:26.291] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:00:26.291] <TB2> INFO: run 1 of 1
[14:00:26.527] <TB2> INFO: Expecting 1364480 events.
[14:00:55.235] <TB2> INFO: 668752 events read in total (28117ms).
[14:01:23.901] <TB2> INFO: 1336328 events read in total (56783ms).
[14:01:25.493] <TB2> INFO: 1364480 events read in total (58375ms).
[14:01:25.532] <TB2> INFO: Test took 59241ms.
[14:01:38.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C0.dat
[14:01:38.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C1.dat
[14:01:38.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C2.dat
[14:01:38.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C3.dat
[14:01:38.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C4.dat
[14:01:38.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C5.dat
[14:01:38.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C6.dat
[14:01:38.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C7.dat
[14:01:38.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C8.dat
[14:01:38.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C9.dat
[14:01:38.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C10.dat
[14:01:38.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C11.dat
[14:01:38.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C12.dat
[14:01:38.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C13.dat
[14:01:38.672] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C14.dat
[14:01:38.673] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C15.dat
[14:01:38.673] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C0.dat
[14:01:38.677] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C1.dat
[14:01:38.682] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C2.dat
[14:01:38.687] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C3.dat
[14:01:38.692] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C4.dat
[14:01:38.697] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C5.dat
[14:01:38.701] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C6.dat
[14:01:38.706] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C7.dat
[14:01:38.711] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C8.dat
[14:01:38.716] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C9.dat
[14:01:38.720] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C10.dat
[14:01:38.725] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C11.dat
[14:01:38.730] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C12.dat
[14:01:38.734] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C13.dat
[14:01:38.739] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C14.dat
[14:01:38.744] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C15.dat
[14:01:38.749] <TB2> INFO: PixTestTrim::trimTest() done
[14:01:38.749] <TB2> INFO: vtrim: 127 120 122 128 159 117 138 132 120 128 107 132 118 120 115 131
[14:01:38.749] <TB2> INFO: vthrcomp: 118 122 132 110 131 124 131 122 132 122 122 127 114 113 115 120
[14:01:38.749] <TB2> INFO: vcal mean: 35.25 34.97 34.98 35.03 35.17 35.31 34.99 35.09 34.86 35.13 35.00 35.32 35.01 34.96 34.92 34.99
[14:01:38.749] <TB2> INFO: vcal RMS: 1.43 1.01 1.01 1.03 1.28 1.61 1.04 1.20 1.09 1.26 1.03 1.65 1.09 0.96 1.00 1.12
[14:01:38.749] <TB2> INFO: bits mean: 9.23 9.60 9.47 8.62 8.09 9.88 9.43 9.01 9.86 9.53 9.14 10.26 9.26 9.54 9.61 9.55
[14:01:38.749] <TB2> INFO: bits RMS: 2.83 2.69 2.72 2.51 2.39 2.65 2.62 2.58 2.70 2.70 2.81 2.47 2.68 2.59 2.65 2.49
[14:01:38.756] <TB2> INFO: ----------------------------------------------------------------------
[14:01:38.756] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:01:38.756] <TB2> INFO: ----------------------------------------------------------------------
[14:01:38.759] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:01:38.773] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:01:38.773] <TB2> INFO: run 1 of 1
[14:01:39.028] <TB2> INFO: Expecting 4160000 events.
[14:02:11.912] <TB2> INFO: 772370 events read in total (32292ms).
[14:02:44.040] <TB2> INFO: 1539385 events read in total (64420ms).
[14:03:16.168] <TB2> INFO: 2300120 events read in total (96549ms).
[14:03:48.354] <TB2> INFO: 3056795 events read in total (128734ms).
[14:04:20.992] <TB2> INFO: 3811070 events read in total (161372ms).
[14:04:36.004] <TB2> INFO: 4160000 events read in total (176384ms).
[14:04:36.078] <TB2> INFO: Test took 177306ms.
[14:05:00.792] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[14:05:00.805] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:05:00.805] <TB2> INFO: run 1 of 1
[14:05:01.041] <TB2> INFO: Expecting 5324800 events.
[14:05:32.245] <TB2> INFO: 685840 events read in total (30612ms).
[14:06:02.660] <TB2> INFO: 1369405 events read in total (61027ms).
[14:06:33.013] <TB2> INFO: 2050445 events read in total (91380ms).
[14:07:03.550] <TB2> INFO: 2729160 events read in total (121917ms).
[14:07:33.872] <TB2> INFO: 3405965 events read in total (152239ms).
[14:08:05.202] <TB2> INFO: 4081430 events read in total (183569ms).
[14:08:35.150] <TB2> INFO: 4756270 events read in total (213517ms).
[14:09:00.657] <TB2> INFO: 5324800 events read in total (239024ms).
[14:09:00.804] <TB2> INFO: Test took 239999ms.
[14:09:29.288] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 221 (-1/-1) hits flags = 528 (plus default)
[14:09:29.301] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:09:29.301] <TB2> INFO: run 1 of 1
[14:09:29.537] <TB2> INFO: Expecting 4617600 events.
[14:10:01.178] <TB2> INFO: 717795 events read in total (31049ms).
[14:10:32.127] <TB2> INFO: 1432580 events read in total (61998ms).
[14:11:03.081] <TB2> INFO: 2143080 events read in total (92952ms).
[14:11:35.417] <TB2> INFO: 2850835 events read in total (125288ms).
[14:12:05.944] <TB2> INFO: 3555925 events read in total (155815ms).
[14:12:36.917] <TB2> INFO: 4260435 events read in total (186788ms).
[14:12:52.812] <TB2> INFO: 4617600 events read in total (202683ms).
[14:12:52.890] <TB2> INFO: Test took 203589ms.
[14:13:20.930] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 220 (-1/-1) hits flags = 528 (plus default)
[14:13:20.945] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:13:20.945] <TB2> INFO: run 1 of 1
[14:13:21.180] <TB2> INFO: Expecting 4596800 events.
[14:13:53.071] <TB2> INFO: 719410 events read in total (31299ms).
[14:14:24.205] <TB2> INFO: 1436095 events read in total (62433ms).
[14:14:55.142] <TB2> INFO: 2148025 events read in total (93370ms).
[14:15:26.402] <TB2> INFO: 2857185 events read in total (124630ms).
[14:15:58.542] <TB2> INFO: 3563800 events read in total (156770ms).
[14:16:30.186] <TB2> INFO: 4269795 events read in total (188414ms).
[14:16:44.706] <TB2> INFO: 4596800 events read in total (202934ms).
[14:16:44.788] <TB2> INFO: Test took 203844ms.
[14:17:12.143] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 219 (-1/-1) hits flags = 528 (plus default)
[14:17:12.157] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:17:12.157] <TB2> INFO: run 1 of 1
[14:17:12.398] <TB2> INFO: Expecting 4576000 events.
[14:17:44.818] <TB2> INFO: 721085 events read in total (31828ms).
[14:18:16.224] <TB2> INFO: 1438950 events read in total (63234ms).
[14:18:47.017] <TB2> INFO: 2152390 events read in total (94027ms).
[14:19:18.163] <TB2> INFO: 2862940 events read in total (125173ms).
[14:19:49.489] <TB2> INFO: 3570545 events read in total (156499ms).
[14:20:21.297] <TB2> INFO: 4277865 events read in total (188307ms).
[14:20:34.565] <TB2> INFO: 4576000 events read in total (201575ms).
[14:20:34.652] <TB2> INFO: Test took 202495ms.
[14:20:58.992] <TB2> INFO: PixTestTrim::trimBitTest() done
[14:20:58.993] <TB2> INFO: PixTestTrim::doTest() done, duration: 2638 seconds
[14:20:58.993] <TB2> INFO: Decoding statistics:
[14:20:58.993] <TB2> INFO: General information:
[14:20:58.993] <TB2> INFO: 16bit words read: 0
[14:20:58.993] <TB2> INFO: valid events total: 0
[14:20:58.993] <TB2> INFO: empty events: 0
[14:20:58.993] <TB2> INFO: valid events with pixels: 0
[14:20:58.993] <TB2> INFO: valid pixel hits: 0
[14:20:58.993] <TB2> INFO: Event errors: 0
[14:20:58.993] <TB2> INFO: start marker: 0
[14:20:58.993] <TB2> INFO: stop marker: 0
[14:20:58.993] <TB2> INFO: overflow: 0
[14:20:58.993] <TB2> INFO: invalid 5bit words: 0
[14:20:58.993] <TB2> INFO: invalid XOR eye diagram: 0
[14:20:58.993] <TB2> INFO: frame (failed synchr.): 0
[14:20:58.993] <TB2> INFO: idle data (no TBM trl): 0
[14:20:58.993] <TB2> INFO: no data (only TBM hdr): 0
[14:20:58.993] <TB2> INFO: TBM errors: 0
[14:20:58.993] <TB2> INFO: flawed TBM headers: 0
[14:20:58.993] <TB2> INFO: flawed TBM trailers: 0
[14:20:58.993] <TB2> INFO: event ID mismatches: 0
[14:20:58.993] <TB2> INFO: ROC errors: 0
[14:20:58.993] <TB2> INFO: missing ROC header(s): 0
[14:20:58.993] <TB2> INFO: misplaced readback start: 0
[14:20:58.993] <TB2> INFO: Pixel decoding errors: 0
[14:20:58.993] <TB2> INFO: pixel data incomplete: 0
[14:20:58.993] <TB2> INFO: pixel address: 0
[14:20:58.993] <TB2> INFO: pulse height fill bit: 0
[14:20:58.993] <TB2> INFO: buffer corruption: 0
[14:20:59.797] <TB2> INFO: ######################################################################
[14:20:59.797] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[14:20:59.797] <TB2> INFO: ######################################################################
[14:21:00.034] <TB2> INFO: Expecting 41600 events.
[14:21:03.552] <TB2> INFO: 41600 events read in total (2926ms).
[14:21:03.553] <TB2> INFO: Test took 3755ms.
[14:21:03.993] <TB2> INFO: Expecting 41600 events.
[14:21:07.544] <TB2> INFO: 41600 events read in total (2959ms).
[14:21:07.545] <TB2> INFO: Test took 3790ms.
[14:21:07.852] <TB2> INFO: Expecting 41600 events.
[14:21:11.382] <TB2> INFO: 41600 events read in total (2936ms).
[14:21:11.383] <TB2> INFO: Test took 3814ms.
[14:21:11.672] <TB2> INFO: Expecting 41600 events.
[14:21:15.222] <TB2> INFO: 41600 events read in total (2958ms).
[14:21:15.223] <TB2> INFO: Test took 3816ms.
[14:21:15.512] <TB2> INFO: Expecting 41600 events.
[14:21:19.054] <TB2> INFO: 41600 events read in total (2950ms).
[14:21:19.054] <TB2> INFO: Test took 3807ms.
[14:21:19.344] <TB2> INFO: Expecting 41600 events.
[14:21:22.830] <TB2> INFO: 41600 events read in total (2894ms).
[14:21:22.831] <TB2> INFO: Test took 3753ms.
[14:21:23.120] <TB2> INFO: Expecting 41600 events.
[14:21:26.619] <TB2> INFO: 41600 events read in total (2908ms).
[14:21:26.620] <TB2> INFO: Test took 3765ms.
[14:21:26.911] <TB2> INFO: Expecting 41600 events.
[14:21:30.518] <TB2> INFO: 41600 events read in total (3015ms).
[14:21:30.519] <TB2> INFO: Test took 3873ms.
[14:21:30.809] <TB2> INFO: Expecting 41600 events.
[14:21:34.400] <TB2> INFO: 41600 events read in total (2999ms).
[14:21:34.401] <TB2> INFO: Test took 3858ms.
[14:21:34.693] <TB2> INFO: Expecting 41600 events.
[14:21:38.297] <TB2> INFO: 41600 events read in total (3012ms).
[14:21:38.298] <TB2> INFO: Test took 3870ms.
[14:21:38.590] <TB2> INFO: Expecting 41600 events.
[14:21:42.121] <TB2> INFO: 41600 events read in total (2939ms).
[14:21:42.122] <TB2> INFO: Test took 3797ms.
[14:21:42.410] <TB2> INFO: Expecting 41600 events.
[14:21:45.964] <TB2> INFO: 41600 events read in total (2962ms).
[14:21:45.965] <TB2> INFO: Test took 3819ms.
[14:21:46.254] <TB2> INFO: Expecting 41600 events.
[14:21:49.837] <TB2> INFO: 41600 events read in total (2992ms).
[14:21:49.838] <TB2> INFO: Test took 3849ms.
[14:21:50.127] <TB2> INFO: Expecting 41600 events.
[14:21:53.644] <TB2> INFO: 41600 events read in total (2925ms).
[14:21:53.646] <TB2> INFO: Test took 3783ms.
[14:21:53.936] <TB2> INFO: Expecting 41600 events.
[14:21:57.536] <TB2> INFO: 41600 events read in total (3008ms).
[14:21:57.537] <TB2> INFO: Test took 3866ms.
[14:21:57.827] <TB2> INFO: Expecting 41600 events.
[14:22:01.384] <TB2> INFO: 41600 events read in total (2965ms).
[14:22:01.385] <TB2> INFO: Test took 3824ms.
[14:22:01.678] <TB2> INFO: Expecting 41600 events.
[14:22:05.225] <TB2> INFO: 41600 events read in total (2956ms).
[14:22:05.226] <TB2> INFO: Test took 3817ms.
[14:22:05.515] <TB2> INFO: Expecting 41600 events.
[14:22:09.059] <TB2> INFO: 41600 events read in total (2952ms).
[14:22:09.060] <TB2> INFO: Test took 3810ms.
[14:22:09.350] <TB2> INFO: Expecting 41600 events.
[14:22:12.895] <TB2> INFO: 41600 events read in total (2953ms).
[14:22:12.896] <TB2> INFO: Test took 3811ms.
[14:22:13.203] <TB2> INFO: Expecting 41600 events.
[14:22:16.761] <TB2> INFO: 41600 events read in total (2966ms).
[14:22:16.762] <TB2> INFO: Test took 3839ms.
[14:22:17.053] <TB2> INFO: Expecting 41600 events.
[14:22:20.538] <TB2> INFO: 41600 events read in total (2893ms).
[14:22:20.538] <TB2> INFO: Test took 3750ms.
[14:22:20.829] <TB2> INFO: Expecting 41600 events.
[14:22:24.327] <TB2> INFO: 41600 events read in total (2907ms).
[14:22:24.327] <TB2> INFO: Test took 3763ms.
[14:22:24.628] <TB2> INFO: Expecting 41600 events.
[14:22:28.145] <TB2> INFO: 41600 events read in total (2925ms).
[14:22:28.145] <TB2> INFO: Test took 3793ms.
[14:22:28.435] <TB2> INFO: Expecting 41600 events.
[14:22:32.053] <TB2> INFO: 41600 events read in total (3026ms).
[14:22:32.054] <TB2> INFO: Test took 3885ms.
[14:22:32.353] <TB2> INFO: Expecting 41600 events.
[14:22:35.919] <TB2> INFO: 41600 events read in total (2975ms).
[14:22:35.920] <TB2> INFO: Test took 3839ms.
[14:22:36.212] <TB2> INFO: Expecting 41600 events.
[14:22:39.706] <TB2> INFO: 41600 events read in total (2902ms).
[14:22:39.707] <TB2> INFO: Test took 3760ms.
[14:22:39.996] <TB2> INFO: Expecting 41600 events.
[14:22:43.497] <TB2> INFO: 41600 events read in total (2909ms).
[14:22:43.498] <TB2> INFO: Test took 3767ms.
[14:22:43.787] <TB2> INFO: Expecting 41600 events.
[14:22:47.297] <TB2> INFO: 41600 events read in total (2918ms).
[14:22:47.298] <TB2> INFO: Test took 3776ms.
[14:22:47.595] <TB2> INFO: Expecting 41600 events.
[14:22:51.198] <TB2> INFO: 41600 events read in total (3011ms).
[14:22:51.198] <TB2> INFO: Test took 3874ms.
[14:22:51.488] <TB2> INFO: Expecting 2560 events.
[14:22:52.381] <TB2> INFO: 2560 events read in total (301ms).
[14:22:52.381] <TB2> INFO: Test took 1170ms.
[14:22:52.689] <TB2> INFO: Expecting 2560 events.
[14:22:53.581] <TB2> INFO: 2560 events read in total (300ms).
[14:22:53.581] <TB2> INFO: Test took 1199ms.
[14:22:53.890] <TB2> INFO: Expecting 2560 events.
[14:22:54.779] <TB2> INFO: 2560 events read in total (298ms).
[14:22:54.779] <TB2> INFO: Test took 1197ms.
[14:22:55.086] <TB2> INFO: Expecting 2560 events.
[14:22:55.968] <TB2> INFO: 2560 events read in total (290ms).
[14:22:55.968] <TB2> INFO: Test took 1188ms.
[14:22:56.277] <TB2> INFO: Expecting 2560 events.
[14:22:57.163] <TB2> INFO: 2560 events read in total (295ms).
[14:22:57.163] <TB2> INFO: Test took 1195ms.
[14:22:57.470] <TB2> INFO: Expecting 2560 events.
[14:22:58.352] <TB2> INFO: 2560 events read in total (290ms).
[14:22:58.352] <TB2> INFO: Test took 1188ms.
[14:22:58.661] <TB2> INFO: Expecting 2560 events.
[14:22:59.549] <TB2> INFO: 2560 events read in total (296ms).
[14:22:59.549] <TB2> INFO: Test took 1196ms.
[14:22:59.857] <TB2> INFO: Expecting 2560 events.
[14:23:00.749] <TB2> INFO: 2560 events read in total (300ms).
[14:23:00.749] <TB2> INFO: Test took 1199ms.
[14:23:01.056] <TB2> INFO: Expecting 2560 events.
[14:23:01.946] <TB2> INFO: 2560 events read in total (298ms).
[14:23:01.946] <TB2> INFO: Test took 1196ms.
[14:23:02.253] <TB2> INFO: Expecting 2560 events.
[14:23:03.135] <TB2> INFO: 2560 events read in total (290ms).
[14:23:03.135] <TB2> INFO: Test took 1188ms.
[14:23:03.443] <TB2> INFO: Expecting 2560 events.
[14:23:04.329] <TB2> INFO: 2560 events read in total (294ms).
[14:23:04.330] <TB2> INFO: Test took 1195ms.
[14:23:04.636] <TB2> INFO: Expecting 2560 events.
[14:23:05.517] <TB2> INFO: 2560 events read in total (289ms).
[14:23:05.518] <TB2> INFO: Test took 1188ms.
[14:23:05.825] <TB2> INFO: Expecting 2560 events.
[14:23:06.713] <TB2> INFO: 2560 events read in total (296ms).
[14:23:06.713] <TB2> INFO: Test took 1195ms.
[14:23:07.021] <TB2> INFO: Expecting 2560 events.
[14:23:07.911] <TB2> INFO: 2560 events read in total (299ms).
[14:23:07.912] <TB2> INFO: Test took 1199ms.
[14:23:08.219] <TB2> INFO: Expecting 2560 events.
[14:23:09.108] <TB2> INFO: 2560 events read in total (298ms).
[14:23:09.108] <TB2> INFO: Test took 1196ms.
[14:23:09.417] <TB2> INFO: Expecting 2560 events.
[14:23:10.311] <TB2> INFO: 2560 events read in total (303ms).
[14:23:10.311] <TB2> INFO: Test took 1202ms.
[14:23:10.314] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:23:10.619] <TB2> INFO: Expecting 655360 events.
[14:23:25.236] <TB2> INFO: 655360 events read in total (14025ms).
[14:23:25.250] <TB2> INFO: Expecting 655360 events.
[14:23:39.729] <TB2> INFO: 655360 events read in total (14075ms).
[14:23:39.749] <TB2> INFO: Expecting 655360 events.
[14:23:54.330] <TB2> INFO: 655360 events read in total (14178ms).
[14:23:54.357] <TB2> INFO: Expecting 655360 events.
[14:24:08.889] <TB2> INFO: 655360 events read in total (14129ms).
[14:24:08.916] <TB2> INFO: Expecting 655360 events.
[14:24:23.311] <TB2> INFO: 655360 events read in total (13992ms).
[14:24:23.340] <TB2> INFO: Expecting 655360 events.
[14:24:37.905] <TB2> INFO: 655360 events read in total (14162ms).
[14:24:37.941] <TB2> INFO: Expecting 655360 events.
[14:24:52.359] <TB2> INFO: 655360 events read in total (14015ms).
[14:24:52.398] <TB2> INFO: Expecting 655360 events.
[14:25:06.845] <TB2> INFO: 655360 events read in total (14044ms).
[14:25:06.901] <TB2> INFO: Expecting 655360 events.
[14:25:21.434] <TB2> INFO: 655360 events read in total (14130ms).
[14:25:21.482] <TB2> INFO: Expecting 655360 events.
[14:25:35.834] <TB2> INFO: 655360 events read in total (13949ms).
[14:25:35.886] <TB2> INFO: Expecting 655360 events.
[14:25:50.346] <TB2> INFO: 655360 events read in total (14057ms).
[14:25:50.419] <TB2> INFO: Expecting 655360 events.
[14:26:04.882] <TB2> INFO: 655360 events read in total (14060ms).
[14:26:04.947] <TB2> INFO: Expecting 655360 events.
[14:26:19.492] <TB2> INFO: 655360 events read in total (14142ms).
[14:26:19.570] <TB2> INFO: Expecting 655360 events.
[14:26:34.013] <TB2> INFO: 655360 events read in total (14040ms).
[14:26:34.086] <TB2> INFO: Expecting 655360 events.
[14:26:48.581] <TB2> INFO: 655360 events read in total (14092ms).
[14:26:48.691] <TB2> INFO: Expecting 655360 events.
[14:27:03.144] <TB2> INFO: 655360 events read in total (14050ms).
[14:27:03.229] <TB2> INFO: Test took 232915ms.
[14:27:03.325] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:27:03.583] <TB2> INFO: Expecting 655360 events.
[14:27:18.014] <TB2> INFO: 655360 events read in total (13839ms).
[14:27:18.027] <TB2> INFO: Expecting 655360 events.
[14:27:32.164] <TB2> INFO: 655360 events read in total (13734ms).
[14:27:32.184] <TB2> INFO: Expecting 655360 events.
[14:27:46.497] <TB2> INFO: 655360 events read in total (13909ms).
[14:27:46.517] <TB2> INFO: Expecting 655360 events.
[14:28:00.859] <TB2> INFO: 655360 events read in total (13939ms).
[14:28:00.888] <TB2> INFO: Expecting 655360 events.
[14:28:15.112] <TB2> INFO: 655360 events read in total (13820ms).
[14:28:15.151] <TB2> INFO: Expecting 655360 events.
[14:28:29.240] <TB2> INFO: 655360 events read in total (13686ms).
[14:28:29.273] <TB2> INFO: Expecting 655360 events.
[14:28:43.647] <TB2> INFO: 655360 events read in total (13971ms).
[14:28:43.697] <TB2> INFO: Expecting 655360 events.
[14:28:58.162] <TB2> INFO: 655360 events read in total (14062ms).
[14:28:58.216] <TB2> INFO: Expecting 655360 events.
[14:29:12.000] <TB2> INFO: 655360 events read in total (14381ms).
[14:29:13.048] <TB2> INFO: Expecting 655360 events.
[14:29:27.554] <TB2> INFO: 655360 events read in total (14103ms).
[14:29:27.604] <TB2> INFO: Expecting 655360 events.
[14:29:42.176] <TB2> INFO: 655360 events read in total (14169ms).
[14:29:42.232] <TB2> INFO: Expecting 655360 events.
[14:29:56.934] <TB2> INFO: 655360 events read in total (14299ms).
[14:29:57.013] <TB2> INFO: Expecting 655360 events.
[14:30:11.995] <TB2> INFO: 655360 events read in total (14578ms).
[14:30:12.091] <TB2> INFO: Expecting 655360 events.
[14:30:26.962] <TB2> INFO: 655360 events read in total (14468ms).
[14:30:27.033] <TB2> INFO: Expecting 655360 events.
[14:30:41.995] <TB2> INFO: 655360 events read in total (14558ms).
[14:30:42.080] <TB2> INFO: Expecting 655360 events.
[14:30:56.970] <TB2> INFO: 655360 events read in total (14487ms).
[14:30:57.052] <TB2> INFO: Test took 233727ms.
[14:30:57.218] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:30:57.224] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:30:57.231] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:30:57.236] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:30:57.243] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:30:57.249] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:30:57.255] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[14:30:57.261] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[14:30:57.268] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[14:30:57.274] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:30:57.280] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:30:57.286] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:30:57.292] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:30:57.298] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:30:57.304] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:30:57.311] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[14:30:57.317] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[14:30:57.323] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[14:30:57.329] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[14:30:57.335] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[14:30:57.342] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[14:30:57.348] <TB2> INFO: safety margin for low PH: adding 11, margin is now 31
[14:30:57.354] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:30:57.361] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:30:57.366] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:30:57.373] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:30:57.379] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:30:57.385] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:30:57.392] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:30:57.398] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:30:57.404] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[14:30:57.410] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[14:30:57.416] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[14:30:57.421] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[14:30:57.428] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[14:30:57.433] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:30:57.439] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:30:57.445] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:30:57.451] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:30:57.457] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:30:57.463] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:30:57.469] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:30:57.476] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:30:57.481] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:30:57.488] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:30:57.494] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:30:57.500] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:30:57.507] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:30:57.513] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[14:30:57.519] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[14:30:57.526] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[14:30:57.532] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:30:57.538] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:30:57.544] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:30:57.550] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:30:57.557] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:30:57.563] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:30:57.570] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:30:57.576] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[14:30:57.583] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[14:30:57.589] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[14:30:57.596] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[14:30:57.602] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[14:30:57.608] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:30:57.614] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:30:57.620] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:30:57.626] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:30:57.633] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[14:30:57.638] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[14:30:57.645] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:30:57.684] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C0.dat
[14:30:57.684] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C1.dat
[14:30:57.684] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C2.dat
[14:30:57.685] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C3.dat
[14:30:57.685] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C4.dat
[14:30:57.685] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C5.dat
[14:30:57.685] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C6.dat
[14:30:57.685] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C7.dat
[14:30:57.686] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C8.dat
[14:30:57.686] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C9.dat
[14:30:57.686] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C10.dat
[14:30:57.686] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C11.dat
[14:30:57.686] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C12.dat
[14:30:57.687] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C13.dat
[14:30:57.687] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C14.dat
[14:30:57.687] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C15.dat
[14:30:57.934] <TB2> INFO: Expecting 41600 events.
[14:31:01.121] <TB2> INFO: 41600 events read in total (2595ms).
[14:31:01.122] <TB2> INFO: Test took 3431ms.
[14:31:01.594] <TB2> INFO: Expecting 41600 events.
[14:31:04.704] <TB2> INFO: 41600 events read in total (2519ms).
[14:31:04.705] <TB2> INFO: Test took 3368ms.
[14:31:05.159] <TB2> INFO: Expecting 41600 events.
[14:31:08.311] <TB2> INFO: 41600 events read in total (2560ms).
[14:31:08.312] <TB2> INFO: Test took 3394ms.
[14:31:08.530] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:08.620] <TB2> INFO: Expecting 2560 events.
[14:31:09.514] <TB2> INFO: 2560 events read in total (302ms).
[14:31:09.515] <TB2> INFO: Test took 985ms.
[14:31:09.517] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:09.824] <TB2> INFO: Expecting 2560 events.
[14:31:10.719] <TB2> INFO: 2560 events read in total (303ms).
[14:31:10.719] <TB2> INFO: Test took 1202ms.
[14:31:10.723] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:11.027] <TB2> INFO: Expecting 2560 events.
[14:31:11.911] <TB2> INFO: 2560 events read in total (292ms).
[14:31:11.911] <TB2> INFO: Test took 1189ms.
[14:31:11.913] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:12.221] <TB2> INFO: Expecting 2560 events.
[14:31:13.111] <TB2> INFO: 2560 events read in total (298ms).
[14:31:13.111] <TB2> INFO: Test took 1198ms.
[14:31:13.115] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:13.419] <TB2> INFO: Expecting 2560 events.
[14:31:14.310] <TB2> INFO: 2560 events read in total (299ms).
[14:31:14.311] <TB2> INFO: Test took 1196ms.
[14:31:14.314] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:14.619] <TB2> INFO: Expecting 2560 events.
[14:31:15.510] <TB2> INFO: 2560 events read in total (299ms).
[14:31:15.511] <TB2> INFO: Test took 1197ms.
[14:31:15.513] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:15.817] <TB2> INFO: Expecting 2560 events.
[14:31:16.708] <TB2> INFO: 2560 events read in total (299ms).
[14:31:16.708] <TB2> INFO: Test took 1195ms.
[14:31:16.712] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:17.017] <TB2> INFO: Expecting 2560 events.
[14:31:17.905] <TB2> INFO: 2560 events read in total (297ms).
[14:31:17.905] <TB2> INFO: Test took 1193ms.
[14:31:17.908] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:18.212] <TB2> INFO: Expecting 2560 events.
[14:31:19.099] <TB2> INFO: 2560 events read in total (295ms).
[14:31:19.099] <TB2> INFO: Test took 1191ms.
[14:31:19.103] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:19.408] <TB2> INFO: Expecting 2560 events.
[14:31:20.296] <TB2> INFO: 2560 events read in total (297ms).
[14:31:20.296] <TB2> INFO: Test took 1194ms.
[14:31:20.298] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:20.604] <TB2> INFO: Expecting 2560 events.
[14:31:21.494] <TB2> INFO: 2560 events read in total (298ms).
[14:31:21.495] <TB2> INFO: Test took 1197ms.
[14:31:21.499] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:21.802] <TB2> INFO: Expecting 2560 events.
[14:31:22.686] <TB2> INFO: 2560 events read in total (292ms).
[14:31:22.687] <TB2> INFO: Test took 1188ms.
[14:31:22.690] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:22.995] <TB2> INFO: Expecting 2560 events.
[14:31:23.880] <TB2> INFO: 2560 events read in total (293ms).
[14:31:23.881] <TB2> INFO: Test took 1191ms.
[14:31:23.883] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:24.189] <TB2> INFO: Expecting 2560 events.
[14:31:25.069] <TB2> INFO: 2560 events read in total (288ms).
[14:31:25.070] <TB2> INFO: Test took 1187ms.
[14:31:25.073] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:25.378] <TB2> INFO: Expecting 2560 events.
[14:31:26.274] <TB2> INFO: 2560 events read in total (304ms).
[14:31:26.274] <TB2> INFO: Test took 1201ms.
[14:31:26.277] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:26.582] <TB2> INFO: Expecting 2560 events.
[14:31:27.475] <TB2> INFO: 2560 events read in total (301ms).
[14:31:27.476] <TB2> INFO: Test took 1199ms.
[14:31:27.481] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:27.784] <TB2> INFO: Expecting 2560 events.
[14:31:28.666] <TB2> INFO: 2560 events read in total (290ms).
[14:31:28.667] <TB2> INFO: Test took 1186ms.
[14:31:28.670] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:28.975] <TB2> INFO: Expecting 2560 events.
[14:31:29.862] <TB2> INFO: 2560 events read in total (296ms).
[14:31:29.862] <TB2> INFO: Test took 1192ms.
[14:31:29.866] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:30.170] <TB2> INFO: Expecting 2560 events.
[14:31:31.060] <TB2> INFO: 2560 events read in total (298ms).
[14:31:31.060] <TB2> INFO: Test took 1194ms.
[14:31:31.063] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:31.370] <TB2> INFO: Expecting 2560 events.
[14:31:32.258] <TB2> INFO: 2560 events read in total (297ms).
[14:31:32.259] <TB2> INFO: Test took 1196ms.
[14:31:32.262] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:32.566] <TB2> INFO: Expecting 2560 events.
[14:31:33.445] <TB2> INFO: 2560 events read in total (287ms).
[14:31:33.446] <TB2> INFO: Test took 1184ms.
[14:31:33.448] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:33.755] <TB2> INFO: Expecting 2560 events.
[14:31:34.648] <TB2> INFO: 2560 events read in total (301ms).
[14:31:34.649] <TB2> INFO: Test took 1201ms.
[14:31:34.652] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:34.957] <TB2> INFO: Expecting 2560 events.
[14:31:35.840] <TB2> INFO: 2560 events read in total (291ms).
[14:31:35.841] <TB2> INFO: Test took 1189ms.
[14:31:35.845] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:36.149] <TB2> INFO: Expecting 2560 events.
[14:31:37.032] <TB2> INFO: 2560 events read in total (291ms).
[14:31:37.032] <TB2> INFO: Test took 1187ms.
[14:31:37.036] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:37.340] <TB2> INFO: Expecting 2560 events.
[14:31:38.239] <TB2> INFO: 2560 events read in total (307ms).
[14:31:38.239] <TB2> INFO: Test took 1203ms.
[14:31:38.244] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:38.547] <TB2> INFO: Expecting 2560 events.
[14:31:39.442] <TB2> INFO: 2560 events read in total (303ms).
[14:31:39.442] <TB2> INFO: Test took 1199ms.
[14:31:39.445] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:39.751] <TB2> INFO: Expecting 2560 events.
[14:31:40.647] <TB2> INFO: 2560 events read in total (304ms).
[14:31:40.647] <TB2> INFO: Test took 1204ms.
[14:31:40.651] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:40.956] <TB2> INFO: Expecting 2560 events.
[14:31:41.847] <TB2> INFO: 2560 events read in total (299ms).
[14:31:41.848] <TB2> INFO: Test took 1198ms.
[14:31:41.850] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:42.156] <TB2> INFO: Expecting 2560 events.
[14:31:43.044] <TB2> INFO: 2560 events read in total (296ms).
[14:31:43.044] <TB2> INFO: Test took 1195ms.
[14:31:43.048] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:43.352] <TB2> INFO: Expecting 2560 events.
[14:31:44.239] <TB2> INFO: 2560 events read in total (295ms).
[14:31:44.239] <TB2> INFO: Test took 1191ms.
[14:31:44.241] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:44.548] <TB2> INFO: Expecting 2560 events.
[14:31:45.430] <TB2> INFO: 2560 events read in total (291ms).
[14:31:45.431] <TB2> INFO: Test took 1190ms.
[14:31:45.434] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:31:45.739] <TB2> INFO: Expecting 2560 events.
[14:31:46.622] <TB2> INFO: 2560 events read in total (292ms).
[14:31:46.622] <TB2> INFO: Test took 1190ms.
[14:31:47.086] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 647 seconds
[14:31:47.086] <TB2> INFO: PH scale (per ROC): 47 29 51 48 50 41 36 31 52 48 35 41 41 40 48 29
[14:31:47.086] <TB2> INFO: PH offset (per ROC): 89 107 123 112 128 112 107 96 119 130 110 109 93 112 108 101
[14:31:47.094] <TB2> INFO: Decoding statistics:
[14:31:47.094] <TB2> INFO: General information:
[14:31:47.094] <TB2> INFO: 16bit words read: 127884
[14:31:47.094] <TB2> INFO: valid events total: 20480
[14:31:47.094] <TB2> INFO: empty events: 17978
[14:31:47.094] <TB2> INFO: valid events with pixels: 2502
[14:31:47.094] <TB2> INFO: valid pixel hits: 2502
[14:31:47.094] <TB2> INFO: Event errors: 0
[14:31:47.094] <TB2> INFO: start marker: 0
[14:31:47.094] <TB2> INFO: stop marker: 0
[14:31:47.094] <TB2> INFO: overflow: 0
[14:31:47.094] <TB2> INFO: invalid 5bit words: 0
[14:31:47.094] <TB2> INFO: invalid XOR eye diagram: 0
[14:31:47.094] <TB2> INFO: frame (failed synchr.): 0
[14:31:47.094] <TB2> INFO: idle data (no TBM trl): 0
[14:31:47.094] <TB2> INFO: no data (only TBM hdr): 0
[14:31:47.094] <TB2> INFO: TBM errors: 0
[14:31:47.094] <TB2> INFO: flawed TBM headers: 0
[14:31:47.094] <TB2> INFO: flawed TBM trailers: 0
[14:31:47.095] <TB2> INFO: event ID mismatches: 0
[14:31:47.095] <TB2> INFO: ROC errors: 0
[14:31:47.095] <TB2> INFO: missing ROC header(s): 0
[14:31:47.095] <TB2> INFO: misplaced readback start: 0
[14:31:47.095] <TB2> INFO: Pixel decoding errors: 0
[14:31:47.095] <TB2> INFO: pixel data incomplete: 0
[14:31:47.095] <TB2> INFO: pixel address: 0
[14:31:47.095] <TB2> INFO: pulse height fill bit: 0
[14:31:47.095] <TB2> INFO: buffer corruption: 0
[14:31:47.261] <TB2> INFO: ######################################################################
[14:31:47.261] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[14:31:47.261] <TB2> INFO: ######################################################################
[14:31:47.275] <TB2> INFO: scanning low vcal = 10
[14:31:47.512] <TB2> INFO: Expecting 41600 events.
[14:31:51.077] <TB2> INFO: 41600 events read in total (2974ms).
[14:31:51.077] <TB2> INFO: Test took 3802ms.
[14:31:51.080] <TB2> INFO: scanning low vcal = 20
[14:31:51.376] <TB2> INFO: Expecting 41600 events.
[14:31:54.959] <TB2> INFO: 41600 events read in total (2992ms).
[14:31:54.960] <TB2> INFO: Test took 3880ms.
[14:31:54.963] <TB2> INFO: scanning low vcal = 30
[14:31:55.258] <TB2> INFO: Expecting 41600 events.
[14:31:58.935] <TB2> INFO: 41600 events read in total (3086ms).
[14:31:58.936] <TB2> INFO: Test took 3972ms.
[14:31:58.939] <TB2> INFO: scanning low vcal = 40
[14:31:59.216] <TB2> INFO: Expecting 41600 events.
[14:32:03.147] <TB2> INFO: 41600 events read in total (3339ms).
[14:32:03.148] <TB2> INFO: Test took 4209ms.
[14:32:03.152] <TB2> INFO: scanning low vcal = 50
[14:32:03.428] <TB2> INFO: Expecting 41600 events.
[14:32:07.465] <TB2> INFO: 41600 events read in total (3446ms).
[14:32:07.466] <TB2> INFO: Test took 4314ms.
[14:32:07.469] <TB2> INFO: scanning low vcal = 60
[14:32:07.746] <TB2> INFO: Expecting 41600 events.
[14:32:11.682] <TB2> INFO: 41600 events read in total (3345ms).
[14:32:11.683] <TB2> INFO: Test took 4213ms.
[14:32:11.686] <TB2> INFO: scanning low vcal = 70
[14:32:11.963] <TB2> INFO: Expecting 41600 events.
[14:32:15.964] <TB2> INFO: 41600 events read in total (3410ms).
[14:32:15.968] <TB2> INFO: Test took 4282ms.
[14:32:15.971] <TB2> INFO: scanning low vcal = 80
[14:32:16.257] <TB2> INFO: Expecting 41600 events.
[14:32:20.297] <TB2> INFO: 41600 events read in total (3449ms).
[14:32:20.299] <TB2> INFO: Test took 4327ms.
[14:32:20.305] <TB2> INFO: scanning low vcal = 90
[14:32:20.592] <TB2> INFO: Expecting 41600 events.
[14:32:24.581] <TB2> INFO: 41600 events read in total (3398ms).
[14:32:24.582] <TB2> INFO: Test took 4277ms.
[14:32:24.588] <TB2> INFO: scanning low vcal = 100
[14:32:24.862] <TB2> INFO: Expecting 41600 events.
[14:32:28.894] <TB2> INFO: 41600 events read in total (3440ms).
[14:32:28.894] <TB2> INFO: Test took 4306ms.
[14:32:28.897] <TB2> INFO: scanning low vcal = 110
[14:32:29.174] <TB2> INFO: Expecting 41600 events.
[14:32:33.207] <TB2> INFO: 41600 events read in total (3441ms).
[14:32:33.207] <TB2> INFO: Test took 4310ms.
[14:32:33.210] <TB2> INFO: scanning low vcal = 120
[14:32:33.525] <TB2> INFO: Expecting 41600 events.
[14:32:37.547] <TB2> INFO: 41600 events read in total (3431ms).
[14:32:37.548] <TB2> INFO: Test took 4338ms.
[14:32:37.551] <TB2> INFO: scanning low vcal = 130
[14:32:37.828] <TB2> INFO: Expecting 41600 events.
[14:32:41.877] <TB2> INFO: 41600 events read in total (3458ms).
[14:32:41.878] <TB2> INFO: Test took 4327ms.
[14:32:41.881] <TB2> INFO: scanning low vcal = 140
[14:32:42.158] <TB2> INFO: Expecting 41600 events.
[14:32:46.129] <TB2> INFO: 41600 events read in total (3379ms).
[14:32:46.130] <TB2> INFO: Test took 4248ms.
[14:32:46.133] <TB2> INFO: scanning low vcal = 150
[14:32:46.449] <TB2> INFO: Expecting 41600 events.
[14:32:50.475] <TB2> INFO: 41600 events read in total (3435ms).
[14:32:50.476] <TB2> INFO: Test took 4343ms.
[14:32:50.480] <TB2> INFO: scanning low vcal = 160
[14:32:50.756] <TB2> INFO: Expecting 41600 events.
[14:32:54.784] <TB2> INFO: 41600 events read in total (3436ms).
[14:32:54.785] <TB2> INFO: Test took 4305ms.
[14:32:54.788] <TB2> INFO: scanning low vcal = 170
[14:32:55.064] <TB2> INFO: Expecting 41600 events.
[14:32:59.064] <TB2> INFO: 41600 events read in total (3408ms).
[14:32:59.065] <TB2> INFO: Test took 4277ms.
[14:32:59.071] <TB2> INFO: scanning low vcal = 180
[14:32:59.345] <TB2> INFO: Expecting 41600 events.
[14:33:03.295] <TB2> INFO: 41600 events read in total (3358ms).
[14:33:03.296] <TB2> INFO: Test took 4225ms.
[14:33:03.300] <TB2> INFO: scanning low vcal = 190
[14:33:03.576] <TB2> INFO: Expecting 41600 events.
[14:33:07.527] <TB2> INFO: 41600 events read in total (3359ms).
[14:33:07.528] <TB2> INFO: Test took 4228ms.
[14:33:07.531] <TB2> INFO: scanning low vcal = 200
[14:33:07.808] <TB2> INFO: Expecting 41600 events.
[14:33:11.762] <TB2> INFO: 41600 events read in total (3363ms).
[14:33:11.763] <TB2> INFO: Test took 4232ms.
[14:33:11.766] <TB2> INFO: scanning low vcal = 210
[14:33:12.043] <TB2> INFO: Expecting 41600 events.
[14:33:15.000] <TB2> INFO: 41600 events read in total (3365ms).
[14:33:15.001] <TB2> INFO: Test took 4234ms.
[14:33:16.005] <TB2> INFO: scanning low vcal = 220
[14:33:16.282] <TB2> INFO: Expecting 41600 events.
[14:33:20.242] <TB2> INFO: 41600 events read in total (3368ms).
[14:33:20.242] <TB2> INFO: Test took 4237ms.
[14:33:20.246] <TB2> INFO: scanning low vcal = 230
[14:33:20.522] <TB2> INFO: Expecting 41600 events.
[14:33:24.478] <TB2> INFO: 41600 events read in total (3364ms).
[14:33:24.479] <TB2> INFO: Test took 4233ms.
[14:33:24.482] <TB2> INFO: scanning low vcal = 240
[14:33:24.759] <TB2> INFO: Expecting 41600 events.
[14:33:28.713] <TB2> INFO: 41600 events read in total (3362ms).
[14:33:28.714] <TB2> INFO: Test took 4232ms.
[14:33:28.718] <TB2> INFO: scanning low vcal = 250
[14:33:28.995] <TB2> INFO: Expecting 41600 events.
[14:33:32.951] <TB2> INFO: 41600 events read in total (3364ms).
[14:33:32.952] <TB2> INFO: Test took 4234ms.
[14:33:32.957] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[14:33:33.232] <TB2> INFO: Expecting 41600 events.
[14:33:37.198] <TB2> INFO: 41600 events read in total (3374ms).
[14:33:37.198] <TB2> INFO: Test took 4241ms.
[14:33:37.202] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[14:33:37.479] <TB2> INFO: Expecting 41600 events.
[14:33:41.439] <TB2> INFO: 41600 events read in total (3368ms).
[14:33:41.440] <TB2> INFO: Test took 4238ms.
[14:33:41.444] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[14:33:41.721] <TB2> INFO: Expecting 41600 events.
[14:33:45.679] <TB2> INFO: 41600 events read in total (3367ms).
[14:33:45.680] <TB2> INFO: Test took 4236ms.
[14:33:45.683] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[14:33:45.960] <TB2> INFO: Expecting 41600 events.
[14:33:49.918] <TB2> INFO: 41600 events read in total (3366ms).
[14:33:49.918] <TB2> INFO: Test took 4234ms.
[14:33:49.921] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[14:33:50.199] <TB2> INFO: Expecting 41600 events.
[14:33:54.163] <TB2> INFO: 41600 events read in total (3372ms).
[14:33:54.164] <TB2> INFO: Test took 4242ms.
[14:33:54.577] <TB2> INFO: PixTestGainPedestal::measure() done
[14:34:28.022] <TB2> INFO: PixTestGainPedestal::fit() done
[14:34:28.022] <TB2> INFO: non-linearity mean: 0.976 1.058 0.982 0.981 0.979 0.953 0.926 1.002 0.983 0.984 0.934 0.948 0.971 0.920 0.973 0.959
[14:34:28.022] <TB2> INFO: non-linearity RMS: 0.024 0.163 0.003 0.004 0.004 0.064 0.092 0.197 0.003 0.003 0.128 0.133 0.172 0.091 0.012 0.165
[14:34:28.022] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C0.dat
[14:34:28.036] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C1.dat
[14:34:28.050] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C2.dat
[14:34:28.063] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C3.dat
[14:34:28.077] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C4.dat
[14:34:28.090] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C5.dat
[14:34:28.104] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C6.dat
[14:34:28.117] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C7.dat
[14:34:28.131] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C8.dat
[14:34:28.144] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C9.dat
[14:34:28.157] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C10.dat
[14:34:28.171] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C11.dat
[14:34:28.185] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C12.dat
[14:34:28.198] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C13.dat
[14:34:28.212] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C14.dat
[14:34:28.225] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C15.dat
[14:34:28.238] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 160 seconds
[14:34:28.238] <TB2> INFO: Decoding statistics:
[14:34:28.238] <TB2> INFO: General information:
[14:34:28.238] <TB2> INFO: 16bit words read: 3323466
[14:34:28.238] <TB2> INFO: valid events total: 332800
[14:34:28.238] <TB2> INFO: empty events: 539
[14:34:28.238] <TB2> INFO: valid events with pixels: 332261
[14:34:28.238] <TB2> INFO: valid pixel hits: 663333
[14:34:28.238] <TB2> INFO: Event errors: 0
[14:34:28.238] <TB2> INFO: start marker: 0
[14:34:28.238] <TB2> INFO: stop marker: 0
[14:34:28.238] <TB2> INFO: overflow: 0
[14:34:28.238] <TB2> INFO: invalid 5bit words: 0
[14:34:28.238] <TB2> INFO: invalid XOR eye diagram: 0
[14:34:28.238] <TB2> INFO: frame (failed synchr.): 0
[14:34:28.239] <TB2> INFO: idle data (no TBM trl): 0
[14:34:28.239] <TB2> INFO: no data (only TBM hdr): 0
[14:34:28.239] <TB2> INFO: TBM errors: 0
[14:34:28.239] <TB2> INFO: flawed TBM headers: 0
[14:34:28.239] <TB2> INFO: flawed TBM trailers: 0
[14:34:28.239] <TB2> INFO: event ID mismatches: 0
[14:34:28.239] <TB2> INFO: ROC errors: 0
[14:34:28.239] <TB2> INFO: missing ROC header(s): 0
[14:34:28.239] <TB2> INFO: misplaced readback start: 0
[14:34:28.239] <TB2> INFO: Pixel decoding errors: 0
[14:34:28.239] <TB2> INFO: pixel data incomplete: 0
[14:34:28.239] <TB2> INFO: pixel address: 0
[14:34:28.239] <TB2> INFO: pulse height fill bit: 0
[14:34:28.239] <TB2> INFO: buffer corruption: 0
[14:34:28.254] <TB2> INFO: Decoding statistics:
[14:34:28.254] <TB2> INFO: General information:
[14:34:28.254] <TB2> INFO: 16bit words read: 3452886
[14:34:28.254] <TB2> INFO: valid events total: 353536
[14:34:28.254] <TB2> INFO: empty events: 18773
[14:34:28.254] <TB2> INFO: valid events with pixels: 334763
[14:34:28.254] <TB2> INFO: valid pixel hits: 665835
[14:34:28.254] <TB2> INFO: Event errors: 0
[14:34:28.254] <TB2> INFO: start marker: 0
[14:34:28.255] <TB2> INFO: stop marker: 0
[14:34:28.255] <TB2> INFO: overflow: 0
[14:34:28.255] <TB2> INFO: invalid 5bit words: 0
[14:34:28.255] <TB2> INFO: invalid XOR eye diagram: 0
[14:34:28.255] <TB2> INFO: frame (failed synchr.): 0
[14:34:28.255] <TB2> INFO: idle data (no TBM trl): 0
[14:34:28.255] <TB2> INFO: no data (only TBM hdr): 0
[14:34:28.255] <TB2> INFO: TBM errors: 0
[14:34:28.255] <TB2> INFO: flawed TBM headers: 0
[14:34:28.255] <TB2> INFO: flawed TBM trailers: 0
[14:34:28.255] <TB2> INFO: event ID mismatches: 0
[14:34:28.255] <TB2> INFO: ROC errors: 0
[14:34:28.255] <TB2> INFO: missing ROC header(s): 0
[14:34:28.255] <TB2> INFO: misplaced readback start: 0
[14:34:28.255] <TB2> INFO: Pixel decoding errors: 0
[14:34:28.255] <TB2> INFO: pixel data incomplete: 0
[14:34:28.255] <TB2> INFO: pixel address: 0
[14:34:28.255] <TB2> INFO: pulse height fill bit: 0
[14:34:28.255] <TB2> INFO: buffer corruption: 0
[14:34:28.255] <TB2> INFO: enter test to run
[14:34:28.255] <TB2> INFO: test: exit no parameter change
[14:34:28.378] <TB2> QUIET: Connection to board 149 closed.
[14:34:28.379] <TB2> INFO: pXar: this is the end, my friend