[11:33:02.217] <TB2> INFO: *** Welcome to pxar ***
[11:33:02.217] <TB2> INFO: *** Today: 2016/10/22
[11:33:02.224] <TB2> INFO: *** Version: c8ba-dirty
[11:33:02.224] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C15.dat
[11:33:02.224] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//tbmParameters_C1b.dat
[11:33:02.224] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//defaultMaskFile.dat
[11:33:02.224] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters_C15.dat
[11:33:02.288] <TB2> INFO: clk: 4
[11:33:02.288] <TB2> INFO: ctr: 4
[11:33:02.288] <TB2> INFO: sda: 19
[11:33:02.288] <TB2> INFO: tin: 9
[11:33:02.288] <TB2> INFO: level: 15
[11:33:02.288] <TB2> INFO: triggerdelay: 0
[11:33:02.288] <TB2> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[11:33:02.288] <TB2> INFO: Log level: INFO
[11:33:02.297] <TB2> INFO: Found DTB DTB_WWXUD2
[11:33:02.305] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[11:33:02.307] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[11:33:02.309] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[11:33:03.805] <TB2> INFO: DUT info:
[11:33:03.805] <TB2> INFO: The DUT currently contains the following objects:
[11:33:03.805] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[11:33:03.805] <TB2> INFO: TBM Core alpha (0): 7 registers set
[11:33:03.805] <TB2> INFO: TBM Core beta (1): 7 registers set
[11:33:03.805] <TB2> INFO: TBM Core alpha (2): 7 registers set
[11:33:03.805] <TB2> INFO: TBM Core beta (3): 7 registers set
[11:33:03.805] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:33:03.805] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:33:03.805] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:33:03.805] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:33:03.805] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:33:03.805] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:33:03.805] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:33:03.805] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:33:03.805] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:33:03.805] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:33:03.805] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:33:03.805] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:33:03.805] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:33:03.806] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:33:03.806] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:33:03.806] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:33:03.806] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:33:04.207] <TB2> INFO: enter 'restricted' command line mode
[11:33:04.207] <TB2> INFO: enter test to run
[11:33:04.207] <TB2> INFO: test: pretest no parameter change
[11:33:04.207] <TB2> INFO: running: pretest
[11:33:04.215] <TB2> INFO: ######################################################################
[11:33:04.215] <TB2> INFO: PixTestPretest::doTest()
[11:33:04.215] <TB2> INFO: ######################################################################
[11:33:04.216] <TB2> INFO: ----------------------------------------------------------------------
[11:33:04.216] <TB2> INFO: PixTestPretest::programROC()
[11:33:04.216] <TB2> INFO: ----------------------------------------------------------------------
[11:33:22.230] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:33:22.230] <TB2> INFO: IA differences per ROC: 16.9 17.7 20.1 17.7 19.3 19.3 22.5 18.5 22.5 20.1 21.7 16.1 20.9 16.1 22.5 22.5
[11:33:22.306] <TB2> INFO: ----------------------------------------------------------------------
[11:33:22.306] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:33:22.306] <TB2> INFO: ----------------------------------------------------------------------
[11:33:29.010] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 390.7 mA = 24.4187 mA/ROC
[11:33:29.010] <TB2> INFO: i(loss) [mA/ROC]: 20.1 19.3 19.3 20.1 20.1 19.3 19.3 19.3 19.3 19.3 18.5 19.3 18.5 19.3 19.3 18.5
[11:33:29.045] <TB2> INFO: ----------------------------------------------------------------------
[11:33:29.045] <TB2> INFO: PixTestPretest::findTiming()
[11:33:29.045] <TB2> INFO: ----------------------------------------------------------------------
[11:33:29.045] <TB2> INFO: PixTestCmd::init()

[11:34:01.058] <TB2> INFO: TBM phases: 160MHz: 7, 400MHz: 5, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[11:34:01.058] <TB2> INFO: (success/tries = 100/100), width = 3
[11:34:02.562] <TB2> INFO: ----------------------------------------------------------------------
[11:34:02.562] <TB2> INFO: PixTestPretest::findWorkingPixel()
[11:34:02.562] <TB2> INFO: ----------------------------------------------------------------------
[11:34:02.656] <TB2> INFO: Expecting 231680 events.
[11:34:12.608] <TB2> INFO: 231680 events read in total (9360ms).
[11:34:12.617] <TB2> INFO: Test took 10051ms.
[11:34:12.862] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:34:12.896] <TB2> INFO: ----------------------------------------------------------------------
[11:34:12.896] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[11:34:12.897] <TB2> INFO: ----------------------------------------------------------------------
[11:34:12.992] <TB2> INFO: Expecting 231680 events.
[11:34:23.103] <TB2> INFO: 231680 events read in total (9519ms).
[11:34:23.113] <TB2> INFO: Test took 10211ms.
[11:34:23.381] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[11:34:23.381] <TB2> INFO: CalDel: 93 94 107 107 85 115 104 95 109 100 106 102 105 108 111 117
[11:34:23.381] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[11:34:23.385] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C0.dat
[11:34:23.385] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C1.dat
[11:34:23.386] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C2.dat
[11:34:23.386] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C3.dat
[11:34:23.386] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C4.dat
[11:34:23.386] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C5.dat
[11:34:23.386] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C6.dat
[11:34:23.386] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C7.dat
[11:34:23.387] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C8.dat
[11:34:23.387] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C9.dat
[11:34:23.387] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C10.dat
[11:34:23.387] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C11.dat
[11:34:23.387] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C12.dat
[11:34:23.387] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C13.dat
[11:34:23.387] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C14.dat
[11:34:23.388] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C15.dat
[11:34:23.388] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//tbmParameters_C0a.dat
[11:34:23.388] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//tbmParameters_C0b.dat
[11:34:23.388] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//tbmParameters_C1a.dat
[11:34:23.388] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//tbmParameters_C1b.dat
[11:34:23.388] <TB2> INFO: PixTestPretest::doTest() done, duration: 79 seconds
[11:34:23.444] <TB2> INFO: enter test to run
[11:34:23.444] <TB2> INFO: test: FullTest no parameter change
[11:34:23.444] <TB2> INFO: running: fulltest
[11:34:23.444] <TB2> INFO: ######################################################################
[11:34:23.444] <TB2> INFO: PixTestFullTest::doTest()
[11:34:23.444] <TB2> INFO: ######################################################################
[11:34:23.445] <TB2> INFO: ######################################################################
[11:34:23.445] <TB2> INFO: PixTestAlive::doTest()
[11:34:23.445] <TB2> INFO: ######################################################################
[11:34:23.446] <TB2> INFO: ----------------------------------------------------------------------
[11:34:23.446] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:34:23.446] <TB2> INFO: ----------------------------------------------------------------------
[11:34:23.732] <TB2> INFO: Expecting 41600 events.
[11:34:27.301] <TB2> INFO: 41600 events read in total (2977ms).
[11:34:27.302] <TB2> INFO: Test took 3854ms.
[11:34:27.535] <TB2> INFO: PixTestAlive::aliveTest() done
[11:34:27.535] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:34:27.537] <TB2> INFO: ----------------------------------------------------------------------
[11:34:27.537] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:34:27.537] <TB2> INFO: ----------------------------------------------------------------------
[11:34:27.779] <TB2> INFO: Expecting 41600 events.
[11:34:30.782] <TB2> INFO: 41600 events read in total (2411ms).
[11:34:30.782] <TB2> INFO: Test took 3243ms.
[11:34:30.783] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:34:31.016] <TB2> INFO: PixTestAlive::maskTest() done
[11:34:31.016] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:34:31.018] <TB2> INFO: ----------------------------------------------------------------------
[11:34:31.018] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:34:31.018] <TB2> INFO: ----------------------------------------------------------------------
[11:34:31.256] <TB2> INFO: Expecting 41600 events.
[11:34:34.751] <TB2> INFO: 41600 events read in total (2903ms).
[11:34:34.752] <TB2> INFO: Test took 3732ms.


[11:34:34.983] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[11:34:34.983] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:34:34.983] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:34:34.983] <TB2> INFO: Decoding statistics:
[11:34:34.983] <TB2> INFO: General information:
[11:34:34.983] <TB2> INFO: 16bit words read: 0
[11:34:34.983] <TB2> INFO: valid events total: 0
[11:34:34.983] <TB2> INFO: empty events: 0
[11:34:34.983] <TB2> INFO: valid events with pixels: 0
[11:34:34.983] <TB2> INFO: valid pixel hits: 0
[11:34:34.983] <TB2> INFO: Event errors: 0
[11:34:34.983] <TB2> INFO: start marker: 0
[11:34:34.983] <TB2> INFO: stop marker: 0
[11:34:34.983] <TB2> INFO: overflow: 0
[11:34:34.983] <TB2> INFO: invalid 5bit words: 0
[11:34:34.983] <TB2> INFO: invalid XOR eye diagram: 0
[11:34:34.983] <TB2> INFO: frame (failed synchr.): 0
[11:34:34.983] <TB2> INFO: idle data (no TBM trl): 0
[11:34:34.983] <TB2> INFO: no data (only TBM hdr): 0
[11:34:34.983] <TB2> INFO: TBM errors: 0
[11:34:34.983] <TB2> INFO: flawed TBM headers: 0
[11:34:34.983] <TB2> INFO: flawed TBM trailers: 0
[11:34:34.983] <TB2> INFO: event ID mismatches: 0
[11:34:34.983] <TB2> INFO: ROC errors: 0
[11:34:34.983] <TB2> INFO: missing ROC header(s): 0
[11:34:34.984] <TB2> INFO: misplaced readback start: 0
[11:34:34.984] <TB2> INFO: Pixel decoding errors: 0
[11:34:34.984] <TB2> INFO: pixel data incomplete: 0
[11:34:34.984] <TB2> INFO: pixel address: 0
[11:34:34.984] <TB2> INFO: pulse height fill bit: 0
[11:34:34.984] <TB2> INFO: buffer corruption: 0
[11:34:34.988] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C15.dat
[11:34:34.988] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[11:34:34.988] <TB2> INFO: ######################################################################
[11:34:34.988] <TB2> INFO: PixTestReadback::doTest()
[11:34:34.988] <TB2> INFO: ######################################################################
[11:34:34.988] <TB2> INFO: ----------------------------------------------------------------------
[11:34:34.988] <TB2> INFO: PixTestReadback::CalibrateVd()
[11:34:34.988] <TB2> INFO: ----------------------------------------------------------------------
[11:34:44.956] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C0.dat
[11:34:44.956] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C1.dat
[11:34:44.956] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C2.dat
[11:34:44.956] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C3.dat
[11:34:44.957] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C4.dat
[11:34:44.957] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C5.dat
[11:34:44.957] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C6.dat
[11:34:44.957] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C7.dat
[11:34:44.957] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C8.dat
[11:34:44.957] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C9.dat
[11:34:44.957] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C10.dat
[11:34:44.957] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C11.dat
[11:34:44.957] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C12.dat
[11:34:44.957] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C13.dat
[11:34:44.957] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C14.dat
[11:34:44.957] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C15.dat
[11:34:44.990] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:34:44.990] <TB2> INFO: ----------------------------------------------------------------------
[11:34:44.990] <TB2> INFO: PixTestReadback::CalibrateVa()
[11:34:44.990] <TB2> INFO: ----------------------------------------------------------------------
[11:34:54.912] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C0.dat
[11:34:54.912] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C1.dat
[11:34:54.912] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C2.dat
[11:34:54.912] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C3.dat
[11:34:54.912] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C4.dat
[11:34:54.912] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C5.dat
[11:34:54.912] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C6.dat
[11:34:54.912] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C7.dat
[11:34:54.912] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C8.dat
[11:34:54.912] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C9.dat
[11:34:54.912] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C10.dat
[11:34:54.912] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C11.dat
[11:34:54.913] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C12.dat
[11:34:54.913] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C13.dat
[11:34:54.913] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C14.dat
[11:34:54.913] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C15.dat
[11:34:54.944] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:34:54.944] <TB2> INFO: ----------------------------------------------------------------------
[11:34:54.944] <TB2> INFO: PixTestReadback::readbackVbg()
[11:34:54.944] <TB2> INFO: ----------------------------------------------------------------------
[11:35:02.615] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:35:02.615] <TB2> INFO: ----------------------------------------------------------------------
[11:35:02.615] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[11:35:02.615] <TB2> INFO: ----------------------------------------------------------------------
[11:35:02.615] <TB2> INFO: Vbg will be calibrated using Vd calibration
[11:35:02.615] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 152.7calibrated Vbg = 1.18093 :::*/*/*/*/
[11:35:02.615] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 158.9calibrated Vbg = 1.17796 :::*/*/*/*/
[11:35:02.615] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 149.5calibrated Vbg = 1.18055 :::*/*/*/*/
[11:35:02.615] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 154.8calibrated Vbg = 1.17931 :::*/*/*/*/
[11:35:02.615] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 162.2calibrated Vbg = 1.17407 :::*/*/*/*/
[11:35:02.615] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 158.4calibrated Vbg = 1.18606 :::*/*/*/*/
[11:35:02.615] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 153.5calibrated Vbg = 1.18588 :::*/*/*/*/
[11:35:02.615] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 161.2calibrated Vbg = 1.18045 :::*/*/*/*/
[11:35:02.615] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 162.7calibrated Vbg = 1.174 :::*/*/*/*/
[11:35:02.615] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 156.2calibrated Vbg = 1.18493 :::*/*/*/*/
[11:35:02.615] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 154.4calibrated Vbg = 1.17701 :::*/*/*/*/
[11:35:02.615] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 147.5calibrated Vbg = 1.16728 :::*/*/*/*/
[11:35:02.615] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 150.5calibrated Vbg = 1.17659 :::*/*/*/*/
[11:35:02.615] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 162.9calibrated Vbg = 1.18191 :::*/*/*/*/
[11:35:02.615] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 151.5calibrated Vbg = 1.18464 :::*/*/*/*/
[11:35:02.615] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 151.8calibrated Vbg = 1.17693 :::*/*/*/*/
[11:35:02.620] <TB2> INFO: ----------------------------------------------------------------------
[11:35:02.620] <TB2> INFO: PixTestReadback::CalibrateIa()
[11:35:02.620] <TB2> INFO: ----------------------------------------------------------------------
[11:37:43.436] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C0.dat
[11:37:43.436] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C1.dat
[11:37:43.436] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C2.dat
[11:37:43.436] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C3.dat
[11:37:43.436] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C4.dat
[11:37:43.436] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C5.dat
[11:37:43.436] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C6.dat
[11:37:43.436] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C7.dat
[11:37:43.436] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C8.dat
[11:37:43.436] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C9.dat
[11:37:43.436] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C10.dat
[11:37:43.436] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C11.dat
[11:37:43.436] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C12.dat
[11:37:43.436] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C13.dat
[11:37:43.437] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C14.dat
[11:37:43.437] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C15.dat
[11:37:43.465] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:37:43.467] <TB2> INFO: PixTestReadback::doTest() done
[11:37:43.467] <TB2> INFO: Decoding statistics:
[11:37:43.467] <TB2> INFO: General information:
[11:37:43.467] <TB2> INFO: 16bit words read: 1536
[11:37:43.467] <TB2> INFO: valid events total: 256
[11:37:43.467] <TB2> INFO: empty events: 256
[11:37:43.467] <TB2> INFO: valid events with pixels: 0
[11:37:43.467] <TB2> INFO: valid pixel hits: 0
[11:37:43.467] <TB2> INFO: Event errors: 0
[11:37:43.467] <TB2> INFO: start marker: 0
[11:37:43.467] <TB2> INFO: stop marker: 0
[11:37:43.467] <TB2> INFO: overflow: 0
[11:37:43.467] <TB2> INFO: invalid 5bit words: 0
[11:37:43.467] <TB2> INFO: invalid XOR eye diagram: 0
[11:37:43.467] <TB2> INFO: frame (failed synchr.): 0
[11:37:43.467] <TB2> INFO: idle data (no TBM trl): 0
[11:37:43.467] <TB2> INFO: no data (only TBM hdr): 0
[11:37:43.467] <TB2> INFO: TBM errors: 0
[11:37:43.467] <TB2> INFO: flawed TBM headers: 0
[11:37:43.467] <TB2> INFO: flawed TBM trailers: 0
[11:37:43.467] <TB2> INFO: event ID mismatches: 0
[11:37:43.467] <TB2> INFO: ROC errors: 0
[11:37:43.467] <TB2> INFO: missing ROC header(s): 0
[11:37:43.467] <TB2> INFO: misplaced readback start: 0
[11:37:43.467] <TB2> INFO: Pixel decoding errors: 0
[11:37:43.467] <TB2> INFO: pixel data incomplete: 0
[11:37:43.467] <TB2> INFO: pixel address: 0
[11:37:43.467] <TB2> INFO: pulse height fill bit: 0
[11:37:43.467] <TB2> INFO: buffer corruption: 0
[11:37:43.515] <TB2> INFO: ######################################################################
[11:37:43.515] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[11:37:43.515] <TB2> INFO: ######################################################################
[11:37:43.517] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[11:37:43.532] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:37:43.532] <TB2> INFO: run 1 of 1
[11:37:43.769] <TB2> INFO: Expecting 3120000 events.
[11:38:14.941] <TB2> INFO: 663840 events read in total (30581ms).











[11:38:45.092] <TB2> INFO: 1320355 events read in total (60732ms).











[11:39:14.664] <TB2> INFO: 1973405 events read in total (90304ms).











[11:39:44.671] <TB2> INFO: 2628535 events read in total (120311ms).
[11:40:07.051] <TB2> INFO: 3120000 events read in total (142691ms).
[11:40:07.120] <TB2> INFO: Test took 143587ms.
[11:40:30.214] <TB2> INFO: PixTestBBMap::doTest() done, duration: 166 seconds
[11:40:30.214] <TB2> INFO: number of dead bumps (per ROC): 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0
[11:40:30.214] <TB2> INFO: separation cut (per ROC): 101 103 105 97 113 103 111 109 111 105 105 111 95 102 99 102
[11:40:30.214] <TB2> INFO: Decoding statistics:
[11:40:30.214] <TB2> INFO: General information:
[11:40:30.214] <TB2> INFO: 16bit words read: 0
[11:40:30.214] <TB2> INFO: valid events total: 0
[11:40:30.214] <TB2> INFO: empty events: 0
[11:40:30.214] <TB2> INFO: valid events with pixels: 0
[11:40:30.214] <TB2> INFO: valid pixel hits: 0
[11:40:30.214] <TB2> INFO: Event errors: 0
[11:40:30.214] <TB2> INFO: start marker: 0
[11:40:30.214] <TB2> INFO: stop marker: 0
[11:40:30.214] <TB2> INFO: overflow: 0
[11:40:30.214] <TB2> INFO: invalid 5bit words: 0
[11:40:30.214] <TB2> INFO: invalid XOR eye diagram: 0
[11:40:30.214] <TB2> INFO: frame (failed synchr.): 0
[11:40:30.214] <TB2> INFO: idle data (no TBM trl): 0
[11:40:30.214] <TB2> INFO: no data (only TBM hdr): 0
[11:40:30.214] <TB2> INFO: TBM errors: 0
[11:40:30.214] <TB2> INFO: flawed TBM headers: 0
[11:40:30.214] <TB2> INFO: flawed TBM trailers: 0
[11:40:30.214] <TB2> INFO: event ID mismatches: 0
[11:40:30.214] <TB2> INFO: ROC errors: 0
[11:40:30.214] <TB2> INFO: missing ROC header(s): 0
[11:40:30.214] <TB2> INFO: misplaced readback start: 0
[11:40:30.214] <TB2> INFO: Pixel decoding errors: 0
[11:40:30.214] <TB2> INFO: pixel data incomplete: 0
[11:40:30.214] <TB2> INFO: pixel address: 0
[11:40:30.214] <TB2> INFO: pulse height fill bit: 0
[11:40:30.214] <TB2> INFO: buffer corruption: 0
[11:40:30.255] <TB2> INFO: ######################################################################
[11:40:30.255] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:40:30.255] <TB2> INFO: ######################################################################
[11:40:30.255] <TB2> INFO: ----------------------------------------------------------------------
[11:40:30.255] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:40:30.255] <TB2> INFO: ----------------------------------------------------------------------
[11:40:30.255] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[11:40:30.272] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[11:40:30.272] <TB2> INFO: run 1 of 1
[11:40:30.528] <TB2> INFO: Expecting 36608000 events.
[11:40:54.037] <TB2> INFO: 672800 events read in total (22918ms).
[11:41:16.687] <TB2> INFO: 1333300 events read in total (45568ms).
[11:41:39.206] <TB2> INFO: 1992500 events read in total (68087ms).
[11:42:01.762] <TB2> INFO: 2651400 events read in total (90643ms).
[11:42:24.502] <TB2> INFO: 3308300 events read in total (113383ms).
[11:42:47.373] <TB2> INFO: 3966800 events read in total (136254ms).
[11:43:09.878] <TB2> INFO: 4625650 events read in total (158759ms).
[11:43:32.562] <TB2> INFO: 5283150 events read in total (181443ms).
[11:43:55.019] <TB2> INFO: 5940000 events read in total (203900ms).
[11:44:17.794] <TB2> INFO: 6598750 events read in total (226675ms).
[11:44:40.523] <TB2> INFO: 7258050 events read in total (249404ms).
[11:45:03.166] <TB2> INFO: 7917050 events read in total (272047ms).
[11:45:26.104] <TB2> INFO: 8576400 events read in total (294985ms).
[11:45:48.815] <TB2> INFO: 9235550 events read in total (317696ms).
[11:46:11.680] <TB2> INFO: 9893850 events read in total (340561ms).
[11:46:34.160] <TB2> INFO: 10549850 events read in total (363041ms).
[11:46:56.917] <TB2> INFO: 11207100 events read in total (385798ms).
[11:47:19.652] <TB2> INFO: 11861250 events read in total (408533ms).
[11:47:42.269] <TB2> INFO: 12517150 events read in total (431150ms).
[11:48:04.795] <TB2> INFO: 13171800 events read in total (453676ms).
[11:48:27.554] <TB2> INFO: 13827400 events read in total (476435ms).
[11:48:50.571] <TB2> INFO: 14483550 events read in total (499452ms).
[11:49:13.174] <TB2> INFO: 15139350 events read in total (522055ms).
[11:49:35.774] <TB2> INFO: 15794150 events read in total (544655ms).
[11:49:58.409] <TB2> INFO: 16449300 events read in total (567290ms).
[11:50:21.174] <TB2> INFO: 17104550 events read in total (590055ms).
[11:50:43.698] <TB2> INFO: 17757900 events read in total (612579ms).
[11:51:06.306] <TB2> INFO: 18413450 events read in total (635187ms).
[11:51:29.189] <TB2> INFO: 19066700 events read in total (658070ms).
[11:51:51.761] <TB2> INFO: 19719600 events read in total (680642ms).
[11:52:14.639] <TB2> INFO: 20370950 events read in total (703520ms).
[11:52:37.552] <TB2> INFO: 21024750 events read in total (726433ms).
[11:53:00.068] <TB2> INFO: 21676550 events read in total (748949ms).
[11:53:22.521] <TB2> INFO: 22328400 events read in total (771402ms).
[11:53:45.103] <TB2> INFO: 22978650 events read in total (793984ms).
[11:54:07.722] <TB2> INFO: 23629550 events read in total (816603ms).
[11:54:30.454] <TB2> INFO: 24281100 events read in total (839335ms).
[11:54:53.352] <TB2> INFO: 24934350 events read in total (862233ms).
[11:55:16.083] <TB2> INFO: 25586750 events read in total (884964ms).
[11:55:38.597] <TB2> INFO: 26237800 events read in total (907478ms).
[11:56:01.064] <TB2> INFO: 26888600 events read in total (929945ms).
[11:56:23.554] <TB2> INFO: 27538700 events read in total (952435ms).
[11:56:46.205] <TB2> INFO: 28189500 events read in total (975086ms).
[11:57:08.838] <TB2> INFO: 28839250 events read in total (997719ms).
[11:57:31.580] <TB2> INFO: 29488550 events read in total (1020461ms).
[11:57:54.140] <TB2> INFO: 30138900 events read in total (1043021ms).
[11:58:17.181] <TB2> INFO: 30790150 events read in total (1066062ms).
[11:58:39.806] <TB2> INFO: 31440950 events read in total (1088687ms).
[11:59:02.464] <TB2> INFO: 32092250 events read in total (1111345ms).
[11:59:25.128] <TB2> INFO: 32744150 events read in total (1134009ms).
[11:59:47.798] <TB2> INFO: 33396900 events read in total (1156679ms).
[12:00:10.412] <TB2> INFO: 34048400 events read in total (1179293ms).
[12:00:33.067] <TB2> INFO: 34702200 events read in total (1201948ms).
[12:00:55.703] <TB2> INFO: 35354050 events read in total (1224584ms).
[12:01:18.384] <TB2> INFO: 36008150 events read in total (1247265ms).
[12:01:38.997] <TB2> INFO: 36608000 events read in total (1267878ms).
[12:01:39.103] <TB2> INFO: Test took 1268831ms.
[12:01:39.686] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:41.805] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:43.724] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:45.374] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:46.985] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:48.715] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:50.560] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:52.340] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:54.443] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:56.461] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:58.234] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:59.854] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:02:01.747] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:02:03.632] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:02:05.476] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:02:07.267] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:02:09.737] <TB2> INFO: PixTestScurves::scurves() done
[12:02:09.737] <TB2> INFO: Vcal mean: 112.23 111.94 116.11 101.24 126.46 123.33 121.96 117.03 121.15 114.35 110.08 120.20 110.50 103.60 104.01 116.26
[12:02:09.737] <TB2> INFO: Vcal RMS: 5.81 4.96 5.29 5.37 5.97 8.65 6.09 5.55 5.60 5.43 4.87 6.57 5.85 5.00 5.07 6.13
[12:02:09.738] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1299 seconds
[12:02:09.738] <TB2> INFO: Decoding statistics:
[12:02:09.738] <TB2> INFO: General information:
[12:02:09.738] <TB2> INFO: 16bit words read: 0
[12:02:09.738] <TB2> INFO: valid events total: 0
[12:02:09.738] <TB2> INFO: empty events: 0
[12:02:09.738] <TB2> INFO: valid events with pixels: 0
[12:02:09.738] <TB2> INFO: valid pixel hits: 0
[12:02:09.738] <TB2> INFO: Event errors: 0
[12:02:09.738] <TB2> INFO: start marker: 0
[12:02:09.738] <TB2> INFO: stop marker: 0
[12:02:09.738] <TB2> INFO: overflow: 0
[12:02:09.738] <TB2> INFO: invalid 5bit words: 0
[12:02:09.738] <TB2> INFO: invalid XOR eye diagram: 0
[12:02:09.738] <TB2> INFO: frame (failed synchr.): 0
[12:02:09.738] <TB2> INFO: idle data (no TBM trl): 0
[12:02:09.738] <TB2> INFO: no data (only TBM hdr): 0
[12:02:09.738] <TB2> INFO: TBM errors: 0
[12:02:09.738] <TB2> INFO: flawed TBM headers: 0
[12:02:09.738] <TB2> INFO: flawed TBM trailers: 0
[12:02:09.738] <TB2> INFO: event ID mismatches: 0
[12:02:09.738] <TB2> INFO: ROC errors: 0
[12:02:09.738] <TB2> INFO: missing ROC header(s): 0
[12:02:09.738] <TB2> INFO: misplaced readback start: 0
[12:02:09.738] <TB2> INFO: Pixel decoding errors: 0
[12:02:09.738] <TB2> INFO: pixel data incomplete: 0
[12:02:09.738] <TB2> INFO: pixel address: 0
[12:02:09.738] <TB2> INFO: pulse height fill bit: 0
[12:02:09.738] <TB2> INFO: buffer corruption: 0
[12:02:09.818] <TB2> INFO: ######################################################################
[12:02:09.818] <TB2> INFO: PixTestTrim::doTest()
[12:02:09.818] <TB2> INFO: ######################################################################
[12:02:09.819] <TB2> INFO: ----------------------------------------------------------------------
[12:02:09.822] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:02:09.822] <TB2> INFO: ----------------------------------------------------------------------
[12:02:09.878] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:02:09.878] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:02:09.893] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:02:09.893] <TB2> INFO: run 1 of 1
[12:02:10.150] <TB2> INFO: Expecting 5025280 events.
[12:02:41.446] <TB2> INFO: 818832 events read in total (30696ms).
[12:03:11.839] <TB2> INFO: 1634368 events read in total (61089ms).
[12:03:42.127] <TB2> INFO: 2447552 events read in total (91378ms).
[12:04:12.222] <TB2> INFO: 3257544 events read in total (121472ms).
[12:04:42.649] <TB2> INFO: 4065752 events read in total (151899ms).
[12:05:12.451] <TB2> INFO: 4871752 events read in total (181701ms).
[12:05:18.455] <TB2> INFO: 5025280 events read in total (187705ms).
[12:05:18.525] <TB2> INFO: Test took 188633ms.
[12:05:35.927] <TB2> INFO: ROC 0 VthrComp = 113
[12:05:35.928] <TB2> INFO: ROC 1 VthrComp = 116
[12:05:35.928] <TB2> INFO: ROC 2 VthrComp = 127
[12:05:35.928] <TB2> INFO: ROC 3 VthrComp = 105
[12:05:35.928] <TB2> INFO: ROC 4 VthrComp = 134
[12:05:35.929] <TB2> INFO: ROC 5 VthrComp = 117
[12:05:35.930] <TB2> INFO: ROC 6 VthrComp = 130
[12:05:35.930] <TB2> INFO: ROC 7 VthrComp = 123
[12:05:35.930] <TB2> INFO: ROC 8 VthrComp = 132
[12:05:35.930] <TB2> INFO: ROC 9 VthrComp = 116
[12:05:35.930] <TB2> INFO: ROC 10 VthrComp = 114
[12:05:35.930] <TB2> INFO: ROC 11 VthrComp = 125
[12:05:35.930] <TB2> INFO: ROC 12 VthrComp = 109
[12:05:35.930] <TB2> INFO: ROC 13 VthrComp = 108
[12:05:35.930] <TB2> INFO: ROC 14 VthrComp = 111
[12:05:35.931] <TB2> INFO: ROC 15 VthrComp = 115
[12:05:36.178] <TB2> INFO: Expecting 41600 events.
[12:05:39.703] <TB2> INFO: 41600 events read in total (2933ms).
[12:05:39.704] <TB2> INFO: Test took 3772ms.
[12:05:39.714] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:05:39.714] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:05:39.727] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:05:39.727] <TB2> INFO: run 1 of 1
[12:05:40.005] <TB2> INFO: Expecting 5025280 events.
[12:06:06.668] <TB2> INFO: 590920 events read in total (26072ms).
[12:06:32.270] <TB2> INFO: 1180760 events read in total (51675ms).
[12:06:57.928] <TB2> INFO: 1769872 events read in total (77332ms).
[12:07:23.603] <TB2> INFO: 2358496 events read in total (103007ms).
[12:07:49.566] <TB2> INFO: 2944568 events read in total (128970ms).
[12:08:15.497] <TB2> INFO: 3529472 events read in total (154901ms).
[12:08:41.748] <TB2> INFO: 4114816 events read in total (181152ms).
[12:09:07.480] <TB2> INFO: 4699440 events read in total (206884ms).
[12:09:21.839] <TB2> INFO: 5025280 events read in total (221243ms).
[12:09:22.053] <TB2> INFO: Test took 222325ms.
[12:09:49.044] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 61.8627 for pixel 6/75 mean/min/max = 47.052/31.8954/62.2085
[12:09:49.045] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 58.6695 for pixel 10/10 mean/min/max = 45.4055/32.0116/58.7993
[12:09:49.045] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 57.7194 for pixel 23/0 mean/min/max = 44.3572/30.9176/57.7968
[12:09:49.046] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 60.0085 for pixel 1/2 mean/min/max = 47.388/34.7626/60.0133
[12:09:49.046] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 60.1925 for pixel 18/19 mean/min/max = 46.4118/32.6244/60.1992
[12:09:49.047] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 63.2911 for pixel 17/0 mean/min/max = 47.1678/31.0122/63.3234
[12:09:49.048] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 58.8681 for pixel 13/2 mean/min/max = 45.3814/31.7717/58.9911
[12:09:49.048] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 60.0582 for pixel 22/6 mean/min/max = 46.2562/32.4325/60.0798
[12:09:49.049] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 57.3377 for pixel 10/3 mean/min/max = 44.7998/31.8592/57.7403
[12:09:49.049] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 60.3722 for pixel 0/4 mean/min/max = 46.1077/31.8105/60.4048
[12:09:49.050] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 58.8977 for pixel 7/1 mean/min/max = 45.5219/32.0159/59.028
[12:09:49.050] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 59.9705 for pixel 4/57 mean/min/max = 45.1988/30.2486/60.1491
[12:09:49.051] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 62.6309 for pixel 21/76 mean/min/max = 48.359/34.0557/62.6623
[12:09:49.051] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 59.0968 for pixel 3/77 mean/min/max = 47.3437/35.4884/59.199
[12:09:49.052] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 58.8716 for pixel 6/7 mean/min/max = 46.75/34.3257/59.1742
[12:09:49.052] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 60.2441 for pixel 5/76 mean/min/max = 46.0586/31.7593/60.358
[12:09:49.053] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:09:49.141] <TB2> INFO: Expecting 411648 events.
[12:09:58.780] <TB2> INFO: 411648 events read in total (9047ms).
[12:09:58.788] <TB2> INFO: Expecting 411648 events.
[12:10:08.112] <TB2> INFO: 411648 events read in total (8921ms).
[12:10:08.124] <TB2> INFO: Expecting 411648 events.
[12:10:17.229] <TB2> INFO: 411648 events read in total (8701ms).
[12:10:17.242] <TB2> INFO: Expecting 411648 events.
[12:10:26.567] <TB2> INFO: 411648 events read in total (8922ms).
[12:10:26.582] <TB2> INFO: Expecting 411648 events.
[12:10:35.955] <TB2> INFO: 411648 events read in total (8970ms).
[12:10:35.975] <TB2> INFO: Expecting 411648 events.
[12:10:45.294] <TB2> INFO: 411648 events read in total (8915ms).
[12:10:45.315] <TB2> INFO: Expecting 411648 events.
[12:10:54.660] <TB2> INFO: 411648 events read in total (8942ms).
[12:10:54.691] <TB2> INFO: Expecting 411648 events.
[12:11:04.099] <TB2> INFO: 411648 events read in total (9005ms).
[12:11:04.126] <TB2> INFO: Expecting 411648 events.
[12:11:13.526] <TB2> INFO: 411648 events read in total (8997ms).
[12:11:13.556] <TB2> INFO: Expecting 411648 events.
[12:11:22.869] <TB2> INFO: 411648 events read in total (8910ms).
[12:11:22.901] <TB2> INFO: Expecting 411648 events.
[12:11:32.205] <TB2> INFO: 411648 events read in total (8901ms).
[12:11:32.240] <TB2> INFO: Expecting 411648 events.
[12:11:41.616] <TB2> INFO: 411648 events read in total (8973ms).
[12:11:41.665] <TB2> INFO: Expecting 411648 events.
[12:11:51.019] <TB2> INFO: 411648 events read in total (8951ms).
[12:11:51.060] <TB2> INFO: Expecting 411648 events.
[12:12:00.496] <TB2> INFO: 411648 events read in total (9033ms).
[12:12:00.538] <TB2> INFO: Expecting 411648 events.
[12:12:09.887] <TB2> INFO: 411648 events read in total (8946ms).
[12:12:09.947] <TB2> INFO: Expecting 411648 events.
[12:12:19.207] <TB2> INFO: 411648 events read in total (8857ms).
[12:12:19.265] <TB2> INFO: Test took 150212ms.
[12:12:20.021] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:12:20.035] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:12:20.035] <TB2> INFO: run 1 of 1
[12:12:20.271] <TB2> INFO: Expecting 5025280 events.
[12:12:47.187] <TB2> INFO: 588760 events read in total (26324ms).
[12:13:13.250] <TB2> INFO: 1175680 events read in total (52387ms).
[12:13:39.283] <TB2> INFO: 1760688 events read in total (78420ms).
[12:14:05.495] <TB2> INFO: 2346304 events read in total (104632ms).
[12:14:31.739] <TB2> INFO: 2929912 events read in total (130876ms).
[12:14:57.937] <TB2> INFO: 3514040 events read in total (157074ms).
[12:15:24.429] <TB2> INFO: 4099512 events read in total (183566ms).
[12:15:50.540] <TB2> INFO: 4684696 events read in total (209677ms).
[12:16:06.045] <TB2> INFO: 5025280 events read in total (225182ms).
[12:16:06.165] <TB2> INFO: Test took 226131ms.
[12:16:29.926] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 2.780482 .. 145.137248
[12:16:30.168] <TB2> INFO: Expecting 208000 events.
[12:16:40.140] <TB2> INFO: 208000 events read in total (9381ms).
[12:16:40.143] <TB2> INFO: Test took 10215ms.
[12:16:40.223] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 155 (-1/-1) hits flags = 528 (plus default)
[12:16:40.237] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:16:40.237] <TB2> INFO: run 1 of 1
[12:16:40.561] <TB2> INFO: Expecting 5125120 events.
[12:17:07.159] <TB2> INFO: 582976 events read in total (26006ms).
[12:17:33.231] <TB2> INFO: 1165920 events read in total (52078ms).
[12:17:58.988] <TB2> INFO: 1748600 events read in total (77835ms).
[12:18:25.126] <TB2> INFO: 2331432 events read in total (103973ms).
[12:18:51.426] <TB2> INFO: 2914128 events read in total (130273ms).
[12:19:17.226] <TB2> INFO: 3496272 events read in total (156073ms).
[12:19:43.354] <TB2> INFO: 4078008 events read in total (182201ms).
[12:20:09.529] <TB2> INFO: 4659792 events read in total (208376ms).
[12:20:30.228] <TB2> INFO: 5125120 events read in total (229075ms).
[12:20:30.318] <TB2> INFO: Test took 230081ms.
[12:20:57.617] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.808132 .. 45.101075
[12:20:57.856] <TB2> INFO: Expecting 208000 events.
[12:21:07.912] <TB2> INFO: 208000 events read in total (9464ms).
[12:21:07.913] <TB2> INFO: Test took 10295ms.
[12:21:07.985] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:21:07.000] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:21:07.000] <TB2> INFO: run 1 of 1
[12:21:08.281] <TB2> INFO: Expecting 1297920 events.
[12:21:36.386] <TB2> INFO: 658904 events read in total (27513ms).
[12:22:03.867] <TB2> INFO: 1297920 events read in total (54994ms).
[12:22:03.905] <TB2> INFO: Test took 55905ms.
[12:22:18.253] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 26.406000 .. 47.201686
[12:22:18.519] <TB2> INFO: Expecting 208000 events.
[12:22:28.233] <TB2> INFO: 208000 events read in total (9123ms).
[12:22:28.234] <TB2> INFO: Test took 9980ms.
[12:22:28.302] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 57 (-1/-1) hits flags = 528 (plus default)
[12:22:28.316] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:22:28.317] <TB2> INFO: run 1 of 1
[12:22:28.596] <TB2> INFO: Expecting 1397760 events.
[12:22:57.220] <TB2> INFO: 655776 events read in total (28033ms).
[12:23:25.893] <TB2> INFO: 1309528 events read in total (56707ms).
[12:23:30.209] <TB2> INFO: 1397760 events read in total (61022ms).
[12:23:30.248] <TB2> INFO: Test took 61932ms.
[12:23:43.620] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 25.075937 .. 47.620487
[12:23:43.867] <TB2> INFO: Expecting 208000 events.
[12:23:53.742] <TB2> INFO: 208000 events read in total (9283ms).
[12:23:53.743] <TB2> INFO: Test took 10121ms.
[12:23:53.790] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 57 (-1/-1) hits flags = 528 (plus default)
[12:23:53.803] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:23:53.804] <TB2> INFO: run 1 of 1
[12:23:54.082] <TB2> INFO: Expecting 1431040 events.
[12:24:21.830] <TB2> INFO: 659712 events read in total (27157ms).
[12:24:49.148] <TB2> INFO: 1319096 events read in total (54475ms).
[12:24:54.067] <TB2> INFO: 1431040 events read in total (59394ms).
[12:24:54.101] <TB2> INFO: Test took 60298ms.
[12:25:09.944] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:25:09.944] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:25:09.959] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:25:09.959] <TB2> INFO: run 1 of 1
[12:25:10.250] <TB2> INFO: Expecting 1364480 events.
[12:25:38.744] <TB2> INFO: 666912 events read in total (27902ms).
[12:26:07.415] <TB2> INFO: 1333632 events read in total (56573ms).
[12:26:09.110] <TB2> INFO: 1364480 events read in total (58269ms).
[12:26:09.145] <TB2> INFO: Test took 59187ms.
[12:26:24.201] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C0.dat
[12:26:24.201] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C1.dat
[12:26:24.201] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C2.dat
[12:26:24.201] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C3.dat
[12:26:24.201] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C4.dat
[12:26:24.201] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C5.dat
[12:26:24.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C6.dat
[12:26:24.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C7.dat
[12:26:24.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C8.dat
[12:26:24.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C9.dat
[12:26:24.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C10.dat
[12:26:24.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C11.dat
[12:26:24.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C12.dat
[12:26:24.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C13.dat
[12:26:24.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C14.dat
[12:26:24.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C15.dat
[12:26:24.202] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C0.dat
[12:26:24.209] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C1.dat
[12:26:24.214] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C2.dat
[12:26:24.218] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C3.dat
[12:26:24.223] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C4.dat
[12:26:24.228] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C5.dat
[12:26:24.233] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C6.dat
[12:26:24.238] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C7.dat
[12:26:24.243] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C8.dat
[12:26:24.248] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C9.dat
[12:26:24.253] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C10.dat
[12:26:24.259] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C11.dat
[12:26:24.265] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C12.dat
[12:26:24.271] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C13.dat
[12:26:24.277] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C14.dat
[12:26:24.283] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C15.dat
[12:26:24.289] <TB2> INFO: PixTestTrim::trimTest() done
[12:26:24.289] <TB2> INFO: vtrim: 128 122 125 117 147 129 140 143 127 117 111 126 129 118 118 122
[12:26:24.289] <TB2> INFO: vthrcomp: 113 116 127 105 134 117 130 123 132 116 114 125 109 108 111 115
[12:26:24.289] <TB2> INFO: vcal mean: 34.99 34.97 34.93 34.99 34.99 35.12 34.97 34.97 34.92 34.96 34.94 34.94 34.97 35.00 34.99 34.95
[12:26:24.289] <TB2> INFO: vcal RMS: 1.24 0.97 1.06 0.91 1.08 1.38 1.03 1.06 1.04 1.11 1.02 1.26 1.01 0.89 0.95 1.06
[12:26:24.289] <TB2> INFO: bits mean: 9.01 9.65 10.10 8.06 9.69 10.19 9.74 9.79 9.86 9.16 9.52 10.04 8.78 8.42 8.70 9.46
[12:26:24.289] <TB2> INFO: bits RMS: 2.84 2.68 2.66 2.76 2.50 2.39 2.66 2.48 2.64 2.91 2.71 2.67 2.56 2.59 2.62 2.70
[12:26:24.298] <TB2> INFO: ----------------------------------------------------------------------
[12:26:24.298] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:26:24.298] <TB2> INFO: ----------------------------------------------------------------------
[12:26:24.301] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:26:24.313] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:26:24.313] <TB2> INFO: run 1 of 1
[12:26:24.575] <TB2> INFO: Expecting 4160000 events.
[12:26:57.359] <TB2> INFO: 744930 events read in total (32193ms).
[12:27:28.827] <TB2> INFO: 1485865 events read in total (63661ms).
[12:28:00.594] <TB2> INFO: 2221955 events read in total (95428ms).
[12:28:32.628] <TB2> INFO: 2954320 events read in total (127462ms).
[12:29:04.245] <TB2> INFO: 3684785 events read in total (159079ms).
[12:29:25.199] <TB2> INFO: 4160000 events read in total (180033ms).
[12:29:25.281] <TB2> INFO: Test took 180968ms.
[12:29:51.096] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[12:29:51.110] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:29:51.110] <TB2> INFO: run 1 of 1
[12:29:51.354] <TB2> INFO: Expecting 4326400 events.
[12:30:23.098] <TB2> INFO: 709520 events read in total (31153ms).
[12:30:53.817] <TB2> INFO: 1416655 events read in total (61872ms).
[12:31:25.115] <TB2> INFO: 2119205 events read in total (93170ms).
[12:31:56.174] <TB2> INFO: 2819145 events read in total (124229ms).
[12:32:27.230] <TB2> INFO: 3516925 events read in total (155285ms).
[12:32:58.286] <TB2> INFO: 4215715 events read in total (186341ms).
[12:33:03.379] <TB2> INFO: 4326400 events read in total (191434ms).
[12:33:03.463] <TB2> INFO: Test took 192353ms.
[12:33:28.427] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 208 (-1/-1) hits flags = 528 (plus default)
[12:33:28.442] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:33:28.442] <TB2> INFO: run 1 of 1
[12:33:28.727] <TB2> INFO: Expecting 4347200 events.
[12:34:00.552] <TB2> INFO: 709145 events read in total (31233ms).
[12:34:31.385] <TB2> INFO: 1415635 events read in total (62066ms).
[12:35:02.836] <TB2> INFO: 2117430 events read in total (93517ms).
[12:35:33.715] <TB2> INFO: 2816330 events read in total (124396ms).
[12:36:04.840] <TB2> INFO: 3513540 events read in total (155521ms).
[12:36:35.754] <TB2> INFO: 4211365 events read in total (186435ms).
[12:36:42.248] <TB2> INFO: 4347200 events read in total (192929ms).
[12:36:42.537] <TB2> INFO: Test took 194094ms.
[12:37:09.795] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[12:37:09.808] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:37:09.808] <TB2> INFO: run 1 of 1
[12:37:10.047] <TB2> INFO: Expecting 4305600 events.
[12:37:41.811] <TB2> INFO: 711280 events read in total (31172ms).
[12:38:14.309] <TB2> INFO: 1420255 events read in total (63670ms).
[12:38:45.249] <TB2> INFO: 2124405 events read in total (94610ms).
[12:39:16.567] <TB2> INFO: 2826000 events read in total (125928ms).
[12:39:47.457] <TB2> INFO: 3525105 events read in total (156818ms).
[12:40:18.372] <TB2> INFO: 4226010 events read in total (187733ms).
[12:40:22.157] <TB2> INFO: 4305600 events read in total (191518ms).
[12:40:22.244] <TB2> INFO: Test took 192435ms.
[12:40:49.180] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[12:40:49.194] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:40:49.194] <TB2> INFO: run 1 of 1
[12:40:49.470] <TB2> INFO: Expecting 4305600 events.
[12:41:21.025] <TB2> INFO: 711850 events read in total (30964ms).
[12:41:51.816] <TB2> INFO: 1421290 events read in total (61755ms).
[12:42:22.915] <TB2> INFO: 2125730 events read in total (92854ms).
[12:42:53.677] <TB2> INFO: 2827520 events read in total (123616ms).
[12:43:23.967] <TB2> INFO: 3526940 events read in total (153906ms).
[12:43:55.194] <TB2> INFO: 4227900 events read in total (185133ms).
[12:43:58.961] <TB2> INFO: 4305600 events read in total (188900ms).
[12:43:59.041] <TB2> INFO: Test took 189847ms.
[12:44:23.673] <TB2> INFO: PixTestTrim::trimBitTest() done
[12:44:23.674] <TB2> INFO: PixTestTrim::doTest() done, duration: 2533 seconds
[12:44:23.674] <TB2> INFO: Decoding statistics:
[12:44:23.674] <TB2> INFO: General information:
[12:44:23.674] <TB2> INFO: 16bit words read: 0
[12:44:23.674] <TB2> INFO: valid events total: 0
[12:44:23.674] <TB2> INFO: empty events: 0
[12:44:23.674] <TB2> INFO: valid events with pixels: 0
[12:44:23.674] <TB2> INFO: valid pixel hits: 0
[12:44:23.674] <TB2> INFO: Event errors: 0
[12:44:23.674] <TB2> INFO: start marker: 0
[12:44:23.674] <TB2> INFO: stop marker: 0
[12:44:23.674] <TB2> INFO: overflow: 0
[12:44:23.674] <TB2> INFO: invalid 5bit words: 0
[12:44:23.674] <TB2> INFO: invalid XOR eye diagram: 0
[12:44:23.674] <TB2> INFO: frame (failed synchr.): 0
[12:44:23.674] <TB2> INFO: idle data (no TBM trl): 0
[12:44:23.674] <TB2> INFO: no data (only TBM hdr): 0
[12:44:23.674] <TB2> INFO: TBM errors: 0
[12:44:23.674] <TB2> INFO: flawed TBM headers: 0
[12:44:23.674] <TB2> INFO: flawed TBM trailers: 0
[12:44:23.674] <TB2> INFO: event ID mismatches: 0
[12:44:23.674] <TB2> INFO: ROC errors: 0
[12:44:23.674] <TB2> INFO: missing ROC header(s): 0
[12:44:23.674] <TB2> INFO: misplaced readback start: 0
[12:44:23.674] <TB2> INFO: Pixel decoding errors: 0
[12:44:23.674] <TB2> INFO: pixel data incomplete: 0
[12:44:23.674] <TB2> INFO: pixel address: 0
[12:44:23.674] <TB2> INFO: pulse height fill bit: 0
[12:44:23.674] <TB2> INFO: buffer corruption: 0
[12:44:24.335] <TB2> INFO: ######################################################################
[12:44:24.336] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[12:44:24.336] <TB2> INFO: ######################################################################
[12:44:24.574] <TB2> INFO: Expecting 41600 events.
[12:44:28.046] <TB2> INFO: 41600 events read in total (2880ms).
[12:44:28.046] <TB2> INFO: Test took 3709ms.
[12:44:28.486] <TB2> INFO: Expecting 41600 events.
[12:44:32.054] <TB2> INFO: 41600 events read in total (2976ms).
[12:44:32.055] <TB2> INFO: Test took 3806ms.
[12:44:32.344] <TB2> INFO: Expecting 41600 events.
[12:44:35.822] <TB2> INFO: 41600 events read in total (2887ms).
[12:44:35.823] <TB2> INFO: Test took 3744ms.
[12:44:36.113] <TB2> INFO: Expecting 41600 events.
[12:44:39.759] <TB2> INFO: 41600 events read in total (3055ms).
[12:44:39.760] <TB2> INFO: Test took 3913ms.
[12:44:40.049] <TB2> INFO: Expecting 41600 events.
[12:44:43.560] <TB2> INFO: 41600 events read in total (2919ms).
[12:44:43.560] <TB2> INFO: Test took 3776ms.
[12:44:43.849] <TB2> INFO: Expecting 41600 events.
[12:44:47.437] <TB2> INFO: 41600 events read in total (2996ms).
[12:44:47.438] <TB2> INFO: Test took 3854ms.
[12:44:47.729] <TB2> INFO: Expecting 41600 events.
[12:44:51.294] <TB2> INFO: 41600 events read in total (2974ms).
[12:44:51.295] <TB2> INFO: Test took 3831ms.
[12:44:51.583] <TB2> INFO: Expecting 41600 events.
[12:44:55.133] <TB2> INFO: 41600 events read in total (2958ms).
[12:44:55.134] <TB2> INFO: Test took 3815ms.
[12:44:55.423] <TB2> INFO: Expecting 41600 events.
[12:44:58.922] <TB2> INFO: 41600 events read in total (2908ms).
[12:44:58.923] <TB2> INFO: Test took 3765ms.
[12:44:59.213] <TB2> INFO: Expecting 41600 events.
[12:45:02.816] <TB2> INFO: 41600 events read in total (3011ms).
[12:45:02.818] <TB2> INFO: Test took 3870ms.
[12:45:03.109] <TB2> INFO: Expecting 41600 events.
[12:45:06.605] <TB2> INFO: 41600 events read in total (2905ms).
[12:45:06.606] <TB2> INFO: Test took 3762ms.
[12:45:06.895] <TB2> INFO: Expecting 41600 events.
[12:45:10.545] <TB2> INFO: 41600 events read in total (3058ms).
[12:45:10.545] <TB2> INFO: Test took 3914ms.
[12:45:10.834] <TB2> INFO: Expecting 41600 events.
[12:45:14.304] <TB2> INFO: 41600 events read in total (2878ms).
[12:45:14.305] <TB2> INFO: Test took 3735ms.
[12:45:14.595] <TB2> INFO: Expecting 41600 events.
[12:45:18.160] <TB2> INFO: 41600 events read in total (2973ms).
[12:45:18.161] <TB2> INFO: Test took 3831ms.
[12:45:18.458] <TB2> INFO: Expecting 41600 events.
[12:45:21.994] <TB2> INFO: 41600 events read in total (2944ms).
[12:45:21.995] <TB2> INFO: Test took 3807ms.
[12:45:22.284] <TB2> INFO: Expecting 41600 events.
[12:45:25.850] <TB2> INFO: 41600 events read in total (2975ms).
[12:45:25.851] <TB2> INFO: Test took 3832ms.
[12:45:26.141] <TB2> INFO: Expecting 41600 events.
[12:45:29.691] <TB2> INFO: 41600 events read in total (2958ms).
[12:45:29.692] <TB2> INFO: Test took 3817ms.
[12:45:29.981] <TB2> INFO: Expecting 41600 events.
[12:45:33.509] <TB2> INFO: 41600 events read in total (2936ms).
[12:45:33.510] <TB2> INFO: Test took 3794ms.
[12:45:33.799] <TB2> INFO: Expecting 41600 events.
[12:45:37.458] <TB2> INFO: 41600 events read in total (3067ms).
[12:45:37.459] <TB2> INFO: Test took 3925ms.
[12:45:37.749] <TB2> INFO: Expecting 41600 events.
[12:45:41.277] <TB2> INFO: 41600 events read in total (2936ms).
[12:45:41.278] <TB2> INFO: Test took 3795ms.
[12:45:41.568] <TB2> INFO: Expecting 41600 events.
[12:45:45.172] <TB2> INFO: 41600 events read in total (3012ms).
[12:45:45.172] <TB2> INFO: Test took 3869ms.
[12:45:45.462] <TB2> INFO: Expecting 41600 events.
[12:45:48.000] <TB2> INFO: 41600 events read in total (2946ms).
[12:45:48.001] <TB2> INFO: Test took 3804ms.
[12:45:49.295] <TB2> INFO: Expecting 41600 events.
[12:45:52.829] <TB2> INFO: 41600 events read in total (2943ms).
[12:45:52.829] <TB2> INFO: Test took 3800ms.
[12:45:53.121] <TB2> INFO: Expecting 41600 events.
[12:45:56.621] <TB2> INFO: 41600 events read in total (2909ms).
[12:45:56.621] <TB2> INFO: Test took 3765ms.
[12:45:56.910] <TB2> INFO: Expecting 41600 events.
[12:46:00.484] <TB2> INFO: 41600 events read in total (2982ms).
[12:46:00.485] <TB2> INFO: Test took 3839ms.
[12:46:00.774] <TB2> INFO: Expecting 41600 events.
[12:46:04.413] <TB2> INFO: 41600 events read in total (3048ms).
[12:46:04.414] <TB2> INFO: Test took 3905ms.
[12:46:04.705] <TB2> INFO: Expecting 41600 events.
[12:46:08.204] <TB2> INFO: 41600 events read in total (2908ms).
[12:46:08.204] <TB2> INFO: Test took 3764ms.
[12:46:08.512] <TB2> INFO: Expecting 41600 events.
[12:46:12.076] <TB2> INFO: 41600 events read in total (2973ms).
[12:46:12.076] <TB2> INFO: Test took 3848ms.
[12:46:12.368] <TB2> INFO: Expecting 41600 events.
[12:46:15.881] <TB2> INFO: 41600 events read in total (2920ms).
[12:46:15.882] <TB2> INFO: Test took 3782ms.
[12:46:16.172] <TB2> INFO: Expecting 41600 events.
[12:46:19.711] <TB2> INFO: 41600 events read in total (2947ms).
[12:46:19.712] <TB2> INFO: Test took 3805ms.
[12:46:20.004] <TB2> INFO: Expecting 2560 events.
[12:46:20.897] <TB2> INFO: 2560 events read in total (302ms).
[12:46:20.897] <TB2> INFO: Test took 1172ms.
[12:46:21.205] <TB2> INFO: Expecting 2560 events.
[12:46:22.094] <TB2> INFO: 2560 events read in total (297ms).
[12:46:22.094] <TB2> INFO: Test took 1197ms.
[12:46:22.402] <TB2> INFO: Expecting 2560 events.
[12:46:23.287] <TB2> INFO: 2560 events read in total (293ms).
[12:46:23.287] <TB2> INFO: Test took 1192ms.
[12:46:23.595] <TB2> INFO: Expecting 2560 events.
[12:46:24.486] <TB2> INFO: 2560 events read in total (299ms).
[12:46:24.486] <TB2> INFO: Test took 1198ms.
[12:46:24.794] <TB2> INFO: Expecting 2560 events.
[12:46:25.675] <TB2> INFO: 2560 events read in total (290ms).
[12:46:25.675] <TB2> INFO: Test took 1189ms.
[12:46:25.983] <TB2> INFO: Expecting 2560 events.
[12:46:26.869] <TB2> INFO: 2560 events read in total (294ms).
[12:46:26.870] <TB2> INFO: Test took 1194ms.
[12:46:27.177] <TB2> INFO: Expecting 2560 events.
[12:46:28.064] <TB2> INFO: 2560 events read in total (295ms).
[12:46:28.064] <TB2> INFO: Test took 1194ms.
[12:46:28.373] <TB2> INFO: Expecting 2560 events.
[12:46:29.261] <TB2> INFO: 2560 events read in total (296ms).
[12:46:29.261] <TB2> INFO: Test took 1197ms.
[12:46:29.570] <TB2> INFO: Expecting 2560 events.
[12:46:30.459] <TB2> INFO: 2560 events read in total (297ms).
[12:46:30.460] <TB2> INFO: Test took 1198ms.
[12:46:30.766] <TB2> INFO: Expecting 2560 events.
[12:46:31.645] <TB2> INFO: 2560 events read in total (287ms).
[12:46:31.646] <TB2> INFO: Test took 1186ms.
[12:46:31.954] <TB2> INFO: Expecting 2560 events.
[12:46:32.846] <TB2> INFO: 2560 events read in total (300ms).
[12:46:32.846] <TB2> INFO: Test took 1199ms.
[12:46:33.153] <TB2> INFO: Expecting 2560 events.
[12:46:34.042] <TB2> INFO: 2560 events read in total (297ms).
[12:46:34.043] <TB2> INFO: Test took 1196ms.
[12:46:34.352] <TB2> INFO: Expecting 2560 events.
[12:46:35.235] <TB2> INFO: 2560 events read in total (292ms).
[12:46:35.235] <TB2> INFO: Test took 1192ms.
[12:46:35.543] <TB2> INFO: Expecting 2560 events.
[12:46:36.435] <TB2> INFO: 2560 events read in total (300ms).
[12:46:36.435] <TB2> INFO: Test took 1200ms.
[12:46:36.743] <TB2> INFO: Expecting 2560 events.
[12:46:37.636] <TB2> INFO: 2560 events read in total (301ms).
[12:46:37.636] <TB2> INFO: Test took 1200ms.
[12:46:37.944] <TB2> INFO: Expecting 2560 events.
[12:46:38.831] <TB2> INFO: 2560 events read in total (296ms).
[12:46:38.832] <TB2> INFO: Test took 1195ms.
[12:46:38.835] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:46:39.140] <TB2> INFO: Expecting 655360 events.
[12:46:54.320] <TB2> INFO: 655360 events read in total (14588ms).
[12:46:54.331] <TB2> INFO: Expecting 655360 events.
[12:47:09.134] <TB2> INFO: 655360 events read in total (14400ms).
[12:47:09.157] <TB2> INFO: Expecting 655360 events.
[12:47:23.979] <TB2> INFO: 655360 events read in total (14419ms).
[12:47:23.000] <TB2> INFO: Expecting 655360 events.
[12:47:38.637] <TB2> INFO: 655360 events read in total (14234ms).
[12:47:38.662] <TB2> INFO: Expecting 655360 events.
[12:47:53.116] <TB2> INFO: 655360 events read in total (14051ms).
[12:47:53.145] <TB2> INFO: Expecting 655360 events.
[12:48:07.680] <TB2> INFO: 655360 events read in total (14132ms).
[12:48:07.718] <TB2> INFO: Expecting 655360 events.
[12:48:22.128] <TB2> INFO: 655360 events read in total (14007ms).
[12:48:22.174] <TB2> INFO: Expecting 655360 events.
[12:48:36.837] <TB2> INFO: 655360 events read in total (14260ms).
[12:48:36.905] <TB2> INFO: Expecting 655360 events.
[12:48:51.429] <TB2> INFO: 655360 events read in total (14119ms).
[12:48:51.490] <TB2> INFO: Expecting 655360 events.
[12:49:05.767] <TB2> INFO: 655360 events read in total (13874ms).
[12:49:05.861] <TB2> INFO: Expecting 655360 events.
[12:49:20.169] <TB2> INFO: 655360 events read in total (13906ms).
[12:49:20.249] <TB2> INFO: Expecting 655360 events.
[12:49:34.675] <TB2> INFO: 655360 events read in total (14023ms).
[12:49:34.770] <TB2> INFO: Expecting 655360 events.
[12:49:49.303] <TB2> INFO: 655360 events read in total (14130ms).
[12:49:49.395] <TB2> INFO: Expecting 655360 events.
[12:50:04.097] <TB2> INFO: 655360 events read in total (14299ms).
[12:50:04.245] <TB2> INFO: Expecting 655360 events.
[12:50:18.711] <TB2> INFO: 655360 events read in total (14063ms).
[12:50:18.871] <TB2> INFO: Expecting 655360 events.
[12:50:33.493] <TB2> INFO: 655360 events read in total (14219ms).
[12:50:33.615] <TB2> INFO: Test took 234780ms.
[12:50:33.712] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:50:33.969] <TB2> INFO: Expecting 655360 events.
[12:50:48.500] <TB2> INFO: 655360 events read in total (13939ms).
[12:50:48.512] <TB2> INFO: Expecting 655360 events.
[12:51:02.748] <TB2> INFO: 655360 events read in total (13833ms).
[12:51:02.770] <TB2> INFO: Expecting 655360 events.
[12:51:17.172] <TB2> INFO: 655360 events read in total (13998ms).
[12:51:17.199] <TB2> INFO: Expecting 655360 events.
[12:51:31.627] <TB2> INFO: 655360 events read in total (14025ms).
[12:51:31.660] <TB2> INFO: Expecting 655360 events.
[12:51:46.049] <TB2> INFO: 655360 events read in total (13986ms).
[12:51:46.082] <TB2> INFO: Expecting 655360 events.
[12:52:00.365] <TB2> INFO: 655360 events read in total (13880ms).
[12:52:00.398] <TB2> INFO: Expecting 655360 events.
[12:52:14.598] <TB2> INFO: 655360 events read in total (13797ms).
[12:52:14.636] <TB2> INFO: Expecting 655360 events.
[12:52:29.065] <TB2> INFO: 655360 events read in total (14027ms).
[12:52:29.138] <TB2> INFO: Expecting 655360 events.
[12:52:43.502] <TB2> INFO: 655360 events read in total (13961ms).
[12:52:43.563] <TB2> INFO: Expecting 655360 events.
[12:52:57.699] <TB2> INFO: 655360 events read in total (13733ms).
[12:52:57.763] <TB2> INFO: Expecting 655360 events.
[12:53:12.224] <TB2> INFO: 655360 events read in total (14057ms).
[12:53:12.296] <TB2> INFO: Expecting 655360 events.
[12:53:26.712] <TB2> INFO: 655360 events read in total (14013ms).
[12:53:26.829] <TB2> INFO: Expecting 655360 events.
[12:53:41.155] <TB2> INFO: 655360 events read in total (13923ms).
[12:53:41.267] <TB2> INFO: Expecting 655360 events.
[12:53:55.977] <TB2> INFO: 655360 events read in total (14307ms).
[12:53:56.103] <TB2> INFO: Expecting 655360 events.
[12:54:10.684] <TB2> INFO: 655360 events read in total (14178ms).
[12:54:10.811] <TB2> INFO: Expecting 655360 events.
[12:54:25.224] <TB2> INFO: 655360 events read in total (14010ms).
[12:54:25.326] <TB2> INFO: Test took 231614ms.
[12:54:25.575] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:25.584] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:25.594] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:54:25.604] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:54:25.615] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[12:54:25.625] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[12:54:25.635] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[12:54:25.643] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[12:54:25.651] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[12:54:25.658] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[12:54:25.665] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[12:54:25.672] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[12:54:25.678] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:25.686] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:25.693] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:25.701] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:25.708] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:25.714] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:25.721] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:25.727] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:25.733] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:25.744] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:25.755] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:25.767] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:25.778] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:25.787] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:54:25.793] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:54:25.799] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:54:25.805] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[12:54:25.811] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[12:54:25.817] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[12:54:25.823] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[12:54:25.860] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C0.dat
[12:54:25.860] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C1.dat
[12:54:25.860] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C2.dat
[12:54:25.860] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C3.dat
[12:54:25.860] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C4.dat
[12:54:25.860] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C5.dat
[12:54:25.860] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C6.dat
[12:54:25.860] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C7.dat
[12:54:25.860] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C8.dat
[12:54:25.860] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C9.dat
[12:54:25.860] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C10.dat
[12:54:25.861] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C11.dat
[12:54:25.861] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C12.dat
[12:54:25.861] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C13.dat
[12:54:25.861] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C14.dat
[12:54:25.861] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C15.dat
[12:54:26.116] <TB2> INFO: Expecting 41600 events.
[12:54:29.354] <TB2> INFO: 41600 events read in total (2647ms).
[12:54:29.355] <TB2> INFO: Test took 3491ms.
[12:54:29.817] <TB2> INFO: Expecting 41600 events.
[12:54:32.882] <TB2> INFO: 41600 events read in total (2474ms).
[12:54:32.883] <TB2> INFO: Test took 3314ms.
[12:54:33.340] <TB2> INFO: Expecting 41600 events.
[12:54:36.480] <TB2> INFO: 41600 events read in total (2548ms).
[12:54:36.481] <TB2> INFO: Test took 3387ms.
[12:54:36.697] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:36.786] <TB2> INFO: Expecting 2560 events.
[12:54:37.670] <TB2> INFO: 2560 events read in total (292ms).
[12:54:37.671] <TB2> INFO: Test took 974ms.
[12:54:37.673] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:37.981] <TB2> INFO: Expecting 2560 events.
[12:54:38.868] <TB2> INFO: 2560 events read in total (296ms).
[12:54:38.868] <TB2> INFO: Test took 1195ms.
[12:54:38.871] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:39.176] <TB2> INFO: Expecting 2560 events.
[12:54:40.066] <TB2> INFO: 2560 events read in total (298ms).
[12:54:40.067] <TB2> INFO: Test took 1196ms.
[12:54:40.070] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:40.376] <TB2> INFO: Expecting 2560 events.
[12:54:41.259] <TB2> INFO: 2560 events read in total (292ms).
[12:54:41.260] <TB2> INFO: Test took 1190ms.
[12:54:41.263] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:41.568] <TB2> INFO: Expecting 2560 events.
[12:54:42.462] <TB2> INFO: 2560 events read in total (303ms).
[12:54:42.463] <TB2> INFO: Test took 1200ms.
[12:54:42.466] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:42.771] <TB2> INFO: Expecting 2560 events.
[12:54:43.668] <TB2> INFO: 2560 events read in total (305ms).
[12:54:43.669] <TB2> INFO: Test took 1203ms.
[12:54:43.672] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:43.977] <TB2> INFO: Expecting 2560 events.
[12:54:44.872] <TB2> INFO: 2560 events read in total (303ms).
[12:54:44.872] <TB2> INFO: Test took 1200ms.
[12:54:44.876] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:45.180] <TB2> INFO: Expecting 2560 events.
[12:54:46.066] <TB2> INFO: 2560 events read in total (294ms).
[12:54:46.067] <TB2> INFO: Test took 1191ms.
[12:54:46.069] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:46.376] <TB2> INFO: Expecting 2560 events.
[12:54:47.255] <TB2> INFO: 2560 events read in total (288ms).
[12:54:47.255] <TB2> INFO: Test took 1187ms.
[12:54:47.257] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:47.564] <TB2> INFO: Expecting 2560 events.
[12:54:48.443] <TB2> INFO: 2560 events read in total (287ms).
[12:54:48.443] <TB2> INFO: Test took 1186ms.
[12:54:48.447] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:48.751] <TB2> INFO: Expecting 2560 events.
[12:54:49.630] <TB2> INFO: 2560 events read in total (287ms).
[12:54:49.631] <TB2> INFO: Test took 1184ms.
[12:54:49.635] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:49.939] <TB2> INFO: Expecting 2560 events.
[12:54:50.819] <TB2> INFO: 2560 events read in total (288ms).
[12:54:50.820] <TB2> INFO: Test took 1185ms.
[12:54:50.822] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:51.129] <TB2> INFO: Expecting 2560 events.
[12:54:52.011] <TB2> INFO: 2560 events read in total (291ms).
[12:54:52.011] <TB2> INFO: Test took 1190ms.
[12:54:52.013] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:52.320] <TB2> INFO: Expecting 2560 events.
[12:54:53.201] <TB2> INFO: 2560 events read in total (289ms).
[12:54:53.201] <TB2> INFO: Test took 1188ms.
[12:54:53.204] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:53.510] <TB2> INFO: Expecting 2560 events.
[12:54:54.394] <TB2> INFO: 2560 events read in total (292ms).
[12:54:54.394] <TB2> INFO: Test took 1190ms.
[12:54:54.398] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:54.702] <TB2> INFO: Expecting 2560 events.
[12:54:55.580] <TB2> INFO: 2560 events read in total (287ms).
[12:54:55.580] <TB2> INFO: Test took 1182ms.
[12:54:55.582] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:55.889] <TB2> INFO: Expecting 2560 events.
[12:54:56.779] <TB2> INFO: 2560 events read in total (298ms).
[12:54:56.779] <TB2> INFO: Test took 1197ms.
[12:54:56.781] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:57.087] <TB2> INFO: Expecting 2560 events.
[12:54:57.978] <TB2> INFO: 2560 events read in total (299ms).
[12:54:57.978] <TB2> INFO: Test took 1197ms.
[12:54:57.981] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:58.286] <TB2> INFO: Expecting 2560 events.
[12:54:59.177] <TB2> INFO: 2560 events read in total (299ms).
[12:54:59.178] <TB2> INFO: Test took 1197ms.
[12:54:59.181] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:59.486] <TB2> INFO: Expecting 2560 events.
[12:55:00.378] <TB2> INFO: 2560 events read in total (300ms).
[12:55:00.379] <TB2> INFO: Test took 1199ms.
[12:55:00.382] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:00.687] <TB2> INFO: Expecting 2560 events.
[12:55:01.575] <TB2> INFO: 2560 events read in total (296ms).
[12:55:01.575] <TB2> INFO: Test took 1193ms.
[12:55:01.578] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:01.883] <TB2> INFO: Expecting 2560 events.
[12:55:02.764] <TB2> INFO: 2560 events read in total (289ms).
[12:55:02.764] <TB2> INFO: Test took 1186ms.
[12:55:02.767] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:03.073] <TB2> INFO: Expecting 2560 events.
[12:55:03.956] <TB2> INFO: 2560 events read in total (292ms).
[12:55:03.957] <TB2> INFO: Test took 1190ms.
[12:55:03.959] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:04.266] <TB2> INFO: Expecting 2560 events.
[12:55:05.148] <TB2> INFO: 2560 events read in total (290ms).
[12:55:05.148] <TB2> INFO: Test took 1189ms.
[12:55:05.152] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:05.457] <TB2> INFO: Expecting 2560 events.
[12:55:06.345] <TB2> INFO: 2560 events read in total (297ms).
[12:55:06.345] <TB2> INFO: Test took 1193ms.
[12:55:06.347] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:06.654] <TB2> INFO: Expecting 2560 events.
[12:55:07.541] <TB2> INFO: 2560 events read in total (296ms).
[12:55:07.541] <TB2> INFO: Test took 1194ms.
[12:55:07.544] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:07.849] <TB2> INFO: Expecting 2560 events.
[12:55:08.739] <TB2> INFO: 2560 events read in total (298ms).
[12:55:08.739] <TB2> INFO: Test took 1195ms.
[12:55:08.744] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:09.047] <TB2> INFO: Expecting 2560 events.
[12:55:09.934] <TB2> INFO: 2560 events read in total (295ms).
[12:55:09.934] <TB2> INFO: Test took 1190ms.
[12:55:09.939] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:10.241] <TB2> INFO: Expecting 2560 events.
[12:55:11.129] <TB2> INFO: 2560 events read in total (296ms).
[12:55:11.129] <TB2> INFO: Test took 1190ms.
[12:55:11.132] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:11.439] <TB2> INFO: Expecting 2560 events.
[12:55:12.336] <TB2> INFO: 2560 events read in total (306ms).
[12:55:12.336] <TB2> INFO: Test took 1204ms.
[12:55:12.340] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:12.644] <TB2> INFO: Expecting 2560 events.
[12:55:13.541] <TB2> INFO: 2560 events read in total (305ms).
[12:55:13.542] <TB2> INFO: Test took 1203ms.
[12:55:13.545] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:55:13.850] <TB2> INFO: Expecting 2560 events.
[12:55:14.741] <TB2> INFO: 2560 events read in total (300ms).
[12:55:14.741] <TB2> INFO: Test took 1196ms.
[12:55:15.221] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 650 seconds
[12:55:15.221] <TB2> INFO: PH scale (per ROC): 57 37 54 60 63 56 34 37 59 57 60 64 48 59 49 48
[12:55:15.221] <TB2> INFO: PH offset (per ROC): 91 112 132 118 131 127 103 101 124 135 125 124 97 125 114 121
[12:55:15.229] <TB2> INFO: Decoding statistics:
[12:55:15.229] <TB2> INFO: General information:
[12:55:15.229] <TB2> INFO: 16bit words read: 127880
[12:55:15.229] <TB2> INFO: valid events total: 20480
[12:55:15.229] <TB2> INFO: empty events: 17980
[12:55:15.229] <TB2> INFO: valid events with pixels: 2500
[12:55:15.229] <TB2> INFO: valid pixel hits: 2500
[12:55:15.229] <TB2> INFO: Event errors: 0
[12:55:15.229] <TB2> INFO: start marker: 0
[12:55:15.229] <TB2> INFO: stop marker: 0
[12:55:15.229] <TB2> INFO: overflow: 0
[12:55:15.229] <TB2> INFO: invalid 5bit words: 0
[12:55:15.229] <TB2> INFO: invalid XOR eye diagram: 0
[12:55:15.229] <TB2> INFO: frame (failed synchr.): 0
[12:55:15.229] <TB2> INFO: idle data (no TBM trl): 0
[12:55:15.229] <TB2> INFO: no data (only TBM hdr): 0
[12:55:15.229] <TB2> INFO: TBM errors: 0
[12:55:15.229] <TB2> INFO: flawed TBM headers: 0
[12:55:15.229] <TB2> INFO: flawed TBM trailers: 0
[12:55:15.229] <TB2> INFO: event ID mismatches: 0
[12:55:15.229] <TB2> INFO: ROC errors: 0
[12:55:15.229] <TB2> INFO: missing ROC header(s): 0
[12:55:15.229] <TB2> INFO: misplaced readback start: 0
[12:55:15.229] <TB2> INFO: Pixel decoding errors: 0
[12:55:15.229] <TB2> INFO: pixel data incomplete: 0
[12:55:15.229] <TB2> INFO: pixel address: 0
[12:55:15.229] <TB2> INFO: pulse height fill bit: 0
[12:55:15.229] <TB2> INFO: buffer corruption: 0
[12:55:15.389] <TB2> INFO: ######################################################################
[12:55:15.389] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[12:55:15.389] <TB2> INFO: ######################################################################
[12:55:15.403] <TB2> INFO: scanning low vcal = 10
[12:55:15.641] <TB2> INFO: Expecting 41600 events.
[12:55:19.234] <TB2> INFO: 41600 events read in total (3002ms).
[12:55:19.234] <TB2> INFO: Test took 3831ms.
[12:55:19.237] <TB2> INFO: scanning low vcal = 20
[12:55:19.535] <TB2> INFO: Expecting 41600 events.
[12:55:23.126] <TB2> INFO: 41600 events read in total (2999ms).
[12:55:23.126] <TB2> INFO: Test took 3889ms.
[12:55:23.128] <TB2> INFO: scanning low vcal = 30
[12:55:23.423] <TB2> INFO: Expecting 41600 events.
[12:55:27.067] <TB2> INFO: 41600 events read in total (3052ms).
[12:55:27.068] <TB2> INFO: Test took 3940ms.
[12:55:27.071] <TB2> INFO: scanning low vcal = 40
[12:55:27.348] <TB2> INFO: Expecting 41600 events.
[12:55:31.356] <TB2> INFO: 41600 events read in total (3416ms).
[12:55:31.357] <TB2> INFO: Test took 4286ms.
[12:55:31.361] <TB2> INFO: scanning low vcal = 50
[12:55:31.638] <TB2> INFO: Expecting 41600 events.
[12:55:35.723] <TB2> INFO: 41600 events read in total (3493ms).
[12:55:35.723] <TB2> INFO: Test took 4362ms.
[12:55:35.727] <TB2> INFO: scanning low vcal = 60
[12:55:36.003] <TB2> INFO: Expecting 41600 events.
[12:55:40.056] <TB2> INFO: 41600 events read in total (3461ms).
[12:55:40.057] <TB2> INFO: Test took 4330ms.
[12:55:40.060] <TB2> INFO: scanning low vcal = 70
[12:55:40.337] <TB2> INFO: Expecting 41600 events.
[12:55:44.398] <TB2> INFO: 41600 events read in total (3469ms).
[12:55:44.398] <TB2> INFO: Test took 4338ms.
[12:55:44.401] <TB2> INFO: scanning low vcal = 80
[12:55:44.679] <TB2> INFO: Expecting 41600 events.
[12:55:48.720] <TB2> INFO: 41600 events read in total (3449ms).
[12:55:48.721] <TB2> INFO: Test took 4320ms.
[12:55:48.724] <TB2> INFO: scanning low vcal = 90
[12:55:48.001] <TB2> INFO: Expecting 41600 events.
[12:55:53.044] <TB2> INFO: 41600 events read in total (3451ms).
[12:55:53.045] <TB2> INFO: Test took 4321ms.
[12:55:53.049] <TB2> INFO: scanning low vcal = 100
[12:55:53.326] <TB2> INFO: Expecting 41600 events.
[12:55:57.364] <TB2> INFO: 41600 events read in total (3446ms).
[12:55:57.364] <TB2> INFO: Test took 4314ms.
[12:55:57.367] <TB2> INFO: scanning low vcal = 110
[12:55:57.645] <TB2> INFO: Expecting 41600 events.
[12:56:01.650] <TB2> INFO: 41600 events read in total (3413ms).
[12:56:01.651] <TB2> INFO: Test took 4283ms.
[12:56:01.654] <TB2> INFO: scanning low vcal = 120
[12:56:01.932] <TB2> INFO: Expecting 41600 events.
[12:56:05.990] <TB2> INFO: 41600 events read in total (3468ms).
[12:56:05.991] <TB2> INFO: Test took 4337ms.
[12:56:05.994] <TB2> INFO: scanning low vcal = 130
[12:56:06.272] <TB2> INFO: Expecting 41600 events.
[12:56:10.315] <TB2> INFO: 41600 events read in total (3451ms).
[12:56:10.316] <TB2> INFO: Test took 4321ms.
[12:56:10.319] <TB2> INFO: scanning low vcal = 140
[12:56:10.595] <TB2> INFO: Expecting 41600 events.
[12:56:14.654] <TB2> INFO: 41600 events read in total (3467ms).
[12:56:14.654] <TB2> INFO: Test took 4335ms.
[12:56:14.657] <TB2> INFO: scanning low vcal = 150
[12:56:14.935] <TB2> INFO: Expecting 41600 events.
[12:56:19.004] <TB2> INFO: 41600 events read in total (3478ms).
[12:56:19.005] <TB2> INFO: Test took 4348ms.
[12:56:19.008] <TB2> INFO: scanning low vcal = 160
[12:56:19.285] <TB2> INFO: Expecting 41600 events.
[12:56:23.332] <TB2> INFO: 41600 events read in total (3455ms).
[12:56:23.333] <TB2> INFO: Test took 4325ms.
[12:56:23.336] <TB2> INFO: scanning low vcal = 170
[12:56:23.613] <TB2> INFO: Expecting 41600 events.
[12:56:27.671] <TB2> INFO: 41600 events read in total (3466ms).
[12:56:27.672] <TB2> INFO: Test took 4336ms.
[12:56:27.677] <TB2> INFO: scanning low vcal = 180
[12:56:27.952] <TB2> INFO: Expecting 41600 events.
[12:56:31.981] <TB2> INFO: 41600 events read in total (3438ms).
[12:56:31.982] <TB2> INFO: Test took 4305ms.
[12:56:31.985] <TB2> INFO: scanning low vcal = 190
[12:56:32.262] <TB2> INFO: Expecting 41600 events.
[12:56:36.303] <TB2> INFO: 41600 events read in total (3449ms).
[12:56:36.304] <TB2> INFO: Test took 4319ms.
[12:56:36.307] <TB2> INFO: scanning low vcal = 200
[12:56:36.585] <TB2> INFO: Expecting 41600 events.
[12:56:40.515] <TB2> INFO: 41600 events read in total (3339ms).
[12:56:40.516] <TB2> INFO: Test took 4209ms.
[12:56:40.519] <TB2> INFO: scanning low vcal = 210
[12:56:40.795] <TB2> INFO: Expecting 41600 events.
[12:56:44.738] <TB2> INFO: 41600 events read in total (3351ms).
[12:56:44.739] <TB2> INFO: Test took 4220ms.
[12:56:44.743] <TB2> INFO: scanning low vcal = 220
[12:56:45.019] <TB2> INFO: Expecting 41600 events.
[12:56:48.951] <TB2> INFO: 41600 events read in total (3340ms).
[12:56:48.951] <TB2> INFO: Test took 4208ms.
[12:56:48.954] <TB2> INFO: scanning low vcal = 230
[12:56:49.231] <TB2> INFO: Expecting 41600 events.
[12:56:53.180] <TB2> INFO: 41600 events read in total (3358ms).
[12:56:53.181] <TB2> INFO: Test took 4226ms.
[12:56:53.184] <TB2> INFO: scanning low vcal = 240
[12:56:53.460] <TB2> INFO: Expecting 41600 events.
[12:56:57.401] <TB2> INFO: 41600 events read in total (3349ms).
[12:56:57.401] <TB2> INFO: Test took 4217ms.
[12:56:57.404] <TB2> INFO: scanning low vcal = 250
[12:56:57.681] <TB2> INFO: Expecting 41600 events.
[12:57:01.606] <TB2> INFO: 41600 events read in total (3333ms).
[12:57:01.607] <TB2> INFO: Test took 4202ms.
[12:57:01.611] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[12:57:01.887] <TB2> INFO: Expecting 41600 events.
[12:57:05.832] <TB2> INFO: 41600 events read in total (3353ms).
[12:57:05.832] <TB2> INFO: Test took 4221ms.
[12:57:05.836] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[12:57:06.112] <TB2> INFO: Expecting 41600 events.
[12:57:10.050] <TB2> INFO: 41600 events read in total (3346ms).
[12:57:10.050] <TB2> INFO: Test took 4214ms.
[12:57:10.054] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[12:57:10.330] <TB2> INFO: Expecting 41600 events.
[12:57:14.323] <TB2> INFO: 41600 events read in total (3401ms).
[12:57:14.324] <TB2> INFO: Test took 4270ms.
[12:57:14.328] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[12:57:14.604] <TB2> INFO: Expecting 41600 events.
[12:57:18.614] <TB2> INFO: 41600 events read in total (3418ms).
[12:57:18.615] <TB2> INFO: Test took 4287ms.
[12:57:18.618] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[12:57:18.894] <TB2> INFO: Expecting 41600 events.
[12:57:22.954] <TB2> INFO: 41600 events read in total (3468ms).
[12:57:22.955] <TB2> INFO: Test took 4337ms.
[12:57:23.383] <TB2> INFO: PixTestGainPedestal::measure() done
[12:57:56.907] <TB2> INFO: PixTestGainPedestal::fit() done
[12:57:56.907] <TB2> INFO: non-linearity mean: 0.978 0.986 0.977 0.981 0.981 0.982 1.033 0.974 0.984 0.983 0.985 0.983 0.957 0.977 0.965 0.978
[12:57:56.907] <TB2> INFO: non-linearity RMS: 0.031 0.183 0.004 0.003 0.005 0.004 0.179 0.189 0.004 0.003 0.003 0.004 0.151 0.004 0.016 0.003
[12:57:56.907] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[12:57:56.920] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[12:57:56.935] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[12:57:56.949] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[12:57:56.962] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[12:57:56.975] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[12:57:56.989] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[12:57:56.003] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[12:57:57.017] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[12:57:57.030] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[12:57:57.044] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[12:57:57.057] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[12:57:57.071] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[12:57:57.084] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[12:57:57.098] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[12:57:57.112] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1046_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[12:57:57.125] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 161 seconds
[12:57:57.125] <TB2> INFO: Decoding statistics:
[12:57:57.125] <TB2> INFO: General information:
[12:57:57.125] <TB2> INFO: 16bit words read: 3330906
[12:57:57.125] <TB2> INFO: valid events total: 332800
[12:57:57.125] <TB2> INFO: empty events: 0
[12:57:57.125] <TB2> INFO: valid events with pixels: 332800
[12:57:57.125] <TB2> INFO: valid pixel hits: 667053
[12:57:57.125] <TB2> INFO: Event errors: 0
[12:57:57.125] <TB2> INFO: start marker: 0
[12:57:57.125] <TB2> INFO: stop marker: 0
[12:57:57.125] <TB2> INFO: overflow: 0
[12:57:57.125] <TB2> INFO: invalid 5bit words: 0
[12:57:57.125] <TB2> INFO: invalid XOR eye diagram: 0
[12:57:57.125] <TB2> INFO: frame (failed synchr.): 0
[12:57:57.125] <TB2> INFO: idle data (no TBM trl): 0
[12:57:57.125] <TB2> INFO: no data (only TBM hdr): 0
[12:57:57.125] <TB2> INFO: TBM errors: 0
[12:57:57.125] <TB2> INFO: flawed TBM headers: 0
[12:57:57.125] <TB2> INFO: flawed TBM trailers: 0
[12:57:57.125] <TB2> INFO: event ID mismatches: 0
[12:57:57.125] <TB2> INFO: ROC errors: 0
[12:57:57.125] <TB2> INFO: missing ROC header(s): 0
[12:57:57.125] <TB2> INFO: misplaced readback start: 0
[12:57:57.125] <TB2> INFO: Pixel decoding errors: 0
[12:57:57.125] <TB2> INFO: pixel data incomplete: 0
[12:57:57.125] <TB2> INFO: pixel address: 0
[12:57:57.125] <TB2> INFO: pulse height fill bit: 0
[12:57:57.125] <TB2> INFO: buffer corruption: 0
[12:57:57.142] <TB2> INFO: Decoding statistics:
[12:57:57.142] <TB2> INFO: General information:
[12:57:57.142] <TB2> INFO: 16bit words read: 3460322
[12:57:57.142] <TB2> INFO: valid events total: 353536
[12:57:57.142] <TB2> INFO: empty events: 18236
[12:57:57.142] <TB2> INFO: valid events with pixels: 335300
[12:57:57.142] <TB2> INFO: valid pixel hits: 669553
[12:57:57.142] <TB2> INFO: Event errors: 0
[12:57:57.142] <TB2> INFO: start marker: 0
[12:57:57.142] <TB2> INFO: stop marker: 0
[12:57:57.142] <TB2> INFO: overflow: 0
[12:57:57.142] <TB2> INFO: invalid 5bit words: 0
[12:57:57.142] <TB2> INFO: invalid XOR eye diagram: 0
[12:57:57.142] <TB2> INFO: frame (failed synchr.): 0
[12:57:57.142] <TB2> INFO: idle data (no TBM trl): 0
[12:57:57.142] <TB2> INFO: no data (only TBM hdr): 0
[12:57:57.142] <TB2> INFO: TBM errors: 0
[12:57:57.142] <TB2> INFO: flawed TBM headers: 0
[12:57:57.142] <TB2> INFO: flawed TBM trailers: 0
[12:57:57.142] <TB2> INFO: event ID mismatches: 0
[12:57:57.142] <TB2> INFO: ROC errors: 0
[12:57:57.142] <TB2> INFO: missing ROC header(s): 0
[12:57:57.142] <TB2> INFO: misplaced readback start: 0
[12:57:57.142] <TB2> INFO: Pixel decoding errors: 0
[12:57:57.142] <TB2> INFO: pixel data incomplete: 0
[12:57:57.142] <TB2> INFO: pixel address: 0
[12:57:57.142] <TB2> INFO: pulse height fill bit: 0
[12:57:57.142] <TB2> INFO: buffer corruption: 0
[12:57:57.142] <TB2> INFO: enter test to run
[12:57:57.142] <TB2> INFO: test: exit no parameter change
[12:57:57.270] <TB2> QUIET: Connection to board 149 closed.
[12:57:57.272] <TB2> INFO: pXar: this is the end, my friend