[13:07:58.573] <TB1> INFO: *** Welcome to pxar ***
[13:07:58.573] <TB1> INFO: *** Today: 2016/10/22
[13:07:58.582] <TB1> INFO: *** Version: c8ba-dirty
[13:07:58.582] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C15.dat
[13:07:58.582] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//tbmParameters_C1b.dat
[13:07:58.582] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//defaultMaskFile.dat
[13:07:58.583] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters_C15.dat
[13:07:58.644] <TB1> INFO: clk: 4
[13:07:58.644] <TB1> INFO: ctr: 4
[13:07:58.644] <TB1> INFO: sda: 19
[13:07:58.644] <TB1> INFO: tin: 9
[13:07:58.644] <TB1> INFO: level: 15
[13:07:58.644] <TB1> INFO: triggerdelay: 0
[13:07:58.644] <TB1> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[13:07:58.645] <TB1> INFO: Log level: INFO
[13:07:58.653] <TB1> INFO: Found DTB DTB_WXC03A
[13:07:58.665] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[13:07:58.667] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
------------------------------------------------------
[13:07:58.668] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[13:08:00.158] <TB1> INFO: DUT info:
[13:08:00.158] <TB1> INFO: The DUT currently contains the following objects:
[13:08:00.158] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[13:08:00.158] <TB1> INFO: TBM Core alpha (0): 7 registers set
[13:08:00.158] <TB1> INFO: TBM Core beta (1): 7 registers set
[13:08:00.158] <TB1> INFO: TBM Core alpha (2): 7 registers set
[13:08:00.159] <TB1> INFO: TBM Core beta (3): 7 registers set
[13:08:00.159] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[13:08:00.159] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:00.159] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:00.159] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:00.159] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:00.159] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:00.159] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:00.159] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:00.159] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:00.159] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:00.159] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:00.159] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:00.159] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:00.159] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:00.159] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:00.159] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:00.159] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[13:08:00.559] <TB1> INFO: enter 'restricted' command line mode
[13:08:00.560] <TB1> INFO: enter test to run
[13:08:00.560] <TB1> INFO: test: pretest no parameter change
[13:08:00.560] <TB1> INFO: running: pretest
[13:08:00.565] <TB1> INFO: ######################################################################
[13:08:00.565] <TB1> INFO: PixTestPretest::doTest()
[13:08:00.565] <TB1> INFO: ######################################################################
[13:08:00.566] <TB1> INFO: ----------------------------------------------------------------------
[13:08:00.566] <TB1> INFO: PixTestPretest::programROC()
[13:08:00.566] <TB1> INFO: ----------------------------------------------------------------------
[13:08:18.579] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[13:08:18.579] <TB1> INFO: IA differences per ROC: 18.5 20.1 20.1 18.5 19.3 19.3 17.7 17.7 16.9 17.7 17.7 19.3 19.3 16.1 20.1 18.5
[13:08:18.645] <TB1> INFO: ----------------------------------------------------------------------
[13:08:18.645] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[13:08:18.645] <TB1> INFO: ----------------------------------------------------------------------
[13:08:39.944] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 383.5 mA = 23.9688 mA/ROC
[13:08:39.944] <TB1> INFO: i(loss) [mA/ROC]: 18.5 18.5 20.1 19.3 18.5 18.5 20.1 20.1 20.1 20.1 20.1 19.3 18.5 18.5 17.7 18.5
[13:08:39.980] <TB1> INFO: ----------------------------------------------------------------------
[13:08:39.980] <TB1> INFO: PixTestPretest::findTiming()
[13:08:39.980] <TB1> INFO: ----------------------------------------------------------------------
[13:08:39.980] <TB1> INFO: PixTestCmd::init()

[13:09:12.080] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[13:09:12.080] <TB1> INFO: (success/tries = 100/100), width = 3
[13:09:13.588] <TB1> INFO: ----------------------------------------------------------------------
[13:09:13.588] <TB1> INFO: PixTestPretest::findWorkingPixel()
[13:09:13.588] <TB1> INFO: ----------------------------------------------------------------------
[13:09:13.683] <TB1> INFO: Expecting 231680 events.
[13:09:23.603] <TB1> INFO: 231680 events read in total (9328ms).
[13:09:23.612] <TB1> INFO: Test took 10019ms.
[13:09:23.863] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[13:09:23.896] <TB1> INFO: ----------------------------------------------------------------------
[13:09:23.896] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[13:09:23.896] <TB1> INFO: ----------------------------------------------------------------------
[13:09:23.991] <TB1> INFO: Expecting 231680 events.
[13:09:33.836] <TB1> INFO: 231680 events read in total (9253ms).
[13:09:33.846] <TB1> INFO: Test took 9944ms.
[13:09:34.109] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[13:09:34.109] <TB1> INFO: CalDel: 79 81 91 111 84 99 111 102 95 85 81 80 94 87 86 80
[13:09:34.110] <TB1> INFO: VthrComp: 53 51 53 52 51 51 51 56 51 51 52 51 51 51 51 51
[13:09:34.113] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C0.dat
[13:09:34.114] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C1.dat
[13:09:34.114] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C2.dat
[13:09:34.115] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C3.dat
[13:09:34.115] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C4.dat
[13:09:34.115] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C5.dat
[13:09:34.115] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C6.dat
[13:09:34.115] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C7.dat
[13:09:34.115] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C8.dat
[13:09:34.116] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C9.dat
[13:09:34.116] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C10.dat
[13:09:34.116] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C11.dat
[13:09:34.116] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C12.dat
[13:09:34.116] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C13.dat
[13:09:34.117] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C14.dat
[13:09:34.117] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters_C15.dat
[13:09:34.117] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//tbmParameters_C0a.dat
[13:09:34.117] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//tbmParameters_C0b.dat
[13:09:34.117] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//tbmParameters_C1a.dat
[13:09:34.117] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//tbmParameters_C1b.dat
[13:09:34.117] <TB1> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[13:09:34.170] <TB1> INFO: enter test to run
[13:09:34.170] <TB1> INFO: test: FullTest no parameter change
[13:09:34.170] <TB1> INFO: running: fulltest
[13:09:34.171] <TB1> INFO: ######################################################################
[13:09:34.171] <TB1> INFO: PixTestFullTest::doTest()
[13:09:34.171] <TB1> INFO: ######################################################################
[13:09:34.172] <TB1> INFO: ######################################################################
[13:09:34.172] <TB1> INFO: PixTestAlive::doTest()
[13:09:34.172] <TB1> INFO: ######################################################################
[13:09:34.173] <TB1> INFO: ----------------------------------------------------------------------
[13:09:34.173] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:09:34.173] <TB1> INFO: ----------------------------------------------------------------------
[13:09:34.416] <TB1> INFO: Expecting 41600 events.
[13:09:38.039] <TB1> INFO: 41600 events read in total (3031ms).
[13:09:38.039] <TB1> INFO: Test took 3865ms.
[13:09:38.267] <TB1> INFO: PixTestAlive::aliveTest() done
[13:09:38.267] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:09:38.268] <TB1> INFO: ----------------------------------------------------------------------
[13:09:38.268] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:09:38.268] <TB1> INFO: ----------------------------------------------------------------------
[13:09:38.521] <TB1> INFO: Expecting 41600 events.
[13:09:41.495] <TB1> INFO: 41600 events read in total (2383ms).
[13:09:41.496] <TB1> INFO: Test took 3226ms.
[13:09:41.496] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[13:09:41.733] <TB1> INFO: PixTestAlive::maskTest() done
[13:09:41.733] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:09:41.735] <TB1> INFO: ----------------------------------------------------------------------
[13:09:41.735] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:09:41.735] <TB1> INFO: ----------------------------------------------------------------------
[13:09:42.009] <TB1> INFO: Expecting 41600 events.
[13:09:45.580] <TB1> INFO: 41600 events read in total (2979ms).
[13:09:45.581] <TB1> INFO: Test took 3844ms.
[13:09:45.817] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[13:09:45.817] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:09:45.817] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[13:09:45.817] <TB1> INFO: Decoding statistics:
[13:09:45.817] <TB1> INFO: General information:
[13:09:45.817] <TB1> INFO: 16bit words read: 0
[13:09:45.817] <TB1> INFO: valid events total: 0
[13:09:45.817] <TB1> INFO: empty events: 0
[13:09:45.817] <TB1> INFO: valid events with pixels: 0
[13:09:45.817] <TB1> INFO: valid pixel hits: 0
[13:09:45.817] <TB1> INFO: Event errors: 0
[13:09:45.817] <TB1> INFO: start marker: 0
[13:09:45.817] <TB1> INFO: stop marker: 0
[13:09:45.817] <TB1> INFO: overflow: 0
[13:09:45.817] <TB1> INFO: invalid 5bit words: 0
[13:09:45.817] <TB1> INFO: invalid XOR eye diagram: 0
[13:09:45.817] <TB1> INFO: frame (failed synchr.): 0
[13:09:45.817] <TB1> INFO: idle data (no TBM trl): 0
[13:09:45.817] <TB1> INFO: no data (only TBM hdr): 0
[13:09:45.817] <TB1> INFO: TBM errors: 0
[13:09:45.817] <TB1> INFO: flawed TBM headers: 0
[13:09:45.817] <TB1> INFO: flawed TBM trailers: 0
[13:09:45.817] <TB1> INFO: event ID mismatches: 0
[13:09:45.817] <TB1> INFO: ROC errors: 0
[13:09:45.817] <TB1> INFO: missing ROC header(s): 0
[13:09:45.818] <TB1> INFO: misplaced readback start: 0
[13:09:45.818] <TB1> INFO: Pixel decoding errors: 0
[13:09:45.818] <TB1> INFO: pixel data incomplete: 0
[13:09:45.818] <TB1> INFO: pixel address: 0
[13:09:45.818] <TB1> INFO: pulse height fill bit: 0
[13:09:45.818] <TB1> INFO: buffer corruption: 0
[13:09:45.826] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C15.dat
[13:09:45.826] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr_C15.dat

[13:09:45.826] <TB1> INFO: ######################################################################
[13:09:45.826] <TB1> INFO: PixTestReadback::doTest()
[13:09:45.826] <TB1> INFO: ######################################################################
[13:09:45.826] <TB1> INFO: ----------------------------------------------------------------------
[13:09:45.826] <TB1> INFO: PixTestReadback::CalibrateVd()
[13:09:45.826] <TB1> INFO: ----------------------------------------------------------------------
[13:09:55.809] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C0.dat
[13:09:55.809] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C1.dat
[13:09:55.809] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C2.dat
[13:09:55.809] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C3.dat
[13:09:55.809] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C4.dat
[13:09:55.809] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C5.dat
[13:09:55.810] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C6.dat
[13:09:55.810] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C7.dat
[13:09:55.810] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C8.dat
[13:09:55.810] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C9.dat
[13:09:55.810] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C10.dat
[13:09:55.810] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C11.dat
[13:09:55.810] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C12.dat
[13:09:55.810] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C13.dat
[13:09:55.810] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C14.dat
[13:09:55.810] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C15.dat
[13:09:55.841] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[13:09:55.841] <TB1> INFO: ----------------------------------------------------------------------
[13:09:55.841] <TB1> INFO: PixTestReadback::CalibrateVa()
[13:09:55.842] <TB1> INFO: ----------------------------------------------------------------------
[13:10:05.763] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C0.dat
[13:10:05.763] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C1.dat
[13:10:05.763] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C2.dat
[13:10:05.763] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C3.dat
[13:10:05.763] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C4.dat
[13:10:05.763] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C5.dat
[13:10:05.763] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C6.dat
[13:10:05.763] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C7.dat
[13:10:05.763] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C8.dat
[13:10:05.763] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C9.dat
[13:10:05.764] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C10.dat
[13:10:05.764] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C11.dat
[13:10:05.764] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C12.dat
[13:10:05.764] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C13.dat
[13:10:05.764] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C14.dat
[13:10:05.764] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C15.dat
[13:10:05.795] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[13:10:05.795] <TB1> INFO: ----------------------------------------------------------------------
[13:10:05.795] <TB1> INFO: PixTestReadback::readbackVbg()
[13:10:05.795] <TB1> INFO: ----------------------------------------------------------------------
[13:10:13.462] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[13:10:13.462] <TB1> INFO: ----------------------------------------------------------------------
[13:10:13.462] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[13:10:13.462] <TB1> INFO: ----------------------------------------------------------------------
[13:10:13.462] <TB1> INFO: Vbg will be calibrated using Vd calibration
[13:10:13.462] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 160.4calibrated Vbg = 1.19644 :::*/*/*/*/
[13:10:13.462] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 159calibrated Vbg = 1.18836 :::*/*/*/*/
[13:10:13.463] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 147.6calibrated Vbg = 1.1931 :::*/*/*/*/
[13:10:13.463] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 155.1calibrated Vbg = 1.19473 :::*/*/*/*/
[13:10:13.463] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 155.3calibrated Vbg = 1.19982 :::*/*/*/*/
[13:10:13.463] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 149.8calibrated Vbg = 1.19812 :::*/*/*/*/
[13:10:13.463] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 153.1calibrated Vbg = 1.20392 :::*/*/*/*/
[13:10:13.463] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 171.8calibrated Vbg = 1.20079 :::*/*/*/*/
[13:10:13.463] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 152.6calibrated Vbg = 1.19193 :::*/*/*/*/
[13:10:13.463] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 155.7calibrated Vbg = 1.19061 :::*/*/*/*/
[13:10:13.463] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 156.3calibrated Vbg = 1.18612 :::*/*/*/*/
[13:10:13.463] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 154.3calibrated Vbg = 1.17927 :::*/*/*/*/
[13:10:13.463] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 159calibrated Vbg = 1.18608 :::*/*/*/*/
[13:10:13.463] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 156.7calibrated Vbg = 1.19708 :::*/*/*/*/
[13:10:13.463] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 162.4calibrated Vbg = 1.19844 :::*/*/*/*/
[13:10:13.463] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 156.8calibrated Vbg = 1.1955 :::*/*/*/*/
[13:10:13.465] <TB1> INFO: ----------------------------------------------------------------------
[13:10:13.466] <TB1> INFO: PixTestReadback::CalibrateIa()
[13:10:13.466] <TB1> INFO: ----------------------------------------------------------------------
[13:12:54.282] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C0.dat
[13:12:54.282] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C1.dat
[13:12:54.282] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C2.dat
[13:12:54.282] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C3.dat
[13:12:54.282] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C4.dat
[13:12:54.282] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C5.dat
[13:12:54.282] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C6.dat
[13:12:54.282] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C7.dat
[13:12:54.282] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C8.dat
[13:12:54.282] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C9.dat
[13:12:54.282] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C10.dat
[13:12:54.282] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C11.dat
[13:12:54.283] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C12.dat
[13:12:54.283] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C13.dat
[13:12:54.283] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C14.dat
[13:12:54.283] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//readbackCal_C15.dat
[13:12:54.312] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[13:12:54.314] <TB1> INFO: PixTestReadback::doTest() done
[13:12:54.314] <TB1> INFO: Decoding statistics:
[13:12:54.314] <TB1> INFO: General information:
[13:12:54.314] <TB1> INFO: 16bit words read: 1536
[13:12:54.314] <TB1> INFO: valid events total: 256
[13:12:54.314] <TB1> INFO: empty events: 256
[13:12:54.314] <TB1> INFO: valid events with pixels: 0
[13:12:54.314] <TB1> INFO: valid pixel hits: 0
[13:12:54.314] <TB1> INFO: Event errors: 0
[13:12:54.314] <TB1> INFO: start marker: 0
[13:12:54.314] <TB1> INFO: stop marker: 0
[13:12:54.314] <TB1> INFO: overflow: 0
[13:12:54.314] <TB1> INFO: invalid 5bit words: 0
[13:12:54.314] <TB1> INFO: invalid XOR eye diagram: 0
[13:12:54.314] <TB1> INFO: frame (failed synchr.): 0
[13:12:54.314] <TB1> INFO: idle data (no TBM trl): 0
[13:12:54.314] <TB1> INFO: no data (only TBM hdr): 0
[13:12:54.314] <TB1> INFO: TBM errors: 0
[13:12:54.314] <TB1> INFO: flawed TBM headers: 0
[13:12:54.314] <TB1> INFO: flawed TBM trailers: 0
[13:12:54.314] <TB1> INFO: event ID mismatches: 0
[13:12:54.314] <TB1> INFO: ROC errors: 0
[13:12:54.315] <TB1> INFO: missing ROC header(s): 0
[13:12:54.315] <TB1> INFO: misplaced readback start: 0
[13:12:54.315] <TB1> INFO: Pixel decoding errors: 0
[13:12:54.315] <TB1> INFO: pixel data incomplete: 0
[13:12:54.315] <TB1> INFO: pixel address: 0
[13:12:54.315] <TB1> INFO: pulse height fill bit: 0
[13:12:54.315] <TB1> INFO: buffer corruption: 0
[13:12:54.363] <TB1> INFO: ######################################################################
[13:12:54.363] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[13:12:54.363] <TB1> INFO: ######################################################################
[13:12:54.366] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[13:12:54.380] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:12:54.381] <TB1> INFO: run 1 of 1
[13:12:54.621] <TB1> INFO: Expecting 3120000 events.
[13:13:25.344] <TB1> INFO: 669155 events read in total (30131ms).











[13:13:55.425] <TB1> INFO: 1331160 events read in total (60213ms).











[13:14:25.274] <TB1> INFO: 1987415 events read in total (90061ms).











[13:14:55.149] <TB1> INFO: 2643320 events read in total (119936ms).











[13:15:17.022] <TB1> INFO: 3120000 events read in total (141809ms).
[13:15:17.110] <TB1> INFO: Test took 142730ms.
[13:15:39.690] <TB1> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 165 seconds
[13:15:39.690] <TB1> INFO: number of dead bumps (per ROC): 0 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0
[13:15:39.690] <TB1> INFO: separation cut (per ROC): 104 106 107 96 107 99 92 109 107 104 121 110 105 99 97 103
[13:15:39.690] <TB1> INFO: Decoding statistics:
[13:15:39.690] <TB1> INFO: General information:
[13:15:39.690] <TB1> INFO: 16bit words read: 0
[13:15:39.690] <TB1> INFO: valid events total: 0
[13:15:39.690] <TB1> INFO: empty events: 0
[13:15:39.690] <TB1> INFO: valid events with pixels: 0
[13:15:39.690] <TB1> INFO: valid pixel hits: 0
[13:15:39.690] <TB1> INFO: Event errors: 0
[13:15:39.690] <TB1> INFO: start marker: 0
[13:15:39.690] <TB1> INFO: stop marker: 0
[13:15:39.690] <TB1> INFO: overflow: 0
[13:15:39.690] <TB1> INFO: invalid 5bit words: 0
[13:15:39.690] <TB1> INFO: invalid XOR eye diagram: 0
[13:15:39.690] <TB1> INFO: frame (failed synchr.): 0
[13:15:39.690] <TB1> INFO: idle data (no TBM trl): 0
[13:15:39.690] <TB1> INFO: no data (only TBM hdr): 0
[13:15:39.690] <TB1> INFO: TBM errors: 0
[13:15:39.690] <TB1> INFO: flawed TBM headers: 0
[13:15:39.690] <TB1> INFO: flawed TBM trailers: 0
[13:15:39.690] <TB1> INFO: event ID mismatches: 0
[13:15:39.690] <TB1> INFO: ROC errors: 0
[13:15:39.690] <TB1> INFO: missing ROC header(s): 0
[13:15:39.690] <TB1> INFO: misplaced readback start: 0
[13:15:39.690] <TB1> INFO: Pixel decoding errors: 0
[13:15:39.690] <TB1> INFO: pixel data incomplete: 0
[13:15:39.690] <TB1> INFO: pixel address: 0
[13:15:39.690] <TB1> INFO: pulse height fill bit: 0
[13:15:39.690] <TB1> INFO: buffer corruption: 0
[13:15:39.737] <TB1> INFO: ######################################################################
[13:15:39.737] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:15:39.738] <TB1> INFO: ######################################################################
[13:15:39.738] <TB1> INFO: ----------------------------------------------------------------------
[13:15:39.738] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[13:15:39.738] <TB1> INFO: ----------------------------------------------------------------------
[13:15:39.738] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[13:15:39.753] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[13:15:39.753] <TB1> INFO: run 1 of 1
[13:15:40.014] <TB1> INFO: Expecting 36608000 events.
[13:16:03.001] <TB1> INFO: 701600 events read in total (23396ms).
[13:16:26.874] <TB1> INFO: 1381600 events read in total (46270ms).
[13:16:49.699] <TB1> INFO: 2064050 events read in total (69094ms).
[13:17:12.723] <TB1> INFO: 2742600 events read in total (92118ms).
[13:17:35.542] <TB1> INFO: 3421300 events read in total (114937ms).
[13:17:59.081] <TB1> INFO: 4099800 events read in total (138476ms).
[13:18:22.035] <TB1> INFO: 4777700 events read in total (161430ms).
[13:18:44.912] <TB1> INFO: 5453450 events read in total (184307ms).
[13:19:07.916] <TB1> INFO: 6133050 events read in total (207311ms).
[13:19:31.085] <TB1> INFO: 6814800 events read in total (230480ms).
[13:19:53.929] <TB1> INFO: 7492350 events read in total (253324ms).
[13:20:16.809] <TB1> INFO: 8167750 events read in total (276204ms).
[13:20:40.017] <TB1> INFO: 8846800 events read in total (299412ms).
[13:21:02.973] <TB1> INFO: 9524700 events read in total (322368ms).
[13:21:25.875] <TB1> INFO: 10201250 events read in total (345270ms).
[13:21:48.534] <TB1> INFO: 10875350 events read in total (367929ms).
[13:22:11.625] <TB1> INFO: 11549700 events read in total (391020ms).
[13:22:34.610] <TB1> INFO: 12222800 events read in total (414005ms).
[13:22:57.355] <TB1> INFO: 12896150 events read in total (436750ms).
[13:23:20.078] <TB1> INFO: 13568350 events read in total (459473ms).
[13:23:42.652] <TB1> INFO: 14238800 events read in total (482047ms).
[13:24:05.431] <TB1> INFO: 14911800 events read in total (504826ms).
[13:24:28.555] <TB1> INFO: 15582850 events read in total (527950ms).
[13:24:51.636] <TB1> INFO: 16254050 events read in total (551031ms).
[13:25:14.516] <TB1> INFO: 16927400 events read in total (573911ms).
[13:25:37.392] <TB1> INFO: 17597950 events read in total (596787ms).
[13:26:00.102] <TB1> INFO: 18266900 events read in total (619497ms).
[13:26:22.682] <TB1> INFO: 18934450 events read in total (642077ms).
[13:26:45.559] <TB1> INFO: 19602500 events read in total (664954ms).
[13:27:08.406] <TB1> INFO: 20271500 events read in total (687801ms).
[13:27:30.855] <TB1> INFO: 20939100 events read in total (710250ms).
[13:27:53.687] <TB1> INFO: 21606200 events read in total (733082ms).
[13:28:16.436] <TB1> INFO: 22271050 events read in total (755831ms).
[13:28:39.486] <TB1> INFO: 22938550 events read in total (778881ms).
[13:29:02.155] <TB1> INFO: 23606850 events read in total (801550ms).
[13:29:25.069] <TB1> INFO: 24273950 events read in total (824464ms).
[13:29:47.769] <TB1> INFO: 24939350 events read in total (847164ms).
[13:30:10.394] <TB1> INFO: 25606750 events read in total (869789ms).
[13:30:33.044] <TB1> INFO: 26274050 events read in total (892439ms).
[13:30:55.914] <TB1> INFO: 26941100 events read in total (915309ms).
[13:31:18.644] <TB1> INFO: 27605850 events read in total (938039ms).
[13:31:41.583] <TB1> INFO: 28272350 events read in total (960978ms).
[13:32:04.038] <TB1> INFO: 28937700 events read in total (983433ms).
[13:32:26.583] <TB1> INFO: 29602050 events read in total (1005978ms).
[13:32:49.838] <TB1> INFO: 30268450 events read in total (1029233ms).
[13:33:12.726] <TB1> INFO: 30932950 events read in total (1052121ms).
[13:33:35.623] <TB1> INFO: 31598950 events read in total (1075018ms).
[13:33:58.458] <TB1> INFO: 32266100 events read in total (1097853ms).
[13:34:21.158] <TB1> INFO: 32931550 events read in total (1120553ms).
[13:34:44.076] <TB1> INFO: 33596950 events read in total (1143471ms).
[13:35:07.122] <TB1> INFO: 34263850 events read in total (1166517ms).
[13:35:30.190] <TB1> INFO: 34931050 events read in total (1189585ms).
[13:35:52.885] <TB1> INFO: 35597450 events read in total (1212280ms).
[13:36:15.708] <TB1> INFO: 36272300 events read in total (1235103ms).
[13:36:26.961] <TB1> INFO: 36608000 events read in total (1246356ms).
[13:36:27.022] <TB1> INFO: Test took 1247269ms.
[13:36:27.525] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:36:29.454] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:36:31.455] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:36:33.639] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:36:35.514] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:36:37.353] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:36:39.072] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:36:40.577] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:36:42.100] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:36:43.003] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:36:46.474] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:36:48.978] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:36:51.293] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:36:53.499] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:36:55.391] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:36:57.406] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:36:58.001] <TB1> INFO: PixTestScurves::scurves() done
[13:36:58.001] <TB1> INFO: Vcal mean: 128.92 124.17 129.01 124.87 121.37 115.14 112.28 129.39 115.43 118.26 131.16 126.02 119.93 117.77 113.45 118.89
[13:36:58.001] <TB1> INFO: Vcal RMS: 5.74 5.73 7.06 6.41 6.25 5.64 4.97 6.82 5.90 6.02 6.43 6.22 5.87 5.37 5.88 5.58
[13:36:58.001] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1279 seconds
[13:36:58.001] <TB1> INFO: Decoding statistics:
[13:36:58.001] <TB1> INFO: General information:
[13:36:58.001] <TB1> INFO: 16bit words read: 0
[13:36:58.001] <TB1> INFO: valid events total: 0
[13:36:58.001] <TB1> INFO: empty events: 0
[13:36:58.001] <TB1> INFO: valid events with pixels: 0
[13:36:58.001] <TB1> INFO: valid pixel hits: 0
[13:36:58.001] <TB1> INFO: Event errors: 0
[13:36:58.001] <TB1> INFO: start marker: 0
[13:36:58.001] <TB1> INFO: stop marker: 0
[13:36:58.001] <TB1> INFO: overflow: 0
[13:36:58.001] <TB1> INFO: invalid 5bit words: 0
[13:36:58.001] <TB1> INFO: invalid XOR eye diagram: 0
[13:36:58.001] <TB1> INFO: frame (failed synchr.): 0
[13:36:58.001] <TB1> INFO: idle data (no TBM trl): 0
[13:36:58.001] <TB1> INFO: no data (only TBM hdr): 0
[13:36:58.001] <TB1> INFO: TBM errors: 0
[13:36:58.001] <TB1> INFO: flawed TBM headers: 0
[13:36:58.001] <TB1> INFO: flawed TBM trailers: 0
[13:36:58.001] <TB1> INFO: event ID mismatches: 0
[13:36:58.001] <TB1> INFO: ROC errors: 0
[13:36:58.001] <TB1> INFO: missing ROC header(s): 0
[13:36:58.001] <TB1> INFO: misplaced readback start: 0
[13:36:58.001] <TB1> INFO: Pixel decoding errors: 0
[13:36:58.001] <TB1> INFO: pixel data incomplete: 0
[13:36:58.001] <TB1> INFO: pixel address: 0
[13:36:58.001] <TB1> INFO: pulse height fill bit: 0
[13:36:58.001] <TB1> INFO: buffer corruption: 0
[13:36:59.073] <TB1> INFO: ######################################################################
[13:36:59.073] <TB1> INFO: PixTestTrim::doTest()
[13:36:59.073] <TB1> INFO: ######################################################################
[13:36:59.074] <TB1> INFO: ----------------------------------------------------------------------
[13:36:59.074] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[13:36:59.074] <TB1> INFO: ----------------------------------------------------------------------
[13:36:59.116] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:36:59.116] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:36:59.130] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:36:59.130] <TB1> INFO: run 1 of 1
[13:36:59.371] <TB1> INFO: Expecting 5025280 events.
[13:37:30.277] <TB1> INFO: 829552 events read in total (30309ms).
[13:38:00.419] <TB1> INFO: 1656136 events read in total (60451ms).
[13:38:30.280] <TB1> INFO: 2480768 events read in total (90312ms).
[13:39:00.423] <TB1> INFO: 3300392 events read in total (120455ms).
[13:39:30.140] <TB1> INFO: 4116256 events read in total (150172ms).
[13:40:00.140] <TB1> INFO: 4931192 events read in total (180172ms).
[13:40:04.046] <TB1> INFO: 5025280 events read in total (184078ms).
[13:40:04.100] <TB1> INFO: Test took 184969ms.
[13:40:23.653] <TB1> INFO: ROC 0 VthrComp = 133
[13:40:23.653] <TB1> INFO: ROC 1 VthrComp = 128
[13:40:23.653] <TB1> INFO: ROC 2 VthrComp = 132
[13:40:23.653] <TB1> INFO: ROC 3 VthrComp = 116
[13:40:23.654] <TB1> INFO: ROC 4 VthrComp = 124
[13:40:23.654] <TB1> INFO: ROC 5 VthrComp = 113
[13:40:23.654] <TB1> INFO: ROC 6 VthrComp = 111
[13:40:23.654] <TB1> INFO: ROC 7 VthrComp = 124
[13:40:23.654] <TB1> INFO: ROC 8 VthrComp = 119
[13:40:23.654] <TB1> INFO: ROC 9 VthrComp = 122
[13:40:23.654] <TB1> INFO: ROC 10 VthrComp = 132
[13:40:23.654] <TB1> INFO: ROC 11 VthrComp = 127
[13:40:23.655] <TB1> INFO: ROC 12 VthrComp = 119
[13:40:23.655] <TB1> INFO: ROC 13 VthrComp = 113
[13:40:23.655] <TB1> INFO: ROC 14 VthrComp = 112
[13:40:23.655] <TB1> INFO: ROC 15 VthrComp = 118
[13:40:23.893] <TB1> INFO: Expecting 41600 events.
[13:40:27.353] <TB1> INFO: 41600 events read in total (2868ms).
[13:40:27.354] <TB1> INFO: Test took 3698ms.
[13:40:27.363] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:40:27.363] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:40:27.374] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:40:27.374] <TB1> INFO: run 1 of 1
[13:40:27.652] <TB1> INFO: Expecting 5025280 events.
[13:40:54.317] <TB1> INFO: 590872 events read in total (26073ms).
[13:41:19.880] <TB1> INFO: 1180760 events read in total (51636ms).
[13:41:45.614] <TB1> INFO: 1770520 events read in total (77370ms).
[13:42:11.112] <TB1> INFO: 2360248 events read in total (102868ms).
[13:42:36.520] <TB1> INFO: 2947936 events read in total (128276ms).
[13:43:02.193] <TB1> INFO: 3533960 events read in total (153949ms).
[13:43:27.668] <TB1> INFO: 4119856 events read in total (179424ms).
[13:43:53.180] <TB1> INFO: 4705192 events read in total (204936ms).
[13:44:07.586] <TB1> INFO: 5025280 events read in total (219342ms).
[13:44:07.659] <TB1> INFO: Test took 220284ms.
[13:44:36.126] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 61.4441 for pixel 50/0 mean/min/max = 46.1548/30.686/61.6237
[13:44:36.127] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 59.031 for pixel 27/17 mean/min/max = 45.4488/31.6449/59.2526
[13:44:36.127] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 62.0651 for pixel 0/16 mean/min/max = 46.8245/31.4981/62.1508
[13:44:36.128] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 65.8106 for pixel 47/1 mean/min/max = 48.9572/31.9363/65.9781
[13:44:36.128] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 60.7823 for pixel 0/14 mean/min/max = 46.6521/32.5189/60.7853
[13:44:36.129] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 60.9289 for pixel 6/38 mean/min/max = 46.5749/32.0284/61.1214
[13:44:36.130] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 64.1624 for pixel 25/2 mean/min/max = 49.1314/33.8332/64.4297
[13:44:36.130] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 67.6826 for pixel 13/78 mean/min/max = 49.0517/30.3787/67.7247
[13:44:36.131] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 61.1208 for pixel 14/18 mean/min/max = 46.1572/31.1023/61.2122
[13:44:36.131] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 60.2203 for pixel 16/1 mean/min/max = 46.4374/32.4837/60.3911
[13:44:36.132] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 64.907 for pixel 8/6 mean/min/max = 50.1687/35.3407/64.9966
[13:44:36.132] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 59.6466 for pixel 51/14 mean/min/max = 45.9411/32.0328/59.8494
[13:44:36.133] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 59.9234 for pixel 12/8 mean/min/max = 46.094/32.2517/59.9363
[13:44:36.133] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 61.3493 for pixel 17/3 mean/min/max = 47.493/33.2888/61.6972
[13:44:36.133] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 63.5301 for pixel 0/12 mean/min/max = 47.9239/32.24/63.6077
[13:44:36.134] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 60.6046 for pixel 2/14 mean/min/max = 46.1002/31.5684/60.6319
[13:44:36.134] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:44:36.223] <TB1> INFO: Expecting 411648 events.
[13:44:45.624] <TB1> INFO: 411648 events read in total (8810ms).
[13:44:45.634] <TB1> INFO: Expecting 411648 events.
[13:44:54.978] <TB1> INFO: 411648 events read in total (8941ms).
[13:44:54.989] <TB1> INFO: Expecting 411648 events.
[13:45:04.250] <TB1> INFO: 411648 events read in total (8858ms).
[13:45:04.269] <TB1> INFO: Expecting 411648 events.
[13:45:13.598] <TB1> INFO: 411648 events read in total (8926ms).
[13:45:13.613] <TB1> INFO: Expecting 411648 events.
[13:45:22.931] <TB1> INFO: 411648 events read in total (8914ms).
[13:45:22.951] <TB1> INFO: Expecting 411648 events.
[13:45:32.233] <TB1> INFO: 411648 events read in total (8879ms).
[13:45:32.255] <TB1> INFO: Expecting 411648 events.
[13:45:41.654] <TB1> INFO: 411648 events read in total (8996ms).
[13:45:41.680] <TB1> INFO: Expecting 411648 events.
[13:45:50.924] <TB1> INFO: 411648 events read in total (8841ms).
[13:45:50.951] <TB1> INFO: Expecting 411648 events.
[13:46:00.211] <TB1> INFO: 411648 events read in total (8857ms).
[13:46:00.241] <TB1> INFO: Expecting 411648 events.
[13:46:09.635] <TB1> INFO: 411648 events read in total (8991ms).
[13:46:09.671] <TB1> INFO: Expecting 411648 events.
[13:46:18.962] <TB1> INFO: 411648 events read in total (8888ms).
[13:46:19.010] <TB1> INFO: Expecting 411648 events.
[13:46:28.296] <TB1> INFO: 411648 events read in total (8883ms).
[13:46:28.348] <TB1> INFO: Expecting 411648 events.
[13:46:37.664] <TB1> INFO: 411648 events read in total (8913ms).
[13:46:37.718] <TB1> INFO: Expecting 411648 events.
[13:46:47.024] <TB1> INFO: 411648 events read in total (8903ms).
[13:46:47.085] <TB1> INFO: Expecting 411648 events.
[13:46:56.394] <TB1> INFO: 411648 events read in total (8906ms).
[13:46:56.440] <TB1> INFO: Expecting 411648 events.
[13:47:05.668] <TB1> INFO: 411648 events read in total (8825ms).
[13:47:05.736] <TB1> INFO: Test took 149602ms.
[13:47:06.526] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:47:06.539] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:47:06.539] <TB1> INFO: run 1 of 1
[13:47:06.777] <TB1> INFO: Expecting 5025280 events.
[13:47:33.183] <TB1> INFO: 588288 events read in total (25814ms).
[13:47:58.903] <TB1> INFO: 1175576 events read in total (51534ms).
[13:48:24.925] <TB1> INFO: 1762776 events read in total (77556ms).
[13:48:51.061] <TB1> INFO: 2348320 events read in total (103692ms).
[13:49:16.952] <TB1> INFO: 2935752 events read in total (129583ms).
[13:49:43.344] <TB1> INFO: 3524896 events read in total (155975ms).
[13:50:09.634] <TB1> INFO: 4113128 events read in total (182265ms).
[13:50:35.871] <TB1> INFO: 4702416 events read in total (208502ms).
[13:50:50.325] <TB1> INFO: 5025280 events read in total (222956ms).
[13:50:50.440] <TB1> INFO: Test took 223901ms.
[13:51:12.868] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 9.628263 .. 147.668542
[13:51:13.158] <TB1> INFO: Expecting 208000 events.
[13:51:22.885] <TB1> INFO: 208000 events read in total (9135ms).
[13:51:22.886] <TB1> INFO: Test took 10016ms.
[13:51:22.937] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 9 .. 157 (-1/-1) hits flags = 528 (plus default)
[13:51:22.950] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:51:22.950] <TB1> INFO: run 1 of 1
[13:51:23.228] <TB1> INFO: Expecting 4958720 events.
[13:51:49.415] <TB1> INFO: 573832 events read in total (25595ms).
[13:52:15.363] <TB1> INFO: 1147448 events read in total (51543ms).
[13:52:41.366] <TB1> INFO: 1720936 events read in total (77547ms).
[13:53:07.160] <TB1> INFO: 2294192 events read in total (103340ms).
[13:53:33.351] <TB1> INFO: 2867480 events read in total (129531ms).
[13:53:59.341] <TB1> INFO: 3440512 events read in total (155521ms).
[13:54:24.947] <TB1> INFO: 4013424 events read in total (181127ms).
[13:54:50.228] <TB1> INFO: 4585552 events read in total (206408ms).
[13:55:07.150] <TB1> INFO: 4958720 events read in total (223330ms).
[13:55:07.259] <TB1> INFO: Test took 224308ms.
[13:55:34.500] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.663997 .. 46.177550
[13:55:34.775] <TB1> INFO: Expecting 208000 events.
[13:55:44.479] <TB1> INFO: 208000 events read in total (9112ms).
[13:55:44.480] <TB1> INFO: Test took 9978ms.
[13:55:44.529] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[13:55:44.543] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:55:44.543] <TB1> INFO: run 1 of 1
[13:55:44.821] <TB1> INFO: Expecting 1331200 events.
[13:56:12.904] <TB1> INFO: 656800 events read in total (27491ms).
[13:56:40.549] <TB1> INFO: 1311616 events read in total (55136ms).
[13:56:41.885] <TB1> INFO: 1331200 events read in total (56473ms).
[13:56:41.917] <TB1> INFO: Test took 57374ms.
[13:56:54.319] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 26.040689 .. 50.966760
[13:56:54.582] <TB1> INFO: Expecting 208000 events.
[13:57:04.846] <TB1> INFO: 208000 events read in total (9672ms).
[13:57:04.847] <TB1> INFO: Test took 10526ms.
[13:57:04.910] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 60 (-1/-1) hits flags = 528 (plus default)
[13:57:04.925] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:57:04.925] <TB1> INFO: run 1 of 1
[13:57:05.203] <TB1> INFO: Expecting 1497600 events.
[13:57:32.823] <TB1> INFO: 647800 events read in total (27029ms).
[13:58:00.163] <TB1> INFO: 1294024 events read in total (54370ms).
[13:58:09.184] <TB1> INFO: 1497600 events read in total (63390ms).
[13:58:09.216] <TB1> INFO: Test took 64292ms.
[13:58:24.352] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 26.548254 .. 56.913077
[13:58:24.590] <TB1> INFO: Expecting 208000 events.
[13:58:34.244] <TB1> INFO: 208000 events read in total (9063ms).
[13:58:34.245] <TB1> INFO: Test took 9891ms.
[13:58:34.292] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 66 (-1/-1) hits flags = 528 (plus default)
[13:58:34.305] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:58:34.305] <TB1> INFO: run 1 of 1
[13:58:34.583] <TB1> INFO: Expecting 1697280 events.
[13:59:02.264] <TB1> INFO: 629936 events read in total (27089ms).
[13:59:29.161] <TB1> INFO: 1260120 events read in total (53986ms).
[13:59:47.554] <TB1> INFO: 1697280 events read in total (72379ms).
[13:59:47.589] <TB1> INFO: Test took 73285ms.
[14:00:02.807] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:00:02.808] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:00:02.822] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[14:00:02.822] <TB1> INFO: run 1 of 1
[14:00:03.093] <TB1> INFO: Expecting 1364480 events.
[14:00:31.941] <TB1> INFO: 667792 events read in total (28256ms).
[14:00:59.979] <TB1> INFO: 1335640 events read in total (56294ms).
[14:01:01.601] <TB1> INFO: 1364480 events read in total (57917ms).
[14:01:01.630] <TB1> INFO: Test took 58808ms.
[14:01:13.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C0.dat
[14:01:13.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C1.dat
[14:01:13.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C2.dat
[14:01:13.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C3.dat
[14:01:13.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C4.dat
[14:01:13.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C5.dat
[14:01:13.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C6.dat
[14:01:13.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C7.dat
[14:01:13.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C8.dat
[14:01:13.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C9.dat
[14:01:13.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C10.dat
[14:01:13.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C11.dat
[14:01:13.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C12.dat
[14:01:13.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C13.dat
[14:01:13.851] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C14.dat
[14:01:13.852] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C15.dat
[14:01:13.852] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C0.dat
[14:01:13.856] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C1.dat
[14:01:13.861] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C2.dat
[14:01:13.866] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C3.dat
[14:01:13.871] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C4.dat
[14:01:13.876] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C5.dat
[14:01:13.880] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C6.dat
[14:01:13.885] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C7.dat
[14:01:13.890] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C8.dat
[14:01:13.895] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C9.dat
[14:01:13.899] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C10.dat
[14:01:13.904] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C11.dat
[14:01:13.909] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C12.dat
[14:01:13.914] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C13.dat
[14:01:13.919] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C14.dat
[14:01:13.923] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//trimParameters35_C15.dat
[14:01:13.928] <TB1> INFO: PixTestTrim::trimTest() done
[14:01:13.928] <TB1> INFO: vtrim: 146 126 139 146 124 130 141 134 124 148 159 123 121 117 132 123
[14:01:13.928] <TB1> INFO: vthrcomp: 133 128 132 116 124 113 111 124 119 122 132 127 119 113 112 118
[14:01:13.928] <TB1> INFO: vcal mean: 35.34 34.98 35.08 36.42 34.94 34.97 34.97 35.29 34.94 34.93 35.05 34.94 34.99 34.94 35.15 34.96
[14:01:13.928] <TB1> INFO: vcal RMS: 1.63 1.07 1.23 2.52 1.01 1.09 1.04 1.56 1.12 1.02 1.07 1.05 1.01 1.21 1.27 1.07
[14:01:13.928] <TB1> INFO: bits mean: 10.35 9.73 9.17 10.24 8.84 9.74 9.00 9.41 9.22 9.68 8.44 9.20 9.33 9.09 8.99 9.47
[14:01:13.928] <TB1> INFO: bits RMS: 2.57 2.67 2.89 2.49 2.92 2.56 2.48 2.83 2.96 2.51 2.38 2.88 2.78 2.75 2.88 2.81
[14:01:13.936] <TB1> INFO: ----------------------------------------------------------------------
[14:01:13.936] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:01:13.936] <TB1> INFO: ----------------------------------------------------------------------
[14:01:13.939] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:01:13.953] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:01:13.953] <TB1> INFO: run 1 of 1
[14:01:14.268] <TB1> INFO: Expecting 4160000 events.
[14:01:47.519] <TB1> INFO: 769755 events read in total (32660ms).
[14:02:19.612] <TB1> INFO: 1530620 events read in total (64753ms).
[14:02:51.429] <TB1> INFO: 2284355 events read in total (96570ms).
[14:03:23.303] <TB1> INFO: 3034460 events read in total (128444ms).
[14:03:55.063] <TB1> INFO: 3782380 events read in total (160204ms).
[14:04:11.482] <TB1> INFO: 4160000 events read in total (176623ms).
[14:04:11.558] <TB1> INFO: Test took 177605ms.
[14:04:39.863] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[14:04:39.876] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:04:39.877] <TB1> INFO: run 1 of 1
[14:04:40.115] <TB1> INFO: Expecting 4326400 events.
[14:05:11.970] <TB1> INFO: 733345 events read in total (31263ms).
[14:05:43.355] <TB1> INFO: 1461025 events read in total (62648ms).
[14:06:14.636] <TB1> INFO: 2182850 events read in total (93929ms).
[14:06:45.727] <TB1> INFO: 2900385 events read in total (125020ms).
[14:07:16.956] <TB1> INFO: 3615995 events read in total (156249ms).
[14:07:47.852] <TB1> INFO: 4326400 events read in total (187145ms).
[14:07:47.961] <TB1> INFO: Test took 188084ms.
[14:08:15.137] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 200 (-1/-1) hits flags = 528 (plus default)
[14:08:15.151] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:08:15.151] <TB1> INFO: run 1 of 1
[14:08:15.387] <TB1> INFO: Expecting 4180800 events.
[14:08:47.775] <TB1> INFO: 743660 events read in total (31796ms).
[14:09:20.353] <TB1> INFO: 1480555 events read in total (64374ms).
[14:09:52.175] <TB1> INFO: 2211335 events read in total (96196ms).
[14:10:23.453] <TB1> INFO: 2938175 events read in total (127474ms).
[14:10:54.769] <TB1> INFO: 3663080 events read in total (158791ms).
[14:11:16.754] <TB1> INFO: 4180800 events read in total (180775ms).
[14:11:16.833] <TB1> INFO: Test took 181681ms.
[14:11:45.875] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:11:45.888] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:11:45.888] <TB1> INFO: run 1 of 1
[14:11:46.124] <TB1> INFO: Expecting 4160000 events.
[14:12:18.712] <TB1> INFO: 745430 events read in total (31996ms).
[14:12:50.398] <TB1> INFO: 1483750 events read in total (63682ms).
[14:13:21.736] <TB1> INFO: 2215850 events read in total (95020ms).
[14:13:53.355] <TB1> INFO: 2944650 events read in total (126639ms).
[14:14:24.701] <TB1> INFO: 3671225 events read in total (157985ms).
[14:14:45.942] <TB1> INFO: 4160000 events read in total (179226ms).
[14:14:46.121] <TB1> INFO: Test took 180233ms.
[14:15:15.261] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[14:15:15.275] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[14:15:15.275] <TB1> INFO: run 1 of 1
[14:15:15.549] <TB1> INFO: Expecting 4139200 events.
[14:15:47.956] <TB1> INFO: 747305 events read in total (31816ms).
[14:16:20.155] <TB1> INFO: 1487545 events read in total (64015ms).
[14:16:52.054] <TB1> INFO: 2221440 events read in total (95914ms).
[14:17:23.468] <TB1> INFO: 2951695 events read in total (127328ms).
[14:17:55.134] <TB1> INFO: 3679595 events read in total (158994ms).
[14:18:14.793] <TB1> INFO: 4139200 events read in total (178653ms).
[14:18:14.918] <TB1> INFO: Test took 179642ms.
[14:18:42.196] <TB1> INFO: PixTestTrim::trimBitTest() done
[14:18:42.197] <TB1> INFO: PixTestTrim::doTest() done, duration: 2503 seconds
[14:18:42.197] <TB1> INFO: Decoding statistics:
[14:18:42.197] <TB1> INFO: General information:
[14:18:42.197] <TB1> INFO: 16bit words read: 0
[14:18:42.197] <TB1> INFO: valid events total: 0
[14:18:42.197] <TB1> INFO: empty events: 0
[14:18:42.197] <TB1> INFO: valid events with pixels: 0
[14:18:42.197] <TB1> INFO: valid pixel hits: 0
[14:18:42.197] <TB1> INFO: Event errors: 0
[14:18:42.197] <TB1> INFO: start marker: 0
[14:18:42.197] <TB1> INFO: stop marker: 0
[14:18:42.197] <TB1> INFO: overflow: 0
[14:18:42.197] <TB1> INFO: invalid 5bit words: 0
[14:18:42.197] <TB1> INFO: invalid XOR eye diagram: 0
[14:18:42.197] <TB1> INFO: frame (failed synchr.): 0
[14:18:42.197] <TB1> INFO: idle data (no TBM trl): 0
[14:18:42.197] <TB1> INFO: no data (only TBM hdr): 0
[14:18:42.197] <TB1> INFO: TBM errors: 0
[14:18:42.197] <TB1> INFO: flawed TBM headers: 0
[14:18:42.197] <TB1> INFO: flawed TBM trailers: 0
[14:18:42.197] <TB1> INFO: event ID mismatches: 0
[14:18:42.197] <TB1> INFO: ROC errors: 0
[14:18:42.197] <TB1> INFO: missing ROC header(s): 0
[14:18:42.197] <TB1> INFO: misplaced readback start: 0
[14:18:42.197] <TB1> INFO: Pixel decoding errors: 0
[14:18:42.197] <TB1> INFO: pixel data incomplete: 0
[14:18:42.197] <TB1> INFO: pixel address: 0
[14:18:42.197] <TB1> INFO: pulse height fill bit: 0
[14:18:42.197] <TB1> INFO: buffer corruption: 0
[14:18:42.889] <TB1> INFO: ######################################################################
[14:18:42.889] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[14:18:42.889] <TB1> INFO: ######################################################################
[14:18:43.165] <TB1> INFO: Expecting 41600 events.
[14:18:46.734] <TB1> INFO: 41600 events read in total (2977ms).
[14:18:46.736] <TB1> INFO: Test took 3846ms.
[14:18:47.209] <TB1> INFO: Expecting 41600 events.
[14:18:50.730] <TB1> INFO: 41600 events read in total (2930ms).
[14:18:50.731] <TB1> INFO: Test took 3789ms.
[14:18:51.021] <TB1> INFO: Expecting 41600 events.
[14:18:54.488] <TB1> INFO: 41600 events read in total (2876ms).
[14:18:54.490] <TB1> INFO: Test took 3734ms.
[14:18:54.779] <TB1> INFO: Expecting 41600 events.
[14:18:58.266] <TB1> INFO: 41600 events read in total (2896ms).
[14:18:58.267] <TB1> INFO: Test took 3753ms.
[14:18:58.560] <TB1> INFO: Expecting 41600 events.
[14:19:02.127] <TB1> INFO: 41600 events read in total (2975ms).
[14:19:02.129] <TB1> INFO: Test took 3835ms.
[14:19:02.422] <TB1> INFO: Expecting 41600 events.
[14:19:05.968] <TB1> INFO: 41600 events read in total (2954ms).
[14:19:05.969] <TB1> INFO: Test took 3811ms.
[14:19:06.258] <TB1> INFO: Expecting 41600 events.
[14:19:09.919] <TB1> INFO: 41600 events read in total (3069ms).
[14:19:09.920] <TB1> INFO: Test took 3927ms.
[14:19:10.212] <TB1> INFO: Expecting 41600 events.
[14:19:13.876] <TB1> INFO: 41600 events read in total (3072ms).
[14:19:13.877] <TB1> INFO: Test took 3930ms.
[14:19:14.169] <TB1> INFO: Expecting 41600 events.
[14:19:17.690] <TB1> INFO: 41600 events read in total (2930ms).
[14:19:17.691] <TB1> INFO: Test took 3787ms.
[14:19:17.982] <TB1> INFO: Expecting 41600 events.
[14:19:21.457] <TB1> INFO: 41600 events read in total (2883ms).
[14:19:21.458] <TB1> INFO: Test took 3741ms.
[14:19:21.747] <TB1> INFO: Expecting 41600 events.
[14:19:25.212] <TB1> INFO: 41600 events read in total (2873ms).
[14:19:25.212] <TB1> INFO: Test took 3730ms.
[14:19:25.501] <TB1> INFO: Expecting 41600 events.
[14:19:28.970] <TB1> INFO: 41600 events read in total (2877ms).
[14:19:28.971] <TB1> INFO: Test took 3734ms.
[14:19:29.260] <TB1> INFO: Expecting 41600 events.
[14:19:32.792] <TB1> INFO: 41600 events read in total (2940ms).
[14:19:32.793] <TB1> INFO: Test took 3798ms.
[14:19:33.083] <TB1> INFO: Expecting 41600 events.
[14:19:36.675] <TB1> INFO: 41600 events read in total (3000ms).
[14:19:36.676] <TB1> INFO: Test took 3858ms.
[14:19:36.966] <TB1> INFO: Expecting 41600 events.
[14:19:40.577] <TB1> INFO: 41600 events read in total (3019ms).
[14:19:40.578] <TB1> INFO: Test took 3877ms.
[14:19:40.867] <TB1> INFO: Expecting 41600 events.
[14:19:44.381] <TB1> INFO: 41600 events read in total (2922ms).
[14:19:44.382] <TB1> INFO: Test took 3779ms.
[14:19:44.673] <TB1> INFO: Expecting 41600 events.
[14:19:48.196] <TB1> INFO: 41600 events read in total (2931ms).
[14:19:48.197] <TB1> INFO: Test took 3788ms.
[14:19:48.486] <TB1> INFO: Expecting 41600 events.
[14:19:52.136] <TB1> INFO: 41600 events read in total (3058ms).
[14:19:52.137] <TB1> INFO: Test took 3916ms.
[14:19:52.427] <TB1> INFO: Expecting 41600 events.
[14:19:55.959] <TB1> INFO: 41600 events read in total (2941ms).
[14:19:55.960] <TB1> INFO: Test took 3798ms.
[14:19:56.252] <TB1> INFO: Expecting 41600 events.
[14:19:59.749] <TB1> INFO: 41600 events read in total (2905ms).
[14:19:59.750] <TB1> INFO: Test took 3763ms.
[14:20:00.039] <TB1> INFO: Expecting 41600 events.
[14:20:03.531] <TB1> INFO: 41600 events read in total (2900ms).
[14:20:03.532] <TB1> INFO: Test took 3758ms.
[14:20:03.822] <TB1> INFO: Expecting 41600 events.
[14:20:07.470] <TB1> INFO: 41600 events read in total (3056ms).
[14:20:07.471] <TB1> INFO: Test took 3913ms.
[14:20:07.763] <TB1> INFO: Expecting 41600 events.
[14:20:11.359] <TB1> INFO: 41600 events read in total (3004ms).
[14:20:11.359] <TB1> INFO: Test took 3861ms.
[14:20:11.649] <TB1> INFO: Expecting 41600 events.
[14:20:15.114] <TB1> INFO: 41600 events read in total (2873ms).
[14:20:15.115] <TB1> INFO: Test took 3731ms.
[14:20:15.424] <TB1> INFO: Expecting 41600 events.
[14:20:18.918] <TB1> INFO: 41600 events read in total (2902ms).
[14:20:18.920] <TB1> INFO: Test took 3781ms.
[14:20:19.211] <TB1> INFO: Expecting 41600 events.
[14:20:22.756] <TB1> INFO: 41600 events read in total (2954ms).
[14:20:22.757] <TB1> INFO: Test took 3811ms.
[14:20:23.046] <TB1> INFO: Expecting 41600 events.
[14:20:26.624] <TB1> INFO: 41600 events read in total (2986ms).
[14:20:26.625] <TB1> INFO: Test took 3844ms.
[14:20:26.931] <TB1> INFO: Expecting 41600 events.
[14:20:30.474] <TB1> INFO: 41600 events read in total (2951ms).
[14:20:30.475] <TB1> INFO: Test took 3826ms.
[14:20:30.766] <TB1> INFO: Expecting 41600 events.
[14:20:34.255] <TB1> INFO: 41600 events read in total (2897ms).
[14:20:34.256] <TB1> INFO: Test took 3754ms.
[14:20:34.549] <TB1> INFO: Expecting 41600 events.
[14:20:38.028] <TB1> INFO: 41600 events read in total (2887ms).
[14:20:38.028] <TB1> INFO: Test took 3744ms.
[14:20:38.318] <TB1> INFO: Expecting 2560 events.
[14:20:39.205] <TB1> INFO: 2560 events read in total (296ms).
[14:20:39.205] <TB1> INFO: Test took 1164ms.
[14:20:39.513] <TB1> INFO: Expecting 2560 events.
[14:20:40.397] <TB1> INFO: 2560 events read in total (292ms).
[14:20:40.397] <TB1> INFO: Test took 1191ms.
[14:20:40.705] <TB1> INFO: Expecting 2560 events.
[14:20:41.588] <TB1> INFO: 2560 events read in total (291ms).
[14:20:41.589] <TB1> INFO: Test took 1191ms.
[14:20:41.896] <TB1> INFO: Expecting 2560 events.
[14:20:42.781] <TB1> INFO: 2560 events read in total (293ms).
[14:20:42.781] <TB1> INFO: Test took 1192ms.
[14:20:43.088] <TB1> INFO: Expecting 2560 events.
[14:20:43.968] <TB1> INFO: 2560 events read in total (288ms).
[14:20:43.968] <TB1> INFO: Test took 1187ms.
[14:20:44.276] <TB1> INFO: Expecting 2560 events.
[14:20:45.159] <TB1> INFO: 2560 events read in total (291ms).
[14:20:45.159] <TB1> INFO: Test took 1190ms.
[14:20:45.467] <TB1> INFO: Expecting 2560 events.
[14:20:46.348] <TB1> INFO: 2560 events read in total (290ms).
[14:20:46.349] <TB1> INFO: Test took 1189ms.
[14:20:46.656] <TB1> INFO: Expecting 2560 events.
[14:20:47.539] <TB1> INFO: 2560 events read in total (291ms).
[14:20:47.539] <TB1> INFO: Test took 1190ms.
[14:20:47.847] <TB1> INFO: Expecting 2560 events.
[14:20:48.729] <TB1> INFO: 2560 events read in total (291ms).
[14:20:48.729] <TB1> INFO: Test took 1190ms.
[14:20:49.036] <TB1> INFO: Expecting 2560 events.
[14:20:49.919] <TB1> INFO: 2560 events read in total (291ms).
[14:20:49.919] <TB1> INFO: Test took 1190ms.
[14:20:50.227] <TB1> INFO: Expecting 2560 events.
[14:20:51.106] <TB1> INFO: 2560 events read in total (288ms).
[14:20:51.106] <TB1> INFO: Test took 1187ms.
[14:20:51.414] <TB1> INFO: Expecting 2560 events.
[14:20:52.295] <TB1> INFO: 2560 events read in total (290ms).
[14:20:52.296] <TB1> INFO: Test took 1189ms.
[14:20:52.603] <TB1> INFO: Expecting 2560 events.
[14:20:53.487] <TB1> INFO: 2560 events read in total (292ms).
[14:20:53.487] <TB1> INFO: Test took 1190ms.
[14:20:53.795] <TB1> INFO: Expecting 2560 events.
[14:20:54.678] <TB1> INFO: 2560 events read in total (291ms).
[14:20:54.678] <TB1> INFO: Test took 1190ms.
[14:20:54.986] <TB1> INFO: Expecting 2560 events.
[14:20:55.871] <TB1> INFO: 2560 events read in total (293ms).
[14:20:55.871] <TB1> INFO: Test took 1192ms.
[14:20:56.179] <TB1> INFO: Expecting 2560 events.
[14:20:57.065] <TB1> INFO: 2560 events read in total (294ms).
[14:20:57.066] <TB1> INFO: Test took 1194ms.
[14:20:57.069] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:20:57.375] <TB1> INFO: Expecting 655360 events.
[14:21:12.181] <TB1> INFO: 655360 events read in total (14215ms).
[14:21:12.199] <TB1> INFO: Expecting 655360 events.
[14:21:26.778] <TB1> INFO: 655360 events read in total (14176ms).
[14:21:26.798] <TB1> INFO: Expecting 655360 events.
[14:21:41.679] <TB1> INFO: 655360 events read in total (14478ms).
[14:21:41.703] <TB1> INFO: Expecting 655360 events.
[14:21:56.409] <TB1> INFO: 655360 events read in total (14303ms).
[14:21:56.440] <TB1> INFO: Expecting 655360 events.
[14:22:11.195] <TB1> INFO: 655360 events read in total (14350ms).
[14:22:11.233] <TB1> INFO: Expecting 655360 events.
[14:22:26.127] <TB1> INFO: 655360 events read in total (14491ms).
[14:22:26.167] <TB1> INFO: Expecting 655360 events.
[14:22:40.723] <TB1> INFO: 655360 events read in total (14153ms).
[14:22:40.764] <TB1> INFO: Expecting 655360 events.
[14:22:55.680] <TB1> INFO: 655360 events read in total (14513ms).
[14:22:55.752] <TB1> INFO: Expecting 655360 events.
[14:23:10.605] <TB1> INFO: 655360 events read in total (14450ms).
[14:23:10.682] <TB1> INFO: Expecting 655360 events.
[14:23:25.161] <TB1> INFO: 655360 events read in total (14076ms).
[14:23:25.308] <TB1> INFO: Expecting 655360 events.
[14:23:39.760] <TB1> INFO: 655360 events read in total (14049ms).
[14:23:39.831] <TB1> INFO: Expecting 655360 events.
[14:23:54.396] <TB1> INFO: 655360 events read in total (14162ms).
[14:23:54.477] <TB1> INFO: Expecting 655360 events.
[14:24:08.998] <TB1> INFO: 655360 events read in total (14118ms).
[14:24:09.083] <TB1> INFO: Expecting 655360 events.
[14:24:23.611] <TB1> INFO: 655360 events read in total (14125ms).
[14:24:23.703] <TB1> INFO: Expecting 655360 events.
[14:24:38.189] <TB1> INFO: 655360 events read in total (14082ms).
[14:24:38.280] <TB1> INFO: Expecting 655360 events.
[14:24:52.746] <TB1> INFO: 655360 events read in total (14062ms).
[14:24:52.906] <TB1> INFO: Test took 235837ms.
[14:24:53.006] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:24:53.264] <TB1> INFO: Expecting 655360 events.
[14:25:07.590] <TB1> INFO: 655360 events read in total (13735ms).
[14:25:07.604] <TB1> INFO: Expecting 655360 events.
[14:25:22.085] <TB1> INFO: 655360 events read in total (14078ms).
[14:25:22.111] <TB1> INFO: Expecting 655360 events.
[14:25:36.543] <TB1> INFO: 655360 events read in total (14029ms).
[14:25:36.574] <TB1> INFO: Expecting 655360 events.
[14:25:50.658] <TB1> INFO: 655360 events read in total (13681ms).
[14:25:50.685] <TB1> INFO: Expecting 655360 events.
[14:26:05.131] <TB1> INFO: 655360 events read in total (14043ms).
[14:26:05.165] <TB1> INFO: Expecting 655360 events.
[14:26:19.609] <TB1> INFO: 655360 events read in total (14041ms).
[14:26:19.658] <TB1> INFO: Expecting 655360 events.
[14:26:33.765] <TB1> INFO: 655360 events read in total (13704ms).
[14:26:33.813] <TB1> INFO: Expecting 655360 events.
[14:26:48.260] <TB1> INFO: 655360 events read in total (14044ms).
[14:26:48.312] <TB1> INFO: Expecting 655360 events.
[14:27:02.621] <TB1> INFO: 655360 events read in total (13906ms).
[14:27:02.670] <TB1> INFO: Expecting 655360 events.
[14:27:17.287] <TB1> INFO: 655360 events read in total (14214ms).
[14:27:17.348] <TB1> INFO: Expecting 655360 events.
[14:27:31.638] <TB1> INFO: 655360 events read in total (13887ms).
[14:27:31.752] <TB1> INFO: Expecting 655360 events.
[14:27:46.186] <TB1> INFO: 655360 events read in total (14031ms).
[14:27:46.293] <TB1> INFO: Expecting 655360 events.
[14:28:00.779] <TB1> INFO: 655360 events read in total (14083ms).
[14:28:00.880] <TB1> INFO: Expecting 655360 events.
[14:28:15.440] <TB1> INFO: 655360 events read in total (14157ms).
[14:28:15.527] <TB1> INFO: Expecting 655360 events.
[14:28:29.970] <TB1> INFO: 655360 events read in total (14040ms).
[14:28:30.064] <TB1> INFO: Expecting 655360 events.
[14:28:44.482] <TB1> INFO: 655360 events read in total (14014ms).
[14:28:44.642] <TB1> INFO: Test took 231636ms.
[14:28:44.824] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:28:44.830] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:28:44.836] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:28:44.842] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[14:28:44.848] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[14:28:44.853] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:28:44.859] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[14:28:44.865] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[14:28:44.871] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[14:28:44.876] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:28:44.882] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:28:44.888] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[14:28:44.894] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[14:28:44.900] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[14:28:44.905] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:28:44.911] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:28:44.917] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:28:44.923] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[14:28:44.928] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[14:28:44.934] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[14:28:44.940] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[14:28:44.946] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:28:44.952] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:28:44.957] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:28:44.963] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:28:44.969] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:28:44.974] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:28:44.980] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[14:28:44.986] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[14:28:44.991] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[14:28:44.997] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[14:28:45.003] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[14:28:45.038] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C0.dat
[14:28:45.038] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C1.dat
[14:28:45.039] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C2.dat
[14:28:45.039] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C3.dat
[14:28:45.039] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C4.dat
[14:28:45.039] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C5.dat
[14:28:45.039] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C6.dat
[14:28:45.039] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C7.dat
[14:28:45.039] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C8.dat
[14:28:45.039] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C9.dat
[14:28:45.039] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C10.dat
[14:28:45.039] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C11.dat
[14:28:45.040] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C12.dat
[14:28:45.040] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C13.dat
[14:28:45.040] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C14.dat
[14:28:45.040] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//dacParameters35_C15.dat
[14:28:45.286] <TB1> INFO: Expecting 41600 events.
[14:28:48.438] <TB1> INFO: 41600 events read in total (2560ms).
[14:28:48.439] <TB1> INFO: Test took 3396ms.
[14:28:48.894] <TB1> INFO: Expecting 41600 events.
[14:28:51.940] <TB1> INFO: 41600 events read in total (2455ms).
[14:28:51.942] <TB1> INFO: Test took 3289ms.
[14:28:52.398] <TB1> INFO: Expecting 41600 events.
[14:28:55.543] <TB1> INFO: 41600 events read in total (2554ms).
[14:28:55.544] <TB1> INFO: Test took 3390ms.
[14:28:55.760] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:28:55.849] <TB1> INFO: Expecting 2560 events.
[14:28:56.735] <TB1> INFO: 2560 events read in total (294ms).
[14:28:56.736] <TB1> INFO: Test took 976ms.
[14:28:56.740] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:28:57.043] <TB1> INFO: Expecting 2560 events.
[14:28:57.934] <TB1> INFO: 2560 events read in total (300ms).
[14:28:57.935] <TB1> INFO: Test took 1195ms.
[14:28:57.938] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:28:58.242] <TB1> INFO: Expecting 2560 events.
[14:28:59.138] <TB1> INFO: 2560 events read in total (304ms).
[14:28:59.139] <TB1> INFO: Test took 1201ms.
[14:28:59.143] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:28:59.447] <TB1> INFO: Expecting 2560 events.
[14:29:00.332] <TB1> INFO: 2560 events read in total (293ms).
[14:29:00.332] <TB1> INFO: Test took 1189ms.
[14:29:00.335] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:00.640] <TB1> INFO: Expecting 2560 events.
[14:29:01.533] <TB1> INFO: 2560 events read in total (301ms).
[14:29:01.533] <TB1> INFO: Test took 1198ms.
[14:29:01.535] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:01.842] <TB1> INFO: Expecting 2560 events.
[14:29:02.740] <TB1> INFO: 2560 events read in total (306ms).
[14:29:02.740] <TB1> INFO: Test took 1205ms.
[14:29:02.743] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:03.048] <TB1> INFO: Expecting 2560 events.
[14:29:03.934] <TB1> INFO: 2560 events read in total (294ms).
[14:29:03.934] <TB1> INFO: Test took 1191ms.
[14:29:03.937] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:04.242] <TB1> INFO: Expecting 2560 events.
[14:29:05.127] <TB1> INFO: 2560 events read in total (293ms).
[14:29:05.127] <TB1> INFO: Test took 1190ms.
[14:29:05.129] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:05.436] <TB1> INFO: Expecting 2560 events.
[14:29:06.318] <TB1> INFO: 2560 events read in total (290ms).
[14:29:06.319] <TB1> INFO: Test took 1190ms.
[14:29:06.321] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:06.627] <TB1> INFO: Expecting 2560 events.
[14:29:07.507] <TB1> INFO: 2560 events read in total (289ms).
[14:29:07.507] <TB1> INFO: Test took 1186ms.
[14:29:07.509] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:07.815] <TB1> INFO: Expecting 2560 events.
[14:29:08.702] <TB1> INFO: 2560 events read in total (296ms).
[14:29:08.702] <TB1> INFO: Test took 1193ms.
[14:29:08.706] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:09.010] <TB1> INFO: Expecting 2560 events.
[14:29:09.891] <TB1> INFO: 2560 events read in total (290ms).
[14:29:09.891] <TB1> INFO: Test took 1186ms.
[14:29:09.894] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:10.201] <TB1> INFO: Expecting 2560 events.
[14:29:11.081] <TB1> INFO: 2560 events read in total (289ms).
[14:29:11.081] <TB1> INFO: Test took 1187ms.
[14:29:11.087] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:11.388] <TB1> INFO: Expecting 2560 events.
[14:29:12.268] <TB1> INFO: 2560 events read in total (288ms).
[14:29:12.268] <TB1> INFO: Test took 1181ms.
[14:29:12.270] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:12.576] <TB1> INFO: Expecting 2560 events.
[14:29:13.466] <TB1> INFO: 2560 events read in total (298ms).
[14:29:13.466] <TB1> INFO: Test took 1196ms.
[14:29:13.469] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:13.774] <TB1> INFO: Expecting 2560 events.
[14:29:14.665] <TB1> INFO: 2560 events read in total (299ms).
[14:29:14.665] <TB1> INFO: Test took 1196ms.
[14:29:14.669] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:14.974] <TB1> INFO: Expecting 2560 events.
[14:29:15.867] <TB1> INFO: 2560 events read in total (302ms).
[14:29:15.867] <TB1> INFO: Test took 1198ms.
[14:29:15.872] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:16.176] <TB1> INFO: Expecting 2560 events.
[14:29:17.068] <TB1> INFO: 2560 events read in total (300ms).
[14:29:17.068] <TB1> INFO: Test took 1196ms.
[14:29:17.071] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:17.377] <TB1> INFO: Expecting 2560 events.
[14:29:18.266] <TB1> INFO: 2560 events read in total (298ms).
[14:29:18.267] <TB1> INFO: Test took 1196ms.
[14:29:18.271] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:18.574] <TB1> INFO: Expecting 2560 events.
[14:29:19.461] <TB1> INFO: 2560 events read in total (295ms).
[14:29:19.461] <TB1> INFO: Test took 1190ms.
[14:29:19.464] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:19.770] <TB1> INFO: Expecting 2560 events.
[14:29:20.657] <TB1> INFO: 2560 events read in total (295ms).
[14:29:20.657] <TB1> INFO: Test took 1194ms.
[14:29:20.662] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:20.965] <TB1> INFO: Expecting 2560 events.
[14:29:21.854] <TB1> INFO: 2560 events read in total (298ms).
[14:29:21.854] <TB1> INFO: Test took 1193ms.
[14:29:21.856] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:22.162] <TB1> INFO: Expecting 2560 events.
[14:29:23.045] <TB1> INFO: 2560 events read in total (291ms).
[14:29:23.046] <TB1> INFO: Test took 1190ms.
[14:29:23.050] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:23.353] <TB1> INFO: Expecting 2560 events.
[14:29:24.235] <TB1> INFO: 2560 events read in total (291ms).
[14:29:24.235] <TB1> INFO: Test took 1185ms.
[14:29:24.238] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:24.544] <TB1> INFO: Expecting 2560 events.
[14:29:25.436] <TB1> INFO: 2560 events read in total (301ms).
[14:29:25.437] <TB1> INFO: Test took 1199ms.
[14:29:25.441] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:25.744] <TB1> INFO: Expecting 2560 events.
[14:29:26.633] <TB1> INFO: 2560 events read in total (298ms).
[14:29:26.634] <TB1> INFO: Test took 1194ms.
[14:29:26.637] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:26.942] <TB1> INFO: Expecting 2560 events.
[14:29:27.827] <TB1> INFO: 2560 events read in total (293ms).
[14:29:27.827] <TB1> INFO: Test took 1191ms.
[14:29:27.830] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:28.136] <TB1> INFO: Expecting 2560 events.
[14:29:29.031] <TB1> INFO: 2560 events read in total (303ms).
[14:29:29.031] <TB1> INFO: Test took 1201ms.
[14:29:29.035] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:29.339] <TB1> INFO: Expecting 2560 events.
[14:29:30.226] <TB1> INFO: 2560 events read in total (295ms).
[14:29:30.226] <TB1> INFO: Test took 1191ms.
[14:29:30.229] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:30.535] <TB1> INFO: Expecting 2560 events.
[14:29:31.430] <TB1> INFO: 2560 events read in total (303ms).
[14:29:31.431] <TB1> INFO: Test took 1202ms.
[14:29:31.435] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:31.739] <TB1> INFO: Expecting 2560 events.
[14:29:32.633] <TB1> INFO: 2560 events read in total (302ms).
[14:29:32.634] <TB1> INFO: Test took 1200ms.
[14:29:32.637] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:29:32.942] <TB1> INFO: Expecting 2560 events.
[14:29:33.831] <TB1> INFO: 2560 events read in total (297ms).
[14:29:33.831] <TB1> INFO: Test took 1194ms.
[14:29:34.308] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 651 seconds
[14:29:34.308] <TB1> INFO: PH scale (per ROC): 49 49 46 39 47 39 36 43 48 34 52 21 53 31 38 38
[14:29:34.308] <TB1> INFO: PH offset (per ROC): 123 105 96 111 115 94 91 105 127 108 127 100 128 78 102 107
[14:29:34.318] <TB1> INFO: Decoding statistics:
[14:29:34.318] <TB1> INFO: General information:
[14:29:34.318] <TB1> INFO: 16bit words read: 127888
[14:29:34.318] <TB1> INFO: valid events total: 20480
[14:29:34.318] <TB1> INFO: empty events: 17976
[14:29:34.318] <TB1> INFO: valid events with pixels: 2504
[14:29:34.318] <TB1> INFO: valid pixel hits: 2504
[14:29:34.318] <TB1> INFO: Event errors: 0
[14:29:34.318] <TB1> INFO: start marker: 0
[14:29:34.318] <TB1> INFO: stop marker: 0
[14:29:34.318] <TB1> INFO: overflow: 0
[14:29:34.318] <TB1> INFO: invalid 5bit words: 0
[14:29:34.318] <TB1> INFO: invalid XOR eye diagram: 0
[14:29:34.318] <TB1> INFO: frame (failed synchr.): 0
[14:29:34.318] <TB1> INFO: idle data (no TBM trl): 0
[14:29:34.318] <TB1> INFO: no data (only TBM hdr): 0
[14:29:34.318] <TB1> INFO: TBM errors: 0
[14:29:34.318] <TB1> INFO: flawed TBM headers: 0
[14:29:34.318] <TB1> INFO: flawed TBM trailers: 0
[14:29:34.318] <TB1> INFO: event ID mismatches: 0
[14:29:34.318] <TB1> INFO: ROC errors: 0
[14:29:34.318] <TB1> INFO: missing ROC header(s): 0
[14:29:34.318] <TB1> INFO: misplaced readback start: 0
[14:29:34.318] <TB1> INFO: Pixel decoding errors: 0
[14:29:34.318] <TB1> INFO: pixel data incomplete: 0
[14:29:34.318] <TB1> INFO: pixel address: 0
[14:29:34.318] <TB1> INFO: pulse height fill bit: 0
[14:29:34.318] <TB1> INFO: buffer corruption: 0
[14:29:34.481] <TB1> INFO: ######################################################################
[14:29:34.481] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[14:29:34.481] <TB1> INFO: ######################################################################
[14:29:34.497] <TB1> INFO: scanning low vcal = 10
[14:29:34.734] <TB1> INFO: Expecting 41600 events.
[14:29:38.329] <TB1> INFO: 41600 events read in total (3003ms).
[14:29:38.329] <TB1> INFO: Test took 3832ms.
[14:29:38.331] <TB1> INFO: scanning low vcal = 20
[14:29:38.627] <TB1> INFO: Expecting 41600 events.
[14:29:42.219] <TB1> INFO: 41600 events read in total (3000ms).
[14:29:42.220] <TB1> INFO: Test took 3889ms.
[14:29:42.222] <TB1> INFO: scanning low vcal = 30
[14:29:42.518] <TB1> INFO: Expecting 41600 events.
[14:29:46.215] <TB1> INFO: 41600 events read in total (3105ms).
[14:29:46.216] <TB1> INFO: Test took 3994ms.
[14:29:46.218] <TB1> INFO: scanning low vcal = 40
[14:29:46.495] <TB1> INFO: Expecting 41600 events.
[14:29:50.464] <TB1> INFO: 41600 events read in total (3377ms).
[14:29:50.466] <TB1> INFO: Test took 4248ms.
[14:29:50.469] <TB1> INFO: scanning low vcal = 50
[14:29:50.746] <TB1> INFO: Expecting 41600 events.
[14:29:54.735] <TB1> INFO: 41600 events read in total (3397ms).
[14:29:54.736] <TB1> INFO: Test took 4267ms.
[14:29:54.739] <TB1> INFO: scanning low vcal = 60
[14:29:55.016] <TB1> INFO: Expecting 41600 events.
[14:29:59.067] <TB1> INFO: 41600 events read in total (3459ms).
[14:29:59.068] <TB1> INFO: Test took 4328ms.
[14:29:59.071] <TB1> INFO: scanning low vcal = 70
[14:29:59.348] <TB1> INFO: Expecting 41600 events.
[14:30:03.417] <TB1> INFO: 41600 events read in total (3477ms).
[14:30:03.418] <TB1> INFO: Test took 4347ms.
[14:30:03.421] <TB1> INFO: scanning low vcal = 80
[14:30:03.698] <TB1> INFO: Expecting 41600 events.
[14:30:07.722] <TB1> INFO: 41600 events read in total (3432ms).
[14:30:07.723] <TB1> INFO: Test took 4302ms.
[14:30:07.726] <TB1> INFO: scanning low vcal = 90
[14:30:08.003] <TB1> INFO: Expecting 41600 events.
[14:30:12.023] <TB1> INFO: 41600 events read in total (3428ms).
[14:30:12.025] <TB1> INFO: Test took 4299ms.
[14:30:12.030] <TB1> INFO: scanning low vcal = 100
[14:30:12.306] <TB1> INFO: Expecting 41600 events.
[14:30:16.371] <TB1> INFO: 41600 events read in total (3473ms).
[14:30:16.372] <TB1> INFO: Test took 4342ms.
[14:30:16.375] <TB1> INFO: scanning low vcal = 110
[14:30:16.652] <TB1> INFO: Expecting 41600 events.
[14:30:20.622] <TB1> INFO: 41600 events read in total (3378ms).
[14:30:20.623] <TB1> INFO: Test took 4247ms.
[14:30:20.626] <TB1> INFO: scanning low vcal = 120
[14:30:20.903] <TB1> INFO: Expecting 41600 events.
[14:30:24.885] <TB1> INFO: 41600 events read in total (3390ms).
[14:30:24.887] <TB1> INFO: Test took 4261ms.
[14:30:24.891] <TB1> INFO: scanning low vcal = 130
[14:30:25.167] <TB1> INFO: Expecting 41600 events.
[14:30:29.179] <TB1> INFO: 41600 events read in total (3420ms).
[14:30:29.179] <TB1> INFO: Test took 4288ms.
[14:30:29.182] <TB1> INFO: scanning low vcal = 140
[14:30:29.460] <TB1> INFO: Expecting 41600 events.
[14:30:33.466] <TB1> INFO: 41600 events read in total (3415ms).
[14:30:33.467] <TB1> INFO: Test took 4285ms.
[14:30:33.471] <TB1> INFO: scanning low vcal = 150
[14:30:33.748] <TB1> INFO: Expecting 41600 events.
[14:30:37.719] <TB1> INFO: 41600 events read in total (3380ms).
[14:30:37.720] <TB1> INFO: Test took 4249ms.
[14:30:37.723] <TB1> INFO: scanning low vcal = 160
[14:30:37.999] <TB1> INFO: Expecting 41600 events.
[14:30:41.980] <TB1> INFO: 41600 events read in total (3389ms).
[14:30:41.981] <TB1> INFO: Test took 4258ms.
[14:30:41.985] <TB1> INFO: scanning low vcal = 170
[14:30:42.262] <TB1> INFO: Expecting 41600 events.
[14:30:46.255] <TB1> INFO: 41600 events read in total (3401ms).
[14:30:46.256] <TB1> INFO: Test took 4270ms.
[14:30:46.261] <TB1> INFO: scanning low vcal = 180
[14:30:46.536] <TB1> INFO: Expecting 41600 events.
[14:30:50.555] <TB1> INFO: 41600 events read in total (3427ms).
[14:30:50.556] <TB1> INFO: Test took 4295ms.
[14:30:50.559] <TB1> INFO: scanning low vcal = 190
[14:30:50.836] <TB1> INFO: Expecting 41600 events.
[14:30:54.821] <TB1> INFO: 41600 events read in total (3393ms).
[14:30:54.821] <TB1> INFO: Test took 4262ms.
[14:30:54.824] <TB1> INFO: scanning low vcal = 200
[14:30:55.101] <TB1> INFO: Expecting 41600 events.
[14:30:59.095] <TB1> INFO: 41600 events read in total (3402ms).
[14:30:59.096] <TB1> INFO: Test took 4272ms.
[14:30:59.099] <TB1> INFO: scanning low vcal = 210
[14:30:59.376] <TB1> INFO: Expecting 41600 events.
[14:31:03.379] <TB1> INFO: 41600 events read in total (3411ms).
[14:31:03.380] <TB1> INFO: Test took 4281ms.
[14:31:03.383] <TB1> INFO: scanning low vcal = 220
[14:31:03.661] <TB1> INFO: Expecting 41600 events.
[14:31:07.684] <TB1> INFO: 41600 events read in total (3431ms).
[14:31:07.685] <TB1> INFO: Test took 4301ms.
[14:31:07.688] <TB1> INFO: scanning low vcal = 230
[14:31:07.965] <TB1> INFO: Expecting 41600 events.
[14:31:11.959] <TB1> INFO: 41600 events read in total (3402ms).
[14:31:11.960] <TB1> INFO: Test took 4272ms.
[14:31:11.963] <TB1> INFO: scanning low vcal = 240
[14:31:12.241] <TB1> INFO: Expecting 41600 events.
[14:31:16.270] <TB1> INFO: 41600 events read in total (3437ms).
[14:31:16.271] <TB1> INFO: Test took 4308ms.
[14:31:16.274] <TB1> INFO: scanning low vcal = 250
[14:31:16.551] <TB1> INFO: Expecting 41600 events.
[14:31:20.558] <TB1> INFO: 41600 events read in total (3415ms).
[14:31:20.559] <TB1> INFO: Test took 4285ms.
[14:31:20.564] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[14:31:20.840] <TB1> INFO: Expecting 41600 events.
[14:31:24.863] <TB1> INFO: 41600 events read in total (3431ms).
[14:31:24.864] <TB1> INFO: Test took 4300ms.
[14:31:24.867] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[14:31:25.144] <TB1> INFO: Expecting 41600 events.
[14:31:29.167] <TB1> INFO: 41600 events read in total (3431ms).
[14:31:29.168] <TB1> INFO: Test took 4300ms.
[14:31:29.171] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[14:31:29.448] <TB1> INFO: Expecting 41600 events.
[14:31:33.476] <TB1> INFO: 41600 events read in total (3436ms).
[14:31:33.477] <TB1> INFO: Test took 4306ms.
[14:31:33.480] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[14:31:33.758] <TB1> INFO: Expecting 41600 events.
[14:31:37.756] <TB1> INFO: 41600 events read in total (3406ms).
[14:31:37.757] <TB1> INFO: Test took 4276ms.
[14:31:37.760] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[14:31:38.037] <TB1> INFO: Expecting 41600 events.
[14:31:42.064] <TB1> INFO: 41600 events read in total (3435ms).
[14:31:42.065] <TB1> INFO: Test took 4305ms.
[14:31:42.491] <TB1> INFO: PixTestGainPedestal::measure() done
[14:32:20.408] <TB1> INFO: PixTestGainPedestal::fit() done
[14:32:20.408] <TB1> INFO: non-linearity mean: 0.984 0.977 0.952 0.935 0.972 0.938 0.943 0.945 0.982 0.941 0.980 1.055 0.982 1.021 0.958 0.936
[14:32:20.408] <TB1> INFO: non-linearity RMS: 0.003 0.007 0.044 0.100 0.009 0.129 0.064 0.055 0.004 0.135 0.004 0.124 0.004 0.165 0.048 0.096
[14:32:20.408] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C0.dat
[14:32:20.423] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C1.dat
[14:32:20.438] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C2.dat
[14:32:20.452] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C3.dat
[14:32:20.466] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C4.dat
[14:32:20.481] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C5.dat
[14:32:20.495] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C6.dat
[14:32:20.509] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C7.dat
[14:32:20.522] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C8.dat
[14:32:20.536] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C9.dat
[14:32:20.551] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C10.dat
[14:32:20.564] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C11.dat
[14:32:20.578] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C12.dat
[14:32:20.592] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C13.dat
[14:32:20.606] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C14.dat
[14:32:20.619] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//003_Fulltest_p17//phCalibrationFitErr35_C15.dat
[14:32:20.632] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 166 seconds
[14:32:20.632] <TB1> INFO: Decoding statistics:
[14:32:20.632] <TB1> INFO: General information:
[14:32:20.632] <TB1> INFO: 16bit words read: 3272948
[14:32:20.632] <TB1> INFO: valid events total: 332800
[14:32:20.632] <TB1> INFO: empty events: 6498
[14:32:20.632] <TB1> INFO: valid events with pixels: 326302
[14:32:20.632] <TB1> INFO: valid pixel hits: 638074
[14:32:20.632] <TB1> INFO: Event errors: 0
[14:32:20.632] <TB1> INFO: start marker: 0
[14:32:20.632] <TB1> INFO: stop marker: 0
[14:32:20.632] <TB1> INFO: overflow: 0
[14:32:20.632] <TB1> INFO: invalid 5bit words: 0
[14:32:20.632] <TB1> INFO: invalid XOR eye diagram: 0
[14:32:20.632] <TB1> INFO: frame (failed synchr.): 0
[14:32:20.632] <TB1> INFO: idle data (no TBM trl): 0
[14:32:20.632] <TB1> INFO: no data (only TBM hdr): 0
[14:32:20.632] <TB1> INFO: TBM errors: 0
[14:32:20.632] <TB1> INFO: flawed TBM headers: 0
[14:32:20.632] <TB1> INFO: flawed TBM trailers: 0
[14:32:20.632] <TB1> INFO: event ID mismatches: 0
[14:32:20.632] <TB1> INFO: ROC errors: 0
[14:32:20.632] <TB1> INFO: missing ROC header(s): 0
[14:32:20.632] <TB1> INFO: misplaced readback start: 0
[14:32:20.632] <TB1> INFO: Pixel decoding errors: 0
[14:32:20.632] <TB1> INFO: pixel data incomplete: 0
[14:32:20.632] <TB1> INFO: pixel address: 0
[14:32:20.632] <TB1> INFO: pulse height fill bit: 0
[14:32:20.632] <TB1> INFO: buffer corruption: 0
[14:32:20.650] <TB1> INFO: Decoding statistics:
[14:32:20.650] <TB1> INFO: General information:
[14:32:20.650] <TB1> INFO: 16bit words read: 3402372
[14:32:20.650] <TB1> INFO: valid events total: 353536
[14:32:20.650] <TB1> INFO: empty events: 24730
[14:32:20.650] <TB1> INFO: valid events with pixels: 328806
[14:32:20.650] <TB1> INFO: valid pixel hits: 640578
[14:32:20.650] <TB1> INFO: Event errors: 0
[14:32:20.650] <TB1> INFO: start marker: 0
[14:32:20.650] <TB1> INFO: stop marker: 0
[14:32:20.650] <TB1> INFO: overflow: 0
[14:32:20.650] <TB1> INFO: invalid 5bit words: 0
[14:32:20.650] <TB1> INFO: invalid XOR eye diagram: 0
[14:32:20.650] <TB1> INFO: frame (failed synchr.): 0
[14:32:20.650] <TB1> INFO: idle data (no TBM trl): 0
[14:32:20.650] <TB1> INFO: no data (only TBM hdr): 0
[14:32:20.650] <TB1> INFO: TBM errors: 0
[14:32:20.650] <TB1> INFO: flawed TBM headers: 0
[14:32:20.650] <TB1> INFO: flawed TBM trailers: 0
[14:32:20.650] <TB1> INFO: event ID mismatches: 0
[14:32:20.650] <TB1> INFO: ROC errors: 0
[14:32:20.650] <TB1> INFO: missing ROC header(s): 0
[14:32:20.650] <TB1> INFO: misplaced readback start: 0
[14:32:20.650] <TB1> INFO: Pixel decoding errors: 0
[14:32:20.650] <TB1> INFO: pixel data incomplete: 0
[14:32:20.650] <TB1> INFO: pixel address: 0
[14:32:20.650] <TB1> INFO: pulse height fill bit: 0
[14:32:20.650] <TB1> INFO: buffer corruption: 0
[14:32:20.650] <TB1> INFO: enter test to run
[14:32:20.650] <TB1> INFO: test: exit no parameter change
[14:32:20.774] <TB1> QUIET: Connection to board 154 closed.
[14:32:20.776] <TB1> INFO: pXar: this is the end, my friend