[11:32:52.222] <TB1> INFO: *** Welcome to pxar ***
[11:32:52.222] <TB1> INFO: *** Today: 2016/10/22
[11:32:52.228] <TB1> INFO: *** Version: c8ba-dirty
[11:32:52.228] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C15.dat
[11:32:52.229] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//tbmParameters_C1b.dat
[11:32:52.229] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//defaultMaskFile.dat
[11:32:52.229] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters_C15.dat
[11:32:52.293] <TB1> INFO: clk: 4
[11:32:52.293] <TB1> INFO: ctr: 4
[11:32:52.293] <TB1> INFO: sda: 19
[11:32:52.293] <TB1> INFO: tin: 9
[11:32:52.293] <TB1> INFO: level: 15
[11:32:52.293] <TB1> INFO: triggerdelay: 0
[11:32:52.293] <TB1> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[11:32:52.293] <TB1> INFO: Log level: INFO
[11:32:52.303] <TB1> INFO: Found DTB DTB_WXC03A
[11:32:52.315] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[11:32:52.317] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
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[11:32:52.318] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[11:32:53.878] <TB1> INFO: DUT info:
[11:32:53.878] <TB1> INFO: The DUT currently contains the following objects:
[11:32:53.878] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[11:32:53.878] <TB1> INFO: TBM Core alpha (0): 7 registers set
[11:32:53.879] <TB1> INFO: TBM Core beta (1): 7 registers set
[11:32:53.879] <TB1> INFO: TBM Core alpha (2): 7 registers set
[11:32:53.879] <TB1> INFO: TBM Core beta (3): 7 registers set
[11:32:53.879] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:32:53.879] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:53.879] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:53.879] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:53.879] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:53.879] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:53.879] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:53.879] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:53.879] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:53.879] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:53.879] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:53.879] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:53.879] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:53.879] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:53.879] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:53.879] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:53.879] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:54.280] <TB1> INFO: enter 'restricted' command line mode
[11:32:54.280] <TB1> INFO: enter test to run
[11:32:54.280] <TB1> INFO: test: pretest no parameter change
[11:32:54.280] <TB1> INFO: running: pretest
[11:32:54.285] <TB1> INFO: ######################################################################
[11:32:54.285] <TB1> INFO: PixTestPretest::doTest()
[11:32:54.285] <TB1> INFO: ######################################################################
[11:32:54.286] <TB1> INFO: ----------------------------------------------------------------------
[11:32:54.286] <TB1> INFO: PixTestPretest::programROC()
[11:32:54.286] <TB1> INFO: ----------------------------------------------------------------------
[11:33:12.300] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:33:12.300] <TB1> INFO: IA differences per ROC: 18.5 20.1 19.3 17.7 18.5 19.3 17.7 16.9 16.9 17.7 17.7 18.5 19.3 16.9 19.3 18.5
[11:33:12.359] <TB1> INFO: ----------------------------------------------------------------------
[11:33:12.359] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:33:12.359] <TB1> INFO: ----------------------------------------------------------------------
[11:33:33.652] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 399.5 mA = 24.9688 mA/ROC
[11:33:33.652] <TB1> INFO: i(loss) [mA/ROC]: 20.9 20.1 20.1 20.1 21.7 20.1 20.9 20.1 20.1 20.9 21.7 21.7 20.1 20.1 20.1 18.5
[11:33:33.688] <TB1> INFO: ----------------------------------------------------------------------
[11:33:33.688] <TB1> INFO: PixTestPretest::findTiming()
[11:33:33.688] <TB1> INFO: ----------------------------------------------------------------------
[11:33:33.689] <TB1> INFO: PixTestCmd::init()

[11:34:05.861] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[11:34:05.861] <TB1> INFO: (success/tries = 100/100), width = 3
[11:34:07.366] <TB1> INFO: ----------------------------------------------------------------------
[11:34:07.366] <TB1> INFO: PixTestPretest::findWorkingPixel()
[11:34:07.366] <TB1> INFO: ----------------------------------------------------------------------
[11:34:07.460] <TB1> INFO: Expecting 231680 events.
[11:34:17.442] <TB1> INFO: 231680 events read in total (9391ms).
[11:34:17.450] <TB1> INFO: Test took 10081ms.
[11:34:17.698] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:34:17.735] <TB1> INFO: ----------------------------------------------------------------------
[11:34:17.735] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[11:34:17.735] <TB1> INFO: ----------------------------------------------------------------------
[11:34:17.830] <TB1> INFO: Expecting 231680 events.
[11:34:27.715] <TB1> INFO: 231680 events read in total (9293ms).
[11:34:27.723] <TB1> INFO: Test took 9983ms.
[11:34:27.994] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[11:34:27.994] <TB1> INFO: CalDel: 88 93 102 125 95 111 121 111 108 97 90 92 107 98 97 89
[11:34:27.994] <TB1> INFO: VthrComp: 54 51 52 52 51 51 51 54 51 51 52 51 51 51 51 51
[11:34:27.002] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C0.dat
[11:34:27.002] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C1.dat
[11:34:27.002] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C2.dat
[11:34:27.002] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C3.dat
[11:34:27.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C4.dat
[11:34:27.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C5.dat
[11:34:28.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C6.dat
[11:34:28.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C7.dat
[11:34:28.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C8.dat
[11:34:28.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C9.dat
[11:34:28.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C10.dat
[11:34:28.003] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C11.dat
[11:34:28.004] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C12.dat
[11:34:28.004] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C13.dat
[11:34:28.004] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C14.dat
[11:34:28.004] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters_C15.dat
[11:34:28.004] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//tbmParameters_C0a.dat
[11:34:28.004] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//tbmParameters_C0b.dat
[11:34:28.004] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//tbmParameters_C1a.dat
[11:34:28.004] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//tbmParameters_C1b.dat
[11:34:28.004] <TB1> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[11:34:28.057] <TB1> INFO: enter test to run
[11:34:28.057] <TB1> INFO: test: FullTest no parameter change
[11:34:28.057] <TB1> INFO: running: fulltest
[11:34:28.057] <TB1> INFO: ######################################################################
[11:34:28.057] <TB1> INFO: PixTestFullTest::doTest()
[11:34:28.057] <TB1> INFO: ######################################################################
[11:34:28.058] <TB1> INFO: ######################################################################
[11:34:28.058] <TB1> INFO: PixTestAlive::doTest()
[11:34:28.058] <TB1> INFO: ######################################################################
[11:34:28.059] <TB1> INFO: ----------------------------------------------------------------------
[11:34:28.059] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:34:28.059] <TB1> INFO: ----------------------------------------------------------------------
[11:34:28.299] <TB1> INFO: Expecting 41600 events.
[11:34:31.821] <TB1> INFO: 41600 events read in total (2930ms).
[11:34:31.822] <TB1> INFO: Test took 3762ms.
[11:34:32.056] <TB1> INFO: PixTestAlive::aliveTest() done
[11:34:32.056] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:34:32.057] <TB1> INFO: ----------------------------------------------------------------------
[11:34:32.057] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:34:32.057] <TB1> INFO: ----------------------------------------------------------------------
[11:34:32.299] <TB1> INFO: Expecting 41600 events.
[11:34:35.248] <TB1> INFO: 41600 events read in total (2357ms).
[11:34:35.249] <TB1> INFO: Test took 3189ms.
[11:34:35.249] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:34:35.489] <TB1> INFO: PixTestAlive::maskTest() done
[11:34:35.489] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:34:35.491] <TB1> INFO: ----------------------------------------------------------------------
[11:34:35.491] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:34:35.491] <TB1> INFO: ----------------------------------------------------------------------
[11:34:35.736] <TB1> INFO: Expecting 41600 events.
[11:34:39.362] <TB1> INFO: 41600 events read in total (3035ms).
[11:34:39.363] <TB1> INFO: Test took 3870ms.
[11:34:39.599] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[11:34:39.599] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:34:39.599] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:34:39.599] <TB1> INFO: Decoding statistics:
[11:34:39.599] <TB1> INFO: General information:
[11:34:39.599] <TB1> INFO: 16bit words read: 0
[11:34:39.599] <TB1> INFO: valid events total: 0
[11:34:39.599] <TB1> INFO: empty events: 0
[11:34:39.599] <TB1> INFO: valid events with pixels: 0
[11:34:39.599] <TB1> INFO: valid pixel hits: 0
[11:34:39.599] <TB1> INFO: Event errors: 0
[11:34:39.599] <TB1> INFO: start marker: 0
[11:34:39.599] <TB1> INFO: stop marker: 0
[11:34:39.600] <TB1> INFO: overflow: 0
[11:34:39.600] <TB1> INFO: invalid 5bit words: 0
[11:34:39.600] <TB1> INFO: invalid XOR eye diagram: 0
[11:34:39.600] <TB1> INFO: frame (failed synchr.): 0
[11:34:39.600] <TB1> INFO: idle data (no TBM trl): 0
[11:34:39.600] <TB1> INFO: no data (only TBM hdr): 0
[11:34:39.600] <TB1> INFO: TBM errors: 0
[11:34:39.600] <TB1> INFO: flawed TBM headers: 0
[11:34:39.600] <TB1> INFO: flawed TBM trailers: 0
[11:34:39.600] <TB1> INFO: event ID mismatches: 0
[11:34:39.600] <TB1> INFO: ROC errors: 0
[11:34:39.600] <TB1> INFO: missing ROC header(s): 0
[11:34:39.600] <TB1> INFO: misplaced readback start: 0
[11:34:39.600] <TB1> INFO: Pixel decoding errors: 0
[11:34:39.600] <TB1> INFO: pixel data incomplete: 0
[11:34:39.600] <TB1> INFO: pixel address: 0
[11:34:39.600] <TB1> INFO: pulse height fill bit: 0
[11:34:39.600] <TB1> INFO: buffer corruption: 0
[11:34:39.608] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C15.dat
[11:34:39.609] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[11:34:39.609] <TB1> INFO: ######################################################################
[11:34:39.609] <TB1> INFO: PixTestReadback::doTest()
[11:34:39.609] <TB1> INFO: ######################################################################
[11:34:39.609] <TB1> INFO: ----------------------------------------------------------------------
[11:34:39.609] <TB1> INFO: PixTestReadback::CalibrateVd()
[11:34:39.609] <TB1> INFO: ----------------------------------------------------------------------
[11:34:49.586] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C0.dat
[11:34:49.586] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C1.dat
[11:34:49.587] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C2.dat
[11:34:49.587] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C3.dat
[11:34:49.587] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C4.dat
[11:34:49.587] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C5.dat
[11:34:49.587] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C6.dat
[11:34:49.587] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C7.dat
[11:34:49.587] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C8.dat
[11:34:49.587] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C9.dat
[11:34:49.587] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C10.dat
[11:34:49.587] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C11.dat
[11:34:49.588] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C12.dat
[11:34:49.588] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C13.dat
[11:34:49.588] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C14.dat
[11:34:49.588] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C15.dat
[11:34:49.620] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:34:49.620] <TB1> INFO: ----------------------------------------------------------------------
[11:34:49.620] <TB1> INFO: PixTestReadback::CalibrateVa()
[11:34:49.620] <TB1> INFO: ----------------------------------------------------------------------
[11:34:59.546] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C0.dat
[11:34:59.546] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C1.dat
[11:34:59.546] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C2.dat
[11:34:59.546] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C3.dat
[11:34:59.546] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C4.dat
[11:34:59.546] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C5.dat
[11:34:59.546] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C6.dat
[11:34:59.546] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C7.dat
[11:34:59.546] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C8.dat
[11:34:59.546] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C9.dat
[11:34:59.546] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C10.dat
[11:34:59.546] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C11.dat
[11:34:59.546] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C12.dat
[11:34:59.547] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C13.dat
[11:34:59.547] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C14.dat
[11:34:59.547] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C15.dat
[11:34:59.576] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:34:59.576] <TB1> INFO: ----------------------------------------------------------------------
[11:34:59.576] <TB1> INFO: PixTestReadback::readbackVbg()
[11:34:59.576] <TB1> INFO: ----------------------------------------------------------------------
[11:35:07.247] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:35:07.247] <TB1> INFO: ----------------------------------------------------------------------
[11:35:07.247] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[11:35:07.247] <TB1> INFO: ----------------------------------------------------------------------
[11:35:07.247] <TB1> INFO: Vbg will be calibrated using Vd calibration
[11:35:07.247] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 161.6calibrated Vbg = 1.18359 :::*/*/*/*/
[11:35:07.247] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 159.1calibrated Vbg = 1.17419 :::*/*/*/*/
[11:35:07.247] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 146.9calibrated Vbg = 1.17642 :::*/*/*/*/
[11:35:07.247] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 156calibrated Vbg = 1.18179 :::*/*/*/*/
[11:35:07.247] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 154.5calibrated Vbg = 1.18519 :::*/*/*/*/
[11:35:07.248] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 148.2calibrated Vbg = 1.18104 :::*/*/*/*/
[11:35:07.248] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 152.7calibrated Vbg = 1.18726 :::*/*/*/*/
[11:35:07.248] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 172.6calibrated Vbg = 1.1827 :::*/*/*/*/
[11:35:07.248] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 152calibrated Vbg = 1.17888 :::*/*/*/*/
[11:35:07.248] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 154.9calibrated Vbg = 1.17397 :::*/*/*/*/
[11:35:07.248] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 155.6calibrated Vbg = 1.16625 :::*/*/*/*/
[11:35:07.248] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 153.6calibrated Vbg = 1.16129 :::*/*/*/*/
[11:35:07.248] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 159calibrated Vbg = 1.17448 :::*/*/*/*/
[11:35:07.248] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 155.7calibrated Vbg = 1.18267 :::*/*/*/*/
[11:35:07.248] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 162.7calibrated Vbg = 1.18318 :::*/*/*/*/
[11:35:07.248] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 156.4calibrated Vbg = 1.18287 :::*/*/*/*/
[11:35:07.251] <TB1> INFO: ----------------------------------------------------------------------
[11:35:07.251] <TB1> INFO: PixTestReadback::CalibrateIa()
[11:35:07.251] <TB1> INFO: ----------------------------------------------------------------------
[11:37:48.053] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C0.dat
[11:37:48.053] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C1.dat
[11:37:48.053] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C2.dat
[11:37:48.053] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C3.dat
[11:37:48.053] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C4.dat
[11:37:48.054] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C5.dat
[11:37:48.054] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C6.dat
[11:37:48.054] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C7.dat
[11:37:48.054] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C8.dat
[11:37:48.054] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C9.dat
[11:37:48.054] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C10.dat
[11:37:48.054] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C11.dat
[11:37:48.054] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C12.dat
[11:37:48.054] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C13.dat
[11:37:48.054] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C14.dat
[11:37:48.054] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//readbackCal_C15.dat
[11:37:48.082] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:37:48.084] <TB1> INFO: PixTestReadback::doTest() done
[11:37:48.085] <TB1> INFO: Decoding statistics:
[11:37:48.085] <TB1> INFO: General information:
[11:37:48.085] <TB1> INFO: 16bit words read: 1536
[11:37:48.085] <TB1> INFO: valid events total: 256
[11:37:48.085] <TB1> INFO: empty events: 256
[11:37:48.085] <TB1> INFO: valid events with pixels: 0
[11:37:48.085] <TB1> INFO: valid pixel hits: 0
[11:37:48.085] <TB1> INFO: Event errors: 0
[11:37:48.085] <TB1> INFO: start marker: 0
[11:37:48.085] <TB1> INFO: stop marker: 0
[11:37:48.085] <TB1> INFO: overflow: 0
[11:37:48.085] <TB1> INFO: invalid 5bit words: 0
[11:37:48.085] <TB1> INFO: invalid XOR eye diagram: 0
[11:37:48.085] <TB1> INFO: frame (failed synchr.): 0
[11:37:48.085] <TB1> INFO: idle data (no TBM trl): 0
[11:37:48.085] <TB1> INFO: no data (only TBM hdr): 0
[11:37:48.085] <TB1> INFO: TBM errors: 0
[11:37:48.085] <TB1> INFO: flawed TBM headers: 0
[11:37:48.085] <TB1> INFO: flawed TBM trailers: 0
[11:37:48.085] <TB1> INFO: event ID mismatches: 0
[11:37:48.085] <TB1> INFO: ROC errors: 0
[11:37:48.085] <TB1> INFO: missing ROC header(s): 0
[11:37:48.085] <TB1> INFO: misplaced readback start: 0
[11:37:48.085] <TB1> INFO: Pixel decoding errors: 0
[11:37:48.085] <TB1> INFO: pixel data incomplete: 0
[11:37:48.085] <TB1> INFO: pixel address: 0
[11:37:48.085] <TB1> INFO: pulse height fill bit: 0
[11:37:48.085] <TB1> INFO: buffer corruption: 0
[11:37:48.136] <TB1> INFO: ######################################################################
[11:37:48.136] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[11:37:48.136] <TB1> INFO: ######################################################################
[11:37:48.139] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[11:37:48.152] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:37:48.152] <TB1> INFO: run 1 of 1
[11:37:48.388] <TB1> INFO: Expecting 3120000 events.
[11:38:19.221] <TB1> INFO: 657455 events read in total (30241ms).











[11:38:48.783] <TB1> INFO: 1307325 events read in total (59803ms).











[11:39:18.461] <TB1> INFO: 1952305 events read in total (89481ms).











[11:39:47.952] <TB1> INFO: 2597190 events read in total (118972ms).











[11:40:11.865] <TB1> INFO: 3120000 events read in total (142885ms).
[11:40:11.949] <TB1> INFO: Test took 143798ms.
[11:40:36.907] <TB1> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 168 seconds
[11:40:36.907] <TB1> INFO: number of dead bumps (per ROC): 0 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0
[11:40:36.907] <TB1> INFO: separation cut (per ROC): 109 107 109 96 112 97 91 106 101 101 119 115 106 95 97 99
[11:40:36.908] <TB1> INFO: Decoding statistics:
[11:40:36.908] <TB1> INFO: General information:
[11:40:36.908] <TB1> INFO: 16bit words read: 0
[11:40:36.908] <TB1> INFO: valid events total: 0
[11:40:36.908] <TB1> INFO: empty events: 0
[11:40:36.908] <TB1> INFO: valid events with pixels: 0
[11:40:36.908] <TB1> INFO: valid pixel hits: 0
[11:40:36.908] <TB1> INFO: Event errors: 0
[11:40:36.908] <TB1> INFO: start marker: 0
[11:40:36.908] <TB1> INFO: stop marker: 0
[11:40:36.908] <TB1> INFO: overflow: 0
[11:40:36.908] <TB1> INFO: invalid 5bit words: 0
[11:40:36.908] <TB1> INFO: invalid XOR eye diagram: 0
[11:40:36.908] <TB1> INFO: frame (failed synchr.): 0
[11:40:36.908] <TB1> INFO: idle data (no TBM trl): 0
[11:40:36.908] <TB1> INFO: no data (only TBM hdr): 0
[11:40:36.908] <TB1> INFO: TBM errors: 0
[11:40:36.908] <TB1> INFO: flawed TBM headers: 0
[11:40:36.908] <TB1> INFO: flawed TBM trailers: 0
[11:40:36.908] <TB1> INFO: event ID mismatches: 0
[11:40:36.908] <TB1> INFO: ROC errors: 0
[11:40:36.909] <TB1> INFO: missing ROC header(s): 0
[11:40:36.909] <TB1> INFO: misplaced readback start: 0
[11:40:36.909] <TB1> INFO: Pixel decoding errors: 0
[11:40:36.909] <TB1> INFO: pixel data incomplete: 0
[11:40:36.909] <TB1> INFO: pixel address: 0
[11:40:36.909] <TB1> INFO: pulse height fill bit: 0
[11:40:36.909] <TB1> INFO: buffer corruption: 0
[11:40:36.951] <TB1> INFO: ######################################################################
[11:40:36.951] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:40:36.951] <TB1> INFO: ######################################################################
[11:40:36.951] <TB1> INFO: ----------------------------------------------------------------------
[11:40:36.951] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:40:36.951] <TB1> INFO: ----------------------------------------------------------------------
[11:40:36.951] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[11:40:36.965] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[11:40:36.965] <TB1> INFO: run 1 of 1
[11:40:37.208] <TB1> INFO: Expecting 36608000 events.
[11:41:00.951] <TB1> INFO: 675050 events read in total (23142ms).
[11:41:23.453] <TB1> INFO: 1335500 events read in total (45644ms).
[11:41:46.306] <TB1> INFO: 1994150 events read in total (68497ms).
[11:42:08.863] <TB1> INFO: 2650900 events read in total (91054ms).
[11:42:31.739] <TB1> INFO: 3310250 events read in total (113930ms).
[11:42:54.372] <TB1> INFO: 3969900 events read in total (136563ms).
[11:43:17.052] <TB1> INFO: 4627650 events read in total (159243ms).
[11:43:39.483] <TB1> INFO: 5284500 events read in total (181674ms).
[11:44:02.233] <TB1> INFO: 5941800 events read in total (204424ms).
[11:44:25.214] <TB1> INFO: 6601950 events read in total (227405ms).
[11:44:48.086] <TB1> INFO: 7261650 events read in total (250277ms).
[11:45:10.828] <TB1> INFO: 7919300 events read in total (273019ms).
[11:45:33.524] <TB1> INFO: 8578200 events read in total (295715ms).
[11:45:56.536] <TB1> INFO: 9236250 events read in total (318727ms).
[11:46:19.786] <TB1> INFO: 9892050 events read in total (341977ms).
[11:46:42.745] <TB1> INFO: 10549350 events read in total (364936ms).
[11:47:05.786] <TB1> INFO: 11205750 events read in total (387977ms).
[11:47:28.950] <TB1> INFO: 11860550 events read in total (411141ms).
[11:47:51.992] <TB1> INFO: 12514600 events read in total (434183ms).
[11:48:14.730] <TB1> INFO: 13170200 events read in total (456921ms).
[11:48:37.791] <TB1> INFO: 13824300 events read in total (479982ms).
[11:49:00.780] <TB1> INFO: 14478750 events read in total (502971ms).
[11:49:23.587] <TB1> INFO: 15132300 events read in total (525778ms).
[11:49:46.501] <TB1> INFO: 15785200 events read in total (548692ms).
[11:50:09.414] <TB1> INFO: 16438550 events read in total (571605ms).
[11:50:32.140] <TB1> INFO: 17091800 events read in total (594331ms).
[11:50:54.687] <TB1> INFO: 17741700 events read in total (616878ms).
[11:51:17.794] <TB1> INFO: 18390350 events read in total (639985ms).
[11:51:40.165] <TB1> INFO: 19040200 events read in total (662356ms).
[11:52:02.702] <TB1> INFO: 19686500 events read in total (684893ms).
[11:52:25.365] <TB1> INFO: 20336050 events read in total (707556ms).
[11:52:47.949] <TB1> INFO: 20983900 events read in total (730140ms).
[11:53:10.406] <TB1> INFO: 21631400 events read in total (752597ms).
[11:53:33.070] <TB1> INFO: 22279350 events read in total (775261ms).
[11:53:55.564] <TB1> INFO: 22927850 events read in total (797755ms).
[11:54:17.965] <TB1> INFO: 23574950 events read in total (820156ms).
[11:54:40.416] <TB1> INFO: 24223150 events read in total (842607ms).
[11:55:02.955] <TB1> INFO: 24869000 events read in total (865146ms).
[11:55:25.237] <TB1> INFO: 25516450 events read in total (887428ms).
[11:55:47.878] <TB1> INFO: 26164650 events read in total (910069ms).
[11:56:10.411] <TB1> INFO: 26812100 events read in total (932602ms).
[11:56:32.826] <TB1> INFO: 27460650 events read in total (955017ms).
[11:56:55.363] <TB1> INFO: 28106000 events read in total (977554ms).
[11:57:17.859] <TB1> INFO: 28752700 events read in total (1000050ms).
[11:57:40.350] <TB1> INFO: 29398850 events read in total (1022541ms).
[11:58:03.265] <TB1> INFO: 30046400 events read in total (1045456ms).
[11:58:25.936] <TB1> INFO: 30693150 events read in total (1068127ms).
[11:58:48.537] <TB1> INFO: 31340100 events read in total (1090728ms).
[11:59:10.844] <TB1> INFO: 31986350 events read in total (1113035ms).
[11:59:33.734] <TB1> INFO: 32634350 events read in total (1135925ms).
[11:59:56.331] <TB1> INFO: 33280950 events read in total (1158522ms).
[12:00:19.120] <TB1> INFO: 33928000 events read in total (1181311ms).
[12:00:41.785] <TB1> INFO: 34573700 events read in total (1203976ms).
[12:01:04.292] <TB1> INFO: 35220650 events read in total (1226483ms).
[12:01:26.804] <TB1> INFO: 35867600 events read in total (1248995ms).
[12:01:49.718] <TB1> INFO: 36525600 events read in total (1271909ms).
[12:01:53.043] <TB1> INFO: 36608000 events read in total (1275234ms).
[12:01:53.118] <TB1> INFO: Test took 1276153ms.
[12:01:53.608] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:01:55.201] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:01:56.961] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:01:58.873] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:02:01.093] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:02:03.221] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:02:05.487] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:02:07.575] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:02:09.959] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:02:12.388] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:02:14.851] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:02:16.470] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:02:18.495] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:02:20.619] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:02:22.954] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:02:25.030] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:02:26.813] <TB1> INFO: PixTestScurves::scurves() done
[12:02:26.813] <TB1> INFO: Vcal mean: 124.42 117.12 122.91 116.95 116.94 106.81 103.41 116.13 103.09 108.21 120.80 119.56 112.53 108.10 108.01 106.70
[12:02:26.813] <TB1> INFO: Vcal RMS: 5.84 5.40 6.99 6.02 5.78 5.22 5.30 6.28 5.76 5.40 6.33 6.02 5.01 4.75 5.49 5.12
[12:02:26.814] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1309 seconds
[12:02:26.814] <TB1> INFO: Decoding statistics:
[12:02:26.814] <TB1> INFO: General information:
[12:02:26.814] <TB1> INFO: 16bit words read: 0
[12:02:26.814] <TB1> INFO: valid events total: 0
[12:02:26.814] <TB1> INFO: empty events: 0
[12:02:26.814] <TB1> INFO: valid events with pixels: 0
[12:02:26.814] <TB1> INFO: valid pixel hits: 0
[12:02:26.814] <TB1> INFO: Event errors: 0
[12:02:26.814] <TB1> INFO: start marker: 0
[12:02:26.814] <TB1> INFO: stop marker: 0
[12:02:26.814] <TB1> INFO: overflow: 0
[12:02:26.814] <TB1> INFO: invalid 5bit words: 0
[12:02:26.814] <TB1> INFO: invalid XOR eye diagram: 0
[12:02:26.814] <TB1> INFO: frame (failed synchr.): 0
[12:02:26.814] <TB1> INFO: idle data (no TBM trl): 0
[12:02:26.814] <TB1> INFO: no data (only TBM hdr): 0
[12:02:26.814] <TB1> INFO: TBM errors: 0
[12:02:26.814] <TB1> INFO: flawed TBM headers: 0
[12:02:26.814] <TB1> INFO: flawed TBM trailers: 0
[12:02:26.814] <TB1> INFO: event ID mismatches: 0
[12:02:26.814] <TB1> INFO: ROC errors: 0
[12:02:26.814] <TB1> INFO: missing ROC header(s): 0
[12:02:26.814] <TB1> INFO: misplaced readback start: 0
[12:02:26.814] <TB1> INFO: Pixel decoding errors: 0
[12:02:26.814] <TB1> INFO: pixel data incomplete: 0
[12:02:26.814] <TB1> INFO: pixel address: 0
[12:02:26.814] <TB1> INFO: pulse height fill bit: 0
[12:02:26.814] <TB1> INFO: buffer corruption: 0
[12:02:26.887] <TB1> INFO: ######################################################################
[12:02:26.888] <TB1> INFO: PixTestTrim::doTest()
[12:02:26.888] <TB1> INFO: ######################################################################
[12:02:26.889] <TB1> INFO: ----------------------------------------------------------------------
[12:02:26.889] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:02:26.889] <TB1> INFO: ----------------------------------------------------------------------
[12:02:26.942] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:02:26.942] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:02:26.956] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:02:26.956] <TB1> INFO: run 1 of 1
[12:02:27.264] <TB1> INFO: Expecting 5025280 events.
[12:02:57.892] <TB1> INFO: 818160 events read in total (30033ms).
[12:03:27.799] <TB1> INFO: 1634024 events read in total (59940ms).
[12:03:57.760] <TB1> INFO: 2445240 events read in total (89901ms).
[12:04:27.492] <TB1> INFO: 3251856 events read in total (119633ms).
[12:04:57.069] <TB1> INFO: 4055672 events read in total (149210ms).
[12:05:27.398] <TB1> INFO: 4858680 events read in total (179539ms).
[12:05:34.322] <TB1> INFO: 5025280 events read in total (186463ms).
[12:05:34.377] <TB1> INFO: Test took 187421ms.
[12:05:54.950] <TB1> INFO: ROC 0 VthrComp = 133
[12:05:54.950] <TB1> INFO: ROC 1 VthrComp = 127
[12:05:54.950] <TB1> INFO: ROC 2 VthrComp = 130
[12:05:54.950] <TB1> INFO: ROC 3 VthrComp = 115
[12:05:54.951] <TB1> INFO: ROC 4 VthrComp = 132
[12:05:54.951] <TB1> INFO: ROC 5 VthrComp = 112
[12:05:54.952] <TB1> INFO: ROC 6 VthrComp = 107
[12:05:54.952] <TB1> INFO: ROC 7 VthrComp = 115
[12:05:54.952] <TB1> INFO: ROC 8 VthrComp = 109
[12:05:54.952] <TB1> INFO: ROC 9 VthrComp = 117
[12:05:54.952] <TB1> INFO: ROC 10 VthrComp = 132
[12:05:54.952] <TB1> INFO: ROC 11 VthrComp = 130
[12:05:54.954] <TB1> INFO: ROC 12 VthrComp = 119
[12:05:54.954] <TB1> INFO: ROC 13 VthrComp = 110
[12:05:54.955] <TB1> INFO: ROC 14 VthrComp = 115
[12:05:54.955] <TB1> INFO: ROC 15 VthrComp = 109
[12:05:55.262] <TB1> INFO: Expecting 41600 events.
[12:05:58.759] <TB1> INFO: 41600 events read in total (2905ms).
[12:05:58.760] <TB1> INFO: Test took 3804ms.
[12:05:58.769] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:05:58.769] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:05:58.780] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:05:58.780] <TB1> INFO: run 1 of 1
[12:05:59.058] <TB1> INFO: Expecting 5025280 events.
[12:06:25.350] <TB1> INFO: 591256 events read in total (25701ms).
[12:06:51.276] <TB1> INFO: 1181552 events read in total (51627ms).
[12:07:17.058] <TB1> INFO: 1772160 events read in total (77409ms).
[12:07:42.070] <TB1> INFO: 2362232 events read in total (102421ms).
[12:08:07.776] <TB1> INFO: 2949760 events read in total (128127ms).
[12:08:33.525] <TB1> INFO: 3535872 events read in total (153876ms).
[12:08:59.511] <TB1> INFO: 4121488 events read in total (179862ms).
[12:09:24.724] <TB1> INFO: 4706696 events read in total (205075ms).
[12:09:39.348] <TB1> INFO: 5025280 events read in total (219699ms).
[12:09:39.444] <TB1> INFO: Test took 220665ms.
[12:10:04.761] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 63.8707 for pixel 18/8 mean/min/max = 48.9074/33.8971/63.9177
[12:10:04.761] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 58.9173 for pixel 41/12 mean/min/max = 45.4957/32.0661/58.9252
[12:10:04.761] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 62.6408 for pixel 16/13 mean/min/max = 47.408/32.0865/62.7295
[12:10:04.762] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 64.4187 for pixel 49/3 mean/min/max = 47.6351/30.7214/64.5488
[12:10:04.762] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 59.2096 for pixel 36/20 mean/min/max = 45.9399/32.5775/59.3023
[12:10:04.762] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 59.6719 for pixel 0/9 mean/min/max = 45.7095/31.7386/59.6804
[12:10:04.763] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 63.6143 for pixel 25/2 mean/min/max = 48.8127/33.9573/63.6681
[12:10:04.763] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 65.3815 for pixel 13/78 mean/min/max = 48.0092/30.2275/65.791
[12:10:04.763] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 63.0891 for pixel 0/16 mean/min/max = 48.5297/33.8957/63.1636
[12:10:04.764] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 58.965 for pixel 46/0 mean/min/max = 45.1494/31.1431/59.1556
[12:10:04.764] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 62.1027 for pixel 14/3 mean/min/max = 47.8158/33.4159/62.2158
[12:10:04.765] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 58.8524 for pixel 0/47 mean/min/max = 45.2562/31.6275/58.8849
[12:10:04.765] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 58.755 for pixel 0/4 mean/min/max = 45.0778/31.3743/58.7812
[12:10:04.766] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 61.2117 for pixel 32/15 mean/min/max = 47.849/34.1642/61.5337
[12:10:04.766] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 61.3687 for pixel 0/20 mean/min/max = 46.6796/31.9633/61.3959
[12:10:04.767] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 61.5773 for pixel 36/38 mean/min/max = 47.734/33.6745/61.7935
[12:10:04.767] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:10:04.856] <TB1> INFO: Expecting 411648 events.
[12:10:14.191] <TB1> INFO: 411648 events read in total (8744ms).
[12:10:14.201] <TB1> INFO: Expecting 411648 events.
[12:10:23.304] <TB1> INFO: 411648 events read in total (8700ms).
[12:10:23.315] <TB1> INFO: Expecting 411648 events.
[12:10:32.644] <TB1> INFO: 411648 events read in total (8925ms).
[12:10:32.658] <TB1> INFO: Expecting 411648 events.
[12:10:41.978] <TB1> INFO: 411648 events read in total (8917ms).
[12:10:41.994] <TB1> INFO: Expecting 411648 events.
[12:10:51.410] <TB1> INFO: 411648 events read in total (9012ms).
[12:10:51.429] <TB1> INFO: Expecting 411648 events.
[12:11:00.768] <TB1> INFO: 411648 events read in total (8936ms).
[12:11:00.790] <TB1> INFO: Expecting 411648 events.
[12:11:10.180] <TB1> INFO: 411648 events read in total (8987ms).
[12:11:10.212] <TB1> INFO: Expecting 411648 events.
[12:11:19.601] <TB1> INFO: 411648 events read in total (8986ms).
[12:11:19.628] <TB1> INFO: Expecting 411648 events.
[12:11:28.974] <TB1> INFO: 411648 events read in total (8943ms).
[12:11:29.009] <TB1> INFO: Expecting 411648 events.
[12:11:38.406] <TB1> INFO: 411648 events read in total (8994ms).
[12:11:38.441] <TB1> INFO: Expecting 411648 events.
[12:11:47.863] <TB1> INFO: 411648 events read in total (9019ms).
[12:11:47.901] <TB1> INFO: Expecting 411648 events.
[12:11:57.295] <TB1> INFO: 411648 events read in total (8991ms).
[12:11:57.334] <TB1> INFO: Expecting 411648 events.
[12:12:06.697] <TB1> INFO: 411648 events read in total (8959ms).
[12:12:06.739] <TB1> INFO: Expecting 411648 events.
[12:12:16.099] <TB1> INFO: 411648 events read in total (8957ms).
[12:12:16.158] <TB1> INFO: Expecting 411648 events.
[12:12:25.446] <TB1> INFO: 411648 events read in total (8885ms).
[12:12:25.493] <TB1> INFO: Expecting 411648 events.
[12:12:34.741] <TB1> INFO: 411648 events read in total (8845ms).
[12:12:34.815] <TB1> INFO: Test took 150048ms.
[12:12:35.714] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:12:35.729] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:12:35.729] <TB1> INFO: run 1 of 1
[12:12:35.965] <TB1> INFO: Expecting 5025280 events.
[12:13:01.985] <TB1> INFO: 585432 events read in total (25428ms).
[12:13:27.478] <TB1> INFO: 1170184 events read in total (50921ms).
[12:13:53.136] <TB1> INFO: 1754696 events read in total (76579ms).
[12:14:19.124] <TB1> INFO: 2338400 events read in total (102567ms).
[12:14:45.048] <TB1> INFO: 2921176 events read in total (128491ms).
[12:15:10.986] <TB1> INFO: 3502552 events read in total (154429ms).
[12:15:36.715] <TB1> INFO: 4083384 events read in total (180158ms).
[12:16:02.288] <TB1> INFO: 4663288 events read in total (205731ms).
[12:16:18.607] <TB1> INFO: 5025280 events read in total (222050ms).
[12:16:18.820] <TB1> INFO: Test took 223092ms.
[12:16:45.648] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 8.030032 .. 145.803418
[12:16:45.974] <TB1> INFO: Expecting 208000 events.
[12:16:55.524] <TB1> INFO: 208000 events read in total (8959ms).
[12:16:55.525] <TB1> INFO: Test took 9876ms.
[12:16:55.574] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 8 .. 155 (-1/-1) hits flags = 528 (plus default)
[12:16:55.587] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:16:55.587] <TB1> INFO: run 1 of 1
[12:16:55.865] <TB1> INFO: Expecting 4925440 events.
[12:17:22.456] <TB1> INFO: 574880 events read in total (26000ms).
[12:17:47.774] <TB1> INFO: 1149688 events read in total (51319ms).
[12:18:13.274] <TB1> INFO: 1724944 events read in total (76818ms).
[12:18:38.911] <TB1> INFO: 2300200 events read in total (102455ms).
[12:19:04.645] <TB1> INFO: 2875272 events read in total (128189ms).
[12:19:29.937] <TB1> INFO: 3450056 events read in total (153481ms).
[12:19:55.453] <TB1> INFO: 4024560 events read in total (178997ms).
[12:20:20.627] <TB1> INFO: 4598568 events read in total (204171ms).
[12:20:35.446] <TB1> INFO: 4925440 events read in total (218990ms).
[12:20:35.567] <TB1> INFO: Test took 219980ms.
[12:21:04.386] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.075854 .. 46.877519
[12:21:04.670] <TB1> INFO: Expecting 208000 events.
[12:21:14.418] <TB1> INFO: 208000 events read in total (9156ms).
[12:21:14.419] <TB1> INFO: Test took 10032ms.
[12:21:14.468] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[12:21:14.481] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:21:14.481] <TB1> INFO: run 1 of 1
[12:21:14.759] <TB1> INFO: Expecting 1331200 events.
[12:21:42.952] <TB1> INFO: 655208 events read in total (27601ms).
[12:22:10.659] <TB1> INFO: 1308776 events read in total (55308ms).
[12:22:12.120] <TB1> INFO: 1331200 events read in total (56769ms).
[12:22:12.154] <TB1> INFO: Test took 57674ms.
[12:22:27.193] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 26.309629 .. 46.873057
[12:22:27.429] <TB1> INFO: Expecting 208000 events.
[12:22:37.175] <TB1> INFO: 208000 events read in total (9153ms).
[12:22:37.176] <TB1> INFO: Test took 9982ms.
[12:22:37.228] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 56 (-1/-1) hits flags = 528 (plus default)
[12:22:37.241] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:22:37.241] <TB1> INFO: run 1 of 1
[12:22:37.519] <TB1> INFO: Expecting 1364480 events.
[12:23:05.712] <TB1> INFO: 659200 events read in total (27601ms).
[12:23:33.692] <TB1> INFO: 1318072 events read in total (55581ms).
[12:23:36.189] <TB1> INFO: 1364480 events read in total (58078ms).
[12:23:36.224] <TB1> INFO: Test took 58983ms.
[12:23:52.178] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 23.493070 .. 44.267291
[12:23:52.511] <TB1> INFO: Expecting 208000 events.
[12:24:02.667] <TB1> INFO: 208000 events read in total (9564ms).
[12:24:02.668] <TB1> INFO: Test took 10488ms.
[12:24:02.736] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 13 .. 54 (-1/-1) hits flags = 528 (plus default)
[12:24:02.750] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:24:02.750] <TB1> INFO: run 1 of 1
[12:24:03.028] <TB1> INFO: Expecting 1397760 events.
[12:24:31.528] <TB1> INFO: 679920 events read in total (27908ms).
[12:24:59.748] <TB1> INFO: 1359304 events read in total (56128ms).
[12:25:01.728] <TB1> INFO: 1397760 events read in total (58108ms).
[12:25:01.752] <TB1> INFO: Test took 59003ms.
[12:25:17.341] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:25:17.341] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:25:17.354] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:25:17.354] <TB1> INFO: run 1 of 1
[12:25:17.629] <TB1> INFO: Expecting 1364480 events.
[12:25:45.705] <TB1> INFO: 667160 events read in total (27484ms).
[12:26:14.255] <TB1> INFO: 1334256 events read in total (56035ms).
[12:26:15.888] <TB1> INFO: 1364480 events read in total (57667ms).
[12:26:15.915] <TB1> INFO: Test took 58561ms.
[12:26:30.958] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C0.dat
[12:26:30.959] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C1.dat
[12:26:30.959] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C2.dat
[12:26:30.959] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C3.dat
[12:26:30.959] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C4.dat
[12:26:30.959] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C5.dat
[12:26:30.959] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C6.dat
[12:26:30.960] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C7.dat
[12:26:30.960] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C8.dat
[12:26:30.960] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C9.dat
[12:26:30.960] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C10.dat
[12:26:30.960] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C11.dat
[12:26:30.960] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C12.dat
[12:26:30.960] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C13.dat
[12:26:30.960] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C14.dat
[12:26:30.961] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C15.dat
[12:26:30.961] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C0.dat
[12:26:30.969] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C1.dat
[12:26:30.974] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C2.dat
[12:26:30.979] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C3.dat
[12:26:30.984] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C4.dat
[12:26:30.989] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C5.dat
[12:26:30.994] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C6.dat
[12:26:30.999] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C7.dat
[12:26:31.004] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C8.dat
[12:26:31.009] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C9.dat
[12:26:31.014] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C10.dat
[12:26:31.018] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C11.dat
[12:26:31.023] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C12.dat
[12:26:31.028] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C13.dat
[12:26:31.033] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C14.dat
[12:26:31.038] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//trimParameters35_C15.dat
[12:26:31.043] <TB1> INFO: PixTestTrim::trimTest() done
[12:26:31.043] <TB1> INFO: vtrim: 167 142 170 135 152 121 144 137 142 151 154 136 121 132 129 139
[12:26:31.043] <TB1> INFO: vthrcomp: 133 127 130 115 132 112 107 115 109 117 132 130 119 110 115 109
[12:26:31.043] <TB1> INFO: vcal mean: 35.02 34.97 35.01 35.00 34.97 35.00 35.00 34.98 35.01 35.03 34.98 34.91 34.99 34.95 35.01 35.00
[12:26:31.043] <TB1> INFO: vcal RMS: 1.09 1.03 1.09 1.21 0.99 0.98 0.98 1.28 0.96 1.02 1.01 0.99 0.98 1.01 0.99 1.01
[12:26:31.043] <TB1> INFO: bits mean: 9.10 9.82 9.50 9.48 9.48 9.31 9.08 9.70 8.60 10.04 8.84 9.27 9.39 9.02 8.59 9.24
[12:26:31.043] <TB1> INFO: bits RMS: 2.47 2.51 2.53 2.77 2.65 2.81 2.43 2.65 2.62 2.55 2.55 2.90 2.88 2.53 3.08 2.49
[12:26:31.050] <TB1> INFO: ----------------------------------------------------------------------
[12:26:31.050] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:26:31.051] <TB1> INFO: ----------------------------------------------------------------------
[12:26:31.053] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:26:31.065] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:26:31.066] <TB1> INFO: run 1 of 1
[12:26:31.302] <TB1> INFO: Expecting 4160000 events.
[12:27:03.422] <TB1> INFO: 740745 events read in total (31529ms).
[12:27:34.691] <TB1> INFO: 1475835 events read in total (62798ms).
[12:28:06.212] <TB1> INFO: 2204290 events read in total (94319ms).
[12:28:37.200] <TB1> INFO: 2927045 events read in total (125307ms).
[12:29:08.449] <TB1> INFO: 3648850 events read in total (156556ms).
[12:29:30.490] <TB1> INFO: 4160000 events read in total (178597ms).
[12:29:30.561] <TB1> INFO: Test took 179495ms.
[12:29:59.858] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[12:29:59.872] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:29:59.872] <TB1> INFO: run 1 of 1
[12:30:00.109] <TB1> INFO: Expecting 4243200 events.
[12:30:31.603] <TB1> INFO: 713190 events read in total (30902ms).
[12:31:03.227] <TB1> INFO: 1422620 events read in total (62526ms).
[12:31:34.375] <TB1> INFO: 2126095 events read in total (93674ms).
[12:32:05.307] <TB1> INFO: 2824110 events read in total (124606ms).
[12:32:36.422] <TB1> INFO: 3520970 events read in total (155721ms).
[12:33:07.016] <TB1> INFO: 4218675 events read in total (186315ms).
[12:33:08.443] <TB1> INFO: 4243200 events read in total (187742ms).
[12:33:08.507] <TB1> INFO: Test took 188635ms.
[12:33:36.397] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 188 (-1/-1) hits flags = 528 (plus default)
[12:33:36.410] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:33:36.410] <TB1> INFO: run 1 of 1
[12:33:36.648] <TB1> INFO: Expecting 3931200 events.
[12:34:08.660] <TB1> INFO: 733255 events read in total (31420ms).
[12:34:40.243] <TB1> INFO: 1461120 events read in total (63003ms).
[12:35:11.311] <TB1> INFO: 2181605 events read in total (94071ms).
[12:35:41.916] <TB1> INFO: 2897250 events read in total (124676ms).
[12:36:12.806] <TB1> INFO: 3611765 events read in total (155566ms).
[12:36:26.775] <TB1> INFO: 3931200 events read in total (169535ms).
[12:36:26.837] <TB1> INFO: Test took 170426ms.
[12:36:50.727] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 189 (-1/-1) hits flags = 528 (plus default)
[12:36:50.741] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:36:50.741] <TB1> INFO: run 1 of 1
[12:36:51.013] <TB1> INFO: Expecting 3952000 events.
[12:37:22.987] <TB1> INFO: 732225 events read in total (31382ms).
[12:37:54.149] <TB1> INFO: 1458960 events read in total (62544ms).
[12:38:25.198] <TB1> INFO: 2178540 events read in total (93593ms).
[12:38:56.328] <TB1> INFO: 2893405 events read in total (124723ms).
[12:39:27.533] <TB1> INFO: 3607110 events read in total (155928ms).
[12:39:42.570] <TB1> INFO: 3952000 events read in total (170965ms).
[12:39:42.653] <TB1> INFO: Test took 171912ms.
[12:40:06.655] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 188 (-1/-1) hits flags = 528 (plus default)
[12:40:06.671] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:40:06.671] <TB1> INFO: run 1 of 1
[12:40:06.908] <TB1> INFO: Expecting 3931200 events.
[12:40:38.908] <TB1> INFO: 734040 events read in total (31408ms).
[12:41:10.206] <TB1> INFO: 1462280 events read in total (62706ms).
[12:41:41.897] <TB1> INFO: 2183215 events read in total (94397ms).
[12:42:13.158] <TB1> INFO: 2899660 events read in total (125658ms).
[12:42:44.182] <TB1> INFO: 3614795 events read in total (156682ms).
[12:42:58.045] <TB1> INFO: 3931200 events read in total (170545ms).
[12:42:58.103] <TB1> INFO: Test took 171431ms.
[12:43:25.384] <TB1> INFO: PixTestTrim::trimBitTest() done
[12:43:25.385] <TB1> INFO: PixTestTrim::doTest() done, duration: 2458 seconds
[12:43:25.385] <TB1> INFO: Decoding statistics:
[12:43:25.385] <TB1> INFO: General information:
[12:43:25.385] <TB1> INFO: 16bit words read: 0
[12:43:25.385] <TB1> INFO: valid events total: 0
[12:43:25.385] <TB1> INFO: empty events: 0
[12:43:25.385] <TB1> INFO: valid events with pixels: 0
[12:43:25.385] <TB1> INFO: valid pixel hits: 0
[12:43:25.385] <TB1> INFO: Event errors: 0
[12:43:25.385] <TB1> INFO: start marker: 0
[12:43:25.385] <TB1> INFO: stop marker: 0
[12:43:25.385] <TB1> INFO: overflow: 0
[12:43:25.385] <TB1> INFO: invalid 5bit words: 0
[12:43:25.385] <TB1> INFO: invalid XOR eye diagram: 0
[12:43:25.385] <TB1> INFO: frame (failed synchr.): 0
[12:43:25.385] <TB1> INFO: idle data (no TBM trl): 0
[12:43:25.385] <TB1> INFO: no data (only TBM hdr): 0
[12:43:25.385] <TB1> INFO: TBM errors: 0
[12:43:25.385] <TB1> INFO: flawed TBM headers: 0
[12:43:25.385] <TB1> INFO: flawed TBM trailers: 0
[12:43:25.385] <TB1> INFO: event ID mismatches: 0
[12:43:25.385] <TB1> INFO: ROC errors: 0
[12:43:25.385] <TB1> INFO: missing ROC header(s): 0
[12:43:25.385] <TB1> INFO: misplaced readback start: 0
[12:43:25.385] <TB1> INFO: Pixel decoding errors: 0
[12:43:25.386] <TB1> INFO: pixel data incomplete: 0
[12:43:25.386] <TB1> INFO: pixel address: 0
[12:43:25.386] <TB1> INFO: pulse height fill bit: 0
[12:43:25.386] <TB1> INFO: buffer corruption: 0
[12:43:26.123] <TB1> INFO: ######################################################################
[12:43:26.123] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[12:43:26.123] <TB1> INFO: ######################################################################
[12:43:26.359] <TB1> INFO: Expecting 41600 events.
[12:43:29.819] <TB1> INFO: 41600 events read in total (2868ms).
[12:43:29.820] <TB1> INFO: Test took 3695ms.
[12:43:30.264] <TB1> INFO: Expecting 41600 events.
[12:43:33.829] <TB1> INFO: 41600 events read in total (2973ms).
[12:43:33.830] <TB1> INFO: Test took 3806ms.
[12:43:34.133] <TB1> INFO: Expecting 41600 events.
[12:43:37.631] <TB1> INFO: 41600 events read in total (2906ms).
[12:43:37.631] <TB1> INFO: Test took 3777ms.
[12:43:37.920] <TB1> INFO: Expecting 41600 events.
[12:43:41.405] <TB1> INFO: 41600 events read in total (2893ms).
[12:43:41.406] <TB1> INFO: Test took 3751ms.
[12:43:41.695] <TB1> INFO: Expecting 41600 events.
[12:43:45.234] <TB1> INFO: 41600 events read in total (2947ms).
[12:43:45.235] <TB1> INFO: Test took 3804ms.
[12:43:45.527] <TB1> INFO: Expecting 41600 events.
[12:43:49.098] <TB1> INFO: 41600 events read in total (2980ms).
[12:43:49.098] <TB1> INFO: Test took 3837ms.
[12:43:49.387] <TB1> INFO: Expecting 41600 events.
[12:43:52.855] <TB1> INFO: 41600 events read in total (2876ms).
[12:43:52.856] <TB1> INFO: Test took 3733ms.
[12:43:53.161] <TB1> INFO: Expecting 41600 events.
[12:43:56.637] <TB1> INFO: 41600 events read in total (2885ms).
[12:43:56.638] <TB1> INFO: Test took 3758ms.
[12:43:56.927] <TB1> INFO: Expecting 41600 events.
[12:44:00.507] <TB1> INFO: 41600 events read in total (2989ms).
[12:44:00.508] <TB1> INFO: Test took 3846ms.
[12:44:00.863] <TB1> INFO: Expecting 41600 events.
[12:44:04.462] <TB1> INFO: 41600 events read in total (3007ms).
[12:44:04.463] <TB1> INFO: Test took 3926ms.
[12:44:04.755] <TB1> INFO: Expecting 41600 events.
[12:44:08.223] <TB1> INFO: 41600 events read in total (2877ms).
[12:44:08.224] <TB1> INFO: Test took 3734ms.
[12:44:08.513] <TB1> INFO: Expecting 41600 events.
[12:44:12.190] <TB1> INFO: 41600 events read in total (3086ms).
[12:44:12.191] <TB1> INFO: Test took 3943ms.
[12:44:12.513] <TB1> INFO: Expecting 41600 events.
[12:44:16.235] <TB1> INFO: 41600 events read in total (3130ms).
[12:44:16.236] <TB1> INFO: Test took 4017ms.
[12:44:16.524] <TB1> INFO: Expecting 41600 events.
[12:44:20.133] <TB1> INFO: 41600 events read in total (3017ms).
[12:44:20.134] <TB1> INFO: Test took 3874ms.
[12:44:20.423] <TB1> INFO: Expecting 41600 events.
[12:44:24.076] <TB1> INFO: 41600 events read in total (3061ms).
[12:44:24.077] <TB1> INFO: Test took 3919ms.
[12:44:24.368] <TB1> INFO: Expecting 41600 events.
[12:44:27.849] <TB1> INFO: 41600 events read in total (2889ms).
[12:44:27.850] <TB1> INFO: Test took 3746ms.
[12:44:28.139] <TB1> INFO: Expecting 41600 events.
[12:44:31.807] <TB1> INFO: 41600 events read in total (3076ms).
[12:44:31.807] <TB1> INFO: Test took 3933ms.
[12:44:32.096] <TB1> INFO: Expecting 41600 events.
[12:44:35.614] <TB1> INFO: 41600 events read in total (2926ms).
[12:44:35.615] <TB1> INFO: Test took 3783ms.
[12:44:35.907] <TB1> INFO: Expecting 41600 events.
[12:44:39.381] <TB1> INFO: 41600 events read in total (2882ms).
[12:44:39.382] <TB1> INFO: Test took 3740ms.
[12:44:39.672] <TB1> INFO: Expecting 41600 events.
[12:44:43.212] <TB1> INFO: 41600 events read in total (2948ms).
[12:44:43.213] <TB1> INFO: Test took 3805ms.
[12:44:43.505] <TB1> INFO: Expecting 41600 events.
[12:44:47.018] <TB1> INFO: 41600 events read in total (2921ms).
[12:44:47.019] <TB1> INFO: Test took 3782ms.
[12:44:47.308] <TB1> INFO: Expecting 41600 events.
[12:44:50.929] <TB1> INFO: 41600 events read in total (3029ms).
[12:44:50.930] <TB1> INFO: Test took 3887ms.
[12:44:51.220] <TB1> INFO: Expecting 41600 events.
[12:44:54.754] <TB1> INFO: 41600 events read in total (2942ms).
[12:44:54.755] <TB1> INFO: Test took 3799ms.
[12:44:55.065] <TB1> INFO: Expecting 41600 events.
[12:44:58.625] <TB1> INFO: 41600 events read in total (2968ms).
[12:44:58.626] <TB1> INFO: Test took 3844ms.
[12:44:58.915] <TB1> INFO: Expecting 41600 events.
[12:45:02.506] <TB1> INFO: 41600 events read in total (2999ms).
[12:45:02.507] <TB1> INFO: Test took 3857ms.
[12:45:02.797] <TB1> INFO: Expecting 41600 events.
[12:45:06.380] <TB1> INFO: 41600 events read in total (2992ms).
[12:45:06.381] <TB1> INFO: Test took 3849ms.
[12:45:06.671] <TB1> INFO: Expecting 41600 events.
[12:45:10.216] <TB1> INFO: 41600 events read in total (2953ms).
[12:45:10.217] <TB1> INFO: Test took 3811ms.
[12:45:10.511] <TB1> INFO: Expecting 41600 events.
[12:45:13.980] <TB1> INFO: 41600 events read in total (2878ms).
[12:45:13.980] <TB1> INFO: Test took 3736ms.
[12:45:14.270] <TB1> INFO: Expecting 41600 events.
[12:45:17.731] <TB1> INFO: 41600 events read in total (2870ms).
[12:45:17.732] <TB1> INFO: Test took 3727ms.
[12:45:18.021] <TB1> INFO: Expecting 41600 events.
[12:45:21.488] <TB1> INFO: 41600 events read in total (2875ms).
[12:45:21.489] <TB1> INFO: Test took 3733ms.
[12:45:21.780] <TB1> INFO: Expecting 41600 events.
[12:45:25.277] <TB1> INFO: 41600 events read in total (2906ms).
[12:45:25.278] <TB1> INFO: Test took 3763ms.
[12:45:25.568] <TB1> INFO: Expecting 2560 events.
[12:45:26.454] <TB1> INFO: 2560 events read in total (294ms).
[12:45:26.454] <TB1> INFO: Test took 1163ms.
[12:45:26.763] <TB1> INFO: Expecting 2560 events.
[12:45:27.657] <TB1> INFO: 2560 events read in total (302ms).
[12:45:27.658] <TB1> INFO: Test took 1204ms.
[12:45:27.965] <TB1> INFO: Expecting 2560 events.
[12:45:28.851] <TB1> INFO: 2560 events read in total (294ms).
[12:45:28.851] <TB1> INFO: Test took 1193ms.
[12:45:29.159] <TB1> INFO: Expecting 2560 events.
[12:45:30.047] <TB1> INFO: 2560 events read in total (297ms).
[12:45:30.047] <TB1> INFO: Test took 1196ms.
[12:45:30.354] <TB1> INFO: Expecting 2560 events.
[12:45:31.244] <TB1> INFO: 2560 events read in total (298ms).
[12:45:31.244] <TB1> INFO: Test took 1196ms.
[12:45:31.552] <TB1> INFO: Expecting 2560 events.
[12:45:32.440] <TB1> INFO: 2560 events read in total (296ms).
[12:45:32.441] <TB1> INFO: Test took 1196ms.
[12:45:32.748] <TB1> INFO: Expecting 2560 events.
[12:45:33.627] <TB1> INFO: 2560 events read in total (287ms).
[12:45:33.627] <TB1> INFO: Test took 1186ms.
[12:45:33.935] <TB1> INFO: Expecting 2560 events.
[12:45:34.818] <TB1> INFO: 2560 events read in total (292ms).
[12:45:34.818] <TB1> INFO: Test took 1191ms.
[12:45:35.126] <TB1> INFO: Expecting 2560 events.
[12:45:36.017] <TB1> INFO: 2560 events read in total (300ms).
[12:45:36.018] <TB1> INFO: Test took 1200ms.
[12:45:36.326] <TB1> INFO: Expecting 2560 events.
[12:45:37.209] <TB1> INFO: 2560 events read in total (292ms).
[12:45:37.209] <TB1> INFO: Test took 1190ms.
[12:45:37.517] <TB1> INFO: Expecting 2560 events.
[12:45:38.410] <TB1> INFO: 2560 events read in total (297ms).
[12:45:38.410] <TB1> INFO: Test took 1201ms.
[12:45:38.719] <TB1> INFO: Expecting 2560 events.
[12:45:39.607] <TB1> INFO: 2560 events read in total (296ms).
[12:45:39.608] <TB1> INFO: Test took 1197ms.
[12:45:39.916] <TB1> INFO: Expecting 2560 events.
[12:45:40.806] <TB1> INFO: 2560 events read in total (298ms).
[12:45:40.806] <TB1> INFO: Test took 1198ms.
[12:45:41.115] <TB1> INFO: Expecting 2560 events.
[12:45:41.000] <TB1> INFO: 2560 events read in total (293ms).
[12:45:41.000] <TB1> INFO: Test took 1193ms.
[12:45:42.307] <TB1> INFO: Expecting 2560 events.
[12:45:43.202] <TB1> INFO: 2560 events read in total (303ms).
[12:45:43.203] <TB1> INFO: Test took 1203ms.
[12:45:43.511] <TB1> INFO: Expecting 2560 events.
[12:45:44.403] <TB1> INFO: 2560 events read in total (301ms).
[12:45:44.403] <TB1> INFO: Test took 1200ms.
[12:45:44.406] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:45:44.712] <TB1> INFO: Expecting 655360 events.
[12:45:59.706] <TB1> INFO: 655360 events read in total (14402ms).
[12:45:59.723] <TB1> INFO: Expecting 655360 events.
[12:46:14.544] <TB1> INFO: 655360 events read in total (14418ms).
[12:46:14.559] <TB1> INFO: Expecting 655360 events.
[12:46:29.292] <TB1> INFO: 655360 events read in total (14330ms).
[12:46:29.313] <TB1> INFO: Expecting 655360 events.
[12:46:44.190] <TB1> INFO: 655360 events read in total (14474ms).
[12:46:44.214] <TB1> INFO: Expecting 655360 events.
[12:46:58.885] <TB1> INFO: 655360 events read in total (14267ms).
[12:46:58.924] <TB1> INFO: Expecting 655360 events.
[12:47:13.826] <TB1> INFO: 655360 events read in total (14499ms).
[12:47:13.860] <TB1> INFO: Expecting 655360 events.
[12:47:28.720] <TB1> INFO: 655360 events read in total (14456ms).
[12:47:28.757] <TB1> INFO: Expecting 655360 events.
[12:47:43.754] <TB1> INFO: 655360 events read in total (14594ms).
[12:47:43.808] <TB1> INFO: Expecting 655360 events.
[12:47:58.598] <TB1> INFO: 655360 events read in total (14387ms).
[12:47:58.648] <TB1> INFO: Expecting 655360 events.
[12:48:13.390] <TB1> INFO: 655360 events read in total (14339ms).
[12:48:13.457] <TB1> INFO: Expecting 655360 events.
[12:48:28.476] <TB1> INFO: 655360 events read in total (14616ms).
[12:48:28.550] <TB1> INFO: Expecting 655360 events.
[12:48:43.373] <TB1> INFO: 655360 events read in total (14420ms).
[12:48:43.432] <TB1> INFO: Expecting 655360 events.
[12:48:58.468] <TB1> INFO: 655360 events read in total (14633ms).
[12:48:58.551] <TB1> INFO: Expecting 655360 events.
[12:49:13.290] <TB1> INFO: 655360 events read in total (14335ms).
[12:49:13.495] <TB1> INFO: Expecting 655360 events.
[12:49:28.218] <TB1> INFO: 655360 events read in total (14320ms).
[12:49:28.325] <TB1> INFO: Expecting 655360 events.
[12:49:43.132] <TB1> INFO: 655360 events read in total (14404ms).
[12:49:43.228] <TB1> INFO: Test took 238822ms.
[12:49:43.322] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:49:43.580] <TB1> INFO: Expecting 655360 events.
[12:49:58.508] <TB1> INFO: 655360 events read in total (14336ms).
[12:49:58.520] <TB1> INFO: Expecting 655360 events.
[12:50:13.271] <TB1> INFO: 655360 events read in total (14348ms).
[12:50:13.288] <TB1> INFO: Expecting 655360 events.
[12:50:27.945] <TB1> INFO: 655360 events read in total (14254ms).
[12:50:27.965] <TB1> INFO: Expecting 655360 events.
[12:50:42.713] <TB1> INFO: 655360 events read in total (14345ms).
[12:50:42.739] <TB1> INFO: Expecting 655360 events.
[12:50:57.580] <TB1> INFO: 655360 events read in total (14438ms).
[12:50:57.610] <TB1> INFO: Expecting 655360 events.
[12:51:12.249] <TB1> INFO: 655360 events read in total (14236ms).
[12:51:12.291] <TB1> INFO: Expecting 655360 events.
[12:51:27.128] <TB1> INFO: 655360 events read in total (14434ms).
[12:51:27.176] <TB1> INFO: Expecting 655360 events.
[12:51:41.968] <TB1> INFO: 655360 events read in total (14389ms).
[12:51:42.012] <TB1> INFO: Expecting 655360 events.
[12:51:56.758] <TB1> INFO: 655360 events read in total (14343ms).
[12:51:56.805] <TB1> INFO: Expecting 655360 events.
[12:52:11.691] <TB1> INFO: 655360 events read in total (14483ms).
[12:52:11.751] <TB1> INFO: Expecting 655360 events.
[12:52:26.125] <TB1> INFO: 655360 events read in total (13971ms).
[12:52:26.180] <TB1> INFO: Expecting 655360 events.
[12:52:40.880] <TB1> INFO: 655360 events read in total (14296ms).
[12:52:40.939] <TB1> INFO: Expecting 655360 events.
[12:52:55.577] <TB1> INFO: 655360 events read in total (14235ms).
[12:52:55.640] <TB1> INFO: Expecting 655360 events.
[12:53:10.089] <TB1> INFO: 655360 events read in total (14045ms).
[12:53:10.216] <TB1> INFO: Expecting 655360 events.
[12:53:24.842] <TB1> INFO: 655360 events read in total (14223ms).
[12:53:24.968] <TB1> INFO: Expecting 655360 events.
[12:53:39.564] <TB1> INFO: 655360 events read in total (14193ms).
[12:53:39.685] <TB1> INFO: Test took 236363ms.
[12:53:39.896] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:39.902] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:39.908] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:39.913] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:39.920] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:39.925] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:39.931] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:53:39.937] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:53:39.943] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[12:53:39.949] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[12:53:39.955] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[12:53:39.962] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[12:53:39.968] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[12:53:39.975] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[12:53:39.980] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:39.986] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:39.994] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:53:39.002] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:53:40.010] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[12:53:40.017] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[12:53:40.025] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[12:53:40.033] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[12:53:40.042] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:40.051] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:40.059] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:40.067] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:53:40.075] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:53:40.083] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:40.091] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:40.099] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:40.108] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:53:40.116] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[12:53:40.124] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[12:53:40.131] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[12:53:40.139] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[12:53:40.145] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[12:53:40.152] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[12:53:40.157] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[12:53:40.163] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[12:53:40.169] <TB1> INFO: safety margin for low PH: adding 10, margin is now 30
[12:53:40.175] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:40.180] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[12:53:40.187] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[12:53:40.221] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C0.dat
[12:53:40.221] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C1.dat
[12:53:40.221] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C2.dat
[12:53:40.221] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C3.dat
[12:53:40.221] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C4.dat
[12:53:40.221] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C5.dat
[12:53:40.222] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C6.dat
[12:53:40.222] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C7.dat
[12:53:40.222] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C8.dat
[12:53:40.222] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C9.dat
[12:53:40.222] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C10.dat
[12:53:40.222] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C11.dat
[12:53:40.222] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C12.dat
[12:53:40.223] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C13.dat
[12:53:40.223] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C14.dat
[12:53:40.223] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//dacParameters35_C15.dat
[12:53:40.476] <TB1> INFO: Expecting 41600 events.
[12:53:43.663] <TB1> INFO: 41600 events read in total (2595ms).
[12:53:43.664] <TB1> INFO: Test took 3437ms.
[12:53:44.122] <TB1> INFO: Expecting 41600 events.
[12:53:47.290] <TB1> INFO: 41600 events read in total (2576ms).
[12:53:47.291] <TB1> INFO: Test took 3413ms.
[12:53:47.763] <TB1> INFO: Expecting 41600 events.
[12:53:50.870] <TB1> INFO: 41600 events read in total (2516ms).
[12:53:50.871] <TB1> INFO: Test took 3367ms.
[12:53:51.086] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:51.175] <TB1> INFO: Expecting 2560 events.
[12:53:52.063] <TB1> INFO: 2560 events read in total (296ms).
[12:53:52.063] <TB1> INFO: Test took 977ms.
[12:53:52.065] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:52.372] <TB1> INFO: Expecting 2560 events.
[12:53:53.260] <TB1> INFO: 2560 events read in total (296ms).
[12:53:53.261] <TB1> INFO: Test took 1196ms.
[12:53:53.264] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:53.569] <TB1> INFO: Expecting 2560 events.
[12:53:54.451] <TB1> INFO: 2560 events read in total (291ms).
[12:53:54.452] <TB1> INFO: Test took 1188ms.
[12:53:54.454] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:54.759] <TB1> INFO: Expecting 2560 events.
[12:53:55.653] <TB1> INFO: 2560 events read in total (302ms).
[12:53:55.654] <TB1> INFO: Test took 1200ms.
[12:53:55.656] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:55.961] <TB1> INFO: Expecting 2560 events.
[12:53:56.852] <TB1> INFO: 2560 events read in total (299ms).
[12:53:56.852] <TB1> INFO: Test took 1196ms.
[12:53:56.855] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:57.160] <TB1> INFO: Expecting 2560 events.
[12:53:58.054] <TB1> INFO: 2560 events read in total (302ms).
[12:53:58.055] <TB1> INFO: Test took 1200ms.
[12:53:58.058] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:58.364] <TB1> INFO: Expecting 2560 events.
[12:53:59.259] <TB1> INFO: 2560 events read in total (304ms).
[12:53:59.260] <TB1> INFO: Test took 1202ms.
[12:53:59.263] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:59.568] <TB1> INFO: Expecting 2560 events.
[12:54:00.461] <TB1> INFO: 2560 events read in total (301ms).
[12:54:00.461] <TB1> INFO: Test took 1198ms.
[12:54:00.464] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:00.769] <TB1> INFO: Expecting 2560 events.
[12:54:01.659] <TB1> INFO: 2560 events read in total (298ms).
[12:54:01.660] <TB1> INFO: Test took 1196ms.
[12:54:01.663] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:01.967] <TB1> INFO: Expecting 2560 events.
[12:54:02.856] <TB1> INFO: 2560 events read in total (297ms).
[12:54:02.856] <TB1> INFO: Test took 1193ms.
[12:54:02.858] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:03.164] <TB1> INFO: Expecting 2560 events.
[12:54:04.051] <TB1> INFO: 2560 events read in total (295ms).
[12:54:04.052] <TB1> INFO: Test took 1194ms.
[12:54:04.055] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:04.360] <TB1> INFO: Expecting 2560 events.
[12:54:05.248] <TB1> INFO: 2560 events read in total (296ms).
[12:54:05.248] <TB1> INFO: Test took 1193ms.
[12:54:05.252] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:05.555] <TB1> INFO: Expecting 2560 events.
[12:54:06.447] <TB1> INFO: 2560 events read in total (300ms).
[12:54:06.448] <TB1> INFO: Test took 1197ms.
[12:54:06.451] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:06.756] <TB1> INFO: Expecting 2560 events.
[12:54:07.638] <TB1> INFO: 2560 events read in total (290ms).
[12:54:07.638] <TB1> INFO: Test took 1187ms.
[12:54:07.642] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:07.947] <TB1> INFO: Expecting 2560 events.
[12:54:08.830] <TB1> INFO: 2560 events read in total (291ms).
[12:54:08.830] <TB1> INFO: Test took 1188ms.
[12:54:08.832] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:09.138] <TB1> INFO: Expecting 2560 events.
[12:54:10.023] <TB1> INFO: 2560 events read in total (293ms).
[12:54:10.023] <TB1> INFO: Test took 1191ms.
[12:54:10.026] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:10.332] <TB1> INFO: Expecting 2560 events.
[12:54:11.213] <TB1> INFO: 2560 events read in total (289ms).
[12:54:11.213] <TB1> INFO: Test took 1187ms.
[12:54:11.216] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:11.520] <TB1> INFO: Expecting 2560 events.
[12:54:12.411] <TB1> INFO: 2560 events read in total (299ms).
[12:54:12.412] <TB1> INFO: Test took 1196ms.
[12:54:12.416] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:12.720] <TB1> INFO: Expecting 2560 events.
[12:54:13.611] <TB1> INFO: 2560 events read in total (299ms).
[12:54:13.611] <TB1> INFO: Test took 1195ms.
[12:54:13.615] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:13.919] <TB1> INFO: Expecting 2560 events.
[12:54:14.811] <TB1> INFO: 2560 events read in total (300ms).
[12:54:14.812] <TB1> INFO: Test took 1197ms.
[12:54:14.814] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:15.120] <TB1> INFO: Expecting 2560 events.
[12:54:16.014] <TB1> INFO: 2560 events read in total (302ms).
[12:54:16.014] <TB1> INFO: Test took 1200ms.
[12:54:16.017] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:16.322] <TB1> INFO: Expecting 2560 events.
[12:54:17.212] <TB1> INFO: 2560 events read in total (298ms).
[12:54:17.212] <TB1> INFO: Test took 1195ms.
[12:54:17.215] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:17.520] <TB1> INFO: Expecting 2560 events.
[12:54:18.406] <TB1> INFO: 2560 events read in total (294ms).
[12:54:18.406] <TB1> INFO: Test took 1191ms.
[12:54:18.409] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:18.715] <TB1> INFO: Expecting 2560 events.
[12:54:19.599] <TB1> INFO: 2560 events read in total (293ms).
[12:54:19.599] <TB1> INFO: Test took 1191ms.
[12:54:19.602] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:19.908] <TB1> INFO: Expecting 2560 events.
[12:54:20.802] <TB1> INFO: 2560 events read in total (302ms).
[12:54:20.803] <TB1> INFO: Test took 1202ms.
[12:54:20.806] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:21.110] <TB1> INFO: Expecting 2560 events.
[12:54:21.002] <TB1> INFO: 2560 events read in total (300ms).
[12:54:21.002] <TB1> INFO: Test took 1196ms.
[12:54:22.006] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:22.311] <TB1> INFO: Expecting 2560 events.
[12:54:23.201] <TB1> INFO: 2560 events read in total (298ms).
[12:54:23.202] <TB1> INFO: Test took 1196ms.
[12:54:23.205] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:23.511] <TB1> INFO: Expecting 2560 events.
[12:54:24.398] <TB1> INFO: 2560 events read in total (295ms).
[12:54:24.399] <TB1> INFO: Test took 1194ms.
[12:54:24.402] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:24.707] <TB1> INFO: Expecting 2560 events.
[12:54:25.596] <TB1> INFO: 2560 events read in total (297ms).
[12:54:25.597] <TB1> INFO: Test took 1195ms.
[12:54:25.599] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:25.904] <TB1> INFO: Expecting 2560 events.
[12:54:26.790] <TB1> INFO: 2560 events read in total (294ms).
[12:54:26.791] <TB1> INFO: Test took 1192ms.
[12:54:26.794] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:27.098] <TB1> INFO: Expecting 2560 events.
[12:54:27.992] <TB1> INFO: 2560 events read in total (302ms).
[12:54:27.993] <TB1> INFO: Test took 1200ms.
[12:54:27.997] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:54:28.299] <TB1> INFO: Expecting 2560 events.
[12:54:29.186] <TB1> INFO: 2560 events read in total (295ms).
[12:54:29.187] <TB1> INFO: Test took 1190ms.
[12:54:29.663] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 663 seconds
[12:54:29.663] <TB1> INFO: PH scale (per ROC): 57 59 52 57 59 48 46 49 53 58 61 60 65 41 51 47
[12:54:29.663] <TB1> INFO: PH offset (per ROC): 127 114 99 127 122 96 95 112 134 123 134 127 133 80 103 111
[12:54:29.670] <TB1> INFO: Decoding statistics:
[12:54:29.670] <TB1> INFO: General information:
[12:54:29.670] <TB1> INFO: 16bit words read: 127882
[12:54:29.670] <TB1> INFO: valid events total: 20480
[12:54:29.670] <TB1> INFO: empty events: 17979
[12:54:29.670] <TB1> INFO: valid events with pixels: 2501
[12:54:29.670] <TB1> INFO: valid pixel hits: 2501
[12:54:29.670] <TB1> INFO: Event errors: 0
[12:54:29.670] <TB1> INFO: start marker: 0
[12:54:29.670] <TB1> INFO: stop marker: 0
[12:54:29.670] <TB1> INFO: overflow: 0
[12:54:29.670] <TB1> INFO: invalid 5bit words: 0
[12:54:29.670] <TB1> INFO: invalid XOR eye diagram: 0
[12:54:29.670] <TB1> INFO: frame (failed synchr.): 0
[12:54:29.670] <TB1> INFO: idle data (no TBM trl): 0
[12:54:29.670] <TB1> INFO: no data (only TBM hdr): 0
[12:54:29.670] <TB1> INFO: TBM errors: 0
[12:54:29.670] <TB1> INFO: flawed TBM headers: 0
[12:54:29.670] <TB1> INFO: flawed TBM trailers: 0
[12:54:29.670] <TB1> INFO: event ID mismatches: 0
[12:54:29.670] <TB1> INFO: ROC errors: 0
[12:54:29.670] <TB1> INFO: missing ROC header(s): 0
[12:54:29.670] <TB1> INFO: misplaced readback start: 0
[12:54:29.670] <TB1> INFO: Pixel decoding errors: 0
[12:54:29.670] <TB1> INFO: pixel data incomplete: 0
[12:54:29.670] <TB1> INFO: pixel address: 0
[12:54:29.670] <TB1> INFO: pulse height fill bit: 0
[12:54:29.670] <TB1> INFO: buffer corruption: 0
[12:54:29.848] <TB1> INFO: ######################################################################
[12:54:29.848] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[12:54:29.848] <TB1> INFO: ######################################################################
[12:54:29.863] <TB1> INFO: scanning low vcal = 10
[12:54:30.104] <TB1> INFO: Expecting 41600 events.
[12:54:33.677] <TB1> INFO: 41600 events read in total (2981ms).
[12:54:33.677] <TB1> INFO: Test took 3814ms.
[12:54:33.679] <TB1> INFO: scanning low vcal = 20
[12:54:33.974] <TB1> INFO: Expecting 41600 events.
[12:54:37.544] <TB1> INFO: 41600 events read in total (2978ms).
[12:54:37.545] <TB1> INFO: Test took 3866ms.
[12:54:37.546] <TB1> INFO: scanning low vcal = 30
[12:54:37.843] <TB1> INFO: Expecting 41600 events.
[12:54:41.512] <TB1> INFO: 41600 events read in total (3077ms).
[12:54:41.513] <TB1> INFO: Test took 3967ms.
[12:54:41.515] <TB1> INFO: scanning low vcal = 40
[12:54:41.793] <TB1> INFO: Expecting 41600 events.
[12:54:45.823] <TB1> INFO: 41600 events read in total (3438ms).
[12:54:45.824] <TB1> INFO: Test took 4308ms.
[12:54:45.827] <TB1> INFO: scanning low vcal = 50
[12:54:46.105] <TB1> INFO: Expecting 41600 events.
[12:54:50.148] <TB1> INFO: 41600 events read in total (3452ms).
[12:54:50.149] <TB1> INFO: Test took 4321ms.
[12:54:50.152] <TB1> INFO: scanning low vcal = 60
[12:54:50.428] <TB1> INFO: Expecting 41600 events.
[12:54:54.389] <TB1> INFO: 41600 events read in total (3369ms).
[12:54:54.390] <TB1> INFO: Test took 4238ms.
[12:54:54.393] <TB1> INFO: scanning low vcal = 70
[12:54:54.670] <TB1> INFO: Expecting 41600 events.
[12:54:58.745] <TB1> INFO: 41600 events read in total (3483ms).
[12:54:58.746] <TB1> INFO: Test took 4353ms.
[12:54:58.749] <TB1> INFO: scanning low vcal = 80
[12:54:59.026] <TB1> INFO: Expecting 41600 events.
[12:55:02.001] <TB1> INFO: 41600 events read in total (3384ms).
[12:55:02.002] <TB1> INFO: Test took 4253ms.
[12:55:03.005] <TB1> INFO: scanning low vcal = 90
[12:55:03.282] <TB1> INFO: Expecting 41600 events.
[12:55:07.264] <TB1> INFO: 41600 events read in total (3390ms).
[12:55:07.264] <TB1> INFO: Test took 4259ms.
[12:55:07.268] <TB1> INFO: scanning low vcal = 100
[12:55:07.544] <TB1> INFO: Expecting 41600 events.
[12:55:11.562] <TB1> INFO: 41600 events read in total (3426ms).
[12:55:11.562] <TB1> INFO: Test took 4294ms.
[12:55:11.565] <TB1> INFO: scanning low vcal = 110
[12:55:11.843] <TB1> INFO: Expecting 41600 events.
[12:55:15.877] <TB1> INFO: 41600 events read in total (3442ms).
[12:55:15.878] <TB1> INFO: Test took 4313ms.
[12:55:15.881] <TB1> INFO: scanning low vcal = 120
[12:55:16.159] <TB1> INFO: Expecting 41600 events.
[12:55:20.154] <TB1> INFO: 41600 events read in total (3404ms).
[12:55:20.155] <TB1> INFO: Test took 4274ms.
[12:55:20.158] <TB1> INFO: scanning low vcal = 130
[12:55:20.435] <TB1> INFO: Expecting 41600 events.
[12:55:24.476] <TB1> INFO: 41600 events read in total (3449ms).
[12:55:24.477] <TB1> INFO: Test took 4319ms.
[12:55:24.481] <TB1> INFO: scanning low vcal = 140
[12:55:24.758] <TB1> INFO: Expecting 41600 events.
[12:55:28.789] <TB1> INFO: 41600 events read in total (3439ms).
[12:55:28.790] <TB1> INFO: Test took 4309ms.
[12:55:28.793] <TB1> INFO: scanning low vcal = 150
[12:55:29.072] <TB1> INFO: Expecting 41600 events.
[12:55:33.126] <TB1> INFO: 41600 events read in total (3462ms).
[12:55:33.127] <TB1> INFO: Test took 4334ms.
[12:55:33.130] <TB1> INFO: scanning low vcal = 160
[12:55:33.407] <TB1> INFO: Expecting 41600 events.
[12:55:37.407] <TB1> INFO: 41600 events read in total (3408ms).
[12:55:37.408] <TB1> INFO: Test took 4278ms.
[12:55:37.411] <TB1> INFO: scanning low vcal = 170
[12:55:37.688] <TB1> INFO: Expecting 41600 events.
[12:55:41.755] <TB1> INFO: 41600 events read in total (3475ms).
[12:55:41.756] <TB1> INFO: Test took 4345ms.
[12:55:41.761] <TB1> INFO: scanning low vcal = 180
[12:55:42.036] <TB1> INFO: Expecting 41600 events.
[12:55:46.089] <TB1> INFO: 41600 events read in total (3461ms).
[12:55:46.090] <TB1> INFO: Test took 4328ms.
[12:55:46.093] <TB1> INFO: scanning low vcal = 190
[12:55:46.377] <TB1> INFO: Expecting 41600 events.
[12:55:50.489] <TB1> INFO: 41600 events read in total (3520ms).
[12:55:50.489] <TB1> INFO: Test took 4396ms.
[12:55:50.492] <TB1> INFO: scanning low vcal = 200
[12:55:50.770] <TB1> INFO: Expecting 41600 events.
[12:55:54.821] <TB1> INFO: 41600 events read in total (3459ms).
[12:55:54.822] <TB1> INFO: Test took 4329ms.
[12:55:54.825] <TB1> INFO: scanning low vcal = 210
[12:55:55.103] <TB1> INFO: Expecting 41600 events.
[12:55:59.143] <TB1> INFO: 41600 events read in total (3448ms).
[12:55:59.144] <TB1> INFO: Test took 4318ms.
[12:55:59.147] <TB1> INFO: scanning low vcal = 220
[12:55:59.425] <TB1> INFO: Expecting 41600 events.
[12:56:03.463] <TB1> INFO: 41600 events read in total (3446ms).
[12:56:03.463] <TB1> INFO: Test took 4317ms.
[12:56:03.467] <TB1> INFO: scanning low vcal = 230
[12:56:03.747] <TB1> INFO: Expecting 41600 events.
[12:56:07.789] <TB1> INFO: 41600 events read in total (3451ms).
[12:56:07.789] <TB1> INFO: Test took 4322ms.
[12:56:07.793] <TB1> INFO: scanning low vcal = 240
[12:56:08.070] <TB1> INFO: Expecting 41600 events.
[12:56:12.116] <TB1> INFO: 41600 events read in total (3454ms).
[12:56:12.116] <TB1> INFO: Test took 4323ms.
[12:56:12.120] <TB1> INFO: scanning low vcal = 250
[12:56:12.397] <TB1> INFO: Expecting 41600 events.
[12:56:16.423] <TB1> INFO: 41600 events read in total (3434ms).
[12:56:16.424] <TB1> INFO: Test took 4304ms.
[12:56:16.428] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[12:56:16.704] <TB1> INFO: Expecting 41600 events.
[12:56:20.691] <TB1> INFO: 41600 events read in total (3396ms).
[12:56:20.692] <TB1> INFO: Test took 4264ms.
[12:56:20.695] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[12:56:20.972] <TB1> INFO: Expecting 41600 events.
[12:56:24.988] <TB1> INFO: 41600 events read in total (3424ms).
[12:56:24.988] <TB1> INFO: Test took 4293ms.
[12:56:24.992] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[12:56:25.268] <TB1> INFO: Expecting 41600 events.
[12:56:29.277] <TB1> INFO: 41600 events read in total (3417ms).
[12:56:29.278] <TB1> INFO: Test took 4286ms.
[12:56:29.281] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[12:56:29.559] <TB1> INFO: Expecting 41600 events.
[12:56:33.556] <TB1> INFO: 41600 events read in total (3406ms).
[12:56:33.556] <TB1> INFO: Test took 4274ms.
[12:56:33.559] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[12:56:33.836] <TB1> INFO: Expecting 41600 events.
[12:56:37.842] <TB1> INFO: 41600 events read in total (3414ms).
[12:56:37.843] <TB1> INFO: Test took 4284ms.
[12:56:38.269] <TB1> INFO: PixTestGainPedestal::measure() done
[12:57:11.412] <TB1> INFO: PixTestGainPedestal::fit() done
[12:57:11.412] <TB1> INFO: non-linearity mean: 0.984 0.979 0.943 0.981 0.980 0.930 0.947 0.960 0.979 0.980 0.978 0.982 0.981 0.972 0.964 0.927
[12:57:11.412] <TB1> INFO: non-linearity RMS: 0.004 0.003 0.056 0.005 0.005 0.116 0.058 0.029 0.005 0.004 0.005 0.003 0.004 0.173 0.037 0.093
[12:57:11.412] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[12:57:11.432] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[12:57:11.451] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[12:57:11.471] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[12:57:11.490] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[12:57:11.509] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[12:57:11.528] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[12:57:11.547] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[12:57:11.566] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[12:57:11.585] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[12:57:11.602] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[12:57:11.615] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[12:57:11.628] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[12:57:11.641] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[12:57:11.654] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[12:57:11.667] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1045_FullQualification_2016-10-22_10h41m_1477125660//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[12:57:11.680] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 161 seconds
[12:57:11.680] <TB1> INFO: Decoding statistics:
[12:57:11.680] <TB1> INFO: General information:
[12:57:11.680] <TB1> INFO: 16bit words read: 3327938
[12:57:11.680] <TB1> INFO: valid events total: 332800
[12:57:11.680] <TB1> INFO: empty events: 0
[12:57:11.680] <TB1> INFO: valid events with pixels: 332800
[12:57:11.680] <TB1> INFO: valid pixel hits: 665569
[12:57:11.680] <TB1> INFO: Event errors: 0
[12:57:11.680] <TB1> INFO: start marker: 0
[12:57:11.680] <TB1> INFO: stop marker: 0
[12:57:11.680] <TB1> INFO: overflow: 0
[12:57:11.680] <TB1> INFO: invalid 5bit words: 0
[12:57:11.680] <TB1> INFO: invalid XOR eye diagram: 0
[12:57:11.680] <TB1> INFO: frame (failed synchr.): 0
[12:57:11.680] <TB1> INFO: idle data (no TBM trl): 0
[12:57:11.680] <TB1> INFO: no data (only TBM hdr): 0
[12:57:11.680] <TB1> INFO: TBM errors: 0
[12:57:11.680] <TB1> INFO: flawed TBM headers: 0
[12:57:11.680] <TB1> INFO: flawed TBM trailers: 0
[12:57:11.680] <TB1> INFO: event ID mismatches: 0
[12:57:11.680] <TB1> INFO: ROC errors: 0
[12:57:11.680] <TB1> INFO: missing ROC header(s): 0
[12:57:11.680] <TB1> INFO: misplaced readback start: 0
[12:57:11.680] <TB1> INFO: Pixel decoding errors: 0
[12:57:11.680] <TB1> INFO: pixel data incomplete: 0
[12:57:11.681] <TB1> INFO: pixel address: 0
[12:57:11.681] <TB1> INFO: pulse height fill bit: 0
[12:57:11.681] <TB1> INFO: buffer corruption: 0
[12:57:11.696] <TB1> INFO: Decoding statistics:
[12:57:11.696] <TB1> INFO: General information:
[12:57:11.696] <TB1> INFO: 16bit words read: 3457356
[12:57:11.696] <TB1> INFO: valid events total: 353536
[12:57:11.696] <TB1> INFO: empty events: 18235
[12:57:11.696] <TB1> INFO: valid events with pixels: 335301
[12:57:11.697] <TB1> INFO: valid pixel hits: 668070
[12:57:11.697] <TB1> INFO: Event errors: 0
[12:57:11.697] <TB1> INFO: start marker: 0
[12:57:11.697] <TB1> INFO: stop marker: 0
[12:57:11.697] <TB1> INFO: overflow: 0
[12:57:11.697] <TB1> INFO: invalid 5bit words: 0
[12:57:11.697] <TB1> INFO: invalid XOR eye diagram: 0
[12:57:11.697] <TB1> INFO: frame (failed synchr.): 0
[12:57:11.697] <TB1> INFO: idle data (no TBM trl): 0
[12:57:11.697] <TB1> INFO: no data (only TBM hdr): 0
[12:57:11.697] <TB1> INFO: TBM errors: 0
[12:57:11.697] <TB1> INFO: flawed TBM headers: 0
[12:57:11.697] <TB1> INFO: flawed TBM trailers: 0
[12:57:11.697] <TB1> INFO: event ID mismatches: 0
[12:57:11.697] <TB1> INFO: ROC errors: 0
[12:57:11.697] <TB1> INFO: missing ROC header(s): 0
[12:57:11.697] <TB1> INFO: misplaced readback start: 0
[12:57:11.697] <TB1> INFO: Pixel decoding errors: 0
[12:57:11.697] <TB1> INFO: pixel data incomplete: 0
[12:57:11.697] <TB1> INFO: pixel address: 0
[12:57:11.697] <TB1> INFO: pulse height fill bit: 0
[12:57:11.697] <TB1> INFO: buffer corruption: 0
[12:57:11.697] <TB1> INFO: enter test to run
[12:57:11.697] <TB1> INFO: test: exit no parameter change
[12:57:11.821] <TB1> QUIET: Connection to board 154 closed.
[12:57:11.822] <TB1> INFO: pXar: this is the end, my friend