[11:45:50.035] <TB2> INFO: *** Welcome to pxar ***
[11:45:50.035] <TB2> INFO: *** Today: 2016/11/14
[11:45:50.043] <TB2> INFO: *** Version: c8ba-dirty
[11:45:50.043] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C15.dat
[11:45:50.043] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//tbmParameters_C1b.dat
[11:45:50.043] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//defaultMaskFile.dat
[11:45:50.043] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters_C15.dat
[11:45:50.105] <TB2> INFO: clk: 4
[11:45:50.105] <TB2> INFO: ctr: 4
[11:45:50.105] <TB2> INFO: sda: 19
[11:45:50.105] <TB2> INFO: tin: 9
[11:45:50.105] <TB2> INFO: level: 15
[11:45:50.105] <TB2> INFO: triggerdelay: 0
[11:45:50.105] <TB2> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[11:45:50.105] <TB2> INFO: Log level: INFO
[11:45:50.114] <TB2> INFO: Found DTB DTB_WWXUD2
[11:45:50.121] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[11:45:50.123] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[11:45:50.125] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[11:45:51.622] <TB2> INFO: DUT info:
[11:45:51.622] <TB2> INFO: The DUT currently contains the following objects:
[11:45:51.622] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[11:45:51.622] <TB2> INFO: TBM Core alpha (0): 7 registers set
[11:45:51.622] <TB2> INFO: TBM Core beta (1): 7 registers set
[11:45:51.622] <TB2> INFO: TBM Core alpha (2): 7 registers set
[11:45:51.622] <TB2> INFO: TBM Core beta (3): 7 registers set
[11:45:51.622] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:45:51.622] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:51.622] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:51.622] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:51.622] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:51.622] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:51.622] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:51.622] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:51.623] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:51.623] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:51.623] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:51.623] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:51.623] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:51.623] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:51.623] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:51.623] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:51.623] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:52.023] <TB2> INFO: enter 'restricted' command line mode
[11:45:52.024] <TB2> INFO: enter test to run
[11:45:52.024] <TB2> INFO: test: pretest no parameter change
[11:45:52.024] <TB2> INFO: running: pretest
[11:45:52.030] <TB2> INFO: ######################################################################
[11:45:52.030] <TB2> INFO: PixTestPretest::doTest()
[11:45:52.030] <TB2> INFO: ######################################################################
[11:45:52.031] <TB2> INFO: ----------------------------------------------------------------------
[11:45:52.031] <TB2> INFO: PixTestPretest::programROC()
[11:45:52.032] <TB2> INFO: ----------------------------------------------------------------------
[11:46:10.048] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:46:10.048] <TB2> INFO: IA differences per ROC: 19.3 20.1 20.1 18.5 18.5 19.3 18.5 20.9 17.7 18.5 20.1 17.7 20.9 18.5 19.3 20.9
[11:46:10.114] <TB2> INFO: ----------------------------------------------------------------------
[11:46:10.114] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:46:10.114] <TB2> INFO: ----------------------------------------------------------------------
[11:46:31.419] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 390.7 mA = 24.4187 mA/ROC
[11:46:31.419] <TB2> INFO: i(loss) [mA/ROC]: 19.3 18.5 19.3 18.5 20.1 19.3 19.3 20.1 19.3 18.5 19.3 19.3 19.3 18.5 19.3 19.3
[11:46:31.450] <TB2> INFO: ----------------------------------------------------------------------
[11:46:31.450] <TB2> INFO: PixTestPretest::findTiming()
[11:46:31.450] <TB2> INFO: ----------------------------------------------------------------------
[11:46:31.450] <TB2> INFO: PixTestCmd::init()

[11:47:03.696] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[11:47:03.696] <TB2> INFO: (success/tries = 100/100), width = 4
[11:47:05.199] <TB2> INFO: ----------------------------------------------------------------------
[11:47:05.199] <TB2> INFO: PixTestPretest::findWorkingPixel()
[11:47:05.199] <TB2> INFO: ----------------------------------------------------------------------
[11:47:05.293] <TB2> INFO: Expecting 231680 events.
[11:47:15.056] <TB2> INFO: 231680 events read in total (9171ms).
[11:47:15.064] <TB2> INFO: Test took 9861ms.
[11:47:15.313] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:47:15.345] <TB2> INFO: ----------------------------------------------------------------------
[11:47:15.345] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[11:47:15.345] <TB2> INFO: ----------------------------------------------------------------------
[11:47:15.438] <TB2> INFO: Expecting 231680 events.
[11:47:25.380] <TB2> INFO: 231680 events read in total (9350ms).
[11:47:25.387] <TB2> INFO: Test took 10037ms.
[11:47:25.659] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[11:47:25.659] <TB2> INFO: CalDel: 83 83 110 104 94 110 103 103 120 95 112 111 99 78 97 113
[11:47:25.659] <TB2> INFO: VthrComp: 51 53 57 52 51 51 52 53 51 51 51 51 51 51 54 53
[11:47:25.663] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C0.dat
[11:47:25.663] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C1.dat
[11:47:25.663] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C2.dat
[11:47:25.663] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C3.dat
[11:47:25.664] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C4.dat
[11:47:25.664] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C5.dat
[11:47:25.664] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C6.dat
[11:47:25.664] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C7.dat
[11:47:25.664] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C8.dat
[11:47:25.664] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C9.dat
[11:47:25.665] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C10.dat
[11:47:25.665] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C11.dat
[11:47:25.665] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C12.dat
[11:47:25.665] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C13.dat
[11:47:25.665] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C14.dat
[11:47:25.665] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C15.dat
[11:47:25.665] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//tbmParameters_C0a.dat
[11:47:25.666] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//tbmParameters_C0b.dat
[11:47:25.666] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//tbmParameters_C1a.dat
[11:47:25.666] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//tbmParameters_C1b.dat
[11:47:25.666] <TB2> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[11:47:25.720] <TB2> INFO: enter test to run
[11:47:25.720] <TB2> INFO: test: FullTest no parameter change
[11:47:25.720] <TB2> INFO: running: fulltest
[11:47:25.720] <TB2> INFO: ######################################################################
[11:47:25.720] <TB2> INFO: PixTestFullTest::doTest()
[11:47:25.720] <TB2> INFO: ######################################################################
[11:47:25.722] <TB2> INFO: ######################################################################
[11:47:25.722] <TB2> INFO: PixTestAlive::doTest()
[11:47:25.722] <TB2> INFO: ######################################################################
[11:47:25.724] <TB2> INFO: ----------------------------------------------------------------------
[11:47:25.724] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:47:25.724] <TB2> INFO: ----------------------------------------------------------------------
[11:47:25.963] <TB2> INFO: Expecting 41600 events.
[11:47:29.592] <TB2> INFO: 41600 events read in total (3037ms).
[11:47:29.593] <TB2> INFO: Test took 3868ms.
[11:47:29.822] <TB2> INFO: PixTestAlive::aliveTest() done
[11:47:29.822] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0
[11:47:29.823] <TB2> INFO: ----------------------------------------------------------------------
[11:47:29.824] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:47:29.824] <TB2> INFO: ----------------------------------------------------------------------
[11:47:30.064] <TB2> INFO: Expecting 41600 events.
[11:47:33.056] <TB2> INFO: 41600 events read in total (2400ms).
[11:47:33.056] <TB2> INFO: Test took 3230ms.
[11:47:33.057] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:47:33.298] <TB2> INFO: PixTestAlive::maskTest() done
[11:47:33.298] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:47:33.302] <TB2> INFO: ----------------------------------------------------------------------
[11:47:33.303] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:47:33.303] <TB2> INFO: ----------------------------------------------------------------------
[11:47:33.546] <TB2> INFO: Expecting 41600 events.
[11:47:37.183] <TB2> INFO: 41600 events read in total (3046ms).
[11:47:37.184] <TB2> INFO: Test took 3879ms.
[11:47:37.420] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[11:47:37.420] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:47:37.420] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:47:37.420] <TB2> INFO: Decoding statistics:
[11:47:37.420] <TB2> INFO: General information:
[11:47:37.420] <TB2> INFO: 16bit words read: 0
[11:47:37.420] <TB2> INFO: valid events total: 0
[11:47:37.420] <TB2> INFO: empty events: 0
[11:47:37.420] <TB2> INFO: valid events with pixels: 0
[11:47:37.420] <TB2> INFO: valid pixel hits: 0
[11:47:37.420] <TB2> INFO: Event errors: 0
[11:47:37.420] <TB2> INFO: start marker: 0
[11:47:37.420] <TB2> INFO: stop marker: 0
[11:47:37.420] <TB2> INFO: overflow: 0
[11:47:37.420] <TB2> INFO: invalid 5bit words: 0
[11:47:37.420] <TB2> INFO: invalid XOR eye diagram: 0
[11:47:37.420] <TB2> INFO: frame (failed synchr.): 0
[11:47:37.421] <TB2> INFO: idle data (no TBM trl): 0
[11:47:37.421] <TB2> INFO: no data (only TBM hdr): 0
[11:47:37.421] <TB2> INFO: TBM errors: 0
[11:47:37.421] <TB2> INFO: flawed TBM headers: 0
[11:47:37.421] <TB2> INFO: flawed TBM trailers: 0
[11:47:37.421] <TB2> INFO: event ID mismatches: 0
[11:47:37.421] <TB2> INFO: ROC errors: 0
[11:47:37.421] <TB2> INFO: missing ROC header(s): 0
[11:47:37.421] <TB2> INFO: misplaced readback start: 0
[11:47:37.421] <TB2> INFO: Pixel decoding errors: 0
[11:47:37.421] <TB2> INFO: pixel data incomplete: 0
[11:47:37.421] <TB2> INFO: pixel address: 0
[11:47:37.421] <TB2> INFO: pulse height fill bit: 0
[11:47:37.421] <TB2> INFO: buffer corruption: 0
[11:47:37.429] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C15.dat
[11:47:37.430] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr_C15.dat

[11:47:37.430] <TB2> INFO: ######################################################################
[11:47:37.430] <TB2> INFO: PixTestReadback::doTest()
[11:47:37.430] <TB2> INFO: ######################################################################
[11:47:37.430] <TB2> INFO: ----------------------------------------------------------------------
[11:47:37.430] <TB2> INFO: PixTestReadback::CalibrateVd()
[11:47:37.430] <TB2> INFO: ----------------------------------------------------------------------
[11:47:47.407] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C0.dat
[11:47:47.407] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C1.dat
[11:47:47.407] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C2.dat
[11:47:47.407] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C3.dat
[11:47:47.407] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C4.dat
[11:47:47.407] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C5.dat
[11:47:47.407] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C6.dat
[11:47:47.407] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C7.dat
[11:47:47.407] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C8.dat
[11:47:47.407] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C9.dat
[11:47:47.407] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C10.dat
[11:47:47.407] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C11.dat
[11:47:47.408] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C12.dat
[11:47:47.408] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C13.dat
[11:47:47.408] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C14.dat
[11:47:47.408] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C15.dat
[11:47:47.438] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:47:47.438] <TB2> INFO: ----------------------------------------------------------------------
[11:47:47.438] <TB2> INFO: PixTestReadback::CalibrateVa()
[11:47:47.438] <TB2> INFO: ----------------------------------------------------------------------
[11:47:57.368] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C0.dat
[11:47:57.368] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C1.dat
[11:47:57.368] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C2.dat
[11:47:57.368] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C3.dat
[11:47:57.368] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C4.dat
[11:47:57.368] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C5.dat
[11:47:57.368] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C6.dat
[11:47:57.368] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C7.dat
[11:47:57.368] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C8.dat
[11:47:57.368] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C9.dat
[11:47:57.368] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C10.dat
[11:47:57.368] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C11.dat
[11:47:57.368] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C12.dat
[11:47:57.368] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C13.dat
[11:47:57.369] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C14.dat
[11:47:57.369] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C15.dat
[11:47:57.399] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:47:57.399] <TB2> INFO: ----------------------------------------------------------------------
[11:47:57.399] <TB2> INFO: PixTestReadback::readbackVbg()
[11:47:57.399] <TB2> INFO: ----------------------------------------------------------------------
[11:48:05.079] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:48:05.079] <TB2> INFO: ----------------------------------------------------------------------
[11:48:05.079] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[11:48:05.079] <TB2> INFO: ----------------------------------------------------------------------
[11:48:05.079] <TB2> INFO: Vbg will be calibrated using Vd calibration
[11:48:05.079] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 153.8calibrated Vbg = 1.20081 :::*/*/*/*/
[11:48:05.079] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 151calibrated Vbg = 1.19626 :::*/*/*/*/
[11:48:05.079] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 161.5calibrated Vbg = 1.19686 :::*/*/*/*/
[11:48:05.079] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 150.5calibrated Vbg = 1.1992 :::*/*/*/*/
[11:48:05.079] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 158.9calibrated Vbg = 1.19994 :::*/*/*/*/
[11:48:05.079] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 154.1calibrated Vbg = 1.21154 :::*/*/*/*/
[11:48:05.079] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 158.3calibrated Vbg = 1.20645 :::*/*/*/*/
[11:48:05.079] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 164.3calibrated Vbg = 1.20927 :::*/*/*/*/
[11:48:05.079] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 156.7calibrated Vbg = 1.20824 :::*/*/*/*/
[11:48:05.079] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 151.7calibrated Vbg = 1.20413 :::*/*/*/*/
[11:48:05.079] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 156.9calibrated Vbg = 1.19607 :::*/*/*/*/
[11:48:05.079] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 158.4calibrated Vbg = 1.18876 :::*/*/*/*/
[11:48:05.079] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 157.2calibrated Vbg = 1.20187 :::*/*/*/*/
[11:48:05.079] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 161.1calibrated Vbg = 1.20019 :::*/*/*/*/
[11:48:05.079] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 154.9calibrated Vbg = 1.19926 :::*/*/*/*/
[11:48:05.079] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 148.1calibrated Vbg = 1.20215 :::*/*/*/*/
[11:48:05.082] <TB2> INFO: ----------------------------------------------------------------------
[11:48:05.082] <TB2> INFO: PixTestReadback::CalibrateIa()
[11:48:05.082] <TB2> INFO: ----------------------------------------------------------------------
[11:50:45.874] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C0.dat
[11:50:45.875] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C1.dat
[11:50:45.875] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C2.dat
[11:50:45.875] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C3.dat
[11:50:45.875] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C4.dat
[11:50:45.875] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C5.dat
[11:50:45.875] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C6.dat
[11:50:45.875] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C7.dat
[11:50:45.875] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C8.dat
[11:50:45.875] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C9.dat
[11:50:45.875] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C10.dat
[11:50:45.875] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C11.dat
[11:50:45.875] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C12.dat
[11:50:45.875] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C13.dat
[11:50:45.875] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C14.dat
[11:50:45.876] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C15.dat
[11:50:45.903] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:50:45.904] <TB2> INFO: PixTestReadback::doTest() done
[11:50:45.904] <TB2> INFO: Decoding statistics:
[11:50:45.904] <TB2> INFO: General information:
[11:50:45.904] <TB2> INFO: 16bit words read: 1536
[11:50:45.905] <TB2> INFO: valid events total: 256
[11:50:45.905] <TB2> INFO: empty events: 256
[11:50:45.905] <TB2> INFO: valid events with pixels: 0
[11:50:45.905] <TB2> INFO: valid pixel hits: 0
[11:50:45.905] <TB2> INFO: Event errors: 0
[11:50:45.905] <TB2> INFO: start marker: 0
[11:50:45.905] <TB2> INFO: stop marker: 0
[11:50:45.905] <TB2> INFO: overflow: 0
[11:50:45.905] <TB2> INFO: invalid 5bit words: 0
[11:50:45.905] <TB2> INFO: invalid XOR eye diagram: 0
[11:50:45.905] <TB2> INFO: frame (failed synchr.): 0
[11:50:45.905] <TB2> INFO: idle data (no TBM trl): 0
[11:50:45.905] <TB2> INFO: no data (only TBM hdr): 0
[11:50:45.905] <TB2> INFO: TBM errors: 0
[11:50:45.905] <TB2> INFO: flawed TBM headers: 0
[11:50:45.905] <TB2> INFO: flawed TBM trailers: 0
[11:50:45.905] <TB2> INFO: event ID mismatches: 0
[11:50:45.905] <TB2> INFO: ROC errors: 0
[11:50:45.905] <TB2> INFO: missing ROC header(s): 0
[11:50:45.905] <TB2> INFO: misplaced readback start: 0
[11:50:45.905] <TB2> INFO: Pixel decoding errors: 0
[11:50:45.905] <TB2> INFO: pixel data incomplete: 0
[11:50:45.905] <TB2> INFO: pixel address: 0
[11:50:45.905] <TB2> INFO: pulse height fill bit: 0
[11:50:45.905] <TB2> INFO: buffer corruption: 0
[11:50:45.956] <TB2> INFO: ######################################################################
[11:50:45.956] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[11:50:45.956] <TB2> INFO: ######################################################################
[11:50:45.958] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[11:50:46.166] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:50:46.166] <TB2> INFO: run 1 of 1
[11:50:46.403] <TB2> INFO: Expecting 3120000 events.
[11:51:17.720] <TB2> INFO: 665155 events read in total (30725ms).











[11:51:48.061] <TB2> INFO: 1326340 events read in total (61066ms).











[11:52:18.527] <TB2> INFO: 1983300 events read in total (91532ms).











[11:52:48.828] <TB2> INFO: 2638985 events read in total (121833ms).











[11:53:11.422] <TB2> INFO: 3120000 events read in total (144427ms).
[11:53:11.502] <TB2> INFO: Test took 145337ms.
[11:53:35.154] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 169 seconds
[11:53:35.154] <TB2> INFO: number of dead bumps (per ROC): 0 0 1 1 0 4 0 1 1 0 1 0 0 0 0 1
[11:53:35.154] <TB2> INFO: separation cut (per ROC): 107 115 107 99 106 102 109 106 94 105 102 91 99 107 105 104
[11:53:35.155] <TB2> INFO: Decoding statistics:
[11:53:35.155] <TB2> INFO: General information:
[11:53:35.155] <TB2> INFO: 16bit words read: 0
[11:53:35.155] <TB2> INFO: valid events total: 0
[11:53:35.155] <TB2> INFO: empty events: 0
[11:53:35.155] <TB2> INFO: valid events with pixels: 0
[11:53:35.155] <TB2> INFO: valid pixel hits: 0
[11:53:35.155] <TB2> INFO: Event errors: 0
[11:53:35.155] <TB2> INFO: start marker: 0
[11:53:35.155] <TB2> INFO: stop marker: 0
[11:53:35.155] <TB2> INFO: overflow: 0
[11:53:35.155] <TB2> INFO: invalid 5bit words: 0
[11:53:35.155] <TB2> INFO: invalid XOR eye diagram: 0
[11:53:35.155] <TB2> INFO: frame (failed synchr.): 0
[11:53:35.155] <TB2> INFO: idle data (no TBM trl): 0
[11:53:35.155] <TB2> INFO: no data (only TBM hdr): 0
[11:53:35.155] <TB2> INFO: TBM errors: 0
[11:53:35.155] <TB2> INFO: flawed TBM headers: 0
[11:53:35.155] <TB2> INFO: flawed TBM trailers: 0
[11:53:35.155] <TB2> INFO: event ID mismatches: 0
[11:53:35.155] <TB2> INFO: ROC errors: 0
[11:53:35.155] <TB2> INFO: missing ROC header(s): 0
[11:53:35.155] <TB2> INFO: misplaced readback start: 0
[11:53:35.155] <TB2> INFO: Pixel decoding errors: 0
[11:53:35.155] <TB2> INFO: pixel data incomplete: 0
[11:53:35.155] <TB2> INFO: pixel address: 0
[11:53:35.155] <TB2> INFO: pulse height fill bit: 0
[11:53:35.155] <TB2> INFO: buffer corruption: 0
[11:53:35.190] <TB2> INFO: ######################################################################
[11:53:35.190] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:53:35.190] <TB2> INFO: ######################################################################
[11:53:35.190] <TB2> INFO: ----------------------------------------------------------------------
[11:53:35.190] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:53:35.190] <TB2> INFO: ----------------------------------------------------------------------
[11:53:35.191] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[11:53:35.206] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[11:53:35.206] <TB2> INFO: run 1 of 1
[11:53:35.444] <TB2> INFO: Expecting 36608000 events.
[11:53:59.901] <TB2> INFO: 704300 events read in total (23865ms).
[11:54:23.311] <TB2> INFO: 1389950 events read in total (47275ms).
[11:54:46.763] <TB2> INFO: 2076300 events read in total (70727ms).
[11:55:09.948] <TB2> INFO: 2760700 events read in total (93912ms).
[11:55:33.179] <TB2> INFO: 3446800 events read in total (117143ms).
[11:55:56.657] <TB2> INFO: 4131600 events read in total (140621ms).
[11:56:20.173] <TB2> INFO: 4816850 events read in total (164137ms).
[11:56:43.644] <TB2> INFO: 5500450 events read in total (187608ms).
[11:57:06.991] <TB2> INFO: 6187800 events read in total (210955ms).
[11:57:30.405] <TB2> INFO: 6871500 events read in total (234369ms).
[11:57:53.799] <TB2> INFO: 7557000 events read in total (257763ms).
[11:58:17.319] <TB2> INFO: 8241000 events read in total (281283ms).
[11:58:40.473] <TB2> INFO: 8928200 events read in total (304437ms).
[11:59:03.680] <TB2> INFO: 9614450 events read in total (327644ms).
[11:59:27.133] <TB2> INFO: 10299050 events read in total (351097ms).
[11:59:50.434] <TB2> INFO: 10982150 events read in total (374398ms).
[12:00:13.642] <TB2> INFO: 11665850 events read in total (397606ms).
[12:00:36.987] <TB2> INFO: 12351050 events read in total (420951ms).
[12:01:00.347] <TB2> INFO: 13033950 events read in total (444311ms).
[12:01:23.643] <TB2> INFO: 13717050 events read in total (467607ms).
[12:01:47.013] <TB2> INFO: 14400350 events read in total (490977ms).
[12:02:10.326] <TB2> INFO: 15082850 events read in total (514290ms).
[12:02:33.644] <TB2> INFO: 15766600 events read in total (537608ms).
[12:02:57.007] <TB2> INFO: 16450300 events read in total (560971ms).
[12:03:20.194] <TB2> INFO: 17133100 events read in total (584158ms).
[12:03:43.480] <TB2> INFO: 17817700 events read in total (607444ms).
[12:04:06.741] <TB2> INFO: 18498000 events read in total (630705ms).
[12:04:29.776] <TB2> INFO: 19175200 events read in total (653740ms).
[12:04:53.024] <TB2> INFO: 19853850 events read in total (676988ms).
[12:05:15.932] <TB2> INFO: 20532450 events read in total (699896ms).
[12:05:39.285] <TB2> INFO: 21210400 events read in total (723249ms).
[12:06:02.349] <TB2> INFO: 21891000 events read in total (746313ms).
[12:06:25.889] <TB2> INFO: 22568550 events read in total (769853ms).
[12:06:49.341] <TB2> INFO: 23247600 events read in total (793305ms).
[12:07:12.650] <TB2> INFO: 23924400 events read in total (816614ms).
[12:07:35.806] <TB2> INFO: 24602750 events read in total (839770ms).
[12:07:59.546] <TB2> INFO: 25280100 events read in total (863510ms).
[12:08:22.833] <TB2> INFO: 25959900 events read in total (886797ms).
[12:08:45.993] <TB2> INFO: 26638150 events read in total (909957ms).
[12:09:09.308] <TB2> INFO: 27317000 events read in total (933272ms).
[12:09:32.953] <TB2> INFO: 27993750 events read in total (956917ms).
[12:09:56.324] <TB2> INFO: 28668500 events read in total (980288ms).
[12:10:19.683] <TB2> INFO: 29344550 events read in total (1003647ms).
[12:10:42.905] <TB2> INFO: 30021750 events read in total (1026869ms).
[12:11:06.219] <TB2> INFO: 30699300 events read in total (1050183ms).
[12:11:29.418] <TB2> INFO: 31374550 events read in total (1073382ms).
[12:11:52.390] <TB2> INFO: 32048300 events read in total (1096354ms).
[12:12:15.430] <TB2> INFO: 32723900 events read in total (1119394ms).
[12:12:38.502] <TB2> INFO: 33400650 events read in total (1142467ms).
[12:13:01.895] <TB2> INFO: 34078300 events read in total (1165859ms).
[12:13:24.985] <TB2> INFO: 34756600 events read in total (1188949ms).
[12:13:48.303] <TB2> INFO: 35434450 events read in total (1212267ms).
[12:14:12.373] <TB2> INFO: 36120100 events read in total (1236337ms).
[12:14:29.708] <TB2> INFO: 36608000 events read in total (1253672ms).
[12:14:29.784] <TB2> INFO: Test took 1254579ms.
[12:14:30.137] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:14:31.561] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:14:33.075] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:14:34.949] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:14:36.814] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:14:38.572] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:14:40.498] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:14:42.564] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:14:44.607] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:14:46.643] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:14:48.697] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:14:50.658] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:14:52.573] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:14:53.978] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:14:55.553] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:14:57.070] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:14:58.505] <TB2> INFO: PixTestScurves::scurves() done
[12:14:58.505] <TB2> INFO: Vcal mean: 127.90 133.18 143.60 123.61 135.60 136.06 130.07 132.95 120.62 124.50 126.30 116.52 119.55 130.87 129.87 135.40
[12:14:58.505] <TB2> INFO: Vcal RMS: 6.47 6.10 5.98 7.07 6.45 7.69 6.61 7.07 6.53 6.22 6.56 6.01 5.83 6.15 6.32 7.60
[12:14:58.506] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1283 seconds
[12:14:58.506] <TB2> INFO: Decoding statistics:
[12:14:58.506] <TB2> INFO: General information:
[12:14:58.506] <TB2> INFO: 16bit words read: 0
[12:14:58.506] <TB2> INFO: valid events total: 0
[12:14:58.506] <TB2> INFO: empty events: 0
[12:14:58.506] <TB2> INFO: valid events with pixels: 0
[12:14:58.506] <TB2> INFO: valid pixel hits: 0
[12:14:58.506] <TB2> INFO: Event errors: 0
[12:14:58.506] <TB2> INFO: start marker: 0
[12:14:58.506] <TB2> INFO: stop marker: 0
[12:14:58.506] <TB2> INFO: overflow: 0
[12:14:58.506] <TB2> INFO: invalid 5bit words: 0
[12:14:58.506] <TB2> INFO: invalid XOR eye diagram: 0
[12:14:58.506] <TB2> INFO: frame (failed synchr.): 0
[12:14:58.506] <TB2> INFO: idle data (no TBM trl): 0
[12:14:58.506] <TB2> INFO: no data (only TBM hdr): 0
[12:14:58.506] <TB2> INFO: TBM errors: 0
[12:14:58.506] <TB2> INFO: flawed TBM headers: 0
[12:14:58.506] <TB2> INFO: flawed TBM trailers: 0
[12:14:58.506] <TB2> INFO: event ID mismatches: 0
[12:14:58.506] <TB2> INFO: ROC errors: 0
[12:14:58.506] <TB2> INFO: missing ROC header(s): 0
[12:14:58.506] <TB2> INFO: misplaced readback start: 0
[12:14:58.506] <TB2> INFO: Pixel decoding errors: 0
[12:14:58.506] <TB2> INFO: pixel data incomplete: 0
[12:14:58.506] <TB2> INFO: pixel address: 0
[12:14:58.506] <TB2> INFO: pulse height fill bit: 0
[12:14:58.506] <TB2> INFO: buffer corruption: 0
[12:14:58.579] <TB2> INFO: ######################################################################
[12:14:58.579] <TB2> INFO: PixTestTrim::doTest()
[12:14:58.579] <TB2> INFO: ######################################################################
[12:14:58.580] <TB2> INFO: ----------------------------------------------------------------------
[12:14:58.580] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:14:58.580] <TB2> INFO: ----------------------------------------------------------------------
[12:14:58.624] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:14:58.624] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:14:58.636] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:14:58.636] <TB2> INFO: run 1 of 1
[12:14:58.885] <TB2> INFO: Expecting 5025280 events.
[12:15:30.450] <TB2> INFO: 836984 events read in total (30965ms).
[12:16:01.945] <TB2> INFO: 1672728 events read in total (62460ms).
[12:16:33.080] <TB2> INFO: 2505848 events read in total (93596ms).
[12:17:04.281] <TB2> INFO: 3336352 events read in total (124796ms).
[12:17:34.823] <TB2> INFO: 4164288 events read in total (155339ms).
[12:18:05.692] <TB2> INFO: 4990832 events read in total (186207ms).
[12:18:07.389] <TB2> INFO: 5025280 events read in total (187904ms).
[12:18:07.467] <TB2> INFO: Test took 188831ms.
[12:18:25.928] <TB2> INFO: ROC 0 VthrComp = 123
[12:18:25.928] <TB2> INFO: ROC 1 VthrComp = 132
[12:18:25.928] <TB2> INFO: ROC 2 VthrComp = 129
[12:18:25.928] <TB2> INFO: ROC 3 VthrComp = 116
[12:18:25.928] <TB2> INFO: ROC 4 VthrComp = 124
[12:18:25.929] <TB2> INFO: ROC 5 VthrComp = 122
[12:18:25.929] <TB2> INFO: ROC 6 VthrComp = 128
[12:18:25.929] <TB2> INFO: ROC 7 VthrComp = 127
[12:18:25.929] <TB2> INFO: ROC 8 VthrComp = 110
[12:18:25.929] <TB2> INFO: ROC 9 VthrComp = 123
[12:18:25.929] <TB2> INFO: ROC 10 VthrComp = 116
[12:18:25.929] <TB2> INFO: ROC 11 VthrComp = 103
[12:18:25.929] <TB2> INFO: ROC 12 VthrComp = 116
[12:18:25.930] <TB2> INFO: ROC 13 VthrComp = 126
[12:18:25.930] <TB2> INFO: ROC 14 VthrComp = 127
[12:18:25.930] <TB2> INFO: ROC 15 VthrComp = 120
[12:18:26.235] <TB2> INFO: Expecting 41600 events.
[12:18:29.846] <TB2> INFO: 41600 events read in total (3020ms).
[12:18:29.847] <TB2> INFO: Test took 3915ms.
[12:18:29.860] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:18:29.860] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:18:29.874] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:18:29.874] <TB2> INFO: run 1 of 1
[12:18:30.161] <TB2> INFO: Expecting 5025280 events.
[12:18:56.896] <TB2> INFO: 595568 events read in total (26144ms).
[12:19:22.990] <TB2> INFO: 1190248 events read in total (52238ms).
[12:19:49.042] <TB2> INFO: 1784432 events read in total (78290ms).
[12:20:15.102] <TB2> INFO: 2378048 events read in total (104350ms).
[12:20:41.159] <TB2> INFO: 2969640 events read in total (130407ms).
[12:21:07.284] <TB2> INFO: 3559208 events read in total (156532ms).
[12:21:33.368] <TB2> INFO: 4147040 events read in total (182616ms).
[12:21:59.539] <TB2> INFO: 4734096 events read in total (208787ms).
[12:22:13.040] <TB2> INFO: 5025280 events read in total (222288ms).
[12:22:13.184] <TB2> INFO: Test took 223311ms.
[12:22:39.558] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 63.7514 for pixel 7/8 mean/min/max = 47.9469/31.9879/63.9059
[12:22:39.558] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 62.4512 for pixel 0/0 mean/min/max = 47.3689/32.2295/62.5084
[12:22:39.559] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 74.6059 for pixel 17/2 mean/min/max = 55.2205/35.786/74.6549
[12:22:39.559] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 66.693 for pixel 20/2 mean/min/max = 48.8178/30.9162/66.7193
[12:22:39.560] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 67.7305 for pixel 46/1 mean/min/max = 50.1698/31.9008/68.4389
[12:22:39.560] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 71.2701 for pixel 0/0 mean/min/max = 50.8359/30.2775/71.3943
[12:22:39.560] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 64.9722 for pixel 4/6 mean/min/max = 49.1342/33.0609/65.2075
[12:22:39.561] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 69.138 for pixel 0/14 mean/min/max = 50.4168/31.3804/69.4532
[12:22:39.561] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 69.7636 for pixel 3/5 mean/min/max = 52.0887/34.1401/70.0372
[12:22:39.562] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 62.0061 for pixel 12/6 mean/min/max = 46.7672/31.465/62.0694
[12:22:39.562] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 69.4168 for pixel 51/8 mean/min/max = 50.2174/30.3852/70.0497
[12:22:39.562] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 70.6533 for pixel 1/3 mean/min/max = 51.6045/32.421/70.7879
[12:22:39.563] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 65.606 for pixel 0/12 mean/min/max = 48.1905/30.6513/65.7297
[12:22:39.563] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 63.4193 for pixel 18/12 mean/min/max = 47.9439/32.1353/63.7525
[12:22:39.563] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 62.0992 for pixel 0/7 mean/min/max = 47.1063/32.0868/62.1257
[12:22:39.564] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 75.6894 for pixel 48/14 mean/min/max = 52.6419/29.3623/75.9215
[12:22:39.564] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:22:39.653] <TB2> INFO: Expecting 411648 events.
[12:22:49.301] <TB2> INFO: 411648 events read in total (9056ms).
[12:22:49.308] <TB2> INFO: Expecting 411648 events.
[12:22:58.703] <TB2> INFO: 411648 events read in total (8992ms).
[12:22:58.713] <TB2> INFO: Expecting 411648 events.
[12:23:08.197] <TB2> INFO: 411648 events read in total (9081ms).
[12:23:08.214] <TB2> INFO: Expecting 411648 events.
[12:23:17.697] <TB2> INFO: 411648 events read in total (9080ms).
[12:23:17.716] <TB2> INFO: Expecting 411648 events.
[12:23:27.210] <TB2> INFO: 411648 events read in total (9091ms).
[12:23:27.230] <TB2> INFO: Expecting 411648 events.
[12:23:36.629] <TB2> INFO: 411648 events read in total (8996ms).
[12:23:36.651] <TB2> INFO: Expecting 411648 events.
[12:23:46.116] <TB2> INFO: 411648 events read in total (9062ms).
[12:23:46.140] <TB2> INFO: Expecting 411648 events.
[12:23:55.562] <TB2> INFO: 411648 events read in total (9019ms).
[12:23:55.589] <TB2> INFO: Expecting 411648 events.
[12:24:04.986] <TB2> INFO: 411648 events read in total (8994ms).
[12:24:05.023] <TB2> INFO: Expecting 411648 events.
[12:24:14.359] <TB2> INFO: 411648 events read in total (8933ms).
[12:24:14.391] <TB2> INFO: Expecting 411648 events.
[12:24:23.818] <TB2> INFO: 411648 events read in total (9024ms).
[12:24:23.852] <TB2> INFO: Expecting 411648 events.
[12:24:33.076] <TB2> INFO: 411648 events read in total (8821ms).
[12:24:33.124] <TB2> INFO: Expecting 411648 events.
[12:24:42.322] <TB2> INFO: 411648 events read in total (8795ms).
[12:24:42.365] <TB2> INFO: Expecting 411648 events.
[12:24:51.790] <TB2> INFO: 411648 events read in total (9022ms).
[12:24:51.835] <TB2> INFO: Expecting 411648 events.
[12:25:01.125] <TB2> INFO: 411648 events read in total (8886ms).
[12:25:01.171] <TB2> INFO: Expecting 411648 events.
[12:25:10.561] <TB2> INFO: 411648 events read in total (8988ms).
[12:25:10.636] <TB2> INFO: Test took 151072ms.
[12:25:11.361] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:25:11.375] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:25:11.375] <TB2> INFO: run 1 of 1
[12:25:11.685] <TB2> INFO: Expecting 5025280 events.
[12:25:38.278] <TB2> INFO: 598072 events read in total (25999ms).
[12:26:05.071] <TB2> INFO: 1195768 events read in total (52792ms).
[12:26:31.811] <TB2> INFO: 1792016 events read in total (79532ms).
[12:26:58.439] <TB2> INFO: 2386496 events read in total (106160ms).
[12:27:25.027] <TB2> INFO: 2982112 events read in total (132749ms).
[12:27:52.499] <TB2> INFO: 3584560 events read in total (160220ms).
[12:28:21.240] <TB2> INFO: 4192040 events read in total (188961ms).
[12:28:49.477] <TB2> INFO: 4801472 events read in total (217198ms).
[12:29:01.025] <TB2> INFO: 5025280 events read in total (228746ms).
[12:29:01.191] <TB2> INFO: Test took 229817ms.
[12:29:25.509] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 0.425673 .. 146.809709
[12:29:25.835] <TB2> INFO: Expecting 208000 events.
[12:29:35.344] <TB2> INFO: 208000 events read in total (8917ms).
[12:29:35.345] <TB2> INFO: Test took 9834ms.
[12:29:35.400] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 0 .. 156 (-1/-1) hits flags = 528 (plus default)
[12:29:35.414] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:29:35.414] <TB2> INFO: run 1 of 1
[12:29:35.724] <TB2> INFO: Expecting 5224960 events.
[12:30:02.546] <TB2> INFO: 587120 events read in total (26231ms).
[12:30:28.988] <TB2> INFO: 1173760 events read in total (52674ms).
[12:30:56.075] <TB2> INFO: 1760504 events read in total (79760ms).
[12:31:22.889] <TB2> INFO: 2346936 events read in total (106574ms).
[12:32:21.929] <TB2> INFO: 2933320 events read in total (165615ms).
[12:33:00.342] <TB2> INFO: 3520000 events read in total (204027ms).
[12:33:27.167] <TB2> INFO: 4107048 events read in total (230852ms).
[12:33:53.641] <TB2> INFO: 4693000 events read in total (257326ms).
[12:34:18.413] <TB2> INFO: 5224960 events read in total (282098ms).
[12:34:18.570] <TB2> INFO: Test took 283157ms.
[12:34:44.895] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 26.043445 .. 47.555864
[12:34:45.132] <TB2> INFO: Expecting 208000 events.
[12:34:55.055] <TB2> INFO: 208000 events read in total (9331ms).
[12:34:55.056] <TB2> INFO: Test took 10160ms.
[12:34:55.103] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 57 (-1/-1) hits flags = 528 (plus default)
[12:34:55.117] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:34:55.117] <TB2> INFO: run 1 of 1
[12:34:55.395] <TB2> INFO: Expecting 1397760 events.
[12:35:23.975] <TB2> INFO: 665408 events read in total (27985ms).
[12:35:51.898] <TB2> INFO: 1328928 events read in total (55909ms).
[12:35:55.218] <TB2> INFO: 1397760 events read in total (59228ms).
[12:35:55.268] <TB2> INFO: Test took 60152ms.
[12:36:08.530] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 29.500000 .. 51.441018
[12:36:08.809] <TB2> INFO: Expecting 208000 events.
[12:36:18.957] <TB2> INFO: 208000 events read in total (9556ms).
[12:36:18.958] <TB2> INFO: Test took 10426ms.
[12:36:19.005] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 19 .. 61 (-1/-1) hits flags = 528 (plus default)
[12:36:19.018] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:36:19.018] <TB2> INFO: run 1 of 1
[12:36:19.296] <TB2> INFO: Expecting 1431040 events.
[12:36:47.347] <TB2> INFO: 635768 events read in total (27460ms).
[12:37:15.296] <TB2> INFO: 1269376 events read in total (55409ms).
[12:37:22.568] <TB2> INFO: 1431040 events read in total (62681ms).
[12:37:22.615] <TB2> INFO: Test took 63598ms.
[12:37:38.105] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 21.500000 .. 56.377351
[12:37:38.344] <TB2> INFO: Expecting 208000 events.
[12:37:48.305] <TB2> INFO: 208000 events read in total (9369ms).
[12:37:48.306] <TB2> INFO: Test took 10200ms.
[12:37:48.381] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 11 .. 66 (-1/-1) hits flags = 528 (plus default)
[12:37:48.395] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:37:48.395] <TB2> INFO: run 1 of 1
[12:37:48.675] <TB2> INFO: Expecting 1863680 events.
[12:38:17.147] <TB2> INFO: 648168 events read in total (27880ms).
[12:38:45.300] <TB2> INFO: 1294960 events read in total (56033ms).
[12:39:09.656] <TB2> INFO: 1863680 events read in total (80389ms).
[12:39:09.712] <TB2> INFO: Test took 81317ms.
[12:39:24.355] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:39:24.355] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:39:24.368] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:39:24.368] <TB2> INFO: run 1 of 1
[12:39:24.625] <TB2> INFO: Expecting 1364480 events.
[12:39:53.274] <TB2> INFO: 670424 events read in total (28057ms).
[12:40:21.495] <TB2> INFO: 1339968 events read in total (56278ms).
[12:40:22.980] <TB2> INFO: 1364480 events read in total (57764ms).
[12:40:23.016] <TB2> INFO: Test took 58649ms.
[12:40:34.725] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C0.dat
[12:40:34.725] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C1.dat
[12:40:34.725] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C2.dat
[12:40:34.725] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C3.dat
[12:40:34.725] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C4.dat
[12:40:34.726] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C5.dat
[12:40:34.726] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C6.dat
[12:40:34.726] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C7.dat
[12:40:34.726] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C8.dat
[12:40:34.726] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C9.dat
[12:40:34.726] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C10.dat
[12:40:34.726] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C11.dat
[12:40:34.726] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C12.dat
[12:40:34.727] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C13.dat
[12:40:34.727] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C14.dat
[12:40:34.727] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C15.dat
[12:40:34.727] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C0.dat
[12:40:34.735] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C1.dat
[12:40:34.740] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C2.dat
[12:40:34.745] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C3.dat
[12:40:34.750] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C4.dat
[12:40:34.755] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C5.dat
[12:40:34.759] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C6.dat
[12:40:34.764] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C7.dat
[12:40:34.769] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C8.dat
[12:40:34.773] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C9.dat
[12:40:34.778] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C10.dat
[12:40:34.783] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C11.dat
[12:40:34.787] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C12.dat
[12:40:34.792] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C13.dat
[12:40:34.797] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C14.dat
[12:40:34.801] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C15.dat
[12:40:34.806] <TB2> INFO: PixTestTrim::trimTest() done
[12:40:34.806] <TB2> INFO: vtrim: 145 113 160 134 146 151 139 146 140 129 151 161 149 132 116 165
[12:40:34.806] <TB2> INFO: vthrcomp: 123 132 129 116 124 122 128 127 110 123 116 103 116 126 127 120
[12:40:34.806] <TB2> INFO: vcal mean: 35.39 35.09 37.09 35.39 35.87 36.09 35.54 35.34 35.76 35.48 35.43 35.42 34.98 37.05 35.13 35.93
[12:40:34.806] <TB2> INFO: vcal RMS: 1.56 1.10 3.19 1.67 2.16 2.57 1.56 1.50 2.04 1.59 1.60 1.57 1.16 2.92 1.25 2.32
[12:40:34.806] <TB2> INFO: bits mean: 9.88 8.82 8.75 9.80 9.42 9.73 8.99 8.84 8.86 9.72 8.66 9.18 9.56 10.23 9.10 9.66
[12:40:34.806] <TB2> INFO: bits RMS: 2.52 2.82 2.84 2.60 2.76 2.74 2.66 2.90 2.64 2.68 3.20 2.61 2.78 2.66 2.85 2.81
[12:40:34.814] <TB2> INFO: ----------------------------------------------------------------------
[12:40:34.814] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:40:34.814] <TB2> INFO: ----------------------------------------------------------------------
[12:40:34.816] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:40:34.831] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:40:34.831] <TB2> INFO: run 1 of 1
[12:40:35.070] <TB2> INFO: Expecting 4160000 events.
[12:41:08.288] <TB2> INFO: 779000 events read in total (32627ms).
[12:41:40.937] <TB2> INFO: 1554155 events read in total (65276ms).
[12:42:13.420] <TB2> INFO: 2325250 events read in total (97760ms).
[12:42:45.787] <TB2> INFO: 3091100 events read in total (130126ms).
[12:43:19.264] <TB2> INFO: 3851835 events read in total (163603ms).
[12:43:32.447] <TB2> INFO: 4160000 events read in total (176786ms).
[12:43:32.506] <TB2> INFO: Test took 177675ms.
[12:43:55.285] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[12:43:55.299] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:43:55.299] <TB2> INFO: run 1 of 1
[12:43:55.535] <TB2> INFO: Expecting 5324800 events.
[12:44:26.672] <TB2> INFO: 690805 events read in total (30546ms).
[12:44:57.312] <TB2> INFO: 1379495 events read in total (61186ms).
[12:45:27.966] <TB2> INFO: 2067050 events read in total (91840ms).
[12:45:58.592] <TB2> INFO: 2752835 events read in total (122466ms).
[12:46:29.291] <TB2> INFO: 3435300 events read in total (153165ms).
[12:47:00.878] <TB2> INFO: 4116640 events read in total (184752ms).
[12:47:31.448] <TB2> INFO: 4795615 events read in total (215322ms).
[12:47:55.137] <TB2> INFO: 5324800 events read in total (239011ms).
[12:47:55.284] <TB2> INFO: Test took 239985ms.
[12:48:29.404] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 220 (-1/-1) hits flags = 528 (plus default)
[12:48:29.418] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:48:29.418] <TB2> INFO: run 1 of 1
[12:48:29.697] <TB2> INFO: Expecting 4596800 events.
[12:49:01.849] <TB2> INFO: 725150 events read in total (31560ms).
[12:49:33.092] <TB2> INFO: 1448255 events read in total (62803ms).
[12:50:04.618] <TB2> INFO: 2168920 events read in total (94329ms).
[12:50:37.398] <TB2> INFO: 2885300 events read in total (127109ms).
[12:51:08.932] <TB2> INFO: 3598595 events read in total (158643ms).
[12:51:40.693] <TB2> INFO: 4309595 events read in total (190404ms).
[12:51:53.495] <TB2> INFO: 4596800 events read in total (203206ms).
[12:51:53.634] <TB2> INFO: Test took 204216ms.
[12:52:18.749] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 219 (-1/-1) hits flags = 528 (plus default)
[12:52:18.763] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:52:18.763] <TB2> INFO: run 1 of 1
[12:52:19.054] <TB2> INFO: Expecting 4576000 events.
[12:52:51.090] <TB2> INFO: 726815 events read in total (31444ms).
[12:53:22.744] <TB2> INFO: 1450535 events read in total (63098ms).
[12:53:54.575] <TB2> INFO: 2172515 events read in total (94929ms).
[12:54:27.460] <TB2> INFO: 2889680 events read in total (127814ms).
[12:54:59.197] <TB2> INFO: 3603730 events read in total (159551ms).
[12:55:30.859] <TB2> INFO: 4316320 events read in total (191213ms).
[12:55:42.470] <TB2> INFO: 4576000 events read in total (202824ms).
[12:55:42.591] <TB2> INFO: Test took 203828ms.
[12:56:09.333] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 218 (-1/-1) hits flags = 528 (plus default)
[12:56:09.346] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:56:09.346] <TB2> INFO: run 1 of 1
[12:56:09.587] <TB2> INFO: Expecting 4555200 events.
[12:56:42.066] <TB2> INFO: 728050 events read in total (31887ms).
[12:57:13.652] <TB2> INFO: 1453620 events read in total (63473ms).
[12:57:45.427] <TB2> INFO: 2176575 events read in total (95248ms).
[12:58:18.346] <TB2> INFO: 2894890 events read in total (128167ms).
[12:58:50.411] <TB2> INFO: 3610225 events read in total (160232ms).
[12:59:21.883] <TB2> INFO: 4323820 events read in total (191704ms).
[12:59:32.348] <TB2> INFO: 4555200 events read in total (202169ms).
[12:59:32.451] <TB2> INFO: Test took 203104ms.
[12:59:58.391] <TB2> INFO: PixTestTrim::trimBitTest() done
[12:59:58.393] <TB2> INFO: PixTestTrim::doTest() done, duration: 2699 seconds
[12:59:58.393] <TB2> INFO: Decoding statistics:
[12:59:58.393] <TB2> INFO: General information:
[12:59:58.393] <TB2> INFO: 16bit words read: 0
[12:59:58.393] <TB2> INFO: valid events total: 0
[12:59:58.393] <TB2> INFO: empty events: 0
[12:59:58.393] <TB2> INFO: valid events with pixels: 0
[12:59:58.393] <TB2> INFO: valid pixel hits: 0
[12:59:58.393] <TB2> INFO: Event errors: 0
[12:59:58.393] <TB2> INFO: start marker: 0
[12:59:58.393] <TB2> INFO: stop marker: 0
[12:59:58.393] <TB2> INFO: overflow: 0
[12:59:58.393] <TB2> INFO: invalid 5bit words: 0
[12:59:58.393] <TB2> INFO: invalid XOR eye diagram: 0
[12:59:58.393] <TB2> INFO: frame (failed synchr.): 0
[12:59:58.393] <TB2> INFO: idle data (no TBM trl): 0
[12:59:58.393] <TB2> INFO: no data (only TBM hdr): 0
[12:59:58.393] <TB2> INFO: TBM errors: 0
[12:59:58.393] <TB2> INFO: flawed TBM headers: 0
[12:59:58.393] <TB2> INFO: flawed TBM trailers: 0
[12:59:58.393] <TB2> INFO: event ID mismatches: 0
[12:59:58.393] <TB2> INFO: ROC errors: 0
[12:59:58.393] <TB2> INFO: missing ROC header(s): 0
[12:59:58.393] <TB2> INFO: misplaced readback start: 0
[12:59:58.393] <TB2> INFO: Pixel decoding errors: 0
[12:59:58.393] <TB2> INFO: pixel data incomplete: 0
[12:59:58.393] <TB2> INFO: pixel address: 0
[12:59:58.393] <TB2> INFO: pulse height fill bit: 0
[12:59:58.393] <TB2> INFO: buffer corruption: 0
[12:59:58.991] <TB2> INFO: ######################################################################
[12:59:58.991] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[12:59:58.991] <TB2> INFO: ######################################################################
[12:59:59.230] <TB2> INFO: Expecting 41600 events.
[13:00:02.714] <TB2> INFO: 41600 events read in total (2892ms).
[13:00:02.715] <TB2> INFO: Test took 3722ms.
[13:00:03.156] <TB2> INFO: Expecting 41600 events.
[13:00:06.664] <TB2> INFO: 41600 events read in total (2917ms).
[13:00:06.665] <TB2> INFO: Test took 3747ms.
[13:00:06.675] <TB2> INFO: Max pixel from chip 0 is [4 ,69] phvalue 153
[13:00:06.675] <TB2> INFO: Max pixel from chip 1 is [14 ,17] phvalue 96
[13:00:06.675] <TB2> INFO: Max pixel from chip 2 is [30 ,20] phvalue 122
[13:00:06.675] <TB2> INFO: Max pixel from chip 3 is [16 ,23] phvalue 224
[13:00:06.675] <TB2> INFO: Max pixel from chip 4 is [6 ,19] phvalue 133
[13:00:06.675] <TB2> INFO: Max pixel from chip 5 is [19 ,8] phvalue 147
[13:00:06.676] <TB2> INFO: Max pixel from chip 6 is [11 ,15] phvalue 151
[13:00:06.676] <TB2> INFO: Max pixel from chip 7 is [12 ,15] phvalue 110
[13:00:06.676] <TB2> INFO: Max pixel from chip 8 is [12 ,8] phvalue 128
[13:00:06.676] <TB2> INFO: Max pixel from chip 9 is [14 ,29] phvalue 100
[13:00:06.676] <TB2> INFO: Max pixel from chip 10 is [4 ,26] phvalue 158
[13:00:06.676] <TB2> INFO: Max pixel from chip 11 is [5 ,12] phvalue 202
[13:00:06.676] <TB2> INFO: Max pixel from chip 12 is [14 ,30] phvalue 111
[13:00:06.677] <TB2> INFO: Max pixel from chip 13 is [8 ,10] phvalue 147
[13:00:06.677] <TB2> INFO: Max pixel from chip 14 is [14 ,5] phvalue 101
[13:00:06.677] <TB2> INFO: Max pixel from chip 15 is [18 ,46] phvalue 143
[13:00:06.957] <TB2> INFO: Expecting 41600 events.
[13:00:10.476] <TB2> INFO: 41600 events read in total (2928ms).
[13:00:10.476] <TB2> INFO: Test took 3785ms.
[13:00:10.489] <TB2> INFO: Min pixel from chip 0 is [3 ,5] phvalue 255
[13:00:10.489] <TB2> INFO: Min pixel from chip 1 is [24 ,43] phvalue 247
[13:00:10.489] <TB2> INFO: Min pixel from chip 2 is [3 ,5] phvalue 255
[13:00:10.490] <TB2> INFO: Min pixel from chip 3 is [3 ,5] phvalue 255
[13:00:10.490] <TB2> INFO: Min pixel from chip 4 is [3 ,5] phvalue 255
[13:00:10.490] <TB2> INFO: Min pixel from chip 5 is [3 ,5] phvalue 255
[13:00:10.490] <TB2> INFO: Min pixel from chip 6 is [3 ,5] phvalue 255
[13:00:10.490] <TB2> INFO: Min pixel from chip 7 is [3 ,5] phvalue 255
[13:00:10.490] <TB2> INFO: Min pixel from chip 8 is [3 ,5] phvalue 255
[13:00:10.490] <TB2> INFO: Min pixel from chip 9 is [3 ,5] phvalue 255
[13:00:10.491] <TB2> INFO: Min pixel from chip 10 is [3 ,5] phvalue 255
[13:00:10.491] <TB2> INFO: Min pixel from chip 11 is [3 ,5] phvalue 255
[13:00:10.491] <TB2> INFO: Min pixel from chip 12 is [3 ,5] phvalue 255
[13:00:10.491] <TB2> INFO: Min pixel from chip 13 is [3 ,5] phvalue 255
[13:00:10.491] <TB2> INFO: Min pixel from chip 14 is [3 ,5] phvalue 255
[13:00:10.491] <TB2> INFO: Min pixel from chip 15 is [3 ,5] phvalue 255
[13:00:10.770] <TB2> INFO: Expecting 2560 events.
[13:00:11.668] <TB2> INFO: 2560 events read in total (306ms).
[13:00:11.669] <TB2> INFO: Test took 1176ms.
[13:00:11.976] <TB2> INFO: Expecting 2560 events.
[13:00:12.869] <TB2> INFO: 2560 events read in total (301ms).
[13:00:12.870] <TB2> INFO: Test took 1201ms.
[13:00:13.176] <TB2> INFO: Expecting 2560 events.
[13:00:14.068] <TB2> INFO: 2560 events read in total (300ms).
[13:00:14.068] <TB2> INFO: Test took 1198ms.
[13:00:14.376] <TB2> INFO: Expecting 2560 events.
[13:00:15.268] <TB2> INFO: 2560 events read in total (300ms).
[13:00:15.268] <TB2> INFO: Test took 1199ms.
[13:00:15.575] <TB2> INFO: Expecting 2560 events.
[13:00:16.457] <TB2> INFO: 2560 events read in total (290ms).
[13:00:16.457] <TB2> INFO: Test took 1188ms.
[13:00:16.765] <TB2> INFO: Expecting 2560 events.
[13:00:17.647] <TB2> INFO: 2560 events read in total (290ms).
[13:00:17.647] <TB2> INFO: Test took 1189ms.
[13:00:17.953] <TB2> INFO: Expecting 2560 events.
[13:00:18.833] <TB2> INFO: 2560 events read in total (288ms).
[13:00:18.833] <TB2> INFO: Test took 1185ms.
[13:00:19.141] <TB2> INFO: Expecting 2560 events.
[13:00:20.026] <TB2> INFO: 2560 events read in total (293ms).
[13:00:20.026] <TB2> INFO: Test took 1193ms.
[13:00:20.334] <TB2> INFO: Expecting 2560 events.
[13:00:21.214] <TB2> INFO: 2560 events read in total (288ms).
[13:00:21.214] <TB2> INFO: Test took 1187ms.
[13:00:21.522] <TB2> INFO: Expecting 2560 events.
[13:00:22.410] <TB2> INFO: 2560 events read in total (296ms).
[13:00:22.410] <TB2> INFO: Test took 1195ms.
[13:00:22.718] <TB2> INFO: Expecting 2560 events.
[13:00:23.606] <TB2> INFO: 2560 events read in total (296ms).
[13:00:23.607] <TB2> INFO: Test took 1196ms.
[13:00:23.913] <TB2> INFO: Expecting 2560 events.
[13:00:24.797] <TB2> INFO: 2560 events read in total (293ms).
[13:00:24.798] <TB2> INFO: Test took 1191ms.
[13:00:25.106] <TB2> INFO: Expecting 2560 events.
[13:00:25.001] <TB2> INFO: 2560 events read in total (303ms).
[13:00:25.001] <TB2> INFO: Test took 1203ms.
[13:00:26.309] <TB2> INFO: Expecting 2560 events.
[13:00:27.207] <TB2> INFO: 2560 events read in total (306ms).
[13:00:27.207] <TB2> INFO: Test took 1205ms.
[13:00:27.515] <TB2> INFO: Expecting 2560 events.
[13:00:28.400] <TB2> INFO: 2560 events read in total (293ms).
[13:00:28.400] <TB2> INFO: Test took 1192ms.
[13:00:28.707] <TB2> INFO: Expecting 2560 events.
[13:00:29.591] <TB2> INFO: 2560 events read in total (292ms).
[13:00:29.591] <TB2> INFO: Test took 1190ms.
[13:00:29.594] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:00:29.900] <TB2> INFO: Expecting 655360 events.
[13:00:44.723] <TB2> INFO: 655360 events read in total (14231ms).
[13:00:44.735] <TB2> INFO: Expecting 655360 events.
[13:00:59.435] <TB2> INFO: 655360 events read in total (14297ms).
[13:00:59.456] <TB2> INFO: Expecting 655360 events.
[13:01:14.105] <TB2> INFO: 655360 events read in total (14246ms).
[13:01:14.126] <TB2> INFO: Expecting 655360 events.
[13:01:28.957] <TB2> INFO: 655360 events read in total (14428ms).
[13:01:28.983] <TB2> INFO: Expecting 655360 events.
[13:01:43.664] <TB2> INFO: 655360 events read in total (14278ms).
[13:01:43.696] <TB2> INFO: Expecting 655360 events.
[13:01:58.532] <TB2> INFO: 655360 events read in total (14433ms).
[13:01:58.568] <TB2> INFO: Expecting 655360 events.
[13:02:13.369] <TB2> INFO: 655360 events read in total (14398ms).
[13:02:13.409] <TB2> INFO: Expecting 655360 events.
[13:02:28.237] <TB2> INFO: 655360 events read in total (14424ms).
[13:02:28.305] <TB2> INFO: Expecting 655360 events.
[13:02:43.104] <TB2> INFO: 655360 events read in total (14396ms).
[13:02:43.157] <TB2> INFO: Expecting 655360 events.
[13:02:58.021] <TB2> INFO: 655360 events read in total (14461ms).
[13:02:58.111] <TB2> INFO: Expecting 655360 events.
[13:03:12.995] <TB2> INFO: 655360 events read in total (14481ms).
[13:03:13.059] <TB2> INFO: Expecting 655360 events.
[13:03:27.967] <TB2> INFO: 655360 events read in total (14505ms).
[13:03:28.044] <TB2> INFO: Expecting 655360 events.
[13:03:42.793] <TB2> INFO: 655360 events read in total (14346ms).
[13:03:42.887] <TB2> INFO: Expecting 655360 events.
[13:03:57.228] <TB2> INFO: 655360 events read in total (13938ms).
[13:03:57.379] <TB2> INFO: Expecting 655360 events.
[13:04:12.244] <TB2> INFO: 655360 events read in total (14462ms).
[13:04:12.376] <TB2> INFO: Expecting 655360 events.
[13:04:27.098] <TB2> INFO: 655360 events read in total (14319ms).
[13:04:27.198] <TB2> INFO: Test took 237604ms.
[13:04:27.294] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:04:27.551] <TB2> INFO: Expecting 655360 events.
[13:04:42.294] <TB2> INFO: 655360 events read in total (14151ms).
[13:04:42.307] <TB2> INFO: Expecting 655360 events.
[13:04:56.550] <TB2> INFO: 655360 events read in total (13840ms).
[13:04:56.567] <TB2> INFO: Expecting 655360 events.
[13:05:11.153] <TB2> INFO: 655360 events read in total (14183ms).
[13:05:11.180] <TB2> INFO: Expecting 655360 events.
[13:05:25.613] <TB2> INFO: 655360 events read in total (14030ms).
[13:05:25.638] <TB2> INFO: Expecting 655360 events.
[13:05:40.144] <TB2> INFO: 655360 events read in total (14103ms).
[13:05:40.175] <TB2> INFO: Expecting 655360 events.
[13:05:54.574] <TB2> INFO: 655360 events read in total (13996ms).
[13:05:54.607] <TB2> INFO: Expecting 655360 events.
[13:06:09.333] <TB2> INFO: 655360 events read in total (14323ms).
[13:06:09.370] <TB2> INFO: Expecting 655360 events.
[13:06:24.096] <TB2> INFO: 655360 events read in total (14323ms).
[13:06:24.165] <TB2> INFO: Expecting 655360 events.
[13:06:38.735] <TB2> INFO: 655360 events read in total (14167ms).
[13:06:38.788] <TB2> INFO: Expecting 655360 events.
[13:06:53.256] <TB2> INFO: 655360 events read in total (14065ms).
[13:06:53.334] <TB2> INFO: Expecting 655360 events.
[13:07:08.220] <TB2> INFO: 655360 events read in total (14483ms).
[13:07:08.293] <TB2> INFO: Expecting 655360 events.
[13:07:23.044] <TB2> INFO: 655360 events read in total (14347ms).
[13:07:23.135] <TB2> INFO: Expecting 655360 events.
[13:07:37.738] <TB2> INFO: 655360 events read in total (14200ms).
[13:07:37.821] <TB2> INFO: Expecting 655360 events.
[13:07:52.280] <TB2> INFO: 655360 events read in total (14056ms).
[13:07:52.391] <TB2> INFO: Expecting 655360 events.
[13:08:06.967] <TB2> INFO: 655360 events read in total (14173ms).
[13:08:07.065] <TB2> INFO: Expecting 655360 events.
[13:08:21.583] <TB2> INFO: 655360 events read in total (14115ms).
[13:08:21.721] <TB2> INFO: Test took 234428ms.
[13:08:21.958] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:08:21.966] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:08:21.974] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:08:21.982] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:08:21.990] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:08:21.998] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[13:08:22.006] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[13:08:22.014] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:08:22.023] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:08:22.030] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:08:22.038] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:08:22.046] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:08:22.054] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:08:22.062] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:08:22.070] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:08:22.078] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:08:22.086] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:08:22.094] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:08:22.102] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:08:22.110] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:08:22.118] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:08:22.126] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:08:22.134] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:08:22.142] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:08:22.150] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:08:22.158] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:08:22.166] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:08:22.173] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:08:22.181] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:08:22.189] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:08:22.197] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:08:22.205] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:08:22.213] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:08:22.221] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:08:22.228] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:08:22.237] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:08:22.244] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:08:22.250] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[13:08:22.256] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[13:08:22.262] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[13:08:22.268] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[13:08:22.273] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:08:22.279] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:08:22.285] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:08:22.291] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:08:22.297] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:08:22.333] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C0.dat
[13:08:22.333] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C1.dat
[13:08:22.334] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C2.dat
[13:08:22.334] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C3.dat
[13:08:22.334] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C4.dat
[13:08:22.334] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C5.dat
[13:08:22.334] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C6.dat
[13:08:22.334] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C7.dat
[13:08:22.335] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C8.dat
[13:08:22.335] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C9.dat
[13:08:22.335] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C10.dat
[13:08:22.335] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C11.dat
[13:08:22.335] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C12.dat
[13:08:22.336] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C13.dat
[13:08:22.336] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C14.dat
[13:08:22.336] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C15.dat
[13:08:22.581] <TB2> INFO: Expecting 41600 events.
[13:08:25.738] <TB2> INFO: 41600 events read in total (2565ms).
[13:08:25.739] <TB2> INFO: Test took 3399ms.
[13:08:26.196] <TB2> INFO: Expecting 41600 events.
[13:08:29.277] <TB2> INFO: 41600 events read in total (2489ms).
[13:08:29.278] <TB2> INFO: Test took 3326ms.
[13:08:29.746] <TB2> INFO: Expecting 41600 events.
[13:08:32.890] <TB2> INFO: 41600 events read in total (2553ms).
[13:08:32.891] <TB2> INFO: Test took 3399ms.
[13:08:33.114] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:33.203] <TB2> INFO: Expecting 2560 events.
[13:08:34.096] <TB2> INFO: 2560 events read in total (301ms).
[13:08:34.096] <TB2> INFO: Test took 983ms.
[13:08:34.099] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:34.404] <TB2> INFO: Expecting 2560 events.
[13:08:35.297] <TB2> INFO: 2560 events read in total (301ms).
[13:08:35.297] <TB2> INFO: Test took 1198ms.
[13:08:35.301] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:35.605] <TB2> INFO: Expecting 2560 events.
[13:08:36.496] <TB2> INFO: 2560 events read in total (299ms).
[13:08:36.496] <TB2> INFO: Test took 1195ms.
[13:08:36.500] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:36.804] <TB2> INFO: Expecting 2560 events.
[13:08:37.696] <TB2> INFO: 2560 events read in total (300ms).
[13:08:37.696] <TB2> INFO: Test took 1196ms.
[13:08:37.700] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:38.004] <TB2> INFO: Expecting 2560 events.
[13:08:38.894] <TB2> INFO: 2560 events read in total (298ms).
[13:08:38.894] <TB2> INFO: Test took 1194ms.
[13:08:38.897] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:39.202] <TB2> INFO: Expecting 2560 events.
[13:08:40.096] <TB2> INFO: 2560 events read in total (302ms).
[13:08:40.096] <TB2> INFO: Test took 1199ms.
[13:08:40.098] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:40.405] <TB2> INFO: Expecting 2560 events.
[13:08:41.293] <TB2> INFO: 2560 events read in total (297ms).
[13:08:41.293] <TB2> INFO: Test took 1195ms.
[13:08:41.296] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:41.601] <TB2> INFO: Expecting 2560 events.
[13:08:42.488] <TB2> INFO: 2560 events read in total (295ms).
[13:08:42.488] <TB2> INFO: Test took 1192ms.
[13:08:42.492] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:42.797] <TB2> INFO: Expecting 2560 events.
[13:08:43.687] <TB2> INFO: 2560 events read in total (299ms).
[13:08:43.688] <TB2> INFO: Test took 1196ms.
[13:08:43.690] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:43.996] <TB2> INFO: Expecting 2560 events.
[13:08:44.884] <TB2> INFO: 2560 events read in total (296ms).
[13:08:44.885] <TB2> INFO: Test took 1195ms.
[13:08:44.888] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:45.193] <TB2> INFO: Expecting 2560 events.
[13:08:46.072] <TB2> INFO: 2560 events read in total (287ms).
[13:08:46.072] <TB2> INFO: Test took 1184ms.
[13:08:46.075] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:46.380] <TB2> INFO: Expecting 2560 events.
[13:08:47.267] <TB2> INFO: 2560 events read in total (295ms).
[13:08:47.268] <TB2> INFO: Test took 1193ms.
[13:08:47.272] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:47.575] <TB2> INFO: Expecting 2560 events.
[13:08:48.460] <TB2> INFO: 2560 events read in total (293ms).
[13:08:48.460] <TB2> INFO: Test took 1188ms.
[13:08:48.464] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:48.769] <TB2> INFO: Expecting 2560 events.
[13:08:49.652] <TB2> INFO: 2560 events read in total (291ms).
[13:08:49.653] <TB2> INFO: Test took 1189ms.
[13:08:49.655] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:49.960] <TB2> INFO: Expecting 2560 events.
[13:08:50.847] <TB2> INFO: 2560 events read in total (295ms).
[13:08:50.847] <TB2> INFO: Test took 1192ms.
[13:08:50.850] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:51.155] <TB2> INFO: Expecting 2560 events.
[13:08:52.043] <TB2> INFO: 2560 events read in total (296ms).
[13:08:52.043] <TB2> INFO: Test took 1193ms.
[13:08:52.046] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:52.352] <TB2> INFO: Expecting 2560 events.
[13:08:53.232] <TB2> INFO: 2560 events read in total (288ms).
[13:08:53.233] <TB2> INFO: Test took 1187ms.
[13:08:53.236] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:53.541] <TB2> INFO: Expecting 2560 events.
[13:08:54.421] <TB2> INFO: 2560 events read in total (288ms).
[13:08:54.422] <TB2> INFO: Test took 1186ms.
[13:08:54.423] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:54.731] <TB2> INFO: Expecting 2560 events.
[13:08:55.622] <TB2> INFO: 2560 events read in total (299ms).
[13:08:55.622] <TB2> INFO: Test took 1199ms.
[13:08:55.625] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:55.929] <TB2> INFO: Expecting 2560 events.
[13:08:56.819] <TB2> INFO: 2560 events read in total (298ms).
[13:08:56.820] <TB2> INFO: Test took 1195ms.
[13:08:56.823] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:57.128] <TB2> INFO: Expecting 2560 events.
[13:08:58.017] <TB2> INFO: 2560 events read in total (297ms).
[13:08:58.018] <TB2> INFO: Test took 1195ms.
[13:08:58.020] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:58.326] <TB2> INFO: Expecting 2560 events.
[13:08:59.214] <TB2> INFO: 2560 events read in total (296ms).
[13:08:59.215] <TB2> INFO: Test took 1195ms.
[13:08:59.218] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:59.522] <TB2> INFO: Expecting 2560 events.
[13:09:00.410] <TB2> INFO: 2560 events read in total (296ms).
[13:09:00.411] <TB2> INFO: Test took 1193ms.
[13:09:00.412] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:09:00.721] <TB2> INFO: Expecting 2560 events.
[13:09:01.610] <TB2> INFO: 2560 events read in total (298ms).
[13:09:01.611] <TB2> INFO: Test took 1199ms.
[13:09:01.614] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:09:01.918] <TB2> INFO: Expecting 2560 events.
[13:09:02.810] <TB2> INFO: 2560 events read in total (300ms).
[13:09:02.810] <TB2> INFO: Test took 1196ms.
[13:09:02.815] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:09:03.119] <TB2> INFO: Expecting 2560 events.
[13:09:04.011] <TB2> INFO: 2560 events read in total (300ms).
[13:09:04.012] <TB2> INFO: Test took 1197ms.
[13:09:04.015] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:09:04.319] <TB2> INFO: Expecting 2560 events.
[13:09:05.212] <TB2> INFO: 2560 events read in total (301ms).
[13:09:05.212] <TB2> INFO: Test took 1197ms.
[13:09:05.214] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:09:05.520] <TB2> INFO: Expecting 2560 events.
[13:09:06.405] <TB2> INFO: 2560 events read in total (293ms).
[13:09:06.405] <TB2> INFO: Test took 1191ms.
[13:09:06.408] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:09:06.714] <TB2> INFO: Expecting 2560 events.
[13:09:07.607] <TB2> INFO: 2560 events read in total (301ms).
[13:09:07.608] <TB2> INFO: Test took 1200ms.
[13:09:07.610] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:09:07.917] <TB2> INFO: Expecting 2560 events.
[13:09:08.804] <TB2> INFO: 2560 events read in total (296ms).
[13:09:08.805] <TB2> INFO: Test took 1195ms.
[13:09:08.808] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:09:09.112] <TB2> INFO: Expecting 2560 events.
[13:09:09.001] <TB2> INFO: 2560 events read in total (297ms).
[13:09:09.001] <TB2> INFO: Test took 1193ms.
[13:09:10.003] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:09:10.310] <TB2> INFO: Expecting 2560 events.
[13:09:11.201] <TB2> INFO: 2560 events read in total (299ms).
[13:09:11.202] <TB2> INFO: Test took 1199ms.
[13:09:11.663] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 552 seconds
[13:09:11.663] <TB2> INFO: PH scale (per ROC): 42 53 33 48 47 36 34 41 34 45 38 41 37 34 43 38
[13:09:11.663] <TB2> INFO: PH offset (per ROC): 96 122 99 80 107 95 89 106 101 111 93 82 103 93 107 95
[13:09:11.673] <TB2> INFO: Decoding statistics:
[13:09:11.673] <TB2> INFO: General information:
[13:09:11.673] <TB2> INFO: 16bit words read: 127872
[13:09:11.673] <TB2> INFO: valid events total: 20480
[13:09:11.673] <TB2> INFO: empty events: 17984
[13:09:11.673] <TB2> INFO: valid events with pixels: 2496
[13:09:11.673] <TB2> INFO: valid pixel hits: 2496
[13:09:11.673] <TB2> INFO: Event errors: 0
[13:09:11.673] <TB2> INFO: start marker: 0
[13:09:11.673] <TB2> INFO: stop marker: 0
[13:09:11.673] <TB2> INFO: overflow: 0
[13:09:11.673] <TB2> INFO: invalid 5bit words: 0
[13:09:11.673] <TB2> INFO: invalid XOR eye diagram: 0
[13:09:11.673] <TB2> INFO: frame (failed synchr.): 0
[13:09:11.673] <TB2> INFO: idle data (no TBM trl): 0
[13:09:11.673] <TB2> INFO: no data (only TBM hdr): 0
[13:09:11.673] <TB2> INFO: TBM errors: 0
[13:09:11.673] <TB2> INFO: flawed TBM headers: 0
[13:09:11.673] <TB2> INFO: flawed TBM trailers: 0
[13:09:11.673] <TB2> INFO: event ID mismatches: 0
[13:09:11.673] <TB2> INFO: ROC errors: 0
[13:09:11.673] <TB2> INFO: missing ROC header(s): 0
[13:09:11.674] <TB2> INFO: misplaced readback start: 0
[13:09:11.674] <TB2> INFO: Pixel decoding errors: 0
[13:09:11.674] <TB2> INFO: pixel data incomplete: 0
[13:09:11.674] <TB2> INFO: pixel address: 0
[13:09:11.674] <TB2> INFO: pulse height fill bit: 0
[13:09:11.674] <TB2> INFO: buffer corruption: 0
[13:09:11.835] <TB2> INFO: ######################################################################
[13:09:11.835] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:09:11.835] <TB2> INFO: ######################################################################
[13:09:11.849] <TB2> INFO: scanning low vcal = 10
[13:09:12.089] <TB2> INFO: Expecting 41600 events.
[13:09:15.695] <TB2> INFO: 41600 events read in total (3014ms).
[13:09:15.695] <TB2> INFO: Test took 3846ms.
[13:09:15.697] <TB2> INFO: scanning low vcal = 20
[13:09:15.990] <TB2> INFO: Expecting 41600 events.
[13:09:19.590] <TB2> INFO: 41600 events read in total (3009ms).
[13:09:19.591] <TB2> INFO: Test took 3894ms.
[13:09:19.593] <TB2> INFO: scanning low vcal = 30
[13:09:19.884] <TB2> INFO: Expecting 41600 events.
[13:09:23.551] <TB2> INFO: 41600 events read in total (3075ms).
[13:09:23.551] <TB2> INFO: Test took 3958ms.
[13:09:23.555] <TB2> INFO: scanning low vcal = 40
[13:09:23.832] <TB2> INFO: Expecting 41600 events.
[13:09:27.746] <TB2> INFO: 41600 events read in total (3323ms).
[13:09:27.747] <TB2> INFO: Test took 4192ms.
[13:09:27.750] <TB2> INFO: scanning low vcal = 50
[13:09:28.027] <TB2> INFO: Expecting 41600 events.
[13:09:31.954] <TB2> INFO: 41600 events read in total (3336ms).
[13:09:31.955] <TB2> INFO: Test took 4205ms.
[13:09:31.958] <TB2> INFO: scanning low vcal = 60
[13:09:32.234] <TB2> INFO: Expecting 41600 events.
[13:09:36.173] <TB2> INFO: 41600 events read in total (3347ms).
[13:09:36.174] <TB2> INFO: Test took 4216ms.
[13:09:36.177] <TB2> INFO: scanning low vcal = 70
[13:09:36.454] <TB2> INFO: Expecting 41600 events.
[13:09:40.408] <TB2> INFO: 41600 events read in total (3363ms).
[13:09:40.409] <TB2> INFO: Test took 4232ms.
[13:09:40.413] <TB2> INFO: scanning low vcal = 80
[13:09:40.688] <TB2> INFO: Expecting 41600 events.
[13:09:44.690] <TB2> INFO: 41600 events read in total (3410ms).
[13:09:44.690] <TB2> INFO: Test took 4277ms.
[13:09:44.693] <TB2> INFO: scanning low vcal = 90
[13:09:44.970] <TB2> INFO: Expecting 41600 events.
[13:09:48.928] <TB2> INFO: 41600 events read in total (3366ms).
[13:09:48.928] <TB2> INFO: Test took 4235ms.
[13:09:48.933] <TB2> INFO: scanning low vcal = 100
[13:09:49.208] <TB2> INFO: Expecting 41600 events.
[13:09:53.167] <TB2> INFO: 41600 events read in total (3367ms).
[13:09:53.168] <TB2> INFO: Test took 4235ms.
[13:09:53.171] <TB2> INFO: scanning low vcal = 110
[13:09:53.448] <TB2> INFO: Expecting 41600 events.
[13:09:57.488] <TB2> INFO: 41600 events read in total (3449ms).
[13:09:57.489] <TB2> INFO: Test took 4318ms.
[13:09:57.492] <TB2> INFO: scanning low vcal = 120
[13:09:57.768] <TB2> INFO: Expecting 41600 events.
[13:10:01.740] <TB2> INFO: 41600 events read in total (3380ms).
[13:10:01.741] <TB2> INFO: Test took 4249ms.
[13:10:01.744] <TB2> INFO: scanning low vcal = 130
[13:10:02.020] <TB2> INFO: Expecting 41600 events.
[13:10:06.015] <TB2> INFO: 41600 events read in total (3403ms).
[13:10:06.016] <TB2> INFO: Test took 4272ms.
[13:10:06.019] <TB2> INFO: scanning low vcal = 140
[13:10:06.295] <TB2> INFO: Expecting 41600 events.
[13:10:10.298] <TB2> INFO: 41600 events read in total (3411ms).
[13:10:10.298] <TB2> INFO: Test took 4279ms.
[13:10:10.302] <TB2> INFO: scanning low vcal = 150
[13:10:10.578] <TB2> INFO: Expecting 41600 events.
[13:10:14.541] <TB2> INFO: 41600 events read in total (3371ms).
[13:10:14.542] <TB2> INFO: Test took 4240ms.
[13:10:14.545] <TB2> INFO: scanning low vcal = 160
[13:10:14.821] <TB2> INFO: Expecting 41600 events.
[13:10:18.862] <TB2> INFO: 41600 events read in total (3449ms).
[13:10:18.863] <TB2> INFO: Test took 4318ms.
[13:10:18.866] <TB2> INFO: scanning low vcal = 170
[13:10:19.180] <TB2> INFO: Expecting 41600 events.
[13:10:23.224] <TB2> INFO: 41600 events read in total (3452ms).
[13:10:23.225] <TB2> INFO: Test took 4359ms.
[13:10:23.230] <TB2> INFO: scanning low vcal = 180
[13:10:23.504] <TB2> INFO: Expecting 41600 events.
[13:10:27.554] <TB2> INFO: 41600 events read in total (3458ms).
[13:10:27.554] <TB2> INFO: Test took 4323ms.
[13:10:27.557] <TB2> INFO: scanning low vcal = 190
[13:10:27.834] <TB2> INFO: Expecting 41600 events.
[13:10:31.907] <TB2> INFO: 41600 events read in total (3482ms).
[13:10:31.908] <TB2> INFO: Test took 4351ms.
[13:10:31.911] <TB2> INFO: scanning low vcal = 200
[13:10:32.226] <TB2> INFO: Expecting 41600 events.
[13:10:36.216] <TB2> INFO: 41600 events read in total (3398ms).
[13:10:36.217] <TB2> INFO: Test took 4306ms.
[13:10:36.220] <TB2> INFO: scanning low vcal = 210
[13:10:36.496] <TB2> INFO: Expecting 41600 events.
[13:10:40.481] <TB2> INFO: 41600 events read in total (3393ms).
[13:10:40.482] <TB2> INFO: Test took 4262ms.
[13:10:40.485] <TB2> INFO: scanning low vcal = 220
[13:10:40.762] <TB2> INFO: Expecting 41600 events.
[13:10:44.778] <TB2> INFO: 41600 events read in total (3425ms).
[13:10:44.779] <TB2> INFO: Test took 4294ms.
[13:10:44.781] <TB2> INFO: scanning low vcal = 230
[13:10:45.061] <TB2> INFO: Expecting 41600 events.
[13:10:49.109] <TB2> INFO: 41600 events read in total (3456ms).
[13:10:49.109] <TB2> INFO: Test took 4327ms.
[13:10:49.113] <TB2> INFO: scanning low vcal = 240
[13:10:49.427] <TB2> INFO: Expecting 41600 events.
[13:10:53.486] <TB2> INFO: 41600 events read in total (3468ms).
[13:10:53.487] <TB2> INFO: Test took 4374ms.
[13:10:53.490] <TB2> INFO: scanning low vcal = 250
[13:10:53.806] <TB2> INFO: Expecting 41600 events.
[13:10:57.800] <TB2> INFO: 41600 events read in total (3403ms).
[13:10:57.801] <TB2> INFO: Test took 4311ms.
[13:10:57.805] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[13:10:58.081] <TB2> INFO: Expecting 41600 events.
[13:11:02.170] <TB2> INFO: 41600 events read in total (3497ms).
[13:11:02.171] <TB2> INFO: Test took 4366ms.
[13:11:02.174] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[13:11:02.490] <TB2> INFO: Expecting 41600 events.
[13:11:06.587] <TB2> INFO: 41600 events read in total (3505ms).
[13:11:06.588] <TB2> INFO: Test took 4414ms.
[13:11:06.591] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[13:11:06.907] <TB2> INFO: Expecting 41600 events.
[13:11:10.884] <TB2> INFO: 41600 events read in total (3386ms).
[13:11:10.885] <TB2> INFO: Test took 4294ms.
[13:11:10.888] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[13:11:11.164] <TB2> INFO: Expecting 41600 events.
[13:11:15.167] <TB2> INFO: 41600 events read in total (3411ms).
[13:11:15.168] <TB2> INFO: Test took 4280ms.
[13:11:15.171] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:11:15.487] <TB2> INFO: Expecting 41600 events.
[13:11:19.470] <TB2> INFO: 41600 events read in total (3392ms).
[13:11:19.471] <TB2> INFO: Test took 4300ms.
[13:11:19.860] <TB2> INFO: PixTestGainPedestal::measure() done
[13:11:52.730] <TB2> INFO: PixTestGainPedestal::fit() done
[13:11:52.730] <TB2> INFO: non-linearity mean: 0.941 0.984 0.961 0.963 0.976 0.944 0.994 0.940 0.935 0.964 0.937 0.943 0.949 0.943 0.939 0.936
[13:11:52.730] <TB2> INFO: non-linearity RMS: 0.078 0.004 0.145 0.026 0.008 0.080 0.167 0.075 0.095 0.052 0.077 0.080 0.156 0.140 0.092 0.116
[13:11:52.730] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C0.dat
[13:11:52.745] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C1.dat
[13:11:52.758] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C2.dat
[13:11:52.771] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C3.dat
[13:11:52.784] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C4.dat
[13:11:52.797] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C5.dat
[13:11:52.810] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C6.dat
[13:11:52.823] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C7.dat
[13:11:52.836] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C8.dat
[13:11:52.849] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C9.dat
[13:11:52.862] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C10.dat
[13:11:52.875] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C11.dat
[13:11:52.888] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C12.dat
[13:11:52.901] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C13.dat
[13:11:52.913] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C14.dat
[13:11:52.927] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C15.dat
[13:11:52.939] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 161 seconds
[13:11:52.939] <TB2> INFO: Decoding statistics:
[13:11:52.939] <TB2> INFO: General information:
[13:11:52.940] <TB2> INFO: 16bit words read: 3192594
[13:11:52.940] <TB2> INFO: valid events total: 332800
[13:11:52.940] <TB2> INFO: empty events: 3133
[13:11:52.940] <TB2> INFO: valid events with pixels: 329667
[13:11:52.940] <TB2> INFO: valid pixel hits: 597897
[13:11:52.940] <TB2> INFO: Event errors: 0
[13:11:52.940] <TB2> INFO: start marker: 0
[13:11:52.940] <TB2> INFO: stop marker: 0
[13:11:52.940] <TB2> INFO: overflow: 0
[13:11:52.940] <TB2> INFO: invalid 5bit words: 0
[13:11:52.940] <TB2> INFO: invalid XOR eye diagram: 0
[13:11:52.940] <TB2> INFO: frame (failed synchr.): 0
[13:11:52.940] <TB2> INFO: idle data (no TBM trl): 0
[13:11:52.940] <TB2> INFO: no data (only TBM hdr): 0
[13:11:52.940] <TB2> INFO: TBM errors: 0
[13:11:52.940] <TB2> INFO: flawed TBM headers: 0
[13:11:52.940] <TB2> INFO: flawed TBM trailers: 0
[13:11:52.940] <TB2> INFO: event ID mismatches: 0
[13:11:52.940] <TB2> INFO: ROC errors: 0
[13:11:52.940] <TB2> INFO: missing ROC header(s): 0
[13:11:52.940] <TB2> INFO: misplaced readback start: 0
[13:11:52.940] <TB2> INFO: Pixel decoding errors: 0
[13:11:52.940] <TB2> INFO: pixel data incomplete: 0
[13:11:52.940] <TB2> INFO: pixel address: 0
[13:11:52.940] <TB2> INFO: pulse height fill bit: 0
[13:11:52.940] <TB2> INFO: buffer corruption: 0
[13:11:52.955] <TB2> INFO: Decoding statistics:
[13:11:52.955] <TB2> INFO: General information:
[13:11:52.955] <TB2> INFO: 16bit words read: 3322002
[13:11:52.955] <TB2> INFO: valid events total: 353536
[13:11:52.955] <TB2> INFO: empty events: 21373
[13:11:52.955] <TB2> INFO: valid events with pixels: 332163
[13:11:52.955] <TB2> INFO: valid pixel hits: 600393
[13:11:52.955] <TB2> INFO: Event errors: 0
[13:11:52.955] <TB2> INFO: start marker: 0
[13:11:52.955] <TB2> INFO: stop marker: 0
[13:11:52.955] <TB2> INFO: overflow: 0
[13:11:52.955] <TB2> INFO: invalid 5bit words: 0
[13:11:52.955] <TB2> INFO: invalid XOR eye diagram: 0
[13:11:52.955] <TB2> INFO: frame (failed synchr.): 0
[13:11:52.955] <TB2> INFO: idle data (no TBM trl): 0
[13:11:52.955] <TB2> INFO: no data (only TBM hdr): 0
[13:11:52.955] <TB2> INFO: TBM errors: 0
[13:11:52.955] <TB2> INFO: flawed TBM headers: 0
[13:11:52.955] <TB2> INFO: flawed TBM trailers: 0
[13:11:52.955] <TB2> INFO: event ID mismatches: 0
[13:11:52.955] <TB2> INFO: ROC errors: 0
[13:11:52.955] <TB2> INFO: missing ROC header(s): 0
[13:11:52.955] <TB2> INFO: misplaced readback start: 0
[13:11:52.955] <TB2> INFO: Pixel decoding errors: 0
[13:11:52.955] <TB2> INFO: pixel data incomplete: 0
[13:11:52.955] <TB2> INFO: pixel address: 0
[13:11:52.955] <TB2> INFO: pulse height fill bit: 0
[13:11:52.955] <TB2> INFO: buffer corruption: 0
[13:11:52.955] <TB2> INFO: enter test to run
[13:11:52.955] <TB2> INFO: test: exit no parameter change
[13:11:53.051] <TB2> QUIET: Connection to board 149 closed.
[13:11:53.059] <TB2> INFO: pXar: this is the end, my friend