[10:10:34.779] <TB2> INFO: *** Welcome to pxar ***
[10:10:34.780] <TB2> INFO: *** Today: 2016/11/14
[10:10:34.786] <TB2> INFO: *** Version: c8ba-dirty
[10:10:34.786] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C15.dat
[10:10:34.787] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//tbmParameters_C1b.dat
[10:10:34.787] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//defaultMaskFile.dat
[10:10:34.787] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters_C15.dat
[10:10:34.884] <TB2> INFO: clk: 4
[10:10:34.884] <TB2> INFO: ctr: 4
[10:10:34.884] <TB2> INFO: sda: 19
[10:10:34.884] <TB2> INFO: tin: 9
[10:10:34.884] <TB2> INFO: level: 15
[10:10:34.884] <TB2> INFO: triggerdelay: 0
[10:10:34.884] <TB2> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[10:10:34.884] <TB2> INFO: Log level: INFO
[10:10:34.895] <TB2> INFO: Found DTB DTB_WWXUD2
[10:10:34.907] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[10:10:34.909] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[10:10:34.911] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[10:10:36.404] <TB2> INFO: DUT info:
[10:10:36.404] <TB2> INFO: The DUT currently contains the following objects:
[10:10:36.404] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[10:10:36.404] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:10:36.404] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:10:36.404] <TB2> INFO: TBM Core alpha (2): 7 registers set
[10:10:36.404] <TB2> INFO: TBM Core beta (3): 7 registers set
[10:10:36.404] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[10:10:36.404] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[10:10:36.404] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[10:10:36.404] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[10:10:36.404] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[10:10:36.404] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[10:10:36.404] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[10:10:36.404] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[10:10:36.404] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[10:10:36.404] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[10:10:36.404] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[10:10:36.404] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[10:10:36.405] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[10:10:36.405] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[10:10:36.405] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[10:10:36.405] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[10:10:36.405] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[10:10:36.805] <TB2> INFO: enter 'restricted' command line mode
[10:10:36.806] <TB2> INFO: enter test to run
[10:10:36.806] <TB2> INFO: test: pretest no parameter change
[10:10:36.806] <TB2> INFO: running: pretest
[10:10:36.811] <TB2> INFO: ######################################################################
[10:10:36.811] <TB2> INFO: PixTestPretest::doTest()
[10:10:36.811] <TB2> INFO: ######################################################################
[10:10:36.813] <TB2> INFO: ----------------------------------------------------------------------
[10:10:36.813] <TB2> INFO: PixTestPretest::programROC()
[10:10:36.813] <TB2> INFO: ----------------------------------------------------------------------
[10:10:54.827] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[10:10:54.827] <TB2> INFO: IA differences per ROC: 18.5 19.3 19.3 16.9 17.7 18.5 17.7 19.3 16.9 17.7 17.7 16.1 19.3 16.9 18.5 20.1
[10:10:54.889] <TB2> INFO: ----------------------------------------------------------------------
[10:10:54.889] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[10:10:54.889] <TB2> INFO: ----------------------------------------------------------------------
[10:11:16.189] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 388.3 mA = 24.2687 mA/ROC
[10:11:16.189] <TB2> INFO: i(loss) [mA/ROC]: 19.3 19.3 19.3 17.7 18.5 19.3 19.3 19.3 20.1 20.1 20.1 19.3 18.5 20.1 18.5 18.5
[10:11:16.224] <TB2> INFO: ----------------------------------------------------------------------
[10:11:16.224] <TB2> INFO: PixTestPretest::findTiming()
[10:11:16.224] <TB2> INFO: ----------------------------------------------------------------------
[10:11:16.224] <TB2> INFO: PixTestCmd::init()
[10:11:16.803] <TB2> WARNING: Not unmasking DUT, not setting Calibrate bits!
[10:11:48.476] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[10:11:48.476] <TB2> INFO: (success/tries = 100/100), width = 3
[10:11:49.981] <TB2> INFO: ----------------------------------------------------------------------
[10:11:49.981] <TB2> INFO: PixTestPretest::findWorkingPixel()
[10:11:49.981] <TB2> INFO: ----------------------------------------------------------------------
[10:11:50.075] <TB2> INFO: Expecting 231680 events.
[10:11:59.913] <TB2> INFO: 231680 events read in total (9246ms).
[10:11:59.928] <TB2> INFO: Test took 9944ms.
[10:12:00.183] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[10:12:00.212] <TB2> INFO: ----------------------------------------------------------------------
[10:12:00.212] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[10:12:00.212] <TB2> INFO: ----------------------------------------------------------------------
[10:12:00.306] <TB2> INFO: Expecting 231680 events.
[10:12:10.206] <TB2> INFO: 231680 events read in total (9308ms).
[10:12:10.214] <TB2> INFO: Test took 9997ms.
[10:12:10.481] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[10:12:10.481] <TB2> INFO: CalDel: 96 95 121 114 106 122 115 111 134 107 124 124 109 87 108 125
[10:12:10.481] <TB2> INFO: VthrComp: 51 52 56 51 51 51 51 51 51 51 51 51 51 51 53 51
[10:12:10.485] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C0.dat
[10:12:10.485] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C1.dat
[10:12:10.486] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C2.dat
[10:12:10.486] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C3.dat
[10:12:10.486] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C4.dat
[10:12:10.486] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C5.dat
[10:12:10.486] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C6.dat
[10:12:10.487] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C7.dat
[10:12:10.487] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C8.dat
[10:12:10.487] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C9.dat
[10:12:10.487] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C10.dat
[10:12:10.487] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C11.dat
[10:12:10.487] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C12.dat
[10:12:10.487] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C13.dat
[10:12:10.488] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C14.dat
[10:12:10.488] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters_C15.dat
[10:12:10.488] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//tbmParameters_C0a.dat
[10:12:10.488] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//tbmParameters_C0b.dat
[10:12:10.488] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//tbmParameters_C1a.dat
[10:12:10.488] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//tbmParameters_C1b.dat
[10:12:10.488] <TB2> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[10:12:10.544] <TB2> INFO: enter test to run
[10:12:10.544] <TB2> INFO: test: FullTest no parameter change
[10:12:10.544] <TB2> INFO: running: fulltest
[10:12:10.544] <TB2> INFO: ######################################################################
[10:12:10.544] <TB2> INFO: PixTestFullTest::doTest()
[10:12:10.544] <TB2> INFO: ######################################################################
[10:12:10.545] <TB2> INFO: ######################################################################
[10:12:10.545] <TB2> INFO: PixTestAlive::doTest()
[10:12:10.545] <TB2> INFO: ######################################################################
[10:12:10.547] <TB2> INFO: ----------------------------------------------------------------------
[10:12:10.547] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:12:10.547] <TB2> INFO: ----------------------------------------------------------------------
[10:12:10.786] <TB2> INFO: Expecting 41600 events.
[10:12:14.424] <TB2> INFO: 41600 events read in total (3047ms).
[10:12:14.424] <TB2> INFO: Test took 3876ms.
[10:12:14.659] <TB2> INFO: PixTestAlive::aliveTest() done
[10:12:14.659] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0
[10:12:14.660] <TB2> INFO: ----------------------------------------------------------------------
[10:12:14.660] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:12:14.660] <TB2> INFO: ----------------------------------------------------------------------
[10:12:14.908] <TB2> INFO: Expecting 41600 events.
[10:12:17.889] <TB2> INFO: 41600 events read in total (2389ms).
[10:12:17.889] <TB2> INFO: Test took 3227ms.
[10:12:17.890] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[10:12:18.128] <TB2> INFO: PixTestAlive::maskTest() done
[10:12:18.129] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:12:18.130] <TB2> INFO: ----------------------------------------------------------------------
[10:12:18.130] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:12:18.130] <TB2> INFO: ----------------------------------------------------------------------
[10:12:18.373] <TB2> INFO: Expecting 41600 events.
[10:12:21.905] <TB2> INFO: 41600 events read in total (2941ms).
[10:12:21.905] <TB2> INFO: Test took 3773ms.
[10:12:22.139] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[10:12:22.139] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:12:22.140] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[10:12:22.140] <TB2> INFO: Decoding statistics:
[10:12:22.140] <TB2> INFO: General information:
[10:12:22.140] <TB2> INFO: 16bit words read: 0
[10:12:22.140] <TB2> INFO: valid events total: 0
[10:12:22.140] <TB2> INFO: empty events: 0
[10:12:22.140] <TB2> INFO: valid events with pixels: 0
[10:12:22.140] <TB2> INFO: valid pixel hits: 0
[10:12:22.140] <TB2> INFO: Event errors: 0
[10:12:22.140] <TB2> INFO: start marker: 0
[10:12:22.140] <TB2> INFO: stop marker: 0
[10:12:22.140] <TB2> INFO: overflow: 0
[10:12:22.140] <TB2> INFO: invalid 5bit words: 0
[10:12:22.140] <TB2> INFO: invalid XOR eye diagram: 0
[10:12:22.140] <TB2> INFO: frame (failed synchr.): 0
[10:12:22.140] <TB2> INFO: idle data (no TBM trl): 0
[10:12:22.140] <TB2> INFO: no data (only TBM hdr): 0
[10:12:22.140] <TB2> INFO: TBM errors: 0
[10:12:22.140] <TB2> INFO: flawed TBM headers: 0
[10:12:22.140] <TB2> INFO: flawed TBM trailers: 0
[10:12:22.140] <TB2> INFO: event ID mismatches: 0
[10:12:22.140] <TB2> INFO: ROC errors: 0
[10:12:22.140] <TB2> INFO: missing ROC header(s): 0
[10:12:22.140] <TB2> INFO: misplaced readback start: 0
[10:12:22.140] <TB2> INFO: Pixel decoding errors: 0
[10:12:22.140] <TB2> INFO: pixel data incomplete: 0
[10:12:22.140] <TB2> INFO: pixel address: 0
[10:12:22.140] <TB2> INFO: pulse height fill bit: 0
[10:12:22.140] <TB2> INFO: buffer corruption: 0
[10:12:22.148] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C15.dat
[10:12:22.148] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr_C15.dat
[10:12:22.148] <TB2> ERROR: <ConfigParameters.cc/readGainPedestalParameters:L1005> cannot open /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr_C0.dat for reading PH calibration constants
[10:12:22.148] <TB2> INFO: ######################################################################
[10:12:22.148] <TB2> INFO: PixTestReadback::doTest()
[10:12:22.148] <TB2> INFO: ######################################################################
[10:12:22.148] <TB2> INFO: ----------------------------------------------------------------------
[10:12:22.148] <TB2> INFO: PixTestReadback::CalibrateVd()
[10:12:22.148] <TB2> INFO: ----------------------------------------------------------------------
[10:12:32.107] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C0.dat
[10:12:32.107] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C1.dat
[10:12:32.107] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C2.dat
[10:12:32.107] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C3.dat
[10:12:32.108] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C4.dat
[10:12:32.108] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C5.dat
[10:12:32.108] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C6.dat
[10:12:32.108] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C7.dat
[10:12:32.108] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C8.dat
[10:12:32.108] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C9.dat
[10:12:32.108] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C10.dat
[10:12:32.108] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C11.dat
[10:12:32.108] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C12.dat
[10:12:32.108] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C13.dat
[10:12:32.108] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C14.dat
[10:12:32.108] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C15.dat
[10:12:32.136] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:12:32.136] <TB2> INFO: ----------------------------------------------------------------------
[10:12:32.136] <TB2> INFO: PixTestReadback::CalibrateVa()
[10:12:32.136] <TB2> INFO: ----------------------------------------------------------------------
[10:12:42.071] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C0.dat
[10:12:42.071] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C1.dat
[10:12:42.071] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C2.dat
[10:12:42.071] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C3.dat
[10:12:42.071] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C4.dat
[10:12:42.071] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C5.dat
[10:12:42.071] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C6.dat
[10:12:42.071] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C7.dat
[10:12:42.071] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C8.dat
[10:12:42.071] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C9.dat
[10:12:42.072] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C10.dat
[10:12:42.072] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C11.dat
[10:12:42.072] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C12.dat
[10:12:42.072] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C13.dat
[10:12:42.072] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C14.dat
[10:12:42.072] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C15.dat
[10:12:42.105] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:12:42.105] <TB2> INFO: ----------------------------------------------------------------------
[10:12:42.105] <TB2> INFO: PixTestReadback::readbackVbg()
[10:12:42.105] <TB2> INFO: ----------------------------------------------------------------------
[10:12:49.778] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:12:49.778] <TB2> INFO: ----------------------------------------------------------------------
[10:12:49.778] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[10:12:49.778] <TB2> INFO: ----------------------------------------------------------------------
[10:12:49.778] <TB2> INFO: Vbg will be calibrated using Vd calibration
[10:12:49.778] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 153.1calibrated Vbg = 1.18475 :::*/*/*/*/
[10:12:49.778] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 150.5calibrated Vbg = 1.18207 :::*/*/*/*/
[10:12:49.778] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 162.5calibrated Vbg = 1.18066 :::*/*/*/*/
[10:12:49.778] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 149.4calibrated Vbg = 1.18315 :::*/*/*/*/
[10:12:49.778] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 158.7calibrated Vbg = 1.18017 :::*/*/*/*/
[10:12:49.778] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 153.9calibrated Vbg = 1.19267 :::*/*/*/*/
[10:12:49.778] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 158.1calibrated Vbg = 1.19198 :::*/*/*/*/
[10:12:49.778] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 164.5calibrated Vbg = 1.18766 :::*/*/*/*/
[10:12:49.778] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 156.1calibrated Vbg = 1.19004 :::*/*/*/*/
[10:12:49.778] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 150.9calibrated Vbg = 1.18347 :::*/*/*/*/
[10:12:49.778] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 156.5calibrated Vbg = 1.17998 :::*/*/*/*/
[10:12:49.778] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 158.6calibrated Vbg = 1.1773 :::*/*/*/*/
[10:12:49.778] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 155.9calibrated Vbg = 1.18259 :::*/*/*/*/
[10:12:49.778] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 161.2calibrated Vbg = 1.18306 :::*/*/*/*/
[10:12:49.778] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 153.8calibrated Vbg = 1.18006 :::*/*/*/*/
[10:12:49.778] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 146.7calibrated Vbg = 1.18344 :::*/*/*/*/
[10:12:49.781] <TB2> INFO: ----------------------------------------------------------------------
[10:12:49.781] <TB2> INFO: PixTestReadback::CalibrateIa()
[10:12:49.781] <TB2> INFO: ----------------------------------------------------------------------
[10:15:30.632] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C0.dat
[10:15:30.632] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C1.dat
[10:15:30.632] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C2.dat
[10:15:30.632] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C3.dat
[10:15:30.632] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C4.dat
[10:15:30.632] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C5.dat
[10:15:30.632] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C6.dat
[10:15:30.632] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C7.dat
[10:15:30.632] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C8.dat
[10:15:30.632] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C9.dat
[10:15:30.632] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C10.dat
[10:15:30.632] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C11.dat
[10:15:30.632] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C12.dat
[10:15:30.632] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C13.dat
[10:15:30.632] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C14.dat
[10:15:30.632] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//readbackCal_C15.dat
[10:15:30.665] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:15:30.666] <TB2> INFO: PixTestReadback::doTest() done
[10:15:30.667] <TB2> INFO: Decoding statistics:
[10:15:30.667] <TB2> INFO: General information:
[10:15:30.667] <TB2> INFO: 16bit words read: 1536
[10:15:30.667] <TB2> INFO: valid events total: 256
[10:15:30.667] <TB2> INFO: empty events: 256
[10:15:30.667] <TB2> INFO: valid events with pixels: 0
[10:15:30.667] <TB2> INFO: valid pixel hits: 0
[10:15:30.667] <TB2> INFO: Event errors: 0
[10:15:30.667] <TB2> INFO: start marker: 0
[10:15:30.667] <TB2> INFO: stop marker: 0
[10:15:30.667] <TB2> INFO: overflow: 0
[10:15:30.667] <TB2> INFO: invalid 5bit words: 0
[10:15:30.667] <TB2> INFO: invalid XOR eye diagram: 0
[10:15:30.667] <TB2> INFO: frame (failed synchr.): 0
[10:15:30.667] <TB2> INFO: idle data (no TBM trl): 0
[10:15:30.667] <TB2> INFO: no data (only TBM hdr): 0
[10:15:30.667] <TB2> INFO: TBM errors: 0
[10:15:30.667] <TB2> INFO: flawed TBM headers: 0
[10:15:30.667] <TB2> INFO: flawed TBM trailers: 0
[10:15:30.667] <TB2> INFO: event ID mismatches: 0
[10:15:30.667] <TB2> INFO: ROC errors: 0
[10:15:30.667] <TB2> INFO: missing ROC header(s): 0
[10:15:30.667] <TB2> INFO: misplaced readback start: 0
[10:15:30.667] <TB2> INFO: Pixel decoding errors: 0
[10:15:30.667] <TB2> INFO: pixel data incomplete: 0
[10:15:30.667] <TB2> INFO: pixel address: 0
[10:15:30.667] <TB2> INFO: pulse height fill bit: 0
[10:15:30.667] <TB2> INFO: buffer corruption: 0
[10:15:30.733] <TB2> INFO: ######################################################################
[10:15:30.734] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[10:15:30.734] <TB2> INFO: ######################################################################
[10:15:30.737] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[10:15:30.759] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[10:15:30.759] <TB2> INFO: run 1 of 1
[10:15:30.002] <TB2> INFO: Expecting 3120000 events.
[10:16:02.408] <TB2> INFO: 659730 events read in total (30814ms).
[10:16:14.495] <TB2> ERROR: <datapipe.cc/CheckEventID:L485> Channel 0 Event ID mismatch: local ID (147) != TBM ID (129)
[10:16:14.636] <TB2> ERROR: <hal.cc/daqAllEvents:L1697> Channels report mismatching event numbers: 147 147 129 147 147 147 147 147
[10:16:14.636] <TB2> ERROR: <datapipe.cc/CheckEventID:L485> Channel 0 Event ID mismatch: local ID (130) != TBM ID (148)
[10:16:14.636] <TB2> ERROR: <datapipe.cc/Read:L170> Dumping the flawed event +- 3 events:
[10:16:14.636] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a097 8000 4030 252 2fef 4030 252 2fef e022 c000
[10:16:14.636] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a091 80b1 4030 252 2fef 4030 252 2fef e022 c000
[10:16:14.636] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a092 80c0 4031 252 2fef 4811 252 2fef e022 c000
[10:16:14.636] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a081 80b1 4810 4810 2fef 4830 252 2fef e022 c000
[10:16:14.636] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a094 8040 4030 252 2fef 4031 252 2fef e022 c000
[10:16:14.636] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a095 80b1 4030 252 2fef 4030 252 2fef e022 c000
[10:16:14.636] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a096 80c0 4030 252 2fef 4030 252 2fef e022 c000
[10:16:32.723] <TB2> INFO: 1316425 events read in total (61130ms).
[10:16:44.774] <TB2> ERROR: <datapipe.cc/CheckEventID:L485> Channel 0 Event ID mismatch: local ID (202) != TBM ID (129)
[10:16:44.916] <TB2> ERROR: <hal.cc/daqAllEvents:L1697> Channels report mismatching event numbers: 202 202 129 202 202 202 202 202
[10:16:44.916] <TB2> ERROR: <datapipe.cc/CheckEventID:L485> Channel 0 Event ID mismatch: local ID (130) != TBM ID (203)
[10:16:44.918] <TB2> ERROR: <datapipe.cc/Read:L170> Dumping the flawed event +- 3 events:
[10:16:44.918] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a0ce 80c0 4810 4810 e022 c000
[10:16:44.918] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a0c8 8040 4810 4810 e022 c000
[10:16:44.918] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a0c9 80b1 4810 4810 e022 c000
[10:16:44.918] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a081 80b1 4810 4810 e022 c000
[10:16:44.918] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a0cb 8000 4811 4811 e022 c000
[10:16:44.918] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a0cc 8040 4810 4810 e022 c000
[10:16:44.918] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a0cd 80b1 4810 4810 e022 c000
[10:17:02.761] <TB2> INFO: 1970790 events read in total (91167ms).
[10:17:33.027] <TB2> INFO: 2622305 events read in total (121433ms).
[10:17:42.241] <TB2> ERROR: <datapipe.cc/CheckEventID:L485> Channel 0 Event ID mismatch: local ID (226) != TBM ID (231)
[10:17:42.379] <TB2> ERROR: <hal.cc/daqAllEvents:L1697> Channels report mismatching event numbers: 226 226 231 226 226 226 226 226
[10:17:42.379] <TB2> ERROR: <datapipe.cc/CheckEventID:L485> Channel 0 Event ID mismatch: local ID (232) != TBM ID (227)
[10:17:42.380] <TB2> ERROR: <datapipe.cc/Read:L170> Dumping the flawed event +- 3 events:
[10:17:42.380] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a0e6 80c0 4810 a6e 21ef 4810 e022 c000
[10:17:42.380] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a0e0 8040 4813 a6e 21ef 4813 e022 c000
[10:17:42.380] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a0e1 80b1 4810 a6e 21ef 4810 e022 c000
[10:17:42.380] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a0e7 8000 4810 810 21ef 4811 e022 c000
[10:17:42.380] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a0e3 8000 4830 4830 e022 c000
[10:17:42.380] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a0e4 8040 4810 a6e 21ef 4811 e022 c000
[10:17:42.380] <TB2> ERROR: <datapipe.cc/Read:L172> ====== 0 ====== a0e5 80b1 4810 a6e 21ef 4810 a6e 21ef e022 c000
[10:17:56.123] <TB2> INFO: 3120000 events read in total (144529ms).
[10:17:56.244] <TB2> INFO: Test took 145486ms.
[10:18:21.493] <TB2> INFO: PixTestBBMap::doTest() done with 1 decoding errors: , duration: 170 seconds
[10:18:21.493] <TB2> INFO: number of dead bumps (per ROC): 0 0 1 1 0 4 0 1 1 0 1 0 0 0 0 1
[10:18:21.493] <TB2> INFO: separation cut (per ROC): 104 114 108 88 95 95 108 100 91 105 98 86 89 110 99 95
[10:18:21.493] <TB2> INFO: Decoding statistics:
[10:18:21.493] <TB2> INFO: General information:
[10:18:21.493] <TB2> INFO: 16bit words read: 0
[10:18:21.493] <TB2> INFO: valid events total: 0
[10:18:21.493] <TB2> INFO: empty events: 0
[10:18:21.493] <TB2> INFO: valid events with pixels: 0
[10:18:21.493] <TB2> INFO: valid pixel hits: 0
[10:18:21.493] <TB2> INFO: Event errors: 0
[10:18:21.493] <TB2> INFO: start marker: 0
[10:18:21.493] <TB2> INFO: stop marker: 0
[10:18:21.493] <TB2> INFO: overflow: 0
[10:18:21.493] <TB2> INFO: invalid 5bit words: 0
[10:18:21.493] <TB2> INFO: invalid XOR eye diagram: 0
[10:18:21.493] <TB2> INFO: frame (failed synchr.): 0
[10:18:21.493] <TB2> INFO: idle data (no TBM trl): 0
[10:18:21.493] <TB2> INFO: no data (only TBM hdr): 0
[10:18:21.493] <TB2> INFO: TBM errors: 0
[10:18:21.493] <TB2> INFO: flawed TBM headers: 0
[10:18:21.493] <TB2> INFO: flawed TBM trailers: 0
[10:18:21.493] <TB2> INFO: event ID mismatches: 0
[10:18:21.493] <TB2> INFO: ROC errors: 0
[10:18:21.493] <TB2> INFO: missing ROC header(s): 0
[10:18:21.493] <TB2> INFO: misplaced readback start: 0
[10:18:21.493] <TB2> INFO: Pixel decoding errors: 0
[10:18:21.493] <TB2> INFO: pixel data incomplete: 0
[10:18:21.493] <TB2> INFO: pixel address: 0
[10:18:21.493] <TB2> INFO: pulse height fill bit: 0
[10:18:21.493] <TB2> INFO: buffer corruption: 0
[10:18:21.529] <TB2> INFO: ######################################################################
[10:18:21.529] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[10:18:21.529] <TB2> INFO: ######################################################################
[10:18:21.529] <TB2> INFO: ----------------------------------------------------------------------
[10:18:21.529] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[10:18:21.529] <TB2> INFO: ----------------------------------------------------------------------
[10:18:21.529] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[10:18:21.543] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[10:18:21.543] <TB2> INFO: run 1 of 1
[10:18:21.783] <TB2> INFO: Expecting 36608000 events.
[10:18:45.733] <TB2> INFO: 678100 events read in total (23349ms).
[10:19:08.691] <TB2> INFO: 1342550 events read in total (46307ms).
[10:19:31.570] <TB2> INFO: 2005300 events read in total (69186ms).
[10:19:54.914] <TB2> INFO: 2667250 events read in total (92530ms).
[10:20:18.277] <TB2> INFO: 3331350 events read in total (115893ms).
[10:20:41.423] <TB2> INFO: 3992900 events read in total (139039ms).
[10:21:04.933] <TB2> INFO: 4655750 events read in total (162549ms).
[10:21:28.071] <TB2> INFO: 5317850 events read in total (185687ms).
[10:21:51.275] <TB2> INFO: 5981600 events read in total (208891ms).
[10:22:14.717] <TB2> INFO: 6644750 events read in total (232333ms).
[10:22:37.791] <TB2> INFO: 7307050 events read in total (255407ms).
[10:23:00.920] <TB2> INFO: 7969200 events read in total (278536ms).
[10:23:23.821] <TB2> INFO: 8631050 events read in total (301437ms).
[10:23:46.819] <TB2> INFO: 9296050 events read in total (324435ms).
[10:24:10.139] <TB2> INFO: 9958100 events read in total (347755ms).
[10:24:33.327] <TB2> INFO: 10620600 events read in total (370943ms).
[10:24:56.004] <TB2> INFO: 11279700 events read in total (393620ms).
[10:25:18.913] <TB2> INFO: 11941800 events read in total (416529ms).
[10:25:41.924] <TB2> INFO: 12603450 events read in total (439540ms).
[10:26:04.960] <TB2> INFO: 13266200 events read in total (462576ms).
[10:26:27.962] <TB2> INFO: 13926750 events read in total (485578ms).
[10:26:51.449] <TB2> INFO: 14588700 events read in total (509065ms).
[10:27:14.628] <TB2> INFO: 15249700 events read in total (532244ms).
[10:27:37.977] <TB2> INFO: 15912450 events read in total (555593ms).
[10:28:00.959] <TB2> INFO: 16574650 events read in total (578575ms).
[10:28:23.948] <TB2> INFO: 17235450 events read in total (601564ms).
[10:28:46.852] <TB2> INFO: 17896600 events read in total (624468ms).
[10:29:09.980] <TB2> INFO: 18556100 events read in total (647596ms).
[10:29:32.955] <TB2> INFO: 19213300 events read in total (670571ms).
[10:29:55.810] <TB2> INFO: 19870150 events read in total (693426ms).
[10:30:18.773] <TB2> INFO: 20527850 events read in total (716389ms).
[10:30:42.206] <TB2> INFO: 21185250 events read in total (739822ms).
[10:31:05.197] <TB2> INFO: 21842900 events read in total (762813ms).
[10:31:28.366] <TB2> INFO: 22499400 events read in total (785982ms).
[10:31:51.312] <TB2> INFO: 23158850 events read in total (808928ms).
[10:32:14.070] <TB2> INFO: 23815550 events read in total (831686ms).
[10:32:36.820] <TB2> INFO: 24472500 events read in total (854436ms).
[10:33:00.281] <TB2> INFO: 25130500 events read in total (877897ms).
[10:33:23.095] <TB2> INFO: 25789450 events read in total (900711ms).
[10:33:46.125] <TB2> INFO: 26446950 events read in total (923741ms).
[10:34:09.053] <TB2> INFO: 27105900 events read in total (946669ms).
[10:34:32.272] <TB2> INFO: 27764700 events read in total (969888ms).
[10:34:55.293] <TB2> INFO: 28423200 events read in total (992909ms).
[10:35:18.014] <TB2> INFO: 29081500 events read in total (1015630ms).
[10:35:41.079] <TB2> INFO: 29737900 events read in total (1038695ms).
[10:36:03.932] <TB2> INFO: 30394100 events read in total (1061548ms).
[10:36:26.886] <TB2> INFO: 31051050 events read in total (1084502ms).
[10:36:49.791] <TB2> INFO: 31710850 events read in total (1107407ms).
[10:37:12.877] <TB2> INFO: 32366050 events read in total (1130493ms).
[10:37:36.106] <TB2> INFO: 33026200 events read in total (1153722ms).
[10:37:59.341] <TB2> INFO: 33685850 events read in total (1176957ms).
[10:38:22.421] <TB2> INFO: 34345500 events read in total (1200037ms).
[10:38:45.292] <TB2> INFO: 35004250 events read in total (1222908ms).
[10:39:08.186] <TB2> INFO: 35663400 events read in total (1245802ms).
[10:39:31.823] <TB2> INFO: 36331100 events read in total (1269439ms).
[10:39:41.768] <TB2> INFO: 36608000 events read in total (1279384ms).
[10:39:41.847] <TB2> INFO: Test took 1280303ms.
[10:39:42.226] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:39:44.135] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:39:45.667] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:39:47.319] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:39:48.812] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:39:50.285] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:39:51.752] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:39:53.229] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:39:54.779] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:39:56.757] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:39:58.843] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:40:00.948] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:40:02.981] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:40:04.954] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:40:06.820] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:40:08.820] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[10:40:10.864] <TB2> INFO: PixTestScurves::scurves() done
[10:40:10.864] <TB2> INFO: Vcal mean: 115.54 126.85 134.34 108.90 116.99 122.68 120.07 117.86 112.11 116.66 116.07 104.27 105.32 128.41 117.47 124.02
[10:40:10.864] <TB2> INFO: Vcal RMS: 5.88 6.24 6.33 6.42 6.23 7.88 6.24 6.58 5.60 5.83 6.01 6.00 5.31 6.21 5.82 8.16
[10:40:10.864] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1309 seconds
[10:40:10.864] <TB2> INFO: Decoding statistics:
[10:40:10.864] <TB2> INFO: General information:
[10:40:10.864] <TB2> INFO: 16bit words read: 0
[10:40:10.864] <TB2> INFO: valid events total: 0
[10:40:10.864] <TB2> INFO: empty events: 0
[10:40:10.864] <TB2> INFO: valid events with pixels: 0
[10:40:10.864] <TB2> INFO: valid pixel hits: 0
[10:40:10.864] <TB2> INFO: Event errors: 0
[10:40:10.864] <TB2> INFO: start marker: 0
[10:40:10.864] <TB2> INFO: stop marker: 0
[10:40:10.864] <TB2> INFO: overflow: 0
[10:40:10.864] <TB2> INFO: invalid 5bit words: 0
[10:40:10.864] <TB2> INFO: invalid XOR eye diagram: 0
[10:40:10.864] <TB2> INFO: frame (failed synchr.): 0
[10:40:10.864] <TB2> INFO: idle data (no TBM trl): 0
[10:40:10.864] <TB2> INFO: no data (only TBM hdr): 0
[10:40:10.864] <TB2> INFO: TBM errors: 0
[10:40:10.864] <TB2> INFO: flawed TBM headers: 0
[10:40:10.864] <TB2> INFO: flawed TBM trailers: 0
[10:40:10.864] <TB2> INFO: event ID mismatches: 0
[10:40:10.864] <TB2> INFO: ROC errors: 0
[10:40:10.864] <TB2> INFO: missing ROC header(s): 0
[10:40:10.864] <TB2> INFO: misplaced readback start: 0
[10:40:10.864] <TB2> INFO: Pixel decoding errors: 0
[10:40:10.864] <TB2> INFO: pixel data incomplete: 0
[10:40:10.864] <TB2> INFO: pixel address: 0
[10:40:10.864] <TB2> INFO: pulse height fill bit: 0
[10:40:10.864] <TB2> INFO: buffer corruption: 0
[10:40:10.958] <TB2> INFO: ######################################################################
[10:40:10.958] <TB2> INFO: PixTestTrim::doTest()
[10:40:10.958] <TB2> INFO: ######################################################################
[10:40:10.959] <TB2> INFO: ----------------------------------------------------------------------
[10:40:10.959] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[10:40:10.959] <TB2> INFO: ----------------------------------------------------------------------
[10:40:11.013] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[10:40:11.013] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[10:40:11.027] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:40:11.027] <TB2> INFO: run 1 of 1
[10:40:11.300] <TB2> INFO: Expecting 5025280 events.
[10:40:42.760] <TB2> INFO: 832736 events read in total (30859ms).
[10:41:13.688] <TB2> INFO: 1664176 events read in total (61787ms).
[10:41:44.951] <TB2> INFO: 2492968 events read in total (93050ms).
[10:42:16.076] <TB2> INFO: 3319280 events read in total (124175ms).
[10:42:46.761] <TB2> INFO: 4140872 events read in total (154861ms).
[10:43:17.644] <TB2> INFO: 4961104 events read in total (185743ms).
[10:43:20.528] <TB2> INFO: 5025280 events read in total (188627ms).
[10:43:20.605] <TB2> INFO: Test took 189578ms.
[10:43:38.995] <TB2> INFO: ROC 0 VthrComp = 113
[10:43:38.995] <TB2> INFO: ROC 1 VthrComp = 130
[10:43:38.995] <TB2> INFO: ROC 2 VthrComp = 131
[10:43:38.995] <TB2> INFO: ROC 3 VthrComp = 102
[10:43:38.995] <TB2> INFO: ROC 4 VthrComp = 108
[10:43:38.995] <TB2> INFO: ROC 5 VthrComp = 114
[10:43:38.995] <TB2> INFO: ROC 6 VthrComp = 125
[10:43:38.996] <TB2> INFO: ROC 7 VthrComp = 114
[10:43:38.996] <TB2> INFO: ROC 8 VthrComp = 108
[10:43:38.996] <TB2> INFO: ROC 9 VthrComp = 123
[10:43:38.996] <TB2> INFO: ROC 10 VthrComp = 113
[10:43:38.996] <TB2> INFO: ROC 11 VthrComp = 96
[10:43:38.996] <TB2> INFO: ROC 12 VthrComp = 104
[10:43:38.996] <TB2> INFO: ROC 13 VthrComp = 130
[10:43:38.996] <TB2> INFO: ROC 14 VthrComp = 118
[10:43:38.996] <TB2> INFO: ROC 15 VthrComp = 110
[10:43:39.235] <TB2> INFO: Expecting 41600 events.
[10:43:42.685] <TB2> INFO: 41600 events read in total (2858ms).
[10:43:42.685] <TB2> INFO: Test took 3687ms.
[10:43:42.694] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[10:43:42.694] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[10:43:42.706] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:43:42.706] <TB2> INFO: run 1 of 1
[10:43:42.986] <TB2> INFO: Expecting 5025280 events.
[10:44:10.502] <TB2> INFO: 596104 events read in total (26925ms).
[10:44:37.227] <TB2> INFO: 1190320 events read in total (53650ms).
[10:45:03.614] <TB2> INFO: 1783992 events read in total (80037ms).
[10:45:30.206] <TB2> INFO: 2377400 events read in total (106629ms).
[10:45:56.973] <TB2> INFO: 2967632 events read in total (133396ms).
[10:46:23.290] <TB2> INFO: 3556528 events read in total (159713ms).
[10:46:49.418] <TB2> INFO: 4144184 events read in total (185841ms).
[10:47:15.889] <TB2> INFO: 4731144 events read in total (212312ms).
[10:47:28.900] <TB2> INFO: 5025280 events read in total (225324ms).
[10:47:28.985] <TB2> INFO: Test took 226278ms.
[10:47:57.451] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 63.8058 for pixel 22/3 mean/min/max = 48.0099/32.0725/63.9473
[10:47:57.452] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 62.8012 for pixel 16/0 mean/min/max = 47.9045/32.8502/62.9588
[10:47:57.452] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 67.4123 for pixel 51/66 mean/min/max = 48.5787/29.3378/67.8196
[10:47:57.453] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 68.2286 for pixel 3/3 mean/min/max = 50.2066/32.0365/68.3768
[10:47:57.453] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 70.0729 for pixel 38/15 mean/min/max = 51.6724/33.2511/70.0938
[10:47:57.454] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 70.0556 for pixel 21/8 mean/min/max = 49.4985/28.7565/70.2405
[10:47:57.454] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 61.5073 for pixel 2/28 mean/min/max = 46.2514/30.8242/61.6785
[10:47:57.455] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 66.9693 for pixel 20/13 mean/min/max = 48.6984/30.3499/67.047
[10:47:57.456] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 67.4263 for pixel 0/1 mean/min/max = 50.2077/32.9146/67.5008
[10:47:57.456] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 60.7784 for pixel 3/2 mean/min/max = 45.7802/30.6885/60.8719
[10:47:57.457] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 68.3054 for pixel 18/5 mean/min/max = 49.2037/29.9313/68.4762
[10:47:57.457] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 68.6647 for pixel 41/0 mean/min/max = 49.865/30.9583/68.7717
[10:47:57.458] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 67.2639 for pixel 9/4 mean/min/max = 50.3775/33.2267/67.5283
[10:47:57.458] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 63.5341 for pixel 18/12 mean/min/max = 48.0182/32.4383/63.5982
[10:47:57.459] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 61.5004 for pixel 0/7 mean/min/max = 46.6559/31.7603/61.5515
[10:47:57.459] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 75.9211 for pixel 10/8 mean/min/max = 53.0624/29.9477/76.1772
[10:47:57.460] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:47:57.550] <TB2> INFO: Expecting 411648 events.
[10:48:07.170] <TB2> INFO: 411648 events read in total (9028ms).
[10:48:07.178] <TB2> INFO: Expecting 411648 events.
[10:48:16.586] <TB2> INFO: 411648 events read in total (9005ms).
[10:48:16.599] <TB2> INFO: Expecting 411648 events.
[10:48:25.936] <TB2> INFO: 411648 events read in total (8934ms).
[10:48:25.953] <TB2> INFO: Expecting 411648 events.
[10:48:35.264] <TB2> INFO: 411648 events read in total (8907ms).
[10:48:35.283] <TB2> INFO: Expecting 411648 events.
[10:48:44.631] <TB2> INFO: 411648 events read in total (8945ms).
[10:48:44.650] <TB2> INFO: Expecting 411648 events.
[10:48:53.872] <TB2> INFO: 411648 events read in total (8818ms).
[10:48:53.893] <TB2> INFO: Expecting 411648 events.
[10:49:03.163] <TB2> INFO: 411648 events read in total (8867ms).
[10:49:03.191] <TB2> INFO: Expecting 411648 events.
[10:49:12.515] <TB2> INFO: 411648 events read in total (8921ms).
[10:49:12.557] <TB2> INFO: Expecting 411648 events.
[10:49:21.825] <TB2> INFO: 411648 events read in total (8865ms).
[10:49:21.881] <TB2> INFO: Expecting 411648 events.
[10:49:31.135] <TB2> INFO: 411648 events read in total (8850ms).
[10:49:31.185] <TB2> INFO: Expecting 411648 events.
[10:49:40.574] <TB2> INFO: 411648 events read in total (8986ms).
[10:49:40.616] <TB2> INFO: Expecting 411648 events.
[10:49:49.928] <TB2> INFO: 411648 events read in total (8909ms).
[10:49:50.028] <TB2> INFO: Expecting 411648 events.
[10:49:59.418] <TB2> INFO: 411648 events read in total (8987ms).
[10:49:59.462] <TB2> INFO: Expecting 411648 events.
[10:50:08.684] <TB2> INFO: 411648 events read in total (8819ms).
[10:50:08.782] <TB2> INFO: Expecting 411648 events.
[10:50:17.972] <TB2> INFO: 411648 events read in total (8787ms).
[10:50:18.035] <TB2> INFO: Expecting 411648 events.
[10:50:27.368] <TB2> INFO: 411648 events read in total (8930ms).
[10:50:27.428] <TB2> INFO: Test took 149968ms.
[10:50:28.122] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[10:50:28.136] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:50:28.136] <TB2> INFO: run 1 of 1
[10:50:28.394] <TB2> INFO: Expecting 5025280 events.
[10:50:55.119] <TB2> INFO: 597080 events read in total (26133ms).
[10:51:21.191] <TB2> INFO: 1189488 events read in total (52205ms).
[10:51:47.563] <TB2> INFO: 1781648 events read in total (78577ms).
[10:52:13.856] <TB2> INFO: 2371720 events read in total (104870ms).
[10:52:39.905] <TB2> INFO: 2960896 events read in total (130920ms).
[10:53:06.371] <TB2> INFO: 3555400 events read in total (157385ms).
[10:53:32.757] <TB2> INFO: 4153432 events read in total (183771ms).
[10:54:00.907] <TB2> INFO: 4750848 events read in total (211921ms).
[10:54:13.938] <TB2> INFO: 5025280 events read in total (224952ms).
[10:54:14.094] <TB2> INFO: Test took 225959ms.
[10:54:36.705] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 1.500000 .. 147.668737
[10:54:36.942] <TB2> INFO: Expecting 208000 events.
[10:54:46.539] <TB2> INFO: 208000 events read in total (9006ms).
[10:54:46.540] <TB2> INFO: Test took 9834ms.
[10:54:46.589] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 1 .. 157 (-1/-1) hits flags = 528 (plus default)
[10:54:46.602] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:54:46.602] <TB2> INFO: run 1 of 1
[10:54:46.881] <TB2> INFO: Expecting 5224960 events.
[10:55:13.181] <TB2> INFO: 583864 events read in total (25709ms).
[10:55:39.138] <TB2> INFO: 1167992 events read in total (51667ms).
[10:56:05.036] <TB2> INFO: 1751712 events read in total (77565ms).
[10:56:31.382] <TB2> INFO: 2335136 events read in total (103910ms).
[10:56:57.173] <TB2> INFO: 2919328 events read in total (129701ms).
[10:57:23.514] <TB2> INFO: 3502528 events read in total (156042ms).
[10:57:49.465] <TB2> INFO: 4086080 events read in total (181993ms).
[10:58:16.068] <TB2> INFO: 4669448 events read in total (208596ms).
[10:58:41.252] <TB2> INFO: 5224960 events read in total (233780ms).
[10:58:41.372] <TB2> INFO: Test took 234770ms.
[10:59:06.580] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 26.572605 .. 47.833441
[10:59:06.818] <TB2> INFO: Expecting 208000 events.
[10:59:16.916] <TB2> INFO: 208000 events read in total (9506ms).
[10:59:16.917] <TB2> INFO: Test took 10336ms.
[10:59:16.988] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 57 (-1/-1) hits flags = 528 (plus default)
[10:59:16.002] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[10:59:16.003] <TB2> INFO: run 1 of 1
[10:59:17.281] <TB2> INFO: Expecting 1397760 events.
[10:59:46.224] <TB2> INFO: 657096 events read in total (28351ms).
[11:00:14.464] <TB2> INFO: 1312088 events read in total (56591ms).
[11:00:18.736] <TB2> INFO: 1397760 events read in total (60863ms).
[11:00:18.774] <TB2> INFO: Test took 61772ms.
[11:00:34.717] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 27.976423 .. 48.696132
[11:00:34.956] <TB2> INFO: Expecting 208000 events.
[11:00:44.938] <TB2> INFO: 208000 events read in total (9390ms).
[11:00:44.939] <TB2> INFO: Test took 10220ms.
[11:00:44.992] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 58 (-1/-1) hits flags = 528 (plus default)
[11:00:45.005] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:00:45.006] <TB2> INFO: run 1 of 1
[11:00:45.284] <TB2> INFO: Expecting 1397760 events.
[11:01:13.866] <TB2> INFO: 649040 events read in total (27990ms).
[11:01:41.656] <TB2> INFO: 1296088 events read in total (55780ms).
[11:01:46.740] <TB2> INFO: 1397760 events read in total (60864ms).
[11:01:46.772] <TB2> INFO: Test took 61767ms.
[11:02:00.532] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 26.282832 .. 51.524942
[11:02:00.772] <TB2> INFO: Expecting 208000 events.
[11:02:10.999] <TB2> INFO: 208000 events read in total (9635ms).
[11:02:10.001] <TB2> INFO: Test took 10467ms.
[11:02:11.050] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 61 (-1/-1) hits flags = 528 (plus default)
[11:02:11.064] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:02:11.064] <TB2> INFO: run 1 of 1
[11:02:11.348] <TB2> INFO: Expecting 1530880 events.
[11:02:39.642] <TB2> INFO: 642552 events read in total (27703ms).
[11:03:07.302] <TB2> INFO: 1284896 events read in total (55363ms).
[11:03:18.144] <TB2> INFO: 1530880 events read in total (66205ms).
[11:03:18.195] <TB2> INFO: Test took 67132ms.
[11:03:32.008] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[11:03:32.008] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[11:03:32.022] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:03:32.022] <TB2> INFO: run 1 of 1
[11:03:32.260] <TB2> INFO: Expecting 1364480 events.
[11:04:00.550] <TB2> INFO: 667992 events read in total (27698ms).
[11:04:28.820] <TB2> INFO: 1335144 events read in total (55968ms).
[11:04:30.627] <TB2> INFO: 1364480 events read in total (57776ms).
[11:04:30.659] <TB2> INFO: Test took 58638ms.
[11:04:43.266] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C0.dat
[11:04:43.266] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C1.dat
[11:04:43.266] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C2.dat
[11:04:43.266] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C3.dat
[11:04:43.266] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C4.dat
[11:04:43.266] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C5.dat
[11:04:43.266] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C6.dat
[11:04:43.266] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C7.dat
[11:04:43.266] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C8.dat
[11:04:43.266] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C9.dat
[11:04:43.266] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C10.dat
[11:04:43.267] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C11.dat
[11:04:43.267] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C12.dat
[11:04:43.267] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C13.dat
[11:04:43.267] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C14.dat
[11:04:43.267] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C15.dat
[11:04:43.267] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters35_C0.dat
[11:04:43.272] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters35_C1.dat
[11:04:43.279] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters35_C2.dat
[11:04:43.286] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters35_C3.dat
[11:04:43.292] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters35_C4.dat
[11:04:43.299] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters35_C5.dat
[11:04:43.305] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters35_C6.dat
[11:04:43.312] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters35_C7.dat
[11:04:43.318] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters35_C8.dat
[11:04:43.325] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters35_C9.dat
[11:04:43.332] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters35_C10.dat
[11:04:43.339] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters35_C11.dat
[11:04:43.346] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters35_C12.dat
[11:04:43.353] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters35_C13.dat
[11:04:43.360] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters35_C14.dat
[11:04:43.367] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//trimParameters35_C15.dat
[11:04:43.374] <TB2> INFO: PixTestTrim::trimTest() done
[11:04:43.374] <TB2> INFO: vtrim: 138 132 134 122 141 151 129 142 127 123 183 149 154 141 113 156
[11:04:43.374] <TB2> INFO: vthrcomp: 113 130 131 102 108 114 125 114 108 123 113 96 104 130 118 110
[11:04:43.374] <TB2> INFO: vcal mean: 35.05 34.99 35.21 35.07 35.64 35.34 34.97 35.11 35.07 35.04 35.05 35.01 35.01 35.07 34.97 35.38
[11:04:43.374] <TB2> INFO: vcal RMS: 1.18 1.07 1.61 1.37 1.95 1.88 1.13 1.31 1.18 1.13 1.39 1.13 1.08 1.14 1.07 1.62
[11:04:43.374] <TB2> INFO: bits mean: 9.34 8.98 9.29 9.00 9.00 9.95 9.56 9.43 8.63 9.44 9.68 9.26 8.85 9.15 9.02 9.09
[11:04:43.374] <TB2> INFO: bits RMS: 2.62 2.60 2.99 2.67 2.71 2.67 2.75 2.76 2.77 2.87 2.68 2.74 2.62 2.63 2.87 2.87
[11:04:43.382] <TB2> INFO: ----------------------------------------------------------------------
[11:04:43.382] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[11:04:43.382] <TB2> INFO: ----------------------------------------------------------------------
[11:04:43.385] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[11:04:43.400] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:04:43.400] <TB2> INFO: run 1 of 1
[11:04:43.665] <TB2> INFO: Expecting 4160000 events.
[11:05:16.744] <TB2> INFO: 748920 events read in total (32488ms).
[11:05:49.199] <TB2> INFO: 1494285 events read in total (64943ms).
[11:06:21.967] <TB2> INFO: 2237135 events read in total (97711ms).
[11:06:54.230] <TB2> INFO: 2976655 events read in total (129974ms).
[11:07:26.524] <TB2> INFO: 3716770 events read in total (162268ms).
[11:07:46.032] <TB2> INFO: 4160000 events read in total (181776ms).
[11:07:46.137] <TB2> INFO: Test took 182737ms.
[11:08:12.233] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 211 (-1/-1) hits flags = 528 (plus default)
[11:08:12.248] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:08:12.248] <TB2> INFO: run 1 of 1
[11:08:12.537] <TB2> INFO: Expecting 4409600 events.
[11:08:44.567] <TB2> INFO: 712070 events read in total (31439ms).
[11:09:16.125] <TB2> INFO: 1421450 events read in total (62997ms).
[11:09:47.758] <TB2> INFO: 2129700 events read in total (94630ms).
[11:10:19.330] <TB2> INFO: 2834045 events read in total (126202ms).
[11:10:50.338] <TB2> INFO: 3537955 events read in total (157210ms).
[11:11:21.607] <TB2> INFO: 4242005 events read in total (188479ms).
[11:11:28.997] <TB2> INFO: 4409600 events read in total (195869ms).
[11:11:29.119] <TB2> INFO: Test took 196871ms.
[11:11:53.794] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[11:11:53.807] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:11:53.807] <TB2> INFO: run 1 of 1
[11:11:54.045] <TB2> INFO: Expecting 4264000 events.
[11:12:25.879] <TB2> INFO: 720275 events read in total (31242ms).
[11:12:57.263] <TB2> INFO: 1437905 events read in total (62626ms).
[11:13:28.796] <TB2> INFO: 2154240 events read in total (94159ms).
[11:14:00.410] <TB2> INFO: 2866025 events read in total (125773ms).
[11:14:31.988] <TB2> INFO: 3578715 events read in total (157351ms).
[11:15:01.580] <TB2> INFO: 4264000 events read in total (186943ms).
[11:15:01.732] <TB2> INFO: Test took 187925ms.
[11:15:28.979] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[11:15:28.992] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:15:28.992] <TB2> INFO: run 1 of 1
[11:15:29.232] <TB2> INFO: Expecting 4284800 events.
[11:16:01.167] <TB2> INFO: 719720 events read in total (31344ms).
[11:16:32.438] <TB2> INFO: 1436640 events read in total (62615ms).
[11:17:03.709] <TB2> INFO: 2151765 events read in total (93886ms).
[11:17:35.093] <TB2> INFO: 2862950 events read in total (125270ms).
[11:18:05.867] <TB2> INFO: 3574715 events read in total (156044ms).
[11:18:36.973] <TB2> INFO: 4284800 events read in total (187150ms).
[11:18:37.093] <TB2> INFO: Test took 188101ms.
[11:19:03.318] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[11:19:03.331] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:19:03.331] <TB2> INFO: run 1 of 1
[11:19:03.567] <TB2> INFO: Expecting 4305600 events.
[11:19:35.132] <TB2> INFO: 718215 events read in total (30974ms).
[11:20:06.152] <TB2> INFO: 1434210 events read in total (61994ms).
[11:20:37.071] <TB2> INFO: 2148180 events read in total (92913ms).
[11:21:08.323] <TB2> INFO: 2858360 events read in total (124165ms).
[11:21:40.605] <TB2> INFO: 3568485 events read in total (156447ms).
[11:22:12.257] <TB2> INFO: 4279805 events read in total (188099ms).
[11:22:13.852] <TB2> INFO: 4305600 events read in total (189694ms).
[11:22:13.972] <TB2> INFO: Test took 190641ms.
[11:22:39.448] <TB2> INFO: PixTestTrim::trimBitTest() done
[11:22:39.450] <TB2> INFO: PixTestTrim::doTest() done, duration: 2548 seconds
[11:22:39.450] <TB2> INFO: Decoding statistics:
[11:22:39.450] <TB2> INFO: General information:
[11:22:39.450] <TB2> INFO: 16bit words read: 0
[11:22:39.450] <TB2> INFO: valid events total: 0
[11:22:39.450] <TB2> INFO: empty events: 0
[11:22:39.450] <TB2> INFO: valid events with pixels: 0
[11:22:39.450] <TB2> INFO: valid pixel hits: 0
[11:22:39.450] <TB2> INFO: Event errors: 0
[11:22:39.450] <TB2> INFO: start marker: 0
[11:22:39.450] <TB2> INFO: stop marker: 0
[11:22:39.450] <TB2> INFO: overflow: 0
[11:22:39.450] <TB2> INFO: invalid 5bit words: 0
[11:22:39.450] <TB2> INFO: invalid XOR eye diagram: 0
[11:22:39.450] <TB2> INFO: frame (failed synchr.): 0
[11:22:39.450] <TB2> INFO: idle data (no TBM trl): 0
[11:22:39.450] <TB2> INFO: no data (only TBM hdr): 0
[11:22:39.450] <TB2> INFO: TBM errors: 0
[11:22:39.450] <TB2> INFO: flawed TBM headers: 0
[11:22:39.450] <TB2> INFO: flawed TBM trailers: 0
[11:22:39.450] <TB2> INFO: event ID mismatches: 0
[11:22:39.450] <TB2> INFO: ROC errors: 0
[11:22:39.450] <TB2> INFO: missing ROC header(s): 0
[11:22:39.450] <TB2> INFO: misplaced readback start: 0
[11:22:39.450] <TB2> INFO: Pixel decoding errors: 0
[11:22:39.450] <TB2> INFO: pixel data incomplete: 0
[11:22:39.450] <TB2> INFO: pixel address: 0
[11:22:39.450] <TB2> INFO: pulse height fill bit: 0
[11:22:39.450] <TB2> INFO: buffer corruption: 0
[11:22:40.062] <TB2> INFO: ######################################################################
[11:22:40.062] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[11:22:40.062] <TB2> INFO: ######################################################################
[11:22:40.303] <TB2> INFO: Expecting 41600 events.
[11:22:43.865] <TB2> INFO: 41600 events read in total (2970ms).
[11:22:43.866] <TB2> INFO: Test took 3803ms.
[11:22:44.314] <TB2> INFO: Expecting 41600 events.
[11:22:47.893] <TB2> INFO: 41600 events read in total (2987ms).
[11:22:47.893] <TB2> INFO: Test took 3821ms.
[11:22:47.903] <TB2> INFO: Max pixel from chip 0 is [4 ,67] phvalue 142
[11:22:47.903] <TB2> INFO: Max pixel from chip 1 is [12 ,65] phvalue 75
[11:22:47.903] <TB2> INFO: Max pixel from chip 2 is [30 ,22] phvalue 99
[11:22:47.904] <TB2> INFO: Max pixel from chip 3 is [16 ,15] phvalue 215
[11:22:47.904] <TB2> INFO: Max pixel from chip 4 is [4 ,7] phvalue 104
[11:22:47.904] <TB2> INFO: Max pixel from chip 5 is [19 ,10] phvalue 120
[11:22:47.904] <TB2> INFO: Max pixel from chip 6 is [6 ,6] phvalue 141
[11:22:47.904] <TB2> INFO: Max pixel from chip 7 is [12 ,17] phvalue 87
[11:22:47.904] <TB2> INFO: Max pixel from chip 8 is [27 ,9] phvalue 106
[11:22:47.904] <TB2> INFO: Max pixel from chip 9 is [14 ,29] phvalue 80
[11:22:47.904] <TB2> INFO: Max pixel from chip 10 is [4 ,30] phvalue 143
[11:22:47.905] <TB2> INFO: Max pixel from chip 11 is [5 ,22] phvalue 189
[11:22:47.905] <TB2> INFO: Max pixel from chip 12 is [14 ,12] phvalue 83
[11:22:47.905] <TB2> INFO: Max pixel from chip 13 is [8 ,36] phvalue 135
[11:22:47.905] <TB2> INFO: Max pixel from chip 14 is [24 ,29] phvalue 78
[11:22:47.905] <TB2> INFO: Max pixel from chip 15 is [11 ,16] phvalue 123
[11:22:48.185] <TB2> INFO: Expecting 41600 events.
[11:22:51.735] <TB2> INFO: 41600 events read in total (2958ms).
[11:22:51.736] <TB2> INFO: Test took 3816ms.
[11:22:51.748] <TB2> INFO: Min pixel from chip 0 is [3 ,5] phvalue 255
[11:22:51.748] <TB2> INFO: Min pixel from chip 1 is [24 ,29] phvalue 236
[11:22:51.748] <TB2> INFO: Min pixel from chip 2 is [3 ,5] phvalue 255
[11:22:51.748] <TB2> INFO: Min pixel from chip 3 is [3 ,5] phvalue 255
[11:22:51.749] <TB2> INFO: Min pixel from chip 4 is [3 ,5] phvalue 255
[11:22:51.749] <TB2> INFO: Min pixel from chip 5 is [3 ,5] phvalue 255
[11:22:51.749] <TB2> INFO: Min pixel from chip 6 is [3 ,5] phvalue 255
[11:22:51.749] <TB2> INFO: Min pixel from chip 7 is [41 ,22] phvalue 246
[11:22:51.749] <TB2> INFO: Min pixel from chip 8 is [3 ,5] phvalue 255
[11:22:51.749] <TB2> INFO: Min pixel from chip 9 is [3 ,5] phvalue 255
[11:22:51.749] <TB2> INFO: Min pixel from chip 10 is [3 ,5] phvalue 255
[11:22:51.749] <TB2> INFO: Min pixel from chip 11 is [3 ,5] phvalue 255
[11:22:51.749] <TB2> INFO: Min pixel from chip 12 is [3 ,5] phvalue 255
[11:22:51.750] <TB2> INFO: Min pixel from chip 13 is [3 ,5] phvalue 255
[11:22:51.750] <TB2> INFO: Min pixel from chip 14 is [48 ,6] phvalue 245
[11:22:51.750] <TB2> INFO: Min pixel from chip 15 is [3 ,5] phvalue 255
[11:22:52.029] <TB2> INFO: Expecting 2560 events.
[11:22:52.921] <TB2> INFO: 2560 events read in total (300ms).
[11:22:52.921] <TB2> INFO: Test took 1169ms.
[11:22:53.228] <TB2> INFO: Expecting 2560 events.
[11:22:54.120] <TB2> INFO: 2560 events read in total (300ms).
[11:22:54.121] <TB2> INFO: Test took 1199ms.
[11:22:54.428] <TB2> INFO: Expecting 2560 events.
[11:22:55.315] <TB2> INFO: 2560 events read in total (295ms).
[11:22:55.315] <TB2> INFO: Test took 1194ms.
[11:22:55.622] <TB2> INFO: Expecting 2560 events.
[11:22:56.511] <TB2> INFO: 2560 events read in total (297ms).
[11:22:56.511] <TB2> INFO: Test took 1196ms.
[11:22:56.820] <TB2> INFO: Expecting 2560 events.
[11:22:57.705] <TB2> INFO: 2560 events read in total (294ms).
[11:22:57.705] <TB2> INFO: Test took 1194ms.
[11:22:58.014] <TB2> INFO: Expecting 2560 events.
[11:22:58.893] <TB2> INFO: 2560 events read in total (288ms).
[11:22:58.894] <TB2> INFO: Test took 1188ms.
[11:22:59.200] <TB2> INFO: Expecting 2560 events.
[11:23:00.080] <TB2> INFO: 2560 events read in total (288ms).
[11:23:00.081] <TB2> INFO: Test took 1187ms.
[11:23:00.389] <TB2> INFO: Expecting 2560 events.
[11:23:01.274] <TB2> INFO: 2560 events read in total (293ms).
[11:23:01.274] <TB2> INFO: Test took 1193ms.
[11:23:01.582] <TB2> INFO: Expecting 2560 events.
[11:23:02.463] <TB2> INFO: 2560 events read in total (289ms).
[11:23:02.464] <TB2> INFO: Test took 1190ms.
[11:23:02.772] <TB2> INFO: Expecting 2560 events.
[11:23:03.663] <TB2> INFO: 2560 events read in total (299ms).
[11:23:03.663] <TB2> INFO: Test took 1199ms.
[11:23:03.972] <TB2> INFO: Expecting 2560 events.
[11:23:04.855] <TB2> INFO: 2560 events read in total (292ms).
[11:23:04.855] <TB2> INFO: Test took 1191ms.
[11:23:05.164] <TB2> INFO: Expecting 2560 events.
[11:23:06.054] <TB2> INFO: 2560 events read in total (299ms).
[11:23:06.054] <TB2> INFO: Test took 1198ms.
[11:23:06.361] <TB2> INFO: Expecting 2560 events.
[11:23:07.253] <TB2> INFO: 2560 events read in total (300ms).
[11:23:07.254] <TB2> INFO: Test took 1199ms.
[11:23:07.562] <TB2> INFO: Expecting 2560 events.
[11:23:08.449] <TB2> INFO: 2560 events read in total (295ms).
[11:23:08.450] <TB2> INFO: Test took 1196ms.
[11:23:08.757] <TB2> INFO: Expecting 2560 events.
[11:23:09.650] <TB2> INFO: 2560 events read in total (302ms).
[11:23:09.650] <TB2> INFO: Test took 1199ms.
[11:23:09.956] <TB2> INFO: Expecting 2560 events.
[11:23:10.847] <TB2> INFO: 2560 events read in total (299ms).
[11:23:10.848] <TB2> INFO: Test took 1197ms.
[11:23:10.851] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:23:11.155] <TB2> INFO: Expecting 655360 events.
[11:23:26.058] <TB2> INFO: 655360 events read in total (14311ms).
[11:23:26.076] <TB2> INFO: Expecting 655360 events.
[11:23:40.746] <TB2> INFO: 655360 events read in total (14267ms).
[11:23:40.765] <TB2> INFO: Expecting 655360 events.
[11:23:55.586] <TB2> INFO: 655360 events read in total (14418ms).
[11:23:55.613] <TB2> INFO: Expecting 655360 events.
[11:24:10.269] <TB2> INFO: 655360 events read in total (14253ms).
[11:24:10.298] <TB2> INFO: Expecting 655360 events.
[11:24:24.969] <TB2> INFO: 655360 events read in total (14268ms).
[11:24:24.001] <TB2> INFO: Expecting 655360 events.
[11:24:39.785] <TB2> INFO: 655360 events read in total (14380ms).
[11:24:39.826] <TB2> INFO: Expecting 655360 events.
[11:24:54.547] <TB2> INFO: 655360 events read in total (14318ms).
[11:24:54.598] <TB2> INFO: Expecting 655360 events.
[11:25:09.203] <TB2> INFO: 655360 events read in total (14202ms).
[11:25:09.248] <TB2> INFO: Expecting 655360 events.
[11:25:23.891] <TB2> INFO: 655360 events read in total (14240ms).
[11:25:23.939] <TB2> INFO: Expecting 655360 events.
[11:25:38.561] <TB2> INFO: 655360 events read in total (14219ms).
[11:25:38.631] <TB2> INFO: Expecting 655360 events.
[11:25:53.227] <TB2> INFO: 655360 events read in total (14193ms).
[11:25:53.299] <TB2> INFO: Expecting 655360 events.
[11:26:07.908] <TB2> INFO: 655360 events read in total (14206ms).
[11:26:07.995] <TB2> INFO: Expecting 655360 events.
[11:26:22.767] <TB2> INFO: 655360 events read in total (14368ms).
[11:26:22.893] <TB2> INFO: Expecting 655360 events.
[11:26:37.640] <TB2> INFO: 655360 events read in total (14344ms).
[11:26:37.763] <TB2> INFO: Expecting 655360 events.
[11:26:52.302] <TB2> INFO: 655360 events read in total (14136ms).
[11:26:52.434] <TB2> INFO: Expecting 655360 events.
[11:27:07.182] <TB2> INFO: 655360 events read in total (14345ms).
[11:27:07.292] <TB2> INFO: Test took 236441ms.
[11:27:07.396] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:27:07.651] <TB2> INFO: Expecting 655360 events.
[11:27:22.499] <TB2> INFO: 655360 events read in total (14256ms).
[11:27:22.518] <TB2> INFO: Expecting 655360 events.
[11:27:37.098] <TB2> INFO: 655360 events read in total (14177ms).
[11:27:37.117] <TB2> INFO: Expecting 655360 events.
[11:27:51.528] <TB2> INFO: 655360 events read in total (14008ms).
[11:27:51.557] <TB2> INFO: Expecting 655360 events.
[11:28:06.110] <TB2> INFO: 655360 events read in total (14150ms).
[11:28:06.150] <TB2> INFO: Expecting 655360 events.
[11:28:20.753] <TB2> INFO: 655360 events read in total (14200ms).
[11:28:20.799] <TB2> INFO: Expecting 655360 events.
[11:28:35.361] <TB2> INFO: 655360 events read in total (14159ms).
[11:28:35.406] <TB2> INFO: Expecting 655360 events.
[11:28:49.972] <TB2> INFO: 655360 events read in total (14163ms).
[11:28:50.040] <TB2> INFO: Expecting 655360 events.
[11:29:04.576] <TB2> INFO: 655360 events read in total (14133ms).
[11:29:04.620] <TB2> INFO: Expecting 655360 events.
[11:29:19.279] <TB2> INFO: 655360 events read in total (14255ms).
[11:29:19.334] <TB2> INFO: Expecting 655360 events.
[11:29:33.980] <TB2> INFO: 655360 events read in total (14243ms).
[11:29:34.052] <TB2> INFO: Expecting 655360 events.
[11:29:48.749] <TB2> INFO: 655360 events read in total (14294ms).
[11:29:48.835] <TB2> INFO: Expecting 655360 events.
[11:30:03.530] <TB2> INFO: 655360 events read in total (14292ms).
[11:30:03.640] <TB2> INFO: Expecting 655360 events.
[11:30:18.663] <TB2> INFO: 655360 events read in total (14620ms).
[11:30:18.764] <TB2> INFO: Expecting 655360 events.
[11:30:33.595] <TB2> INFO: 655360 events read in total (14428ms).
[11:30:33.683] <TB2> INFO: Expecting 655360 events.
[11:30:48.813] <TB2> INFO: 655360 events read in total (14727ms).
[11:30:48.936] <TB2> INFO: Expecting 655360 events.
[11:31:03.608] <TB2> INFO: 655360 events read in total (14269ms).
[11:31:03.712] <TB2> INFO: Test took 236317ms.
[11:31:03.902] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:31:03.907] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:31:03.913] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:31:03.919] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:31:03.924] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:31:03.930] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:31:03.936] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:31:03.944] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:31:03.950] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[11:31:03.955] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[11:31:03.962] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[11:31:03.968] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[11:31:03.975] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[11:31:03.981] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:31:03.987] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:31:03.993] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:31:03.999] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:31:04.004] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:31:04.010] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:31:04.016] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:31:04.022] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:31:04.030] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:31:04.037] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:31:04.045] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:31:04.052] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[11:31:04.058] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[11:31:04.065] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[11:31:04.073] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[11:31:04.081] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[11:31:04.088] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[11:31:04.095] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[11:31:04.100] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[11:31:04.106] <TB2> INFO: safety margin for low PH: adding 11, margin is now 31
[11:31:04.113] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:31:04.118] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:31:04.126] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:31:04.165] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C0.dat
[11:31:04.165] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C1.dat
[11:31:04.165] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C2.dat
[11:31:04.166] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C3.dat
[11:31:04.166] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C4.dat
[11:31:04.166] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C5.dat
[11:31:04.166] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C6.dat
[11:31:04.167] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C7.dat
[11:31:04.167] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C8.dat
[11:31:04.167] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C9.dat
[11:31:04.167] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C10.dat
[11:31:04.168] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C11.dat
[11:31:04.168] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C12.dat
[11:31:04.168] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C13.dat
[11:31:04.168] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C14.dat
[11:31:04.168] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//dacParameters35_C15.dat
[11:31:04.459] <TB2> INFO: Expecting 41600 events.
[11:31:07.627] <TB2> INFO: 41600 events read in total (2576ms).
[11:31:07.628] <TB2> INFO: Test took 3455ms.
[11:31:08.100] <TB2> INFO: Expecting 41600 events.
[11:31:11.219] <TB2> INFO: 41600 events read in total (2527ms).
[11:31:11.220] <TB2> INFO: Test took 3378ms.
[11:31:11.677] <TB2> INFO: Expecting 41600 events.
[11:31:14.899] <TB2> INFO: 41600 events read in total (2630ms).
[11:31:14.900] <TB2> INFO: Test took 3467ms.
[11:31:15.123] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:15.212] <TB2> INFO: Expecting 2560 events.
[11:31:16.112] <TB2> INFO: 2560 events read in total (308ms).
[11:31:16.112] <TB2> INFO: Test took 989ms.
[11:31:16.115] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:16.420] <TB2> INFO: Expecting 2560 events.
[11:31:17.316] <TB2> INFO: 2560 events read in total (304ms).
[11:31:17.316] <TB2> INFO: Test took 1201ms.
[11:31:17.318] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:17.625] <TB2> INFO: Expecting 2560 events.
[11:31:18.515] <TB2> INFO: 2560 events read in total (298ms).
[11:31:18.516] <TB2> INFO: Test took 1198ms.
[11:31:18.518] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:18.824] <TB2> INFO: Expecting 2560 events.
[11:31:19.719] <TB2> INFO: 2560 events read in total (303ms).
[11:31:19.719] <TB2> INFO: Test took 1201ms.
[11:31:19.723] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:20.026] <TB2> INFO: Expecting 2560 events.
[11:31:20.920] <TB2> INFO: 2560 events read in total (302ms).
[11:31:20.920] <TB2> INFO: Test took 1198ms.
[11:31:20.924] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:21.228] <TB2> INFO: Expecting 2560 events.
[11:31:22.118] <TB2> INFO: 2560 events read in total (298ms).
[11:31:22.118] <TB2> INFO: Test took 1194ms.
[11:31:22.121] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:22.427] <TB2> INFO: Expecting 2560 events.
[11:31:23.324] <TB2> INFO: 2560 events read in total (306ms).
[11:31:23.324] <TB2> INFO: Test took 1204ms.
[11:31:23.327] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:23.633] <TB2> INFO: Expecting 2560 events.
[11:31:24.519] <TB2> INFO: 2560 events read in total (294ms).
[11:31:24.519] <TB2> INFO: Test took 1192ms.
[11:31:24.523] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:24.826] <TB2> INFO: Expecting 2560 events.
[11:31:25.716] <TB2> INFO: 2560 events read in total (299ms).
[11:31:25.717] <TB2> INFO: Test took 1195ms.
[11:31:25.721] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:26.024] <TB2> INFO: Expecting 2560 events.
[11:31:26.906] <TB2> INFO: 2560 events read in total (290ms).
[11:31:26.907] <TB2> INFO: Test took 1186ms.
[11:31:26.910] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:27.215] <TB2> INFO: Expecting 2560 events.
[11:31:28.108] <TB2> INFO: 2560 events read in total (301ms).
[11:31:28.109] <TB2> INFO: Test took 1199ms.
[11:31:28.115] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:28.421] <TB2> INFO: Expecting 2560 events.
[11:31:29.310] <TB2> INFO: 2560 events read in total (297ms).
[11:31:29.310] <TB2> INFO: Test took 1195ms.
[11:31:29.314] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:29.626] <TB2> INFO: Expecting 2560 events.
[11:31:30.512] <TB2> INFO: 2560 events read in total (294ms).
[11:31:30.512] <TB2> INFO: Test took 1198ms.
[11:31:30.514] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:30.823] <TB2> INFO: Expecting 2560 events.
[11:31:31.705] <TB2> INFO: 2560 events read in total (289ms).
[11:31:31.706] <TB2> INFO: Test took 1192ms.
[11:31:31.708] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:32.013] <TB2> INFO: Expecting 2560 events.
[11:31:32.898] <TB2> INFO: 2560 events read in total (293ms).
[11:31:32.898] <TB2> INFO: Test took 1190ms.
[11:31:32.900] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:33.206] <TB2> INFO: Expecting 2560 events.
[11:31:34.096] <TB2> INFO: 2560 events read in total (298ms).
[11:31:34.096] <TB2> INFO: Test took 1196ms.
[11:31:34.100] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:34.405] <TB2> INFO: Expecting 2560 events.
[11:31:35.332] <TB2> INFO: 2560 events read in total (335ms).
[11:31:35.333] <TB2> INFO: Test took 1233ms.
[11:31:35.336] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:35.641] <TB2> INFO: Expecting 2560 events.
[11:31:36.530] <TB2> INFO: 2560 events read in total (298ms).
[11:31:36.530] <TB2> INFO: Test took 1194ms.
[11:31:36.534] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:36.838] <TB2> INFO: Expecting 2560 events.
[11:31:37.729] <TB2> INFO: 2560 events read in total (299ms).
[11:31:37.730] <TB2> INFO: Test took 1196ms.
[11:31:37.732] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:38.038] <TB2> INFO: Expecting 2560 events.
[11:31:38.932] <TB2> INFO: 2560 events read in total (302ms).
[11:31:38.932] <TB2> INFO: Test took 1200ms.
[11:31:38.935] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:39.240] <TB2> INFO: Expecting 2560 events.
[11:31:40.132] <TB2> INFO: 2560 events read in total (300ms).
[11:31:40.132] <TB2> INFO: Test took 1197ms.
[11:31:40.137] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:40.441] <TB2> INFO: Expecting 2560 events.
[11:31:41.331] <TB2> INFO: 2560 events read in total (298ms).
[11:31:41.331] <TB2> INFO: Test took 1194ms.
[11:31:41.335] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:41.639] <TB2> INFO: Expecting 2560 events.
[11:31:42.545] <TB2> INFO: 2560 events read in total (291ms).
[11:31:42.545] <TB2> INFO: Test took 1211ms.
[11:31:42.549] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:42.854] <TB2> INFO: Expecting 2560 events.
[11:31:43.742] <TB2> INFO: 2560 events read in total (297ms).
[11:31:43.742] <TB2> INFO: Test took 1193ms.
[11:31:43.746] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:44.050] <TB2> INFO: Expecting 2560 events.
[11:31:44.948] <TB2> INFO: 2560 events read in total (304ms).
[11:31:44.948] <TB2> INFO: Test took 1202ms.
[11:31:44.951] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:45.256] <TB2> INFO: Expecting 2560 events.
[11:31:46.147] <TB2> INFO: 2560 events read in total (299ms).
[11:31:46.147] <TB2> INFO: Test took 1196ms.
[11:31:46.150] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:46.456] <TB2> INFO: Expecting 2560 events.
[11:31:47.349] <TB2> INFO: 2560 events read in total (301ms).
[11:31:47.349] <TB2> INFO: Test took 1199ms.
[11:31:47.353] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:47.657] <TB2> INFO: Expecting 2560 events.
[11:31:48.546] <TB2> INFO: 2560 events read in total (297ms).
[11:31:48.547] <TB2> INFO: Test took 1194ms.
[11:31:48.549] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:48.856] <TB2> INFO: Expecting 2560 events.
[11:31:49.749] <TB2> INFO: 2560 events read in total (301ms).
[11:31:49.750] <TB2> INFO: Test took 1201ms.
[11:31:49.753] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:50.058] <TB2> INFO: Expecting 2560 events.
[11:31:50.948] <TB2> INFO: 2560 events read in total (299ms).
[11:31:50.949] <TB2> INFO: Test took 1196ms.
[11:31:50.952] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:51.257] <TB2> INFO: Expecting 2560 events.
[11:31:52.144] <TB2> INFO: 2560 events read in total (295ms).
[11:31:52.145] <TB2> INFO: Test took 1193ms.
[11:31:52.148] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:31:52.453] <TB2> INFO: Expecting 2560 events.
[11:31:53.342] <TB2> INFO: 2560 events read in total (294ms).
[11:31:53.343] <TB2> INFO: Test took 1195ms.
[11:31:53.820] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 553 seconds
[11:31:53.820] <TB2> INFO: PH scale (per ROC): 48 62 41 58 53 43 41 60 44 52 47 48 47 40 65 46
[11:31:53.820] <TB2> INFO: PH offset (per ROC): 98 126 106 84 112 103 93 123 108 114 98 86 112 96 125 101
[11:31:53.831] <TB2> INFO: Decoding statistics:
[11:31:53.831] <TB2> INFO: General information:
[11:31:53.831] <TB2> INFO: 16bit words read: 127880
[11:31:53.831] <TB2> INFO: valid events total: 20480
[11:31:53.831] <TB2> INFO: empty events: 17980
[11:31:53.831] <TB2> INFO: valid events with pixels: 2500
[11:31:53.831] <TB2> INFO: valid pixel hits: 2500
[11:31:53.831] <TB2> INFO: Event errors: 0
[11:31:53.831] <TB2> INFO: start marker: 0
[11:31:53.831] <TB2> INFO: stop marker: 0
[11:31:53.831] <TB2> INFO: overflow: 0
[11:31:53.831] <TB2> INFO: invalid 5bit words: 0
[11:31:53.831] <TB2> INFO: invalid XOR eye diagram: 0
[11:31:53.831] <TB2> INFO: frame (failed synchr.): 0
[11:31:53.831] <TB2> INFO: idle data (no TBM trl): 0
[11:31:53.831] <TB2> INFO: no data (only TBM hdr): 0
[11:31:53.831] <TB2> INFO: TBM errors: 0
[11:31:53.831] <TB2> INFO: flawed TBM headers: 0
[11:31:53.831] <TB2> INFO: flawed TBM trailers: 0
[11:31:53.831] <TB2> INFO: event ID mismatches: 0
[11:31:53.831] <TB2> INFO: ROC errors: 0
[11:31:53.831] <TB2> INFO: missing ROC header(s): 0
[11:31:53.831] <TB2> INFO: misplaced readback start: 0
[11:31:53.831] <TB2> INFO: Pixel decoding errors: 0
[11:31:53.831] <TB2> INFO: pixel data incomplete: 0
[11:31:53.831] <TB2> INFO: pixel address: 0
[11:31:53.831] <TB2> INFO: pulse height fill bit: 0
[11:31:53.831] <TB2> INFO: buffer corruption: 0
[11:31:53.989] <TB2> INFO: ######################################################################
[11:31:53.989] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[11:31:53.989] <TB2> INFO: ######################################################################
[11:31:54.004] <TB2> INFO: scanning low vcal = 10
[11:31:54.257] <TB2> INFO: Expecting 41600 events.
[11:31:57.852] <TB2> INFO: 41600 events read in total (3003ms).
[11:31:57.853] <TB2> INFO: Test took 3849ms.
[11:31:57.855] <TB2> INFO: scanning low vcal = 20
[11:31:58.151] <TB2> INFO: Expecting 41600 events.
[11:32:01.733] <TB2> INFO: 41600 events read in total (2990ms).
[11:32:01.733] <TB2> INFO: Test took 3878ms.
[11:32:01.735] <TB2> INFO: scanning low vcal = 30
[11:32:02.032] <TB2> INFO: Expecting 41600 events.
[11:32:05.694] <TB2> INFO: 41600 events read in total (3070ms).
[11:32:05.696] <TB2> INFO: Test took 3961ms.
[11:32:05.698] <TB2> INFO: scanning low vcal = 40
[11:32:05.977] <TB2> INFO: Expecting 41600 events.
[11:32:09.892] <TB2> INFO: 41600 events read in total (3323ms).
[11:32:09.893] <TB2> INFO: Test took 4194ms.
[11:32:09.897] <TB2> INFO: scanning low vcal = 50
[11:32:10.174] <TB2> INFO: Expecting 41600 events.
[11:32:14.122] <TB2> INFO: 41600 events read in total (3357ms).
[11:32:14.123] <TB2> INFO: Test took 4226ms.
[11:32:14.127] <TB2> INFO: scanning low vcal = 60
[11:32:14.406] <TB2> INFO: Expecting 41600 events.
[11:32:18.374] <TB2> INFO: 41600 events read in total (3376ms).
[11:32:18.375] <TB2> INFO: Test took 4248ms.
[11:32:18.378] <TB2> INFO: scanning low vcal = 70
[11:32:18.660] <TB2> INFO: Expecting 41600 events.
[11:32:22.616] <TB2> INFO: 41600 events read in total (3361ms).
[11:32:22.617] <TB2> INFO: Test took 4239ms.
[11:32:22.620] <TB2> INFO: scanning low vcal = 80
[11:32:22.902] <TB2> INFO: Expecting 41600 events.
[11:32:26.839] <TB2> INFO: 41600 events read in total (3345ms).
[11:32:26.840] <TB2> INFO: Test took 4220ms.
[11:32:26.843] <TB2> INFO: scanning low vcal = 90
[11:32:27.120] <TB2> INFO: Expecting 41600 events.
[11:32:31.104] <TB2> INFO: 41600 events read in total (3393ms).
[11:32:31.106] <TB2> INFO: Test took 4263ms.
[11:32:31.109] <TB2> INFO: scanning low vcal = 100
[11:32:31.385] <TB2> INFO: Expecting 41600 events.
[11:32:35.333] <TB2> INFO: 41600 events read in total (3356ms).
[11:32:35.334] <TB2> INFO: Test took 4224ms.
[11:32:35.337] <TB2> INFO: scanning low vcal = 110
[11:32:35.614] <TB2> INFO: Expecting 41600 events.
[11:32:39.678] <TB2> INFO: 41600 events read in total (3472ms).
[11:32:39.679] <TB2> INFO: Test took 4342ms.
[11:32:39.682] <TB2> INFO: scanning low vcal = 120
[11:32:39.959] <TB2> INFO: Expecting 41600 events.
[11:32:43.961] <TB2> INFO: 41600 events read in total (3411ms).
[11:32:43.961] <TB2> INFO: Test took 4279ms.
[11:32:43.964] <TB2> INFO: scanning low vcal = 130
[11:32:44.243] <TB2> INFO: Expecting 41600 events.
[11:32:48.274] <TB2> INFO: 41600 events read in total (3439ms).
[11:32:48.276] <TB2> INFO: Test took 4312ms.
[11:32:48.279] <TB2> INFO: scanning low vcal = 140
[11:32:48.555] <TB2> INFO: Expecting 41600 events.
[11:32:52.573] <TB2> INFO: 41600 events read in total (3426ms).
[11:32:52.575] <TB2> INFO: Test took 4296ms.
[11:32:52.581] <TB2> INFO: scanning low vcal = 150
[11:32:52.855] <TB2> INFO: Expecting 41600 events.
[11:32:56.818] <TB2> INFO: 41600 events read in total (3372ms).
[11:32:56.819] <TB2> INFO: Test took 4238ms.
[11:32:56.822] <TB2> INFO: scanning low vcal = 160
[11:32:57.120] <TB2> INFO: Expecting 41600 events.
[11:33:01.115] <TB2> INFO: 41600 events read in total (3404ms).
[11:33:01.116] <TB2> INFO: Test took 4294ms.
[11:33:01.120] <TB2> INFO: scanning low vcal = 170
[11:33:01.396] <TB2> INFO: Expecting 41600 events.
[11:33:05.387] <TB2> INFO: 41600 events read in total (3399ms).
[11:33:05.388] <TB2> INFO: Test took 4268ms.
[11:33:05.393] <TB2> INFO: scanning low vcal = 180
[11:33:05.668] <TB2> INFO: Expecting 41600 events.
[11:33:09.713] <TB2> INFO: 41600 events read in total (3454ms).
[11:33:09.714] <TB2> INFO: Test took 4321ms.
[11:33:09.717] <TB2> INFO: scanning low vcal = 190
[11:33:09.993] <TB2> INFO: Expecting 41600 events.
[11:33:13.989] <TB2> INFO: 41600 events read in total (3404ms).
[11:33:13.990] <TB2> INFO: Test took 4273ms.
[11:33:13.993] <TB2> INFO: scanning low vcal = 200
[11:33:14.269] <TB2> INFO: Expecting 41600 events.
[11:33:18.332] <TB2> INFO: 41600 events read in total (3471ms).
[11:33:18.333] <TB2> INFO: Test took 4340ms.
[11:33:18.337] <TB2> INFO: scanning low vcal = 210
[11:33:18.613] <TB2> INFO: Expecting 41600 events.
[11:33:22.681] <TB2> INFO: 41600 events read in total (3477ms).
[11:33:22.682] <TB2> INFO: Test took 4345ms.
[11:33:22.685] <TB2> INFO: scanning low vcal = 220
[11:33:22.962] <TB2> INFO: Expecting 41600 events.
[11:33:27.035] <TB2> INFO: 41600 events read in total (3481ms).
[11:33:27.036] <TB2> INFO: Test took 4350ms.
[11:33:27.039] <TB2> INFO: scanning low vcal = 230
[11:33:27.368] <TB2> INFO: Expecting 41600 events.
[11:33:31.440] <TB2> INFO: 41600 events read in total (3480ms).
[11:33:31.440] <TB2> INFO: Test took 4400ms.
[11:33:31.445] <TB2> INFO: scanning low vcal = 240
[11:33:31.720] <TB2> INFO: Expecting 41600 events.
[11:33:35.684] <TB2> INFO: 41600 events read in total (3372ms).
[11:33:35.685] <TB2> INFO: Test took 4240ms.
[11:33:35.688] <TB2> INFO: scanning low vcal = 250
[11:33:35.964] <TB2> INFO: Expecting 41600 events.
[11:33:39.930] <TB2> INFO: 41600 events read in total (3374ms).
[11:33:39.930] <TB2> INFO: Test took 4242ms.
[11:33:39.934] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[11:33:40.210] <TB2> INFO: Expecting 41600 events.
[11:33:44.172] <TB2> INFO: 41600 events read in total (3370ms).
[11:33:44.173] <TB2> INFO: Test took 4239ms.
[11:33:44.175] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[11:33:44.453] <TB2> INFO: Expecting 41600 events.
[11:33:48.407] <TB2> INFO: 41600 events read in total (3363ms).
[11:33:48.408] <TB2> INFO: Test took 4232ms.
[11:33:48.411] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[11:33:48.687] <TB2> INFO: Expecting 41600 events.
[11:33:52.645] <TB2> INFO: 41600 events read in total (3366ms).
[11:33:52.646] <TB2> INFO: Test took 4235ms.
[11:33:52.649] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[11:33:52.926] <TB2> INFO: Expecting 41600 events.
[11:33:56.899] <TB2> INFO: 41600 events read in total (3381ms).
[11:33:56.900] <TB2> INFO: Test took 4251ms.
[11:33:56.903] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[11:33:57.180] <TB2> INFO: Expecting 41600 events.
[11:34:01.144] <TB2> INFO: 41600 events read in total (3373ms).
[11:34:01.145] <TB2> INFO: Test took 4242ms.
[11:34:01.585] <TB2> INFO: PixTestGainPedestal::measure() done
[11:34:43.771] <TB2> INFO: PixTestGainPedestal::fit() done
[11:34:43.771] <TB2> INFO: non-linearity mean: 0.935 0.984 0.963 0.966 0.979 0.954 0.989 0.987 0.948 0.961 0.938 0.946 0.933 0.962 0.988 0.934
[11:34:43.771] <TB2> INFO: non-linearity RMS: 0.097 0.004 0.146 0.028 0.006 0.075 0.173 0.003 0.068 0.052 0.063 0.081 0.091 0.144 0.003 0.121
[11:34:43.771] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr35_C0.dat
[11:34:43.784] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr35_C1.dat
[11:34:43.797] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr35_C2.dat
[11:34:43.811] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr35_C3.dat
[11:34:43.825] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr35_C4.dat
[11:34:43.839] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr35_C5.dat
[11:34:43.853] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr35_C6.dat
[11:34:43.868] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr35_C7.dat
[11:34:43.882] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr35_C8.dat
[11:34:43.896] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr35_C9.dat
[11:34:43.911] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr35_C10.dat
[11:34:43.924] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr35_C11.dat
[11:34:43.938] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr35_C12.dat
[11:34:43.952] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr35_C13.dat
[11:34:43.966] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr35_C14.dat
[11:34:43.981] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1043_FullQualification_2016-11-14_09h59m_1479113999//000_Fulltest_m20//phCalibrationFitErr35_C15.dat
[11:34:43.995] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 170 seconds
[11:34:43.995] <TB2> INFO: Decoding statistics:
[11:34:43.995] <TB2> INFO: General information:
[11:34:43.995] <TB2> INFO: 16bit words read: 3327286
[11:34:43.995] <TB2> INFO: valid events total: 332800
[11:34:43.995] <TB2> INFO: empty events: 0
[11:34:43.995] <TB2> INFO: valid events with pixels: 332800
[11:34:43.995] <TB2> INFO: valid pixel hits: 665243
[11:34:43.995] <TB2> INFO: Event errors: 0
[11:34:43.995] <TB2> INFO: start marker: 0
[11:34:43.995] <TB2> INFO: stop marker: 0
[11:34:43.995] <TB2> INFO: overflow: 0
[11:34:43.995] <TB2> INFO: invalid 5bit words: 0
[11:34:43.995] <TB2> INFO: invalid XOR eye diagram: 0
[11:34:43.995] <TB2> INFO: frame (failed synchr.): 0
[11:34:43.995] <TB2> INFO: idle data (no TBM trl): 0
[11:34:43.995] <TB2> INFO: no data (only TBM hdr): 0
[11:34:43.995] <TB2> INFO: TBM errors: 0
[11:34:43.995] <TB2> INFO: flawed TBM headers: 0
[11:34:43.995] <TB2> INFO: flawed TBM trailers: 0
[11:34:43.995] <TB2> INFO: event ID mismatches: 0
[11:34:43.995] <TB2> INFO: ROC errors: 0
[11:34:43.995] <TB2> INFO: missing ROC header(s): 0
[11:34:43.995] <TB2> INFO: misplaced readback start: 0
[11:34:43.995] <TB2> INFO: Pixel decoding errors: 0
[11:34:43.995] <TB2> INFO: pixel data incomplete: 0
[11:34:43.995] <TB2> INFO: pixel address: 0
[11:34:43.995] <TB2> INFO: pulse height fill bit: 0
[11:34:43.995] <TB2> INFO: buffer corruption: 0
[11:34:44.011] <TB2> INFO: Decoding statistics:
[11:34:44.011] <TB2> INFO: General information:
[11:34:44.011] <TB2> INFO: 16bit words read: 3456702
[11:34:44.011] <TB2> INFO: valid events total: 353536
[11:34:44.011] <TB2> INFO: empty events: 18236
[11:34:44.011] <TB2> INFO: valid events with pixels: 335300
[11:34:44.011] <TB2> INFO: valid pixel hits: 667743
[11:34:44.011] <TB2> INFO: Event errors: 0
[11:34:44.011] <TB2> INFO: start marker: 0
[11:34:44.011] <TB2> INFO: stop marker: 0
[11:34:44.011] <TB2> INFO: overflow: 0
[11:34:44.011] <TB2> INFO: invalid 5bit words: 0
[11:34:44.011] <TB2> INFO: invalid XOR eye diagram: 0
[11:34:44.011] <TB2> INFO: frame (failed synchr.): 0
[11:34:44.011] <TB2> INFO: idle data (no TBM trl): 0
[11:34:44.011] <TB2> INFO: no data (only TBM hdr): 0
[11:34:44.011] <TB2> INFO: TBM errors: 0
[11:34:44.011] <TB2> INFO: flawed TBM headers: 0
[11:34:44.011] <TB2> INFO: flawed TBM trailers: 0
[11:34:44.011] <TB2> INFO: event ID mismatches: 0
[11:34:44.011] <TB2> INFO: ROC errors: 0
[11:34:44.011] <TB2> INFO: missing ROC header(s): 0
[11:34:44.011] <TB2> INFO: misplaced readback start: 0
[11:34:44.011] <TB2> INFO: Pixel decoding errors: 0
[11:34:44.011] <TB2> INFO: pixel data incomplete: 0
[11:34:44.011] <TB2> INFO: pixel address: 0
[11:34:44.011] <TB2> INFO: pulse height fill bit: 0
[11:34:44.011] <TB2> INFO: buffer corruption: 0
[11:34:44.011] <TB2> INFO: enter test to run
[11:34:44.011] <TB2> INFO: test: exit no parameter change
[11:34:44.117] <TB2> QUIET: Connection to board 149 closed.
[11:34:44.118] <TB2> INFO: pXar: this is the end, my friend