[19:02:16.828] <TB2> INFO: *** Welcome to pxar ***
[19:02:16.828] <TB2> INFO: *** Today: 2016/10/26
[19:02:16.835] <TB2> INFO: *** Version: c8ba-dirty
[19:02:16.836] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C15.dat
[19:02:16.836] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[19:02:16.836] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//defaultMaskFile.dat
[19:02:16.836] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters_C15.dat
[19:02:16.891] <TB2> INFO: clk: 4
[19:02:16.891] <TB2> INFO: ctr: 4
[19:02:16.891] <TB2> INFO: sda: 19
[19:02:16.891] <TB2> INFO: tin: 9
[19:02:16.891] <TB2> INFO: level: 15
[19:02:16.891] <TB2> INFO: triggerdelay: 0
[19:02:16.891] <TB2> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[19:02:16.891] <TB2> INFO: Log level: INFO
[19:02:16.901] <TB2> INFO: Found DTB DTB_WXC55Z
[19:02:16.912] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[19:02:16.914] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[19:02:16.916] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[19:02:18.398] <TB2> INFO: DUT info:
[19:02:18.398] <TB2> INFO: The DUT currently contains the following objects:
[19:02:18.399] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[19:02:18.399] <TB2> INFO: TBM Core alpha (0): 7 registers set
[19:02:18.399] <TB2> INFO: TBM Core beta (1): 7 registers set
[19:02:18.399] <TB2> INFO: TBM Core alpha (2): 7 registers set
[19:02:18.399] <TB2> INFO: TBM Core beta (3): 7 registers set
[19:02:18.399] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[19:02:18.399] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:18.399] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:18.399] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:18.399] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:18.399] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:18.399] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:18.399] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:18.399] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:18.399] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:18.399] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:18.399] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:18.399] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:18.399] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:18.399] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:18.399] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:18.399] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[19:02:18.800] <TB2> INFO: enter 'restricted' command line mode
[19:02:18.800] <TB2> INFO: enter test to run
[19:02:18.800] <TB2> INFO: test: pretest no parameter change
[19:02:18.800] <TB2> INFO: running: pretest
[19:02:19.693] <TB2> INFO: ######################################################################
[19:02:19.693] <TB2> INFO: PixTestPretest::doTest()
[19:02:19.693] <TB2> INFO: ######################################################################
[19:02:19.694] <TB2> INFO: ----------------------------------------------------------------------
[19:02:19.694] <TB2> INFO: PixTestPretest::programROC()
[19:02:19.694] <TB2> INFO: ----------------------------------------------------------------------
[19:02:37.707] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[19:02:37.707] <TB2> INFO: IA differences per ROC: 19.3 20.1 18.5 21.7 16.1 18.5 17.7 17.7 17.7 19.3 20.1 18.5 18.5 17.7 16.9 18.5
[19:02:37.742] <TB2> INFO: ----------------------------------------------------------------------
[19:02:37.742] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[19:02:37.742] <TB2> INFO: ----------------------------------------------------------------------
[19:02:58.989] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 377.8 mA = 23.6125 mA/ROC
[19:02:58.989] <TB2> INFO: i(loss) [mA/ROC]: 18.5 18.5 18.5 19.3 19.3 18.5 19.3 18.5 18.5 19.3 18.5 18.5 18.5 20.1 18.5 18.5
[19:02:59.018] <TB2> INFO: ----------------------------------------------------------------------
[19:02:59.018] <TB2> INFO: PixTestPretest::findTiming()
[19:02:59.018] <TB2> INFO: ----------------------------------------------------------------------
[19:02:59.018] <TB2> INFO: PixTestCmd::init()

[19:03:30.288] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[19:03:30.288] <TB2> INFO: (success/tries = 100/100), width = 4
[19:03:31.790] <TB2> INFO: ----------------------------------------------------------------------
[19:03:31.790] <TB2> INFO: PixTestPretest::findWorkingPixel()
[19:03:31.790] <TB2> INFO: ----------------------------------------------------------------------
[19:03:31.881] <TB2> INFO: Expecting 231680 events.
[19:03:41.497] <TB2> INFO: 231680 events read in total (9025ms).
[19:03:41.506] <TB2> INFO: Test took 9714ms.
[19:03:41.751] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[19:03:41.779] <TB2> INFO: ----------------------------------------------------------------------
[19:03:41.779] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[19:03:41.779] <TB2> INFO: ----------------------------------------------------------------------
[19:03:41.872] <TB2> INFO: Expecting 231680 events.
[19:03:51.575] <TB2> INFO: 231680 events read in total (9112ms).
[19:03:51.582] <TB2> INFO: Test took 9799ms.
[19:03:51.842] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[19:03:51.842] <TB2> INFO: CalDel: 86 98 80 91 102 95 82 96 85 79 97 100 95 97 90 88
[19:03:51.842] <TB2> INFO: VthrComp: 51 51 51 51 52 51 51 53 51 51 51 51 51 51 51 51
[19:03:51.844] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C0.dat
[19:03:51.845] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C1.dat
[19:03:51.845] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C2.dat
[19:03:51.845] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C3.dat
[19:03:51.845] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C4.dat
[19:03:51.845] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C5.dat
[19:03:51.845] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C6.dat
[19:03:51.845] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C7.dat
[19:03:51.845] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C8.dat
[19:03:51.845] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C9.dat
[19:03:51.846] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C10.dat
[19:03:51.846] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C11.dat
[19:03:51.846] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C12.dat
[19:03:51.846] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C13.dat
[19:03:51.846] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C14.dat
[19:03:51.846] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters_C15.dat
[19:03:51.846] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[19:03:51.846] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[19:03:51.846] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[19:03:51.846] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[19:03:51.846] <TB2> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[19:03:51.942] <TB2> INFO: enter test to run
[19:03:51.942] <TB2> INFO: test: fulltest no parameter change
[19:03:51.942] <TB2> INFO: running: fulltest
[19:03:51.942] <TB2> INFO: ######################################################################
[19:03:51.942] <TB2> INFO: PixTestFullTest::doTest()
[19:03:51.942] <TB2> INFO: ######################################################################
[19:03:51.943] <TB2> INFO: ######################################################################
[19:03:51.943] <TB2> INFO: PixTestAlive::doTest()
[19:03:51.943] <TB2> INFO: ######################################################################
[19:03:51.944] <TB2> INFO: ----------------------------------------------------------------------
[19:03:51.944] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[19:03:51.944] <TB2> INFO: ----------------------------------------------------------------------
[19:03:52.182] <TB2> INFO: Expecting 41600 events.
[19:03:55.627] <TB2> INFO: 41600 events read in total (2853ms).
[19:03:55.627] <TB2> INFO: Test took 3682ms.
[19:03:55.853] <TB2> INFO: PixTestAlive::aliveTest() done
[19:03:55.853] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[19:03:55.854] <TB2> INFO: ----------------------------------------------------------------------
[19:03:55.854] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[19:03:55.854] <TB2> INFO: ----------------------------------------------------------------------
[19:03:56.088] <TB2> INFO: Expecting 41600 events.
[19:03:59.017] <TB2> INFO: 41600 events read in total (2337ms).
[19:03:59.018] <TB2> INFO: Test took 3163ms.
[19:03:59.018] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[19:03:59.255] <TB2> INFO: PixTestAlive::maskTest() done
[19:03:59.255] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[19:03:59.256] <TB2> INFO: ----------------------------------------------------------------------
[19:03:59.256] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[19:03:59.256] <TB2> INFO: ----------------------------------------------------------------------
[19:03:59.492] <TB2> INFO: Expecting 41600 events.
[19:04:02.943] <TB2> INFO: 41600 events read in total (2859ms).
[19:04:02.944] <TB2> INFO: Test took 3687ms.
[19:04:03.174] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[19:04:03.174] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[19:04:03.174] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[19:04:03.174] <TB2> INFO: Decoding statistics:
[19:04:03.174] <TB2> INFO: General information:
[19:04:03.174] <TB2> INFO: 16bit words read: 0
[19:04:03.174] <TB2> INFO: valid events total: 0
[19:04:03.174] <TB2> INFO: empty events: 0
[19:04:03.174] <TB2> INFO: valid events with pixels: 0
[19:04:03.174] <TB2> INFO: valid pixel hits: 0
[19:04:03.174] <TB2> INFO: Event errors: 0
[19:04:03.174] <TB2> INFO: start marker: 0
[19:04:03.174] <TB2> INFO: stop marker: 0
[19:04:03.174] <TB2> INFO: overflow: 0
[19:04:03.174] <TB2> INFO: invalid 5bit words: 0
[19:04:03.174] <TB2> INFO: invalid XOR eye diagram: 0
[19:04:03.174] <TB2> INFO: frame (failed synchr.): 0
[19:04:03.174] <TB2> INFO: idle data (no TBM trl): 0
[19:04:03.174] <TB2> INFO: no data (only TBM hdr): 0
[19:04:03.174] <TB2> INFO: TBM errors: 0
[19:04:03.174] <TB2> INFO: flawed TBM headers: 0
[19:04:03.174] <TB2> INFO: flawed TBM trailers: 0
[19:04:03.174] <TB2> INFO: event ID mismatches: 0
[19:04:03.174] <TB2> INFO: ROC errors: 0
[19:04:03.174] <TB2> INFO: missing ROC header(s): 0
[19:04:03.174] <TB2> INFO: misplaced readback start: 0
[19:04:03.174] <TB2> INFO: Pixel decoding errors: 0
[19:04:03.174] <TB2> INFO: pixel data incomplete: 0
[19:04:03.174] <TB2> INFO: pixel address: 0
[19:04:03.174] <TB2> INFO: pulse height fill bit: 0
[19:04:03.174] <TB2> INFO: buffer corruption: 0
[19:04:03.182] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C15.dat
[19:04:03.182] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[19:04:03.182] <TB2> INFO: ######################################################################
[19:04:03.182] <TB2> INFO: PixTestReadback::doTest()
[19:04:03.182] <TB2> INFO: ######################################################################
[19:04:03.182] <TB2> INFO: ----------------------------------------------------------------------
[19:04:03.182] <TB2> INFO: PixTestReadback::CalibrateVd()
[19:04:03.182] <TB2> INFO: ----------------------------------------------------------------------
[19:04:13.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C0.dat
[19:04:13.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C1.dat
[19:04:13.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C2.dat
[19:04:13.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C3.dat
[19:04:13.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C4.dat
[19:04:13.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C5.dat
[19:04:13.140] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C6.dat
[19:04:13.141] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C7.dat
[19:04:13.141] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C8.dat
[19:04:13.141] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C9.dat
[19:04:13.141] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C10.dat
[19:04:13.141] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C11.dat
[19:04:13.141] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C12.dat
[19:04:13.141] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C13.dat
[19:04:13.141] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C14.dat
[19:04:13.141] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C15.dat
[19:04:13.170] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[19:04:13.170] <TB2> INFO: ----------------------------------------------------------------------
[19:04:13.170] <TB2> INFO: PixTestReadback::CalibrateVa()
[19:04:13.170] <TB2> INFO: ----------------------------------------------------------------------
[19:04:23.060] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C0.dat
[19:04:23.060] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C1.dat
[19:04:23.060] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C2.dat
[19:04:23.060] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C3.dat
[19:04:23.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C4.dat
[19:04:23.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C5.dat
[19:04:23.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C6.dat
[19:04:23.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C7.dat
[19:04:23.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C8.dat
[19:04:23.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C9.dat
[19:04:23.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C10.dat
[19:04:23.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C11.dat
[19:04:23.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C12.dat
[19:04:23.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C13.dat
[19:04:23.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C14.dat
[19:04:23.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C15.dat
[19:04:23.089] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[19:04:23.089] <TB2> INFO: ----------------------------------------------------------------------
[19:04:23.089] <TB2> INFO: PixTestReadback::readbackVbg()
[19:04:23.089] <TB2> INFO: ----------------------------------------------------------------------
[19:04:30.729] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[19:04:30.729] <TB2> INFO: ----------------------------------------------------------------------
[19:04:30.729] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[19:04:30.729] <TB2> INFO: ----------------------------------------------------------------------
[19:04:30.729] <TB2> INFO: Vbg will be calibrated using Vd calibration
[19:04:30.729] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 152.7calibrated Vbg = 1.18081 :::*/*/*/*/
[19:04:30.729] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 161.3calibrated Vbg = 1.17059 :::*/*/*/*/
[19:04:30.729] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 155.3calibrated Vbg = 1.17123 :::*/*/*/*/
[19:04:30.729] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 146calibrated Vbg = 1.17363 :::*/*/*/*/
[19:04:30.729] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 158.9calibrated Vbg = 1.17962 :::*/*/*/*/
[19:04:30.729] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 159.1calibrated Vbg = 1.17139 :::*/*/*/*/
[19:04:30.729] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 163.4calibrated Vbg = 1.18097 :::*/*/*/*/
[19:04:30.729] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 152.9calibrated Vbg = 1.17765 :::*/*/*/*/
[19:04:30.729] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 143.5calibrated Vbg = 1.16786 :::*/*/*/*/
[19:04:30.729] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 156.6calibrated Vbg = 1.16816 :::*/*/*/*/
[19:04:30.729] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 159.5calibrated Vbg = 1.17151 :::*/*/*/*/
[19:04:30.729] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 161.2calibrated Vbg = 1.16135 :::*/*/*/*/
[19:04:30.729] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 153.9calibrated Vbg = 1.18026 :::*/*/*/*/
[19:04:30.729] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 151.8calibrated Vbg = 1.17276 :::*/*/*/*/
[19:04:30.729] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 160.4calibrated Vbg = 1.16512 :::*/*/*/*/
[19:04:30.729] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 149calibrated Vbg = 1.17173 :::*/*/*/*/
[19:04:30.731] <TB2> INFO: ----------------------------------------------------------------------
[19:04:30.731] <TB2> INFO: PixTestReadback::CalibrateIa()
[19:04:30.731] <TB2> INFO: ----------------------------------------------------------------------
[19:07:11.060] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C0.dat
[19:07:11.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C1.dat
[19:07:11.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C2.dat
[19:07:11.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C3.dat
[19:07:11.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C4.dat
[19:07:11.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C5.dat
[19:07:11.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C6.dat
[19:07:11.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C7.dat
[19:07:11.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C8.dat
[19:07:11.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C9.dat
[19:07:11.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C10.dat
[19:07:11.061] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C11.dat
[19:07:11.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C12.dat
[19:07:11.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C13.dat
[19:07:11.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C14.dat
[19:07:11.062] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//readbackCal_C15.dat
[19:07:11.088] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[19:07:11.090] <TB2> INFO: PixTestReadback::doTest() done
[19:07:11.090] <TB2> INFO: Decoding statistics:
[19:07:11.090] <TB2> INFO: General information:
[19:07:11.090] <TB2> INFO: 16bit words read: 1536
[19:07:11.090] <TB2> INFO: valid events total: 256
[19:07:11.090] <TB2> INFO: empty events: 256
[19:07:11.090] <TB2> INFO: valid events with pixels: 0
[19:07:11.090] <TB2> INFO: valid pixel hits: 0
[19:07:11.090] <TB2> INFO: Event errors: 0
[19:07:11.090] <TB2> INFO: start marker: 0
[19:07:11.090] <TB2> INFO: stop marker: 0
[19:07:11.090] <TB2> INFO: overflow: 0
[19:07:11.090] <TB2> INFO: invalid 5bit words: 0
[19:07:11.090] <TB2> INFO: invalid XOR eye diagram: 0
[19:07:11.090] <TB2> INFO: frame (failed synchr.): 0
[19:07:11.090] <TB2> INFO: idle data (no TBM trl): 0
[19:07:11.090] <TB2> INFO: no data (only TBM hdr): 0
[19:07:11.090] <TB2> INFO: TBM errors: 0
[19:07:11.090] <TB2> INFO: flawed TBM headers: 0
[19:07:11.090] <TB2> INFO: flawed TBM trailers: 0
[19:07:11.090] <TB2> INFO: event ID mismatches: 0
[19:07:11.090] <TB2> INFO: ROC errors: 0
[19:07:11.090] <TB2> INFO: missing ROC header(s): 0
[19:07:11.090] <TB2> INFO: misplaced readback start: 0
[19:07:11.090] <TB2> INFO: Pixel decoding errors: 0
[19:07:11.090] <TB2> INFO: pixel data incomplete: 0
[19:07:11.090] <TB2> INFO: pixel address: 0
[19:07:11.090] <TB2> INFO: pulse height fill bit: 0
[19:07:11.090] <TB2> INFO: buffer corruption: 0
[19:07:11.123] <TB2> INFO: ######################################################################
[19:07:11.123] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[19:07:11.123] <TB2> INFO: ######################################################################
[19:07:11.126] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[19:07:11.139] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[19:07:11.139] <TB2> INFO: run 1 of 1
[19:07:11.405] <TB2> INFO: Expecting 3120000 events.
[19:07:41.791] <TB2> INFO: 668050 events read in total (29794ms).
[19:08:11.395] <TB2> INFO: 1333440 events read in total (59398ms).











[19:08:40.977] <TB2> INFO: 1994240 events read in total (88980ms).











[19:09:10.666] <TB2> INFO: 2654090 events read in total (118669ms).











[19:09:32.040] <TB2> INFO: 3120000 events read in total (140043ms).
[19:09:32.099] <TB2> INFO: Test took 140961ms.
[19:09:58.644] <TB2> INFO: PixTestBBMap::doTest() done, duration: 167 seconds
[19:09:58.644] <TB2> INFO: number of dead bumps (per ROC): 1 0 0 0 3 1 1 2 0 0 0 1 0 0 1 0
[19:09:58.644] <TB2> INFO: separation cut (per ROC): 103 106 103 120 100 106 110 102 101 104 108 105 107 102 109 105
[19:09:58.644] <TB2> INFO: Decoding statistics:
[19:09:58.644] <TB2> INFO: General information:
[19:09:58.644] <TB2> INFO: 16bit words read: 0
[19:09:58.644] <TB2> INFO: valid events total: 0
[19:09:58.644] <TB2> INFO: empty events: 0
[19:09:58.644] <TB2> INFO: valid events with pixels: 0
[19:09:58.644] <TB2> INFO: valid pixel hits: 0
[19:09:58.644] <TB2> INFO: Event errors: 0
[19:09:58.644] <TB2> INFO: start marker: 0
[19:09:58.644] <TB2> INFO: stop marker: 0
[19:09:58.644] <TB2> INFO: overflow: 0
[19:09:58.644] <TB2> INFO: invalid 5bit words: 0
[19:09:58.644] <TB2> INFO: invalid XOR eye diagram: 0
[19:09:58.644] <TB2> INFO: frame (failed synchr.): 0
[19:09:58.644] <TB2> INFO: idle data (no TBM trl): 0
[19:09:58.644] <TB2> INFO: no data (only TBM hdr): 0
[19:09:58.644] <TB2> INFO: TBM errors: 0
[19:09:58.644] <TB2> INFO: flawed TBM headers: 0
[19:09:58.644] <TB2> INFO: flawed TBM trailers: 0
[19:09:58.644] <TB2> INFO: event ID mismatches: 0
[19:09:58.644] <TB2> INFO: ROC errors: 0
[19:09:58.644] <TB2> INFO: missing ROC header(s): 0
[19:09:58.644] <TB2> INFO: misplaced readback start: 0
[19:09:58.644] <TB2> INFO: Pixel decoding errors: 0
[19:09:58.645] <TB2> INFO: pixel data incomplete: 0
[19:09:58.645] <TB2> INFO: pixel address: 0
[19:09:58.645] <TB2> INFO: pulse height fill bit: 0
[19:09:58.645] <TB2> INFO: buffer corruption: 0
[19:09:58.681] <TB2> INFO: ######################################################################
[19:09:58.681] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[19:09:58.681] <TB2> INFO: ######################################################################
[19:09:58.681] <TB2> INFO: ----------------------------------------------------------------------
[19:09:58.681] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[19:09:58.681] <TB2> INFO: ----------------------------------------------------------------------
[19:09:58.681] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[19:09:58.690] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[19:09:58.690] <TB2> INFO: run 1 of 1
[19:09:58.956] <TB2> INFO: Expecting 36608000 events.
[19:10:22.700] <TB2> INFO: 693450 events read in total (23152ms).
[19:10:45.359] <TB2> INFO: 1368500 events read in total (45811ms).
[19:11:08.179] <TB2> INFO: 2042400 events read in total (68631ms).
[19:11:30.720] <TB2> INFO: 2715150 events read in total (91172ms).
[19:11:53.570] <TB2> INFO: 3389950 events read in total (114022ms).
[19:12:16.360] <TB2> INFO: 4064450 events read in total (136812ms).
[19:12:38.866] <TB2> INFO: 4740100 events read in total (159318ms).
[19:13:01.395] <TB2> INFO: 5411800 events read in total (181847ms).
[19:13:24.106] <TB2> INFO: 6086350 events read in total (204558ms).
[19:13:46.642] <TB2> INFO: 6756850 events read in total (227094ms).
[19:14:09.265] <TB2> INFO: 7430200 events read in total (249717ms).
[19:14:31.812] <TB2> INFO: 8102400 events read in total (272264ms).
[19:14:54.646] <TB2> INFO: 8774700 events read in total (295098ms).
[19:15:17.392] <TB2> INFO: 9446750 events read in total (317844ms).
[19:15:40.175] <TB2> INFO: 10116850 events read in total (340627ms).
[19:16:02.968] <TB2> INFO: 10788100 events read in total (363421ms).
[19:16:25.306] <TB2> INFO: 11458350 events read in total (385758ms).
[19:16:47.908] <TB2> INFO: 12128950 events read in total (408360ms).
[19:17:10.700] <TB2> INFO: 12796850 events read in total (431152ms).
[19:17:33.250] <TB2> INFO: 13468200 events read in total (453702ms).
[19:17:55.733] <TB2> INFO: 14134550 events read in total (476185ms).
[19:18:18.241] <TB2> INFO: 14804450 events read in total (498693ms).
[19:18:40.884] <TB2> INFO: 15470600 events read in total (521336ms).
[19:19:03.545] <TB2> INFO: 16139650 events read in total (543997ms).
[19:19:26.356] <TB2> INFO: 16806850 events read in total (566808ms).
[19:19:48.841] <TB2> INFO: 17475050 events read in total (589293ms).
[19:20:11.554] <TB2> INFO: 18142200 events read in total (612006ms).
[19:20:34.218] <TB2> INFO: 18809250 events read in total (634670ms).
[19:20:56.798] <TB2> INFO: 19472950 events read in total (657250ms).
[19:21:19.375] <TB2> INFO: 20139300 events read in total (679827ms).
[19:21:41.954] <TB2> INFO: 20803100 events read in total (702406ms).
[19:22:04.560] <TB2> INFO: 21467950 events read in total (725012ms).
[19:22:27.310] <TB2> INFO: 22131050 events read in total (747763ms).
[19:22:49.836] <TB2> INFO: 22794250 events read in total (770288ms).
[19:23:12.272] <TB2> INFO: 23457850 events read in total (792724ms).
[19:23:34.784] <TB2> INFO: 24119350 events read in total (815236ms).
[19:23:57.397] <TB2> INFO: 24782100 events read in total (837849ms).
[19:24:19.793] <TB2> INFO: 25443100 events read in total (860245ms).
[19:24:42.652] <TB2> INFO: 26106150 events read in total (883104ms).
[19:25:05.095] <TB2> INFO: 26765900 events read in total (905547ms).
[19:25:27.882] <TB2> INFO: 27427250 events read in total (928334ms).
[19:25:50.609] <TB2> INFO: 28087350 events read in total (951061ms).
[19:26:13.141] <TB2> INFO: 28748350 events read in total (973593ms).
[19:26:35.608] <TB2> INFO: 29407500 events read in total (996060ms).
[19:26:58.106] <TB2> INFO: 30067450 events read in total (1018558ms).
[19:27:20.388] <TB2> INFO: 30726300 events read in total (1040840ms).
[19:27:43.070] <TB2> INFO: 31385850 events read in total (1063522ms).
[19:28:05.437] <TB2> INFO: 32045500 events read in total (1085889ms).
[19:28:27.937] <TB2> INFO: 32706600 events read in total (1108389ms).
[19:28:50.109] <TB2> INFO: 33366850 events read in total (1130562ms).
[19:29:12.662] <TB2> INFO: 34027800 events read in total (1153114ms).
[19:29:35.155] <TB2> INFO: 34690250 events read in total (1175607ms).
[19:29:57.938] <TB2> INFO: 35351250 events read in total (1198390ms).
[19:30:20.469] <TB2> INFO: 36016150 events read in total (1220921ms).
[19:30:41.128] <TB2> INFO: 36608000 events read in total (1241580ms).
[19:30:41.200] <TB2> INFO: Test took 1242510ms.
[19:30:41.611] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:30:43.505] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:30:45.183] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:30:47.036] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:30:48.933] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:30:50.813] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:30:52.353] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:30:53.956] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:30:55.804] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:30:57.569] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:30:59.483] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:31:01.447] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:31:03.456] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:31:05.161] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:31:06.588] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:31:08.175] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[19:31:09.960] <TB2> INFO: PixTestScurves::scurves() done
[19:31:09.960] <TB2> INFO: Vcal mean: 113.58 124.20 106.51 122.26 122.74 113.38 119.68 121.97 107.52 120.75 123.13 126.39 112.82 115.35 130.41 115.77
[19:31:09.960] <TB2> INFO: Vcal RMS: 5.00 6.38 5.39 6.51 7.50 5.06 5.88 6.88 4.78 6.46 6.54 5.64 5.21 5.38 6.39 5.83
[19:31:09.960] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1271 seconds
[19:31:09.960] <TB2> INFO: Decoding statistics:
[19:31:09.960] <TB2> INFO: General information:
[19:31:09.960] <TB2> INFO: 16bit words read: 0
[19:31:09.960] <TB2> INFO: valid events total: 0
[19:31:09.960] <TB2> INFO: empty events: 0
[19:31:09.960] <TB2> INFO: valid events with pixels: 0
[19:31:09.960] <TB2> INFO: valid pixel hits: 0
[19:31:09.960] <TB2> INFO: Event errors: 0
[19:31:09.960] <TB2> INFO: start marker: 0
[19:31:09.960] <TB2> INFO: stop marker: 0
[19:31:09.960] <TB2> INFO: overflow: 0
[19:31:09.960] <TB2> INFO: invalid 5bit words: 0
[19:31:09.960] <TB2> INFO: invalid XOR eye diagram: 0
[19:31:09.960] <TB2> INFO: frame (failed synchr.): 0
[19:31:09.960] <TB2> INFO: idle data (no TBM trl): 0
[19:31:09.960] <TB2> INFO: no data (only TBM hdr): 0
[19:31:09.960] <TB2> INFO: TBM errors: 0
[19:31:09.960] <TB2> INFO: flawed TBM headers: 0
[19:31:09.960] <TB2> INFO: flawed TBM trailers: 0
[19:31:09.960] <TB2> INFO: event ID mismatches: 0
[19:31:09.960] <TB2> INFO: ROC errors: 0
[19:31:09.960] <TB2> INFO: missing ROC header(s): 0
[19:31:09.960] <TB2> INFO: misplaced readback start: 0
[19:31:09.960] <TB2> INFO: Pixel decoding errors: 0
[19:31:09.960] <TB2> INFO: pixel data incomplete: 0
[19:31:09.960] <TB2> INFO: pixel address: 0
[19:31:09.960] <TB2> INFO: pulse height fill bit: 0
[19:31:09.960] <TB2> INFO: buffer corruption: 0
[19:31:10.024] <TB2> INFO: ######################################################################
[19:31:10.024] <TB2> INFO: PixTestTrim::doTest()
[19:31:10.024] <TB2> INFO: ######################################################################
[19:31:10.025] <TB2> INFO: ----------------------------------------------------------------------
[19:31:10.025] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[19:31:10.025] <TB2> INFO: ----------------------------------------------------------------------
[19:31:10.067] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[19:31:10.067] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[19:31:10.075] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[19:31:10.075] <TB2> INFO: run 1 of 1
[19:31:10.308] <TB2> INFO: Expecting 5025280 events.
[19:31:40.686] <TB2> INFO: 826144 events read in total (29785ms).
[19:32:10.737] <TB2> INFO: 1650112 events read in total (59837ms).
[19:32:40.824] <TB2> INFO: 2471056 events read in total (89924ms).
[19:33:10.867] <TB2> INFO: 3289104 events read in total (119966ms).
[19:33:40.495] <TB2> INFO: 4104264 events read in total (149594ms).
[19:34:11.118] <TB2> INFO: 4918208 events read in total (180217ms).
[19:34:15.279] <TB2> INFO: 5025280 events read in total (184378ms).
[19:34:15.324] <TB2> INFO: Test took 185248ms.
[19:34:33.899] <TB2> INFO: ROC 0 VthrComp = 120
[19:34:33.899] <TB2> INFO: ROC 1 VthrComp = 120
[19:34:33.900] <TB2> INFO: ROC 2 VthrComp = 109
[19:34:33.900] <TB2> INFO: ROC 3 VthrComp = 131
[19:34:33.900] <TB2> INFO: ROC 4 VthrComp = 120
[19:34:33.900] <TB2> INFO: ROC 5 VthrComp = 115
[19:34:33.900] <TB2> INFO: ROC 6 VthrComp = 129
[19:34:33.900] <TB2> INFO: ROC 7 VthrComp = 117
[19:34:33.900] <TB2> INFO: ROC 8 VthrComp = 106
[19:34:33.900] <TB2> INFO: ROC 9 VthrComp = 126
[19:34:33.900] <TB2> INFO: ROC 10 VthrComp = 124
[19:34:33.901] <TB2> INFO: ROC 11 VthrComp = 120
[19:34:33.901] <TB2> INFO: ROC 12 VthrComp = 114
[19:34:33.901] <TB2> INFO: ROC 13 VthrComp = 118
[19:34:33.901] <TB2> INFO: ROC 14 VthrComp = 128
[19:34:33.901] <TB2> INFO: ROC 15 VthrComp = 117
[19:34:34.137] <TB2> INFO: Expecting 41600 events.
[19:34:37.666] <TB2> INFO: 41600 events read in total (2938ms).
[19:34:37.666] <TB2> INFO: Test took 3764ms.
[19:34:37.675] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[19:34:37.675] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[19:34:37.684] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[19:34:37.684] <TB2> INFO: run 1 of 1
[19:34:37.962] <TB2> INFO: Expecting 5025280 events.
[19:35:04.175] <TB2> INFO: 594056 events read in total (25622ms).
[19:35:29.964] <TB2> INFO: 1186744 events read in total (51411ms).
[19:35:55.356] <TB2> INFO: 1778824 events read in total (76803ms).
[19:36:21.261] <TB2> INFO: 2369680 events read in total (102708ms).
[19:36:46.583] <TB2> INFO: 2958176 events read in total (128030ms).
[19:37:12.299] <TB2> INFO: 3544800 events read in total (153746ms).
[19:37:38.027] <TB2> INFO: 4130064 events read in total (179474ms).
[19:38:03.463] <TB2> INFO: 4714912 events read in total (204910ms).
[19:38:17.676] <TB2> INFO: 5025280 events read in total (219123ms).
[19:38:17.736] <TB2> INFO: Test took 220052ms.
[19:38:43.320] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 58.222 for pixel 10/0 mean/min/max = 45.981/33.6973/58.2648
[19:38:43.320] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 66.4615 for pixel 0/10 mean/min/max = 49.3211/32.0793/66.563
[19:38:43.321] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 61.6184 for pixel 2/17 mean/min/max = 48.336/34.6439/62.028
[19:38:43.321] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 60.4434 for pixel 0/76 mean/min/max = 47.0811/33.6363/60.5259
[19:38:43.321] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 64.7239 for pixel 0/36 mean/min/max = 48.0751/31.2825/64.8676
[19:38:43.322] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 59.0585 for pixel 0/55 mean/min/max = 45.7345/32.4007/59.0682
[19:38:43.322] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 57.8291 for pixel 0/44 mean/min/max = 44.5252/31.2136/57.8369
[19:38:43.322] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 66.118 for pixel 17/0 mean/min/max = 49.3067/32.1155/66.4978
[19:38:43.322] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 62.9298 for pixel 2/26 mean/min/max = 48.8816/34.744/63.0192
[19:38:43.323] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 60.5732 for pixel 0/17 mean/min/max = 46.1814/31.7465/60.6163
[19:38:43.323] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 60.6034 for pixel 16/19 mean/min/max = 46.5112/32.3503/60.6721
[19:38:43.323] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 63.0763 for pixel 14/10 mean/min/max = 48.3385/33.552/63.1251
[19:38:43.323] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 60.8484 for pixel 13/0 mean/min/max = 46.7303/32.4682/60.9923
[19:38:43.324] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 59.5814 for pixel 0/78 mean/min/max = 45.599/31.5511/59.6468
[19:38:43.324] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 63.1837 for pixel 3/2 mean/min/max = 48.2342/33.0868/63.3816
[19:38:43.324] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 59.7351 for pixel 2/7 mean/min/max = 45.9064/32.0598/59.7529
[19:38:43.324] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[19:38:43.413] <TB2> INFO: Expecting 411648 events.
[19:38:52.586] <TB2> INFO: 411648 events read in total (8579ms).
[19:38:52.593] <TB2> INFO: Expecting 411648 events.
[19:39:01.548] <TB2> INFO: 411648 events read in total (8552ms).
[19:39:01.557] <TB2> INFO: Expecting 411648 events.
[19:39:10.604] <TB2> INFO: 411648 events read in total (8644ms).
[19:39:10.615] <TB2> INFO: Expecting 411648 events.
[19:39:19.638] <TB2> INFO: 411648 events read in total (8620ms).
[19:39:19.658] <TB2> INFO: Expecting 411648 events.
[19:39:28.660] <TB2> INFO: 411648 events read in total (8599ms).
[19:39:28.684] <TB2> INFO: Expecting 411648 events.
[19:39:37.682] <TB2> INFO: 411648 events read in total (8595ms).
[19:39:37.702] <TB2> INFO: Expecting 411648 events.
[19:39:46.766] <TB2> INFO: 411648 events read in total (8661ms).
[19:39:46.799] <TB2> INFO: Expecting 411648 events.
[19:39:55.830] <TB2> INFO: 411648 events read in total (8628ms).
[19:39:55.875] <TB2> INFO: Expecting 411648 events.
[19:40:04.962] <TB2> INFO: 411648 events read in total (8684ms).
[19:40:04.996] <TB2> INFO: Expecting 411648 events.
[19:40:14.020] <TB2> INFO: 411648 events read in total (8621ms).
[19:40:14.064] <TB2> INFO: Expecting 411648 events.
[19:40:23.120] <TB2> INFO: 411648 events read in total (8653ms).
[19:40:23.160] <TB2> INFO: Expecting 411648 events.
[19:40:32.174] <TB2> INFO: 411648 events read in total (8611ms).
[19:40:32.212] <TB2> INFO: Expecting 411648 events.
[19:40:41.393] <TB2> INFO: 411648 events read in total (8778ms).
[19:40:41.444] <TB2> INFO: Expecting 411648 events.
[19:40:50.450] <TB2> INFO: 411648 events read in total (8603ms).
[19:40:50.490] <TB2> INFO: Expecting 411648 events.
[19:40:59.648] <TB2> INFO: 411648 events read in total (8755ms).
[19:40:59.695] <TB2> INFO: Expecting 411648 events.
[19:41:08.900] <TB2> INFO: 411648 events read in total (8791ms).
[19:41:08.945] <TB2> INFO: Test took 145621ms.
[19:41:09.567] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[19:41:09.575] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[19:41:09.575] <TB2> INFO: run 1 of 1
[19:41:09.807] <TB2> INFO: Expecting 5025280 events.
[19:41:35.995] <TB2> INFO: 587280 events read in total (25596ms).
[19:42:01.837] <TB2> INFO: 1173960 events read in total (51438ms).
[19:42:27.464] <TB2> INFO: 1759984 events read in total (77065ms).
[19:42:53.127] <TB2> INFO: 2344440 events read in total (102728ms).
[19:43:19.234] <TB2> INFO: 2928808 events read in total (128836ms).
[19:43:44.554] <TB2> INFO: 3513544 events read in total (154155ms).
[19:44:10.069] <TB2> INFO: 4099536 events read in total (179670ms).
[19:44:35.736] <TB2> INFO: 4684992 events read in total (205337ms).
[19:44:51.238] <TB2> INFO: 5025280 events read in total (220840ms).
[19:44:51.339] <TB2> INFO: Test took 221764ms.
[19:45:15.226] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 2.849112 .. 147.111279
[19:45:15.470] <TB2> INFO: Expecting 208000 events.
[19:45:24.939] <TB2> INFO: 208000 events read in total (8877ms).
[19:45:24.940] <TB2> INFO: Test took 9713ms.
[19:45:24.985] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 157 (-1/-1) hits flags = 528 (plus default)
[19:45:24.995] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[19:45:24.995] <TB2> INFO: run 1 of 1
[19:45:25.273] <TB2> INFO: Expecting 5191680 events.
[19:45:51.249] <TB2> INFO: 583144 events read in total (25384ms).
[19:46:16.911] <TB2> INFO: 1166032 events read in total (51046ms).
[19:46:42.835] <TB2> INFO: 1749016 events read in total (76970ms).
[19:47:08.536] <TB2> INFO: 2332328 events read in total (102671ms).
[19:47:34.175] <TB2> INFO: 2915552 events read in total (128310ms).
[19:47:59.735] <TB2> INFO: 3497912 events read in total (153870ms).
[19:48:25.451] <TB2> INFO: 4079824 events read in total (179586ms).
[19:48:51.041] <TB2> INFO: 4660848 events read in total (205176ms).
[19:49:15.494] <TB2> INFO: 5191680 events read in total (229629ms).
[19:49:15.609] <TB2> INFO: Test took 230613ms.
[19:49:40.783] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 26.500000 .. 45.812010
[19:49:41.024] <TB2> INFO: Expecting 208000 events.
[19:49:50.534] <TB2> INFO: 208000 events read in total (8919ms).
[19:49:50.535] <TB2> INFO: Test took 9751ms.
[19:49:50.601] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 55 (-1/-1) hits flags = 528 (plus default)
[19:49:50.612] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[19:49:50.612] <TB2> INFO: run 1 of 1
[19:49:50.890] <TB2> INFO: Expecting 1331200 events.
[19:50:18.718] <TB2> INFO: 665200 events read in total (27237ms).
[19:50:46.642] <TB2> INFO: 1328784 events read in total (55161ms).
[19:50:47.195] <TB2> INFO: 1331200 events read in total (55715ms).
[19:50:47.224] <TB2> INFO: Test took 56612ms.
[19:51:01.659] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 27.161393 .. 49.512005
[19:51:01.900] <TB2> INFO: Expecting 208000 events.
[19:51:11.751] <TB2> INFO: 208000 events read in total (9259ms).
[19:51:11.752] <TB2> INFO: Test took 10092ms.
[19:51:11.802] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 59 (-1/-1) hits flags = 528 (plus default)
[19:51:11.810] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[19:51:11.811] <TB2> INFO: run 1 of 1
[19:51:12.089] <TB2> INFO: Expecting 1431040 events.
[19:51:39.811] <TB2> INFO: 646104 events read in total (27131ms).
[19:52:07.759] <TB2> INFO: 1291928 events read in total (55080ms).
[19:52:13.939] <TB2> INFO: 1431040 events read in total (61259ms).
[19:52:13.972] <TB2> INFO: Test took 62162ms.
[19:52:28.270] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 26.744660 .. 54.051930
[19:52:28.503] <TB2> INFO: Expecting 208000 events.
[19:52:38.130] <TB2> INFO: 208000 events read in total (9035ms).
[19:52:38.131] <TB2> INFO: Test took 9861ms.
[19:52:38.197] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 64 (-1/-1) hits flags = 528 (plus default)
[19:52:38.208] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[19:52:38.208] <TB2> INFO: run 1 of 1
[19:52:38.486] <TB2> INFO: Expecting 1630720 events.
[19:53:05.757] <TB2> INFO: 635544 events read in total (26680ms).
[19:53:32.937] <TB2> INFO: 1270952 events read in total (53861ms).
[19:53:48.274] <TB2> INFO: 1630720 events read in total (69197ms).
[19:53:48.303] <TB2> INFO: Test took 70095ms.
[19:54:02.698] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[19:54:02.699] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[19:54:02.707] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[19:54:02.707] <TB2> INFO: run 1 of 1
[19:54:02.961] <TB2> INFO: Expecting 1364480 events.
[19:54:30.767] <TB2> INFO: 668880 events read in total (27214ms).
[19:54:58.753] <TB2> INFO: 1337456 events read in total (55200ms).
[19:55:00.261] <TB2> INFO: 1364480 events read in total (56709ms).
[19:55:00.284] <TB2> INFO: Test took 57576ms.
[19:55:12.488] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C0.dat
[19:55:12.488] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C1.dat
[19:55:12.488] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C2.dat
[19:55:12.488] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C3.dat
[19:55:12.488] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C4.dat
[19:55:12.489] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C5.dat
[19:55:12.489] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C6.dat
[19:55:12.489] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C7.dat
[19:55:12.489] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C8.dat
[19:55:12.489] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C9.dat
[19:55:12.489] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C10.dat
[19:55:12.489] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C11.dat
[19:55:12.489] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C12.dat
[19:55:12.489] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C13.dat
[19:55:12.489] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C14.dat
[19:55:12.489] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C15.dat
[19:55:12.489] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C0.dat
[19:55:12.495] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C1.dat
[19:55:12.501] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C2.dat
[19:55:12.506] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C3.dat
[19:55:12.511] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C4.dat
[19:55:12.517] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C5.dat
[19:55:12.523] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C6.dat
[19:55:12.528] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C7.dat
[19:55:12.534] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C8.dat
[19:55:12.539] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C9.dat
[19:55:12.545] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C10.dat
[19:55:12.550] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C11.dat
[19:55:12.556] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C12.dat
[19:55:12.561] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C13.dat
[19:55:12.567] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C14.dat
[19:55:12.572] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters35_C15.dat
[19:55:12.578] <TB2> INFO: PixTestTrim::trimTest() done
[19:55:12.578] <TB2> INFO: vtrim: 138 131 130 142 118 113 141 151 158 128 147 152 145 125 155 127
[19:55:12.578] <TB2> INFO: vthrcomp: 120 120 109 131 120 115 129 117 106 126 124 120 114 118 128 117
[19:55:12.578] <TB2> INFO: vcal mean: 35.01 35.28 35.03 35.01 35.38 34.98 34.97 36.03 35.01 35.13 35.15 35.55 35.06 34.97 35.67 35.04
[19:55:12.578] <TB2> INFO: vcal RMS: 0.90 1.34 0.98 0.96 1.65 0.99 1.05 2.22 1.10 1.15 1.24 1.76 1.15 1.00 1.76 1.13
[19:55:12.578] <TB2> INFO: bits mean: 9.23 9.18 8.80 8.99 9.14 9.48 10.49 10.05 9.32 9.33 10.03 9.84 10.20 9.77 9.71 9.91
[19:55:12.578] <TB2> INFO: bits RMS: 2.55 2.65 2.50 2.62 2.92 2.72 2.40 2.39 2.32 2.84 2.43 2.39 2.29 2.68 2.51 2.52
[19:55:12.585] <TB2> INFO: ----------------------------------------------------------------------
[19:55:12.585] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[19:55:12.585] <TB2> INFO: ----------------------------------------------------------------------
[19:55:12.588] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[19:55:12.599] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[19:55:12.599] <TB2> INFO: run 1 of 1
[19:55:12.834] <TB2> INFO: Expecting 4160000 events.
[19:55:44.697] <TB2> INFO: 761665 events read in total (31271ms).
[19:56:15.924] <TB2> INFO: 1515915 events read in total (62498ms).
[19:56:47.226] <TB2> INFO: 2263625 events read in total (93800ms).
[19:57:18.357] <TB2> INFO: 3003980 events read in total (124931ms).
[19:57:49.634] <TB2> INFO: 3740855 events read in total (156208ms).
[19:58:08.402] <TB2> INFO: 4160000 events read in total (174976ms).
[19:58:08.464] <TB2> INFO: Test took 175865ms.
[19:58:34.775] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 202 (-1/-1) hits flags = 528 (plus default)
[19:58:34.785] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[19:58:34.785] <TB2> INFO: run 1 of 1
[19:58:35.016] <TB2> INFO: Expecting 4222400 events.
[19:59:06.692] <TB2> INFO: 733505 events read in total (31084ms).
[19:59:37.408] <TB2> INFO: 1459120 events read in total (61800ms).
[20:00:08.075] <TB2> INFO: 2179485 events read in total (92467ms).
[20:00:38.529] <TB2> INFO: 2894810 events read in total (122921ms).
[20:01:09.140] <TB2> INFO: 3606480 events read in total (153532ms).
[20:01:35.568] <TB2> INFO: 4222400 events read in total (179960ms).
[20:01:35.641] <TB2> INFO: Test took 180856ms.
[20:02:03.762] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[20:02:03.772] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[20:02:03.772] <TB2> INFO: run 1 of 1
[20:02:04.005] <TB2> INFO: Expecting 4097600 events.
[20:02:35.927] <TB2> INFO: 742060 events read in total (31330ms).
[20:03:06.882] <TB2> INFO: 1476100 events read in total (62285ms).
[20:03:38.005] <TB2> INFO: 2204615 events read in total (93408ms).
[20:04:08.869] <TB2> INFO: 2927350 events read in total (124272ms).
[20:04:39.752] <TB2> INFO: 3646300 events read in total (155155ms).
[20:04:59.718] <TB2> INFO: 4097600 events read in total (175121ms).
[20:04:59.771] <TB2> INFO: Test took 176000ms.
[20:05:25.242] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 192 (-1/-1) hits flags = 528 (plus default)
[20:05:25.253] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[20:05:25.253] <TB2> INFO: run 1 of 1
[20:05:25.509] <TB2> INFO: Expecting 4014400 events.
[20:05:57.751] <TB2> INFO: 747865 events read in total (31651ms).
[20:06:28.925] <TB2> INFO: 1487795 events read in total (62825ms).
[20:07:00.041] <TB2> INFO: 2221680 events read in total (93941ms).
[20:07:30.801] <TB2> INFO: 2949525 events read in total (124701ms).
[20:08:01.765] <TB2> INFO: 3674090 events read in total (155665ms).
[20:08:16.608] <TB2> INFO: 4014400 events read in total (170508ms).
[20:08:16.661] <TB2> INFO: Test took 171408ms.
[20:08:43.605] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 193 (-1/-1) hits flags = 528 (plus default)
[20:08:43.615] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[20:08:43.615] <TB2> INFO: run 1 of 1
[20:08:43.893] <TB2> INFO: Expecting 4035200 events.
[20:09:16.057] <TB2> INFO: 746710 events read in total (31573ms).
[20:09:47.227] <TB2> INFO: 1485570 events read in total (62743ms).
[20:10:18.111] <TB2> INFO: 2218365 events read in total (93627ms).
[20:10:48.949] <TB2> INFO: 2945345 events read in total (124465ms).
[20:11:19.829] <TB2> INFO: 3669195 events read in total (155345ms).
[20:11:35.579] <TB2> INFO: 4035200 events read in total (171095ms).
[20:11:35.629] <TB2> INFO: Test took 172014ms.
[20:12:04.529] <TB2> INFO: PixTestTrim::trimBitTest() done
[20:12:04.531] <TB2> INFO: PixTestTrim::doTest() done, duration: 2454 seconds
[20:12:04.531] <TB2> INFO: Decoding statistics:
[20:12:04.531] <TB2> INFO: General information:
[20:12:04.531] <TB2> INFO: 16bit words read: 0
[20:12:04.531] <TB2> INFO: valid events total: 0
[20:12:04.531] <TB2> INFO: empty events: 0
[20:12:04.531] <TB2> INFO: valid events with pixels: 0
[20:12:04.531] <TB2> INFO: valid pixel hits: 0
[20:12:04.531] <TB2> INFO: Event errors: 0
[20:12:04.531] <TB2> INFO: start marker: 0
[20:12:04.531] <TB2> INFO: stop marker: 0
[20:12:04.531] <TB2> INFO: overflow: 0
[20:12:04.531] <TB2> INFO: invalid 5bit words: 0
[20:12:04.531] <TB2> INFO: invalid XOR eye diagram: 0
[20:12:04.531] <TB2> INFO: frame (failed synchr.): 0
[20:12:04.531] <TB2> INFO: idle data (no TBM trl): 0
[20:12:04.531] <TB2> INFO: no data (only TBM hdr): 0
[20:12:04.531] <TB2> INFO: TBM errors: 0
[20:12:04.531] <TB2> INFO: flawed TBM headers: 0
[20:12:04.531] <TB2> INFO: flawed TBM trailers: 0
[20:12:04.531] <TB2> INFO: event ID mismatches: 0
[20:12:04.531] <TB2> INFO: ROC errors: 0
[20:12:04.531] <TB2> INFO: missing ROC header(s): 0
[20:12:04.531] <TB2> INFO: misplaced readback start: 0
[20:12:04.531] <TB2> INFO: Pixel decoding errors: 0
[20:12:04.531] <TB2> INFO: pixel data incomplete: 0
[20:12:04.531] <TB2> INFO: pixel address: 0
[20:12:04.531] <TB2> INFO: pulse height fill bit: 0
[20:12:04.531] <TB2> INFO: buffer corruption: 0
[20:12:05.151] <TB2> INFO: ######################################################################
[20:12:05.151] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[20:12:05.151] <TB2> INFO: ######################################################################
[20:12:05.426] <TB2> INFO: Expecting 41600 events.
[20:12:08.856] <TB2> INFO: 41600 events read in total (2838ms).
[20:12:08.857] <TB2> INFO: Test took 3704ms.
[20:12:09.303] <TB2> INFO: Expecting 41600 events.
[20:12:12.838] <TB2> INFO: 41600 events read in total (2943ms).
[20:12:12.839] <TB2> INFO: Test took 3777ms.
[20:12:13.129] <TB2> INFO: Expecting 41600 events.
[20:12:16.644] <TB2> INFO: 41600 events read in total (2924ms).
[20:12:16.645] <TB2> INFO: Test took 3781ms.
[20:12:16.940] <TB2> INFO: Expecting 41600 events.
[20:12:20.411] <TB2> INFO: 41600 events read in total (2879ms).
[20:12:20.412] <TB2> INFO: Test took 3740ms.
[20:12:20.700] <TB2> INFO: Expecting 41600 events.
[20:12:24.286] <TB2> INFO: 41600 events read in total (2994ms).
[20:12:24.287] <TB2> INFO: Test took 3852ms.
[20:12:24.578] <TB2> INFO: Expecting 41600 events.
[20:12:28.112] <TB2> INFO: 41600 events read in total (2943ms).
[20:12:28.113] <TB2> INFO: Test took 3800ms.
[20:12:28.402] <TB2> INFO: Expecting 41600 events.
[20:12:31.888] <TB2> INFO: 41600 events read in total (2894ms).
[20:12:31.888] <TB2> INFO: Test took 3751ms.
[20:12:32.179] <TB2> INFO: Expecting 41600 events.
[20:12:35.696] <TB2> INFO: 41600 events read in total (2925ms).
[20:12:35.697] <TB2> INFO: Test took 3783ms.
[20:12:35.985] <TB2> INFO: Expecting 41600 events.
[20:12:39.480] <TB2> INFO: 41600 events read in total (2903ms).
[20:12:39.481] <TB2> INFO: Test took 3760ms.
[20:12:39.769] <TB2> INFO: Expecting 41600 events.
[20:12:43.375] <TB2> INFO: 41600 events read in total (3014ms).
[20:12:43.376] <TB2> INFO: Test took 3872ms.
[20:12:43.664] <TB2> INFO: Expecting 41600 events.
[20:12:47.182] <TB2> INFO: 41600 events read in total (2927ms).
[20:12:47.183] <TB2> INFO: Test took 3784ms.
[20:12:47.471] <TB2> INFO: Expecting 41600 events.
[20:12:50.970] <TB2> INFO: 41600 events read in total (2907ms).
[20:12:50.971] <TB2> INFO: Test took 3765ms.
[20:12:51.260] <TB2> INFO: Expecting 41600 events.
[20:12:54.766] <TB2> INFO: 41600 events read in total (2915ms).
[20:12:54.766] <TB2> INFO: Test took 3771ms.
[20:12:55.054] <TB2> INFO: Expecting 41600 events.
[20:12:58.602] <TB2> INFO: 41600 events read in total (2956ms).
[20:12:58.602] <TB2> INFO: Test took 3812ms.
[20:12:58.890] <TB2> INFO: Expecting 41600 events.
[20:13:02.452] <TB2> INFO: 41600 events read in total (2970ms).
[20:13:02.452] <TB2> INFO: Test took 3827ms.
[20:13:02.740] <TB2> INFO: Expecting 41600 events.
[20:13:06.208] <TB2> INFO: 41600 events read in total (2876ms).
[20:13:06.209] <TB2> INFO: Test took 3733ms.
[20:13:06.498] <TB2> INFO: Expecting 41600 events.
[20:13:09.955] <TB2> INFO: 41600 events read in total (2866ms).
[20:13:09.956] <TB2> INFO: Test took 3723ms.
[20:13:10.244] <TB2> INFO: Expecting 41600 events.
[20:13:13.706] <TB2> INFO: 41600 events read in total (2870ms).
[20:13:13.706] <TB2> INFO: Test took 3727ms.
[20:13:13.994] <TB2> INFO: Expecting 41600 events.
[20:13:17.527] <TB2> INFO: 41600 events read in total (2941ms).
[20:13:17.528] <TB2> INFO: Test took 3798ms.
[20:13:17.816] <TB2> INFO: Expecting 41600 events.
[20:13:21.292] <TB2> INFO: 41600 events read in total (2884ms).
[20:13:21.293] <TB2> INFO: Test took 3741ms.
[20:13:21.581] <TB2> INFO: Expecting 41600 events.
[20:13:25.119] <TB2> INFO: 41600 events read in total (2946ms).
[20:13:25.120] <TB2> INFO: Test took 3804ms.
[20:13:25.411] <TB2> INFO: Expecting 41600 events.
[20:13:28.862] <TB2> INFO: 41600 events read in total (2860ms).
[20:13:28.863] <TB2> INFO: Test took 3717ms.
[20:13:29.151] <TB2> INFO: Expecting 41600 events.
[20:13:32.599] <TB2> INFO: 41600 events read in total (2856ms).
[20:13:32.599] <TB2> INFO: Test took 3713ms.
[20:13:32.888] <TB2> INFO: Expecting 41600 events.
[20:13:36.352] <TB2> INFO: 41600 events read in total (2872ms).
[20:13:36.353] <TB2> INFO: Test took 3730ms.
[20:13:36.643] <TB2> INFO: Expecting 41600 events.
[20:13:40.254] <TB2> INFO: 41600 events read in total (3019ms).
[20:13:40.255] <TB2> INFO: Test took 3877ms.
[20:13:40.543] <TB2> INFO: Expecting 41600 events.
[20:13:44.059] <TB2> INFO: 41600 events read in total (2925ms).
[20:13:44.060] <TB2> INFO: Test took 3782ms.
[20:13:44.348] <TB2> INFO: Expecting 41600 events.
[20:13:47.821] <TB2> INFO: 41600 events read in total (2881ms).
[20:13:47.821] <TB2> INFO: Test took 3738ms.
[20:13:48.111] <TB2> INFO: Expecting 41600 events.
[20:13:51.588] <TB2> INFO: 41600 events read in total (2885ms).
[20:13:51.589] <TB2> INFO: Test took 3743ms.
[20:13:51.877] <TB2> INFO: Expecting 2560 events.
[20:13:52.761] <TB2> INFO: 2560 events read in total (292ms).
[20:13:52.762] <TB2> INFO: Test took 1161ms.
[20:13:53.069] <TB2> INFO: Expecting 2560 events.
[20:13:53.952] <TB2> INFO: 2560 events read in total (291ms).
[20:13:53.952] <TB2> INFO: Test took 1190ms.
[20:13:54.260] <TB2> INFO: Expecting 2560 events.
[20:13:55.146] <TB2> INFO: 2560 events read in total (295ms).
[20:13:55.146] <TB2> INFO: Test took 1194ms.
[20:13:55.454] <TB2> INFO: Expecting 2560 events.
[20:13:56.337] <TB2> INFO: 2560 events read in total (291ms).
[20:13:56.337] <TB2> INFO: Test took 1191ms.
[20:13:56.645] <TB2> INFO: Expecting 2560 events.
[20:13:57.523] <TB2> INFO: 2560 events read in total (286ms).
[20:13:57.523] <TB2> INFO: Test took 1186ms.
[20:13:57.830] <TB2> INFO: Expecting 2560 events.
[20:13:58.709] <TB2> INFO: 2560 events read in total (287ms).
[20:13:58.709] <TB2> INFO: Test took 1186ms.
[20:13:59.017] <TB2> INFO: Expecting 2560 events.
[20:13:59.896] <TB2> INFO: 2560 events read in total (288ms).
[20:13:59.897] <TB2> INFO: Test took 1188ms.
[20:14:00.204] <TB2> INFO: Expecting 2560 events.
[20:14:01.083] <TB2> INFO: 2560 events read in total (287ms).
[20:14:01.083] <TB2> INFO: Test took 1186ms.
[20:14:01.391] <TB2> INFO: Expecting 2560 events.
[20:14:02.271] <TB2> INFO: 2560 events read in total (288ms).
[20:14:02.272] <TB2> INFO: Test took 1188ms.
[20:14:02.580] <TB2> INFO: Expecting 2560 events.
[20:14:03.458] <TB2> INFO: 2560 events read in total (287ms).
[20:14:03.458] <TB2> INFO: Test took 1186ms.
[20:14:03.766] <TB2> INFO: Expecting 2560 events.
[20:14:04.648] <TB2> INFO: 2560 events read in total (291ms).
[20:14:04.648] <TB2> INFO: Test took 1190ms.
[20:14:04.956] <TB2> INFO: Expecting 2560 events.
[20:14:05.836] <TB2> INFO: 2560 events read in total (287ms).
[20:14:05.836] <TB2> INFO: Test took 1187ms.
[20:14:06.144] <TB2> INFO: Expecting 2560 events.
[20:14:07.029] <TB2> INFO: 2560 events read in total (294ms).
[20:14:07.029] <TB2> INFO: Test took 1192ms.
[20:14:07.337] <TB2> INFO: Expecting 2560 events.
[20:14:08.222] <TB2> INFO: 2560 events read in total (293ms).
[20:14:08.222] <TB2> INFO: Test took 1193ms.
[20:14:08.530] <TB2> INFO: Expecting 2560 events.
[20:14:09.413] <TB2> INFO: 2560 events read in total (292ms).
[20:14:09.413] <TB2> INFO: Test took 1191ms.
[20:14:09.721] <TB2> INFO: Expecting 2560 events.
[20:14:10.607] <TB2> INFO: 2560 events read in total (294ms).
[20:14:10.607] <TB2> INFO: Test took 1193ms.
[20:14:10.610] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:14:10.916] <TB2> INFO: Expecting 655360 events.
[20:14:25.268] <TB2> INFO: 655360 events read in total (13760ms).
[20:14:25.280] <TB2> INFO: Expecting 655360 events.
[20:14:39.397] <TB2> INFO: 655360 events read in total (13714ms).
[20:14:39.413] <TB2> INFO: Expecting 655360 events.
[20:14:53.555] <TB2> INFO: 655360 events read in total (13739ms).
[20:14:53.574] <TB2> INFO: Expecting 655360 events.
[20:15:07.645] <TB2> INFO: 655360 events read in total (13668ms).
[20:15:07.668] <TB2> INFO: Expecting 655360 events.
[20:15:21.719] <TB2> INFO: 655360 events read in total (13647ms).
[20:15:21.755] <TB2> INFO: Expecting 655360 events.
[20:15:35.809] <TB2> INFO: 655360 events read in total (13651ms).
[20:15:35.841] <TB2> INFO: Expecting 655360 events.
[20:15:49.950] <TB2> INFO: 655360 events read in total (13706ms).
[20:15:49.986] <TB2> INFO: Expecting 655360 events.
[20:16:04.105] <TB2> INFO: 655360 events read in total (13716ms).
[20:16:04.159] <TB2> INFO: Expecting 655360 events.
[20:16:18.237] <TB2> INFO: 655360 events read in total (13675ms).
[20:16:18.282] <TB2> INFO: Expecting 655360 events.
[20:16:32.353] <TB2> INFO: 655360 events read in total (13668ms).
[20:16:32.404] <TB2> INFO: Expecting 655360 events.
[20:16:46.452] <TB2> INFO: 655360 events read in total (13645ms).
[20:16:46.506] <TB2> INFO: Expecting 655360 events.
[20:17:00.556] <TB2> INFO: 655360 events read in total (13647ms).
[20:17:00.635] <TB2> INFO: Expecting 655360 events.
[20:17:14.693] <TB2> INFO: 655360 events read in total (13655ms).
[20:17:14.777] <TB2> INFO: Expecting 655360 events.
[20:17:28.921] <TB2> INFO: 655360 events read in total (13741ms).
[20:17:28.990] <TB2> INFO: Expecting 655360 events.
[20:17:43.068] <TB2> INFO: 655360 events read in total (13675ms).
[20:17:43.139] <TB2> INFO: Expecting 655360 events.
[20:17:57.315] <TB2> INFO: 655360 events read in total (13773ms).
[20:17:57.392] <TB2> INFO: Test took 226782ms.
[20:17:57.471] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:17:57.736] <TB2> INFO: Expecting 655360 events.
[20:18:11.943] <TB2> INFO: 655360 events read in total (13616ms).
[20:18:11.957] <TB2> INFO: Expecting 655360 events.
[20:18:25.880] <TB2> INFO: 655360 events read in total (13520ms).
[20:18:25.896] <TB2> INFO: Expecting 655360 events.
[20:18:39.944] <TB2> INFO: 655360 events read in total (13645ms).
[20:18:39.963] <TB2> INFO: Expecting 655360 events.
[20:18:53.924] <TB2> INFO: 655360 events read in total (13558ms).
[20:18:53.954] <TB2> INFO: Expecting 655360 events.
[20:19:07.814] <TB2> INFO: 655360 events read in total (13457ms).
[20:19:07.841] <TB2> INFO: Expecting 655360 events.
[20:19:21.913] <TB2> INFO: 655360 events read in total (13669ms).
[20:19:21.943] <TB2> INFO: Expecting 655360 events.
[20:19:35.894] <TB2> INFO: 655360 events read in total (13548ms).
[20:19:35.929] <TB2> INFO: Expecting 655360 events.
[20:19:49.967] <TB2> INFO: 655360 events read in total (13635ms).
[20:19:50.005] <TB2> INFO: Expecting 655360 events.
[20:20:04.022] <TB2> INFO: 655360 events read in total (13614ms).
[20:20:04.083] <TB2> INFO: Expecting 655360 events.
[20:20:18.020] <TB2> INFO: 655360 events read in total (13534ms).
[20:20:18.070] <TB2> INFO: Expecting 655360 events.
[20:20:31.867] <TB2> INFO: 655360 events read in total (13394ms).
[20:20:31.919] <TB2> INFO: Expecting 655360 events.
[20:20:45.709] <TB2> INFO: 655360 events read in total (13387ms).
[20:20:45.765] <TB2> INFO: Expecting 655360 events.
[20:20:59.856] <TB2> INFO: 655360 events read in total (13688ms).
[20:20:59.917] <TB2> INFO: Expecting 655360 events.
[20:21:13.845] <TB2> INFO: 655360 events read in total (13525ms).
[20:21:13.910] <TB2> INFO: Expecting 655360 events.
[20:21:27.850] <TB2> INFO: 655360 events read in total (13537ms).
[20:21:27.920] <TB2> INFO: Expecting 655360 events.
[20:21:42.049] <TB2> INFO: 655360 events read in total (13725ms).
[20:21:42.121] <TB2> INFO: Test took 224650ms.
[20:21:42.276] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:42.281] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:42.286] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:42.290] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:42.294] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:42.299] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:42.303] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:42.308] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[20:21:42.312] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[20:21:42.317] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[20:21:42.321] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[20:21:42.326] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:42.330] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:42.334] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[20:21:42.339] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[20:21:42.343] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[20:21:42.348] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[20:21:42.352] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[20:21:42.357] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[20:21:42.361] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[20:21:42.366] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[20:21:42.370] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[20:21:42.375] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:42.379] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:42.384] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[20:21:42.388] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:42.393] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[20:21:42.397] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[20:21:42.402] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[20:21:42.406] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[20:21:42.411] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:42.415] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:42.420] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:42.425] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[20:21:42.429] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[20:21:42.434] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[20:21:42.438] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[20:21:42.443] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[20:21:42.448] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[20:21:42.481] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C0.dat
[20:21:42.481] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C1.dat
[20:21:42.481] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C2.dat
[20:21:42.481] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C3.dat
[20:21:42.481] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C4.dat
[20:21:42.482] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C5.dat
[20:21:42.482] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C6.dat
[20:21:42.482] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C7.dat
[20:21:42.482] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C8.dat
[20:21:42.482] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C9.dat
[20:21:42.482] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C10.dat
[20:21:42.482] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C11.dat
[20:21:42.482] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C12.dat
[20:21:42.482] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C13.dat
[20:21:42.482] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C14.dat
[20:21:42.482] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters35_C15.dat
[20:21:42.717] <TB2> INFO: Expecting 41600 events.
[20:21:45.797] <TB2> INFO: 41600 events read in total (2489ms).
[20:21:45.798] <TB2> INFO: Test took 3313ms.
[20:21:46.283] <TB2> INFO: Expecting 41600 events.
[20:21:49.303] <TB2> INFO: 41600 events read in total (2429ms).
[20:21:49.304] <TB2> INFO: Test took 3296ms.
[20:21:49.748] <TB2> INFO: Expecting 41600 events.
[20:21:52.868] <TB2> INFO: 41600 events read in total (2528ms).
[20:21:52.868] <TB2> INFO: Test took 3353ms.
[20:21:53.084] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:53.172] <TB2> INFO: Expecting 2560 events.
[20:21:54.055] <TB2> INFO: 2560 events read in total (291ms).
[20:21:54.056] <TB2> INFO: Test took 972ms.
[20:21:54.057] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:54.364] <TB2> INFO: Expecting 2560 events.
[20:21:55.250] <TB2> INFO: 2560 events read in total (294ms).
[20:21:55.250] <TB2> INFO: Test took 1193ms.
[20:21:55.252] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:55.559] <TB2> INFO: Expecting 2560 events.
[20:21:56.443] <TB2> INFO: 2560 events read in total (293ms).
[20:21:56.443] <TB2> INFO: Test took 1191ms.
[20:21:56.445] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:56.752] <TB2> INFO: Expecting 2560 events.
[20:21:57.634] <TB2> INFO: 2560 events read in total (291ms).
[20:21:57.635] <TB2> INFO: Test took 1190ms.
[20:21:57.636] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:57.943] <TB2> INFO: Expecting 2560 events.
[20:21:58.826] <TB2> INFO: 2560 events read in total (292ms).
[20:21:58.827] <TB2> INFO: Test took 1191ms.
[20:21:58.829] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:21:59.135] <TB2> INFO: Expecting 2560 events.
[20:22:00.019] <TB2> INFO: 2560 events read in total (292ms).
[20:22:00.019] <TB2> INFO: Test took 1190ms.
[20:22:00.021] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:00.328] <TB2> INFO: Expecting 2560 events.
[20:22:01.210] <TB2> INFO: 2560 events read in total (291ms).
[20:22:01.210] <TB2> INFO: Test took 1189ms.
[20:22:01.212] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:01.519] <TB2> INFO: Expecting 2560 events.
[20:22:02.402] <TB2> INFO: 2560 events read in total (292ms).
[20:22:02.402] <TB2> INFO: Test took 1190ms.
[20:22:02.404] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:02.711] <TB2> INFO: Expecting 2560 events.
[20:22:03.590] <TB2> INFO: 2560 events read in total (288ms).
[20:22:03.591] <TB2> INFO: Test took 1187ms.
[20:22:03.592] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:03.899] <TB2> INFO: Expecting 2560 events.
[20:22:04.780] <TB2> INFO: 2560 events read in total (289ms).
[20:22:04.780] <TB2> INFO: Test took 1188ms.
[20:22:04.782] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:05.088] <TB2> INFO: Expecting 2560 events.
[20:22:05.967] <TB2> INFO: 2560 events read in total (287ms).
[20:22:05.967] <TB2> INFO: Test took 1185ms.
[20:22:05.969] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:06.276] <TB2> INFO: Expecting 2560 events.
[20:22:07.157] <TB2> INFO: 2560 events read in total (290ms).
[20:22:07.157] <TB2> INFO: Test took 1188ms.
[20:22:07.159] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:07.466] <TB2> INFO: Expecting 2560 events.
[20:22:08.348] <TB2> INFO: 2560 events read in total (291ms).
[20:22:08.348] <TB2> INFO: Test took 1189ms.
[20:22:08.350] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:08.656] <TB2> INFO: Expecting 2560 events.
[20:22:09.536] <TB2> INFO: 2560 events read in total (288ms).
[20:22:09.536] <TB2> INFO: Test took 1186ms.
[20:22:09.538] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:09.844] <TB2> INFO: Expecting 2560 events.
[20:22:10.724] <TB2> INFO: 2560 events read in total (288ms).
[20:22:10.724] <TB2> INFO: Test took 1186ms.
[20:22:10.726] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:11.033] <TB2> INFO: Expecting 2560 events.
[20:22:11.911] <TB2> INFO: 2560 events read in total (287ms).
[20:22:11.911] <TB2> INFO: Test took 1185ms.
[20:22:11.913] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:12.220] <TB2> INFO: Expecting 2560 events.
[20:22:13.099] <TB2> INFO: 2560 events read in total (288ms).
[20:22:13.099] <TB2> INFO: Test took 1186ms.
[20:22:13.101] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:13.408] <TB2> INFO: Expecting 2560 events.
[20:22:14.285] <TB2> INFO: 2560 events read in total (286ms).
[20:22:14.285] <TB2> INFO: Test took 1184ms.
[20:22:14.287] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:14.593] <TB2> INFO: Expecting 2560 events.
[20:22:15.472] <TB2> INFO: 2560 events read in total (287ms).
[20:22:15.472] <TB2> INFO: Test took 1185ms.
[20:22:15.474] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:15.781] <TB2> INFO: Expecting 2560 events.
[20:22:16.663] <TB2> INFO: 2560 events read in total (288ms).
[20:22:16.663] <TB2> INFO: Test took 1189ms.
[20:22:16.664] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:16.971] <TB2> INFO: Expecting 2560 events.
[20:22:17.851] <TB2> INFO: 2560 events read in total (288ms).
[20:22:17.851] <TB2> INFO: Test took 1187ms.
[20:22:17.853] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:18.159] <TB2> INFO: Expecting 2560 events.
[20:22:19.038] <TB2> INFO: 2560 events read in total (287ms).
[20:22:19.039] <TB2> INFO: Test took 1186ms.
[20:22:19.040] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:19.347] <TB2> INFO: Expecting 2560 events.
[20:22:20.225] <TB2> INFO: 2560 events read in total (286ms).
[20:22:20.226] <TB2> INFO: Test took 1186ms.
[20:22:20.228] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:20.534] <TB2> INFO: Expecting 2560 events.
[20:22:21.412] <TB2> INFO: 2560 events read in total (286ms).
[20:22:21.413] <TB2> INFO: Test took 1186ms.
[20:22:21.414] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:21.721] <TB2> INFO: Expecting 2560 events.
[20:22:22.605] <TB2> INFO: 2560 events read in total (292ms).
[20:22:22.605] <TB2> INFO: Test took 1191ms.
[20:22:22.607] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:22.914] <TB2> INFO: Expecting 2560 events.
[20:22:23.797] <TB2> INFO: 2560 events read in total (292ms).
[20:22:23.797] <TB2> INFO: Test took 1190ms.
[20:22:23.799] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:24.105] <TB2> INFO: Expecting 2560 events.
[20:22:24.992] <TB2> INFO: 2560 events read in total (295ms).
[20:22:24.992] <TB2> INFO: Test took 1193ms.
[20:22:24.994] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:25.301] <TB2> INFO: Expecting 2560 events.
[20:22:26.184] <TB2> INFO: 2560 events read in total (292ms).
[20:22:26.184] <TB2> INFO: Test took 1190ms.
[20:22:26.186] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:26.492] <TB2> INFO: Expecting 2560 events.
[20:22:27.378] <TB2> INFO: 2560 events read in total (294ms).
[20:22:27.378] <TB2> INFO: Test took 1192ms.
[20:22:27.380] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:27.687] <TB2> INFO: Expecting 2560 events.
[20:22:28.569] <TB2> INFO: 2560 events read in total (291ms).
[20:22:28.569] <TB2> INFO: Test took 1189ms.
[20:22:28.571] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:28.878] <TB2> INFO: Expecting 2560 events.
[20:22:29.763] <TB2> INFO: 2560 events read in total (294ms).
[20:22:29.764] <TB2> INFO: Test took 1193ms.
[20:22:29.766] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:22:30.072] <TB2> INFO: Expecting 2560 events.
[20:22:30.956] <TB2> INFO: 2560 events read in total (293ms).
[20:22:30.957] <TB2> INFO: Test took 1192ms.
[20:22:31.420] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 626 seconds
[20:22:31.420] <TB2> INFO: PH scale (per ROC): 49 46 41 39 29 47 35 31 40 58 53 38 48 32 36 46
[20:22:31.420] <TB2> INFO: PH offset (per ROC): 103 102 99 109 85 107 101 105 112 122 116 101 110 107 97 109
[20:22:31.425] <TB2> INFO: Decoding statistics:
[20:22:31.425] <TB2> INFO: General information:
[20:22:31.425] <TB2> INFO: 16bit words read: 127890
[20:22:31.425] <TB2> INFO: valid events total: 20480
[20:22:31.425] <TB2> INFO: empty events: 17975
[20:22:31.425] <TB2> INFO: valid events with pixels: 2505
[20:22:31.425] <TB2> INFO: valid pixel hits: 2505
[20:22:31.425] <TB2> INFO: Event errors: 0
[20:22:31.426] <TB2> INFO: start marker: 0
[20:22:31.426] <TB2> INFO: stop marker: 0
[20:22:31.426] <TB2> INFO: overflow: 0
[20:22:31.426] <TB2> INFO: invalid 5bit words: 0
[20:22:31.426] <TB2> INFO: invalid XOR eye diagram: 0
[20:22:31.426] <TB2> INFO: frame (failed synchr.): 0
[20:22:31.426] <TB2> INFO: idle data (no TBM trl): 0
[20:22:31.426] <TB2> INFO: no data (only TBM hdr): 0
[20:22:31.426] <TB2> INFO: TBM errors: 0
[20:22:31.426] <TB2> INFO: flawed TBM headers: 0
[20:22:31.426] <TB2> INFO: flawed TBM trailers: 0
[20:22:31.426] <TB2> INFO: event ID mismatches: 0
[20:22:31.426] <TB2> INFO: ROC errors: 0
[20:22:31.426] <TB2> INFO: missing ROC header(s): 0
[20:22:31.426] <TB2> INFO: misplaced readback start: 0
[20:22:31.426] <TB2> INFO: Pixel decoding errors: 0
[20:22:31.426] <TB2> INFO: pixel data incomplete: 0
[20:22:31.426] <TB2> INFO: pixel address: 0
[20:22:31.426] <TB2> INFO: pulse height fill bit: 0
[20:22:31.426] <TB2> INFO: buffer corruption: 0
[20:22:31.779] <TB2> INFO: ######################################################################
[20:22:31.779] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[20:22:31.779] <TB2> INFO: ######################################################################
[20:22:31.791] <TB2> INFO: scanning low vcal = 10
[20:22:32.023] <TB2> INFO: Expecting 41600 events.
[20:22:35.592] <TB2> INFO: 41600 events read in total (2977ms).
[20:22:35.592] <TB2> INFO: Test took 3800ms.
[20:22:35.594] <TB2> INFO: scanning low vcal = 20
[20:22:35.893] <TB2> INFO: Expecting 41600 events.
[20:22:39.441] <TB2> INFO: 41600 events read in total (2956ms).
[20:22:39.442] <TB2> INFO: Test took 3848ms.
[20:22:39.443] <TB2> INFO: scanning low vcal = 30
[20:22:39.743] <TB2> INFO: Expecting 41600 events.
[20:22:43.389] <TB2> INFO: 41600 events read in total (3055ms).
[20:22:43.389] <TB2> INFO: Test took 3946ms.
[20:22:43.392] <TB2> INFO: scanning low vcal = 40
[20:22:43.672] <TB2> INFO: Expecting 41600 events.
[20:22:47.640] <TB2> INFO: 41600 events read in total (3376ms).
[20:22:47.641] <TB2> INFO: Test took 4249ms.
[20:22:47.644] <TB2> INFO: scanning low vcal = 50
[20:22:47.921] <TB2> INFO: Expecting 41600 events.
[20:22:51.905] <TB2> INFO: 41600 events read in total (3393ms).
[20:22:51.906] <TB2> INFO: Test took 4262ms.
[20:22:51.909] <TB2> INFO: scanning low vcal = 60
[20:22:52.186] <TB2> INFO: Expecting 41600 events.
[20:22:56.145] <TB2> INFO: 41600 events read in total (3368ms).
[20:22:56.146] <TB2> INFO: Test took 4237ms.
[20:22:56.148] <TB2> INFO: scanning low vcal = 70
[20:22:56.425] <TB2> INFO: Expecting 41600 events.
[20:23:00.363] <TB2> INFO: 41600 events read in total (3346ms).
[20:23:00.364] <TB2> INFO: Test took 4215ms.
[20:23:00.367] <TB2> INFO: scanning low vcal = 80
[20:23:00.643] <TB2> INFO: Expecting 41600 events.
[20:23:04.581] <TB2> INFO: 41600 events read in total (3346ms).
[20:23:04.582] <TB2> INFO: Test took 4215ms.
[20:23:04.584] <TB2> INFO: scanning low vcal = 90
[20:23:04.861] <TB2> INFO: Expecting 41600 events.
[20:23:08.810] <TB2> INFO: 41600 events read in total (3357ms).
[20:23:08.811] <TB2> INFO: Test took 4227ms.
[20:23:08.814] <TB2> INFO: scanning low vcal = 100
[20:23:09.090] <TB2> INFO: Expecting 41600 events.
[20:23:13.038] <TB2> INFO: 41600 events read in total (3356ms).
[20:23:13.039] <TB2> INFO: Test took 4225ms.
[20:23:13.041] <TB2> INFO: scanning low vcal = 110
[20:23:13.318] <TB2> INFO: Expecting 41600 events.
[20:23:17.271] <TB2> INFO: 41600 events read in total (3361ms).
[20:23:17.272] <TB2> INFO: Test took 4230ms.
[20:23:17.275] <TB2> INFO: scanning low vcal = 120
[20:23:17.551] <TB2> INFO: Expecting 41600 events.
[20:23:21.500] <TB2> INFO: 41600 events read in total (3357ms).
[20:23:21.500] <TB2> INFO: Test took 4225ms.
[20:23:21.503] <TB2> INFO: scanning low vcal = 130
[20:23:21.780] <TB2> INFO: Expecting 41600 events.
[20:23:25.755] <TB2> INFO: 41600 events read in total (3384ms).
[20:23:25.755] <TB2> INFO: Test took 4252ms.
[20:23:25.758] <TB2> INFO: scanning low vcal = 140
[20:23:26.035] <TB2> INFO: Expecting 41600 events.
[20:23:29.973] <TB2> INFO: 41600 events read in total (3346ms).
[20:23:29.974] <TB2> INFO: Test took 4216ms.
[20:23:29.977] <TB2> INFO: scanning low vcal = 150
[20:23:30.253] <TB2> INFO: Expecting 41600 events.
[20:23:34.187] <TB2> INFO: 41600 events read in total (3342ms).
[20:23:34.188] <TB2> INFO: Test took 4211ms.
[20:23:34.190] <TB2> INFO: scanning low vcal = 160
[20:23:34.467] <TB2> INFO: Expecting 41600 events.
[20:23:38.399] <TB2> INFO: 41600 events read in total (3340ms).
[20:23:38.399] <TB2> INFO: Test took 4209ms.
[20:23:38.402] <TB2> INFO: scanning low vcal = 170
[20:23:38.679] <TB2> INFO: Expecting 41600 events.
[20:23:42.643] <TB2> INFO: 41600 events read in total (3373ms).
[20:23:42.643] <TB2> INFO: Test took 4241ms.
[20:23:42.646] <TB2> INFO: scanning low vcal = 180
[20:23:42.922] <TB2> INFO: Expecting 41600 events.
[20:23:46.857] <TB2> INFO: 41600 events read in total (3343ms).
[20:23:46.858] <TB2> INFO: Test took 4212ms.
[20:23:46.860] <TB2> INFO: scanning low vcal = 190
[20:23:47.137] <TB2> INFO: Expecting 41600 events.
[20:23:51.098] <TB2> INFO: 41600 events read in total (3369ms).
[20:23:51.099] <TB2> INFO: Test took 4239ms.
[20:23:51.101] <TB2> INFO: scanning low vcal = 200
[20:23:51.378] <TB2> INFO: Expecting 41600 events.
[20:23:55.322] <TB2> INFO: 41600 events read in total (3352ms).
[20:23:55.323] <TB2> INFO: Test took 4221ms.
[20:23:55.325] <TB2> INFO: scanning low vcal = 210
[20:23:55.602] <TB2> INFO: Expecting 41600 events.
[20:23:59.544] <TB2> INFO: 41600 events read in total (3351ms).
[20:23:59.544] <TB2> INFO: Test took 4219ms.
[20:23:59.547] <TB2> INFO: scanning low vcal = 220
[20:23:59.824] <TB2> INFO: Expecting 41600 events.
[20:24:03.781] <TB2> INFO: 41600 events read in total (3366ms).
[20:24:03.781] <TB2> INFO: Test took 4235ms.
[20:24:03.784] <TB2> INFO: scanning low vcal = 230
[20:24:04.061] <TB2> INFO: Expecting 41600 events.
[20:24:07.002] <TB2> INFO: 41600 events read in total (3350ms).
[20:24:08.003] <TB2> INFO: Test took 4219ms.
[20:24:08.006] <TB2> INFO: scanning low vcal = 240
[20:24:08.282] <TB2> INFO: Expecting 41600 events.
[20:24:12.212] <TB2> INFO: 41600 events read in total (3338ms).
[20:24:12.212] <TB2> INFO: Test took 4206ms.
[20:24:12.215] <TB2> INFO: scanning low vcal = 250
[20:24:12.491] <TB2> INFO: Expecting 41600 events.
[20:24:16.469] <TB2> INFO: 41600 events read in total (3386ms).
[20:24:16.470] <TB2> INFO: Test took 4255ms.
[20:24:16.474] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[20:24:16.750] <TB2> INFO: Expecting 41600 events.
[20:24:20.720] <TB2> INFO: 41600 events read in total (3379ms).
[20:24:20.721] <TB2> INFO: Test took 4247ms.
[20:24:20.723] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[20:24:20.000] <TB2> INFO: Expecting 41600 events.
[20:24:25.020] <TB2> INFO: 41600 events read in total (3421ms).
[20:24:25.021] <TB2> INFO: Test took 4297ms.
[20:24:25.024] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[20:24:25.310] <TB2> INFO: Expecting 41600 events.
[20:24:29.272] <TB2> INFO: 41600 events read in total (3371ms).
[20:24:29.273] <TB2> INFO: Test took 4249ms.
[20:24:29.276] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[20:24:29.553] <TB2> INFO: Expecting 41600 events.
[20:24:33.520] <TB2> INFO: 41600 events read in total (3375ms).
[20:24:33.521] <TB2> INFO: Test took 4245ms.
[20:24:33.524] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[20:24:33.801] <TB2> INFO: Expecting 41600 events.
[20:24:37.757] <TB2> INFO: 41600 events read in total (3365ms).
[20:24:37.758] <TB2> INFO: Test took 4234ms.
[20:24:38.422] <TB2> INFO: PixTestGainPedestal::measure() done
[20:25:20.112] <TB2> INFO: PixTestGainPedestal::fit() done
[20:25:20.112] <TB2> INFO: non-linearity mean: 0.967 0.974 0.924 0.954 0.971 0.953 0.954 0.972 0.941 0.984 0.984 0.933 0.971 0.990 0.918 0.960
[20:25:20.112] <TB2> INFO: non-linearity RMS: 0.010 0.009 0.135 0.183 0.179 0.052 0.157 0.188 0.072 0.003 0.003 0.108 0.027 0.192 0.133 0.021
[20:25:20.112] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[20:25:20.131] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[20:25:20.150] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[20:25:20.169] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[20:25:20.187] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[20:25:20.206] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[20:25:20.227] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[20:25:20.247] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[20:25:20.266] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[20:25:20.289] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[20:25:20.312] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[20:25:20.329] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[20:25:20.344] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[20:25:20.364] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[20:25:20.382] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[20:25:20.402] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[20:25:20.421] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 168 seconds
[20:25:20.421] <TB2> INFO: Decoding statistics:
[20:25:20.421] <TB2> INFO: General information:
[20:25:20.421] <TB2> INFO: 16bit words read: 3268180
[20:25:20.421] <TB2> INFO: valid events total: 332800
[20:25:20.421] <TB2> INFO: empty events: 2378
[20:25:20.421] <TB2> INFO: valid events with pixels: 330422
[20:25:20.421] <TB2> INFO: valid pixel hits: 635690
[20:25:20.421] <TB2> INFO: Event errors: 0
[20:25:20.421] <TB2> INFO: start marker: 0
[20:25:20.421] <TB2> INFO: stop marker: 0
[20:25:20.421] <TB2> INFO: overflow: 0
[20:25:20.421] <TB2> INFO: invalid 5bit words: 0
[20:25:20.421] <TB2> INFO: invalid XOR eye diagram: 0
[20:25:20.421] <TB2> INFO: frame (failed synchr.): 0
[20:25:20.421] <TB2> INFO: idle data (no TBM trl): 0
[20:25:20.421] <TB2> INFO: no data (only TBM hdr): 0
[20:25:20.421] <TB2> INFO: TBM errors: 0
[20:25:20.421] <TB2> INFO: flawed TBM headers: 0
[20:25:20.421] <TB2> INFO: flawed TBM trailers: 0
[20:25:20.422] <TB2> INFO: event ID mismatches: 0
[20:25:20.422] <TB2> INFO: ROC errors: 0
[20:25:20.422] <TB2> INFO: missing ROC header(s): 0
[20:25:20.422] <TB2> INFO: misplaced readback start: 0
[20:25:20.422] <TB2> INFO: Pixel decoding errors: 0
[20:25:20.422] <TB2> INFO: pixel data incomplete: 0
[20:25:20.422] <TB2> INFO: pixel address: 0
[20:25:20.422] <TB2> INFO: pulse height fill bit: 0
[20:25:20.422] <TB2> INFO: buffer corruption: 0
[20:25:20.441] <TB2> INFO: Decoding statistics:
[20:25:20.441] <TB2> INFO: General information:
[20:25:20.441] <TB2> INFO: 16bit words read: 3397606
[20:25:20.441] <TB2> INFO: valid events total: 353536
[20:25:20.441] <TB2> INFO: empty events: 20609
[20:25:20.441] <TB2> INFO: valid events with pixels: 332927
[20:25:20.441] <TB2> INFO: valid pixel hits: 638195
[20:25:20.441] <TB2> INFO: Event errors: 0
[20:25:20.441] <TB2> INFO: start marker: 0
[20:25:20.441] <TB2> INFO: stop marker: 0
[20:25:20.441] <TB2> INFO: overflow: 0
[20:25:20.441] <TB2> INFO: invalid 5bit words: 0
[20:25:20.441] <TB2> INFO: invalid XOR eye diagram: 0
[20:25:20.441] <TB2> INFO: frame (failed synchr.): 0
[20:25:20.441] <TB2> INFO: idle data (no TBM trl): 0
[20:25:20.441] <TB2> INFO: no data (only TBM hdr): 0
[20:25:20.441] <TB2> INFO: TBM errors: 0
[20:25:20.441] <TB2> INFO: flawed TBM headers: 0
[20:25:20.441] <TB2> INFO: flawed TBM trailers: 0
[20:25:20.441] <TB2> INFO: event ID mismatches: 0
[20:25:20.441] <TB2> INFO: ROC errors: 0
[20:25:20.441] <TB2> INFO: missing ROC header(s): 0
[20:25:20.441] <TB2> INFO: misplaced readback start: 0
[20:25:20.441] <TB2> INFO: Pixel decoding errors: 0
[20:25:20.441] <TB2> INFO: pixel data incomplete: 0
[20:25:20.441] <TB2> INFO: pixel address: 0
[20:25:20.441] <TB2> INFO: pulse height fill bit: 0
[20:25:20.441] <TB2> INFO: buffer corruption: 0
[20:25:20.441] <TB2> INFO: enter test to run
[20:25:20.441] <TB2> INFO: test: Trim80 no parameter change
[20:25:20.441] <TB2> INFO: running: trim80
[20:25:20.464] <TB2> INFO: ######################################################################
[20:25:20.464] <TB2> INFO: PixTestTrim80::doTest()
[20:25:20.464] <TB2> INFO: ######################################################################
[20:25:20.465] <TB2> INFO: ----------------------------------------------------------------------
[20:25:20.465] <TB2> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[20:25:20.465] <TB2> INFO: ----------------------------------------------------------------------
[20:25:20.511] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[20:25:20.511] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[20:25:20.521] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:25:20.521] <TB2> INFO: run 1 of 1
[20:25:20.791] <TB2> INFO: Expecting 5025280 events.
[20:25:48.558] <TB2> INFO: 681016 events read in total (27174ms).
[20:26:15.517] <TB2> INFO: 1358800 events read in total (54133ms).
[20:26:42.551] <TB2> INFO: 2034056 events read in total (81167ms).
[20:27:09.723] <TB2> INFO: 2707992 events read in total (108339ms).
[20:27:36.373] <TB2> INFO: 3379040 events read in total (134989ms).
[20:28:03.322] <TB2> INFO: 4048288 events read in total (161938ms).
[20:28:30.006] <TB2> INFO: 4715848 events read in total (188622ms).
[20:28:42.529] <TB2> INFO: 5025280 events read in total (201145ms).
[20:28:42.587] <TB2> INFO: Test took 202066ms.
[20:29:06.534] <TB2> INFO: ROC 0 VthrComp = 71
[20:29:06.534] <TB2> INFO: ROC 1 VthrComp = 75
[20:29:06.534] <TB2> INFO: ROC 2 VthrComp = 63
[20:29:06.534] <TB2> INFO: ROC 3 VthrComp = 76
[20:29:06.535] <TB2> INFO: ROC 4 VthrComp = 74
[20:29:06.535] <TB2> INFO: ROC 5 VthrComp = 70
[20:29:06.535] <TB2> INFO: ROC 6 VthrComp = 74
[20:29:06.535] <TB2> INFO: ROC 7 VthrComp = 74
[20:29:06.535] <TB2> INFO: ROC 8 VthrComp = 64
[20:29:06.535] <TB2> INFO: ROC 9 VthrComp = 74
[20:29:06.535] <TB2> INFO: ROC 10 VthrComp = 74
[20:29:06.535] <TB2> INFO: ROC 11 VthrComp = 76
[20:29:06.535] <TB2> INFO: ROC 12 VthrComp = 70
[20:29:06.536] <TB2> INFO: ROC 13 VthrComp = 71
[20:29:06.536] <TB2> INFO: ROC 14 VthrComp = 79
[20:29:06.536] <TB2> INFO: ROC 15 VthrComp = 71
[20:29:06.784] <TB2> INFO: Expecting 41600 events.
[20:29:10.226] <TB2> INFO: 41600 events read in total (2850ms).
[20:29:10.227] <TB2> INFO: Test took 3689ms.
[20:29:10.236] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[20:29:10.236] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[20:29:10.245] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:29:10.245] <TB2> INFO: run 1 of 1
[20:29:10.523] <TB2> INFO: Expecting 5025280 events.
[20:29:38.151] <TB2> INFO: 686264 events read in total (27037ms).
[20:30:05.067] <TB2> INFO: 1367440 events read in total (53953ms).
[20:30:31.964] <TB2> INFO: 2047056 events read in total (80850ms).
[20:30:58.953] <TB2> INFO: 2723056 events read in total (107839ms).
[20:31:25.873] <TB2> INFO: 3396000 events read in total (134760ms).
[20:31:52.623] <TB2> INFO: 4065768 events read in total (161509ms).
[20:32:19.143] <TB2> INFO: 4736184 events read in total (188029ms).
[20:32:30.693] <TB2> INFO: 5025280 events read in total (199579ms).
[20:32:30.739] <TB2> INFO: Test took 200494ms.
[20:32:56.152] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 104.334 for pixel 0/62 mean/min/max = 89.0224/73.6815/104.363
[20:32:56.153] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 113.297 for pixel 0/2 mean/min/max = 95.2514/76.9927/113.51
[20:32:56.154] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 108.101 for pixel 0/19 mean/min/max = 91.4982/74.8031/108.193
[20:32:56.154] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 110.162 for pixel 0/26 mean/min/max = 94.1595/77.9235/110.396
[20:32:56.155] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 115.213 for pixel 0/13 mean/min/max = 95.4482/75.1866/115.71
[20:32:56.155] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 104.583 for pixel 0/3 mean/min/max = 89.1914/73.7588/104.624
[20:32:56.155] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 108.651 for pixel 5/72 mean/min/max = 92.7109/76.6535/108.768
[20:32:56.156] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 114.957 for pixel 0/71 mean/min/max = 96.292/77.4319/115.152
[20:32:56.156] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 105.759 for pixel 0/56 mean/min/max = 90.7644/75.4838/106.045
[20:32:56.157] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 111.141 for pixel 1/22 mean/min/max = 94.2518/77.2573/111.246
[20:32:56.157] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 111.81 for pixel 0/30 mean/min/max = 94.7785/77.4996/112.057
[20:32:56.157] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 110.407 for pixel 4/57 mean/min/max = 94.5141/78.5839/110.444
[20:32:56.158] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 105.853 for pixel 0/37 mean/min/max = 89.8237/73.7913/105.856
[20:32:56.158] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 105.413 for pixel 0/3 mean/min/max = 90.2339/74.8432/105.625
[20:32:56.158] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 111.793 for pixel 22/8 mean/min/max = 94.7322/77.6189/111.845
[20:32:56.159] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 107.308 for pixel 0/62 mean/min/max = 90.3761/73.3758/107.376
[20:32:56.159] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[20:32:56.247] <TB2> INFO: Expecting 411648 events.
[20:33:05.625] <TB2> INFO: 411648 events read in total (8786ms).
[20:33:05.634] <TB2> INFO: Expecting 411648 events.
[20:33:14.643] <TB2> INFO: 411648 events read in total (8606ms).
[20:33:14.653] <TB2> INFO: Expecting 411648 events.
[20:33:23.787] <TB2> INFO: 411648 events read in total (8731ms).
[20:33:23.799] <TB2> INFO: Expecting 411648 events.
[20:33:32.894] <TB2> INFO: 411648 events read in total (8692ms).
[20:33:32.908] <TB2> INFO: Expecting 411648 events.
[20:33:41.984] <TB2> INFO: 411648 events read in total (8673ms).
[20:33:41.002] <TB2> INFO: Expecting 411648 events.
[20:33:51.045] <TB2> INFO: 411648 events read in total (8640ms).
[20:33:51.064] <TB2> INFO: Expecting 411648 events.
[20:34:00.124] <TB2> INFO: 411648 events read in total (8657ms).
[20:34:00.147] <TB2> INFO: Expecting 411648 events.
[20:34:09.238] <TB2> INFO: 411648 events read in total (8688ms).
[20:34:09.263] <TB2> INFO: Expecting 411648 events.
[20:34:18.329] <TB2> INFO: 411648 events read in total (8663ms).
[20:34:18.357] <TB2> INFO: Expecting 411648 events.
[20:34:27.432] <TB2> INFO: 411648 events read in total (8672ms).
[20:34:27.463] <TB2> INFO: Expecting 411648 events.
[20:34:36.536] <TB2> INFO: 411648 events read in total (8670ms).
[20:34:36.582] <TB2> INFO: Expecting 411648 events.
[20:34:45.640] <TB2> INFO: 411648 events read in total (8655ms).
[20:34:45.689] <TB2> INFO: Expecting 411648 events.
[20:34:54.851] <TB2> INFO: 411648 events read in total (8759ms).
[20:34:54.903] <TB2> INFO: Expecting 411648 events.
[20:35:03.968] <TB2> INFO: 411648 events read in total (8662ms).
[20:35:04.019] <TB2> INFO: Expecting 411648 events.
[20:35:13.026] <TB2> INFO: 411648 events read in total (8604ms).
[20:35:13.072] <TB2> INFO: Expecting 411648 events.
[20:35:22.247] <TB2> INFO: 411648 events read in total (8772ms).
[20:35:22.304] <TB2> INFO: Test took 146145ms.
[20:35:23.887] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[20:35:23.896] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:35:23.896] <TB2> INFO: run 1 of 1
[20:35:24.139] <TB2> INFO: Expecting 5025280 events.
[20:35:51.785] <TB2> INFO: 669816 events read in total (27054ms).
[20:36:18.790] <TB2> INFO: 1335856 events read in total (54059ms).
[20:36:45.704] <TB2> INFO: 2000656 events read in total (80973ms).
[20:37:11.973] <TB2> INFO: 2662632 events read in total (107242ms).
[20:37:38.717] <TB2> INFO: 3319920 events read in total (133986ms).
[20:38:05.101] <TB2> INFO: 3976472 events read in total (160370ms).
[20:38:31.875] <TB2> INFO: 4630104 events read in total (187144ms).
[20:38:47.813] <TB2> INFO: 5025280 events read in total (203082ms).
[20:38:47.876] <TB2> INFO: Test took 203980ms.
[20:39:12.975] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 53.807607 .. 100.884104
[20:39:13.211] <TB2> INFO: Expecting 208000 events.
[20:39:23.411] <TB2> INFO: 208000 events read in total (9609ms).
[20:39:23.412] <TB2> INFO: Test took 10435ms.
[20:39:23.457] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 43 .. 110 (-1/-1) hits flags = 528 (plus default)
[20:39:23.466] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:39:23.466] <TB2> INFO: run 1 of 1
[20:39:23.771] <TB2> INFO: Expecting 2263040 events.
[20:39:51.493] <TB2> INFO: 690336 events read in total (27130ms).
[20:40:18.910] <TB2> INFO: 1377040 events read in total (54548ms).
[20:40:46.664] <TB2> INFO: 2055936 events read in total (82301ms).
[20:40:55.398] <TB2> INFO: 2263040 events read in total (91035ms).
[20:40:55.436] <TB2> INFO: Test took 91969ms.
[20:41:14.677] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 62.621323 .. 89.550077
[20:41:14.951] <TB2> INFO: Expecting 208000 events.
[20:41:24.770] <TB2> INFO: 208000 events read in total (9227ms).
[20:41:24.771] <TB2> INFO: Test took 10092ms.
[20:41:24.840] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 52 .. 99 (-1/-1) hits flags = 528 (plus default)
[20:41:24.851] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:41:24.851] <TB2> INFO: run 1 of 1
[20:41:25.129] <TB2> INFO: Expecting 1597440 events.
[20:41:53.487] <TB2> INFO: 701920 events read in total (27766ms).
[20:42:21.501] <TB2> INFO: 1402664 events read in total (55780ms).
[20:42:29.671] <TB2> INFO: 1597440 events read in total (63950ms).
[20:42:29.698] <TB2> INFO: Test took 64847ms.
[20:42:46.705] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 65.199697 .. 85.333341
[20:42:46.938] <TB2> INFO: Expecting 208000 events.
[20:42:56.584] <TB2> INFO: 208000 events read in total (9055ms).
[20:42:56.585] <TB2> INFO: Test took 9879ms.
[20:42:56.633] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 55 .. 95 (-1/-1) hits flags = 528 (plus default)
[20:42:56.642] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:42:56.642] <TB2> INFO: run 1 of 1
[20:42:56.920] <TB2> INFO: Expecting 1364480 events.
[20:43:25.685] <TB2> INFO: 713056 events read in total (28174ms).
[20:43:52.014] <TB2> INFO: 1364480 events read in total (54503ms).
[20:43:52.040] <TB2> INFO: Test took 55398ms.
[20:44:08.947] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 68.693582 .. 85.039662
[20:44:09.193] <TB2> INFO: Expecting 208000 events.
[20:44:19.015] <TB2> INFO: 208000 events read in total (9231ms).
[20:44:19.016] <TB2> INFO: Test took 10067ms.
[20:44:19.064] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 58 .. 95 (-1/-1) hits flags = 528 (plus default)
[20:44:19.076] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:44:19.076] <TB2> INFO: run 1 of 1
[20:44:19.354] <TB2> INFO: Expecting 1264640 events.
[20:44:48.184] <TB2> INFO: 703320 events read in total (28238ms).
[20:45:10.763] <TB2> INFO: 1264640 events read in total (50818ms).
[20:45:10.796] <TB2> INFO: Test took 51721ms.
[20:45:28.090] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[20:45:28.090] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[20:45:28.101] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[20:45:28.101] <TB2> INFO: run 1 of 1
[20:45:28.372] <TB2> INFO: Expecting 1364480 events.
[20:45:56.412] <TB2> INFO: 668432 events read in total (27449ms).
[20:46:23.907] <TB2> INFO: 1336520 events read in total (54944ms).
[20:46:25.527] <TB2> INFO: 1364480 events read in total (56564ms).
[20:46:25.546] <TB2> INFO: Test took 57444ms.
[20:46:43.360] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C0.dat
[20:46:43.360] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C1.dat
[20:46:43.360] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C2.dat
[20:46:43.360] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C3.dat
[20:46:43.360] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C4.dat
[20:46:43.361] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C5.dat
[20:46:43.361] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C6.dat
[20:46:43.361] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C7.dat
[20:46:43.361] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C8.dat
[20:46:43.361] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C9.dat
[20:46:43.361] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C10.dat
[20:46:43.361] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C11.dat
[20:46:43.361] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C12.dat
[20:46:43.361] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C13.dat
[20:46:43.361] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C14.dat
[20:46:43.361] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//dacParameters80_C15.dat
[20:46:43.362] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C0.dat
[20:46:43.368] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C1.dat
[20:46:43.373] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C2.dat
[20:46:43.379] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C3.dat
[20:46:43.385] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C4.dat
[20:46:43.390] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C5.dat
[20:46:43.396] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C6.dat
[20:46:43.401] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C7.dat
[20:46:43.407] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C8.dat
[20:46:43.412] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C9.dat
[20:46:43.418] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C10.dat
[20:46:43.423] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C11.dat
[20:46:43.429] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C12.dat
[20:46:43.436] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C13.dat
[20:46:43.444] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C14.dat
[20:46:43.451] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1036_FullQualification_2016-10-26_16h26m_1477492000//003_FulltestTrim80_p17//trimParameters80_C15.dat
[20:46:43.456] <TB2> INFO: PixTestTrim80::trimTest() done
[20:46:43.456] <TB2> INFO: vtrim: 97 102 101 116 112 89 109 110 91 114 124 113 88 94 136 91
[20:46:43.456] <TB2> INFO: vthrcomp: 71 75 63 76 74 70 74 74 64 74 74 76 70 71 79 71
[20:46:43.456] <TB2> INFO: vcal mean: 79.94 79.97 79.99 79.99 79.97 79.94 79.96 79.99 80.00 79.96 79.96 80.02 79.96 80.00 79.94 79.95
[20:46:43.456] <TB2> INFO: vcal RMS: 0.72 0.84 0.73 0.72 0.87 0.75 0.74 0.84 0.70 0.75 0.75 0.77 0.75 0.72 0.79 0.72
[20:46:43.456] <TB2> INFO: bits mean: 10.61 9.43 10.66 9.61 9.81 10.86 9.98 9.04 10.00 9.67 9.88 9.57 10.37 10.34 10.24 10.40
[20:46:43.456] <TB2> INFO: bits RMS: 2.41 2.30 2.13 2.14 2.28 2.32 2.14 2.32 2.42 2.19 2.04 2.08 2.51 2.36 1.90 2.46
[20:46:43.463] <TB2> INFO: ----------------------------------------------------------------------
[20:46:43.464] <TB2> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[20:46:43.464] <TB2> INFO: ----------------------------------------------------------------------
[20:46:43.467] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[20:46:43.479] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[20:46:43.479] <TB2> INFO: run 1 of 1
[20:46:43.714] <TB2> INFO: Expecting 4160000 events.
[20:47:15.739] <TB2> INFO: 761315 events read in total (31433ms).
[20:47:47.473] <TB2> INFO: 1515415 events read in total (63167ms).
[20:48:18.799] <TB2> INFO: 2262975 events read in total (94493ms).
[20:48:49.705] <TB2> INFO: 3003610 events read in total (125399ms).
[20:49:20.711] <TB2> INFO: 3740280 events read in total (156405ms).
[20:49:38.821] <TB2> INFO: 4160000 events read in total (174515ms).
[20:49:38.868] <TB2> INFO: Test took 175389ms.
[20:50:07.458] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 209 (-1/-1) hits flags = 528 (plus default)
[20:50:07.467] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[20:50:07.467] <TB2> INFO: run 1 of 1
[20:50:07.731] <TB2> INFO: Expecting 4368000 events.
[20:50:39.828] <TB2> INFO: 724285 events read in total (31505ms).
[20:51:10.546] <TB2> INFO: 1441690 events read in total (62223ms).
[20:51:41.170] <TB2> INFO: 2153590 events read in total (92847ms).
[20:52:11.532] <TB2> INFO: 2861825 events read in total (123209ms).
[20:52:42.005] <TB2> INFO: 3566105 events read in total (153682ms).
[20:53:12.647] <TB2> INFO: 4270000 events read in total (184324ms).
[20:53:17.302] <TB2> INFO: 4368000 events read in total (188979ms).
[20:53:17.378] <TB2> INFO: Test took 189911ms.
[20:53:48.008] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 195 (-1/-1) hits flags = 528 (plus default)
[20:53:48.021] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[20:53:48.021] <TB2> INFO: run 1 of 1
[20:53:48.342] <TB2> INFO: Expecting 4076800 events.
[20:54:20.564] <TB2> INFO: 743175 events read in total (31630ms).
[20:54:51.859] <TB2> INFO: 1478420 events read in total (62925ms).
[20:55:23.096] <TB2> INFO: 2208115 events read in total (94162ms).
[20:55:54.230] <TB2> INFO: 2931915 events read in total (125296ms).
[20:56:25.089] <TB2> INFO: 3652055 events read in total (156155ms).
[20:56:43.069] <TB2> INFO: 4076800 events read in total (174135ms).
[20:56:43.135] <TB2> INFO: Test took 175114ms.
[20:57:10.898] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 194 (-1/-1) hits flags = 528 (plus default)
[20:57:10.908] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[20:57:10.908] <TB2> INFO: run 1 of 1
[20:57:11.142] <TB2> INFO: Expecting 4056000 events.
[20:57:43.061] <TB2> INFO: 745040 events read in total (31328ms).
[20:58:13.958] <TB2> INFO: 1482185 events read in total (62225ms).
[20:58:44.807] <TB2> INFO: 2213420 events read in total (93075ms).
[20:59:15.723] <TB2> INFO: 2938540 events read in total (123990ms).
[20:59:46.765] <TB2> INFO: 3660320 events read in total (155032ms).
[21:00:03.587] <TB2> INFO: 4056000 events read in total (171854ms).
[21:00:03.639] <TB2> INFO: Test took 172731ms.
[21:00:31.619] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 193 (-1/-1) hits flags = 528 (plus default)
[21:00:31.628] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[21:00:31.628] <TB2> INFO: run 1 of 1
[21:00:31.864] <TB2> INFO: Expecting 4035200 events.
[21:01:03.627] <TB2> INFO: 746705 events read in total (31172ms).
[21:01:34.721] <TB2> INFO: 1485625 events read in total (62266ms).
[21:02:05.705] <TB2> INFO: 2218440 events read in total (93250ms).
[21:02:36.982] <TB2> INFO: 2945325 events read in total (124527ms).
[21:03:09.286] <TB2> INFO: 3668985 events read in total (156831ms).
[21:03:26.196] <TB2> INFO: 4035200 events read in total (173741ms).
[21:03:26.268] <TB2> INFO: Test took 174640ms.
[21:03:49.876] <TB2> INFO: PixTestTrim80::trimBitTest() done
[21:03:49.877] <TB2> INFO: PixTestTrim80::doTest() done, duration: 2309 seconds
[21:03:50.512] <TB2> INFO: enter test to run
[21:03:50.512] <TB2> INFO: test: exit no parameter change
[21:03:50.607] <TB2> QUIET: Connection to board 156 closed.
[21:03:50.608] <TB2> INFO: pXar: this is the end, my friend