[12:11:11.241] <TB2> INFO: *** Welcome to pxar ***
[12:11:11.241] <TB2> INFO: *** Today: 2016/10/20
[12:11:11.247] <TB2> INFO: *** Version: c8ba-dirty
[12:11:11.247] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C15.dat
[12:11:11.248] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//tbmParameters_C1b.dat
[12:11:11.248] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//defaultMaskFile.dat
[12:11:11.248] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters_C15.dat
[12:11:11.308] <TB2> INFO: clk: 4
[12:11:11.308] <TB2> INFO: ctr: 4
[12:11:11.308] <TB2> INFO: sda: 19
[12:11:11.308] <TB2> INFO: tin: 9
[12:11:11.308] <TB2> INFO: level: 15
[12:11:11.308] <TB2> INFO: triggerdelay: 0
[12:11:11.308] <TB2> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[12:11:11.308] <TB2> INFO: Log level: INFO
[12:11:11.317] <TB2> INFO: Found DTB DTB_WWXUD2
[12:11:11.324] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[12:11:11.326] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[12:11:11.328] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[12:11:12.822] <TB2> INFO: DUT info:
[12:11:12.822] <TB2> INFO: The DUT currently contains the following objects:
[12:11:12.822] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[12:11:12.822] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:11:12.822] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:11:12.822] <TB2> INFO: TBM Core alpha (2): 7 registers set
[12:11:12.822] <TB2> INFO: TBM Core beta (3): 7 registers set
[12:11:12.822] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[12:11:12.823] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:11:12.823] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:11:12.823] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:11:12.823] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:11:12.823] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:11:12.823] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:11:12.823] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:11:12.823] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:11:12.823] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:11:12.823] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:11:12.823] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:11:12.823] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:11:12.823] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:11:12.823] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:11:12.823] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:11:12.823] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:11:13.224] <TB2> INFO: enter 'restricted' command line mode
[12:11:13.224] <TB2> INFO: enter test to run
[12:11:13.224] <TB2> INFO: test: pretest no parameter change
[12:11:13.224] <TB2> INFO: running: pretest
[12:11:13.229] <TB2> INFO: ######################################################################
[12:11:13.230] <TB2> INFO: PixTestPretest::doTest()
[12:11:13.230] <TB2> INFO: ######################################################################
[12:11:13.231] <TB2> INFO: ----------------------------------------------------------------------
[12:11:13.231] <TB2> INFO: PixTestPretest::programROC()
[12:11:13.231] <TB2> INFO: ----------------------------------------------------------------------
[12:11:31.245] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:11:31.245] <TB2> INFO: IA differences per ROC: 17.7 20.1 18.5 20.9 20.1 20.9 19.3 16.9 19.3 19.3 19.3 20.9 16.9 20.9 23.3 18.5
[12:11:31.307] <TB2> INFO: ----------------------------------------------------------------------
[12:11:31.307] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:11:31.307] <TB2> INFO: ----------------------------------------------------------------------
[12:11:37.706] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 393.1 mA = 24.5688 mA/ROC
[12:11:37.706] <TB2> INFO: i(loss) [mA/ROC]: 20.1 20.1 20.1 20.1 20.1 19.3 19.3 20.1 19.3 20.1 20.1 19.3 19.3 19.3 19.3 19.3
[12:11:37.739] <TB2> INFO: ----------------------------------------------------------------------
[12:11:37.739] <TB2> INFO: PixTestPretest::findTiming()
[12:11:37.739] <TB2> INFO: ----------------------------------------------------------------------
[12:11:37.739] <TB2> INFO: PixTestCmd::init()

[12:12:10.034] <TB2> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[12:12:10.034] <TB2> INFO: (success/tries = 100/100), width = 4
[12:12:11.541] <TB2> INFO: ----------------------------------------------------------------------
[12:12:11.541] <TB2> INFO: PixTestPretest::findWorkingPixel()
[12:12:11.541] <TB2> INFO: ----------------------------------------------------------------------
[12:12:11.636] <TB2> INFO: Expecting 231680 events.
[12:12:21.638] <TB2> INFO: 231680 events read in total (9410ms).
[12:12:21.646] <TB2> INFO: Test took 10099ms.
[12:12:21.893] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:12:21.930] <TB2> INFO: ----------------------------------------------------------------------
[12:12:21.930] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[12:12:21.930] <TB2> INFO: ----------------------------------------------------------------------
[12:12:22.025] <TB2> INFO: Expecting 231680 events.
[12:12:32.038] <TB2> INFO: 231680 events read in total (9422ms).
[12:12:32.049] <TB2> INFO: Test took 10114ms.
[12:12:32.302] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[12:12:32.302] <TB2> INFO: CalDel: 94 108 95 97 109 97 97 82 98 93 104 108 90 103 97 101
[12:12:32.302] <TB2> INFO: VthrComp: 52 51 51 51 52 51 53 54 51 53 51 53 56 51 51 56
[12:12:32.304] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C0.dat
[12:12:32.305] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C1.dat
[12:12:32.305] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C2.dat
[12:12:32.305] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C3.dat
[12:12:32.305] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C4.dat
[12:12:32.305] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C5.dat
[12:12:32.305] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C6.dat
[12:12:32.305] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C7.dat
[12:12:32.305] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C8.dat
[12:12:32.305] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C9.dat
[12:12:32.305] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C10.dat
[12:12:32.306] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C11.dat
[12:12:32.306] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C12.dat
[12:12:32.306] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C13.dat
[12:12:32.306] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C14.dat
[12:12:32.306] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters_C15.dat
[12:12:32.306] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//tbmParameters_C0a.dat
[12:12:32.306] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//tbmParameters_C0b.dat
[12:12:32.306] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//tbmParameters_C1a.dat
[12:12:32.306] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//tbmParameters_C1b.dat
[12:12:32.306] <TB2> INFO: PixTestPretest::doTest() done, duration: 79 seconds
[12:12:32.358] <TB2> INFO: enter test to run
[12:12:32.358] <TB2> INFO: test: FullTest no parameter change
[12:12:32.358] <TB2> INFO: running: fulltest
[12:12:32.358] <TB2> INFO: ######################################################################
[12:12:32.358] <TB2> INFO: PixTestFullTest::doTest()
[12:12:32.358] <TB2> INFO: ######################################################################
[12:12:32.359] <TB2> INFO: ######################################################################
[12:12:32.359] <TB2> INFO: PixTestAlive::doTest()
[12:12:32.359] <TB2> INFO: ######################################################################
[12:12:32.360] <TB2> INFO: ----------------------------------------------------------------------
[12:12:32.360] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:12:32.360] <TB2> INFO: ----------------------------------------------------------------------
[12:12:32.598] <TB2> INFO: Expecting 41600 events.
[12:12:36.060] <TB2> INFO: 41600 events read in total (2870ms).
[12:12:36.060] <TB2> INFO: Test took 3698ms.
[12:12:36.286] <TB2> INFO: PixTestAlive::aliveTest() done
[12:12:36.286] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:12:36.287] <TB2> INFO: ----------------------------------------------------------------------
[12:12:36.287] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:12:36.287] <TB2> INFO: ----------------------------------------------------------------------
[12:12:36.526] <TB2> INFO: Expecting 41600 events.
[12:12:39.527] <TB2> INFO: 41600 events read in total (2410ms).
[12:12:39.528] <TB2> INFO: Test took 3238ms.
[12:12:39.528] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:12:39.763] <TB2> INFO: PixTestAlive::maskTest() done
[12:12:39.763] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:12:39.764] <TB2> INFO: ----------------------------------------------------------------------
[12:12:39.764] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:12:39.764] <TB2> INFO: ----------------------------------------------------------------------
[12:12:40.021] <TB2> INFO: Expecting 41600 events.
[12:12:43.602] <TB2> INFO: 41600 events read in total (2990ms).
[12:12:43.603] <TB2> INFO: Test took 3837ms.
[12:12:43.838] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[12:12:43.838] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:12:43.839] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[12:12:43.839] <TB2> INFO: Decoding statistics:
[12:12:43.839] <TB2> INFO: General information:
[12:12:43.839] <TB2> INFO: 16bit words read: 0
[12:12:43.839] <TB2> INFO: valid events total: 0
[12:12:43.839] <TB2> INFO: empty events: 0
[12:12:43.839] <TB2> INFO: valid events with pixels: 0
[12:12:43.839] <TB2> INFO: valid pixel hits: 0
[12:12:43.839] <TB2> INFO: Event errors: 0
[12:12:43.839] <TB2> INFO: start marker: 0
[12:12:43.839] <TB2> INFO: stop marker: 0
[12:12:43.839] <TB2> INFO: overflow: 0
[12:12:43.839] <TB2> INFO: invalid 5bit words: 0
[12:12:43.839] <TB2> INFO: invalid XOR eye diagram: 0
[12:12:43.839] <TB2> INFO: frame (failed synchr.): 0
[12:12:43.839] <TB2> INFO: idle data (no TBM trl): 0
[12:12:43.839] <TB2> INFO: no data (only TBM hdr): 0
[12:12:43.839] <TB2> INFO: TBM errors: 0
[12:12:43.839] <TB2> INFO: flawed TBM headers: 0
[12:12:43.839] <TB2> INFO: flawed TBM trailers: 0
[12:12:43.839] <TB2> INFO: event ID mismatches: 0
[12:12:43.839] <TB2> INFO: ROC errors: 0
[12:12:43.839] <TB2> INFO: missing ROC header(s): 0
[12:12:43.839] <TB2> INFO: misplaced readback start: 0
[12:12:43.839] <TB2> INFO: Pixel decoding errors: 0
[12:12:43.839] <TB2> INFO: pixel data incomplete: 0
[12:12:43.839] <TB2> INFO: pixel address: 0
[12:12:43.839] <TB2> INFO: pulse height fill bit: 0
[12:12:43.839] <TB2> INFO: buffer corruption: 0
[12:12:43.846] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C15.dat
[12:12:43.846] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr_C15.dat

[12:12:43.846] <TB2> INFO: ######################################################################
[12:12:43.846] <TB2> INFO: PixTestReadback::doTest()
[12:12:43.846] <TB2> INFO: ######################################################################
[12:12:43.846] <TB2> INFO: ----------------------------------------------------------------------
[12:12:43.846] <TB2> INFO: PixTestReadback::CalibrateVd()
[12:12:43.846] <TB2> INFO: ----------------------------------------------------------------------
[12:12:53.816] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C0.dat
[12:12:53.816] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C1.dat
[12:12:53.816] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C2.dat
[12:12:53.816] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C3.dat
[12:12:53.816] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C4.dat
[12:12:53.816] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C5.dat
[12:12:53.816] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C6.dat
[12:12:53.816] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C7.dat
[12:12:53.816] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C8.dat
[12:12:53.816] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C9.dat
[12:12:53.816] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C10.dat
[12:12:53.816] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C11.dat
[12:12:53.817] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C12.dat
[12:12:53.817] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C13.dat
[12:12:53.817] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C14.dat
[12:12:53.817] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C15.dat
[12:12:53.847] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:12:53.847] <TB2> INFO: ----------------------------------------------------------------------
[12:12:53.847] <TB2> INFO: PixTestReadback::CalibrateVa()
[12:12:53.847] <TB2> INFO: ----------------------------------------------------------------------
[12:13:03.769] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C0.dat
[12:13:03.769] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C1.dat
[12:13:03.769] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C2.dat
[12:13:03.769] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C3.dat
[12:13:03.769] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C4.dat
[12:13:03.769] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C5.dat
[12:13:03.769] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C6.dat
[12:13:03.769] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C7.dat
[12:13:03.769] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C8.dat
[12:13:03.769] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C9.dat
[12:13:03.769] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C10.dat
[12:13:03.769] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C11.dat
[12:13:03.769] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C12.dat
[12:13:03.769] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C13.dat
[12:13:03.769] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C14.dat
[12:13:03.770] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C15.dat
[12:13:03.797] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:13:03.797] <TB2> INFO: ----------------------------------------------------------------------
[12:13:03.797] <TB2> INFO: PixTestReadback::readbackVbg()
[12:13:03.797] <TB2> INFO: ----------------------------------------------------------------------
[12:13:11.463] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:13:11.463] <TB2> INFO: ----------------------------------------------------------------------
[12:13:11.463] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[12:13:11.463] <TB2> INFO: ----------------------------------------------------------------------
[12:13:11.463] <TB2> INFO: Vbg will be calibrated using Vd calibration
[12:13:11.463] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 157.4calibrated Vbg = 1.20323 :::*/*/*/*/
[12:13:11.463] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 156.2calibrated Vbg = 1.19891 :::*/*/*/*/
[12:13:11.463] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 154.7calibrated Vbg = 1.19464 :::*/*/*/*/
[12:13:11.463] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 152.7calibrated Vbg = 1.20086 :::*/*/*/*/
[12:13:11.463] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 149.5calibrated Vbg = 1.19294 :::*/*/*/*/
[12:13:11.464] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 150.9calibrated Vbg = 1.20482 :::*/*/*/*/
[12:13:11.464] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 161.9calibrated Vbg = 1.19494 :::*/*/*/*/
[12:13:11.464] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 165calibrated Vbg = 1.19782 :::*/*/*/*/
[12:13:11.464] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 161.1calibrated Vbg = 1.19648 :::*/*/*/*/
[12:13:11.464] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 158.1calibrated Vbg = 1.19398 :::*/*/*/*/
[12:13:11.464] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 155.6calibrated Vbg = 1.19096 :::*/*/*/*/
[12:13:11.464] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 160calibrated Vbg = 1.18247 :::*/*/*/*/
[12:13:11.464] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 167.9calibrated Vbg = 1.18811 :::*/*/*/*/
[12:13:11.464] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 151.9calibrated Vbg = 1.19796 :::*/*/*/*/
[12:13:11.464] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 154.2calibrated Vbg = 1.20005 :::*/*/*/*/
[12:13:11.464] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 164.9calibrated Vbg = 1.19757 :::*/*/*/*/
[12:13:11.466] <TB2> INFO: ----------------------------------------------------------------------
[12:13:11.466] <TB2> INFO: PixTestReadback::CalibrateIa()
[12:13:11.466] <TB2> INFO: ----------------------------------------------------------------------
[12:15:52.285] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C0.dat
[12:15:52.285] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C1.dat
[12:15:52.285] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C2.dat
[12:15:52.285] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C3.dat
[12:15:52.285] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C4.dat
[12:15:52.285] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C5.dat
[12:15:52.285] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C6.dat
[12:15:52.285] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C7.dat
[12:15:52.285] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C8.dat
[12:15:52.285] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C9.dat
[12:15:52.286] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C10.dat
[12:15:52.286] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C11.dat
[12:15:52.286] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C12.dat
[12:15:52.286] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C13.dat
[12:15:52.286] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C14.dat
[12:15:52.286] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//readbackCal_C15.dat
[12:15:52.317] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[12:15:52.319] <TB2> INFO: PixTestReadback::doTest() done
[12:15:52.319] <TB2> INFO: Decoding statistics:
[12:15:52.319] <TB2> INFO: General information:
[12:15:52.319] <TB2> INFO: 16bit words read: 1536
[12:15:52.319] <TB2> INFO: valid events total: 256
[12:15:52.319] <TB2> INFO: empty events: 256
[12:15:52.319] <TB2> INFO: valid events with pixels: 0
[12:15:52.319] <TB2> INFO: valid pixel hits: 0
[12:15:52.319] <TB2> INFO: Event errors: 0
[12:15:52.319] <TB2> INFO: start marker: 0
[12:15:52.319] <TB2> INFO: stop marker: 0
[12:15:52.319] <TB2> INFO: overflow: 0
[12:15:52.319] <TB2> INFO: invalid 5bit words: 0
[12:15:52.319] <TB2> INFO: invalid XOR eye diagram: 0
[12:15:52.319] <TB2> INFO: frame (failed synchr.): 0
[12:15:52.319] <TB2> INFO: idle data (no TBM trl): 0
[12:15:52.319] <TB2> INFO: no data (only TBM hdr): 0
[12:15:52.319] <TB2> INFO: TBM errors: 0
[12:15:52.319] <TB2> INFO: flawed TBM headers: 0
[12:15:52.319] <TB2> INFO: flawed TBM trailers: 0
[12:15:52.319] <TB2> INFO: event ID mismatches: 0
[12:15:52.319] <TB2> INFO: ROC errors: 0
[12:15:52.319] <TB2> INFO: missing ROC header(s): 0
[12:15:52.319] <TB2> INFO: misplaced readback start: 0
[12:15:52.319] <TB2> INFO: Pixel decoding errors: 0
[12:15:52.319] <TB2> INFO: pixel data incomplete: 0
[12:15:52.319] <TB2> INFO: pixel address: 0
[12:15:52.319] <TB2> INFO: pulse height fill bit: 0
[12:15:52.319] <TB2> INFO: buffer corruption: 0
[12:15:52.371] <TB2> INFO: ######################################################################
[12:15:52.371] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:15:52.371] <TB2> INFO: ######################################################################
[12:15:52.373] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:15:52.388] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:15:52.388] <TB2> INFO: run 1 of 1
[12:15:52.624] <TB2> INFO: Expecting 3120000 events.
[12:16:23.249] <TB2> INFO: 667925 events read in total (30034ms).











[12:16:53.290] <TB2> INFO: 1331095 events read in total (60075ms).











[12:17:23.622] <TB2> INFO: 1993040 events read in total (90407ms).











[12:17:53.801] <TB2> INFO: 2656080 events read in total (120586ms).











[12:18:15.337] <TB2> INFO: 3120000 events read in total (142122ms).
[12:18:15.412] <TB2> INFO: Test took 143025ms.
[12:18:38.898] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 166 seconds
[12:18:38.898] <TB2> INFO: number of dead bumps (per ROC): 0 1 0 14 1 0 1 0 0 0 0 0 2 0 0 0
[12:18:38.898] <TB2> INFO: separation cut (per ROC): 105 105 105 106 105 97 108 105 106 114 119 123 107 103 110 120
[12:18:38.899] <TB2> INFO: Decoding statistics:
[12:18:38.899] <TB2> INFO: General information:
[12:18:38.899] <TB2> INFO: 16bit words read: 0
[12:18:38.899] <TB2> INFO: valid events total: 0
[12:18:38.899] <TB2> INFO: empty events: 0
[12:18:38.899] <TB2> INFO: valid events with pixels: 0
[12:18:38.899] <TB2> INFO: valid pixel hits: 0
[12:18:38.899] <TB2> INFO: Event errors: 0
[12:18:38.899] <TB2> INFO: start marker: 0
[12:18:38.899] <TB2> INFO: stop marker: 0
[12:18:38.899] <TB2> INFO: overflow: 0
[12:18:38.899] <TB2> INFO: invalid 5bit words: 0
[12:18:38.899] <TB2> INFO: invalid XOR eye diagram: 0
[12:18:38.899] <TB2> INFO: frame (failed synchr.): 0
[12:18:38.899] <TB2> INFO: idle data (no TBM trl): 0
[12:18:38.899] <TB2> INFO: no data (only TBM hdr): 0
[12:18:38.899] <TB2> INFO: TBM errors: 0
[12:18:38.899] <TB2> INFO: flawed TBM headers: 0
[12:18:38.899] <TB2> INFO: flawed TBM trailers: 0
[12:18:38.899] <TB2> INFO: event ID mismatches: 0
[12:18:38.899] <TB2> INFO: ROC errors: 0
[12:18:38.899] <TB2> INFO: missing ROC header(s): 0
[12:18:38.899] <TB2> INFO: misplaced readback start: 0
[12:18:38.899] <TB2> INFO: Pixel decoding errors: 0
[12:18:38.899] <TB2> INFO: pixel data incomplete: 0
[12:18:38.899] <TB2> INFO: pixel address: 0
[12:18:38.899] <TB2> INFO: pulse height fill bit: 0
[12:18:38.899] <TB2> INFO: buffer corruption: 0
[12:18:38.938] <TB2> INFO: ######################################################################
[12:18:38.938] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:18:38.938] <TB2> INFO: ######################################################################
[12:18:38.938] <TB2> INFO: ----------------------------------------------------------------------
[12:18:38.938] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:18:38.938] <TB2> INFO: ----------------------------------------------------------------------
[12:18:38.939] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:18:38.955] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[12:18:38.955] <TB2> INFO: run 1 of 1
[12:18:39.226] <TB2> INFO: Expecting 36608000 events.
[12:19:03.360] <TB2> INFO: 720450 events read in total (23542ms).
[12:19:26.436] <TB2> INFO: 1425350 events read in total (46618ms).
[12:19:49.957] <TB2> INFO: 2129100 events read in total (70139ms).
[12:20:13.071] <TB2> INFO: 2833000 events read in total (93253ms).
[12:20:36.339] <TB2> INFO: 3536750 events read in total (116521ms).
[12:20:59.952] <TB2> INFO: 4238950 events read in total (140134ms).
[12:21:23.129] <TB2> INFO: 4938900 events read in total (163311ms).
[12:21:46.570] <TB2> INFO: 5639450 events read in total (186752ms).
[12:22:09.940] <TB2> INFO: 6340100 events read in total (210122ms).
[12:22:33.474] <TB2> INFO: 7039850 events read in total (233656ms).
[12:22:56.760] <TB2> INFO: 7736300 events read in total (256942ms).
[12:23:20.305] <TB2> INFO: 8435350 events read in total (280487ms).
[12:23:43.774] <TB2> INFO: 9133050 events read in total (303956ms).
[12:24:07.125] <TB2> INFO: 9833950 events read in total (327307ms).
[12:24:30.252] <TB2> INFO: 10532050 events read in total (350434ms).
[12:24:53.738] <TB2> INFO: 11229750 events read in total (373920ms).
[12:25:17.267] <TB2> INFO: 11927750 events read in total (397449ms).
[12:25:40.595] <TB2> INFO: 12623300 events read in total (420777ms).
[12:26:04.173] <TB2> INFO: 13318300 events read in total (444355ms).
[12:26:27.528] <TB2> INFO: 14013050 events read in total (467710ms).
[12:26:51.044] <TB2> INFO: 14708950 events read in total (491226ms).
[12:27:14.397] <TB2> INFO: 15404550 events read in total (514579ms).
[12:27:37.922] <TB2> INFO: 16100050 events read in total (538104ms).
[12:28:01.234] <TB2> INFO: 16796900 events read in total (561416ms).
[12:28:24.650] <TB2> INFO: 17491900 events read in total (584832ms).
[12:28:48.197] <TB2> INFO: 18186200 events read in total (608379ms).
[12:29:11.526] <TB2> INFO: 18879950 events read in total (631708ms).
[12:29:34.965] <TB2> INFO: 19571450 events read in total (655147ms).
[12:29:58.714] <TB2> INFO: 20262500 events read in total (678896ms).
[12:30:21.775] <TB2> INFO: 20952550 events read in total (701957ms).
[12:30:45.096] <TB2> INFO: 21643850 events read in total (725278ms).
[12:31:07.935] <TB2> INFO: 22333450 events read in total (748117ms).
[12:31:31.207] <TB2> INFO: 23022100 events read in total (771389ms).
[12:31:54.227] <TB2> INFO: 23712300 events read in total (794409ms).
[12:32:17.501] <TB2> INFO: 24400550 events read in total (817683ms).
[12:32:40.740] <TB2> INFO: 25091450 events read in total (840922ms).
[12:33:03.871] <TB2> INFO: 25781600 events read in total (864053ms).
[12:33:27.016] <TB2> INFO: 26469650 events read in total (887198ms).
[12:33:50.270] <TB2> INFO: 27159600 events read in total (910452ms).
[12:34:13.501] <TB2> INFO: 27849150 events read in total (933683ms).
[12:34:36.772] <TB2> INFO: 28537450 events read in total (956954ms).
[12:35:00.038] <TB2> INFO: 29225350 events read in total (980220ms).
[12:35:23.057] <TB2> INFO: 29912950 events read in total (1003239ms).
[12:35:46.286] <TB2> INFO: 30600150 events read in total (1026468ms).
[12:36:09.541] <TB2> INFO: 31287800 events read in total (1049723ms).
[12:36:32.741] <TB2> INFO: 31975900 events read in total (1072923ms).
[12:36:55.829] <TB2> INFO: 32664600 events read in total (1096011ms).
[12:37:19.110] <TB2> INFO: 33352450 events read in total (1119292ms).
[12:37:42.702] <TB2> INFO: 34043850 events read in total (1142884ms).
[12:38:05.890] <TB2> INFO: 34733450 events read in total (1166072ms).
[12:38:29.365] <TB2> INFO: 35425150 events read in total (1189547ms).
[12:38:52.598] <TB2> INFO: 36120850 events read in total (1212780ms).
[12:39:08.758] <TB2> INFO: 36608000 events read in total (1228940ms).
[12:39:08.845] <TB2> INFO: Test took 1229889ms.
[12:39:09.282] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:39:11.160] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:39:13.047] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:39:14.946] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:39:16.866] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:39:18.874] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:39:20.838] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:39:22.889] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:39:24.933] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:39:26.988] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:39:29.060] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:39:30.999] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:39:32.763] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:39:34.773] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:39:36.661] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:39:38.600] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:39:40.530] <TB2> INFO: PixTestScurves::scurves() done
[12:39:40.530] <TB2> INFO: Vcal mean: 130.47 127.47 132.02 124.89 136.35 120.11 128.21 129.32 137.28 134.67 135.61 140.18 133.70 123.58 125.31 133.23
[12:39:40.530] <TB2> INFO: Vcal RMS: 6.42 6.23 6.19 5.99 5.78 6.88 5.97 6.32 6.18 6.36 6.70 6.12 6.22 6.48 6.67 6.92
[12:39:40.530] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1261 seconds
[12:39:40.530] <TB2> INFO: Decoding statistics:
[12:39:40.530] <TB2> INFO: General information:
[12:39:40.530] <TB2> INFO: 16bit words read: 0
[12:39:40.530] <TB2> INFO: valid events total: 0
[12:39:40.531] <TB2> INFO: empty events: 0
[12:39:40.531] <TB2> INFO: valid events with pixels: 0
[12:39:40.531] <TB2> INFO: valid pixel hits: 0
[12:39:40.531] <TB2> INFO: Event errors: 0
[12:39:40.531] <TB2> INFO: start marker: 0
[12:39:40.531] <TB2> INFO: stop marker: 0
[12:39:40.531] <TB2> INFO: overflow: 0
[12:39:40.531] <TB2> INFO: invalid 5bit words: 0
[12:39:40.531] <TB2> INFO: invalid XOR eye diagram: 0
[12:39:40.531] <TB2> INFO: frame (failed synchr.): 0
[12:39:40.531] <TB2> INFO: idle data (no TBM trl): 0
[12:39:40.531] <TB2> INFO: no data (only TBM hdr): 0
[12:39:40.531] <TB2> INFO: TBM errors: 0
[12:39:40.531] <TB2> INFO: flawed TBM headers: 0
[12:39:40.531] <TB2> INFO: flawed TBM trailers: 0
[12:39:40.531] <TB2> INFO: event ID mismatches: 0
[12:39:40.531] <TB2> INFO: ROC errors: 0
[12:39:40.531] <TB2> INFO: missing ROC header(s): 0
[12:39:40.531] <TB2> INFO: misplaced readback start: 0
[12:39:40.531] <TB2> INFO: Pixel decoding errors: 0
[12:39:40.531] <TB2> INFO: pixel data incomplete: 0
[12:39:40.531] <TB2> INFO: pixel address: 0
[12:39:40.531] <TB2> INFO: pulse height fill bit: 0
[12:39:40.531] <TB2> INFO: buffer corruption: 0
[12:39:40.621] <TB2> INFO: ######################################################################
[12:39:40.621] <TB2> INFO: PixTestTrim::doTest()
[12:39:40.621] <TB2> INFO: ######################################################################
[12:39:40.622] <TB2> INFO: ----------------------------------------------------------------------
[12:39:40.622] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:39:40.622] <TB2> INFO: ----------------------------------------------------------------------
[12:39:40.690] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:39:40.690] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:39:40.705] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:39:40.705] <TB2> INFO: run 1 of 1
[12:39:41.030] <TB2> INFO: Expecting 5025280 events.
[12:40:11.820] <TB2> INFO: 840632 events read in total (30187ms).
[12:40:42.173] <TB2> INFO: 1679296 events read in total (60541ms).
[12:41:12.337] <TB2> INFO: 2515112 events read in total (90704ms).
[12:41:42.652] <TB2> INFO: 3345816 events read in total (121019ms).
[12:42:13.276] <TB2> INFO: 4173096 events read in total (151643ms).
[12:42:43.616] <TB2> INFO: 4998984 events read in total (181983ms).
[12:42:44.971] <TB2> INFO: 5025280 events read in total (183338ms).
[12:42:45.016] <TB2> INFO: Test took 184311ms.
[12:43:02.634] <TB2> INFO: ROC 0 VthrComp = 126
[12:43:02.634] <TB2> INFO: ROC 1 VthrComp = 124
[12:43:02.635] <TB2> INFO: ROC 2 VthrComp = 126
[12:43:02.635] <TB2> INFO: ROC 3 VthrComp = 126
[12:43:02.635] <TB2> INFO: ROC 4 VthrComp = 130
[12:43:02.635] <TB2> INFO: ROC 5 VthrComp = 115
[12:43:02.635] <TB2> INFO: ROC 6 VthrComp = 126
[12:43:02.635] <TB2> INFO: ROC 7 VthrComp = 130
[12:43:02.635] <TB2> INFO: ROC 8 VthrComp = 130
[12:43:02.636] <TB2> INFO: ROC 9 VthrComp = 130
[12:43:02.636] <TB2> INFO: ROC 10 VthrComp = 129
[12:43:02.636] <TB2> INFO: ROC 11 VthrComp = 134
[12:43:02.637] <TB2> INFO: ROC 12 VthrComp = 132
[12:43:02.637] <TB2> INFO: ROC 13 VthrComp = 121
[12:43:02.638] <TB2> INFO: ROC 14 VthrComp = 125
[12:43:02.638] <TB2> INFO: ROC 15 VthrComp = 129
[12:43:02.889] <TB2> INFO: Expecting 41600 events.
[12:43:06.647] <TB2> INFO: 41600 events read in total (3166ms).
[12:43:06.648] <TB2> INFO: Test took 4008ms.
[12:43:06.657] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:43:06.657] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:43:06.668] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:43:06.668] <TB2> INFO: run 1 of 1
[12:43:06.946] <TB2> INFO: Expecting 5025280 events.
[12:43:33.079] <TB2> INFO: 593432 events read in total (25541ms).
[12:43:59.110] <TB2> INFO: 1185136 events read in total (51573ms).
[12:44:25.323] <TB2> INFO: 1777968 events read in total (77785ms).
[12:44:51.459] <TB2> INFO: 2370128 events read in total (103921ms).
[12:45:17.310] <TB2> INFO: 2959440 events read in total (129772ms).
[12:45:43.198] <TB2> INFO: 3547064 events read in total (155660ms).
[12:46:09.594] <TB2> INFO: 4133368 events read in total (182056ms).
[12:46:36.139] <TB2> INFO: 4718872 events read in total (208601ms).
[12:46:49.595] <TB2> INFO: 5025280 events read in total (222057ms).
[12:46:49.680] <TB2> INFO: Test took 223012ms.
[12:47:18.033] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 62.2411 for pixel 33/5 mean/min/max = 46.6515/30.7757/62.5272
[12:47:18.033] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 62.4713 for pixel 12/9 mean/min/max = 47.305/32.1287/62.4812
[12:47:18.034] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 61.704 for pixel 21/4 mean/min/max = 46.6343/31.408/61.8606
[12:47:18.034] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 60.8161 for pixel 30/22 mean/min/max = 46.4084/31.9331/60.8838
[12:47:18.035] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 63.3142 for pixel 51/15 mean/min/max = 47.4953/31.6385/63.3521
[12:47:18.035] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 64.1609 for pixel 4/0 mean/min/max = 47.6731/31.0987/64.2475
[12:47:18.036] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 63.3386 for pixel 2/10 mean/min/max = 46.9668/30.5918/63.3418
[12:47:18.036] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 62.2886 for pixel 47/15 mean/min/max = 46.4214/30.4423/62.4005
[12:47:18.037] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 65.5701 for pixel 17/2 mean/min/max = 49.2488/32.6625/65.8352
[12:47:18.037] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 66.4705 for pixel 0/7 mean/min/max = 50.2343/33.9252/66.5434
[12:47:18.038] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 62.8849 for pixel 21/79 mean/min/max = 46.9522/30.9542/62.9502
[12:47:18.038] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 66.3581 for pixel 13/14 mean/min/max = 50.4796/34.5253/66.434
[12:47:18.038] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 62.034 for pixel 0/15 mean/min/max = 47.232/32.4209/62.0431
[12:47:18.039] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 62.8985 for pixel 14/15 mean/min/max = 47.9359/32.7955/63.0763
[12:47:18.039] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 58.7461 for pixel 12/55 mean/min/max = 45.6524/32.2438/59.061
[12:47:18.040] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 65.1373 for pixel 0/9 mean/min/max = 49.5987/33.9439/65.2534
[12:47:18.040] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:18.129] <TB2> INFO: Expecting 411648 events.
[12:47:27.580] <TB2> INFO: 411648 events read in total (8860ms).
[12:47:27.588] <TB2> INFO: Expecting 411648 events.
[12:47:36.713] <TB2> INFO: 411648 events read in total (8722ms).
[12:47:36.723] <TB2> INFO: Expecting 411648 events.
[12:47:46.044] <TB2> INFO: 411648 events read in total (8918ms).
[12:47:46.057] <TB2> INFO: Expecting 411648 events.
[12:47:55.397] <TB2> INFO: 411648 events read in total (8937ms).
[12:47:55.415] <TB2> INFO: Expecting 411648 events.
[12:48:04.735] <TB2> INFO: 411648 events read in total (8917ms).
[12:48:04.754] <TB2> INFO: Expecting 411648 events.
[12:48:13.001] <TB2> INFO: 411648 events read in total (8844ms).
[12:48:14.023] <TB2> INFO: Expecting 411648 events.
[12:48:23.369] <TB2> INFO: 411648 events read in total (8943ms).
[12:48:23.393] <TB2> INFO: Expecting 411648 events.
[12:48:32.717] <TB2> INFO: 411648 events read in total (8921ms).
[12:48:32.745] <TB2> INFO: Expecting 411648 events.
[12:48:41.940] <TB2> INFO: 411648 events read in total (8792ms).
[12:48:41.969] <TB2> INFO: Expecting 411648 events.
[12:48:51.252] <TB2> INFO: 411648 events read in total (8880ms).
[12:48:51.285] <TB2> INFO: Expecting 411648 events.
[12:49:00.743] <TB2> INFO: 411648 events read in total (9055ms).
[12:49:00.790] <TB2> INFO: Expecting 411648 events.
[12:49:10.065] <TB2> INFO: 411648 events read in total (8872ms).
[12:49:10.103] <TB2> INFO: Expecting 411648 events.
[12:49:19.390] <TB2> INFO: 411648 events read in total (8884ms).
[12:49:19.431] <TB2> INFO: Expecting 411648 events.
[12:49:28.768] <TB2> INFO: 411648 events read in total (8934ms).
[12:49:28.814] <TB2> INFO: Expecting 411648 events.
[12:49:38.060] <TB2> INFO: 411648 events read in total (8843ms).
[12:49:38.121] <TB2> INFO: Expecting 411648 events.
[12:49:47.369] <TB2> INFO: 411648 events read in total (8844ms).
[12:49:47.417] <TB2> INFO: Test took 149378ms.
[12:49:48.073] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:49:48.086] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:49:48.086] <TB2> INFO: run 1 of 1
[12:49:48.325] <TB2> INFO: Expecting 5025280 events.
[12:50:14.998] <TB2> INFO: 596416 events read in total (26081ms).
[12:50:41.057] <TB2> INFO: 1188280 events read in total (52140ms).
[12:51:07.398] <TB2> INFO: 1778864 events read in total (78481ms).
[12:51:33.840] <TB2> INFO: 2366608 events read in total (104923ms).
[12:52:00.140] <TB2> INFO: 2956720 events read in total (131224ms).
[12:52:26.504] <TB2> INFO: 3547840 events read in total (157587ms).
[12:52:52.758] <TB2> INFO: 4139696 events read in total (183841ms).
[12:53:18.884] <TB2> INFO: 4731976 events read in total (209967ms).
[12:53:32.218] <TB2> INFO: 5025280 events read in total (223301ms).
[12:53:32.363] <TB2> INFO: Test took 224278ms.
[12:53:54.640] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 5.691371 .. 146.859684
[12:53:54.911] <TB2> INFO: Expecting 208000 events.
[12:54:04.515] <TB2> INFO: 208000 events read in total (9012ms).
[12:54:04.516] <TB2> INFO: Test took 9874ms.
[12:54:04.574] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 5 .. 156 (-1/-1) hits flags = 528 (plus default)
[12:54:04.587] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:54:04.587] <TB2> INFO: run 1 of 1
[12:54:04.865] <TB2> INFO: Expecting 5058560 events.
[12:54:31.134] <TB2> INFO: 579752 events read in total (25678ms).
[12:54:57.047] <TB2> INFO: 1159480 events read in total (51592ms).
[12:55:22.471] <TB2> INFO: 1739208 events read in total (77016ms).
[12:55:48.274] <TB2> INFO: 2318752 events read in total (102818ms).
[12:56:14.186] <TB2> INFO: 2898240 events read in total (128730ms).
[12:56:40.631] <TB2> INFO: 3477448 events read in total (155175ms).
[12:57:06.725] <TB2> INFO: 4056184 events read in total (181269ms).
[12:57:32.211] <TB2> INFO: 4634440 events read in total (206755ms).
[12:57:51.182] <TB2> INFO: 5058560 events read in total (225726ms).
[12:57:51.302] <TB2> INFO: Test took 226716ms.
[12:58:17.921] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.259965 .. 46.792316
[12:58:18.195] <TB2> INFO: Expecting 208000 events.
[12:58:28.585] <TB2> INFO: 208000 events read in total (9798ms).
[12:58:28.586] <TB2> INFO: Test took 10663ms.
[12:58:28.634] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[12:58:28.647] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:58:28.647] <TB2> INFO: run 1 of 1
[12:58:28.925] <TB2> INFO: Expecting 1331200 events.
[12:58:56.990] <TB2> INFO: 659616 events read in total (27474ms).
[12:59:25.320] <TB2> INFO: 1316832 events read in total (55805ms).
[12:59:26.356] <TB2> INFO: 1331200 events read in total (56841ms).
[12:59:26.393] <TB2> INFO: Test took 57747ms.
[12:59:40.666] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 27.751197 .. 48.632625
[12:59:40.908] <TB2> INFO: Expecting 208000 events.
[12:59:51.232] <TB2> INFO: 208000 events read in total (9733ms).
[12:59:51.233] <TB2> INFO: Test took 10565ms.
[12:59:51.295] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 58 (-1/-1) hits flags = 528 (plus default)
[12:59:51.308] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[12:59:51.308] <TB2> INFO: run 1 of 1
[12:59:51.586] <TB2> INFO: Expecting 1397760 events.
[13:00:21.380] <TB2> INFO: 651016 events read in total (29202ms).
[13:00:49.615] <TB2> INFO: 1300504 events read in total (57437ms).
[13:00:54.165] <TB2> INFO: 1397760 events read in total (61987ms).
[13:00:54.201] <TB2> INFO: Test took 62893ms.
[13:01:07.301] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 25.514048 .. 49.577571
[13:01:07.545] <TB2> INFO: Expecting 208000 events.
[13:01:17.254] <TB2> INFO: 208000 events read in total (9118ms).
[13:01:17.255] <TB2> INFO: Test took 9952ms.
[13:01:17.304] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 15 .. 59 (-1/-1) hits flags = 528 (plus default)
[13:01:17.319] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:01:17.319] <TB2> INFO: run 1 of 1
[13:01:17.597] <TB2> INFO: Expecting 1497600 events.
[13:01:46.320] <TB2> INFO: 653896 events read in total (28132ms).
[13:02:14.388] <TB2> INFO: 1307384 events read in total (56200ms).
[13:02:23.004] <TB2> INFO: 1497600 events read in total (64816ms).
[13:02:23.046] <TB2> INFO: Test took 65727ms.
[13:02:36.416] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[13:02:36.416] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[13:02:36.429] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:02:36.429] <TB2> INFO: run 1 of 1
[13:02:36.664] <TB2> INFO: Expecting 1364480 events.
[13:03:04.707] <TB2> INFO: 669120 events read in total (27451ms).
[13:03:32.774] <TB2> INFO: 1336952 events read in total (55518ms).
[13:03:34.354] <TB2> INFO: 1364480 events read in total (57098ms).
[13:03:34.386] <TB2> INFO: Test took 57958ms.
[13:03:49.414] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C0.dat
[13:03:49.414] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C1.dat
[13:03:49.414] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C2.dat
[13:03:49.414] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C3.dat
[13:03:49.414] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C4.dat
[13:03:49.414] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C5.dat
[13:03:49.414] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C6.dat
[13:03:49.414] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C7.dat
[13:03:49.414] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C8.dat
[13:03:49.415] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C9.dat
[13:03:49.415] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C10.dat
[13:03:49.415] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C11.dat
[13:03:49.415] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C12.dat
[13:03:49.415] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C13.dat
[13:03:49.415] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C14.dat
[13:03:49.415] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C15.dat
[13:03:49.415] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters35_C0.dat
[13:03:49.420] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters35_C1.dat
[13:03:49.425] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters35_C2.dat
[13:03:49.430] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters35_C3.dat
[13:03:49.435] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters35_C4.dat
[13:03:49.439] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters35_C5.dat
[13:03:49.444] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters35_C6.dat
[13:03:49.450] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters35_C7.dat
[13:03:49.455] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters35_C8.dat
[13:03:49.459] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters35_C9.dat
[13:03:49.464] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters35_C10.dat
[13:03:49.469] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters35_C11.dat
[13:03:49.474] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters35_C12.dat
[13:03:49.479] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters35_C13.dat
[13:03:49.483] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters35_C14.dat
[13:03:49.488] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//trimParameters35_C15.dat
[13:03:49.493] <TB2> INFO: PixTestTrim::trimTest() done
[13:03:49.493] <TB2> INFO: vtrim: 128 145 138 146 131 132 140 154 138 141 127 147 137 137 125 124
[13:03:49.493] <TB2> INFO: vthrcomp: 126 124 126 126 130 115 126 130 130 130 129 134 132 121 125 129
[13:03:49.493] <TB2> INFO: vcal mean: 35.03 35.04 35.14 34.97 35.18 35.01 35.34 35.09 35.68 35.62 34.99 35.58 35.14 35.06 34.96 35.08
[13:03:49.493] <TB2> INFO: vcal RMS: 1.21 1.15 1.37 1.02 1.34 1.17 1.70 1.44 1.91 1.85 1.24 1.76 1.26 1.15 1.03 1.18
[13:03:49.493] <TB2> INFO: bits mean: 9.70 10.00 9.83 9.61 9.54 9.50 9.81 10.37 9.29 8.53 9.16 9.14 9.46 9.24 9.63 8.07
[13:03:49.493] <TB2> INFO: bits RMS: 2.73 2.40 2.63 2.61 2.71 2.70 2.78 2.47 2.73 2.79 2.98 2.43 2.67 2.67 2.62 2.79
[13:03:49.501] <TB2> INFO: ----------------------------------------------------------------------
[13:03:49.501] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:03:49.501] <TB2> INFO: ----------------------------------------------------------------------
[13:03:49.503] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:03:49.519] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:03:49.519] <TB2> INFO: run 1 of 1
[13:03:49.774] <TB2> INFO: Expecting 4160000 events.
[13:04:23.989] <TB2> INFO: 802505 events read in total (33623ms).
[13:04:56.001] <TB2> INFO: 1595565 events read in total (66635ms).
[13:05:30.195] <TB2> INFO: 2381350 events read in total (99829ms).
[13:06:03.184] <TB2> INFO: 3162235 events read in total (132818ms).
[13:06:35.976] <TB2> INFO: 3941085 events read in total (165610ms).
[13:06:45.258] <TB2> INFO: 4160000 events read in total (174892ms).
[13:06:45.434] <TB2> INFO: Test took 175915ms.
[13:07:10.918] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 217 (-1/-1) hits flags = 528 (plus default)
[13:07:10.931] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:07:10.931] <TB2> INFO: run 1 of 1
[13:07:11.169] <TB2> INFO: Expecting 4534400 events.
[13:07:44.232] <TB2> INFO: 743690 events read in total (32471ms).
[13:08:15.974] <TB2> INFO: 1481450 events read in total (64213ms).
[13:08:48.048] <TB2> INFO: 2214980 events read in total (96287ms).
[13:09:19.803] <TB2> INFO: 2943695 events read in total (128042ms).
[13:09:51.173] <TB2> INFO: 3670960 events read in total (159412ms).
[13:10:22.944] <TB2> INFO: 4398040 events read in total (191183ms).
[13:10:29.179] <TB2> INFO: 4534400 events read in total (197418ms).
[13:10:29.255] <TB2> INFO: Test took 198324ms.
[13:10:57.176] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 209 (-1/-1) hits flags = 528 (plus default)
[13:10:57.190] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:10:57.190] <TB2> INFO: run 1 of 1
[13:10:57.426] <TB2> INFO: Expecting 4368000 events.
[13:11:30.735] <TB2> INFO: 755650 events read in total (32717ms).
[13:12:02.909] <TB2> INFO: 1503925 events read in total (64891ms).
[13:12:34.999] <TB2> INFO: 2248645 events read in total (96981ms).
[13:13:07.106] <TB2> INFO: 2987965 events read in total (129088ms).
[13:13:38.867] <TB2> INFO: 3724985 events read in total (160849ms).
[13:14:06.602] <TB2> INFO: 4368000 events read in total (188584ms).
[13:14:06.680] <TB2> INFO: Test took 189490ms.
[13:14:33.813] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 210 (-1/-1) hits flags = 528 (plus default)
[13:14:33.826] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:14:33.826] <TB2> INFO: run 1 of 1
[13:14:34.065] <TB2> INFO: Expecting 4388800 events.
[13:15:07.016] <TB2> INFO: 754180 events read in total (32360ms).
[13:15:38.988] <TB2> INFO: 1501340 events read in total (64332ms).
[13:16:10.844] <TB2> INFO: 2244745 events read in total (96188ms).
[13:16:42.896] <TB2> INFO: 2983205 events read in total (128240ms).
[13:17:14.660] <TB2> INFO: 3719010 events read in total (160004ms).
[13:17:43.548] <TB2> INFO: 4388800 events read in total (188892ms).
[13:17:43.639] <TB2> INFO: Test took 189813ms.
[13:18:07.894] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[13:18:07.907] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[13:18:07.907] <TB2> INFO: run 1 of 1
[13:18:08.183] <TB2> INFO: Expecting 4430400 events.
[13:18:40.276] <TB2> INFO: 751765 events read in total (31501ms).
[13:19:12.297] <TB2> INFO: 1496715 events read in total (63522ms).
[13:19:44.062] <TB2> INFO: 2237745 events read in total (95287ms).
[13:20:15.836] <TB2> INFO: 2973420 events read in total (127061ms).
[13:20:47.798] <TB2> INFO: 3707035 events read in total (159023ms).
[13:21:19.711] <TB2> INFO: 4430400 events read in total (190936ms).
[13:21:19.815] <TB2> INFO: Test took 191908ms.
[13:21:47.047] <TB2> INFO: PixTestTrim::trimBitTest() done
[13:21:47.048] <TB2> INFO: PixTestTrim::doTest() done, duration: 2526 seconds
[13:21:47.048] <TB2> INFO: Decoding statistics:
[13:21:47.048] <TB2> INFO: General information:
[13:21:47.048] <TB2> INFO: 16bit words read: 0
[13:21:47.048] <TB2> INFO: valid events total: 0
[13:21:47.048] <TB2> INFO: empty events: 0
[13:21:47.048] <TB2> INFO: valid events with pixels: 0
[13:21:47.048] <TB2> INFO: valid pixel hits: 0
[13:21:47.048] <TB2> INFO: Event errors: 0
[13:21:47.048] <TB2> INFO: start marker: 0
[13:21:47.048] <TB2> INFO: stop marker: 0
[13:21:47.048] <TB2> INFO: overflow: 0
[13:21:47.048] <TB2> INFO: invalid 5bit words: 0
[13:21:47.048] <TB2> INFO: invalid XOR eye diagram: 0
[13:21:47.048] <TB2> INFO: frame (failed synchr.): 0
[13:21:47.048] <TB2> INFO: idle data (no TBM trl): 0
[13:21:47.048] <TB2> INFO: no data (only TBM hdr): 0
[13:21:47.048] <TB2> INFO: TBM errors: 0
[13:21:47.048] <TB2> INFO: flawed TBM headers: 0
[13:21:47.048] <TB2> INFO: flawed TBM trailers: 0
[13:21:47.048] <TB2> INFO: event ID mismatches: 0
[13:21:47.048] <TB2> INFO: ROC errors: 0
[13:21:47.048] <TB2> INFO: missing ROC header(s): 0
[13:21:47.048] <TB2> INFO: misplaced readback start: 0
[13:21:47.048] <TB2> INFO: Pixel decoding errors: 0
[13:21:47.048] <TB2> INFO: pixel data incomplete: 0
[13:21:47.048] <TB2> INFO: pixel address: 0
[13:21:47.048] <TB2> INFO: pulse height fill bit: 0
[13:21:47.048] <TB2> INFO: buffer corruption: 0
[13:21:47.695] <TB2> INFO: ######################################################################
[13:21:47.695] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:21:47.695] <TB2> INFO: ######################################################################
[13:21:47.934] <TB2> INFO: Expecting 41600 events.
[13:21:51.435] <TB2> INFO: 41600 events read in total (2909ms).
[13:21:51.435] <TB2> INFO: Test took 3738ms.
[13:21:51.889] <TB2> INFO: Expecting 41600 events.
[13:21:55.608] <TB2> INFO: 41600 events read in total (3127ms).
[13:21:55.609] <TB2> INFO: Test took 3970ms.
[13:21:55.898] <TB2> INFO: Expecting 41600 events.
[13:21:59.460] <TB2> INFO: 41600 events read in total (2970ms).
[13:21:59.461] <TB2> INFO: Test took 3828ms.
[13:21:59.752] <TB2> INFO: Expecting 41600 events.
[13:22:03.248] <TB2> INFO: 41600 events read in total (2904ms).
[13:22:03.249] <TB2> INFO: Test took 3762ms.
[13:22:03.539] <TB2> INFO: Expecting 41600 events.
[13:22:07.132] <TB2> INFO: 41600 events read in total (3002ms).
[13:22:07.133] <TB2> INFO: Test took 3859ms.
[13:22:07.421] <TB2> INFO: Expecting 41600 events.
[13:22:10.916] <TB2> INFO: 41600 events read in total (2903ms).
[13:22:10.916] <TB2> INFO: Test took 3759ms.
[13:22:11.205] <TB2> INFO: Expecting 41600 events.
[13:22:14.695] <TB2> INFO: 41600 events read in total (2898ms).
[13:22:14.696] <TB2> INFO: Test took 3755ms.
[13:22:14.985] <TB2> INFO: Expecting 41600 events.
[13:22:18.511] <TB2> INFO: 41600 events read in total (2934ms).
[13:22:18.512] <TB2> INFO: Test took 3791ms.
[13:22:18.801] <TB2> INFO: Expecting 41600 events.
[13:22:22.315] <TB2> INFO: 41600 events read in total (2922ms).
[13:22:22.315] <TB2> INFO: Test took 3779ms.
[13:22:22.604] <TB2> INFO: Expecting 41600 events.
[13:22:26.186] <TB2> INFO: 41600 events read in total (2990ms).
[13:22:26.187] <TB2> INFO: Test took 3848ms.
[13:22:26.505] <TB2> INFO: Expecting 41600 events.
[13:22:30.041] <TB2> INFO: 41600 events read in total (2944ms).
[13:22:30.042] <TB2> INFO: Test took 3831ms.
[13:22:30.348] <TB2> INFO: Expecting 41600 events.
[13:22:33.974] <TB2> INFO: 41600 events read in total (3034ms).
[13:22:33.975] <TB2> INFO: Test took 3906ms.
[13:22:34.264] <TB2> INFO: Expecting 41600 events.
[13:22:37.790] <TB2> INFO: 41600 events read in total (2934ms).
[13:22:37.791] <TB2> INFO: Test took 3792ms.
[13:22:38.081] <TB2> INFO: Expecting 41600 events.
[13:22:41.665] <TB2> INFO: 41600 events read in total (2992ms).
[13:22:41.665] <TB2> INFO: Test took 3850ms.
[13:22:41.955] <TB2> INFO: Expecting 41600 events.
[13:22:45.539] <TB2> INFO: 41600 events read in total (2992ms).
[13:22:45.540] <TB2> INFO: Test took 3850ms.
[13:22:45.830] <TB2> INFO: Expecting 41600 events.
[13:22:49.354] <TB2> INFO: 41600 events read in total (2932ms).
[13:22:49.355] <TB2> INFO: Test took 3790ms.
[13:22:49.645] <TB2> INFO: Expecting 41600 events.
[13:22:53.198] <TB2> INFO: 41600 events read in total (2961ms).
[13:22:53.199] <TB2> INFO: Test took 3820ms.
[13:22:53.492] <TB2> INFO: Expecting 41600 events.
[13:22:57.007] <TB2> INFO: 41600 events read in total (2924ms).
[13:22:57.008] <TB2> INFO: Test took 3782ms.
[13:22:57.298] <TB2> INFO: Expecting 41600 events.
[13:23:00.807] <TB2> INFO: 41600 events read in total (2917ms).
[13:23:00.808] <TB2> INFO: Test took 3776ms.
[13:23:01.098] <TB2> INFO: Expecting 41600 events.
[13:23:04.653] <TB2> INFO: 41600 events read in total (2963ms).
[13:23:04.654] <TB2> INFO: Test took 3821ms.
[13:23:04.945] <TB2> INFO: Expecting 41600 events.
[13:23:08.439] <TB2> INFO: 41600 events read in total (2902ms).
[13:23:08.440] <TB2> INFO: Test took 3761ms.
[13:23:08.731] <TB2> INFO: Expecting 41600 events.
[13:23:12.220] <TB2> INFO: 41600 events read in total (2897ms).
[13:23:12.221] <TB2> INFO: Test took 3755ms.
[13:23:12.510] <TB2> INFO: Expecting 41600 events.
[13:23:16.108] <TB2> INFO: 41600 events read in total (3006ms).
[13:23:16.109] <TB2> INFO: Test took 3864ms.
[13:23:16.400] <TB2> INFO: Expecting 41600 events.
[13:23:20.019] <TB2> INFO: 41600 events read in total (3027ms).
[13:23:20.020] <TB2> INFO: Test took 3886ms.
[13:23:20.309] <TB2> INFO: Expecting 41600 events.
[13:23:23.855] <TB2> INFO: 41600 events read in total (2954ms).
[13:23:23.856] <TB2> INFO: Test took 3812ms.
[13:23:24.146] <TB2> INFO: Expecting 41600 events.
[13:23:27.676] <TB2> INFO: 41600 events read in total (2938ms).
[13:23:27.676] <TB2> INFO: Test took 3796ms.
[13:23:27.989] <TB2> INFO: Expecting 41600 events.
[13:23:31.538] <TB2> INFO: 41600 events read in total (2957ms).
[13:23:31.539] <TB2> INFO: Test took 3839ms.
[13:23:31.834] <TB2> INFO: Expecting 41600 events.
[13:23:35.370] <TB2> INFO: 41600 events read in total (2945ms).
[13:23:35.371] <TB2> INFO: Test took 3803ms.
[13:23:35.661] <TB2> INFO: Expecting 2560 events.
[13:23:36.552] <TB2> INFO: 2560 events read in total (299ms).
[13:23:36.552] <TB2> INFO: Test took 1170ms.
[13:23:36.860] <TB2> INFO: Expecting 2560 events.
[13:23:37.752] <TB2> INFO: 2560 events read in total (300ms).
[13:23:37.752] <TB2> INFO: Test took 1199ms.
[13:23:38.061] <TB2> INFO: Expecting 2560 events.
[13:23:38.949] <TB2> INFO: 2560 events read in total (296ms).
[13:23:38.949] <TB2> INFO: Test took 1196ms.
[13:23:39.258] <TB2> INFO: Expecting 2560 events.
[13:23:40.144] <TB2> INFO: 2560 events read in total (295ms).
[13:23:40.144] <TB2> INFO: Test took 1194ms.
[13:23:40.452] <TB2> INFO: Expecting 2560 events.
[13:23:41.342] <TB2> INFO: 2560 events read in total (298ms).
[13:23:41.342] <TB2> INFO: Test took 1197ms.
[13:23:41.650] <TB2> INFO: Expecting 2560 events.
[13:23:42.537] <TB2> INFO: 2560 events read in total (295ms).
[13:23:42.537] <TB2> INFO: Test took 1194ms.
[13:23:42.845] <TB2> INFO: Expecting 2560 events.
[13:23:43.731] <TB2> INFO: 2560 events read in total (294ms).
[13:23:43.732] <TB2> INFO: Test took 1195ms.
[13:23:44.040] <TB2> INFO: Expecting 2560 events.
[13:23:44.925] <TB2> INFO: 2560 events read in total (294ms).
[13:23:44.926] <TB2> INFO: Test took 1194ms.
[13:23:45.233] <TB2> INFO: Expecting 2560 events.
[13:23:46.110] <TB2> INFO: 2560 events read in total (285ms).
[13:23:46.111] <TB2> INFO: Test took 1185ms.
[13:23:46.420] <TB2> INFO: Expecting 2560 events.
[13:23:47.300] <TB2> INFO: 2560 events read in total (288ms).
[13:23:47.300] <TB2> INFO: Test took 1189ms.
[13:23:47.608] <TB2> INFO: Expecting 2560 events.
[13:23:48.496] <TB2> INFO: 2560 events read in total (296ms).
[13:23:48.497] <TB2> INFO: Test took 1196ms.
[13:23:48.803] <TB2> INFO: Expecting 2560 events.
[13:23:49.689] <TB2> INFO: 2560 events read in total (294ms).
[13:23:49.689] <TB2> INFO: Test took 1192ms.
[13:23:49.996] <TB2> INFO: Expecting 2560 events.
[13:23:50.882] <TB2> INFO: 2560 events read in total (294ms).
[13:23:50.883] <TB2> INFO: Test took 1193ms.
[13:23:51.189] <TB2> INFO: Expecting 2560 events.
[13:23:52.082] <TB2> INFO: 2560 events read in total (301ms).
[13:23:52.082] <TB2> INFO: Test took 1198ms.
[13:23:52.390] <TB2> INFO: Expecting 2560 events.
[13:23:53.276] <TB2> INFO: 2560 events read in total (295ms).
[13:23:53.277] <TB2> INFO: Test took 1194ms.
[13:23:53.585] <TB2> INFO: Expecting 2560 events.
[13:23:54.476] <TB2> INFO: 2560 events read in total (299ms).
[13:23:54.476] <TB2> INFO: Test took 1199ms.
[13:23:54.479] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:23:54.786] <TB2> INFO: Expecting 655360 events.
[13:24:09.804] <TB2> INFO: 655360 events read in total (14427ms).
[13:24:09.820] <TB2> INFO: Expecting 655360 events.
[13:24:24.857] <TB2> INFO: 655360 events read in total (14634ms).
[13:24:24.881] <TB2> INFO: Expecting 655360 events.
[13:24:39.462] <TB2> INFO: 655360 events read in total (14178ms).
[13:24:39.486] <TB2> INFO: Expecting 655360 events.
[13:24:54.168] <TB2> INFO: 655360 events read in total (14268ms).
[13:24:54.196] <TB2> INFO: Expecting 655360 events.
[13:25:08.834] <TB2> INFO: 655360 events read in total (14235ms).
[13:25:08.877] <TB2> INFO: Expecting 655360 events.
[13:25:23.443] <TB2> INFO: 655360 events read in total (14163ms).
[13:25:23.516] <TB2> INFO: Expecting 655360 events.
[13:25:38.006] <TB2> INFO: 655360 events read in total (14087ms).
[13:25:38.054] <TB2> INFO: Expecting 655360 events.
[13:25:52.749] <TB2> INFO: 655360 events read in total (14292ms).
[13:25:52.821] <TB2> INFO: Expecting 655360 events.
[13:26:07.272] <TB2> INFO: 655360 events read in total (14048ms).
[13:26:07.324] <TB2> INFO: Expecting 655360 events.
[13:26:22.114] <TB2> INFO: 655360 events read in total (14387ms).
[13:26:22.312] <TB2> INFO: Expecting 655360 events.
[13:26:36.989] <TB2> INFO: 655360 events read in total (14273ms).
[13:26:37.046] <TB2> INFO: Expecting 655360 events.
[13:26:51.716] <TB2> INFO: 655360 events read in total (14266ms).
[13:26:51.788] <TB2> INFO: Expecting 655360 events.
[13:27:06.325] <TB2> INFO: 655360 events read in total (14134ms).
[13:27:06.414] <TB2> INFO: Expecting 655360 events.
[13:27:21.115] <TB2> INFO: 655360 events read in total (14298ms).
[13:27:21.260] <TB2> INFO: Expecting 655360 events.
[13:27:35.720] <TB2> INFO: 655360 events read in total (14056ms).
[13:27:35.810] <TB2> INFO: Expecting 655360 events.
[13:27:50.375] <TB2> INFO: 655360 events read in total (14162ms).
[13:27:50.603] <TB2> INFO: Test took 236124ms.
[13:27:50.702] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:27:50.957] <TB2> INFO: Expecting 655360 events.
[13:28:05.605] <TB2> INFO: 655360 events read in total (14056ms).
[13:28:05.619] <TB2> INFO: Expecting 655360 events.
[13:28:20.312] <TB2> INFO: 655360 events read in total (14289ms).
[13:28:20.328] <TB2> INFO: Expecting 655360 events.
[13:28:34.702] <TB2> INFO: 655360 events read in total (13971ms).
[13:28:34.722] <TB2> INFO: Expecting 655360 events.
[13:28:49.290] <TB2> INFO: 655360 events read in total (14165ms).
[13:28:49.314] <TB2> INFO: Expecting 655360 events.
[13:29:03.839] <TB2> INFO: 655360 events read in total (14121ms).
[13:29:03.868] <TB2> INFO: Expecting 655360 events.
[13:29:18.085] <TB2> INFO: 655360 events read in total (13814ms).
[13:29:18.120] <TB2> INFO: Expecting 655360 events.
[13:29:32.782] <TB2> INFO: 655360 events read in total (14259ms).
[13:29:32.823] <TB2> INFO: Expecting 655360 events.
[13:29:47.191] <TB2> INFO: 655360 events read in total (13965ms).
[13:29:47.241] <TB2> INFO: Expecting 655360 events.
[13:30:01.352] <TB2> INFO: 655360 events read in total (13708ms).
[13:30:01.399] <TB2> INFO: Expecting 655360 events.
[13:30:15.819] <TB2> INFO: 655360 events read in total (14017ms).
[13:30:16.035] <TB2> INFO: Expecting 655360 events.
[13:30:30.485] <TB2> INFO: 655360 events read in total (14047ms).
[13:30:30.541] <TB2> INFO: Expecting 655360 events.
[13:30:44.941] <TB2> INFO: 655360 events read in total (13996ms).
[13:30:45.143] <TB2> INFO: Expecting 655360 events.
[13:30:59.538] <TB2> INFO: 655360 events read in total (13992ms).
[13:30:59.625] <TB2> INFO: Expecting 655360 events.
[13:31:13.923] <TB2> INFO: 655360 events read in total (13895ms).
[13:31:14.135] <TB2> INFO: Expecting 655360 events.
[13:31:27.925] <TB2> INFO: 655360 events read in total (13387ms).
[13:31:28.081] <TB2> INFO: Expecting 655360 events.
[13:31:42.388] <TB2> INFO: 655360 events read in total (13904ms).
[13:31:42.475] <TB2> INFO: Test took 231773ms.
[13:31:42.695] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:31:42.701] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:31:42.707] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:31:42.713] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:31:42.719] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:31:42.724] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:31:42.730] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:31:42.736] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:31:42.741] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:31:42.747] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:31:42.753] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:31:42.758] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:31:42.764] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:31:42.770] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:31:42.776] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:31:42.781] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:31:42.787] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:31:42.793] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:31:42.798] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:31:42.804] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:31:42.810] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:31:42.815] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:31:42.821] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:31:42.827] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:31:42.832] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:31:42.838] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:31:42.844] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:31:42.850] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:31:42.855] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[13:31:42.861] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[13:31:42.867] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[13:31:42.872] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[13:31:42.878] <TB2> INFO: safety margin for low PH: adding 9, margin is now 29
[13:31:42.883] <TB2> INFO: safety margin for low PH: adding 10, margin is now 30
[13:31:42.889] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:31:42.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C0.dat
[13:31:42.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C1.dat
[13:31:42.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C2.dat
[13:31:42.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C3.dat
[13:31:42.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C4.dat
[13:31:42.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C5.dat
[13:31:42.925] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C6.dat
[13:31:42.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C7.dat
[13:31:42.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C8.dat
[13:31:42.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C9.dat
[13:31:42.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C10.dat
[13:31:42.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C11.dat
[13:31:42.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C12.dat
[13:31:42.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C13.dat
[13:31:42.926] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C14.dat
[13:31:42.927] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//dacParameters35_C15.dat
[13:31:43.170] <TB2> INFO: Expecting 41600 events.
[13:31:46.354] <TB2> INFO: 41600 events read in total (2592ms).
[13:31:46.354] <TB2> INFO: Test took 3425ms.
[13:31:46.872] <TB2> INFO: Expecting 41600 events.
[13:31:49.970] <TB2> INFO: 41600 events read in total (2506ms).
[13:31:49.972] <TB2> INFO: Test took 3403ms.
[13:31:50.448] <TB2> INFO: Expecting 41600 events.
[13:31:53.611] <TB2> INFO: 41600 events read in total (2572ms).
[13:31:53.612] <TB2> INFO: Test took 3426ms.
[13:31:53.828] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:31:53.917] <TB2> INFO: Expecting 2560 events.
[13:31:54.810] <TB2> INFO: 2560 events read in total (301ms).
[13:31:54.810] <TB2> INFO: Test took 982ms.
[13:31:54.813] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:31:55.117] <TB2> INFO: Expecting 2560 events.
[13:31:55.001] <TB2> INFO: 2560 events read in total (292ms).
[13:31:55.002] <TB2> INFO: Test took 1189ms.
[13:31:56.003] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:31:56.310] <TB2> INFO: Expecting 2560 events.
[13:31:57.200] <TB2> INFO: 2560 events read in total (298ms).
[13:31:57.201] <TB2> INFO: Test took 1198ms.
[13:31:57.203] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:31:57.508] <TB2> INFO: Expecting 2560 events.
[13:31:58.404] <TB2> INFO: 2560 events read in total (305ms).
[13:31:58.404] <TB2> INFO: Test took 1201ms.
[13:31:58.407] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:31:58.713] <TB2> INFO: Expecting 2560 events.
[13:31:59.603] <TB2> INFO: 2560 events read in total (299ms).
[13:31:59.604] <TB2> INFO: Test took 1198ms.
[13:31:59.606] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:31:59.912] <TB2> INFO: Expecting 2560 events.
[13:32:00.803] <TB2> INFO: 2560 events read in total (299ms).
[13:32:00.804] <TB2> INFO: Test took 1198ms.
[13:32:00.806] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:01.112] <TB2> INFO: Expecting 2560 events.
[13:32:01.003] <TB2> INFO: 2560 events read in total (299ms).
[13:32:02.003] <TB2> INFO: Test took 1197ms.
[13:32:02.006] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:02.311] <TB2> INFO: Expecting 2560 events.
[13:32:03.207] <TB2> INFO: 2560 events read in total (304ms).
[13:32:03.208] <TB2> INFO: Test took 1202ms.
[13:32:03.210] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:03.516] <TB2> INFO: Expecting 2560 events.
[13:32:04.406] <TB2> INFO: 2560 events read in total (299ms).
[13:32:04.406] <TB2> INFO: Test took 1196ms.
[13:32:04.409] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:04.714] <TB2> INFO: Expecting 2560 events.
[13:32:05.606] <TB2> INFO: 2560 events read in total (300ms).
[13:32:05.606] <TB2> INFO: Test took 1198ms.
[13:32:05.609] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:05.914] <TB2> INFO: Expecting 2560 events.
[13:32:06.794] <TB2> INFO: 2560 events read in total (288ms).
[13:32:06.794] <TB2> INFO: Test took 1186ms.
[13:32:06.796] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:07.103] <TB2> INFO: Expecting 2560 events.
[13:32:07.988] <TB2> INFO: 2560 events read in total (293ms).
[13:32:07.988] <TB2> INFO: Test took 1192ms.
[13:32:07.991] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:08.296] <TB2> INFO: Expecting 2560 events.
[13:32:09.177] <TB2> INFO: 2560 events read in total (289ms).
[13:32:09.177] <TB2> INFO: Test took 1186ms.
[13:32:09.179] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:09.486] <TB2> INFO: Expecting 2560 events.
[13:32:10.371] <TB2> INFO: 2560 events read in total (293ms).
[13:32:10.371] <TB2> INFO: Test took 1192ms.
[13:32:10.374] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:10.680] <TB2> INFO: Expecting 2560 events.
[13:32:11.571] <TB2> INFO: 2560 events read in total (300ms).
[13:32:11.571] <TB2> INFO: Test took 1197ms.
[13:32:11.573] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:11.880] <TB2> INFO: Expecting 2560 events.
[13:32:12.765] <TB2> INFO: 2560 events read in total (294ms).
[13:32:12.765] <TB2> INFO: Test took 1193ms.
[13:32:12.768] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:13.074] <TB2> INFO: Expecting 2560 events.
[13:32:13.960] <TB2> INFO: 2560 events read in total (295ms).
[13:32:13.960] <TB2> INFO: Test took 1192ms.
[13:32:13.963] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:14.268] <TB2> INFO: Expecting 2560 events.
[13:32:15.158] <TB2> INFO: 2560 events read in total (298ms).
[13:32:15.158] <TB2> INFO: Test took 1195ms.
[13:32:15.160] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:15.467] <TB2> INFO: Expecting 2560 events.
[13:32:16.347] <TB2> INFO: 2560 events read in total (289ms).
[13:32:16.347] <TB2> INFO: Test took 1187ms.
[13:32:16.349] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:16.656] <TB2> INFO: Expecting 2560 events.
[13:32:17.546] <TB2> INFO: 2560 events read in total (298ms).
[13:32:17.546] <TB2> INFO: Test took 1197ms.
[13:32:17.549] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:17.854] <TB2> INFO: Expecting 2560 events.
[13:32:18.742] <TB2> INFO: 2560 events read in total (296ms).
[13:32:18.742] <TB2> INFO: Test took 1193ms.
[13:32:18.744] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:19.050] <TB2> INFO: Expecting 2560 events.
[13:32:19.933] <TB2> INFO: 2560 events read in total (291ms).
[13:32:19.934] <TB2> INFO: Test took 1190ms.
[13:32:19.936] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:20.242] <TB2> INFO: Expecting 2560 events.
[13:32:21.125] <TB2> INFO: 2560 events read in total (292ms).
[13:32:21.126] <TB2> INFO: Test took 1190ms.
[13:32:21.128] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:21.434] <TB2> INFO: Expecting 2560 events.
[13:32:22.319] <TB2> INFO: 2560 events read in total (294ms).
[13:32:22.320] <TB2> INFO: Test took 1192ms.
[13:32:22.322] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:22.628] <TB2> INFO: Expecting 2560 events.
[13:32:23.513] <TB2> INFO: 2560 events read in total (293ms).
[13:32:23.513] <TB2> INFO: Test took 1191ms.
[13:32:23.516] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:23.821] <TB2> INFO: Expecting 2560 events.
[13:32:24.712] <TB2> INFO: 2560 events read in total (299ms).
[13:32:24.712] <TB2> INFO: Test took 1196ms.
[13:32:24.715] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:25.019] <TB2> INFO: Expecting 2560 events.
[13:32:25.910] <TB2> INFO: 2560 events read in total (299ms).
[13:32:25.910] <TB2> INFO: Test took 1195ms.
[13:32:25.912] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:26.219] <TB2> INFO: Expecting 2560 events.
[13:32:27.110] <TB2> INFO: 2560 events read in total (300ms).
[13:32:27.110] <TB2> INFO: Test took 1198ms.
[13:32:27.113] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:27.418] <TB2> INFO: Expecting 2560 events.
[13:32:28.312] <TB2> INFO: 2560 events read in total (302ms).
[13:32:28.313] <TB2> INFO: Test took 1200ms.
[13:32:28.315] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:28.621] <TB2> INFO: Expecting 2560 events.
[13:32:29.512] <TB2> INFO: 2560 events read in total (299ms).
[13:32:29.512] <TB2> INFO: Test took 1197ms.
[13:32:29.514] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:29.820] <TB2> INFO: Expecting 2560 events.
[13:32:30.715] <TB2> INFO: 2560 events read in total (304ms).
[13:32:30.715] <TB2> INFO: Test took 1201ms.
[13:32:30.718] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:32:31.023] <TB2> INFO: Expecting 2560 events.
[13:32:31.917] <TB2> INFO: 2560 events read in total (303ms).
[13:32:31.917] <TB2> INFO: Test took 1199ms.
[13:32:32.387] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 644 seconds
[13:32:32.387] <TB2> INFO: PH scale (per ROC): 43 36 38 34 35 45 41 41 46 35 43 33 46 35 31 30
[13:32:32.388] <TB2> INFO: PH offset (per ROC): 105 100 101 109 106 95 106 92 124 102 105 105 109 109 93 107
[13:32:32.396] <TB2> INFO: Decoding statistics:
[13:32:32.397] <TB2> INFO: General information:
[13:32:32.397] <TB2> INFO: 16bit words read: 127884
[13:32:32.397] <TB2> INFO: valid events total: 20480
[13:32:32.397] <TB2> INFO: empty events: 17978
[13:32:32.397] <TB2> INFO: valid events with pixels: 2502
[13:32:32.397] <TB2> INFO: valid pixel hits: 2502
[13:32:32.397] <TB2> INFO: Event errors: 0
[13:32:32.397] <TB2> INFO: start marker: 0
[13:32:32.397] <TB2> INFO: stop marker: 0
[13:32:32.397] <TB2> INFO: overflow: 0
[13:32:32.397] <TB2> INFO: invalid 5bit words: 0
[13:32:32.397] <TB2> INFO: invalid XOR eye diagram: 0
[13:32:32.397] <TB2> INFO: frame (failed synchr.): 0
[13:32:32.397] <TB2> INFO: idle data (no TBM trl): 0
[13:32:32.397] <TB2> INFO: no data (only TBM hdr): 0
[13:32:32.397] <TB2> INFO: TBM errors: 0
[13:32:32.397] <TB2> INFO: flawed TBM headers: 0
[13:32:32.397] <TB2> INFO: flawed TBM trailers: 0
[13:32:32.397] <TB2> INFO: event ID mismatches: 0
[13:32:32.397] <TB2> INFO: ROC errors: 0
[13:32:32.397] <TB2> INFO: missing ROC header(s): 0
[13:32:32.397] <TB2> INFO: misplaced readback start: 0
[13:32:32.397] <TB2> INFO: Pixel decoding errors: 0
[13:32:32.397] <TB2> INFO: pixel data incomplete: 0
[13:32:32.397] <TB2> INFO: pixel address: 0
[13:32:32.397] <TB2> INFO: pulse height fill bit: 0
[13:32:32.397] <TB2> INFO: buffer corruption: 0
[13:32:32.619] <TB2> INFO: ######################################################################
[13:32:32.619] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:32:32.619] <TB2> INFO: ######################################################################
[13:32:32.635] <TB2> INFO: scanning low vcal = 10
[13:32:32.874] <TB2> INFO: Expecting 41600 events.
[13:32:36.501] <TB2> INFO: 41600 events read in total (3036ms).
[13:32:36.501] <TB2> INFO: Test took 3866ms.
[13:32:36.503] <TB2> INFO: scanning low vcal = 20
[13:32:36.799] <TB2> INFO: Expecting 41600 events.
[13:32:40.436] <TB2> INFO: 41600 events read in total (3045ms).
[13:32:40.436] <TB2> INFO: Test took 3933ms.
[13:32:40.438] <TB2> INFO: scanning low vcal = 30
[13:32:40.732] <TB2> INFO: Expecting 41600 events.
[13:32:44.406] <TB2> INFO: 41600 events read in total (3082ms).
[13:32:44.407] <TB2> INFO: Test took 3969ms.
[13:32:44.409] <TB2> INFO: scanning low vcal = 40
[13:32:44.686] <TB2> INFO: Expecting 41600 events.
[13:32:48.690] <TB2> INFO: 41600 events read in total (3413ms).
[13:32:48.691] <TB2> INFO: Test took 4282ms.
[13:32:48.694] <TB2> INFO: scanning low vcal = 50
[13:32:48.971] <TB2> INFO: Expecting 41600 events.
[13:32:53.066] <TB2> INFO: 41600 events read in total (3503ms).
[13:32:53.067] <TB2> INFO: Test took 4372ms.
[13:32:53.071] <TB2> INFO: scanning low vcal = 60
[13:32:53.347] <TB2> INFO: Expecting 41600 events.
[13:32:57.359] <TB2> INFO: 41600 events read in total (3421ms).
[13:32:57.360] <TB2> INFO: Test took 4289ms.
[13:32:57.364] <TB2> INFO: scanning low vcal = 70
[13:32:57.644] <TB2> INFO: Expecting 41600 events.
[13:33:01.713] <TB2> INFO: 41600 events read in total (3477ms).
[13:33:01.714] <TB2> INFO: Test took 4350ms.
[13:33:01.717] <TB2> INFO: scanning low vcal = 80
[13:33:01.994] <TB2> INFO: Expecting 41600 events.
[13:33:05.999] <TB2> INFO: 41600 events read in total (3413ms).
[13:33:05.000] <TB2> INFO: Test took 4283ms.
[13:33:05.002] <TB2> INFO: scanning low vcal = 90
[13:33:06.279] <TB2> INFO: Expecting 41600 events.
[13:33:10.278] <TB2> INFO: 41600 events read in total (3407ms).
[13:33:10.279] <TB2> INFO: Test took 4276ms.
[13:33:10.283] <TB2> INFO: scanning low vcal = 100
[13:33:10.559] <TB2> INFO: Expecting 41600 events.
[13:33:14.564] <TB2> INFO: 41600 events read in total (3413ms).
[13:33:14.565] <TB2> INFO: Test took 4282ms.
[13:33:14.568] <TB2> INFO: scanning low vcal = 110
[13:33:14.844] <TB2> INFO: Expecting 41600 events.
[13:33:18.863] <TB2> INFO: 41600 events read in total (3427ms).
[13:33:18.863] <TB2> INFO: Test took 4295ms.
[13:33:18.866] <TB2> INFO: scanning low vcal = 120
[13:33:19.143] <TB2> INFO: Expecting 41600 events.
[13:33:23.127] <TB2> INFO: 41600 events read in total (3392ms).
[13:33:23.128] <TB2> INFO: Test took 4262ms.
[13:33:23.131] <TB2> INFO: scanning low vcal = 130
[13:33:23.408] <TB2> INFO: Expecting 41600 events.
[13:33:27.484] <TB2> INFO: 41600 events read in total (3484ms).
[13:33:27.484] <TB2> INFO: Test took 4353ms.
[13:33:27.487] <TB2> INFO: scanning low vcal = 140
[13:33:27.784] <TB2> INFO: Expecting 41600 events.
[13:33:31.788] <TB2> INFO: 41600 events read in total (3413ms).
[13:33:31.789] <TB2> INFO: Test took 4301ms.
[13:33:31.792] <TB2> INFO: scanning low vcal = 150
[13:33:32.068] <TB2> INFO: Expecting 41600 events.
[13:33:36.083] <TB2> INFO: 41600 events read in total (3423ms).
[13:33:36.084] <TB2> INFO: Test took 4292ms.
[13:33:36.087] <TB2> INFO: scanning low vcal = 160
[13:33:36.364] <TB2> INFO: Expecting 41600 events.
[13:33:40.396] <TB2> INFO: 41600 events read in total (3441ms).
[13:33:40.397] <TB2> INFO: Test took 4310ms.
[13:33:40.400] <TB2> INFO: scanning low vcal = 170
[13:33:40.677] <TB2> INFO: Expecting 41600 events.
[13:33:44.685] <TB2> INFO: 41600 events read in total (3417ms).
[13:33:44.686] <TB2> INFO: Test took 4286ms.
[13:33:44.692] <TB2> INFO: scanning low vcal = 180
[13:33:44.966] <TB2> INFO: Expecting 41600 events.
[13:33:49.008] <TB2> INFO: 41600 events read in total (3451ms).
[13:33:49.009] <TB2> INFO: Test took 4317ms.
[13:33:49.012] <TB2> INFO: scanning low vcal = 190
[13:33:49.289] <TB2> INFO: Expecting 41600 events.
[13:33:53.371] <TB2> INFO: 41600 events read in total (3490ms).
[13:33:53.372] <TB2> INFO: Test took 4360ms.
[13:33:53.375] <TB2> INFO: scanning low vcal = 200
[13:33:53.652] <TB2> INFO: Expecting 41600 events.
[13:33:57.662] <TB2> INFO: 41600 events read in total (3418ms).
[13:33:57.662] <TB2> INFO: Test took 4287ms.
[13:33:57.665] <TB2> INFO: scanning low vcal = 210
[13:33:57.942] <TB2> INFO: Expecting 41600 events.
[13:34:01.999] <TB2> INFO: 41600 events read in total (3465ms).
[13:34:01.000] <TB2> INFO: Test took 4335ms.
[13:34:02.003] <TB2> INFO: scanning low vcal = 220
[13:34:02.280] <TB2> INFO: Expecting 41600 events.
[13:34:06.294] <TB2> INFO: 41600 events read in total (3422ms).
[13:34:06.295] <TB2> INFO: Test took 4292ms.
[13:34:06.298] <TB2> INFO: scanning low vcal = 230
[13:34:06.575] <TB2> INFO: Expecting 41600 events.
[13:34:10.590] <TB2> INFO: 41600 events read in total (3423ms).
[13:34:10.591] <TB2> INFO: Test took 4293ms.
[13:34:10.594] <TB2> INFO: scanning low vcal = 240
[13:34:10.870] <TB2> INFO: Expecting 41600 events.
[13:34:14.944] <TB2> INFO: 41600 events read in total (3482ms).
[13:34:14.945] <TB2> INFO: Test took 4351ms.
[13:34:14.948] <TB2> INFO: scanning low vcal = 250
[13:34:15.249] <TB2> INFO: Expecting 41600 events.
[13:34:19.303] <TB2> INFO: 41600 events read in total (3462ms).
[13:34:19.304] <TB2> INFO: Test took 4356ms.
[13:34:19.308] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[13:34:19.584] <TB2> INFO: Expecting 41600 events.
[13:34:23.603] <TB2> INFO: 41600 events read in total (3427ms).
[13:34:23.604] <TB2> INFO: Test took 4295ms.
[13:34:23.607] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[13:34:23.884] <TB2> INFO: Expecting 41600 events.
[13:34:27.854] <TB2> INFO: 41600 events read in total (3379ms).
[13:34:27.854] <TB2> INFO: Test took 4247ms.
[13:34:27.858] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[13:34:28.134] <TB2> INFO: Expecting 41600 events.
[13:34:32.106] <TB2> INFO: 41600 events read in total (3380ms).
[13:34:32.106] <TB2> INFO: Test took 4248ms.
[13:34:32.110] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[13:34:32.386] <TB2> INFO: Expecting 41600 events.
[13:34:36.350] <TB2> INFO: 41600 events read in total (3372ms).
[13:34:36.350] <TB2> INFO: Test took 4241ms.
[13:34:36.354] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:34:36.630] <TB2> INFO: Expecting 41600 events.
[13:34:40.600] <TB2> INFO: 41600 events read in total (3378ms).
[13:34:40.601] <TB2> INFO: Test took 4247ms.
[13:34:41.024] <TB2> INFO: PixTestGainPedestal::measure() done
[13:35:13.104] <TB2> INFO: PixTestGainPedestal::fit() done
[13:35:13.104] <TB2> INFO: non-linearity mean: 0.958 0.916 0.938 0.982 0.941 0.971 0.949 0.925 0.980 0.943 0.947 0.953 0.948 1.020 0.921 0.934
[13:35:13.104] <TB2> INFO: non-linearity RMS: 0.051 0.137 0.090 0.172 0.132 0.024 0.077 0.121 0.004 0.064 0.049 0.159 0.047 0.165 0.152 0.164
[13:35:13.105] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr35_C0.dat
[13:35:13.118] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr35_C1.dat
[13:35:13.131] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr35_C2.dat
[13:35:13.144] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr35_C3.dat
[13:35:13.158] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr35_C4.dat
[13:35:13.171] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr35_C5.dat
[13:35:13.185] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr35_C6.dat
[13:35:13.198] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr35_C7.dat
[13:35:13.212] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr35_C8.dat
[13:35:13.225] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr35_C9.dat
[13:35:13.238] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr35_C10.dat
[13:35:13.252] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr35_C11.dat
[13:35:13.265] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr35_C12.dat
[13:35:13.279] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr35_C13.dat
[13:35:13.292] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr35_C14.dat
[13:35:13.306] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//003_Fulltest_p17//phCalibrationFitErr35_C15.dat
[13:35:13.319] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 160 seconds
[13:35:13.319] <TB2> INFO: Decoding statistics:
[13:35:13.319] <TB2> INFO: General information:
[13:35:13.319] <TB2> INFO: 16bit words read: 3298872
[13:35:13.319] <TB2> INFO: valid events total: 332800
[13:35:13.319] <TB2> INFO: empty events: 1560
[13:35:13.319] <TB2> INFO: valid events with pixels: 331240
[13:35:13.319] <TB2> INFO: valid pixel hits: 651036
[13:35:13.319] <TB2> INFO: Event errors: 0
[13:35:13.319] <TB2> INFO: start marker: 0
[13:35:13.319] <TB2> INFO: stop marker: 0
[13:35:13.319] <TB2> INFO: overflow: 0
[13:35:13.319] <TB2> INFO: invalid 5bit words: 0
[13:35:13.319] <TB2> INFO: invalid XOR eye diagram: 0
[13:35:13.319] <TB2> INFO: frame (failed synchr.): 0
[13:35:13.319] <TB2> INFO: idle data (no TBM trl): 0
[13:35:13.319] <TB2> INFO: no data (only TBM hdr): 0
[13:35:13.319] <TB2> INFO: TBM errors: 0
[13:35:13.319] <TB2> INFO: flawed TBM headers: 0
[13:35:13.319] <TB2> INFO: flawed TBM trailers: 0
[13:35:13.319] <TB2> INFO: event ID mismatches: 0
[13:35:13.319] <TB2> INFO: ROC errors: 0
[13:35:13.319] <TB2> INFO: missing ROC header(s): 0
[13:35:13.319] <TB2> INFO: misplaced readback start: 0
[13:35:13.319] <TB2> INFO: Pixel decoding errors: 0
[13:35:13.319] <TB2> INFO: pixel data incomplete: 0
[13:35:13.319] <TB2> INFO: pixel address: 0
[13:35:13.319] <TB2> INFO: pulse height fill bit: 0
[13:35:13.319] <TB2> INFO: buffer corruption: 0
[13:35:13.335] <TB2> INFO: Decoding statistics:
[13:35:13.335] <TB2> INFO: General information:
[13:35:13.335] <TB2> INFO: 16bit words read: 3428292
[13:35:13.335] <TB2> INFO: valid events total: 353536
[13:35:13.335] <TB2> INFO: empty events: 19794
[13:35:13.335] <TB2> INFO: valid events with pixels: 333742
[13:35:13.335] <TB2> INFO: valid pixel hits: 653538
[13:35:13.335] <TB2> INFO: Event errors: 0
[13:35:13.335] <TB2> INFO: start marker: 0
[13:35:13.335] <TB2> INFO: stop marker: 0
[13:35:13.335] <TB2> INFO: overflow: 0
[13:35:13.335] <TB2> INFO: invalid 5bit words: 0
[13:35:13.335] <TB2> INFO: invalid XOR eye diagram: 0
[13:35:13.335] <TB2> INFO: frame (failed synchr.): 0
[13:35:13.335] <TB2> INFO: idle data (no TBM trl): 0
[13:35:13.335] <TB2> INFO: no data (only TBM hdr): 0
[13:35:13.335] <TB2> INFO: TBM errors: 0
[13:35:13.335] <TB2> INFO: flawed TBM headers: 0
[13:35:13.335] <TB2> INFO: flawed TBM trailers: 0
[13:35:13.335] <TB2> INFO: event ID mismatches: 0
[13:35:13.335] <TB2> INFO: ROC errors: 0
[13:35:13.335] <TB2> INFO: missing ROC header(s): 0
[13:35:13.335] <TB2> INFO: misplaced readback start: 0
[13:35:13.335] <TB2> INFO: Pixel decoding errors: 0
[13:35:13.335] <TB2> INFO: pixel data incomplete: 0
[13:35:13.335] <TB2> INFO: pixel address: 0
[13:35:13.335] <TB2> INFO: pulse height fill bit: 0
[13:35:13.335] <TB2> INFO: buffer corruption: 0
[13:35:13.335] <TB2> INFO: enter test to run
[13:35:13.335] <TB2> INFO: test: exit no parameter change
[13:35:13.458] <TB2> QUIET: Connection to board 149 closed.
[13:35:13.458] <TB2> INFO: pXar: this is the end, my friend