[10:37:13.080] <TB2> INFO: *** Welcome to pxar ***
[10:37:13.080] <TB2> INFO: *** Today: 2016/10/20
[10:37:13.086] <TB2> INFO: *** Version: c8ba-dirty
[10:37:13.086] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C15.dat
[10:37:13.086] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//tbmParameters_C1b.dat
[10:37:13.086] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//defaultMaskFile.dat
[10:37:13.086] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters_C15.dat
[10:37:13.149] <TB2> INFO: clk: 4
[10:37:13.149] <TB2> INFO: ctr: 4
[10:37:13.149] <TB2> INFO: sda: 19
[10:37:13.149] <TB2> INFO: tin: 9
[10:37:13.149] <TB2> INFO: level: 15
[10:37:13.149] <TB2> INFO: triggerdelay: 0
[10:37:13.149] <TB2> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[10:37:13.149] <TB2> INFO: Log level: INFO
[10:37:13.158] <TB2> INFO: Found DTB DTB_WWXUD2
[10:37:13.165] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[10:37:13.167] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[10:37:13.169] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[10:37:14.661] <TB2> INFO: DUT info:
[10:37:14.661] <TB2> INFO: The DUT currently contains the following objects:
[10:37:14.661] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[10:37:14.661] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:37:14.661] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:37:14.661] <TB2> INFO: TBM Core alpha (2): 7 registers set
[10:37:14.661] <TB2> INFO: TBM Core beta (3): 7 registers set
[10:37:14.661] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[10:37:14.661] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[10:37:14.661] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[10:37:14.661] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[10:37:14.661] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[10:37:14.661] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[10:37:14.662] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[10:37:14.662] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[10:37:14.662] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[10:37:14.662] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[10:37:14.662] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[10:37:14.662] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[10:37:14.662] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[10:37:14.662] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[10:37:14.662] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[10:37:14.662] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[10:37:14.662] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[10:37:15.063] <TB2> INFO: enter 'restricted' command line mode
[10:37:15.063] <TB2> INFO: enter test to run
[10:37:15.063] <TB2> INFO: test: pretest no parameter change
[10:37:15.063] <TB2> INFO: running: pretest
[10:37:15.070] <TB2> INFO: ######################################################################
[10:37:15.070] <TB2> INFO: PixTestPretest::doTest()
[10:37:15.070] <TB2> INFO: ######################################################################
[10:37:15.071] <TB2> INFO: ----------------------------------------------------------------------
[10:37:15.071] <TB2> INFO: PixTestPretest::programROC()
[10:37:15.071] <TB2> INFO: ----------------------------------------------------------------------
[10:37:33.085] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[10:37:33.085] <TB2> INFO: IA differences per ROC: 16.9 20.1 17.7 20.9 20.9 21.7 19.3 16.1 19.3 19.3 19.3 20.9 16.1 20.9 23.3 17.7
[10:37:33.154] <TB2> INFO: ----------------------------------------------------------------------
[10:37:33.154] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[10:37:33.154] <TB2> INFO: ----------------------------------------------------------------------
[10:37:54.447] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 379.4 mA = 23.7125 mA/ROC
[10:37:54.448] <TB2> INFO: i(loss) [mA/ROC]: 20.1 20.1 18.5 19.3 20.1 19.3 19.3 19.3 19.3 19.3 20.1 19.3 18.5 19.3 20.1 18.5
[10:37:54.484] <TB2> INFO: ----------------------------------------------------------------------
[10:37:54.484] <TB2> INFO: PixTestPretest::findTiming()
[10:37:54.484] <TB2> INFO: ----------------------------------------------------------------------
[10:37:54.484] <TB2> INFO: PixTestCmd::init()

[10:38:26.795] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[10:38:26.795] <TB2> INFO: (success/tries = 100/100), width = 3
[10:38:28.299] <TB2> INFO: ----------------------------------------------------------------------
[10:38:28.299] <TB2> INFO: PixTestPretest::findWorkingPixel()
[10:38:28.299] <TB2> INFO: ----------------------------------------------------------------------
[10:38:28.392] <TB2> INFO: Expecting 231680 events.
[10:38:38.190] <TB2> INFO: 231680 events read in total (9206ms).
[10:38:38.198] <TB2> INFO: Test took 9896ms.
[10:38:38.444] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[10:38:38.475] <TB2> INFO: ----------------------------------------------------------------------
[10:38:38.475] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[10:38:38.475] <TB2> INFO: ----------------------------------------------------------------------
[10:38:38.569] <TB2> INFO: Expecting 231680 events.
[10:38:48.478] <TB2> INFO: 231680 events read in total (9317ms).
[10:38:48.486] <TB2> INFO: Test took 10005ms.
[10:38:48.737] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[10:38:48.737] <TB2> INFO: CalDel: 105 117 107 108 118 109 109 89 110 103 113 118 98 113 106 111
[10:38:48.737] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 53 51 51 53
[10:38:48.739] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C0.dat
[10:38:48.739] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C1.dat
[10:38:48.739] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C2.dat
[10:38:48.740] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C3.dat
[10:38:48.740] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C4.dat
[10:38:48.740] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C5.dat
[10:38:48.740] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C6.dat
[10:38:48.740] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C7.dat
[10:38:48.740] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C8.dat
[10:38:48.740] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C9.dat
[10:38:48.740] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C10.dat
[10:38:48.740] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C11.dat
[10:38:48.741] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C12.dat
[10:38:48.741] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C13.dat
[10:38:48.741] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C14.dat
[10:38:48.741] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters_C15.dat
[10:38:48.741] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//tbmParameters_C0a.dat
[10:38:48.741] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//tbmParameters_C0b.dat
[10:38:48.741] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//tbmParameters_C1a.dat
[10:38:48.741] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//tbmParameters_C1b.dat
[10:38:48.741] <TB2> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[10:38:48.794] <TB2> INFO: enter test to run
[10:38:48.794] <TB2> INFO: test: FullTest no parameter change
[10:38:48.794] <TB2> INFO: running: fulltest
[10:38:48.794] <TB2> INFO: ######################################################################
[10:38:48.794] <TB2> INFO: PixTestFullTest::doTest()
[10:38:48.794] <TB2> INFO: ######################################################################
[10:38:48.795] <TB2> INFO: ######################################################################
[10:38:48.795] <TB2> INFO: PixTestAlive::doTest()
[10:38:48.795] <TB2> INFO: ######################################################################
[10:38:48.796] <TB2> INFO: ----------------------------------------------------------------------
[10:38:48.797] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:38:48.797] <TB2> INFO: ----------------------------------------------------------------------
[10:38:49.033] <TB2> INFO: Expecting 41600 events.
[10:38:52.583] <TB2> INFO: 41600 events read in total (2958ms).
[10:38:52.584] <TB2> INFO: Test took 3786ms.
[10:38:52.821] <TB2> INFO: PixTestAlive::aliveTest() done
[10:38:52.821] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:38:52.823] <TB2> INFO: ----------------------------------------------------------------------
[10:38:52.823] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:38:52.823] <TB2> INFO: ----------------------------------------------------------------------
[10:38:53.067] <TB2> INFO: Expecting 41600 events.
[10:38:56.034] <TB2> INFO: 41600 events read in total (2376ms).
[10:38:56.035] <TB2> INFO: Test took 3210ms.
[10:38:56.035] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[10:38:56.279] <TB2> INFO: PixTestAlive::maskTest() done
[10:38:56.279] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:38:56.281] <TB2> INFO: ----------------------------------------------------------------------
[10:38:56.281] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[10:38:56.281] <TB2> INFO: ----------------------------------------------------------------------
[10:38:56.521] <TB2> INFO: Expecting 41600 events.
[10:39:00.053] <TB2> INFO: 41600 events read in total (2939ms).
[10:39:00.054] <TB2> INFO: Test took 3771ms.
[10:39:00.290] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[10:39:00.290] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[10:39:00.291] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[10:39:00.291] <TB2> INFO: Decoding statistics:
[10:39:00.291] <TB2> INFO: General information:
[10:39:00.291] <TB2> INFO: 16bit words read: 0
[10:39:00.291] <TB2> INFO: valid events total: 0
[10:39:00.291] <TB2> INFO: empty events: 0
[10:39:00.291] <TB2> INFO: valid events with pixels: 0
[10:39:00.291] <TB2> INFO: valid pixel hits: 0
[10:39:00.291] <TB2> INFO: Event errors: 0
[10:39:00.291] <TB2> INFO: start marker: 0
[10:39:00.291] <TB2> INFO: stop marker: 0
[10:39:00.291] <TB2> INFO: overflow: 0
[10:39:00.291] <TB2> INFO: invalid 5bit words: 0
[10:39:00.291] <TB2> INFO: invalid XOR eye diagram: 0
[10:39:00.291] <TB2> INFO: frame (failed synchr.): 0
[10:39:00.291] <TB2> INFO: idle data (no TBM trl): 0
[10:39:00.291] <TB2> INFO: no data (only TBM hdr): 0
[10:39:00.291] <TB2> INFO: TBM errors: 0
[10:39:00.291] <TB2> INFO: flawed TBM headers: 0
[10:39:00.291] <TB2> INFO: flawed TBM trailers: 0
[10:39:00.291] <TB2> INFO: event ID mismatches: 0
[10:39:00.291] <TB2> INFO: ROC errors: 0
[10:39:00.291] <TB2> INFO: missing ROC header(s): 0
[10:39:00.291] <TB2> INFO: misplaced readback start: 0
[10:39:00.291] <TB2> INFO: Pixel decoding errors: 0
[10:39:00.291] <TB2> INFO: pixel data incomplete: 0
[10:39:00.291] <TB2> INFO: pixel address: 0
[10:39:00.291] <TB2> INFO: pulse height fill bit: 0
[10:39:00.291] <TB2> INFO: buffer corruption: 0
[10:39:00.298] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C15.dat
[10:39:00.299] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[10:39:00.299] <TB2> INFO: ######################################################################
[10:39:00.299] <TB2> INFO: PixTestReadback::doTest()
[10:39:00.299] <TB2> INFO: ######################################################################
[10:39:00.299] <TB2> INFO: ----------------------------------------------------------------------
[10:39:00.299] <TB2> INFO: PixTestReadback::CalibrateVd()
[10:39:00.299] <TB2> INFO: ----------------------------------------------------------------------
[10:39:10.256] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C0.dat
[10:39:10.256] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C1.dat
[10:39:10.256] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C2.dat
[10:39:10.256] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C3.dat
[10:39:10.256] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C4.dat
[10:39:10.256] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C5.dat
[10:39:10.257] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C6.dat
[10:39:10.257] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C7.dat
[10:39:10.257] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C8.dat
[10:39:10.257] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C9.dat
[10:39:10.257] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C10.dat
[10:39:10.257] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C11.dat
[10:39:10.257] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C12.dat
[10:39:10.257] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C13.dat
[10:39:10.257] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C14.dat
[10:39:10.257] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C15.dat
[10:39:10.291] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:39:10.291] <TB2> INFO: ----------------------------------------------------------------------
[10:39:10.291] <TB2> INFO: PixTestReadback::CalibrateVa()
[10:39:10.291] <TB2> INFO: ----------------------------------------------------------------------
[10:39:20.231] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C0.dat
[10:39:20.232] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C1.dat
[10:39:20.232] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C2.dat
[10:39:20.232] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C3.dat
[10:39:20.232] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C4.dat
[10:39:20.232] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C5.dat
[10:39:20.232] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C6.dat
[10:39:20.232] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C7.dat
[10:39:20.232] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C8.dat
[10:39:20.232] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C9.dat
[10:39:20.232] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C10.dat
[10:39:20.232] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C11.dat
[10:39:20.232] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C12.dat
[10:39:20.232] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C13.dat
[10:39:20.232] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C14.dat
[10:39:20.232] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C15.dat
[10:39:20.262] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:39:20.262] <TB2> INFO: ----------------------------------------------------------------------
[10:39:20.262] <TB2> INFO: PixTestReadback::readbackVbg()
[10:39:20.262] <TB2> INFO: ----------------------------------------------------------------------
[10:39:27.935] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:39:27.935] <TB2> INFO: ----------------------------------------------------------------------
[10:39:27.935] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[10:39:27.935] <TB2> INFO: ----------------------------------------------------------------------
[10:39:27.935] <TB2> INFO: Vbg will be calibrated using Vd calibration
[10:39:27.935] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 156.1calibrated Vbg = 1.17959 :::*/*/*/*/
[10:39:27.935] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 155.1calibrated Vbg = 1.1799 :::*/*/*/*/
[10:39:27.935] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 154.2calibrated Vbg = 1.17912 :::*/*/*/*/
[10:39:27.936] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 152.3calibrated Vbg = 1.18211 :::*/*/*/*/
[10:39:27.936] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 148.9calibrated Vbg = 1.17436 :::*/*/*/*/
[10:39:27.936] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 149.4calibrated Vbg = 1.18428 :::*/*/*/*/
[10:39:27.936] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 163.2calibrated Vbg = 1.18234 :::*/*/*/*/
[10:39:27.936] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 164.8calibrated Vbg = 1.18095 :::*/*/*/*/
[10:39:27.936] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 161calibrated Vbg = 1.17647 :::*/*/*/*/
[10:39:27.936] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 157calibrated Vbg = 1.17745 :::*/*/*/*/
[10:39:27.936] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 155.4calibrated Vbg = 1.1738 :::*/*/*/*/
[10:39:27.936] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 159.9calibrated Vbg = 1.16875 :::*/*/*/*/
[10:39:27.936] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 168.3calibrated Vbg = 1.17274 :::*/*/*/*/
[10:39:27.936] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 151.4calibrated Vbg = 1.17844 :::*/*/*/*/
[10:39:27.936] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 153.2calibrated Vbg = 1.17759 :::*/*/*/*/
[10:39:27.936] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 165.1calibrated Vbg = 1.18262 :::*/*/*/*/
[10:39:27.938] <TB2> INFO: ----------------------------------------------------------------------
[10:39:27.938] <TB2> INFO: PixTestReadback::CalibrateIa()
[10:39:27.938] <TB2> INFO: ----------------------------------------------------------------------
[10:42:08.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C0.dat
[10:42:08.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C1.dat
[10:42:08.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C2.dat
[10:42:08.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C3.dat
[10:42:08.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C4.dat
[10:42:08.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C5.dat
[10:42:08.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C6.dat
[10:42:08.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C7.dat
[10:42:08.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C8.dat
[10:42:08.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C9.dat
[10:42:08.771] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C10.dat
[10:42:08.772] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C11.dat
[10:42:08.772] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C12.dat
[10:42:08.772] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C13.dat
[10:42:08.772] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C14.dat
[10:42:08.772] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//readbackCal_C15.dat
[10:42:08.802] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[10:42:08.804] <TB2> INFO: PixTestReadback::doTest() done
[10:42:08.804] <TB2> INFO: Decoding statistics:
[10:42:08.804] <TB2> INFO: General information:
[10:42:08.804] <TB2> INFO: 16bit words read: 1536
[10:42:08.804] <TB2> INFO: valid events total: 256
[10:42:08.804] <TB2> INFO: empty events: 256
[10:42:08.804] <TB2> INFO: valid events with pixels: 0
[10:42:08.804] <TB2> INFO: valid pixel hits: 0
[10:42:08.804] <TB2> INFO: Event errors: 0
[10:42:08.804] <TB2> INFO: start marker: 0
[10:42:08.804] <TB2> INFO: stop marker: 0
[10:42:08.804] <TB2> INFO: overflow: 0
[10:42:08.804] <TB2> INFO: invalid 5bit words: 0
[10:42:08.804] <TB2> INFO: invalid XOR eye diagram: 0
[10:42:08.804] <TB2> INFO: frame (failed synchr.): 0
[10:42:08.804] <TB2> INFO: idle data (no TBM trl): 0
[10:42:08.804] <TB2> INFO: no data (only TBM hdr): 0
[10:42:08.804] <TB2> INFO: TBM errors: 0
[10:42:08.805] <TB2> INFO: flawed TBM headers: 0
[10:42:08.805] <TB2> INFO: flawed TBM trailers: 0
[10:42:08.805] <TB2> INFO: event ID mismatches: 0
[10:42:08.805] <TB2> INFO: ROC errors: 0
[10:42:08.805] <TB2> INFO: missing ROC header(s): 0
[10:42:08.805] <TB2> INFO: misplaced readback start: 0
[10:42:08.805] <TB2> INFO: Pixel decoding errors: 0
[10:42:08.805] <TB2> INFO: pixel data incomplete: 0
[10:42:08.805] <TB2> INFO: pixel address: 0
[10:42:08.805] <TB2> INFO: pulse height fill bit: 0
[10:42:08.805] <TB2> INFO: buffer corruption: 0
[10:42:08.854] <TB2> INFO: ######################################################################
[10:42:08.854] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[10:42:08.854] <TB2> INFO: ######################################################################
[10:42:08.857] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[10:42:08.873] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[10:42:08.873] <TB2> INFO: run 1 of 1
[10:42:09.118] <TB2> INFO: Expecting 3120000 events.
[10:42:39.922] <TB2> INFO: 660670 events read in total (30212ms).





















[10:43:09.699] <TB2> INFO: 1316205 events read in total (59989ms).











[10:43:39.749] <TB2> INFO: 1971250 events read in total (90039ms).











[10:44:09.692] <TB2> INFO: 2627695 events read in total (119982ms).











[10:44:31.723] <TB2> INFO: 3120000 events read in total (142013ms).
[10:44:31.787] <TB2> INFO: Test took 142915ms.
[10:44:53.733] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 164 seconds
[10:44:53.733] <TB2> INFO: number of dead bumps (per ROC): 0 1 0 15 1 0 1 0 0 0 0 1 2 0 0 0
[10:44:53.733] <TB2> INFO: separation cut (per ROC): 102 101 98 87 100 90 101 103 104 105 107 109 104 98 107 104
[10:44:53.733] <TB2> INFO: Decoding statistics:
[10:44:53.733] <TB2> INFO: General information:
[10:44:53.733] <TB2> INFO: 16bit words read: 0
[10:44:53.733] <TB2> INFO: valid events total: 0
[10:44:53.733] <TB2> INFO: empty events: 0
[10:44:53.733] <TB2> INFO: valid events with pixels: 0
[10:44:53.733] <TB2> INFO: valid pixel hits: 0
[10:44:53.733] <TB2> INFO: Event errors: 0
[10:44:53.733] <TB2> INFO: start marker: 0
[10:44:53.733] <TB2> INFO: stop marker: 0
[10:44:53.733] <TB2> INFO: overflow: 0
[10:44:53.734] <TB2> INFO: invalid 5bit words: 0
[10:44:53.734] <TB2> INFO: invalid XOR eye diagram: 0
[10:44:53.734] <TB2> INFO: frame (failed synchr.): 0
[10:44:53.734] <TB2> INFO: idle data (no TBM trl): 0
[10:44:53.734] <TB2> INFO: no data (only TBM hdr): 0
[10:44:53.734] <TB2> INFO: TBM errors: 0
[10:44:53.734] <TB2> INFO: flawed TBM headers: 0
[10:44:53.734] <TB2> INFO: flawed TBM trailers: 0
[10:44:53.734] <TB2> INFO: event ID mismatches: 0
[10:44:53.734] <TB2> INFO: ROC errors: 0
[10:44:53.734] <TB2> INFO: missing ROC header(s): 0
[10:44:53.734] <TB2> INFO: misplaced readback start: 0
[10:44:53.734] <TB2> INFO: Pixel decoding errors: 0
[10:44:53.734] <TB2> INFO: pixel data incomplete: 0
[10:44:53.734] <TB2> INFO: pixel address: 0
[10:44:53.734] <TB2> INFO: pulse height fill bit: 0
[10:44:53.734] <TB2> INFO: buffer corruption: 0
[10:44:53.772] <TB2> INFO: ######################################################################
[10:44:53.772] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[10:44:53.772] <TB2> INFO: ######################################################################
[10:44:53.772] <TB2> INFO: ----------------------------------------------------------------------
[10:44:53.772] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[10:44:53.773] <TB2> INFO: ----------------------------------------------------------------------
[10:44:53.773] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[10:44:53.788] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[10:44:53.788] <TB2> INFO: run 1 of 1
[10:44:54.047] <TB2> INFO: Expecting 36608000 events.
[10:45:17.924] <TB2> INFO: 682850 events read in total (23285ms).
[10:45:41.018] <TB2> INFO: 1353450 events read in total (46379ms).
[10:46:04.196] <TB2> INFO: 2021750 events read in total (69557ms).
[10:46:27.331] <TB2> INFO: 2691200 events read in total (92692ms).
[10:46:50.639] <TB2> INFO: 3359000 events read in total (116000ms).
[10:47:13.815] <TB2> INFO: 4025950 events read in total (139176ms).
[10:47:37.150] <TB2> INFO: 4692550 events read in total (162511ms).
[10:48:00.585] <TB2> INFO: 5358200 events read in total (185946ms).
[10:48:23.738] <TB2> INFO: 6024400 events read in total (209099ms).
[10:48:47.268] <TB2> INFO: 6691200 events read in total (232629ms).
[10:49:10.048] <TB2> INFO: 7356750 events read in total (255409ms).
[10:49:33.082] <TB2> INFO: 8023050 events read in total (278443ms).
[10:49:56.300] <TB2> INFO: 8690300 events read in total (301661ms).
[10:50:19.345] <TB2> INFO: 9357150 events read in total (324706ms).
[10:50:42.519] <TB2> INFO: 10023950 events read in total (347880ms).
[10:51:05.507] <TB2> INFO: 10689500 events read in total (370868ms).
[10:51:28.832] <TB2> INFO: 11354600 events read in total (394193ms).
[10:51:51.744] <TB2> INFO: 12019550 events read in total (417105ms).
[10:52:14.729] <TB2> INFO: 12685550 events read in total (440090ms).
[10:52:37.668] <TB2> INFO: 13348250 events read in total (463029ms).
[10:53:00.544] <TB2> INFO: 14012050 events read in total (485905ms).
[10:53:23.807] <TB2> INFO: 14676150 events read in total (509168ms).
[10:53:46.443] <TB2> INFO: 15338450 events read in total (531804ms).
[10:54:09.365] <TB2> INFO: 16002700 events read in total (554726ms).
[10:54:32.105] <TB2> INFO: 16665900 events read in total (577466ms).
[10:54:55.251] <TB2> INFO: 17329150 events read in total (600612ms).
[10:55:18.017] <TB2> INFO: 17990300 events read in total (623378ms).
[10:55:40.655] <TB2> INFO: 18651450 events read in total (646016ms).
[10:56:03.325] <TB2> INFO: 19312600 events read in total (668686ms).
[10:56:25.938] <TB2> INFO: 19973100 events read in total (691299ms).
[10:56:48.625] <TB2> INFO: 20632100 events read in total (713987ms).
[10:57:11.361] <TB2> INFO: 21293250 events read in total (736722ms).
[10:57:34.507] <TB2> INFO: 21954350 events read in total (759868ms).
[10:57:57.358] <TB2> INFO: 22615450 events read in total (782719ms).
[10:58:20.300] <TB2> INFO: 23274100 events read in total (805661ms).
[10:58:42.832] <TB2> INFO: 23932700 events read in total (828193ms).
[10:59:05.217] <TB2> INFO: 24589850 events read in total (850578ms).
[10:59:28.051] <TB2> INFO: 25248500 events read in total (873412ms).
[10:59:50.798] <TB2> INFO: 25907500 events read in total (896159ms).
[11:00:13.327] <TB2> INFO: 26568750 events read in total (918688ms).
[11:00:35.840] <TB2> INFO: 27227500 events read in total (941201ms).
[11:00:58.675] <TB2> INFO: 27885950 events read in total (964036ms).
[11:01:21.506] <TB2> INFO: 28543850 events read in total (986867ms).
[11:01:43.953] <TB2> INFO: 29200550 events read in total (1009314ms).
[11:02:06.542] <TB2> INFO: 29858700 events read in total (1031903ms).
[11:02:29.079] <TB2> INFO: 30515350 events read in total (1054440ms).
[11:02:51.655] <TB2> INFO: 31171250 events read in total (1077016ms).
[11:03:14.364] <TB2> INFO: 31827150 events read in total (1099725ms).
[11:03:37.195] <TB2> INFO: 32486050 events read in total (1122556ms).
[11:03:59.788] <TB2> INFO: 33142300 events read in total (1145149ms).
[11:04:22.389] <TB2> INFO: 33799900 events read in total (1167750ms).
[11:04:45.370] <TB2> INFO: 34458150 events read in total (1190731ms).
[11:05:07.887] <TB2> INFO: 35116250 events read in total (1213248ms).
[11:05:30.686] <TB2> INFO: 35774150 events read in total (1236047ms).
[11:05:54.118] <TB2> INFO: 36442400 events read in total (1259479ms).
[11:06:00.232] <TB2> INFO: 36608000 events read in total (1265593ms).
[11:06:00.339] <TB2> INFO: Test took 1266550ms.
[11:06:00.802] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:06:02.482] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:06:04.517] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:06:06.267] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:06:08.137] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:06:10.137] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:06:11.736] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:06:13.644] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:06:16.038] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:06:17.880] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:06:19.977] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:06:21.797] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:06:23.749] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:06:25.855] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:06:27.962] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:06:29.581] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:06:31.125] <TB2> INFO: PixTestScurves::scurves() done
[11:06:31.125] <TB2> INFO: Vcal mean: 117.33 112.31 113.51 109.08 121.71 108.12 117.74 117.27 124.82 125.02 121.11 127.71 118.05 107.96 112.47 115.34
[11:06:31.125] <TB2> INFO: Vcal RMS: 5.89 5.23 5.38 5.19 6.08 6.06 5.68 5.82 6.46 6.47 6.96 6.87 5.93 5.15 5.41 6.00
[11:06:31.125] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1297 seconds
[11:06:31.125] <TB2> INFO: Decoding statistics:
[11:06:31.125] <TB2> INFO: General information:
[11:06:31.125] <TB2> INFO: 16bit words read: 0
[11:06:31.125] <TB2> INFO: valid events total: 0
[11:06:31.125] <TB2> INFO: empty events: 0
[11:06:31.125] <TB2> INFO: valid events with pixels: 0
[11:06:31.125] <TB2> INFO: valid pixel hits: 0
[11:06:31.125] <TB2> INFO: Event errors: 0
[11:06:31.125] <TB2> INFO: start marker: 0
[11:06:31.125] <TB2> INFO: stop marker: 0
[11:06:31.126] <TB2> INFO: overflow: 0
[11:06:31.126] <TB2> INFO: invalid 5bit words: 0
[11:06:31.126] <TB2> INFO: invalid XOR eye diagram: 0
[11:06:31.126] <TB2> INFO: frame (failed synchr.): 0
[11:06:31.126] <TB2> INFO: idle data (no TBM trl): 0
[11:06:31.126] <TB2> INFO: no data (only TBM hdr): 0
[11:06:31.126] <TB2> INFO: TBM errors: 0
[11:06:31.126] <TB2> INFO: flawed TBM headers: 0
[11:06:31.126] <TB2> INFO: flawed TBM trailers: 0
[11:06:31.126] <TB2> INFO: event ID mismatches: 0
[11:06:31.126] <TB2> INFO: ROC errors: 0
[11:06:31.126] <TB2> INFO: missing ROC header(s): 0
[11:06:31.126] <TB2> INFO: misplaced readback start: 0
[11:06:31.126] <TB2> INFO: Pixel decoding errors: 0
[11:06:31.126] <TB2> INFO: pixel data incomplete: 0
[11:06:31.126] <TB2> INFO: pixel address: 0
[11:06:31.126] <TB2> INFO: pulse height fill bit: 0
[11:06:31.126] <TB2> INFO: buffer corruption: 0
[11:06:31.196] <TB2> INFO: ######################################################################
[11:06:31.196] <TB2> INFO: PixTestTrim::doTest()
[11:06:31.196] <TB2> INFO: ######################################################################
[11:06:31.197] <TB2> INFO: ----------------------------------------------------------------------
[11:06:31.197] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[11:06:31.197] <TB2> INFO: ----------------------------------------------------------------------
[11:06:31.239] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[11:06:31.239] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:06:31.252] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:06:31.252] <TB2> INFO: run 1 of 1
[11:06:31.506] <TB2> INFO: Expecting 5025280 events.
[11:07:02.221] <TB2> INFO: 828960 events read in total (30115ms).
[11:07:32.608] <TB2> INFO: 1654816 events read in total (60502ms).
[11:08:02.965] <TB2> INFO: 2477600 events read in total (90859ms).
[11:08:33.245] <TB2> INFO: 3298720 events read in total (121139ms).
[11:09:03.687] <TB2> INFO: 4116768 events read in total (151581ms).
[11:09:34.124] <TB2> INFO: 4933504 events read in total (182018ms).
[11:09:37.816] <TB2> INFO: 5025280 events read in total (185710ms).
[11:09:37.870] <TB2> INFO: Test took 186619ms.
[11:09:55.418] <TB2> INFO: ROC 0 VthrComp = 116
[11:09:55.418] <TB2> INFO: ROC 1 VthrComp = 112
[11:09:55.418] <TB2> INFO: ROC 2 VthrComp = 108
[11:09:55.419] <TB2> INFO: ROC 3 VthrComp = 112
[11:09:55.419] <TB2> INFO: ROC 4 VthrComp = 119
[11:09:55.419] <TB2> INFO: ROC 5 VthrComp = 106
[11:09:55.419] <TB2> INFO: ROC 6 VthrComp = 116
[11:09:55.419] <TB2> INFO: ROC 7 VthrComp = 115
[11:09:55.419] <TB2> INFO: ROC 8 VthrComp = 123
[11:09:55.419] <TB2> INFO: ROC 9 VthrComp = 124
[11:09:55.419] <TB2> INFO: ROC 10 VthrComp = 118
[11:09:55.419] <TB2> INFO: ROC 11 VthrComp = 128
[11:09:55.420] <TB2> INFO: ROC 12 VthrComp = 117
[11:09:55.420] <TB2> INFO: ROC 13 VthrComp = 109
[11:09:55.420] <TB2> INFO: ROC 14 VthrComp = 116
[11:09:55.420] <TB2> INFO: ROC 15 VthrComp = 115
[11:09:55.706] <TB2> INFO: Expecting 41600 events.
[11:09:59.254] <TB2> INFO: 41600 events read in total (2956ms).
[11:09:59.255] <TB2> INFO: Test took 3834ms.
[11:09:59.266] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[11:09:59.266] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:09:59.280] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:09:59.280] <TB2> INFO: run 1 of 1
[11:09:59.558] <TB2> INFO: Expecting 5025280 events.
[11:10:25.514] <TB2> INFO: 591912 events read in total (25364ms).
[11:10:50.917] <TB2> INFO: 1183032 events read in total (50767ms).
[11:11:16.385] <TB2> INFO: 1774152 events read in total (76235ms).
[11:11:41.778] <TB2> INFO: 2364720 events read in total (101628ms).
[11:12:07.817] <TB2> INFO: 2953128 events read in total (127667ms).
[11:12:33.346] <TB2> INFO: 3540056 events read in total (153196ms).
[11:12:59.151] <TB2> INFO: 4125904 events read in total (179001ms).
[11:13:25.428] <TB2> INFO: 4711056 events read in total (205278ms).
[11:13:39.115] <TB2> INFO: 5025280 events read in total (218965ms).
[11:13:39.233] <TB2> INFO: Test took 219953ms.
[11:14:03.536] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 61.9873 for pixel 21/5 mean/min/max = 46.5165/30.9496/62.0834
[11:14:03.537] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 62.0706 for pixel 20/4 mean/min/max = 47.0731/32.0693/62.077
[11:14:03.537] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 64.4605 for pixel 6/44 mean/min/max = 49.08/33.6321/64.5279
[11:14:03.537] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 60.1697 for pixel 0/24 mean/min/max = 46.0883/31.9725/60.2042
[11:14:03.538] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 62.3026 for pixel 32/0 mean/min/max = 46.4268/30.465/62.3887
[11:14:03.538] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 64.4375 for pixel 4/0 mean/min/max = 48.8936/33.0928/64.6945
[11:14:03.539] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 62.2193 for pixel 20/11 mean/min/max = 46.7617/30.9215/62.602
[11:14:03.539] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 62.6564 for pixel 23/11 mean/min/max = 47.1973/31.5573/62.8373
[11:14:03.540] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 64.0066 for pixel 33/0 mean/min/max = 47.1115/30.1634/64.0597
[11:14:03.540] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 63.77 for pixel 10/69 mean/min/max = 47.3051/30.7183/63.8919
[11:14:03.541] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 62.9606 for pixel 44/6 mean/min/max = 46.6277/30.1426/63.1129
[11:14:03.541] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 62.6065 for pixel 6/1 mean/min/max = 46.4753/30.209/62.7416
[11:14:03.541] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 62.0158 for pixel 48/9 mean/min/max = 46.7076/31.3937/62.0215
[11:14:03.542] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 63.3941 for pixel 44/13 mean/min/max = 48.4141/33.4304/63.3978
[11:14:03.542] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 58.4204 for pixel 17/4 mean/min/max = 45.4877/32.3157/58.6598
[11:14:03.543] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 61.9917 for pixel 5/4 mean/min/max = 46.8409/31.3767/62.3051
[11:14:03.543] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:14:03.633] <TB2> INFO: Expecting 411648 events.
[11:14:13.058] <TB2> INFO: 411648 events read in total (8833ms).
[11:14:13.066] <TB2> INFO: Expecting 411648 events.
[11:14:22.501] <TB2> INFO: 411648 events read in total (9032ms).
[11:14:22.514] <TB2> INFO: Expecting 411648 events.
[11:14:31.998] <TB2> INFO: 411648 events read in total (9081ms).
[11:14:32.014] <TB2> INFO: Expecting 411648 events.
[11:14:41.431] <TB2> INFO: 411648 events read in total (9014ms).
[11:14:41.447] <TB2> INFO: Expecting 411648 events.
[11:14:50.978] <TB2> INFO: 411648 events read in total (9128ms).
[11:14:50.999] <TB2> INFO: Expecting 411648 events.
[11:15:00.629] <TB2> INFO: 411648 events read in total (9227ms).
[11:15:00.650] <TB2> INFO: Expecting 411648 events.
[11:15:10.169] <TB2> INFO: 411648 events read in total (9116ms).
[11:15:10.201] <TB2> INFO: Expecting 411648 events.
[11:15:19.666] <TB2> INFO: 411648 events read in total (9062ms).
[11:15:19.694] <TB2> INFO: Expecting 411648 events.
[11:15:29.158] <TB2> INFO: 411648 events read in total (9061ms).
[11:15:29.189] <TB2> INFO: Expecting 411648 events.
[11:15:38.657] <TB2> INFO: 411648 events read in total (9065ms).
[11:15:38.689] <TB2> INFO: Expecting 411648 events.
[11:15:48.269] <TB2> INFO: 411648 events read in total (9176ms).
[11:15:48.307] <TB2> INFO: Expecting 411648 events.
[11:15:57.811] <TB2> INFO: 411648 events read in total (9101ms).
[11:15:57.852] <TB2> INFO: Expecting 411648 events.
[11:16:07.368] <TB2> INFO: 411648 events read in total (9113ms).
[11:16:07.423] <TB2> INFO: Expecting 411648 events.
[11:16:16.970] <TB2> INFO: 411648 events read in total (9144ms).
[11:16:17.015] <TB2> INFO: Expecting 411648 events.
[11:16:26.621] <TB2> INFO: 411648 events read in total (9203ms).
[11:16:26.773] <TB2> INFO: Expecting 411648 events.
[11:16:36.025] <TB2> INFO: 411648 events read in total (8849ms).
[11:16:36.082] <TB2> INFO: Test took 152539ms.
[11:16:36.797] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[11:16:36.810] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:16:36.810] <TB2> INFO: run 1 of 1
[11:16:37.051] <TB2> INFO: Expecting 5025280 events.
[11:17:03.797] <TB2> INFO: 596288 events read in total (26155ms).
[11:17:29.771] <TB2> INFO: 1190216 events read in total (52129ms).
[11:17:55.908] <TB2> INFO: 1784096 events read in total (78266ms).
[11:18:22.069] <TB2> INFO: 2377088 events read in total (104427ms).
[11:18:47.994] <TB2> INFO: 2970560 events read in total (130353ms).
[11:19:14.626] <TB2> INFO: 3568280 events read in total (156984ms).
[11:19:41.089] <TB2> INFO: 4165160 events read in total (183447ms).
[11:20:07.775] <TB2> INFO: 4759032 events read in total (210133ms).
[11:20:19.806] <TB2> INFO: 5025280 events read in total (222164ms).
[11:20:19.974] <TB2> INFO: Test took 223164ms.
[11:20:42.101] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 3.214059 .. 147.744931
[11:20:42.383] <TB2> INFO: Expecting 208000 events.
[11:20:51.729] <TB2> INFO: 208000 events read in total (8754ms).
[11:20:51.731] <TB2> INFO: Test took 9627ms.
[11:20:51.799] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 3 .. 157 (-1/-1) hits flags = 528 (plus default)
[11:20:51.814] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:20:51.814] <TB2> INFO: run 1 of 1
[11:20:52.092] <TB2> INFO: Expecting 5158400 events.
[11:21:18.296] <TB2> INFO: 582024 events read in total (25612ms).
[11:21:44.170] <TB2> INFO: 1163976 events read in total (51487ms).
[11:22:10.075] <TB2> INFO: 1745744 events read in total (77392ms).
[11:22:35.998] <TB2> INFO: 2327712 events read in total (103314ms).
[11:23:01.582] <TB2> INFO: 2909424 events read in total (128898ms).
[11:23:27.478] <TB2> INFO: 3491136 events read in total (154794ms).
[11:23:53.190] <TB2> INFO: 4072000 events read in total (180506ms).
[11:24:19.018] <TB2> INFO: 4652176 events read in total (206334ms).
[11:24:41.364] <TB2> INFO: 5158400 events read in total (228680ms).
[11:24:41.468] <TB2> INFO: Test took 229655ms.
[11:25:07.946] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.383707 .. 47.428368
[11:25:08.185] <TB2> INFO: Expecting 208000 events.
[11:25:17.775] <TB2> INFO: 208000 events read in total (8999ms).
[11:25:17.776] <TB2> INFO: Test took 9829ms.
[11:25:17.824] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 57 (-1/-1) hits flags = 528 (plus default)
[11:25:17.838] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:25:17.838] <TB2> INFO: run 1 of 1
[11:25:18.116] <TB2> INFO: Expecting 1364480 events.
[11:25:46.445] <TB2> INFO: 652456 events read in total (27737ms).
[11:26:14.798] <TB2> INFO: 1302104 events read in total (56090ms).
[11:26:17.843] <TB2> INFO: 1364480 events read in total (59135ms).
[11:26:17.883] <TB2> INFO: Test took 60046ms.
[11:26:33.606] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 25.250337 .. 48.137161
[11:26:33.884] <TB2> INFO: Expecting 208000 events.
[11:26:43.937] <TB2> INFO: 208000 events read in total (9461ms).
[11:26:43.938] <TB2> INFO: Test took 10331ms.
[11:26:43.987] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 58 (-1/-1) hits flags = 528 (plus default)
[11:26:43.001] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:26:43.001] <TB2> INFO: run 1 of 1
[11:26:44.279] <TB2> INFO: Expecting 1464320 events.
[11:27:12.406] <TB2> INFO: 656776 events read in total (27536ms).
[11:27:39.492] <TB2> INFO: 1312160 events read in total (54622ms).
[11:27:46.456] <TB2> INFO: 1464320 events read in total (61586ms).
[11:27:46.490] <TB2> INFO: Test took 62489ms.
[11:28:01.115] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 26.029052 .. 46.650453
[11:28:01.353] <TB2> INFO: Expecting 208000 events.
[11:28:11.375] <TB2> INFO: 208000 events read in total (9430ms).
[11:28:11.376] <TB2> INFO: Test took 10259ms.
[11:28:11.457] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 56 (-1/-1) hits flags = 528 (plus default)
[11:28:11.471] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:28:11.471] <TB2> INFO: run 1 of 1
[11:28:11.749] <TB2> INFO: Expecting 1364480 events.
[11:28:40.004] <TB2> INFO: 658960 events read in total (27663ms).
[11:29:07.632] <TB2> INFO: 1317656 events read in total (55291ms).
[11:29:09.002] <TB2> INFO: 1364480 events read in total (57661ms).
[11:29:10.030] <TB2> INFO: Test took 58559ms.
[11:29:24.399] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[11:29:24.399] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[11:29:24.413] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:29:24.413] <TB2> INFO: run 1 of 1
[11:29:24.729] <TB2> INFO: Expecting 1364480 events.
[11:29:52.714] <TB2> INFO: 667456 events read in total (27393ms).
[11:30:21.234] <TB2> INFO: 1334320 events read in total (55913ms).
[11:30:22.928] <TB2> INFO: 1364480 events read in total (57608ms).
[11:30:22.956] <TB2> INFO: Test took 58542ms.
[11:30:36.780] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C0.dat
[11:30:36.780] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C1.dat
[11:30:36.780] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C2.dat
[11:30:36.780] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C3.dat
[11:30:36.781] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C4.dat
[11:30:36.781] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C5.dat
[11:30:36.781] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C6.dat
[11:30:36.781] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C7.dat
[11:30:36.781] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C8.dat
[11:30:36.781] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C9.dat
[11:30:36.781] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C10.dat
[11:30:36.781] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C11.dat
[11:30:36.781] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C12.dat
[11:30:36.782] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C13.dat
[11:30:36.782] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C14.dat
[11:30:36.782] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C15.dat
[11:30:36.782] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters35_C0.dat
[11:30:36.788] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters35_C1.dat
[11:30:36.794] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters35_C2.dat
[11:30:36.800] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters35_C3.dat
[11:30:36.806] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters35_C4.dat
[11:30:36.812] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters35_C5.dat
[11:30:36.817] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters35_C6.dat
[11:30:36.823] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters35_C7.dat
[11:30:36.829] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters35_C8.dat
[11:30:36.835] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters35_C9.dat
[11:30:36.841] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters35_C10.dat
[11:30:36.847] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters35_C11.dat
[11:30:36.853] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters35_C12.dat
[11:30:36.859] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters35_C13.dat
[11:30:36.865] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters35_C14.dat
[11:30:36.871] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//trimParameters35_C15.dat
[11:30:36.877] <TB2> INFO: PixTestTrim::trimTest() done
[11:30:36.877] <TB2> INFO: vtrim: 127 132 145 134 126 129 141 137 142 152 154 123 132 135 129 117
[11:30:36.877] <TB2> INFO: vthrcomp: 116 112 108 112 119 106 116 115 123 124 118 128 117 109 116 115
[11:30:36.877] <TB2> INFO: vcal mean: 34.93 34.92 35.21 34.98 34.93 34.98 35.04 34.96 35.17 35.25 35.05 34.98 35.04 35.04 34.93 34.98
[11:30:36.877] <TB2> INFO: vcal RMS: 1.08 1.02 1.34 0.99 1.25 1.07 1.32 1.11 1.48 1.58 1.35 1.28 1.19 1.03 1.02 1.23
[11:30:36.877] <TB2> INFO: bits mean: 9.71 9.50 9.50 9.34 9.96 8.93 9.78 9.38 10.27 10.28 10.34 9.78 9.72 9.01 9.81 9.59
[11:30:36.877] <TB2> INFO: bits RMS: 2.68 2.59 2.38 2.77 2.63 2.60 2.64 2.72 2.50 2.45 2.46 2.75 2.67 2.60 2.53 2.67
[11:30:36.886] <TB2> INFO: ----------------------------------------------------------------------
[11:30:36.886] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[11:30:36.886] <TB2> INFO: ----------------------------------------------------------------------
[11:30:36.888] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[11:30:36.902] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:30:36.902] <TB2> INFO: run 1 of 1
[11:30:37.140] <TB2> INFO: Expecting 4160000 events.
[11:31:09.933] <TB2> INFO: 756620 events read in total (32201ms).
[11:31:42.178] <TB2> INFO: 1508030 events read in total (64446ms).
[11:32:14.247] <TB2> INFO: 2254570 events read in total (96515ms).
[11:32:46.016] <TB2> INFO: 2997510 events read in total (128284ms).
[11:33:17.434] <TB2> INFO: 3736775 events read in total (159702ms).
[11:33:35.771] <TB2> INFO: 4160000 events read in total (178039ms).
[11:33:35.846] <TB2> INFO: Test took 178944ms.
[11:34:01.214] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 202 (-1/-1) hits flags = 528 (plus default)
[11:34:01.227] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:34:01.227] <TB2> INFO: run 1 of 1
[11:34:01.483] <TB2> INFO: Expecting 4222400 events.
[11:34:33.457] <TB2> INFO: 727305 events read in total (31382ms).
[11:35:04.521] <TB2> INFO: 1450745 events read in total (62446ms).
[11:35:35.713] <TB2> INFO: 2170035 events read in total (93638ms).
[11:36:07.026] <TB2> INFO: 2885965 events read in total (124951ms).
[11:36:37.874] <TB2> INFO: 3598965 events read in total (155799ms).
[11:37:04.990] <TB2> INFO: 4222400 events read in total (182915ms).
[11:37:05.099] <TB2> INFO: Test took 183872ms.
[11:37:34.116] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 185 (-1/-1) hits flags = 528 (plus default)
[11:37:34.130] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:37:34.130] <TB2> INFO: run 1 of 1
[11:37:34.395] <TB2> INFO: Expecting 3868800 events.
[11:38:07.105] <TB2> INFO: 752920 events read in total (32118ms).
[11:38:38.922] <TB2> INFO: 1500925 events read in total (63935ms).
[11:39:10.666] <TB2> INFO: 2242680 events read in total (95679ms).
[11:39:42.287] <TB2> INFO: 2981460 events read in total (127300ms).
[11:40:14.220] <TB2> INFO: 3717030 events read in total (159233ms).
[11:40:21.467] <TB2> INFO: 3868800 events read in total (166480ms).
[11:40:21.667] <TB2> INFO: Test took 167536ms.
[11:40:51.654] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 185 (-1/-1) hits flags = 528 (plus default)
[11:40:51.667] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:40:51.667] <TB2> INFO: run 1 of 1
[11:40:51.910] <TB2> INFO: Expecting 3868800 events.
[11:41:24.501] <TB2> INFO: 753110 events read in total (32000ms).
[11:41:56.640] <TB2> INFO: 1501350 events read in total (64139ms).
[11:42:28.405] <TB2> INFO: 2243400 events read in total (95904ms).
[11:43:00.559] <TB2> INFO: 2982685 events read in total (128058ms).
[11:43:32.145] <TB2> INFO: 3718745 events read in total (159644ms).
[11:43:38.973] <TB2> INFO: 3868800 events read in total (166472ms).
[11:43:39.058] <TB2> INFO: Test took 167391ms.
[11:44:05.772] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 185 (-1/-1) hits flags = 528 (plus default)
[11:44:05.784] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:44:05.784] <TB2> INFO: run 1 of 1
[11:44:06.020] <TB2> INFO: Expecting 3868800 events.
[11:44:39.011] <TB2> INFO: 753385 events read in total (32399ms).
[11:45:11.060] <TB2> INFO: 1501840 events read in total (64448ms).
[11:45:42.954] <TB2> INFO: 2244215 events read in total (96342ms).
[11:46:14.537] <TB2> INFO: 2983620 events read in total (127925ms).
[11:46:46.380] <TB2> INFO: 3719795 events read in total (159768ms).
[11:46:53.079] <TB2> INFO: 3868800 events read in total (166467ms).
[11:46:53.142] <TB2> INFO: Test took 167358ms.
[11:47:17.553] <TB2> INFO: PixTestTrim::trimBitTest() done
[11:47:17.555] <TB2> INFO: PixTestTrim::doTest() done, duration: 2446 seconds
[11:47:17.555] <TB2> INFO: Decoding statistics:
[11:47:17.555] <TB2> INFO: General information:
[11:47:17.555] <TB2> INFO: 16bit words read: 0
[11:47:17.555] <TB2> INFO: valid events total: 0
[11:47:17.555] <TB2> INFO: empty events: 0
[11:47:17.555] <TB2> INFO: valid events with pixels: 0
[11:47:17.555] <TB2> INFO: valid pixel hits: 0
[11:47:17.555] <TB2> INFO: Event errors: 0
[11:47:17.555] <TB2> INFO: start marker: 0
[11:47:17.555] <TB2> INFO: stop marker: 0
[11:47:17.555] <TB2> INFO: overflow: 0
[11:47:17.555] <TB2> INFO: invalid 5bit words: 0
[11:47:17.555] <TB2> INFO: invalid XOR eye diagram: 0
[11:47:17.555] <TB2> INFO: frame (failed synchr.): 0
[11:47:17.555] <TB2> INFO: idle data (no TBM trl): 0
[11:47:17.555] <TB2> INFO: no data (only TBM hdr): 0
[11:47:17.555] <TB2> INFO: TBM errors: 0
[11:47:17.555] <TB2> INFO: flawed TBM headers: 0
[11:47:17.555] <TB2> INFO: flawed TBM trailers: 0
[11:47:17.555] <TB2> INFO: event ID mismatches: 0
[11:47:17.555] <TB2> INFO: ROC errors: 0
[11:47:17.555] <TB2> INFO: missing ROC header(s): 0
[11:47:17.555] <TB2> INFO: misplaced readback start: 0
[11:47:17.555] <TB2> INFO: Pixel decoding errors: 0
[11:47:17.555] <TB2> INFO: pixel data incomplete: 0
[11:47:17.555] <TB2> INFO: pixel address: 0
[11:47:17.555] <TB2> INFO: pulse height fill bit: 0
[11:47:17.555] <TB2> INFO: buffer corruption: 0
[11:47:18.154] <TB2> INFO: ######################################################################
[11:47:18.154] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[11:47:18.154] <TB2> INFO: ######################################################################
[11:47:18.391] <TB2> INFO: Expecting 41600 events.
[11:47:21.830] <TB2> INFO: 41600 events read in total (2847ms).
[11:47:21.831] <TB2> INFO: Test took 3676ms.
[11:47:22.275] <TB2> INFO: Expecting 41600 events.
[11:47:25.758] <TB2> INFO: 41600 events read in total (2892ms).
[11:47:25.759] <TB2> INFO: Test took 3724ms.
[11:47:26.050] <TB2> INFO: Expecting 41600 events.
[11:47:29.668] <TB2> INFO: 41600 events read in total (3027ms).
[11:47:29.669] <TB2> INFO: Test took 3884ms.
[11:47:29.960] <TB2> INFO: Expecting 41600 events.
[11:47:33.547] <TB2> INFO: 41600 events read in total (2995ms).
[11:47:33.547] <TB2> INFO: Test took 3852ms.
[11:47:33.836] <TB2> INFO: Expecting 41600 events.
[11:47:37.399] <TB2> INFO: 41600 events read in total (2971ms).
[11:47:37.400] <TB2> INFO: Test took 3828ms.
[11:47:37.689] <TB2> INFO: Expecting 41600 events.
[11:47:41.166] <TB2> INFO: 41600 events read in total (2885ms).
[11:47:41.167] <TB2> INFO: Test took 3743ms.
[11:47:41.456] <TB2> INFO: Expecting 41600 events.
[11:47:45.020] <TB2> INFO: 41600 events read in total (2972ms).
[11:47:45.021] <TB2> INFO: Test took 3830ms.
[11:47:45.310] <TB2> INFO: Expecting 41600 events.
[11:47:48.872] <TB2> INFO: 41600 events read in total (2971ms).
[11:47:48.873] <TB2> INFO: Test took 3828ms.
[11:47:49.161] <TB2> INFO: Expecting 41600 events.
[11:47:52.694] <TB2> INFO: 41600 events read in total (2941ms).
[11:47:52.695] <TB2> INFO: Test took 3798ms.
[11:47:52.984] <TB2> INFO: Expecting 41600 events.
[11:47:56.460] <TB2> INFO: 41600 events read in total (2885ms).
[11:47:56.461] <TB2> INFO: Test took 3742ms.
[11:47:56.751] <TB2> INFO: Expecting 41600 events.
[11:48:00.278] <TB2> INFO: 41600 events read in total (2935ms).
[11:48:00.279] <TB2> INFO: Test took 3794ms.
[11:48:00.569] <TB2> INFO: Expecting 41600 events.
[11:48:04.139] <TB2> INFO: 41600 events read in total (2978ms).
[11:48:04.140] <TB2> INFO: Test took 3837ms.
[11:48:04.429] <TB2> INFO: Expecting 41600 events.
[11:48:07.975] <TB2> INFO: 41600 events read in total (2954ms).
[11:48:07.976] <TB2> INFO: Test took 3812ms.
[11:48:08.268] <TB2> INFO: Expecting 41600 events.
[11:48:11.890] <TB2> INFO: 41600 events read in total (3030ms).
[11:48:11.891] <TB2> INFO: Test took 3889ms.
[11:48:12.180] <TB2> INFO: Expecting 41600 events.
[11:48:15.655] <TB2> INFO: 41600 events read in total (2883ms).
[11:48:15.656] <TB2> INFO: Test took 3741ms.
[11:48:15.965] <TB2> INFO: Expecting 41600 events.
[11:48:19.533] <TB2> INFO: 41600 events read in total (2977ms).
[11:48:19.534] <TB2> INFO: Test took 3854ms.
[11:48:19.826] <TB2> INFO: Expecting 41600 events.
[11:48:23.476] <TB2> INFO: 41600 events read in total (3058ms).
[11:48:23.477] <TB2> INFO: Test took 3916ms.
[11:48:23.767] <TB2> INFO: Expecting 41600 events.
[11:48:27.297] <TB2> INFO: 41600 events read in total (2938ms).
[11:48:27.298] <TB2> INFO: Test took 3797ms.
[11:48:27.590] <TB2> INFO: Expecting 41600 events.
[11:48:31.078] <TB2> INFO: 41600 events read in total (2896ms).
[11:48:31.078] <TB2> INFO: Test took 3753ms.
[11:48:31.368] <TB2> INFO: Expecting 41600 events.
[11:48:34.879] <TB2> INFO: 41600 events read in total (2919ms).
[11:48:34.880] <TB2> INFO: Test took 3777ms.
[11:48:35.181] <TB2> INFO: Expecting 41600 events.
[11:48:38.727] <TB2> INFO: 41600 events read in total (2954ms).
[11:48:38.728] <TB2> INFO: Test took 3824ms.
[11:48:39.018] <TB2> INFO: Expecting 41600 events.
[11:48:42.641] <TB2> INFO: 41600 events read in total (3031ms).
[11:48:42.642] <TB2> INFO: Test took 3890ms.
[11:48:42.931] <TB2> INFO: Expecting 41600 events.
[11:48:46.496] <TB2> INFO: 41600 events read in total (2973ms).
[11:48:46.497] <TB2> INFO: Test took 3831ms.
[11:48:46.787] <TB2> INFO: Expecting 41600 events.
[11:48:50.382] <TB2> INFO: 41600 events read in total (3004ms).
[11:48:50.383] <TB2> INFO: Test took 3862ms.
[11:48:50.693] <TB2> INFO: Expecting 41600 events.
[11:48:54.197] <TB2> INFO: 41600 events read in total (2912ms).
[11:48:54.198] <TB2> INFO: Test took 3787ms.
[11:48:54.487] <TB2> INFO: Expecting 41600 events.
[11:48:58.104] <TB2> INFO: 41600 events read in total (3025ms).
[11:48:58.105] <TB2> INFO: Test took 3883ms.
[11:48:58.394] <TB2> INFO: Expecting 41600 events.
[11:49:01.889] <TB2> INFO: 41600 events read in total (2903ms).
[11:49:01.890] <TB2> INFO: Test took 3761ms.
[11:49:02.179] <TB2> INFO: Expecting 41600 events.
[11:49:05.745] <TB2> INFO: 41600 events read in total (2975ms).
[11:49:05.746] <TB2> INFO: Test took 3833ms.
[11:49:06.037] <TB2> INFO: Expecting 41600 events.
[11:49:09.544] <TB2> INFO: 41600 events read in total (2915ms).
[11:49:09.545] <TB2> INFO: Test took 3773ms.
[11:49:09.836] <TB2> INFO: Expecting 2560 events.
[11:49:10.731] <TB2> INFO: 2560 events read in total (303ms).
[11:49:10.731] <TB2> INFO: Test took 1173ms.
[11:49:11.038] <TB2> INFO: Expecting 2560 events.
[11:49:11.927] <TB2> INFO: 2560 events read in total (298ms).
[11:49:11.928] <TB2> INFO: Test took 1196ms.
[11:49:12.237] <TB2> INFO: Expecting 2560 events.
[11:49:13.131] <TB2> INFO: 2560 events read in total (302ms).
[11:49:13.131] <TB2> INFO: Test took 1203ms.
[11:49:13.439] <TB2> INFO: Expecting 2560 events.
[11:49:14.334] <TB2> INFO: 2560 events read in total (304ms).
[11:49:14.334] <TB2> INFO: Test took 1202ms.
[11:49:14.641] <TB2> INFO: Expecting 2560 events.
[11:49:15.523] <TB2> INFO: 2560 events read in total (290ms).
[11:49:15.523] <TB2> INFO: Test took 1188ms.
[11:49:15.831] <TB2> INFO: Expecting 2560 events.
[11:49:16.715] <TB2> INFO: 2560 events read in total (293ms).
[11:49:16.716] <TB2> INFO: Test took 1192ms.
[11:49:17.023] <TB2> INFO: Expecting 2560 events.
[11:49:17.914] <TB2> INFO: 2560 events read in total (298ms).
[11:49:17.914] <TB2> INFO: Test took 1198ms.
[11:49:18.223] <TB2> INFO: Expecting 2560 events.
[11:49:19.109] <TB2> INFO: 2560 events read in total (294ms).
[11:49:19.110] <TB2> INFO: Test took 1195ms.
[11:49:19.419] <TB2> INFO: Expecting 2560 events.
[11:49:20.300] <TB2> INFO: 2560 events read in total (289ms).
[11:49:20.300] <TB2> INFO: Test took 1190ms.
[11:49:20.608] <TB2> INFO: Expecting 2560 events.
[11:49:21.498] <TB2> INFO: 2560 events read in total (298ms).
[11:49:21.498] <TB2> INFO: Test took 1197ms.
[11:49:21.805] <TB2> INFO: Expecting 2560 events.
[11:49:22.693] <TB2> INFO: 2560 events read in total (296ms).
[11:49:22.693] <TB2> INFO: Test took 1194ms.
[11:49:22.001] <TB2> INFO: Expecting 2560 events.
[11:49:23.893] <TB2> INFO: 2560 events read in total (300ms).
[11:49:23.893] <TB2> INFO: Test took 1200ms.
[11:49:24.201] <TB2> INFO: Expecting 2560 events.
[11:49:25.095] <TB2> INFO: 2560 events read in total (302ms).
[11:49:25.096] <TB2> INFO: Test took 1202ms.
[11:49:25.402] <TB2> INFO: Expecting 2560 events.
[11:49:26.294] <TB2> INFO: 2560 events read in total (300ms).
[11:49:26.294] <TB2> INFO: Test took 1198ms.
[11:49:26.603] <TB2> INFO: Expecting 2560 events.
[11:49:27.486] <TB2> INFO: 2560 events read in total (292ms).
[11:49:27.486] <TB2> INFO: Test took 1192ms.
[11:49:27.794] <TB2> INFO: Expecting 2560 events.
[11:49:28.679] <TB2> INFO: 2560 events read in total (293ms).
[11:49:28.679] <TB2> INFO: Test took 1193ms.
[11:49:28.684] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:49:28.990] <TB2> INFO: Expecting 655360 events.
[11:49:43.711] <TB2> INFO: 655360 events read in total (14130ms).
[11:49:43.723] <TB2> INFO: Expecting 655360 events.
[11:49:58.420] <TB2> INFO: 655360 events read in total (14295ms).
[11:49:58.436] <TB2> INFO: Expecting 655360 events.
[11:50:13.052] <TB2> INFO: 655360 events read in total (14213ms).
[11:50:13.072] <TB2> INFO: Expecting 655360 events.
[11:50:27.729] <TB2> INFO: 655360 events read in total (14253ms).
[11:50:27.757] <TB2> INFO: Expecting 655360 events.
[11:50:42.324] <TB2> INFO: 655360 events read in total (14164ms).
[11:50:42.353] <TB2> INFO: Expecting 655360 events.
[11:50:56.906] <TB2> INFO: 655360 events read in total (14150ms).
[11:50:56.940] <TB2> INFO: Expecting 655360 events.
[11:51:11.584] <TB2> INFO: 655360 events read in total (14241ms).
[11:51:11.624] <TB2> INFO: Expecting 655360 events.
[11:51:26.198] <TB2> INFO: 655360 events read in total (14171ms).
[11:51:26.240] <TB2> INFO: Expecting 655360 events.
[11:51:40.894] <TB2> INFO: 655360 events read in total (14251ms).
[11:51:40.940] <TB2> INFO: Expecting 655360 events.
[11:51:55.538] <TB2> INFO: 655360 events read in total (14195ms).
[11:51:55.657] <TB2> INFO: Expecting 655360 events.
[11:52:10.204] <TB2> INFO: 655360 events read in total (14144ms).
[11:52:10.261] <TB2> INFO: Expecting 655360 events.
[11:52:24.822] <TB2> INFO: 655360 events read in total (14158ms).
[11:52:24.896] <TB2> INFO: Expecting 655360 events.
[11:52:39.431] <TB2> INFO: 655360 events read in total (14132ms).
[11:52:39.510] <TB2> INFO: Expecting 655360 events.
[11:52:54.177] <TB2> INFO: 655360 events read in total (14264ms).
[11:52:54.262] <TB2> INFO: Expecting 655360 events.
[11:53:08.828] <TB2> INFO: 655360 events read in total (14163ms).
[11:53:08.977] <TB2> INFO: Expecting 655360 events.
[11:53:23.631] <TB2> INFO: 655360 events read in total (14251ms).
[11:53:23.812] <TB2> INFO: Test took 235128ms.
[11:53:23.926] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:53:24.184] <TB2> INFO: Expecting 655360 events.
[11:53:38.964] <TB2> INFO: 655360 events read in total (14188ms).
[11:53:38.976] <TB2> INFO: Expecting 655360 events.
[11:53:53.547] <TB2> INFO: 655360 events read in total (14168ms).
[11:53:53.569] <TB2> INFO: Expecting 655360 events.
[11:54:08.138] <TB2> INFO: 655360 events read in total (14165ms).
[11:54:08.165] <TB2> INFO: Expecting 655360 events.
[11:54:22.615] <TB2> INFO: 655360 events read in total (14047ms).
[11:54:22.641] <TB2> INFO: Expecting 655360 events.
[11:54:37.039] <TB2> INFO: 655360 events read in total (13995ms).
[11:54:37.079] <TB2> INFO: Expecting 655360 events.
[11:54:51.560] <TB2> INFO: 655360 events read in total (14078ms).
[11:54:51.605] <TB2> INFO: Expecting 655360 events.
[11:55:05.962] <TB2> INFO: 655360 events read in total (13954ms).
[11:55:06.008] <TB2> INFO: Expecting 655360 events.
[11:55:20.550] <TB2> INFO: 655360 events read in total (14139ms).
[11:55:20.592] <TB2> INFO: Expecting 655360 events.
[11:55:34.986] <TB2> INFO: 655360 events read in total (13991ms).
[11:55:35.032] <TB2> INFO: Expecting 655360 events.
[11:55:49.355] <TB2> INFO: 655360 events read in total (13920ms).
[11:55:49.486] <TB2> INFO: Expecting 655360 events.
[11:56:03.867] <TB2> INFO: 655360 events read in total (13978ms).
[11:56:03.937] <TB2> INFO: Expecting 655360 events.
[11:56:18.404] <TB2> INFO: 655360 events read in total (14064ms).
[11:56:18.478] <TB2> INFO: Expecting 655360 events.
[11:56:32.840] <TB2> INFO: 655360 events read in total (13959ms).
[11:56:32.933] <TB2> INFO: Expecting 655360 events.
[11:56:47.167] <TB2> INFO: 655360 events read in total (13831ms).
[11:56:47.271] <TB2> INFO: Expecting 655360 events.
[11:57:01.993] <TB2> INFO: 655360 events read in total (14319ms).
[11:57:02.144] <TB2> INFO: Expecting 655360 events.
[11:57:16.839] <TB2> INFO: 655360 events read in total (14292ms).
[11:57:16.975] <TB2> INFO: Test took 233049ms.
[11:57:17.151] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:57:17.158] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:57:17.164] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:57:17.173] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[11:57:17.181] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[11:57:17.190] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[11:57:17.198] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:57:17.205] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:57:17.213] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:57:17.218] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:57:17.224] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:57:17.230] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:57:17.235] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:57:17.242] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:57:17.248] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:57:17.253] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:57:17.260] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[11:57:17.266] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[11:57:17.271] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[11:57:17.278] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[11:57:17.283] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:57:17.290] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:57:17.295] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:57:17.301] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:57:17.307] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:57:17.313] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:57:17.318] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:57:17.324] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:57:17.330] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:57:17.335] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:57:17.373] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C0.dat
[11:57:17.374] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C1.dat
[11:57:17.374] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C2.dat
[11:57:17.374] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C3.dat
[11:57:17.374] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C4.dat
[11:57:17.374] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C5.dat
[11:57:17.374] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C6.dat
[11:57:17.375] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C7.dat
[11:57:17.375] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C8.dat
[11:57:17.375] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C9.dat
[11:57:17.375] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C10.dat
[11:57:17.375] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C11.dat
[11:57:17.375] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C12.dat
[11:57:17.376] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C13.dat
[11:57:17.376] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C14.dat
[11:57:17.376] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//dacParameters35_C15.dat
[11:57:17.619] <TB2> INFO: Expecting 41600 events.
[11:57:20.796] <TB2> INFO: 41600 events read in total (2585ms).
[11:57:20.797] <TB2> INFO: Test took 3418ms.
[11:57:21.251] <TB2> INFO: Expecting 41600 events.
[11:57:24.281] <TB2> INFO: 41600 events read in total (2438ms).
[11:57:24.282] <TB2> INFO: Test took 3272ms.
[11:57:24.739] <TB2> INFO: Expecting 41600 events.
[11:57:27.939] <TB2> INFO: 41600 events read in total (2608ms).
[11:57:27.940] <TB2> INFO: Test took 3444ms.
[11:57:28.158] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:28.248] <TB2> INFO: Expecting 2560 events.
[11:57:29.140] <TB2> INFO: 2560 events read in total (300ms).
[11:57:29.141] <TB2> INFO: Test took 983ms.
[11:57:29.144] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:29.449] <TB2> INFO: Expecting 2560 events.
[11:57:30.342] <TB2> INFO: 2560 events read in total (301ms).
[11:57:30.342] <TB2> INFO: Test took 1199ms.
[11:57:30.345] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:30.650] <TB2> INFO: Expecting 2560 events.
[11:57:31.541] <TB2> INFO: 2560 events read in total (299ms).
[11:57:31.542] <TB2> INFO: Test took 1197ms.
[11:57:31.543] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:31.851] <TB2> INFO: Expecting 2560 events.
[11:57:32.737] <TB2> INFO: 2560 events read in total (295ms).
[11:57:32.737] <TB2> INFO: Test took 1194ms.
[11:57:32.741] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:33.045] <TB2> INFO: Expecting 2560 events.
[11:57:33.936] <TB2> INFO: 2560 events read in total (299ms).
[11:57:33.937] <TB2> INFO: Test took 1196ms.
[11:57:33.940] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:34.244] <TB2> INFO: Expecting 2560 events.
[11:57:35.133] <TB2> INFO: 2560 events read in total (297ms).
[11:57:35.134] <TB2> INFO: Test took 1194ms.
[11:57:35.138] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:35.442] <TB2> INFO: Expecting 2560 events.
[11:57:36.334] <TB2> INFO: 2560 events read in total (300ms).
[11:57:36.335] <TB2> INFO: Test took 1197ms.
[11:57:36.338] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:36.643] <TB2> INFO: Expecting 2560 events.
[11:57:37.541] <TB2> INFO: 2560 events read in total (306ms).
[11:57:37.542] <TB2> INFO: Test took 1204ms.
[11:57:37.546] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:37.849] <TB2> INFO: Expecting 2560 events.
[11:57:38.741] <TB2> INFO: 2560 events read in total (300ms).
[11:57:38.741] <TB2> INFO: Test took 1195ms.
[11:57:38.744] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:39.049] <TB2> INFO: Expecting 2560 events.
[11:57:39.942] <TB2> INFO: 2560 events read in total (301ms).
[11:57:39.943] <TB2> INFO: Test took 1199ms.
[11:57:39.946] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:40.250] <TB2> INFO: Expecting 2560 events.
[11:57:41.140] <TB2> INFO: 2560 events read in total (298ms).
[11:57:41.140] <TB2> INFO: Test took 1194ms.
[11:57:41.142] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:41.450] <TB2> INFO: Expecting 2560 events.
[11:57:42.340] <TB2> INFO: 2560 events read in total (298ms).
[11:57:42.340] <TB2> INFO: Test took 1198ms.
[11:57:42.344] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:42.648] <TB2> INFO: Expecting 2560 events.
[11:57:43.537] <TB2> INFO: 2560 events read in total (297ms).
[11:57:43.537] <TB2> INFO: Test took 1193ms.
[11:57:43.540] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:43.845] <TB2> INFO: Expecting 2560 events.
[11:57:44.731] <TB2> INFO: 2560 events read in total (294ms).
[11:57:44.731] <TB2> INFO: Test took 1191ms.
[11:57:44.733] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:45.040] <TB2> INFO: Expecting 2560 events.
[11:57:45.928] <TB2> INFO: 2560 events read in total (296ms).
[11:57:45.929] <TB2> INFO: Test took 1196ms.
[11:57:45.932] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:46.236] <TB2> INFO: Expecting 2560 events.
[11:57:47.120] <TB2> INFO: 2560 events read in total (292ms).
[11:57:47.120] <TB2> INFO: Test took 1188ms.
[11:57:47.122] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:47.428] <TB2> INFO: Expecting 2560 events.
[11:57:48.319] <TB2> INFO: 2560 events read in total (299ms).
[11:57:48.320] <TB2> INFO: Test took 1198ms.
[11:57:48.323] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:48.629] <TB2> INFO: Expecting 2560 events.
[11:57:49.510] <TB2> INFO: 2560 events read in total (290ms).
[11:57:49.510] <TB2> INFO: Test took 1187ms.
[11:57:49.513] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:49.818] <TB2> INFO: Expecting 2560 events.
[11:57:50.704] <TB2> INFO: 2560 events read in total (294ms).
[11:57:50.705] <TB2> INFO: Test took 1192ms.
[11:57:50.708] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:51.013] <TB2> INFO: Expecting 2560 events.
[11:57:51.903] <TB2> INFO: 2560 events read in total (298ms).
[11:57:51.904] <TB2> INFO: Test took 1196ms.
[11:57:51.907] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:52.211] <TB2> INFO: Expecting 2560 events.
[11:57:53.096] <TB2> INFO: 2560 events read in total (293ms).
[11:57:53.096] <TB2> INFO: Test took 1189ms.
[11:57:53.099] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:53.405] <TB2> INFO: Expecting 2560 events.
[11:57:54.286] <TB2> INFO: 2560 events read in total (289ms).
[11:57:54.286] <TB2> INFO: Test took 1187ms.
[11:57:54.289] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:54.595] <TB2> INFO: Expecting 2560 events.
[11:57:55.480] <TB2> INFO: 2560 events read in total (293ms).
[11:57:55.481] <TB2> INFO: Test took 1192ms.
[11:57:55.483] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:55.789] <TB2> INFO: Expecting 2560 events.
[11:57:56.679] <TB2> INFO: 2560 events read in total (298ms).
[11:57:56.679] <TB2> INFO: Test took 1196ms.
[11:57:56.682] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:56.987] <TB2> INFO: Expecting 2560 events.
[11:57:57.880] <TB2> INFO: 2560 events read in total (301ms).
[11:57:57.881] <TB2> INFO: Test took 1199ms.
[11:57:57.884] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:58.189] <TB2> INFO: Expecting 2560 events.
[11:57:59.081] <TB2> INFO: 2560 events read in total (300ms).
[11:57:59.082] <TB2> INFO: Test took 1198ms.
[11:57:59.084] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:57:59.388] <TB2> INFO: Expecting 2560 events.
[11:58:00.281] <TB2> INFO: 2560 events read in total (301ms).
[11:58:00.282] <TB2> INFO: Test took 1198ms.
[11:58:00.285] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:58:00.590] <TB2> INFO: Expecting 2560 events.
[11:58:01.480] <TB2> INFO: 2560 events read in total (299ms).
[11:58:01.481] <TB2> INFO: Test took 1196ms.
[11:58:01.485] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:58:01.788] <TB2> INFO: Expecting 2560 events.
[11:58:02.674] <TB2> INFO: 2560 events read in total (294ms).
[11:58:02.674] <TB2> INFO: Test took 1190ms.
[11:58:02.678] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:58:02.982] <TB2> INFO: Expecting 2560 events.
[11:58:03.881] <TB2> INFO: 2560 events read in total (308ms).
[11:58:03.882] <TB2> INFO: Test took 1204ms.
[11:58:03.885] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:58:04.191] <TB2> INFO: Expecting 2560 events.
[11:58:05.081] <TB2> INFO: 2560 events read in total (298ms).
[11:58:05.081] <TB2> INFO: Test took 1197ms.
[11:58:05.083] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:58:05.390] <TB2> INFO: Expecting 2560 events.
[11:58:06.273] <TB2> INFO: 2560 events read in total (292ms).
[11:58:06.274] <TB2> INFO: Test took 1191ms.
[11:58:06.745] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 648 seconds
[11:58:06.745] <TB2> INFO: PH scale (per ROC): 48 42 63 61 40 50 48 46 48 45 48 44 53 67 35 59
[11:58:06.745] <TB2> INFO: PH offset (per ROC): 111 108 119 129 112 100 111 100 132 109 111 109 114 134 97 123
[11:58:06.754] <TB2> INFO: Decoding statistics:
[11:58:06.754] <TB2> INFO: General information:
[11:58:06.754] <TB2> INFO: 16bit words read: 127884
[11:58:06.754] <TB2> INFO: valid events total: 20480
[11:58:06.754] <TB2> INFO: empty events: 17978
[11:58:06.754] <TB2> INFO: valid events with pixels: 2502
[11:58:06.754] <TB2> INFO: valid pixel hits: 2502
[11:58:06.754] <TB2> INFO: Event errors: 0
[11:58:06.754] <TB2> INFO: start marker: 0
[11:58:06.754] <TB2> INFO: stop marker: 0
[11:58:06.754] <TB2> INFO: overflow: 0
[11:58:06.754] <TB2> INFO: invalid 5bit words: 0
[11:58:06.754] <TB2> INFO: invalid XOR eye diagram: 0
[11:58:06.754] <TB2> INFO: frame (failed synchr.): 0
[11:58:06.754] <TB2> INFO: idle data (no TBM trl): 0
[11:58:06.754] <TB2> INFO: no data (only TBM hdr): 0
[11:58:06.754] <TB2> INFO: TBM errors: 0
[11:58:06.754] <TB2> INFO: flawed TBM headers: 0
[11:58:06.754] <TB2> INFO: flawed TBM trailers: 0
[11:58:06.754] <TB2> INFO: event ID mismatches: 0
[11:58:06.754] <TB2> INFO: ROC errors: 0
[11:58:06.754] <TB2> INFO: missing ROC header(s): 0
[11:58:06.754] <TB2> INFO: misplaced readback start: 0
[11:58:06.754] <TB2> INFO: Pixel decoding errors: 0
[11:58:06.754] <TB2> INFO: pixel data incomplete: 0
[11:58:06.754] <TB2> INFO: pixel address: 0
[11:58:06.754] <TB2> INFO: pulse height fill bit: 0
[11:58:06.754] <TB2> INFO: buffer corruption: 0
[11:58:06.915] <TB2> INFO: ######################################################################
[11:58:06.915] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[11:58:06.915] <TB2> INFO: ######################################################################
[11:58:06.930] <TB2> INFO: scanning low vcal = 10
[11:58:07.167] <TB2> INFO: Expecting 41600 events.
[11:58:10.774] <TB2> INFO: 41600 events read in total (3015ms).
[11:58:10.775] <TB2> INFO: Test took 3845ms.
[11:58:10.776] <TB2> INFO: scanning low vcal = 20
[11:58:11.070] <TB2> INFO: Expecting 41600 events.
[11:58:14.655] <TB2> INFO: 41600 events read in total (2993ms).
[11:58:14.655] <TB2> INFO: Test took 3879ms.
[11:58:14.657] <TB2> INFO: scanning low vcal = 30
[11:58:14.953] <TB2> INFO: Expecting 41600 events.
[11:58:18.597] <TB2> INFO: 41600 events read in total (3052ms).
[11:58:18.598] <TB2> INFO: Test took 3941ms.
[11:58:18.600] <TB2> INFO: scanning low vcal = 40
[11:58:18.879] <TB2> INFO: Expecting 41600 events.
[11:58:22.885] <TB2> INFO: 41600 events read in total (3414ms).
[11:58:22.887] <TB2> INFO: Test took 4287ms.
[11:58:22.890] <TB2> INFO: scanning low vcal = 50
[11:58:23.168] <TB2> INFO: Expecting 41600 events.
[11:58:27.180] <TB2> INFO: 41600 events read in total (3421ms).
[11:58:27.181] <TB2> INFO: Test took 4291ms.
[11:58:27.184] <TB2> INFO: scanning low vcal = 60
[11:58:27.461] <TB2> INFO: Expecting 41600 events.
[11:58:31.483] <TB2> INFO: 41600 events read in total (3430ms).
[11:58:31.483] <TB2> INFO: Test took 4299ms.
[11:58:31.486] <TB2> INFO: scanning low vcal = 70
[11:58:31.763] <TB2> INFO: Expecting 41600 events.
[11:58:35.773] <TB2> INFO: 41600 events read in total (3418ms).
[11:58:35.774] <TB2> INFO: Test took 4288ms.
[11:58:35.777] <TB2> INFO: scanning low vcal = 80
[11:58:36.053] <TB2> INFO: Expecting 41600 events.
[11:58:40.051] <TB2> INFO: 41600 events read in total (3406ms).
[11:58:40.052] <TB2> INFO: Test took 4275ms.
[11:58:40.055] <TB2> INFO: scanning low vcal = 90
[11:58:40.332] <TB2> INFO: Expecting 41600 events.
[11:58:44.334] <TB2> INFO: 41600 events read in total (3411ms).
[11:58:44.335] <TB2> INFO: Test took 4280ms.
[11:58:44.339] <TB2> INFO: scanning low vcal = 100
[11:58:44.615] <TB2> INFO: Expecting 41600 events.
[11:58:48.660] <TB2> INFO: 41600 events read in total (3453ms).
[11:58:48.661] <TB2> INFO: Test took 4322ms.
[11:58:48.665] <TB2> INFO: scanning low vcal = 110
[11:58:48.942] <TB2> INFO: Expecting 41600 events.
[11:58:52.960] <TB2> INFO: 41600 events read in total (3427ms).
[11:58:52.961] <TB2> INFO: Test took 4296ms.
[11:58:52.964] <TB2> INFO: scanning low vcal = 120
[11:58:53.241] <TB2> INFO: Expecting 41600 events.
[11:58:57.217] <TB2> INFO: 41600 events read in total (3385ms).
[11:58:57.217] <TB2> INFO: Test took 4253ms.
[11:58:57.220] <TB2> INFO: scanning low vcal = 130
[11:58:57.501] <TB2> INFO: Expecting 41600 events.
[11:59:01.467] <TB2> INFO: 41600 events read in total (3374ms).
[11:59:01.468] <TB2> INFO: Test took 4248ms.
[11:59:01.471] <TB2> INFO: scanning low vcal = 140
[11:59:01.753] <TB2> INFO: Expecting 41600 events.
[11:59:05.717] <TB2> INFO: 41600 events read in total (3372ms).
[11:59:05.718] <TB2> INFO: Test took 4247ms.
[11:59:05.721] <TB2> INFO: scanning low vcal = 150
[11:59:05.998] <TB2> INFO: Expecting 41600 events.
[11:59:10.009] <TB2> INFO: 41600 events read in total (3419ms).
[11:59:10.009] <TB2> INFO: Test took 4288ms.
[11:59:10.012] <TB2> INFO: scanning low vcal = 160
[11:59:10.289] <TB2> INFO: Expecting 41600 events.
[11:59:14.261] <TB2> INFO: 41600 events read in total (3380ms).
[11:59:14.261] <TB2> INFO: Test took 4248ms.
[11:59:14.264] <TB2> INFO: scanning low vcal = 170
[11:59:14.541] <TB2> INFO: Expecting 41600 events.
[11:59:18.521] <TB2> INFO: 41600 events read in total (3388ms).
[11:59:18.522] <TB2> INFO: Test took 4258ms.
[11:59:18.527] <TB2> INFO: scanning low vcal = 180
[11:59:18.801] <TB2> INFO: Expecting 41600 events.
[11:59:22.801] <TB2> INFO: 41600 events read in total (3408ms).
[11:59:22.802] <TB2> INFO: Test took 4275ms.
[11:59:22.805] <TB2> INFO: scanning low vcal = 190
[11:59:23.082] <TB2> INFO: Expecting 41600 events.
[11:59:27.060] <TB2> INFO: 41600 events read in total (3386ms).
[11:59:27.061] <TB2> INFO: Test took 4256ms.
[11:59:27.064] <TB2> INFO: scanning low vcal = 200
[11:59:27.340] <TB2> INFO: Expecting 41600 events.
[11:59:31.324] <TB2> INFO: 41600 events read in total (3392ms).
[11:59:31.325] <TB2> INFO: Test took 4261ms.
[11:59:31.328] <TB2> INFO: scanning low vcal = 210
[11:59:31.604] <TB2> INFO: Expecting 41600 events.
[11:59:35.599] <TB2> INFO: 41600 events read in total (3403ms).
[11:59:35.600] <TB2> INFO: Test took 4272ms.
[11:59:35.603] <TB2> INFO: scanning low vcal = 220
[11:59:35.879] <TB2> INFO: Expecting 41600 events.
[11:59:39.867] <TB2> INFO: 41600 events read in total (3396ms).
[11:59:39.868] <TB2> INFO: Test took 4265ms.
[11:59:39.871] <TB2> INFO: scanning low vcal = 230
[11:59:40.148] <TB2> INFO: Expecting 41600 events.
[11:59:44.145] <TB2> INFO: 41600 events read in total (3404ms).
[11:59:44.146] <TB2> INFO: Test took 4274ms.
[11:59:44.149] <TB2> INFO: scanning low vcal = 240
[11:59:44.427] <TB2> INFO: Expecting 41600 events.
[11:59:48.429] <TB2> INFO: 41600 events read in total (3410ms).
[11:59:48.429] <TB2> INFO: Test took 4280ms.
[11:59:48.432] <TB2> INFO: scanning low vcal = 250
[11:59:48.709] <TB2> INFO: Expecting 41600 events.
[11:59:52.671] <TB2> INFO: 41600 events read in total (3371ms).
[11:59:52.673] <TB2> INFO: Test took 4241ms.
[11:59:52.679] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[11:59:52.954] <TB2> INFO: Expecting 41600 events.
[11:59:56.936] <TB2> INFO: 41600 events read in total (3391ms).
[11:59:56.937] <TB2> INFO: Test took 4258ms.
[11:59:56.940] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[11:59:57.217] <TB2> INFO: Expecting 41600 events.
[12:00:01.165] <TB2> INFO: 41600 events read in total (3356ms).
[12:00:01.165] <TB2> INFO: Test took 4225ms.
[12:00:01.168] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[12:00:01.445] <TB2> INFO: Expecting 41600 events.
[12:00:05.373] <TB2> INFO: 41600 events read in total (3337ms).
[12:00:05.373] <TB2> INFO: Test took 4204ms.
[12:00:05.376] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[12:00:05.653] <TB2> INFO: Expecting 41600 events.
[12:00:09.590] <TB2> INFO: 41600 events read in total (3345ms).
[12:00:09.591] <TB2> INFO: Test took 4214ms.
[12:00:09.593] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[12:00:09.870] <TB2> INFO: Expecting 41600 events.
[12:00:13.871] <TB2> INFO: 41600 events read in total (3409ms).
[12:00:13.872] <TB2> INFO: Test took 4278ms.
[12:00:14.437] <TB2> INFO: PixTestGainPedestal::measure() done
[12:00:51.567] <TB2> INFO: PixTestGainPedestal::fit() done
[12:00:51.567] <TB2> INFO: non-linearity mean: 0.963 0.917 0.986 0.982 0.932 0.972 0.953 0.926 0.981 0.952 0.955 0.946 0.954 0.986 0.916 0.982
[12:00:51.567] <TB2> INFO: non-linearity RMS: 0.038 0.121 0.003 0.003 0.139 0.017 0.062 0.119 0.004 0.048 0.043 0.145 0.041 0.003 0.145 0.003
[12:00:51.567] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[12:00:51.582] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[12:00:51.595] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[12:00:51.608] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[12:00:51.621] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[12:00:51.634] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[12:00:51.647] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[12:00:51.660] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[12:00:51.674] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[12:00:51.687] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[12:00:51.699] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[12:00:51.712] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[12:00:51.726] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[12:00:51.739] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[12:00:51.752] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[12:00:51.765] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1030_FullQualification_2016-10-20_09h44m_1476949484//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[12:00:51.778] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 164 seconds
[12:00:51.778] <TB2> INFO: Decoding statistics:
[12:00:51.778] <TB2> INFO: General information:
[12:00:51.778] <TB2> INFO: 16bit words read: 3327536
[12:00:51.778] <TB2> INFO: valid events total: 332800
[12:00:51.778] <TB2> INFO: empty events: 0
[12:00:51.778] <TB2> INFO: valid events with pixels: 332800
[12:00:51.778] <TB2> INFO: valid pixel hits: 665368
[12:00:51.778] <TB2> INFO: Event errors: 0
[12:00:51.778] <TB2> INFO: start marker: 0
[12:00:51.778] <TB2> INFO: stop marker: 0
[12:00:51.778] <TB2> INFO: overflow: 0
[12:00:51.778] <TB2> INFO: invalid 5bit words: 0
[12:00:51.778] <TB2> INFO: invalid XOR eye diagram: 0
[12:00:51.778] <TB2> INFO: frame (failed synchr.): 0
[12:00:51.778] <TB2> INFO: idle data (no TBM trl): 0
[12:00:51.778] <TB2> INFO: no data (only TBM hdr): 0
[12:00:51.778] <TB2> INFO: TBM errors: 0
[12:00:51.778] <TB2> INFO: flawed TBM headers: 0
[12:00:51.778] <TB2> INFO: flawed TBM trailers: 0
[12:00:51.778] <TB2> INFO: event ID mismatches: 0
[12:00:51.778] <TB2> INFO: ROC errors: 0
[12:00:51.778] <TB2> INFO: missing ROC header(s): 0
[12:00:51.778] <TB2> INFO: misplaced readback start: 0
[12:00:51.778] <TB2> INFO: Pixel decoding errors: 0
[12:00:51.778] <TB2> INFO: pixel data incomplete: 0
[12:00:51.778] <TB2> INFO: pixel address: 0
[12:00:51.778] <TB2> INFO: pulse height fill bit: 0
[12:00:51.778] <TB2> INFO: buffer corruption: 0
[12:00:51.794] <TB2> INFO: Decoding statistics:
[12:00:51.794] <TB2> INFO: General information:
[12:00:51.794] <TB2> INFO: 16bit words read: 3456956
[12:00:51.794] <TB2> INFO: valid events total: 353536
[12:00:51.794] <TB2> INFO: empty events: 18234
[12:00:51.794] <TB2> INFO: valid events with pixels: 335302
[12:00:51.794] <TB2> INFO: valid pixel hits: 667870
[12:00:51.795] <TB2> INFO: Event errors: 0
[12:00:51.795] <TB2> INFO: start marker: 0
[12:00:51.795] <TB2> INFO: stop marker: 0
[12:00:51.795] <TB2> INFO: overflow: 0
[12:00:51.795] <TB2> INFO: invalid 5bit words: 0
[12:00:51.795] <TB2> INFO: invalid XOR eye diagram: 0
[12:00:51.795] <TB2> INFO: frame (failed synchr.): 0
[12:00:51.795] <TB2> INFO: idle data (no TBM trl): 0
[12:00:51.795] <TB2> INFO: no data (only TBM hdr): 0
[12:00:51.795] <TB2> INFO: TBM errors: 0
[12:00:51.795] <TB2> INFO: flawed TBM headers: 0
[12:00:51.795] <TB2> INFO: flawed TBM trailers: 0
[12:00:51.795] <TB2> INFO: event ID mismatches: 0
[12:00:51.795] <TB2> INFO: ROC errors: 0
[12:00:51.795] <TB2> INFO: missing ROC header(s): 0
[12:00:51.795] <TB2> INFO: misplaced readback start: 0
[12:00:51.795] <TB2> INFO: Pixel decoding errors: 0
[12:00:51.795] <TB2> INFO: pixel data incomplete: 0
[12:00:51.795] <TB2> INFO: pixel address: 0
[12:00:51.795] <TB2> INFO: pulse height fill bit: 0
[12:00:51.795] <TB2> INFO: buffer corruption: 0
[12:00:51.795] <TB2> INFO: enter test to run
[12:00:51.795] <TB2> INFO: test: exit no parameter change
[12:00:51.921] <TB2> QUIET: Connection to board 149 closed.
[12:00:51.922] <TB2> INFO: pXar: this is the end, my friend