[16:39:32.246] <TB2> INFO: *** Welcome to pxar ***
[16:39:32.246] <TB2> INFO: *** Today: 2016/10/19
[16:39:32.253] <TB2> INFO: *** Version: c8ba-dirty
[16:39:32.253] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C15.dat
[16:39:32.253] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//tbmParameters_C1b.dat
[16:39:32.254] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//defaultMaskFile.dat
[16:39:32.254] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters_C15.dat
[16:39:32.317] <TB2> INFO: clk: 4
[16:39:32.318] <TB2> INFO: ctr: 4
[16:39:32.318] <TB2> INFO: sda: 19
[16:39:32.318] <TB2> INFO: tin: 9
[16:39:32.318] <TB2> INFO: level: 15
[16:39:32.318] <TB2> INFO: triggerdelay: 0
[16:39:32.318] <TB2> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[16:39:32.318] <TB2> INFO: Log level: INFO
[16:39:32.327] <TB2> INFO: Found DTB DTB_WWXUD2
[16:39:32.334] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[16:39:32.336] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[16:39:32.339] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[16:39:33.829] <TB2> INFO: DUT info:
[16:39:33.829] <TB2> INFO: The DUT currently contains the following objects:
[16:39:33.829] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[16:39:33.829] <TB2> INFO: TBM Core alpha (0): 7 registers set
[16:39:33.829] <TB2> INFO: TBM Core beta (1): 7 registers set
[16:39:33.829] <TB2> INFO: TBM Core alpha (2): 7 registers set
[16:39:33.829] <TB2> INFO: TBM Core beta (3): 7 registers set
[16:39:33.829] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[16:39:33.829] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[16:39:33.829] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[16:39:33.829] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[16:39:33.829] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[16:39:33.829] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[16:39:33.829] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[16:39:33.829] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[16:39:33.829] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[16:39:33.829] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[16:39:33.829] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[16:39:33.829] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[16:39:33.829] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[16:39:33.829] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[16:39:33.829] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[16:39:33.829] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[16:39:33.829] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[16:39:34.230] <TB2> INFO: enter 'restricted' command line mode
[16:39:34.230] <TB2> INFO: enter test to run
[16:39:34.230] <TB2> INFO: test: pretest no parameter change
[16:39:34.230] <TB2> INFO: running: pretest
[16:39:34.237] <TB2> INFO: ######################################################################
[16:39:34.237] <TB2> INFO: PixTestPretest::doTest()
[16:39:34.237] <TB2> INFO: ######################################################################
[16:39:34.238] <TB2> INFO: ----------------------------------------------------------------------
[16:39:34.238] <TB2> INFO: PixTestPretest::programROC()
[16:39:34.238] <TB2> INFO: ----------------------------------------------------------------------
[16:39:52.253] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[16:39:52.253] <TB2> INFO: IA differences per ROC: 21.7 16.1 16.9 16.9 16.1 20.1 17.7 19.3 20.1 17.7 16.9 17.7 16.9 17.7 19.3 19.3
[16:39:52.316] <TB2> INFO: ----------------------------------------------------------------------
[16:39:52.316] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[16:39:52.316] <TB2> INFO: ----------------------------------------------------------------------
[16:39:58.618] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 386.7 mA = 24.1687 mA/ROC
[16:39:58.618] <TB2> INFO: i(loss) [mA/ROC]: 20.1 20.1 20.1 20.1 20.1 20.1 20.1 20.1 19.3 19.3 20.1 19.3 19.3 20.1 20.1 19.3
[16:39:58.654] <TB2> INFO: ----------------------------------------------------------------------
[16:39:58.654] <TB2> INFO: PixTestPretest::findTiming()
[16:39:58.654] <TB2> INFO: ----------------------------------------------------------------------
[16:39:58.654] <TB2> INFO: PixTestCmd::init()

[16:40:31.217] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[16:40:31.218] <TB2> INFO: (success/tries = 100/100), width = 4
[16:40:32.701] <TB2> INFO: ----------------------------------------------------------------------
[16:40:32.701] <TB2> INFO: PixTestPretest::findWorkingPixel()
[16:40:32.701] <TB2> INFO: ----------------------------------------------------------------------
[16:40:32.796] <TB2> INFO: Expecting 231680 events.
[16:40:42.709] <TB2> INFO: 231680 events read in total (9321ms).
[16:40:42.716] <TB2> INFO: Test took 10010ms.
[16:40:42.967] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[16:40:43.003] <TB2> INFO: ----------------------------------------------------------------------
[16:40:43.003] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[16:40:43.003] <TB2> INFO: ----------------------------------------------------------------------
[16:40:43.098] <TB2> INFO: Expecting 231680 events.
[16:40:53.051] <TB2> INFO: 231680 events read in total (9361ms).
[16:40:53.061] <TB2> INFO: Test took 10053ms.
[16:40:53.329] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[16:40:53.329] <TB2> INFO: CalDel: 99 97 80 80 90 80 82 85 84 93 91 95 82 93 92 79
[16:40:53.329] <TB2> INFO: VthrComp: 51 53 51 51 51 51 51 51 51 51 51 51 51 51 51 53
[16:40:53.332] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C0.dat
[16:40:53.333] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C1.dat
[16:40:53.333] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C2.dat
[16:40:53.333] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C3.dat
[16:40:53.333] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C4.dat
[16:40:53.333] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C5.dat
[16:40:53.333] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C6.dat
[16:40:53.333] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C7.dat
[16:40:53.334] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C8.dat
[16:40:53.334] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C9.dat
[16:40:53.334] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C10.dat
[16:40:53.334] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C11.dat
[16:40:53.334] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C12.dat
[16:40:53.334] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C13.dat
[16:40:53.335] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C14.dat
[16:40:53.335] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters_C15.dat
[16:40:53.335] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//tbmParameters_C0a.dat
[16:40:53.335] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//tbmParameters_C0b.dat
[16:40:53.335] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//tbmParameters_C1a.dat
[16:40:53.335] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//tbmParameters_C1b.dat
[16:40:53.335] <TB2> INFO: PixTestPretest::doTest() done, duration: 79 seconds
[16:40:53.388] <TB2> INFO: enter test to run
[16:40:53.388] <TB2> INFO: test: FullTest no parameter change
[16:40:53.388] <TB2> INFO: running: fulltest
[16:40:53.388] <TB2> INFO: ######################################################################
[16:40:53.388] <TB2> INFO: PixTestFullTest::doTest()
[16:40:53.388] <TB2> INFO: ######################################################################
[16:40:53.389] <TB2> INFO: ######################################################################
[16:40:53.389] <TB2> INFO: PixTestAlive::doTest()
[16:40:53.389] <TB2> INFO: ######################################################################
[16:40:53.391] <TB2> INFO: ----------------------------------------------------------------------
[16:40:53.391] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:40:53.391] <TB2> INFO: ----------------------------------------------------------------------
[16:40:53.628] <TB2> INFO: Expecting 41600 events.
[16:40:57.130] <TB2> INFO: 41600 events read in total (2910ms).
[16:40:57.131] <TB2> INFO: Test took 3739ms.
[16:40:57.363] <TB2> INFO: PixTestAlive::aliveTest() done
[16:40:57.363] <TB2> INFO: number of dead pixels (per ROC): 0 0 4 0 0 2 0 0 1 0 0 0 0 0 0 0
[16:40:57.365] <TB2> INFO: ----------------------------------------------------------------------
[16:40:57.365] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:40:57.365] <TB2> INFO: ----------------------------------------------------------------------
[16:40:57.613] <TB2> INFO: Expecting 41600 events.
[16:41:00.667] <TB2> INFO: 41600 events read in total (2462ms).
[16:41:00.667] <TB2> INFO: Test took 3301ms.
[16:41:00.668] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[16:41:00.909] <TB2> INFO: PixTestAlive::maskTest() done
[16:41:00.909] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[16:41:00.910] <TB2> INFO: ----------------------------------------------------------------------
[16:41:00.910] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:41:00.910] <TB2> INFO: ----------------------------------------------------------------------
[16:41:01.155] <TB2> INFO: Expecting 41600 events.
[16:41:04.806] <TB2> INFO: 41600 events read in total (3059ms).
[16:41:04.806] <TB2> INFO: Test took 3895ms.
[16:41:05.039] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[16:41:05.039] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[16:41:05.040] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[16:41:05.040] <TB2> INFO: Decoding statistics:
[16:41:05.040] <TB2> INFO: General information:
[16:41:05.040] <TB2> INFO: 16bit words read: 0
[16:41:05.040] <TB2> INFO: valid events total: 0
[16:41:05.040] <TB2> INFO: empty events: 0
[16:41:05.040] <TB2> INFO: valid events with pixels: 0
[16:41:05.040] <TB2> INFO: valid pixel hits: 0
[16:41:05.040] <TB2> INFO: Event errors: 0
[16:41:05.040] <TB2> INFO: start marker: 0
[16:41:05.040] <TB2> INFO: stop marker: 0
[16:41:05.040] <TB2> INFO: overflow: 0
[16:41:05.040] <TB2> INFO: invalid 5bit words: 0
[16:41:05.040] <TB2> INFO: invalid XOR eye diagram: 0
[16:41:05.040] <TB2> INFO: frame (failed synchr.): 0
[16:41:05.040] <TB2> INFO: idle data (no TBM trl): 0
[16:41:05.040] <TB2> INFO: no data (only TBM hdr): 0
[16:41:05.040] <TB2> INFO: TBM errors: 0
[16:41:05.040] <TB2> INFO: flawed TBM headers: 0
[16:41:05.040] <TB2> INFO: flawed TBM trailers: 0
[16:41:05.040] <TB2> INFO: event ID mismatches: 0
[16:41:05.040] <TB2> INFO: ROC errors: 0
[16:41:05.040] <TB2> INFO: missing ROC header(s): 0
[16:41:05.040] <TB2> INFO: misplaced readback start: 0
[16:41:05.040] <TB2> INFO: Pixel decoding errors: 0
[16:41:05.040] <TB2> INFO: pixel data incomplete: 0
[16:41:05.040] <TB2> INFO: pixel address: 0
[16:41:05.040] <TB2> INFO: pulse height fill bit: 0
[16:41:05.040] <TB2> INFO: buffer corruption: 0
[16:41:05.044] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C15.dat
[16:41:05.044] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr_C15.dat

[16:41:05.044] <TB2> INFO: ######################################################################
[16:41:05.044] <TB2> INFO: PixTestReadback::doTest()
[16:41:05.044] <TB2> INFO: ######################################################################
[16:41:05.044] <TB2> INFO: ----------------------------------------------------------------------
[16:41:05.044] <TB2> INFO: PixTestReadback::CalibrateVd()
[16:41:05.044] <TB2> INFO: ----------------------------------------------------------------------
[16:41:15.017] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C0.dat
[16:41:15.018] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C1.dat
[16:41:15.018] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C2.dat
[16:41:15.018] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C3.dat
[16:41:15.018] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C4.dat
[16:41:15.018] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C5.dat
[16:41:15.018] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C6.dat
[16:41:15.019] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C7.dat
[16:41:15.019] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C8.dat
[16:41:15.019] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C9.dat
[16:41:15.019] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C10.dat
[16:41:15.019] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C11.dat
[16:41:15.019] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C12.dat
[16:41:15.019] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C13.dat
[16:41:15.019] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C14.dat
[16:41:15.019] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C15.dat
[16:41:15.049] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:41:15.049] <TB2> INFO: ----------------------------------------------------------------------
[16:41:15.049] <TB2> INFO: PixTestReadback::CalibrateVa()
[16:41:15.049] <TB2> INFO: ----------------------------------------------------------------------
[16:41:24.981] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C0.dat
[16:41:24.981] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C1.dat
[16:41:24.981] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C2.dat
[16:41:24.982] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C3.dat
[16:41:24.982] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C4.dat
[16:41:24.982] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C5.dat
[16:41:24.982] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C6.dat
[16:41:24.982] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C7.dat
[16:41:24.982] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C8.dat
[16:41:24.982] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C9.dat
[16:41:24.982] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C10.dat
[16:41:24.982] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C11.dat
[16:41:24.982] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C12.dat
[16:41:24.982] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C13.dat
[16:41:24.982] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C14.dat
[16:41:24.982] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C15.dat
[16:41:25.015] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:41:25.015] <TB2> INFO: ----------------------------------------------------------------------
[16:41:25.015] <TB2> INFO: PixTestReadback::readbackVbg()
[16:41:25.015] <TB2> INFO: ----------------------------------------------------------------------
[16:41:32.691] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:41:32.691] <TB2> INFO: ----------------------------------------------------------------------
[16:41:32.691] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[16:41:32.691] <TB2> INFO: ----------------------------------------------------------------------
[16:41:32.691] <TB2> INFO: Vbg will be calibrated using Vd calibration
[16:41:32.691] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 141.5calibrated Vbg = 1.20032 :::*/*/*/*/
[16:41:32.691] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 168.4calibrated Vbg = 1.19776 :::*/*/*/*/
[16:41:32.691] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 158.3calibrated Vbg = 1.19145 :::*/*/*/*/
[16:41:32.691] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 156.9calibrated Vbg = 1.18947 :::*/*/*/*/
[16:41:32.691] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 166.4calibrated Vbg = 1.19506 :::*/*/*/*/
[16:41:32.691] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 151calibrated Vbg = 1.2027 :::*/*/*/*/
[16:41:32.691] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 144.1calibrated Vbg = 1.19955 :::*/*/*/*/
[16:41:32.691] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 153.3calibrated Vbg = 1.20186 :::*/*/*/*/
[16:41:32.691] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 160.6calibrated Vbg = 1.19597 :::*/*/*/*/
[16:41:32.691] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 160.3calibrated Vbg = 1.18873 :::*/*/*/*/
[16:41:32.692] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 161.9calibrated Vbg = 1.19183 :::*/*/*/*/
[16:41:32.692] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 161.7calibrated Vbg = 1.18261 :::*/*/*/*/
[16:41:32.692] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 154.7calibrated Vbg = 1.19036 :::*/*/*/*/
[16:41:32.692] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 160calibrated Vbg = 1.196 :::*/*/*/*/
[16:41:32.692] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 163calibrated Vbg = 1.19857 :::*/*/*/*/
[16:41:32.692] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 161.9calibrated Vbg = 1.19703 :::*/*/*/*/
[16:41:32.695] <TB2> INFO: ----------------------------------------------------------------------
[16:41:32.695] <TB2> INFO: PixTestReadback::CalibrateIa()
[16:41:32.695] <TB2> INFO: ----------------------------------------------------------------------
[16:44:13.535] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C0.dat
[16:44:13.535] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C1.dat
[16:44:13.535] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C2.dat
[16:44:13.535] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C3.dat
[16:44:13.535] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C4.dat
[16:44:13.535] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C5.dat
[16:44:13.536] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C6.dat
[16:44:13.536] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C7.dat
[16:44:13.536] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C8.dat
[16:44:13.536] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C9.dat
[16:44:13.536] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C10.dat
[16:44:13.536] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C11.dat
[16:44:13.536] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C12.dat
[16:44:13.536] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C13.dat
[16:44:13.536] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C14.dat
[16:44:13.536] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//readbackCal_C15.dat
[16:44:13.565] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:44:13.566] <TB2> INFO: PixTestReadback::doTest() done
[16:44:13.566] <TB2> INFO: Decoding statistics:
[16:44:13.566] <TB2> INFO: General information:
[16:44:13.566] <TB2> INFO: 16bit words read: 1536
[16:44:13.566] <TB2> INFO: valid events total: 256
[16:44:13.566] <TB2> INFO: empty events: 256
[16:44:13.566] <TB2> INFO: valid events with pixels: 0
[16:44:13.566] <TB2> INFO: valid pixel hits: 0
[16:44:13.566] <TB2> INFO: Event errors: 0
[16:44:13.566] <TB2> INFO: start marker: 0
[16:44:13.566] <TB2> INFO: stop marker: 0
[16:44:13.566] <TB2> INFO: overflow: 0
[16:44:13.566] <TB2> INFO: invalid 5bit words: 0
[16:44:13.566] <TB2> INFO: invalid XOR eye diagram: 0
[16:44:13.566] <TB2> INFO: frame (failed synchr.): 0
[16:44:13.566] <TB2> INFO: idle data (no TBM trl): 0
[16:44:13.566] <TB2> INFO: no data (only TBM hdr): 0
[16:44:13.566] <TB2> INFO: TBM errors: 0
[16:44:13.566] <TB2> INFO: flawed TBM headers: 0
[16:44:13.566] <TB2> INFO: flawed TBM trailers: 0
[16:44:13.566] <TB2> INFO: event ID mismatches: 0
[16:44:13.566] <TB2> INFO: ROC errors: 0
[16:44:13.566] <TB2> INFO: missing ROC header(s): 0
[16:44:13.566] <TB2> INFO: misplaced readback start: 0
[16:44:13.566] <TB2> INFO: Pixel decoding errors: 0
[16:44:13.566] <TB2> INFO: pixel data incomplete: 0
[16:44:13.566] <TB2> INFO: pixel address: 0
[16:44:13.566] <TB2> INFO: pulse height fill bit: 0
[16:44:13.566] <TB2> INFO: buffer corruption: 0
[16:44:13.613] <TB2> INFO: ######################################################################
[16:44:13.613] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[16:44:13.613] <TB2> INFO: ######################################################################
[16:44:13.616] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[16:44:13.631] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:44:13.631] <TB2> INFO: run 1 of 1
[16:44:13.911] <TB2> INFO: Expecting 3120000 events.
[16:44:45.366] <TB2> INFO: 677820 events read in total (30864ms).
[16:45:15.774] <TB2> INFO: 1348695 events read in total (61272ms).











[16:45:46.133] <TB2> INFO: 2013865 events read in total (91631ms).











[16:46:16.263] <TB2> INFO: 2676670 events read in total (121761ms).











[16:46:36.538] <TB2> INFO: 3120000 events read in total (142036ms).
[16:46:36.600] <TB2> INFO: Test took 142971ms.
[16:47:01.784] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 168 seconds
[16:47:01.784] <TB2> INFO: number of dead bumps (per ROC): 0 0 1 0 1 2 0 0 0 0 0 5 1 0 0 3
[16:47:01.784] <TB2> INFO: separation cut (per ROC): 108 110 117 115 114 124 106 114 110 114 113 118 110 115 115 124
[16:47:01.784] <TB2> INFO: Decoding statistics:
[16:47:01.784] <TB2> INFO: General information:
[16:47:01.784] <TB2> INFO: 16bit words read: 0
[16:47:01.784] <TB2> INFO: valid events total: 0
[16:47:01.784] <TB2> INFO: empty events: 0
[16:47:01.784] <TB2> INFO: valid events with pixels: 0
[16:47:01.784] <TB2> INFO: valid pixel hits: 0
[16:47:01.784] <TB2> INFO: Event errors: 0
[16:47:01.784] <TB2> INFO: start marker: 0
[16:47:01.784] <TB2> INFO: stop marker: 0
[16:47:01.784] <TB2> INFO: overflow: 0
[16:47:01.784] <TB2> INFO: invalid 5bit words: 0
[16:47:01.784] <TB2> INFO: invalid XOR eye diagram: 0
[16:47:01.784] <TB2> INFO: frame (failed synchr.): 0
[16:47:01.784] <TB2> INFO: idle data (no TBM trl): 0
[16:47:01.784] <TB2> INFO: no data (only TBM hdr): 0
[16:47:01.784] <TB2> INFO: TBM errors: 0
[16:47:01.784] <TB2> INFO: flawed TBM headers: 0
[16:47:01.784] <TB2> INFO: flawed TBM trailers: 0
[16:47:01.784] <TB2> INFO: event ID mismatches: 0
[16:47:01.784] <TB2> INFO: ROC errors: 0
[16:47:01.784] <TB2> INFO: missing ROC header(s): 0
[16:47:01.784] <TB2> INFO: misplaced readback start: 0
[16:47:01.784] <TB2> INFO: Pixel decoding errors: 0
[16:47:01.784] <TB2> INFO: pixel data incomplete: 0
[16:47:01.784] <TB2> INFO: pixel address: 0
[16:47:01.784] <TB2> INFO: pulse height fill bit: 0
[16:47:01.784] <TB2> INFO: buffer corruption: 0
[16:47:01.821] <TB2> INFO: ######################################################################
[16:47:01.821] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:47:01.821] <TB2> INFO: ######################################################################
[16:47:01.821] <TB2> INFO: ----------------------------------------------------------------------
[16:47:01.821] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:47:01.821] <TB2> INFO: ----------------------------------------------------------------------
[16:47:01.821] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[16:47:01.835] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[16:47:01.835] <TB2> INFO: run 1 of 1
[16:47:02.080] <TB2> INFO: Expecting 36608000 events.
[16:47:25.915] <TB2> INFO: 698250 events read in total (23243ms).
[16:47:49.495] <TB2> INFO: 1381750 events read in total (46823ms).
[16:48:12.649] <TB2> INFO: 2063450 events read in total (69977ms).
[16:48:35.791] <TB2> INFO: 2744550 events read in total (93119ms).
[16:48:58.910] <TB2> INFO: 3426500 events read in total (116238ms).
[16:49:22.045] <TB2> INFO: 4108850 events read in total (139373ms).
[16:49:45.277] <TB2> INFO: 4788300 events read in total (162605ms).
[16:50:08.828] <TB2> INFO: 5468450 events read in total (186156ms).
[16:50:31.917] <TB2> INFO: 6146200 events read in total (209245ms).
[16:50:54.940] <TB2> INFO: 6825150 events read in total (232268ms).
[16:51:18.157] <TB2> INFO: 7502700 events read in total (255485ms).
[16:51:41.233] <TB2> INFO: 8181250 events read in total (278561ms).
[16:52:04.325] <TB2> INFO: 8860650 events read in total (301653ms).
[16:52:27.515] <TB2> INFO: 9539100 events read in total (324843ms).
[16:52:50.816] <TB2> INFO: 10216550 events read in total (348144ms).
[16:53:13.958] <TB2> INFO: 10892900 events read in total (371286ms).
[16:53:37.289] <TB2> INFO: 11569500 events read in total (394617ms).
[16:54:00.163] <TB2> INFO: 12245000 events read in total (417491ms).
[16:54:23.157] <TB2> INFO: 12920550 events read in total (440485ms).
[16:54:46.294] <TB2> INFO: 13595650 events read in total (463622ms).
[16:55:09.243] <TB2> INFO: 14271950 events read in total (486571ms).
[16:55:32.163] <TB2> INFO: 14946950 events read in total (509491ms).
[16:55:55.261] <TB2> INFO: 15619950 events read in total (532589ms).
[16:56:18.367] <TB2> INFO: 16293200 events read in total (555695ms).
[16:56:41.336] <TB2> INFO: 16967100 events read in total (578664ms).
[16:57:04.382] <TB2> INFO: 17640200 events read in total (601710ms).
[16:57:27.706] <TB2> INFO: 18312600 events read in total (625034ms).
[16:57:50.954] <TB2> INFO: 18982600 events read in total (648282ms).
[16:58:14.268] <TB2> INFO: 19656050 events read in total (671596ms).
[16:58:37.332] <TB2> INFO: 20324850 events read in total (694660ms).
[16:59:00.514] <TB2> INFO: 20994000 events read in total (717842ms).
[16:59:23.353] <TB2> INFO: 21663900 events read in total (740681ms).
[16:59:46.663] <TB2> INFO: 22333150 events read in total (763991ms).
[17:00:09.542] <TB2> INFO: 23001650 events read in total (786870ms).
[17:00:32.559] <TB2> INFO: 23670400 events read in total (809887ms).
[17:00:55.496] <TB2> INFO: 24337650 events read in total (832824ms).
[17:01:18.565] <TB2> INFO: 25005850 events read in total (855893ms).
[17:01:41.730] <TB2> INFO: 25674450 events read in total (879058ms).
[17:02:04.665] <TB2> INFO: 26342000 events read in total (901993ms).
[17:02:27.659] <TB2> INFO: 27007250 events read in total (924987ms).
[17:02:50.572] <TB2> INFO: 27673000 events read in total (947900ms).
[17:03:13.346] <TB2> INFO: 28339650 events read in total (970674ms).
[17:03:36.339] <TB2> INFO: 29004500 events read in total (993667ms).
[17:03:59.331] <TB2> INFO: 29669850 events read in total (1016659ms).
[17:04:21.990] <TB2> INFO: 30334450 events read in total (1039318ms).
[17:04:45.051] <TB2> INFO: 31000400 events read in total (1062379ms).
[17:05:08.076] <TB2> INFO: 31664650 events read in total (1085404ms).
[17:05:31.147] <TB2> INFO: 32331750 events read in total (1108475ms).
[17:05:54.098] <TB2> INFO: 32995850 events read in total (1131426ms).
[17:06:16.989] <TB2> INFO: 33660700 events read in total (1154317ms).
[17:06:40.143] <TB2> INFO: 34326950 events read in total (1177471ms).
[17:07:03.161] <TB2> INFO: 34994350 events read in total (1200489ms).
[17:07:26.572] <TB2> INFO: 35661550 events read in total (1223900ms).
[17:07:50.077] <TB2> INFO: 36337700 events read in total (1247405ms).
[17:07:59.605] <TB2> INFO: 36608000 events read in total (1256933ms).
[17:07:59.673] <TB2> INFO: Test took 1257838ms.
[17:08:00.079] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:08:01.489] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:08:03.681] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:08:06.038] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:08:07.829] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:08:09.372] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:08:11.128] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:08:12.967] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:08:14.837] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:08:16.821] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:08:18.795] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:08:20.767] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:08:22.702] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:08:24.537] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:08:26.654] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:08:28.602] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:08:30.632] <TB2> INFO: PixTestScurves::scurves() done
[17:08:30.632] <TB2> INFO: Vcal mean: 113.50 125.39 130.85 128.35 118.53 129.40 107.15 126.36 123.61 130.90 123.33 121.95 118.27 117.52 130.29 124.73
[17:08:30.632] <TB2> INFO: Vcal RMS: 4.58 6.56 7.77 5.99 6.32 6.47 4.96 6.33 5.80 6.77 5.63 6.24 5.96 5.66 6.29 6.46
[17:08:30.632] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1288 seconds
[17:08:30.632] <TB2> INFO: Decoding statistics:
[17:08:30.632] <TB2> INFO: General information:
[17:08:30.632] <TB2> INFO: 16bit words read: 0
[17:08:30.632] <TB2> INFO: valid events total: 0
[17:08:30.632] <TB2> INFO: empty events: 0
[17:08:30.632] <TB2> INFO: valid events with pixels: 0
[17:08:30.632] <TB2> INFO: valid pixel hits: 0
[17:08:30.632] <TB2> INFO: Event errors: 0
[17:08:30.632] <TB2> INFO: start marker: 0
[17:08:30.632] <TB2> INFO: stop marker: 0
[17:08:30.632] <TB2> INFO: overflow: 0
[17:08:30.632] <TB2> INFO: invalid 5bit words: 0
[17:08:30.632] <TB2> INFO: invalid XOR eye diagram: 0
[17:08:30.632] <TB2> INFO: frame (failed synchr.): 0
[17:08:30.632] <TB2> INFO: idle data (no TBM trl): 0
[17:08:30.632] <TB2> INFO: no data (only TBM hdr): 0
[17:08:30.632] <TB2> INFO: TBM errors: 0
[17:08:30.632] <TB2> INFO: flawed TBM headers: 0
[17:08:30.632] <TB2> INFO: flawed TBM trailers: 0
[17:08:30.632] <TB2> INFO: event ID mismatches: 0
[17:08:30.632] <TB2> INFO: ROC errors: 0
[17:08:30.632] <TB2> INFO: missing ROC header(s): 0
[17:08:30.632] <TB2> INFO: misplaced readback start: 0
[17:08:30.632] <TB2> INFO: Pixel decoding errors: 0
[17:08:30.632] <TB2> INFO: pixel data incomplete: 0
[17:08:30.632] <TB2> INFO: pixel address: 0
[17:08:30.632] <TB2> INFO: pulse height fill bit: 0
[17:08:30.633] <TB2> INFO: buffer corruption: 0
[17:08:30.712] <TB2> INFO: ######################################################################
[17:08:30.712] <TB2> INFO: PixTestTrim::doTest()
[17:08:30.712] <TB2> INFO: ######################################################################
[17:08:30.713] <TB2> INFO: ----------------------------------------------------------------------
[17:08:30.713] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[17:08:30.713] <TB2> INFO: ----------------------------------------------------------------------
[17:08:30.770] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[17:08:30.770] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:08:30.784] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:08:30.784] <TB2> INFO: run 1 of 1
[17:08:31.067] <TB2> INFO: Expecting 5025280 events.
[17:09:01.754] <TB2> INFO: 828256 events read in total (30096ms).
[17:09:31.642] <TB2> INFO: 1654304 events read in total (59984ms).
[17:10:01.654] <TB2> INFO: 2476200 events read in total (89996ms).
[17:10:31.651] <TB2> INFO: 3294848 events read in total (119993ms).
[17:11:01.911] <TB2> INFO: 4110440 events read in total (150253ms).
[17:11:31.386] <TB2> INFO: 4924232 events read in total (179728ms).
[17:11:35.714] <TB2> INFO: 5025280 events read in total (184056ms).
[17:11:35.763] <TB2> INFO: Test took 184979ms.
[17:11:53.820] <TB2> INFO: ROC 0 VthrComp = 126
[17:11:53.821] <TB2> INFO: ROC 1 VthrComp = 128
[17:11:53.821] <TB2> INFO: ROC 2 VthrComp = 132
[17:11:53.821] <TB2> INFO: ROC 3 VthrComp = 132
[17:11:53.821] <TB2> INFO: ROC 4 VthrComp = 125
[17:11:53.821] <TB2> INFO: ROC 5 VthrComp = 135
[17:11:53.821] <TB2> INFO: ROC 6 VthrComp = 114
[17:11:53.821] <TB2> INFO: ROC 7 VthrComp = 130
[17:11:53.822] <TB2> INFO: ROC 8 VthrComp = 130
[17:11:53.822] <TB2> INFO: ROC 9 VthrComp = 131
[17:11:53.822] <TB2> INFO: ROC 10 VthrComp = 126
[17:11:53.822] <TB2> INFO: ROC 11 VthrComp = 122
[17:11:53.822] <TB2> INFO: ROC 12 VthrComp = 122
[17:11:53.822] <TB2> INFO: ROC 13 VthrComp = 126
[17:11:53.822] <TB2> INFO: ROC 14 VthrComp = 127
[17:11:53.822] <TB2> INFO: ROC 15 VthrComp = 132
[17:11:54.097] <TB2> INFO: Expecting 41600 events.
[17:11:57.768] <TB2> INFO: 41600 events read in total (3080ms).
[17:11:57.769] <TB2> INFO: Test took 3945ms.
[17:11:57.778] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[17:11:57.778] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:11:57.790] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:11:57.790] <TB2> INFO: run 1 of 1
[17:11:58.068] <TB2> INFO: Expecting 5025280 events.
[17:12:24.607] <TB2> INFO: 591632 events read in total (25947ms).
[17:12:50.382] <TB2> INFO: 1181984 events read in total (51722ms).
[17:13:15.000] <TB2> INFO: 1771792 events read in total (77340ms).
[17:13:42.053] <TB2> INFO: 2360304 events read in total (103393ms).
[17:14:08.027] <TB2> INFO: 2946760 events read in total (129367ms).
[17:14:34.102] <TB2> INFO: 3532160 events read in total (155442ms).
[17:14:59.603] <TB2> INFO: 4117264 events read in total (180943ms).
[17:15:25.388] <TB2> INFO: 4701536 events read in total (206728ms).
[17:15:39.925] <TB2> INFO: 5025280 events read in total (221265ms).
[17:15:39.994] <TB2> INFO: Test took 222203ms.
[17:16:05.341] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 55.0638 for pixel 38/2 mean/min/max = 44.0574/32.529/55.5859
[17:16:05.341] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 64.4887 for pixel 0/6 mean/min/max = 48.5986/32.6588/64.5383
[17:16:05.342] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 61.2315 for pixel 0/40 mean/min/max = 46.9405/32.6241/61.2569
[17:16:05.342] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 61.1048 for pixel 13/17 mean/min/max = 47.1879/33.1862/61.1896
[17:16:05.343] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 61.0026 for pixel 2/77 mean/min/max = 45.9341/30.6426/61.2256
[17:16:05.343] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 60.8712 for pixel 44/70 mean/min/max = 47.8416/34.794/60.8891
[17:16:05.343] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 58.5533 for pixel 14/69 mean/min/max = 45.6824/32.7635/58.6013
[17:16:05.344] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 62.4906 for pixel 3/0 mean/min/max = 48.9773/35.4542/62.5004
[17:16:05.344] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 57.7112 for pixel 6/2 mean/min/max = 45.0877/32.441/57.7343
[17:16:05.345] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 62.0648 for pixel 20/69 mean/min/max = 46.7499/31.3485/62.1514
[17:16:05.345] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 57.7509 for pixel 24/27 mean/min/max = 45.3274/32.833/57.8218
[17:16:05.346] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 60.5041 for pixel 14/44 mean/min/max = 46.6176/32.7231/60.5122
[17:16:05.346] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 58.9938 for pixel 1/50 mean/min/max = 45.8558/32.6449/59.0667
[17:16:05.347] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 56.8056 for pixel 1/10 mean/min/max = 44.7204/32.6202/56.8207
[17:16:05.347] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 62.3698 for pixel 9/78 mean/min/max = 47.0853/31.7822/62.3884
[17:16:05.347] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 58.9253 for pixel 1/2 mean/min/max = 45.4381/31.7501/59.1262
[17:16:05.349] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:05.437] <TB2> INFO: Expecting 411648 events.
[17:16:15.014] <TB2> INFO: 411648 events read in total (8985ms).
[17:16:15.025] <TB2> INFO: Expecting 411648 events.
[17:16:24.393] <TB2> INFO: 411648 events read in total (8965ms).
[17:16:24.407] <TB2> INFO: Expecting 411648 events.
[17:16:33.750] <TB2> INFO: 411648 events read in total (8940ms).
[17:16:33.767] <TB2> INFO: Expecting 411648 events.
[17:16:43.182] <TB2> INFO: 411648 events read in total (9012ms).
[17:16:43.202] <TB2> INFO: Expecting 411648 events.
[17:16:52.704] <TB2> INFO: 411648 events read in total (9099ms).
[17:16:52.730] <TB2> INFO: Expecting 411648 events.
[17:17:02.196] <TB2> INFO: 411648 events read in total (9063ms).
[17:17:02.223] <TB2> INFO: Expecting 411648 events.
[17:17:11.602] <TB2> INFO: 411648 events read in total (8976ms).
[17:17:11.638] <TB2> INFO: Expecting 411648 events.
[17:17:20.972] <TB2> INFO: 411648 events read in total (8931ms).
[17:17:21.008] <TB2> INFO: Expecting 411648 events.
[17:17:30.392] <TB2> INFO: 411648 events read in total (8981ms).
[17:17:30.434] <TB2> INFO: Expecting 411648 events.
[17:17:39.863] <TB2> INFO: 411648 events read in total (9026ms).
[17:17:39.908] <TB2> INFO: Expecting 411648 events.
[17:17:49.363] <TB2> INFO: 411648 events read in total (9052ms).
[17:17:49.407] <TB2> INFO: Expecting 411648 events.
[17:17:58.862] <TB2> INFO: 411648 events read in total (9046ms).
[17:17:58.909] <TB2> INFO: Expecting 411648 events.
[17:18:08.298] <TB2> INFO: 411648 events read in total (8986ms).
[17:18:08.354] <TB2> INFO: Expecting 411648 events.
[17:18:17.849] <TB2> INFO: 411648 events read in total (9092ms).
[17:18:17.895] <TB2> INFO: Expecting 411648 events.
[17:18:27.201] <TB2> INFO: 411648 events read in total (8903ms).
[17:18:27.258] <TB2> INFO: Expecting 411648 events.
[17:18:36.552] <TB2> INFO: 411648 events read in total (8890ms).
[17:18:36.603] <TB2> INFO: Test took 151254ms.
[17:18:37.388] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[17:18:37.401] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:18:37.401] <TB2> INFO: run 1 of 1
[17:18:37.639] <TB2> INFO: Expecting 5025280 events.
[17:19:04.107] <TB2> INFO: 586992 events read in total (25876ms).
[17:19:30.021] <TB2> INFO: 1172104 events read in total (51791ms).
[17:19:55.907] <TB2> INFO: 1756800 events read in total (77676ms).
[17:20:22.069] <TB2> INFO: 2339928 events read in total (103838ms).
[17:20:48.019] <TB2> INFO: 2924480 events read in total (129788ms).
[17:21:14.384] <TB2> INFO: 3510560 events read in total (156153ms).
[17:21:40.643] <TB2> INFO: 4095584 events read in total (182412ms).
[17:22:06.923] <TB2> INFO: 4680184 events read in total (208692ms).
[17:22:22.682] <TB2> INFO: 5025280 events read in total (224451ms).
[17:22:22.816] <TB2> INFO: Test took 225416ms.
[17:22:47.991] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 2.144951 .. 147.412839
[17:22:48.231] <TB2> INFO: Expecting 208000 events.
[17:22:58.235] <TB2> INFO: 208000 events read in total (9413ms).
[17:22:58.236] <TB2> INFO: Test took 10244ms.
[17:22:58.283] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 157 (-1/-1) hits flags = 528 (plus default)
[17:22:58.296] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:22:58.296] <TB2> INFO: run 1 of 1
[17:22:58.574] <TB2> INFO: Expecting 5191680 events.
[17:23:25.212] <TB2> INFO: 581992 events read in total (26046ms).
[17:23:51.660] <TB2> INFO: 1164384 events read in total (52494ms).
[17:24:17.783] <TB2> INFO: 1747176 events read in total (78617ms).
[17:24:43.600] <TB2> INFO: 2330272 events read in total (104435ms).
[17:25:09.402] <TB2> INFO: 2912600 events read in total (130236ms).
[17:25:35.510] <TB2> INFO: 3494912 events read in total (156344ms).
[17:26:01.357] <TB2> INFO: 4076832 events read in total (182191ms).
[17:26:27.305] <TB2> INFO: 4658184 events read in total (208139ms).
[17:26:50.991] <TB2> INFO: 5191680 events read in total (231825ms).
[17:26:51.118] <TB2> INFO: Test took 232822ms.
[17:27:17.584] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.928793 .. 62.198148
[17:27:17.824] <TB2> INFO: Expecting 208000 events.
[17:27:27.772] <TB2> INFO: 208000 events read in total (9356ms).
[17:27:27.772] <TB2> INFO: Test took 10187ms.
[17:27:27.823] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 72 (-1/-1) hits flags = 528 (plus default)
[17:27:27.838] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:27:27.838] <TB2> INFO: run 1 of 1
[17:27:28.116] <TB2> INFO: Expecting 1863680 events.
[17:27:55.356] <TB2> INFO: 614984 events read in total (26649ms).
[17:28:22.432] <TB2> INFO: 1229216 events read in total (53724ms).
[17:28:49.660] <TB2> INFO: 1842744 events read in total (80952ms).
[17:28:50.956] <TB2> INFO: 1863680 events read in total (82248ms).
[17:28:50.992] <TB2> INFO: Test took 83154ms.
[17:29:05.835] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 27.102986 .. 50.180952
[17:29:06.073] <TB2> INFO: Expecting 208000 events.
[17:29:15.787] <TB2> INFO: 208000 events read in total (9123ms).
[17:29:15.788] <TB2> INFO: Test took 9952ms.
[17:29:15.839] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 60 (-1/-1) hits flags = 528 (plus default)
[17:29:15.852] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:29:15.852] <TB2> INFO: run 1 of 1
[17:29:16.130] <TB2> INFO: Expecting 1464320 events.
[17:29:45.069] <TB2> INFO: 642536 events read in total (28348ms).
[17:30:12.885] <TB2> INFO: 1284152 events read in total (56164ms).
[17:30:20.879] <TB2> INFO: 1464320 events read in total (64158ms).
[17:30:20.911] <TB2> INFO: Test took 65059ms.
[17:30:34.506] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 26.085274 .. 56.044452
[17:30:34.796] <TB2> INFO: Expecting 208000 events.
[17:30:44.957] <TB2> INFO: 208000 events read in total (9562ms).
[17:30:44.960] <TB2> INFO: Test took 10452ms.
[17:30:45.013] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 66 (-1/-1) hits flags = 528 (plus default)
[17:30:45.027] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:30:45.027] <TB2> INFO: run 1 of 1
[17:30:45.305] <TB2> INFO: Expecting 1697280 events.
[17:31:13.006] <TB2> INFO: 630608 events read in total (27109ms).
[17:31:40.546] <TB2> INFO: 1260224 events read in total (54649ms).
[17:31:59.008] <TB2> INFO: 1697280 events read in total (73111ms).
[17:31:59.058] <TB2> INFO: Test took 74032ms.
[17:32:12.839] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[17:32:12.839] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[17:32:12.852] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:32:12.852] <TB2> INFO: run 1 of 1
[17:32:13.088] <TB2> INFO: Expecting 1364480 events.
[17:32:42.024] <TB2> INFO: 669040 events read in total (28344ms).
[17:33:10.198] <TB2> INFO: 1337144 events read in total (56518ms).
[17:33:11.784] <TB2> INFO: 1364480 events read in total (58104ms).
[17:33:11.811] <TB2> INFO: Test took 58959ms.
[17:33:27.093] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C0.dat
[17:33:27.093] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C1.dat
[17:33:27.093] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C2.dat
[17:33:27.093] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C3.dat
[17:33:27.093] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C4.dat
[17:33:27.093] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C5.dat
[17:33:27.093] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C6.dat
[17:33:27.093] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C7.dat
[17:33:27.093] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C8.dat
[17:33:27.093] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C9.dat
[17:33:27.093] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C10.dat
[17:33:27.093] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C11.dat
[17:33:27.094] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C12.dat
[17:33:27.094] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C13.dat
[17:33:27.094] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C14.dat
[17:33:27.094] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C15.dat
[17:33:27.094] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters35_C0.dat
[17:33:27.100] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters35_C1.dat
[17:33:27.106] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters35_C2.dat
[17:33:27.112] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters35_C3.dat
[17:33:27.117] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters35_C4.dat
[17:33:27.122] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters35_C5.dat
[17:33:27.126] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters35_C6.dat
[17:33:27.131] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters35_C7.dat
[17:33:27.136] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters35_C8.dat
[17:33:27.140] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters35_C9.dat
[17:33:27.145] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters35_C10.dat
[17:33:27.150] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters35_C11.dat
[17:33:27.155] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters35_C12.dat
[17:33:27.159] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters35_C13.dat
[17:33:27.164] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters35_C14.dat
[17:33:27.169] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//trimParameters35_C15.dat
[17:33:27.173] <TB2> INFO: PixTestTrim::trimTest() done
[17:33:27.173] <TB2> INFO: vtrim: 121 145 132 138 141 150 125 145 118 150 119 131 126 114 133 126
[17:33:27.173] <TB2> INFO: vthrcomp: 126 128 132 132 125 135 114 130 130 131 126 122 122 126 127 132
[17:33:27.173] <TB2> INFO: vcal mean: 35.00 35.17 35.07 35.16 34.97 35.00 35.00 35.08 35.02 35.19 35.11 35.17 34.96 35.00 35.17 35.03
[17:33:27.173] <TB2> INFO: vcal RMS: 0.93 1.25 1.42 1.22 1.10 1.36 0.92 1.09 1.14 1.40 1.11 1.20 0.99 0.92 1.39 1.01
[17:33:27.173] <TB2> INFO: bits mean: 9.87 9.01 9.09 9.36 9.68 8.93 9.44 8.43 9.64 10.16 9.50 9.55 9.46 9.60 9.44 9.30
[17:33:27.173] <TB2> INFO: bits RMS: 2.57 2.71 2.72 2.56 2.83 2.29 2.68 2.49 2.69 2.50 2.71 2.63 2.68 2.67 2.77 2.87
[17:33:27.181] <TB2> INFO: ----------------------------------------------------------------------
[17:33:27.181] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[17:33:27.181] <TB2> INFO: ----------------------------------------------------------------------
[17:33:27.184] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[17:33:27.196] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:33:27.196] <TB2> INFO: run 1 of 1
[17:33:27.433] <TB2> INFO: Expecting 4160000 events.
[17:34:00.501] <TB2> INFO: 767145 events read in total (32477ms).
[17:34:32.428] <TB2> INFO: 1525580 events read in total (64404ms).
[17:35:04.480] <TB2> INFO: 2278605 events read in total (96456ms).
[17:35:36.528] <TB2> INFO: 3026435 events read in total (128504ms).
[17:36:08.683] <TB2> INFO: 3769585 events read in total (160659ms).
[17:36:25.725] <TB2> INFO: 4160000 events read in total (177701ms).
[17:36:25.843] <TB2> INFO: Test took 178647ms.
[17:36:52.255] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[17:36:52.268] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:36:52.268] <TB2> INFO: run 1 of 1
[17:36:52.505] <TB2> INFO: Expecting 4264000 events.
[17:37:24.859] <TB2> INFO: 734710 events read in total (31762ms).
[17:37:56.377] <TB2> INFO: 1461625 events read in total (63280ms).
[17:38:28.215] <TB2> INFO: 2185005 events read in total (95118ms).
[17:39:00.023] <TB2> INFO: 2903775 events read in total (126926ms).
[17:39:31.410] <TB2> INFO: 3619565 events read in total (158313ms).
[17:40:00.142] <TB2> INFO: 4264000 events read in total (187045ms).
[17:40:00.224] <TB2> INFO: Test took 187956ms.
[17:40:27.277] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 198 (-1/-1) hits flags = 528 (plus default)
[17:40:27.291] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:40:27.291] <TB2> INFO: run 1 of 1
[17:40:27.553] <TB2> INFO: Expecting 4139200 events.
[17:41:00.030] <TB2> INFO: 743350 events read in total (31885ms).
[17:41:31.690] <TB2> INFO: 1478955 events read in total (63545ms).
[17:42:03.724] <TB2> INFO: 2210320 events read in total (95579ms).
[17:42:34.965] <TB2> INFO: 2936550 events read in total (126821ms).
[17:43:07.061] <TB2> INFO: 3659855 events read in total (158916ms).
[17:43:28.055] <TB2> INFO: 4139200 events read in total (179910ms).
[17:43:28.171] <TB2> INFO: Test took 180880ms.
[17:43:54.964] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[17:43:54.977] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:43:54.977] <TB2> INFO: run 1 of 1
[17:43:55.214] <TB2> INFO: Expecting 4160000 events.
[17:44:27.700] <TB2> INFO: 742225 events read in total (31894ms).
[17:44:59.223] <TB2> INFO: 1476580 events read in total (63417ms).
[17:45:30.811] <TB2> INFO: 2206750 events read in total (95005ms).
[17:46:02.344] <TB2> INFO: 2931995 events read in total (126538ms).
[17:46:34.372] <TB2> INFO: 3654115 events read in total (158566ms).
[17:46:56.077] <TB2> INFO: 4160000 events read in total (180271ms).
[17:46:56.182] <TB2> INFO: Test took 181206ms.
[17:47:22.765] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 197 (-1/-1) hits flags = 528 (plus default)
[17:47:22.778] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:47:22.778] <TB2> INFO: run 1 of 1
[17:47:23.015] <TB2> INFO: Expecting 4118400 events.
[17:47:55.854] <TB2> INFO: 744950 events read in total (32248ms).
[17:48:27.582] <TB2> INFO: 1482255 events read in total (63976ms).
[17:48:58.869] <TB2> INFO: 2215365 events read in total (95263ms).
[17:49:30.306] <TB2> INFO: 2942760 events read in total (126700ms).
[17:50:01.814] <TB2> INFO: 3667545 events read in total (158208ms).
[17:50:21.212] <TB2> INFO: 4118400 events read in total (177606ms).
[17:50:21.283] <TB2> INFO: Test took 178505ms.
[17:50:44.825] <TB2> INFO: PixTestTrim::trimBitTest() done
[17:50:44.826] <TB2> INFO: PixTestTrim::doTest() done, duration: 2534 seconds
[17:50:44.826] <TB2> INFO: Decoding statistics:
[17:50:44.826] <TB2> INFO: General information:
[17:50:44.826] <TB2> INFO: 16bit words read: 0
[17:50:44.826] <TB2> INFO: valid events total: 0
[17:50:44.826] <TB2> INFO: empty events: 0
[17:50:44.826] <TB2> INFO: valid events with pixels: 0
[17:50:44.826] <TB2> INFO: valid pixel hits: 0
[17:50:44.826] <TB2> INFO: Event errors: 0
[17:50:44.826] <TB2> INFO: start marker: 0
[17:50:44.826] <TB2> INFO: stop marker: 0
[17:50:44.826] <TB2> INFO: overflow: 0
[17:50:44.826] <TB2> INFO: invalid 5bit words: 0
[17:50:44.826] <TB2> INFO: invalid XOR eye diagram: 0
[17:50:44.826] <TB2> INFO: frame (failed synchr.): 0
[17:50:44.827] <TB2> INFO: idle data (no TBM trl): 0
[17:50:44.827] <TB2> INFO: no data (only TBM hdr): 0
[17:50:44.827] <TB2> INFO: TBM errors: 0
[17:50:44.827] <TB2> INFO: flawed TBM headers: 0
[17:50:44.827] <TB2> INFO: flawed TBM trailers: 0
[17:50:44.827] <TB2> INFO: event ID mismatches: 0
[17:50:44.827] <TB2> INFO: ROC errors: 0
[17:50:44.827] <TB2> INFO: missing ROC header(s): 0
[17:50:44.827] <TB2> INFO: misplaced readback start: 0
[17:50:44.827] <TB2> INFO: Pixel decoding errors: 0
[17:50:44.827] <TB2> INFO: pixel data incomplete: 0
[17:50:44.827] <TB2> INFO: pixel address: 0
[17:50:44.827] <TB2> INFO: pulse height fill bit: 0
[17:50:44.827] <TB2> INFO: buffer corruption: 0
[17:50:45.428] <TB2> INFO: ######################################################################
[17:50:45.428] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[17:50:45.428] <TB2> INFO: ######################################################################
[17:50:45.666] <TB2> INFO: Expecting 41600 events.
[17:50:49.188] <TB2> INFO: 41600 events read in total (2930ms).
[17:50:49.189] <TB2> INFO: Test took 3760ms.
[17:50:49.675] <TB2> INFO: Expecting 41600 events.
[17:50:53.281] <TB2> INFO: 41600 events read in total (3015ms).
[17:50:53.282] <TB2> INFO: Test took 3888ms.
[17:50:53.571] <TB2> INFO: Expecting 41600 events.
[17:50:57.155] <TB2> INFO: 41600 events read in total (2993ms).
[17:50:57.156] <TB2> INFO: Test took 3850ms.
[17:50:57.452] <TB2> INFO: Expecting 41600 events.
[17:51:00.994] <TB2> INFO: 41600 events read in total (2950ms).
[17:51:00.995] <TB2> INFO: Test took 3815ms.
[17:51:01.288] <TB2> INFO: Expecting 41600 events.
[17:51:04.856] <TB2> INFO: 41600 events read in total (2976ms).
[17:51:04.857] <TB2> INFO: Test took 3833ms.
[17:51:05.161] <TB2> INFO: Expecting 41600 events.
[17:51:08.836] <TB2> INFO: 41600 events read in total (3083ms).
[17:51:08.837] <TB2> INFO: Test took 3955ms.
[17:51:09.128] <TB2> INFO: Expecting 41600 events.
[17:51:12.704] <TB2> INFO: 41600 events read in total (2984ms).
[17:51:12.704] <TB2> INFO: Test took 3840ms.
[17:51:12.993] <TB2> INFO: Expecting 41600 events.
[17:51:16.503] <TB2> INFO: 41600 events read in total (2918ms).
[17:51:16.504] <TB2> INFO: Test took 3776ms.
[17:51:16.793] <TB2> INFO: Expecting 41600 events.
[17:51:20.292] <TB2> INFO: 41600 events read in total (2907ms).
[17:51:20.293] <TB2> INFO: Test took 3764ms.
[17:51:20.581] <TB2> INFO: Expecting 41600 events.
[17:51:24.071] <TB2> INFO: 41600 events read in total (2898ms).
[17:51:24.072] <TB2> INFO: Test took 3755ms.
[17:51:24.360] <TB2> INFO: Expecting 41600 events.
[17:51:27.942] <TB2> INFO: 41600 events read in total (2991ms).
[17:51:27.944] <TB2> INFO: Test took 3848ms.
[17:51:28.237] <TB2> INFO: Expecting 41600 events.
[17:51:31.751] <TB2> INFO: 41600 events read in total (2923ms).
[17:51:31.752] <TB2> INFO: Test took 3780ms.
[17:51:32.042] <TB2> INFO: Expecting 41600 events.
[17:51:35.650] <TB2> INFO: 41600 events read in total (3016ms).
[17:51:35.651] <TB2> INFO: Test took 3874ms.
[17:51:35.940] <TB2> INFO: Expecting 41600 events.
[17:51:39.602] <TB2> INFO: 41600 events read in total (3070ms).
[17:51:39.603] <TB2> INFO: Test took 3928ms.
[17:51:39.892] <TB2> INFO: Expecting 41600 events.
[17:51:43.462] <TB2> INFO: 41600 events read in total (2978ms).
[17:51:43.463] <TB2> INFO: Test took 3835ms.
[17:51:43.752] <TB2> INFO: Expecting 41600 events.
[17:51:47.324] <TB2> INFO: 41600 events read in total (2980ms).
[17:51:47.325] <TB2> INFO: Test took 3838ms.
[17:51:47.614] <TB2> INFO: Expecting 41600 events.
[17:51:51.133] <TB2> INFO: 41600 events read in total (2928ms).
[17:51:51.133] <TB2> INFO: Test took 3784ms.
[17:51:51.435] <TB2> INFO: Expecting 41600 events.
[17:51:54.999] <TB2> INFO: 41600 events read in total (2972ms).
[17:51:54.000] <TB2> INFO: Test took 3842ms.
[17:51:55.290] <TB2> INFO: Expecting 41600 events.
[17:51:58.913] <TB2> INFO: 41600 events read in total (3031ms).
[17:51:58.914] <TB2> INFO: Test took 3889ms.
[17:51:59.206] <TB2> INFO: Expecting 41600 events.
[17:52:02.763] <TB2> INFO: 41600 events read in total (2966ms).
[17:52:02.764] <TB2> INFO: Test took 3823ms.
[17:52:03.052] <TB2> INFO: Expecting 41600 events.
[17:52:06.624] <TB2> INFO: 41600 events read in total (2980ms).
[17:52:06.625] <TB2> INFO: Test took 3839ms.
[17:52:06.918] <TB2> INFO: Expecting 41600 events.
[17:52:10.448] <TB2> INFO: 41600 events read in total (2939ms).
[17:52:10.449] <TB2> INFO: Test took 3797ms.
[17:52:10.739] <TB2> INFO: Expecting 41600 events.
[17:52:14.285] <TB2> INFO: 41600 events read in total (2954ms).
[17:52:14.286] <TB2> INFO: Test took 3812ms.
[17:52:14.575] <TB2> INFO: Expecting 41600 events.
[17:52:18.106] <TB2> INFO: 41600 events read in total (2939ms).
[17:52:18.106] <TB2> INFO: Test took 3796ms.
[17:52:18.396] <TB2> INFO: Expecting 41600 events.
[17:52:21.899] <TB2> INFO: 41600 events read in total (2912ms).
[17:52:21.900] <TB2> INFO: Test took 3770ms.
[17:52:22.189] <TB2> INFO: Expecting 41600 events.
[17:52:25.740] <TB2> INFO: 41600 events read in total (2959ms).
[17:52:25.741] <TB2> INFO: Test took 3817ms.
[17:52:26.047] <TB2> INFO: Expecting 41600 events.
[17:52:29.641] <TB2> INFO: 41600 events read in total (3002ms).
[17:52:29.642] <TB2> INFO: Test took 3875ms.
[17:52:29.932] <TB2> INFO: Expecting 41600 events.
[17:52:33.421] <TB2> INFO: 41600 events read in total (2897ms).
[17:52:33.422] <TB2> INFO: Test took 3755ms.
[17:52:33.711] <TB2> INFO: Expecting 41600 events.
[17:52:37.237] <TB2> INFO: 41600 events read in total (2934ms).
[17:52:37.237] <TB2> INFO: Test took 3791ms.
[17:52:37.531] <TB2> INFO: Expecting 41600 events.
[17:52:41.139] <TB2> INFO: 41600 events read in total (3016ms).
[17:52:41.140] <TB2> INFO: Test took 3875ms.
[17:52:41.430] <TB2> INFO: Expecting 2560 events.
[17:52:42.326] <TB2> INFO: 2560 events read in total (304ms).
[17:52:42.326] <TB2> INFO: Test took 1173ms.
[17:52:42.634] <TB2> INFO: Expecting 2560 events.
[17:52:43.528] <TB2> INFO: 2560 events read in total (302ms).
[17:52:43.528] <TB2> INFO: Test took 1201ms.
[17:52:43.837] <TB2> INFO: Expecting 2560 events.
[17:52:44.725] <TB2> INFO: 2560 events read in total (296ms).
[17:52:44.726] <TB2> INFO: Test took 1197ms.
[17:52:45.033] <TB2> INFO: Expecting 2560 events.
[17:52:45.928] <TB2> INFO: 2560 events read in total (303ms).
[17:52:45.929] <TB2> INFO: Test took 1203ms.
[17:52:46.236] <TB2> INFO: Expecting 2560 events.
[17:52:47.127] <TB2> INFO: 2560 events read in total (300ms).
[17:52:47.128] <TB2> INFO: Test took 1199ms.
[17:52:47.435] <TB2> INFO: Expecting 2560 events.
[17:52:48.322] <TB2> INFO: 2560 events read in total (295ms).
[17:52:48.322] <TB2> INFO: Test took 1194ms.
[17:52:48.631] <TB2> INFO: Expecting 2560 events.
[17:52:49.516] <TB2> INFO: 2560 events read in total (294ms).
[17:52:49.516] <TB2> INFO: Test took 1194ms.
[17:52:49.824] <TB2> INFO: Expecting 2560 events.
[17:52:50.710] <TB2> INFO: 2560 events read in total (294ms).
[17:52:50.710] <TB2> INFO: Test took 1194ms.
[17:52:51.018] <TB2> INFO: Expecting 2560 events.
[17:52:51.909] <TB2> INFO: 2560 events read in total (300ms).
[17:52:51.910] <TB2> INFO: Test took 1199ms.
[17:52:52.217] <TB2> INFO: Expecting 2560 events.
[17:52:53.098] <TB2> INFO: 2560 events read in total (289ms).
[17:52:53.098] <TB2> INFO: Test took 1189ms.
[17:52:53.405] <TB2> INFO: Expecting 2560 events.
[17:52:54.293] <TB2> INFO: 2560 events read in total (296ms).
[17:52:54.294] <TB2> INFO: Test took 1195ms.
[17:52:54.602] <TB2> INFO: Expecting 2560 events.
[17:52:55.490] <TB2> INFO: 2560 events read in total (296ms).
[17:52:55.490] <TB2> INFO: Test took 1196ms.
[17:52:55.799] <TB2> INFO: Expecting 2560 events.
[17:52:56.684] <TB2> INFO: 2560 events read in total (294ms).
[17:52:56.684] <TB2> INFO: Test took 1193ms.
[17:52:56.991] <TB2> INFO: Expecting 2560 events.
[17:52:57.882] <TB2> INFO: 2560 events read in total (299ms).
[17:52:57.882] <TB2> INFO: Test took 1197ms.
[17:52:58.190] <TB2> INFO: Expecting 2560 events.
[17:52:59.082] <TB2> INFO: 2560 events read in total (300ms).
[17:52:59.082] <TB2> INFO: Test took 1199ms.
[17:52:59.389] <TB2> INFO: Expecting 2560 events.
[17:53:00.281] <TB2> INFO: 2560 events read in total (300ms).
[17:53:00.281] <TB2> INFO: Test took 1198ms.
[17:53:00.285] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:53:00.590] <TB2> INFO: Expecting 655360 events.
[17:53:15.376] <TB2> INFO: 655360 events read in total (14194ms).
[17:53:15.388] <TB2> INFO: Expecting 655360 events.
[17:53:30.076] <TB2> INFO: 655360 events read in total (14285ms).
[17:53:30.091] <TB2> INFO: Expecting 655360 events.
[17:53:44.647] <TB2> INFO: 655360 events read in total (14153ms).
[17:53:44.671] <TB2> INFO: Expecting 655360 events.
[17:53:59.342] <TB2> INFO: 655360 events read in total (14267ms).
[17:53:59.373] <TB2> INFO: Expecting 655360 events.
[17:54:14.026] <TB2> INFO: 655360 events read in total (14250ms).
[17:54:14.055] <TB2> INFO: Expecting 655360 events.
[17:54:28.707] <TB2> INFO: 655360 events read in total (14249ms).
[17:54:28.740] <TB2> INFO: Expecting 655360 events.
[17:54:43.388] <TB2> INFO: 655360 events read in total (14245ms).
[17:54:43.428] <TB2> INFO: Expecting 655360 events.
[17:54:58.008] <TB2> INFO: 655360 events read in total (14176ms).
[17:54:58.050] <TB2> INFO: Expecting 655360 events.
[17:55:12.597] <TB2> INFO: 655360 events read in total (14144ms).
[17:55:12.645] <TB2> INFO: Expecting 655360 events.
[17:55:27.323] <TB2> INFO: 655360 events read in total (14275ms).
[17:55:27.373] <TB2> INFO: Expecting 655360 events.
[17:55:41.979] <TB2> INFO: 655360 events read in total (14202ms).
[17:55:42.100] <TB2> INFO: Expecting 655360 events.
[17:55:56.842] <TB2> INFO: 655360 events read in total (14339ms).
[17:55:56.953] <TB2> INFO: Expecting 655360 events.
[17:56:11.748] <TB2> INFO: 655360 events read in total (14392ms).
[17:56:11.883] <TB2> INFO: Expecting 655360 events.
[17:56:26.622] <TB2> INFO: 655360 events read in total (14336ms).
[17:56:26.708] <TB2> INFO: Expecting 655360 events.
[17:56:41.433] <TB2> INFO: 655360 events read in total (14322ms).
[17:56:41.605] <TB2> INFO: Expecting 655360 events.
[17:56:56.270] <TB2> INFO: 655360 events read in total (14262ms).
[17:56:56.437] <TB2> INFO: Test took 236152ms.
[17:56:56.534] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:56:56.789] <TB2> INFO: Expecting 655360 events.
[17:57:11.658] <TB2> INFO: 655360 events read in total (14277ms).
[17:57:11.675] <TB2> INFO: Expecting 655360 events.
[17:57:26.373] <TB2> INFO: 655360 events read in total (14295ms).
[17:57:26.389] <TB2> INFO: Expecting 655360 events.
[17:57:40.729] <TB2> INFO: 655360 events read in total (13936ms).
[17:57:40.749] <TB2> INFO: Expecting 655360 events.
[17:57:55.640] <TB2> INFO: 655360 events read in total (14488ms).
[17:57:55.664] <TB2> INFO: Expecting 655360 events.
[17:58:10.012] <TB2> INFO: 655360 events read in total (13944ms).
[17:58:10.040] <TB2> INFO: Expecting 655360 events.
[17:58:24.651] <TB2> INFO: 655360 events read in total (14208ms).
[17:58:24.685] <TB2> INFO: Expecting 655360 events.
[17:58:39.302] <TB2> INFO: 655360 events read in total (14214ms).
[17:58:39.353] <TB2> INFO: Expecting 655360 events.
[17:58:53.754] <TB2> INFO: 655360 events read in total (13998ms).
[17:58:53.797] <TB2> INFO: Expecting 655360 events.
[17:59:08.507] <TB2> INFO: 655360 events read in total (14307ms).
[17:59:08.554] <TB2> INFO: Expecting 655360 events.
[17:59:23.233] <TB2> INFO: 655360 events read in total (14276ms).
[17:59:23.299] <TB2> INFO: Expecting 655360 events.
[17:59:38.068] <TB2> INFO: 655360 events read in total (14366ms).
[17:59:38.164] <TB2> INFO: Expecting 655360 events.
[17:59:52.753] <TB2> INFO: 655360 events read in total (14186ms).
[17:59:52.845] <TB2> INFO: Expecting 655360 events.
[18:00:07.485] <TB2> INFO: 655360 events read in total (14238ms).
[18:00:07.590] <TB2> INFO: Expecting 655360 events.
[18:00:22.487] <TB2> INFO: 655360 events read in total (14493ms).
[18:00:22.592] <TB2> INFO: Expecting 655360 events.
[18:00:37.490] <TB2> INFO: 655360 events read in total (14495ms).
[18:00:37.601] <TB2> INFO: Expecting 655360 events.
[18:00:52.601] <TB2> INFO: 655360 events read in total (14597ms).
[18:00:52.716] <TB2> INFO: Test took 236183ms.
[18:00:52.888] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:00:52.894] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:00:52.900] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:00:52.905] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[18:00:52.911] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:00:52.917] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:00:52.922] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[18:00:52.928] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[18:00:52.934] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[18:00:52.940] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[18:00:52.945] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[18:00:52.951] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[18:00:52.957] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:00:52.963] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:00:52.968] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:00:52.974] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:00:52.980] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:00:52.985] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:00:52.991] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:00:52.997] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[18:00:52.002] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[18:00:53.008] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[18:00:53.014] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[18:00:53.020] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[18:00:53.025] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:00:53.031] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:00:53.037] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[18:00:53.042] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:00:53.048] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:00:53.054] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[18:00:53.060] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[18:00:53.065] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[18:00:53.071] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[18:00:53.077] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[18:00:53.083] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[18:00:53.088] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[18:00:53.094] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:00:53.100] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:00:53.106] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:00:53.112] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:00:53.117] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:00:53.123] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:00:53.159] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C0.dat
[18:00:53.159] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C1.dat
[18:00:53.159] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C2.dat
[18:00:53.160] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C3.dat
[18:00:53.160] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C4.dat
[18:00:53.160] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C5.dat
[18:00:53.160] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C6.dat
[18:00:53.160] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C7.dat
[18:00:53.161] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C8.dat
[18:00:53.161] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C9.dat
[18:00:53.161] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C10.dat
[18:00:53.161] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C11.dat
[18:00:53.161] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C12.dat
[18:00:53.161] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C13.dat
[18:00:53.162] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C14.dat
[18:00:53.162] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//dacParameters35_C15.dat
[18:00:53.405] <TB2> INFO: Expecting 41600 events.
[18:00:56.602] <TB2> INFO: 41600 events read in total (2605ms).
[18:00:56.603] <TB2> INFO: Test took 3437ms.
[18:00:57.059] <TB2> INFO: Expecting 41600 events.
[18:01:00.145] <TB2> INFO: 41600 events read in total (2494ms).
[18:01:00.146] <TB2> INFO: Test took 3329ms.
[18:01:00.602] <TB2> INFO: Expecting 41600 events.
[18:01:03.715] <TB2> INFO: 41600 events read in total (2521ms).
[18:01:03.716] <TB2> INFO: Test took 3356ms.
[18:01:03.934] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:04.024] <TB2> INFO: Expecting 2560 events.
[18:01:04.917] <TB2> INFO: 2560 events read in total (302ms).
[18:01:04.918] <TB2> INFO: Test took 984ms.
[18:01:04.921] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:05.227] <TB2> INFO: Expecting 2560 events.
[18:01:06.119] <TB2> INFO: 2560 events read in total (300ms).
[18:01:06.119] <TB2> INFO: Test took 1198ms.
[18:01:06.122] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:06.427] <TB2> INFO: Expecting 2560 events.
[18:01:07.311] <TB2> INFO: 2560 events read in total (292ms).
[18:01:07.312] <TB2> INFO: Test took 1190ms.
[18:01:07.314] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:07.621] <TB2> INFO: Expecting 2560 events.
[18:01:08.513] <TB2> INFO: 2560 events read in total (300ms).
[18:01:08.514] <TB2> INFO: Test took 1200ms.
[18:01:08.516] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:08.822] <TB2> INFO: Expecting 2560 events.
[18:01:09.715] <TB2> INFO: 2560 events read in total (301ms).
[18:01:09.716] <TB2> INFO: Test took 1200ms.
[18:01:09.719] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:10.024] <TB2> INFO: Expecting 2560 events.
[18:01:10.910] <TB2> INFO: 2560 events read in total (295ms).
[18:01:10.911] <TB2> INFO: Test took 1192ms.
[18:01:10.913] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:11.219] <TB2> INFO: Expecting 2560 events.
[18:01:12.112] <TB2> INFO: 2560 events read in total (301ms).
[18:01:12.112] <TB2> INFO: Test took 1199ms.
[18:01:12.114] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:12.422] <TB2> INFO: Expecting 2560 events.
[18:01:13.315] <TB2> INFO: 2560 events read in total (302ms).
[18:01:13.315] <TB2> INFO: Test took 1201ms.
[18:01:13.318] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:13.623] <TB2> INFO: Expecting 2560 events.
[18:01:14.508] <TB2> INFO: 2560 events read in total (293ms).
[18:01:14.509] <TB2> INFO: Test took 1192ms.
[18:01:14.512] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:14.817] <TB2> INFO: Expecting 2560 events.
[18:01:15.699] <TB2> INFO: 2560 events read in total (290ms).
[18:01:15.699] <TB2> INFO: Test took 1187ms.
[18:01:15.702] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:16.007] <TB2> INFO: Expecting 2560 events.
[18:01:16.896] <TB2> INFO: 2560 events read in total (298ms).
[18:01:16.896] <TB2> INFO: Test took 1194ms.
[18:01:16.899] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:17.204] <TB2> INFO: Expecting 2560 events.
[18:01:18.090] <TB2> INFO: 2560 events read in total (294ms).
[18:01:18.091] <TB2> INFO: Test took 1192ms.
[18:01:18.094] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:18.399] <TB2> INFO: Expecting 2560 events.
[18:01:19.287] <TB2> INFO: 2560 events read in total (296ms).
[18:01:19.287] <TB2> INFO: Test took 1193ms.
[18:01:19.289] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:19.597] <TB2> INFO: Expecting 2560 events.
[18:01:20.478] <TB2> INFO: 2560 events read in total (289ms).
[18:01:20.478] <TB2> INFO: Test took 1189ms.
[18:01:20.481] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:20.786] <TB2> INFO: Expecting 2560 events.
[18:01:21.676] <TB2> INFO: 2560 events read in total (298ms).
[18:01:21.677] <TB2> INFO: Test took 1196ms.
[18:01:21.680] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:21.984] <TB2> INFO: Expecting 2560 events.
[18:01:22.872] <TB2> INFO: 2560 events read in total (296ms).
[18:01:22.872] <TB2> INFO: Test took 1192ms.
[18:01:22.874] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:23.180] <TB2> INFO: Expecting 2560 events.
[18:01:24.064] <TB2> INFO: 2560 events read in total (292ms).
[18:01:24.065] <TB2> INFO: Test took 1191ms.
[18:01:24.067] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:24.374] <TB2> INFO: Expecting 2560 events.
[18:01:25.256] <TB2> INFO: 2560 events read in total (290ms).
[18:01:25.256] <TB2> INFO: Test took 1189ms.
[18:01:25.259] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:25.565] <TB2> INFO: Expecting 2560 events.
[18:01:26.454] <TB2> INFO: 2560 events read in total (297ms).
[18:01:26.455] <TB2> INFO: Test took 1196ms.
[18:01:26.457] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:26.762] <TB2> INFO: Expecting 2560 events.
[18:01:27.649] <TB2> INFO: 2560 events read in total (295ms).
[18:01:27.650] <TB2> INFO: Test took 1193ms.
[18:01:27.652] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:27.958] <TB2> INFO: Expecting 2560 events.
[18:01:28.841] <TB2> INFO: 2560 events read in total (291ms).
[18:01:28.841] <TB2> INFO: Test took 1189ms.
[18:01:28.843] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:29.151] <TB2> INFO: Expecting 2560 events.
[18:01:30.041] <TB2> INFO: 2560 events read in total (298ms).
[18:01:30.042] <TB2> INFO: Test took 1199ms.
[18:01:30.045] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:30.349] <TB2> INFO: Expecting 2560 events.
[18:01:31.237] <TB2> INFO: 2560 events read in total (296ms).
[18:01:31.237] <TB2> INFO: Test took 1192ms.
[18:01:31.240] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:31.546] <TB2> INFO: Expecting 2560 events.
[18:01:32.431] <TB2> INFO: 2560 events read in total (293ms).
[18:01:32.431] <TB2> INFO: Test took 1191ms.
[18:01:32.433] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:32.738] <TB2> INFO: Expecting 2560 events.
[18:01:33.627] <TB2> INFO: 2560 events read in total (297ms).
[18:01:33.628] <TB2> INFO: Test took 1195ms.
[18:01:33.630] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:33.937] <TB2> INFO: Expecting 2560 events.
[18:01:34.822] <TB2> INFO: 2560 events read in total (293ms).
[18:01:34.822] <TB2> INFO: Test took 1192ms.
[18:01:34.825] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:35.131] <TB2> INFO: Expecting 2560 events.
[18:01:36.023] <TB2> INFO: 2560 events read in total (301ms).
[18:01:36.024] <TB2> INFO: Test took 1199ms.
[18:01:36.027] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:36.331] <TB2> INFO: Expecting 2560 events.
[18:01:37.218] <TB2> INFO: 2560 events read in total (295ms).
[18:01:37.218] <TB2> INFO: Test took 1191ms.
[18:01:37.221] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:37.526] <TB2> INFO: Expecting 2560 events.
[18:01:38.419] <TB2> INFO: 2560 events read in total (301ms).
[18:01:38.419] <TB2> INFO: Test took 1198ms.
[18:01:38.422] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:38.728] <TB2> INFO: Expecting 2560 events.
[18:01:39.622] <TB2> INFO: 2560 events read in total (302ms).
[18:01:39.622] <TB2> INFO: Test took 1200ms.
[18:01:39.626] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:39.930] <TB2> INFO: Expecting 2560 events.
[18:01:40.818] <TB2> INFO: 2560 events read in total (296ms).
[18:01:40.818] <TB2> INFO: Test took 1192ms.
[18:01:40.821] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:41.127] <TB2> INFO: Expecting 2560 events.
[18:01:42.023] <TB2> INFO: 2560 events read in total (304ms).
[18:01:42.024] <TB2> INFO: Test took 1203ms.
[18:01:42.497] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 657 seconds
[18:01:42.497] <TB2> INFO: PH scale (per ROC): 56 51 51 36 55 50 50 32 35 48 44 36 51 39 44 57
[18:01:42.497] <TB2> INFO: PH offset (per ROC): 109 112 114 94 107 114 122 96 98 86 102 107 129 101 89 126
[18:01:42.508] <TB2> INFO: Decoding statistics:
[18:01:42.508] <TB2> INFO: General information:
[18:01:42.508] <TB2> INFO: 16bit words read: 127882
[18:01:42.508] <TB2> INFO: valid events total: 20480
[18:01:42.508] <TB2> INFO: empty events: 17979
[18:01:42.508] <TB2> INFO: valid events with pixels: 2501
[18:01:42.508] <TB2> INFO: valid pixel hits: 2501
[18:01:42.508] <TB2> INFO: Event errors: 0
[18:01:42.508] <TB2> INFO: start marker: 0
[18:01:42.508] <TB2> INFO: stop marker: 0
[18:01:42.508] <TB2> INFO: overflow: 0
[18:01:42.508] <TB2> INFO: invalid 5bit words: 0
[18:01:42.508] <TB2> INFO: invalid XOR eye diagram: 0
[18:01:42.508] <TB2> INFO: frame (failed synchr.): 0
[18:01:42.508] <TB2> INFO: idle data (no TBM trl): 0
[18:01:42.508] <TB2> INFO: no data (only TBM hdr): 0
[18:01:42.508] <TB2> INFO: TBM errors: 0
[18:01:42.508] <TB2> INFO: flawed TBM headers: 0
[18:01:42.508] <TB2> INFO: flawed TBM trailers: 0
[18:01:42.508] <TB2> INFO: event ID mismatches: 0
[18:01:42.508] <TB2> INFO: ROC errors: 0
[18:01:42.508] <TB2> INFO: missing ROC header(s): 0
[18:01:42.508] <TB2> INFO: misplaced readback start: 0
[18:01:42.508] <TB2> INFO: Pixel decoding errors: 0
[18:01:42.508] <TB2> INFO: pixel data incomplete: 0
[18:01:42.508] <TB2> INFO: pixel address: 0
[18:01:42.508] <TB2> INFO: pulse height fill bit: 0
[18:01:42.508] <TB2> INFO: buffer corruption: 0
[18:01:42.668] <TB2> INFO: ######################################################################
[18:01:42.668] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[18:01:42.668] <TB2> INFO: ######################################################################
[18:01:42.683] <TB2> INFO: scanning low vcal = 10
[18:01:42.922] <TB2> INFO: Expecting 41600 events.
[18:01:46.546] <TB2> INFO: 41600 events read in total (3032ms).
[18:01:46.546] <TB2> INFO: Test took 3863ms.
[18:01:46.548] <TB2> INFO: scanning low vcal = 20
[18:01:46.847] <TB2> INFO: Expecting 41600 events.
[18:01:50.407] <TB2> INFO: 41600 events read in total (2969ms).
[18:01:50.407] <TB2> INFO: Test took 3859ms.
[18:01:50.409] <TB2> INFO: scanning low vcal = 30
[18:01:50.707] <TB2> INFO: Expecting 41600 events.
[18:01:54.340] <TB2> INFO: 41600 events read in total (3041ms).
[18:01:54.341] <TB2> INFO: Test took 3932ms.
[18:01:54.343] <TB2> INFO: scanning low vcal = 40
[18:01:54.622] <TB2> INFO: Expecting 41600 events.
[18:01:58.565] <TB2> INFO: 41600 events read in total (3352ms).
[18:01:58.567] <TB2> INFO: Test took 4223ms.
[18:01:58.571] <TB2> INFO: scanning low vcal = 50
[18:01:58.846] <TB2> INFO: Expecting 41600 events.
[18:02:02.805] <TB2> INFO: 41600 events read in total (3367ms).
[18:02:02.806] <TB2> INFO: Test took 4235ms.
[18:02:02.809] <TB2> INFO: scanning low vcal = 60
[18:02:03.085] <TB2> INFO: Expecting 41600 events.
[18:02:07.027] <TB2> INFO: 41600 events read in total (3350ms).
[18:02:07.028] <TB2> INFO: Test took 4219ms.
[18:02:07.032] <TB2> INFO: scanning low vcal = 70
[18:02:07.308] <TB2> INFO: Expecting 41600 events.
[18:02:11.370] <TB2> INFO: 41600 events read in total (3470ms).
[18:02:11.371] <TB2> INFO: Test took 4339ms.
[18:02:11.374] <TB2> INFO: scanning low vcal = 80
[18:02:11.650] <TB2> INFO: Expecting 41600 events.
[18:02:15.646] <TB2> INFO: 41600 events read in total (3404ms).
[18:02:15.647] <TB2> INFO: Test took 4273ms.
[18:02:15.650] <TB2> INFO: scanning low vcal = 90
[18:02:15.926] <TB2> INFO: Expecting 41600 events.
[18:02:19.874] <TB2> INFO: 41600 events read in total (3356ms).
[18:02:19.875] <TB2> INFO: Test took 4225ms.
[18:02:19.878] <TB2> INFO: scanning low vcal = 100
[18:02:20.154] <TB2> INFO: Expecting 41600 events.
[18:02:24.132] <TB2> INFO: 41600 events read in total (3386ms).
[18:02:24.133] <TB2> INFO: Test took 4254ms.
[18:02:24.136] <TB2> INFO: scanning low vcal = 110
[18:02:24.413] <TB2> INFO: Expecting 41600 events.
[18:02:28.381] <TB2> INFO: 41600 events read in total (3377ms).
[18:02:28.382] <TB2> INFO: Test took 4246ms.
[18:02:28.385] <TB2> INFO: scanning low vcal = 120
[18:02:28.687] <TB2> INFO: Expecting 41600 events.
[18:02:32.691] <TB2> INFO: 41600 events read in total (3412ms).
[18:02:32.691] <TB2> INFO: Test took 4306ms.
[18:02:32.694] <TB2> INFO: scanning low vcal = 130
[18:02:32.971] <TB2> INFO: Expecting 41600 events.
[18:02:37.029] <TB2> INFO: 41600 events read in total (3466ms).
[18:02:37.030] <TB2> INFO: Test took 4336ms.
[18:02:37.033] <TB2> INFO: scanning low vcal = 140
[18:02:37.310] <TB2> INFO: Expecting 41600 events.
[18:02:41.296] <TB2> INFO: 41600 events read in total (3395ms).
[18:02:41.296] <TB2> INFO: Test took 4263ms.
[18:02:41.299] <TB2> INFO: scanning low vcal = 150
[18:02:41.576] <TB2> INFO: Expecting 41600 events.
[18:02:45.543] <TB2> INFO: 41600 events read in total (3375ms).
[18:02:45.543] <TB2> INFO: Test took 4244ms.
[18:02:45.546] <TB2> INFO: scanning low vcal = 160
[18:02:45.848] <TB2> INFO: Expecting 41600 events.
[18:02:49.848] <TB2> INFO: 41600 events read in total (3408ms).
[18:02:49.848] <TB2> INFO: Test took 4301ms.
[18:02:49.851] <TB2> INFO: scanning low vcal = 170
[18:02:50.127] <TB2> INFO: Expecting 41600 events.
[18:02:54.151] <TB2> INFO: 41600 events read in total (3432ms).
[18:02:54.152] <TB2> INFO: Test took 4301ms.
[18:02:54.157] <TB2> INFO: scanning low vcal = 180
[18:02:54.432] <TB2> INFO: Expecting 41600 events.
[18:02:58.506] <TB2> INFO: 41600 events read in total (3483ms).
[18:02:58.506] <TB2> INFO: Test took 4348ms.
[18:02:58.510] <TB2> INFO: scanning low vcal = 190
[18:02:58.837] <TB2> INFO: Expecting 41600 events.
[18:03:02.842] <TB2> INFO: 41600 events read in total (3413ms).
[18:03:02.843] <TB2> INFO: Test took 4333ms.
[18:03:02.846] <TB2> INFO: scanning low vcal = 200
[18:03:03.122] <TB2> INFO: Expecting 41600 events.
[18:03:07.092] <TB2> INFO: 41600 events read in total (3379ms).
[18:03:07.093] <TB2> INFO: Test took 4247ms.
[18:03:07.096] <TB2> INFO: scanning low vcal = 210
[18:03:07.373] <TB2> INFO: Expecting 41600 events.
[18:03:11.401] <TB2> INFO: 41600 events read in total (3436ms).
[18:03:11.402] <TB2> INFO: Test took 4306ms.
[18:03:11.406] <TB2> INFO: scanning low vcal = 220
[18:03:11.701] <TB2> INFO: Expecting 41600 events.
[18:03:15.715] <TB2> INFO: 41600 events read in total (3423ms).
[18:03:15.716] <TB2> INFO: Test took 4310ms.
[18:03:15.720] <TB2> INFO: scanning low vcal = 230
[18:03:15.996] <TB2> INFO: Expecting 41600 events.
[18:03:19.994] <TB2> INFO: 41600 events read in total (3407ms).
[18:03:19.995] <TB2> INFO: Test took 4275ms.
[18:03:19.998] <TB2> INFO: scanning low vcal = 240
[18:03:20.288] <TB2> INFO: Expecting 41600 events.
[18:03:24.275] <TB2> INFO: 41600 events read in total (3396ms).
[18:03:24.275] <TB2> INFO: Test took 4277ms.
[18:03:24.278] <TB2> INFO: scanning low vcal = 250
[18:03:24.555] <TB2> INFO: Expecting 41600 events.
[18:03:28.597] <TB2> INFO: 41600 events read in total (3450ms).
[18:03:28.598] <TB2> INFO: Test took 4319ms.
[18:03:28.602] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[18:03:28.911] <TB2> INFO: Expecting 41600 events.
[18:03:32.891] <TB2> INFO: 41600 events read in total (3388ms).
[18:03:32.892] <TB2> INFO: Test took 4289ms.
[18:03:32.895] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[18:03:33.172] <TB2> INFO: Expecting 41600 events.
[18:03:37.143] <TB2> INFO: 41600 events read in total (3380ms).
[18:03:37.144] <TB2> INFO: Test took 4249ms.
[18:03:37.147] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[18:03:37.423] <TB2> INFO: Expecting 41600 events.
[18:03:41.479] <TB2> INFO: 41600 events read in total (3464ms).
[18:03:41.480] <TB2> INFO: Test took 4333ms.
[18:03:41.484] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[18:03:41.799] <TB2> INFO: Expecting 41600 events.
[18:03:45.763] <TB2> INFO: 41600 events read in total (3372ms).
[18:03:45.764] <TB2> INFO: Test took 4280ms.
[18:03:45.767] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[18:03:46.044] <TB2> INFO: Expecting 41600 events.
[18:03:49.003] <TB2> INFO: 41600 events read in total (3367ms).
[18:03:50.004] <TB2> INFO: Test took 4237ms.
[18:03:50.412] <TB2> INFO: PixTestGainPedestal::measure() done
[18:04:22.721] <TB2> INFO: PixTestGainPedestal::fit() done
[18:04:22.721] <TB2> INFO: non-linearity mean: 0.964 0.967 0.973 0.916 0.965 0.980 0.977 0.938 0.915 0.963 0.918 0.948 0.973 0.978 0.948 0.980
[18:04:22.721] <TB2> INFO: non-linearity RMS: 0.022 0.016 0.007 0.134 0.020 0.006 0.005 0.155 0.093 0.031 0.144 0.159 0.005 0.169 0.042 0.004
[18:04:22.721] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr35_C0.dat
[18:04:22.735] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr35_C1.dat
[18:04:22.748] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr35_C2.dat
[18:04:22.762] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr35_C3.dat
[18:04:22.775] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr35_C4.dat
[18:04:22.789] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr35_C5.dat
[18:04:22.802] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr35_C6.dat
[18:04:22.815] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr35_C7.dat
[18:04:22.829] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr35_C8.dat
[18:04:22.842] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr35_C9.dat
[18:04:22.855] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr35_C10.dat
[18:04:22.869] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr35_C11.dat
[18:04:22.882] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr35_C12.dat
[18:04:22.896] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr35_C13.dat
[18:04:22.909] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr35_C14.dat
[18:04:22.923] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//003_Fulltest_p17//phCalibrationFitErr35_C15.dat
[18:04:22.936] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 160 seconds
[18:04:22.936] <TB2> INFO: Decoding statistics:
[18:04:22.936] <TB2> INFO: General information:
[18:04:22.936] <TB2> INFO: 16bit words read: 3315552
[18:04:22.936] <TB2> INFO: valid events total: 332800
[18:04:22.936] <TB2> INFO: empty events: 184
[18:04:22.936] <TB2> INFO: valid events with pixels: 332616
[18:04:22.936] <TB2> INFO: valid pixel hits: 659376
[18:04:22.936] <TB2> INFO: Event errors: 0
[18:04:22.936] <TB2> INFO: start marker: 0
[18:04:22.936] <TB2> INFO: stop marker: 0
[18:04:22.936] <TB2> INFO: overflow: 0
[18:04:22.936] <TB2> INFO: invalid 5bit words: 0
[18:04:22.936] <TB2> INFO: invalid XOR eye diagram: 0
[18:04:22.937] <TB2> INFO: frame (failed synchr.): 0
[18:04:22.937] <TB2> INFO: idle data (no TBM trl): 0
[18:04:22.937] <TB2> INFO: no data (only TBM hdr): 0
[18:04:22.937] <TB2> INFO: TBM errors: 0
[18:04:22.937] <TB2> INFO: flawed TBM headers: 0
[18:04:22.937] <TB2> INFO: flawed TBM trailers: 0
[18:04:22.937] <TB2> INFO: event ID mismatches: 0
[18:04:22.937] <TB2> INFO: ROC errors: 0
[18:04:22.937] <TB2> INFO: missing ROC header(s): 0
[18:04:22.937] <TB2> INFO: misplaced readback start: 0
[18:04:22.937] <TB2> INFO: Pixel decoding errors: 0
[18:04:22.937] <TB2> INFO: pixel data incomplete: 0
[18:04:22.937] <TB2> INFO: pixel address: 0
[18:04:22.937] <TB2> INFO: pulse height fill bit: 0
[18:04:22.937] <TB2> INFO: buffer corruption: 0
[18:04:22.953] <TB2> INFO: Decoding statistics:
[18:04:22.953] <TB2> INFO: General information:
[18:04:22.953] <TB2> INFO: 16bit words read: 3444970
[18:04:22.953] <TB2> INFO: valid events total: 353536
[18:04:22.953] <TB2> INFO: empty events: 18419
[18:04:22.953] <TB2> INFO: valid events with pixels: 335117
[18:04:22.953] <TB2> INFO: valid pixel hits: 661877
[18:04:22.953] <TB2> INFO: Event errors: 0
[18:04:22.954] <TB2> INFO: start marker: 0
[18:04:22.954] <TB2> INFO: stop marker: 0
[18:04:22.954] <TB2> INFO: overflow: 0
[18:04:22.954] <TB2> INFO: invalid 5bit words: 0
[18:04:22.954] <TB2> INFO: invalid XOR eye diagram: 0
[18:04:22.954] <TB2> INFO: frame (failed synchr.): 0
[18:04:22.954] <TB2> INFO: idle data (no TBM trl): 0
[18:04:22.954] <TB2> INFO: no data (only TBM hdr): 0
[18:04:22.954] <TB2> INFO: TBM errors: 0
[18:04:22.954] <TB2> INFO: flawed TBM headers: 0
[18:04:22.954] <TB2> INFO: flawed TBM trailers: 0
[18:04:22.954] <TB2> INFO: event ID mismatches: 0
[18:04:22.954] <TB2> INFO: ROC errors: 0
[18:04:22.954] <TB2> INFO: missing ROC header(s): 0
[18:04:22.954] <TB2> INFO: misplaced readback start: 0
[18:04:22.954] <TB2> INFO: Pixel decoding errors: 0
[18:04:22.954] <TB2> INFO: pixel data incomplete: 0
[18:04:22.954] <TB2> INFO: pixel address: 0
[18:04:22.954] <TB2> INFO: pulse height fill bit: 0
[18:04:22.954] <TB2> INFO: buffer corruption: 0
[18:04:22.954] <TB2> INFO: enter test to run
[18:04:22.954] <TB2> INFO: test: exit no parameter change
[18:04:23.074] <TB2> QUIET: Connection to board 149 closed.
[18:04:23.075] <TB2> INFO: pXar: this is the end, my friend