[15:04:46.214] <TB2> INFO: *** Welcome to pxar ***
[15:04:46.214] <TB2> INFO: *** Today: 2016/10/19
[15:04:46.221] <TB2> INFO: *** Version: c8ba-dirty
[15:04:46.221] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C15.dat
[15:04:46.222] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//tbmParameters_C1b.dat
[15:04:46.222] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//defaultMaskFile.dat
[15:04:46.222] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters_C15.dat
[15:04:46.285] <TB2> INFO: clk: 4
[15:04:46.285] <TB2> INFO: ctr: 4
[15:04:46.285] <TB2> INFO: sda: 19
[15:04:46.285] <TB2> INFO: tin: 9
[15:04:46.285] <TB2> INFO: level: 15
[15:04:46.285] <TB2> INFO: triggerdelay: 0
[15:04:46.285] <TB2> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[15:04:46.285] <TB2> INFO: Log level: INFO
[15:04:46.293] <TB2> INFO: Found DTB DTB_WWXUD2
[15:04:46.301] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[15:04:46.303] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[15:04:46.304] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[15:04:47.847] <TB2> INFO: DUT info:
[15:04:47.848] <TB2> INFO: The DUT currently contains the following objects:
[15:04:47.848] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[15:04:47.848] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:04:47.848] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:04:47.848] <TB2> INFO: TBM Core alpha (2): 7 registers set
[15:04:47.848] <TB2> INFO: TBM Core beta (3): 7 registers set
[15:04:47.848] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[15:04:47.848] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[15:04:47.848] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[15:04:47.848] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[15:04:47.848] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[15:04:47.848] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[15:04:47.848] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[15:04:47.848] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[15:04:47.848] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[15:04:47.848] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[15:04:47.848] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[15:04:47.848] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[15:04:47.848] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[15:04:47.848] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[15:04:47.848] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[15:04:47.848] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[15:04:47.848] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[15:04:48.249] <TB2> INFO: enter 'restricted' command line mode
[15:04:48.249] <TB2> INFO: enter test to run
[15:04:48.249] <TB2> INFO: test: pretest no parameter change
[15:04:48.249] <TB2> INFO: running: pretest
[15:04:48.256] <TB2> INFO: ######################################################################
[15:04:48.256] <TB2> INFO: PixTestPretest::doTest()
[15:04:48.256] <TB2> INFO: ######################################################################
[15:04:48.257] <TB2> INFO: ----------------------------------------------------------------------
[15:04:48.257] <TB2> INFO: PixTestPretest::programROC()
[15:04:48.257] <TB2> INFO: ----------------------------------------------------------------------
[15:05:06.271] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[15:05:06.271] <TB2> INFO: IA differences per ROC: 21.7 16.1 16.9 16.1 16.1 20.1 17.7 19.3 20.1 17.7 16.1 17.7 16.1 16.9 19.3 19.3
[15:05:06.337] <TB2> INFO: ----------------------------------------------------------------------
[15:05:06.337] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[15:05:06.337] <TB2> INFO: ----------------------------------------------------------------------
[15:05:13.946] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 386.7 mA = 24.1687 mA/ROC
[15:05:13.946] <TB2> INFO: i(loss) [mA/ROC]: 20.1 20.1 20.1 20.1 19.3 20.1 20.1 20.1 19.3 20.1 20.1 20.1 20.1 20.1 20.1 19.3
[15:05:13.981] <TB2> INFO: ----------------------------------------------------------------------
[15:05:13.981] <TB2> INFO: PixTestPretest::findTiming()
[15:05:13.981] <TB2> INFO: ----------------------------------------------------------------------
[15:05:13.981] <TB2> INFO: PixTestCmd::init()

[15:05:46.493] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[15:05:46.493] <TB2> INFO: (success/tries = 100/100), width = 4
[15:05:47.996] <TB2> INFO: ----------------------------------------------------------------------
[15:05:47.996] <TB2> INFO: PixTestPretest::findWorkingPixel()
[15:05:47.996] <TB2> INFO: ----------------------------------------------------------------------
[15:05:48.088] <TB2> INFO: Expecting 231680 events.
[15:05:57.942] <TB2> INFO: 231680 events read in total (9262ms).
[15:05:57.950] <TB2> INFO: Test took 9951ms.
[15:05:58.200] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[15:05:58.234] <TB2> INFO: ----------------------------------------------------------------------
[15:05:58.234] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[15:05:58.234] <TB2> INFO: ----------------------------------------------------------------------
[15:05:58.329] <TB2> INFO: Expecting 231680 events.
[15:06:08.283] <TB2> INFO: 231680 events read in total (9363ms).
[15:06:08.293] <TB2> INFO: Test took 10053ms.
[15:06:08.557] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[15:06:08.558] <TB2> INFO: CalDel: 109 109 91 93 101 89 92 96 95 105 102 109 92 105 103 87
[15:06:08.558] <TB2> INFO: VthrComp: 51 52 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[15:06:08.561] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C0.dat
[15:06:08.561] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C1.dat
[15:06:08.561] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C2.dat
[15:06:08.562] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C3.dat
[15:06:08.562] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C4.dat
[15:06:08.562] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C5.dat
[15:06:08.562] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C6.dat
[15:06:08.563] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C7.dat
[15:06:08.563] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C8.dat
[15:06:08.563] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C9.dat
[15:06:08.563] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C10.dat
[15:06:08.563] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C11.dat
[15:06:08.563] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C12.dat
[15:06:08.563] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C13.dat
[15:06:08.564] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C14.dat
[15:06:08.564] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters_C15.dat
[15:06:08.564] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//tbmParameters_C0a.dat
[15:06:08.564] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//tbmParameters_C0b.dat
[15:06:08.564] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//tbmParameters_C1a.dat
[15:06:08.564] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//tbmParameters_C1b.dat
[15:06:08.564] <TB2> INFO: PixTestPretest::doTest() done, duration: 80 seconds
[15:06:08.633] <TB2> INFO: enter test to run
[15:06:08.633] <TB2> INFO: test: FullTest no parameter change
[15:06:08.633] <TB2> INFO: running: fulltest
[15:06:08.633] <TB2> INFO: ######################################################################
[15:06:08.633] <TB2> INFO: PixTestFullTest::doTest()
[15:06:08.633] <TB2> INFO: ######################################################################
[15:06:08.634] <TB2> INFO: ######################################################################
[15:06:08.634] <TB2> INFO: PixTestAlive::doTest()
[15:06:08.634] <TB2> INFO: ######################################################################
[15:06:08.635] <TB2> INFO: ----------------------------------------------------------------------
[15:06:08.635] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:06:08.635] <TB2> INFO: ----------------------------------------------------------------------
[15:06:08.877] <TB2> INFO: Expecting 41600 events.
[15:06:12.386] <TB2> INFO: 41600 events read in total (2917ms).
[15:06:12.387] <TB2> INFO: Test took 3750ms.
[15:06:12.624] <TB2> INFO: PixTestAlive::aliveTest() done
[15:06:12.624] <TB2> INFO: number of dead pixels (per ROC): 0 0 3 0 0 2 0 0 1 0 0 0 0 0 0 0
[15:06:12.625] <TB2> INFO: ----------------------------------------------------------------------
[15:06:12.625] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:06:12.625] <TB2> INFO: ----------------------------------------------------------------------
[15:06:12.870] <TB2> INFO: Expecting 41600 events.
[15:06:15.908] <TB2> INFO: 41600 events read in total (2446ms).
[15:06:15.908] <TB2> INFO: Test took 3281ms.
[15:06:15.909] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[15:06:16.147] <TB2> INFO: PixTestAlive::maskTest() done
[15:06:16.148] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:06:16.149] <TB2> INFO: ----------------------------------------------------------------------
[15:06:16.149] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:06:16.149] <TB2> INFO: ----------------------------------------------------------------------
[15:06:16.386] <TB2> INFO: Expecting 41600 events.
[15:06:19.910] <TB2> INFO: 41600 events read in total (2932ms).
[15:06:19.911] <TB2> INFO: Test took 3761ms.
[15:06:20.138] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[15:06:20.138] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:06:20.138] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[15:06:20.138] <TB2> INFO: Decoding statistics:
[15:06:20.138] <TB2> INFO: General information:
[15:06:20.138] <TB2> INFO: 16bit words read: 0
[15:06:20.138] <TB2> INFO: valid events total: 0
[15:06:20.138] <TB2> INFO: empty events: 0
[15:06:20.138] <TB2> INFO: valid events with pixels: 0
[15:06:20.138] <TB2> INFO: valid pixel hits: 0
[15:06:20.138] <TB2> INFO: Event errors: 0
[15:06:20.138] <TB2> INFO: start marker: 0
[15:06:20.138] <TB2> INFO: stop marker: 0
[15:06:20.138] <TB2> INFO: overflow: 0
[15:06:20.138] <TB2> INFO: invalid 5bit words: 0
[15:06:20.138] <TB2> INFO: invalid XOR eye diagram: 0
[15:06:20.138] <TB2> INFO: frame (failed synchr.): 0
[15:06:20.139] <TB2> INFO: idle data (no TBM trl): 0
[15:06:20.139] <TB2> INFO: no data (only TBM hdr): 0
[15:06:20.139] <TB2> INFO: TBM errors: 0
[15:06:20.139] <TB2> INFO: flawed TBM headers: 0
[15:06:20.139] <TB2> INFO: flawed TBM trailers: 0
[15:06:20.139] <TB2> INFO: event ID mismatches: 0
[15:06:20.139] <TB2> INFO: ROC errors: 0
[15:06:20.139] <TB2> INFO: missing ROC header(s): 0
[15:06:20.139] <TB2> INFO: misplaced readback start: 0
[15:06:20.139] <TB2> INFO: Pixel decoding errors: 0
[15:06:20.139] <TB2> INFO: pixel data incomplete: 0
[15:06:20.139] <TB2> INFO: pixel address: 0
[15:06:20.139] <TB2> INFO: pulse height fill bit: 0
[15:06:20.139] <TB2> INFO: buffer corruption: 0
[15:06:20.143] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C15.dat
[15:06:20.143] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[15:06:20.143] <TB2> INFO: ######################################################################
[15:06:20.143] <TB2> INFO: PixTestReadback::doTest()
[15:06:20.143] <TB2> INFO: ######################################################################
[15:06:20.143] <TB2> INFO: ----------------------------------------------------------------------
[15:06:20.143] <TB2> INFO: PixTestReadback::CalibrateVd()
[15:06:20.143] <TB2> INFO: ----------------------------------------------------------------------
[15:06:30.115] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C0.dat
[15:06:30.115] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C1.dat
[15:06:30.115] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C2.dat
[15:06:30.115] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C3.dat
[15:06:30.115] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C4.dat
[15:06:30.115] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C5.dat
[15:06:30.116] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C6.dat
[15:06:30.116] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C7.dat
[15:06:30.116] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C8.dat
[15:06:30.116] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C9.dat
[15:06:30.116] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C10.dat
[15:06:30.116] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C11.dat
[15:06:30.116] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C12.dat
[15:06:30.116] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C13.dat
[15:06:30.116] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C14.dat
[15:06:30.116] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C15.dat
[15:06:30.146] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[15:06:30.146] <TB2> INFO: ----------------------------------------------------------------------
[15:06:30.146] <TB2> INFO: PixTestReadback::CalibrateVa()
[15:06:30.146] <TB2> INFO: ----------------------------------------------------------------------
[15:06:40.079] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C0.dat
[15:06:40.080] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C1.dat
[15:06:40.080] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C2.dat
[15:06:40.080] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C3.dat
[15:06:40.080] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C4.dat
[15:06:40.080] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C5.dat
[15:06:40.080] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C6.dat
[15:06:40.080] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C7.dat
[15:06:40.080] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C8.dat
[15:06:40.080] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C9.dat
[15:06:40.080] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C10.dat
[15:06:40.080] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C11.dat
[15:06:40.080] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C12.dat
[15:06:40.080] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C13.dat
[15:06:40.080] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C14.dat
[15:06:40.080] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C15.dat
[15:06:40.116] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[15:06:40.116] <TB2> INFO: ----------------------------------------------------------------------
[15:06:40.116] <TB2> INFO: PixTestReadback::readbackVbg()
[15:06:40.116] <TB2> INFO: ----------------------------------------------------------------------
[15:06:47.791] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[15:06:47.791] <TB2> INFO: ----------------------------------------------------------------------
[15:06:47.791] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[15:06:47.791] <TB2> INFO: ----------------------------------------------------------------------
[15:06:47.791] <TB2> INFO: Vbg will be calibrated using Vd calibration
[15:06:47.791] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 140calibrated Vbg = 1.18546 :::*/*/*/*/
[15:06:47.791] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 169.2calibrated Vbg = 1.18392 :::*/*/*/*/
[15:06:47.791] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 158.1calibrated Vbg = 1.17402 :::*/*/*/*/
[15:06:47.791] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 156.8calibrated Vbg = 1.17168 :::*/*/*/*/
[15:06:47.791] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 166.1calibrated Vbg = 1.17614 :::*/*/*/*/
[15:06:47.791] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 150.9calibrated Vbg = 1.18406 :::*/*/*/*/
[15:06:47.791] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 143.1calibrated Vbg = 1.18459 :::*/*/*/*/
[15:06:47.791] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 152.8calibrated Vbg = 1.18928 :::*/*/*/*/
[15:06:47.791] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 160.8calibrated Vbg = 1.18216 :::*/*/*/*/
[15:06:47.791] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 159.7calibrated Vbg = 1.17406 :::*/*/*/*/
[15:06:47.792] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 162calibrated Vbg = 1.1745 :::*/*/*/*/
[15:06:47.792] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 161.5calibrated Vbg = 1.16938 :::*/*/*/*/
[15:06:47.792] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 153.9calibrated Vbg = 1.1737 :::*/*/*/*/
[15:06:47.792] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 159.9calibrated Vbg = 1.1789 :::*/*/*/*/
[15:06:47.792] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 162.8calibrated Vbg = 1.1822 :::*/*/*/*/
[15:06:47.792] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 162.4calibrated Vbg = 1.18162 :::*/*/*/*/
[15:06:47.795] <TB2> INFO: ----------------------------------------------------------------------
[15:06:47.795] <TB2> INFO: PixTestReadback::CalibrateIa()
[15:06:47.795] <TB2> INFO: ----------------------------------------------------------------------
[15:09:28.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C0.dat
[15:09:28.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C1.dat
[15:09:28.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C2.dat
[15:09:28.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C3.dat
[15:09:28.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C4.dat
[15:09:28.625] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C5.dat
[15:09:28.625] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C6.dat
[15:09:28.625] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C7.dat
[15:09:28.625] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C8.dat
[15:09:28.625] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C9.dat
[15:09:28.625] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C10.dat
[15:09:28.625] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C11.dat
[15:09:28.625] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C12.dat
[15:09:28.625] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C13.dat
[15:09:28.625] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C14.dat
[15:09:28.625] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//readbackCal_C15.dat
[15:09:28.655] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[15:09:28.658] <TB2> INFO: PixTestReadback::doTest() done
[15:09:28.658] <TB2> INFO: Decoding statistics:
[15:09:28.658] <TB2> INFO: General information:
[15:09:28.658] <TB2> INFO: 16bit words read: 1536
[15:09:28.658] <TB2> INFO: valid events total: 256
[15:09:28.658] <TB2> INFO: empty events: 256
[15:09:28.658] <TB2> INFO: valid events with pixels: 0
[15:09:28.658] <TB2> INFO: valid pixel hits: 0
[15:09:28.658] <TB2> INFO: Event errors: 0
[15:09:28.658] <TB2> INFO: start marker: 0
[15:09:28.658] <TB2> INFO: stop marker: 0
[15:09:28.658] <TB2> INFO: overflow: 0
[15:09:28.658] <TB2> INFO: invalid 5bit words: 0
[15:09:28.658] <TB2> INFO: invalid XOR eye diagram: 0
[15:09:28.658] <TB2> INFO: frame (failed synchr.): 0
[15:09:28.658] <TB2> INFO: idle data (no TBM trl): 0
[15:09:28.658] <TB2> INFO: no data (only TBM hdr): 0
[15:09:28.658] <TB2> INFO: TBM errors: 0
[15:09:28.658] <TB2> INFO: flawed TBM headers: 0
[15:09:28.658] <TB2> INFO: flawed TBM trailers: 0
[15:09:28.658] <TB2> INFO: event ID mismatches: 0
[15:09:28.658] <TB2> INFO: ROC errors: 0
[15:09:28.658] <TB2> INFO: missing ROC header(s): 0
[15:09:28.658] <TB2> INFO: misplaced readback start: 0
[15:09:28.658] <TB2> INFO: Pixel decoding errors: 0
[15:09:28.658] <TB2> INFO: pixel data incomplete: 0
[15:09:28.658] <TB2> INFO: pixel address: 0
[15:09:28.658] <TB2> INFO: pulse height fill bit: 0
[15:09:28.659] <TB2> INFO: buffer corruption: 0
[15:09:28.710] <TB2> INFO: ######################################################################
[15:09:28.710] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[15:09:28.710] <TB2> INFO: ######################################################################
[15:09:28.712] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[15:09:28.725] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:09:28.725] <TB2> INFO: run 1 of 1
[15:09:28.960] <TB2> INFO: Expecting 3120000 events.
[15:09:59.724] <TB2> INFO: 661295 events read in total (30172ms).
[15:10:29.769] <TB2> INFO: 1315920 events read in total (60217ms).











[15:10:59.666] <TB2> INFO: 1964740 events read in total (90114ms).











[15:11:29.964] <TB2> INFO: 2612595 events read in total (120412ms).











[15:11:53.201] <TB2> INFO: 3120000 events read in total (143649ms).
[15:11:53.282] <TB2> INFO: Test took 144558ms.
[15:12:19.398] <TB2> INFO: PixTestBBMap::doTest() done, duration: 170 seconds
[15:12:19.398] <TB2> INFO: number of dead bumps (per ROC): 0 0 2 0 2 2 0 0 0 0 0 4 1 0 0 3
[15:12:19.398] <TB2> INFO: separation cut (per ROC): 104 109 113 112 101 116 99 108 106 111 106 120 108 108 106 117
[15:12:19.398] <TB2> INFO: Decoding statistics:
[15:12:19.398] <TB2> INFO: General information:
[15:12:19.398] <TB2> INFO: 16bit words read: 0
[15:12:19.398] <TB2> INFO: valid events total: 0
[15:12:19.398] <TB2> INFO: empty events: 0
[15:12:19.398] <TB2> INFO: valid events with pixels: 0
[15:12:19.398] <TB2> INFO: valid pixel hits: 0
[15:12:19.398] <TB2> INFO: Event errors: 0
[15:12:19.398] <TB2> INFO: start marker: 0
[15:12:19.398] <TB2> INFO: stop marker: 0
[15:12:19.398] <TB2> INFO: overflow: 0
[15:12:19.398] <TB2> INFO: invalid 5bit words: 0
[15:12:19.398] <TB2> INFO: invalid XOR eye diagram: 0
[15:12:19.398] <TB2> INFO: frame (failed synchr.): 0
[15:12:19.398] <TB2> INFO: idle data (no TBM trl): 0
[15:12:19.398] <TB2> INFO: no data (only TBM hdr): 0
[15:12:19.398] <TB2> INFO: TBM errors: 0
[15:12:19.398] <TB2> INFO: flawed TBM headers: 0
[15:12:19.398] <TB2> INFO: flawed TBM trailers: 0
[15:12:19.398] <TB2> INFO: event ID mismatches: 0
[15:12:19.398] <TB2> INFO: ROC errors: 0
[15:12:19.398] <TB2> INFO: missing ROC header(s): 0
[15:12:19.398] <TB2> INFO: misplaced readback start: 0
[15:12:19.398] <TB2> INFO: Pixel decoding errors: 0
[15:12:19.398] <TB2> INFO: pixel data incomplete: 0
[15:12:19.398] <TB2> INFO: pixel address: 0
[15:12:19.398] <TB2> INFO: pulse height fill bit: 0
[15:12:19.398] <TB2> INFO: buffer corruption: 0
[15:12:19.448] <TB2> INFO: ######################################################################
[15:12:19.448] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[15:12:19.448] <TB2> INFO: ######################################################################
[15:12:19.448] <TB2> INFO: ----------------------------------------------------------------------
[15:12:19.448] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[15:12:19.448] <TB2> INFO: ----------------------------------------------------------------------
[15:12:19.448] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[15:12:19.463] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[15:12:19.463] <TB2> INFO: run 1 of 1
[15:12:19.788] <TB2> INFO: Expecting 36608000 events.
[15:12:43.347] <TB2> INFO: 668050 events read in total (22967ms).
[15:13:05.878] <TB2> INFO: 1325400 events read in total (45498ms).
[15:13:28.887] <TB2> INFO: 1981200 events read in total (68507ms).
[15:13:51.628] <TB2> INFO: 2639300 events read in total (91248ms).
[15:14:14.401] <TB2> INFO: 3296350 events read in total (114021ms).
[15:14:37.493] <TB2> INFO: 3951800 events read in total (137113ms).
[15:15:00.076] <TB2> INFO: 4605400 events read in total (159696ms).
[15:15:22.989] <TB2> INFO: 5258250 events read in total (182609ms).
[15:15:45.683] <TB2> INFO: 5910900 events read in total (205303ms).
[15:16:08.187] <TB2> INFO: 6562700 events read in total (227807ms).
[15:16:30.899] <TB2> INFO: 7214900 events read in total (250519ms).
[15:16:53.722] <TB2> INFO: 7865400 events read in total (273342ms).
[15:17:16.575] <TB2> INFO: 8518550 events read in total (296196ms).
[15:17:39.491] <TB2> INFO: 9170500 events read in total (319111ms).
[15:18:02.332] <TB2> INFO: 9822900 events read in total (341952ms).
[15:18:25.153] <TB2> INFO: 10471700 events read in total (364773ms).
[15:18:47.692] <TB2> INFO: 11123000 events read in total (387312ms).
[15:19:10.478] <TB2> INFO: 11772900 events read in total (410098ms).
[15:19:33.251] <TB2> INFO: 12423550 events read in total (432871ms).
[15:19:56.182] <TB2> INFO: 13074100 events read in total (455802ms).
[15:20:18.882] <TB2> INFO: 13725200 events read in total (478502ms).
[15:20:41.488] <TB2> INFO: 14375000 events read in total (501108ms).
[15:21:04.282] <TB2> INFO: 15025050 events read in total (523902ms).
[15:21:26.829] <TB2> INFO: 15672750 events read in total (546449ms).
[15:21:49.157] <TB2> INFO: 16321100 events read in total (568777ms).
[15:22:12.005] <TB2> INFO: 16970850 events read in total (591625ms).
[15:22:34.629] <TB2> INFO: 17617500 events read in total (614249ms).
[15:22:57.146] <TB2> INFO: 18266850 events read in total (636766ms).
[15:23:19.944] <TB2> INFO: 18912950 events read in total (659564ms).
[15:23:42.814] <TB2> INFO: 19561450 events read in total (682434ms).
[15:24:05.409] <TB2> INFO: 20207600 events read in total (705029ms).
[15:24:28.018] <TB2> INFO: 20852900 events read in total (727638ms).
[15:24:50.630] <TB2> INFO: 21498350 events read in total (750250ms).
[15:25:13.562] <TB2> INFO: 22144450 events read in total (773182ms).
[15:25:36.207] <TB2> INFO: 22789100 events read in total (795827ms).
[15:25:58.693] <TB2> INFO: 23433450 events read in total (818313ms).
[15:26:21.060] <TB2> INFO: 24077450 events read in total (840680ms).
[15:26:43.557] <TB2> INFO: 24721050 events read in total (863177ms).
[15:27:06.145] <TB2> INFO: 25366900 events read in total (885765ms).
[15:27:28.735] <TB2> INFO: 26010650 events read in total (908355ms).
[15:27:51.299] <TB2> INFO: 26655150 events read in total (930919ms).
[15:28:13.894] <TB2> INFO: 27297800 events read in total (953514ms).
[15:28:36.771] <TB2> INFO: 27941400 events read in total (976391ms).
[15:28:59.425] <TB2> INFO: 28586000 events read in total (999045ms).
[15:29:21.985] <TB2> INFO: 29229350 events read in total (1021605ms).
[15:29:44.255] <TB2> INFO: 29872800 events read in total (1043875ms).
[15:30:06.780] <TB2> INFO: 30516050 events read in total (1066400ms).
[15:30:29.344] <TB2> INFO: 31158950 events read in total (1088964ms).
[15:30:51.972] <TB2> INFO: 31802200 events read in total (1111592ms).
[15:31:14.621] <TB2> INFO: 32446950 events read in total (1134241ms).
[15:31:37.214] <TB2> INFO: 33088000 events read in total (1156834ms).
[15:31:59.828] <TB2> INFO: 33731600 events read in total (1179448ms).
[15:32:22.233] <TB2> INFO: 34376500 events read in total (1201853ms).
[15:32:44.671] <TB2> INFO: 35020700 events read in total (1224291ms).
[15:33:07.250] <TB2> INFO: 35665150 events read in total (1246870ms).
[15:33:29.667] <TB2> INFO: 36316550 events read in total (1269287ms).
[15:33:39.698] <TB2> INFO: 36608000 events read in total (1279318ms).
[15:33:39.784] <TB2> INFO: Test took 1280321ms.
[15:33:40.236] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:33:41.930] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:33:43.622] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:33:45.510] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:33:47.474] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:33:49.962] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:33:52.080] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:33:54.048] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:33:56.149] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:33:58.114] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:34:00.167] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:34:02.197] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:34:04.211] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:34:06.171] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:34:07.711] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:34:09.541] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[15:34:11.114] <TB2> INFO: PixTestScurves::scurves() done
[15:34:11.114] <TB2> INFO: Vcal mean: 100.27 116.02 117.37 117.52 106.04 118.45 95.41 111.77 112.81 120.23 112.34 111.63 109.18 107.26 119.72 118.00
[15:34:11.114] <TB2> INFO: Vcal RMS: 4.74 6.08 6.85 5.70 5.76 6.12 5.05 4.96 5.08 6.49 4.79 5.17 4.90 4.95 6.02 5.92
[15:34:11.114] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1311 seconds
[15:34:11.114] <TB2> INFO: Decoding statistics:
[15:34:11.114] <TB2> INFO: General information:
[15:34:11.114] <TB2> INFO: 16bit words read: 0
[15:34:11.114] <TB2> INFO: valid events total: 0
[15:34:11.114] <TB2> INFO: empty events: 0
[15:34:11.114] <TB2> INFO: valid events with pixels: 0
[15:34:11.114] <TB2> INFO: valid pixel hits: 0
[15:34:11.114] <TB2> INFO: Event errors: 0
[15:34:11.114] <TB2> INFO: start marker: 0
[15:34:11.114] <TB2> INFO: stop marker: 0
[15:34:11.114] <TB2> INFO: overflow: 0
[15:34:11.114] <TB2> INFO: invalid 5bit words: 0
[15:34:11.114] <TB2> INFO: invalid XOR eye diagram: 0
[15:34:11.114] <TB2> INFO: frame (failed synchr.): 0
[15:34:11.114] <TB2> INFO: idle data (no TBM trl): 0
[15:34:11.114] <TB2> INFO: no data (only TBM hdr): 0
[15:34:11.114] <TB2> INFO: TBM errors: 0
[15:34:11.114] <TB2> INFO: flawed TBM headers: 0
[15:34:11.114] <TB2> INFO: flawed TBM trailers: 0
[15:34:11.114] <TB2> INFO: event ID mismatches: 0
[15:34:11.114] <TB2> INFO: ROC errors: 0
[15:34:11.114] <TB2> INFO: missing ROC header(s): 0
[15:34:11.114] <TB2> INFO: misplaced readback start: 0
[15:34:11.114] <TB2> INFO: Pixel decoding errors: 0
[15:34:11.114] <TB2> INFO: pixel data incomplete: 0
[15:34:11.114] <TB2> INFO: pixel address: 0
[15:34:11.114] <TB2> INFO: pulse height fill bit: 0
[15:34:11.114] <TB2> INFO: buffer corruption: 0
[15:34:11.180] <TB2> INFO: ######################################################################
[15:34:11.180] <TB2> INFO: PixTestTrim::doTest()
[15:34:11.180] <TB2> INFO: ######################################################################
[15:34:11.181] <TB2> INFO: ----------------------------------------------------------------------
[15:34:11.181] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[15:34:11.181] <TB2> INFO: ----------------------------------------------------------------------
[15:34:11.237] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[15:34:11.237] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[15:34:11.250] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:34:11.250] <TB2> INFO: run 1 of 1
[15:34:11.486] <TB2> INFO: Expecting 5025280 events.
[15:34:42.291] <TB2> INFO: 816712 events read in total (30208ms).
[15:35:12.156] <TB2> INFO: 1630968 events read in total (60073ms).
[15:35:41.001] <TB2> INFO: 2441112 events read in total (89918ms).
[15:36:12.011] <TB2> INFO: 3247744 events read in total (119928ms).
[15:36:41.737] <TB2> INFO: 4052040 events read in total (149655ms).
[15:37:11.126] <TB2> INFO: 4854192 events read in total (179043ms).
[15:37:18.197] <TB2> INFO: 5025280 events read in total (186114ms).
[15:37:18.261] <TB2> INFO: Test took 187011ms.
[15:37:37.215] <TB2> INFO: ROC 0 VthrComp = 113
[15:37:37.215] <TB2> INFO: ROC 1 VthrComp = 122
[15:37:37.215] <TB2> INFO: ROC 2 VthrComp = 124
[15:37:37.215] <TB2> INFO: ROC 3 VthrComp = 127
[15:37:37.215] <TB2> INFO: ROC 4 VthrComp = 111
[15:37:37.216] <TB2> INFO: ROC 5 VthrComp = 132
[15:37:37.216] <TB2> INFO: ROC 6 VthrComp = 107
[15:37:37.216] <TB2> INFO: ROC 7 VthrComp = 125
[15:37:37.216] <TB2> INFO: ROC 8 VthrComp = 125
[15:37:37.216] <TB2> INFO: ROC 9 VthrComp = 128
[15:37:37.216] <TB2> INFO: ROC 10 VthrComp = 119
[15:37:37.216] <TB2> INFO: ROC 11 VthrComp = 116
[15:37:37.216] <TB2> INFO: ROC 12 VthrComp = 119
[15:37:37.216] <TB2> INFO: ROC 13 VthrComp = 119
[15:37:37.216] <TB2> INFO: ROC 14 VthrComp = 123
[15:37:37.216] <TB2> INFO: ROC 15 VthrComp = 128
[15:37:37.457] <TB2> INFO: Expecting 41600 events.
[15:37:41.156] <TB2> INFO: 41600 events read in total (3106ms).
[15:37:41.157] <TB2> INFO: Test took 3939ms.
[15:37:41.166] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[15:37:41.166] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[15:37:41.177] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:37:41.177] <TB2> INFO: run 1 of 1
[15:37:41.455] <TB2> INFO: Expecting 5025280 events.
[15:38:08.009] <TB2> INFO: 589104 events read in total (25956ms).
[15:38:33.539] <TB2> INFO: 1177160 events read in total (51486ms).
[15:38:59.623] <TB2> INFO: 1764712 events read in total (77570ms).
[15:39:25.532] <TB2> INFO: 2351232 events read in total (103479ms).
[15:39:51.467] <TB2> INFO: 2935784 events read in total (129414ms).
[15:40:17.180] <TB2> INFO: 3519632 events read in total (155127ms).
[15:40:42.857] <TB2> INFO: 4103512 events read in total (180804ms).
[15:41:09.576] <TB2> INFO: 4686944 events read in total (207523ms).
[15:41:24.906] <TB2> INFO: 5025280 events read in total (222853ms).
[15:41:24.001] <TB2> INFO: Test took 223825ms.
[15:41:52.086] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 55.5517 for pixel 1/11 mean/min/max = 44.2537/32.6037/55.9038
[15:41:52.087] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 62.9632 for pixel 2/14 mean/min/max = 46.9439/30.8895/62.9982
[15:41:52.087] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 60.3116 for pixel 0/40 mean/min/max = 45.5081/30.5269/60.4892
[15:41:52.088] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 59.9492 for pixel 7/10 mean/min/max = 45.7003/31.353/60.0476
[15:41:52.088] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 62.6283 for pixel 6/79 mean/min/max = 47.7302/32.6987/62.7618
[15:41:52.089] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 57.9115 for pixel 3/13 mean/min/max = 45.8569/33.5669/58.147
[15:41:52.089] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 58.7756 for pixel 11/2 mean/min/max = 46.5497/34.3016/58.7977
[15:41:52.090] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 58.2619 for pixel 14/0 mean/min/max = 45.2627/31.902/58.6233
[15:41:52.090] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 57.3713 for pixel 10/19 mean/min/max = 44.7084/31.9091/57.5077
[15:41:52.091] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 61.9878 for pixel 20/59 mean/min/max = 46.7458/31.411/62.0807
[15:41:52.091] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 57.3106 for pixel 0/60 mean/min/max = 44.7988/32.0649/57.5327
[15:41:52.092] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 59.5585 for pixel 9/65 mean/min/max = 45.603/31.457/59.7491
[15:41:52.092] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 57.6985 for pixel 0/17 mean/min/max = 44.7203/31.7355/57.705
[15:41:52.092] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 56.0439 for pixel 0/3 mean/min/max = 43.957/31.6004/56.3136
[15:41:52.093] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 61.6767 for pixel 2/4 mean/min/max = 46.7744/31.834/61.7147
[15:41:52.093] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 58.4418 for pixel 1/60 mean/min/max = 45.0753/31.5842/58.5663
[15:41:52.094] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:41:52.182] <TB2> INFO: Expecting 411648 events.
[15:42:01.654] <TB2> INFO: 411648 events read in total (8880ms).
[15:42:01.662] <TB2> INFO: Expecting 411648 events.
[15:42:10.919] <TB2> INFO: 411648 events read in total (8854ms).
[15:42:10.929] <TB2> INFO: Expecting 411648 events.
[15:42:20.263] <TB2> INFO: 411648 events read in total (8931ms).
[15:42:20.279] <TB2> INFO: Expecting 411648 events.
[15:42:29.516] <TB2> INFO: 411648 events read in total (8834ms).
[15:42:29.532] <TB2> INFO: Expecting 411648 events.
[15:42:38.782] <TB2> INFO: 411648 events read in total (8847ms).
[15:42:38.801] <TB2> INFO: Expecting 411648 events.
[15:42:48.115] <TB2> INFO: 411648 events read in total (8911ms).
[15:42:48.138] <TB2> INFO: Expecting 411648 events.
[15:42:57.530] <TB2> INFO: 411648 events read in total (8989ms).
[15:42:57.554] <TB2> INFO: Expecting 411648 events.
[15:43:06.931] <TB2> INFO: 411648 events read in total (8974ms).
[15:43:06.958] <TB2> INFO: Expecting 411648 events.
[15:43:16.308] <TB2> INFO: 411648 events read in total (8946ms).
[15:43:16.338] <TB2> INFO: Expecting 411648 events.
[15:43:25.733] <TB2> INFO: 411648 events read in total (8992ms).
[15:43:25.770] <TB2> INFO: Expecting 411648 events.
[15:43:35.085] <TB2> INFO: 411648 events read in total (8912ms).
[15:43:35.130] <TB2> INFO: Expecting 411648 events.
[15:43:44.514] <TB2> INFO: 411648 events read in total (8980ms).
[15:43:44.552] <TB2> INFO: Expecting 411648 events.
[15:43:53.777] <TB2> INFO: 411648 events read in total (8822ms).
[15:43:53.831] <TB2> INFO: Expecting 411648 events.
[15:44:03.072] <TB2> INFO: 411648 events read in total (8838ms).
[15:44:03.127] <TB2> INFO: Expecting 411648 events.
[15:44:12.454] <TB2> INFO: 411648 events read in total (8924ms).
[15:44:12.501] <TB2> INFO: Expecting 411648 events.
[15:44:21.773] <TB2> INFO: 411648 events read in total (8869ms).
[15:44:21.837] <TB2> INFO: Test took 149743ms.
[15:44:22.652] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[15:44:22.664] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:44:22.664] <TB2> INFO: run 1 of 1
[15:44:22.901] <TB2> INFO: Expecting 5025280 events.
[15:44:49.498] <TB2> INFO: 585128 events read in total (26005ms).
[15:45:15.383] <TB2> INFO: 1168976 events read in total (51890ms).
[15:45:41.293] <TB2> INFO: 1753056 events read in total (77800ms).
[15:46:07.440] <TB2> INFO: 2334560 events read in total (103947ms).
[15:46:33.759] <TB2> INFO: 2917240 events read in total (130266ms).
[15:46:59.907] <TB2> INFO: 3498736 events read in total (156414ms).
[15:47:26.233] <TB2> INFO: 4078936 events read in total (182740ms).
[15:47:52.283] <TB2> INFO: 4658880 events read in total (208790ms).
[15:48:08.993] <TB2> INFO: 5025280 events read in total (225500ms).
[15:48:09.140] <TB2> INFO: Test took 226477ms.
[15:48:35.906] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 5.500000 .. 147.576789
[15:48:36.223] <TB2> INFO: Expecting 208000 events.
[15:48:45.931] <TB2> INFO: 208000 events read in total (9117ms).
[15:48:45.932] <TB2> INFO: Test took 10024ms.
[15:48:45.980] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 5 .. 157 (-1/-1) hits flags = 528 (plus default)
[15:48:45.992] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:48:45.992] <TB2> INFO: run 1 of 1
[15:48:46.270] <TB2> INFO: Expecting 5091840 events.
[15:49:12.774] <TB2> INFO: 578008 events read in total (25913ms).
[15:49:38.549] <TB2> INFO: 1156304 events read in total (51688ms).
[15:50:04.365] <TB2> INFO: 1734720 events read in total (77504ms).
[15:50:30.272] <TB2> INFO: 2313368 events read in total (103411ms).
[15:50:56.117] <TB2> INFO: 2890968 events read in total (129256ms).
[15:51:21.780] <TB2> INFO: 3468408 events read in total (154919ms).
[15:51:47.253] <TB2> INFO: 4046048 events read in total (180392ms).
[15:52:12.568] <TB2> INFO: 4622912 events read in total (205707ms).
[15:52:33.628] <TB2> INFO: 5091840 events read in total (226767ms).
[15:52:33.730] <TB2> INFO: Test took 227738ms.
[15:52:59.587] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.242279 .. 68.152267
[15:52:59.829] <TB2> INFO: Expecting 208000 events.
[15:53:09.609] <TB2> INFO: 208000 events read in total (9189ms).
[15:53:09.611] <TB2> INFO: Test took 10021ms.
[15:53:09.680] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 78 (-1/-1) hits flags = 528 (plus default)
[15:53:09.694] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:53:09.694] <TB2> INFO: run 1 of 1
[15:53:09.973] <TB2> INFO: Expecting 2063360 events.
[15:53:37.197] <TB2> INFO: 604432 events read in total (26632ms).
[15:54:03.322] <TB2> INFO: 1208664 events read in total (52758ms).
[15:54:29.947] <TB2> INFO: 1812352 events read in total (79382ms).
[15:54:40.890] <TB2> INFO: 2063360 events read in total (90325ms).
[15:54:40.942] <TB2> INFO: Test took 91248ms.
[15:54:58.133] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 25.764373 .. 58.781971
[15:54:58.372] <TB2> INFO: Expecting 208000 events.
[15:55:08.270] <TB2> INFO: 208000 events read in total (9306ms).
[15:55:08.270] <TB2> INFO: Test took 10136ms.
[15:55:08.340] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 68 (-1/-1) hits flags = 528 (plus default)
[15:55:08.353] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:55:08.354] <TB2> INFO: run 1 of 1
[15:55:08.632] <TB2> INFO: Expecting 1797120 events.
[15:55:36.105] <TB2> INFO: 628504 events read in total (26882ms).
[15:56:03.180] <TB2> INFO: 1256552 events read in total (53957ms).
[15:56:26.282] <TB2> INFO: 1797120 events read in total (77059ms).
[15:56:26.312] <TB2> INFO: Test took 77959ms.
[15:56:43.270] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 24.750516 .. 47.829186
[15:56:43.519] <TB2> INFO: Expecting 208000 events.
[15:56:53.382] <TB2> INFO: 208000 events read in total (9271ms).
[15:56:53.383] <TB2> INFO: Test took 10112ms.
[15:56:53.432] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 57 (-1/-1) hits flags = 528 (plus default)
[15:56:53.447] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:56:53.447] <TB2> INFO: run 1 of 1
[15:56:53.726] <TB2> INFO: Expecting 1464320 events.
[15:57:22.064] <TB2> INFO: 662784 events read in total (27747ms).
[15:57:49.473] <TB2> INFO: 1325872 events read in total (55156ms).
[15:57:55.621] <TB2> INFO: 1464320 events read in total (61304ms).
[15:57:55.652] <TB2> INFO: Test took 62206ms.
[15:58:08.138] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[15:58:08.139] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[15:58:08.151] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[15:58:08.151] <TB2> INFO: run 1 of 1
[15:58:08.386] <TB2> INFO: Expecting 1364480 events.
[15:58:37.019] <TB2> INFO: 667376 events read in total (28041ms).
[15:59:05.087] <TB2> INFO: 1334088 events read in total (56109ms).
[15:59:06.792] <TB2> INFO: 1364480 events read in total (57814ms).
[15:59:06.826] <TB2> INFO: Test took 58676ms.
[15:59:19.623] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C0.dat
[15:59:19.623] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C1.dat
[15:59:19.623] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C2.dat
[15:59:19.623] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C3.dat
[15:59:19.623] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C4.dat
[15:59:19.623] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C5.dat
[15:59:19.623] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C6.dat
[15:59:19.623] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C7.dat
[15:59:19.623] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C8.dat
[15:59:19.623] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C9.dat
[15:59:19.623] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C10.dat
[15:59:19.623] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C11.dat
[15:59:19.624] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C12.dat
[15:59:19.624] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C13.dat
[15:59:19.624] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C14.dat
[15:59:19.624] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C15.dat
[15:59:19.624] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters35_C0.dat
[15:59:19.629] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters35_C1.dat
[15:59:19.633] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters35_C2.dat
[15:59:19.640] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters35_C3.dat
[15:59:19.645] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters35_C4.dat
[15:59:19.652] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters35_C5.dat
[15:59:19.658] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters35_C6.dat
[15:59:19.664] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters35_C7.dat
[15:59:19.670] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters35_C8.dat
[15:59:19.676] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters35_C9.dat
[15:59:19.682] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters35_C10.dat
[15:59:19.688] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters35_C11.dat
[15:59:19.694] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters35_C12.dat
[15:59:19.700] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters35_C13.dat
[15:59:19.707] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters35_C14.dat
[15:59:19.713] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//trimParameters35_C15.dat
[15:59:19.719] <TB2> INFO: PixTestTrim::trimTest() done
[15:59:19.719] <TB2> INFO: vtrim: 120 143 122 128 141 134 127 125 125 159 122 136 116 112 137 146
[15:59:19.719] <TB2> INFO: vthrcomp: 113 122 124 127 111 132 107 125 125 128 119 116 119 119 123 128
[15:59:19.719] <TB2> INFO: vcal mean: 34.99 34.99 34.94 34.97 34.99 34.95 35.03 34.97 34.94 34.97 34.92 34.98 34.93 34.95 34.94 34.96
[15:59:19.719] <TB2> INFO: vcal RMS: 0.89 1.17 2.44 1.07 0.99 1.18 0.86 1.02 1.11 1.09 0.99 1.02 0.99 0.95 1.10 1.01
[15:59:19.719] <TB2> INFO: bits mean: 9.71 9.49 9.37 9.52 8.86 9.05 8.85 9.44 9.85 9.92 9.50 9.99 9.36 9.80 9.28 10.06
[15:59:19.719] <TB2> INFO: bits RMS: 2.60 2.73 2.90 2.74 2.72 2.61 2.59 2.77 2.61 2.50 2.75 2.58 2.90 2.74 2.75 2.51
[15:59:19.726] <TB2> INFO: ----------------------------------------------------------------------
[15:59:19.726] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[15:59:19.727] <TB2> INFO: ----------------------------------------------------------------------
[15:59:19.729] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[15:59:19.741] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:59:19.741] <TB2> INFO: run 1 of 1
[15:59:19.983] <TB2> INFO: Expecting 4160000 events.
[15:59:51.965] <TB2> INFO: 731725 events read in total (31390ms).
[16:00:23.171] <TB2> INFO: 1456450 events read in total (62596ms).
[16:00:54.529] <TB2> INFO: 2177750 events read in total (93954ms).
[16:01:26.681] <TB2> INFO: 2894930 events read in total (126106ms).
[16:01:57.695] <TB2> INFO: 3609290 events read in total (157120ms).
[16:02:21.806] <TB2> INFO: 4160000 events read in total (181231ms).
[16:02:21.971] <TB2> INFO: Test took 182231ms.
[16:02:46.565] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 197 (-1/-1) hits flags = 528 (plus default)
[16:02:46.578] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:02:46.578] <TB2> INFO: run 1 of 1
[16:02:46.821] <TB2> INFO: Expecting 4118400 events.
[16:03:18.632] <TB2> INFO: 712790 events read in total (31219ms).
[16:03:49.254] <TB2> INFO: 1419545 events read in total (61841ms).
[16:04:19.003] <TB2> INFO: 2122860 events read in total (92590ms).
[16:04:52.044] <TB2> INFO: 2822260 events read in total (124631ms).
[16:05:23.010] <TB2> INFO: 3519155 events read in total (155597ms).
[16:05:49.683] <TB2> INFO: 4118400 events read in total (182270ms).
[16:05:49.790] <TB2> INFO: Test took 183213ms.
[16:06:15.461] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 184 (-1/-1) hits flags = 528 (plus default)
[16:06:15.475] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:06:15.475] <TB2> INFO: run 1 of 1
[16:06:15.758] <TB2> INFO: Expecting 3848000 events.
[16:06:47.803] <TB2> INFO: 730015 events read in total (31454ms).
[16:07:19.932] <TB2> INFO: 1453120 events read in total (63583ms).
[16:07:50.890] <TB2> INFO: 2171945 events read in total (94541ms).
[16:08:21.657] <TB2> INFO: 2886355 events read in total (125308ms).
[16:08:52.895] <TB2> INFO: 3598685 events read in total (156546ms).
[16:09:03.885] <TB2> INFO: 3848000 events read in total (167536ms).
[16:09:03.974] <TB2> INFO: Test took 168500ms.
[16:09:28.482] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 188 (-1/-1) hits flags = 528 (plus default)
[16:09:28.496] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:09:28.496] <TB2> INFO: run 1 of 1
[16:09:28.769] <TB2> INFO: Expecting 3931200 events.
[16:10:00.849] <TB2> INFO: 724605 events read in total (31489ms).
[16:10:32.196] <TB2> INFO: 1442670 events read in total (62836ms).
[16:11:02.637] <TB2> INFO: 2156570 events read in total (93277ms).
[16:11:33.162] <TB2> INFO: 2866225 events read in total (123802ms).
[16:12:04.369] <TB2> INFO: 3573435 events read in total (155009ms).
[16:12:20.207] <TB2> INFO: 3931200 events read in total (170847ms).
[16:12:20.284] <TB2> INFO: Test took 171787ms.
[16:12:45.355] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 184 (-1/-1) hits flags = 528 (plus default)
[16:12:45.368] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:12:45.368] <TB2> INFO: run 1 of 1
[16:12:45.604] <TB2> INFO: Expecting 3848000 events.
[16:13:17.952] <TB2> INFO: 730480 events read in total (31757ms).
[16:13:49.293] <TB2> INFO: 1453835 events read in total (63098ms).
[16:14:20.706] <TB2> INFO: 2172750 events read in total (94511ms).
[16:14:51.130] <TB2> INFO: 2887295 events read in total (124935ms).
[16:15:22.907] <TB2> INFO: 3599880 events read in total (156712ms).
[16:15:34.119] <TB2> INFO: 3848000 events read in total (167924ms).
[16:15:34.207] <TB2> INFO: Test took 168839ms.
[16:15:57.045] <TB2> INFO: PixTestTrim::trimBitTest() done
[16:15:57.046] <TB2> INFO: PixTestTrim::doTest() done, duration: 2505 seconds
[16:15:57.046] <TB2> INFO: Decoding statistics:
[16:15:57.046] <TB2> INFO: General information:
[16:15:57.046] <TB2> INFO: 16bit words read: 0
[16:15:57.046] <TB2> INFO: valid events total: 0
[16:15:57.046] <TB2> INFO: empty events: 0
[16:15:57.046] <TB2> INFO: valid events with pixels: 0
[16:15:57.046] <TB2> INFO: valid pixel hits: 0
[16:15:57.046] <TB2> INFO: Event errors: 0
[16:15:57.046] <TB2> INFO: start marker: 0
[16:15:57.046] <TB2> INFO: stop marker: 0
[16:15:57.046] <TB2> INFO: overflow: 0
[16:15:57.046] <TB2> INFO: invalid 5bit words: 0
[16:15:57.046] <TB2> INFO: invalid XOR eye diagram: 0
[16:15:57.046] <TB2> INFO: frame (failed synchr.): 0
[16:15:57.046] <TB2> INFO: idle data (no TBM trl): 0
[16:15:57.046] <TB2> INFO: no data (only TBM hdr): 0
[16:15:57.046] <TB2> INFO: TBM errors: 0
[16:15:57.046] <TB2> INFO: flawed TBM headers: 0
[16:15:57.046] <TB2> INFO: flawed TBM trailers: 0
[16:15:57.046] <TB2> INFO: event ID mismatches: 0
[16:15:57.046] <TB2> INFO: ROC errors: 0
[16:15:57.046] <TB2> INFO: missing ROC header(s): 0
[16:15:57.047] <TB2> INFO: misplaced readback start: 0
[16:15:57.047] <TB2> INFO: Pixel decoding errors: 0
[16:15:57.047] <TB2> INFO: pixel data incomplete: 0
[16:15:57.047] <TB2> INFO: pixel address: 0
[16:15:57.047] <TB2> INFO: pulse height fill bit: 0
[16:15:57.047] <TB2> INFO: buffer corruption: 0
[16:15:57.671] <TB2> INFO: ######################################################################
[16:15:57.671] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[16:15:57.671] <TB2> INFO: ######################################################################
[16:15:57.908] <TB2> INFO: Expecting 41600 events.
[16:16:01.455] <TB2> INFO: 41600 events read in total (2955ms).
[16:16:01.456] <TB2> INFO: Test took 3784ms.
[16:16:01.897] <TB2> INFO: Expecting 41600 events.
[16:16:05.557] <TB2> INFO: 41600 events read in total (3068ms).
[16:16:05.558] <TB2> INFO: Test took 3898ms.
[16:16:05.863] <TB2> INFO: Expecting 41600 events.
[16:16:09.424] <TB2> INFO: 41600 events read in total (2969ms).
[16:16:09.424] <TB2> INFO: Test took 3842ms.
[16:16:09.714] <TB2> INFO: Expecting 41600 events.
[16:16:13.264] <TB2> INFO: 41600 events read in total (2959ms).
[16:16:13.265] <TB2> INFO: Test took 3817ms.
[16:16:13.554] <TB2> INFO: Expecting 41600 events.
[16:16:17.068] <TB2> INFO: 41600 events read in total (2923ms).
[16:16:17.069] <TB2> INFO: Test took 3780ms.
[16:16:17.362] <TB2> INFO: Expecting 41600 events.
[16:16:20.919] <TB2> INFO: 41600 events read in total (2965ms).
[16:16:20.920] <TB2> INFO: Test took 3823ms.
[16:16:21.209] <TB2> INFO: Expecting 41600 events.
[16:16:24.798] <TB2> INFO: 41600 events read in total (2997ms).
[16:16:24.799] <TB2> INFO: Test took 3855ms.
[16:16:25.088] <TB2> INFO: Expecting 41600 events.
[16:16:28.668] <TB2> INFO: 41600 events read in total (2988ms).
[16:16:28.669] <TB2> INFO: Test took 3846ms.
[16:16:28.958] <TB2> INFO: Expecting 41600 events.
[16:16:32.471] <TB2> INFO: 41600 events read in total (2922ms).
[16:16:32.472] <TB2> INFO: Test took 3779ms.
[16:16:32.761] <TB2> INFO: Expecting 41600 events.
[16:16:36.369] <TB2> INFO: 41600 events read in total (3016ms).
[16:16:36.369] <TB2> INFO: Test took 3873ms.
[16:16:36.658] <TB2> INFO: Expecting 41600 events.
[16:16:40.344] <TB2> INFO: 41600 events read in total (3094ms).
[16:16:40.344] <TB2> INFO: Test took 3951ms.
[16:16:40.636] <TB2> INFO: Expecting 41600 events.
[16:16:44.254] <TB2> INFO: 41600 events read in total (3026ms).
[16:16:44.254] <TB2> INFO: Test took 3883ms.
[16:16:44.545] <TB2> INFO: Expecting 41600 events.
[16:16:48.195] <TB2> INFO: 41600 events read in total (3058ms).
[16:16:48.196] <TB2> INFO: Test took 3916ms.
[16:16:48.485] <TB2> INFO: Expecting 41600 events.
[16:16:52.117] <TB2> INFO: 41600 events read in total (3040ms).
[16:16:52.118] <TB2> INFO: Test took 3898ms.
[16:16:52.409] <TB2> INFO: Expecting 41600 events.
[16:16:56.089] <TB2> INFO: 41600 events read in total (3089ms).
[16:16:56.090] <TB2> INFO: Test took 3947ms.
[16:16:56.380] <TB2> INFO: Expecting 41600 events.
[16:16:59.913] <TB2> INFO: 41600 events read in total (2941ms).
[16:16:59.914] <TB2> INFO: Test took 3800ms.
[16:17:00.204] <TB2> INFO: Expecting 41600 events.
[16:17:03.718] <TB2> INFO: 41600 events read in total (2922ms).
[16:17:03.719] <TB2> INFO: Test took 3781ms.
[16:17:04.011] <TB2> INFO: Expecting 41600 events.
[16:17:07.529] <TB2> INFO: 41600 events read in total (2926ms).
[16:17:07.529] <TB2> INFO: Test took 3783ms.
[16:17:07.840] <TB2> INFO: Expecting 41600 events.
[16:17:11.466] <TB2> INFO: 41600 events read in total (3035ms).
[16:17:11.467] <TB2> INFO: Test took 3914ms.
[16:17:11.756] <TB2> INFO: Expecting 41600 events.
[16:17:15.355] <TB2> INFO: 41600 events read in total (3007ms).
[16:17:15.356] <TB2> INFO: Test took 3865ms.
[16:17:15.646] <TB2> INFO: Expecting 41600 events.
[16:17:19.253] <TB2> INFO: 41600 events read in total (3016ms).
[16:17:19.254] <TB2> INFO: Test took 3874ms.
[16:17:19.546] <TB2> INFO: Expecting 41600 events.
[16:17:23.104] <TB2> INFO: 41600 events read in total (2966ms).
[16:17:23.105] <TB2> INFO: Test took 3824ms.
[16:17:23.395] <TB2> INFO: Expecting 41600 events.
[16:17:27.008] <TB2> INFO: 41600 events read in total (3021ms).
[16:17:27.008] <TB2> INFO: Test took 3878ms.
[16:17:27.298] <TB2> INFO: Expecting 41600 events.
[16:17:30.829] <TB2> INFO: 41600 events read in total (2939ms).
[16:17:30.829] <TB2> INFO: Test took 3796ms.
[16:17:31.119] <TB2> INFO: Expecting 41600 events.
[16:17:34.665] <TB2> INFO: 41600 events read in total (2954ms).
[16:17:34.665] <TB2> INFO: Test took 3811ms.
[16:17:34.954] <TB2> INFO: Expecting 41600 events.
[16:17:38.445] <TB2> INFO: 41600 events read in total (2899ms).
[16:17:38.446] <TB2> INFO: Test took 3757ms.
[16:17:38.735] <TB2> INFO: Expecting 41600 events.
[16:17:42.300] <TB2> INFO: 41600 events read in total (2973ms).
[16:17:42.301] <TB2> INFO: Test took 3831ms.
[16:17:42.590] <TB2> INFO: Expecting 41600 events.
[16:17:46.111] <TB2> INFO: 41600 events read in total (2930ms).
[16:17:46.112] <TB2> INFO: Test took 3787ms.
[16:17:46.412] <TB2> INFO: Expecting 41600 events.
[16:17:49.965] <TB2> INFO: 41600 events read in total (2961ms).
[16:17:49.966] <TB2> INFO: Test took 3827ms.
[16:17:50.256] <TB2> INFO: Expecting 41600 events.
[16:17:53.812] <TB2> INFO: 41600 events read in total (2965ms).
[16:17:53.813] <TB2> INFO: Test took 3822ms.
[16:17:54.104] <TB2> INFO: Expecting 41600 events.
[16:17:57.734] <TB2> INFO: 41600 events read in total (3038ms).
[16:17:57.735] <TB2> INFO: Test took 3896ms.
[16:17:58.025] <TB2> INFO: Expecting 2560 events.
[16:17:58.909] <TB2> INFO: 2560 events read in total (293ms).
[16:17:58.909] <TB2> INFO: Test took 1162ms.
[16:17:59.217] <TB2> INFO: Expecting 2560 events.
[16:18:00.110] <TB2> INFO: 2560 events read in total (301ms).
[16:18:00.110] <TB2> INFO: Test took 1200ms.
[16:18:00.418] <TB2> INFO: Expecting 2560 events.
[16:18:01.310] <TB2> INFO: 2560 events read in total (300ms).
[16:18:01.311] <TB2> INFO: Test took 1200ms.
[16:18:01.618] <TB2> INFO: Expecting 2560 events.
[16:18:02.508] <TB2> INFO: 2560 events read in total (298ms).
[16:18:02.509] <TB2> INFO: Test took 1197ms.
[16:18:02.817] <TB2> INFO: Expecting 2560 events.
[16:18:03.699] <TB2> INFO: 2560 events read in total (290ms).
[16:18:03.699] <TB2> INFO: Test took 1190ms.
[16:18:04.007] <TB2> INFO: Expecting 2560 events.
[16:18:04.886] <TB2> INFO: 2560 events read in total (287ms).
[16:18:04.887] <TB2> INFO: Test took 1187ms.
[16:18:05.193] <TB2> INFO: Expecting 2560 events.
[16:18:06.074] <TB2> INFO: 2560 events read in total (289ms).
[16:18:06.074] <TB2> INFO: Test took 1187ms.
[16:18:06.383] <TB2> INFO: Expecting 2560 events.
[16:18:07.264] <TB2> INFO: 2560 events read in total (290ms).
[16:18:07.264] <TB2> INFO: Test took 1189ms.
[16:18:07.573] <TB2> INFO: Expecting 2560 events.
[16:18:08.461] <TB2> INFO: 2560 events read in total (297ms).
[16:18:08.461] <TB2> INFO: Test took 1196ms.
[16:18:08.770] <TB2> INFO: Expecting 2560 events.
[16:18:09.654] <TB2> INFO: 2560 events read in total (292ms).
[16:18:09.654] <TB2> INFO: Test took 1193ms.
[16:18:09.961] <TB2> INFO: Expecting 2560 events.
[16:18:10.850] <TB2> INFO: 2560 events read in total (297ms).
[16:18:10.850] <TB2> INFO: Test took 1195ms.
[16:18:11.158] <TB2> INFO: Expecting 2560 events.
[16:18:12.045] <TB2> INFO: 2560 events read in total (295ms).
[16:18:12.045] <TB2> INFO: Test took 1195ms.
[16:18:12.354] <TB2> INFO: Expecting 2560 events.
[16:18:13.243] <TB2> INFO: 2560 events read in total (297ms).
[16:18:13.244] <TB2> INFO: Test took 1198ms.
[16:18:13.551] <TB2> INFO: Expecting 2560 events.
[16:18:14.442] <TB2> INFO: 2560 events read in total (299ms).
[16:18:14.442] <TB2> INFO: Test took 1198ms.
[16:18:14.750] <TB2> INFO: Expecting 2560 events.
[16:18:15.640] <TB2> INFO: 2560 events read in total (298ms).
[16:18:15.641] <TB2> INFO: Test took 1198ms.
[16:18:15.949] <TB2> INFO: Expecting 2560 events.
[16:18:16.837] <TB2> INFO: 2560 events read in total (297ms).
[16:18:16.838] <TB2> INFO: Test took 1196ms.
[16:18:16.842] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:18:17.146] <TB2> INFO: Expecting 655360 events.
[16:18:32.114] <TB2> INFO: 655360 events read in total (14376ms).
[16:18:32.127] <TB2> INFO: Expecting 655360 events.
[16:18:46.696] <TB2> INFO: 655360 events read in total (14166ms).
[16:18:46.713] <TB2> INFO: Expecting 655360 events.
[16:19:01.312] <TB2> INFO: 655360 events read in total (14196ms).
[16:19:01.332] <TB2> INFO: Expecting 655360 events.
[16:19:15.933] <TB2> INFO: 655360 events read in total (14198ms).
[16:19:15.960] <TB2> INFO: Expecting 655360 events.
[16:19:30.504] <TB2> INFO: 655360 events read in total (14141ms).
[16:19:30.534] <TB2> INFO: Expecting 655360 events.
[16:19:45.140] <TB2> INFO: 655360 events read in total (14203ms).
[16:19:45.174] <TB2> INFO: Expecting 655360 events.
[16:19:59.771] <TB2> INFO: 655360 events read in total (14194ms).
[16:19:59.815] <TB2> INFO: Expecting 655360 events.
[16:20:14.415] <TB2> INFO: 655360 events read in total (14197ms).
[16:20:14.457] <TB2> INFO: Expecting 655360 events.
[16:20:29.248] <TB2> INFO: 655360 events read in total (14388ms).
[16:20:29.312] <TB2> INFO: Expecting 655360 events.
[16:20:43.929] <TB2> INFO: 655360 events read in total (14214ms).
[16:20:43.979] <TB2> INFO: Expecting 655360 events.
[16:20:58.874] <TB2> INFO: 655360 events read in total (14492ms).
[16:20:58.940] <TB2> INFO: Expecting 655360 events.
[16:21:13.550] <TB2> INFO: 655360 events read in total (14207ms).
[16:21:13.611] <TB2> INFO: Expecting 655360 events.
[16:21:28.239] <TB2> INFO: 655360 events read in total (14225ms).
[16:21:28.314] <TB2> INFO: Expecting 655360 events.
[16:21:43.071] <TB2> INFO: 655360 events read in total (14354ms).
[16:21:43.155] <TB2> INFO: Expecting 655360 events.
[16:21:57.918] <TB2> INFO: 655360 events read in total (14360ms).
[16:21:58.014] <TB2> INFO: Expecting 655360 events.
[16:22:12.527] <TB2> INFO: 655360 events read in total (14110ms).
[16:22:12.621] <TB2> INFO: Test took 235779ms.
[16:22:12.719] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:22:12.973] <TB2> INFO: Expecting 655360 events.
[16:22:27.827] <TB2> INFO: 655360 events read in total (14262ms).
[16:22:27.839] <TB2> INFO: Expecting 655360 events.
[16:22:42.565] <TB2> INFO: 655360 events read in total (14323ms).
[16:22:42.581] <TB2> INFO: Expecting 655360 events.
[16:22:57.180] <TB2> INFO: 655360 events read in total (14196ms).
[16:22:57.200] <TB2> INFO: Expecting 655360 events.
[16:23:11.718] <TB2> INFO: 655360 events read in total (14115ms).
[16:23:11.750] <TB2> INFO: Expecting 655360 events.
[16:23:26.247] <TB2> INFO: 655360 events read in total (14094ms).
[16:23:26.285] <TB2> INFO: Expecting 655360 events.
[16:23:40.834] <TB2> INFO: 655360 events read in total (14146ms).
[16:23:40.879] <TB2> INFO: Expecting 655360 events.
[16:23:55.573] <TB2> INFO: 655360 events read in total (14290ms).
[16:23:55.636] <TB2> INFO: Expecting 655360 events.
[16:24:10.130] <TB2> INFO: 655360 events read in total (14091ms).
[16:24:10.179] <TB2> INFO: Expecting 655360 events.
[16:24:25.019] <TB2> INFO: 655360 events read in total (14437ms).
[16:24:25.070] <TB2> INFO: Expecting 655360 events.
[16:24:39.866] <TB2> INFO: 655360 events read in total (14393ms).
[16:24:39.916] <TB2> INFO: Expecting 655360 events.
[16:24:54.617] <TB2> INFO: 655360 events read in total (14297ms).
[16:24:54.708] <TB2> INFO: Expecting 655360 events.
[16:25:09.601] <TB2> INFO: 655360 events read in total (14490ms).
[16:25:09.663] <TB2> INFO: Expecting 655360 events.
[16:25:24.688] <TB2> INFO: 655360 events read in total (14621ms).
[16:25:24.761] <TB2> INFO: Expecting 655360 events.
[16:25:39.674] <TB2> INFO: 655360 events read in total (14510ms).
[16:25:39.763] <TB2> INFO: Expecting 655360 events.
[16:25:54.700] <TB2> INFO: 655360 events read in total (14534ms).
[16:25:54.919] <TB2> INFO: Expecting 655360 events.
[16:26:09.671] <TB2> INFO: 655360 events read in total (14349ms).
[16:26:09.793] <TB2> INFO: Test took 237074ms.
[16:26:09.960] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[16:26:09.966] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[16:26:09.972] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[16:26:09.978] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[16:26:09.984] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[16:26:09.990] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[16:26:09.996] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[16:26:09.002] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[16:26:10.008] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[16:26:10.015] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[16:26:10.022] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[16:26:10.028] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[16:26:10.034] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[16:26:10.040] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[16:26:10.045] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[16:26:10.052] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[16:26:10.057] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[16:26:10.064] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[16:26:10.099] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C0.dat
[16:26:10.099] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C1.dat
[16:26:10.099] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C2.dat
[16:26:10.099] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C3.dat
[16:26:10.099] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C4.dat
[16:26:10.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C5.dat
[16:26:10.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C6.dat
[16:26:10.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C7.dat
[16:26:10.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C8.dat
[16:26:10.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C9.dat
[16:26:10.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C10.dat
[16:26:10.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C11.dat
[16:26:10.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C12.dat
[16:26:10.100] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C13.dat
[16:26:10.101] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C14.dat
[16:26:10.101] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//dacParameters35_C15.dat
[16:26:10.395] <TB2> INFO: Expecting 41600 events.
[16:26:13.558] <TB2> INFO: 41600 events read in total (2571ms).
[16:26:13.558] <TB2> INFO: Test took 3454ms.
[16:26:14.005] <TB2> INFO: Expecting 41600 events.
[16:26:17.143] <TB2> INFO: 41600 events read in total (2546ms).
[16:26:17.145] <TB2> INFO: Test took 3376ms.
[16:26:17.606] <TB2> INFO: Expecting 41600 events.
[16:26:20.789] <TB2> INFO: 41600 events read in total (2591ms).
[16:26:20.790] <TB2> INFO: Test took 3429ms.
[16:26:21.010] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:21.100] <TB2> INFO: Expecting 2560 events.
[16:26:21.002] <TB2> INFO: 2560 events read in total (310ms).
[16:26:21.003] <TB2> INFO: Test took 993ms.
[16:26:22.006] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:22.310] <TB2> INFO: Expecting 2560 events.
[16:26:23.198] <TB2> INFO: 2560 events read in total (296ms).
[16:26:23.199] <TB2> INFO: Test took 1193ms.
[16:26:23.202] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:23.506] <TB2> INFO: Expecting 2560 events.
[16:26:24.400] <TB2> INFO: 2560 events read in total (302ms).
[16:26:24.401] <TB2> INFO: Test took 1199ms.
[16:26:24.404] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:24.709] <TB2> INFO: Expecting 2560 events.
[16:26:25.601] <TB2> INFO: 2560 events read in total (301ms).
[16:26:25.601] <TB2> INFO: Test took 1197ms.
[16:26:25.604] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:25.911] <TB2> INFO: Expecting 2560 events.
[16:26:26.801] <TB2> INFO: 2560 events read in total (298ms).
[16:26:26.802] <TB2> INFO: Test took 1198ms.
[16:26:26.805] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:27.110] <TB2> INFO: Expecting 2560 events.
[16:26:27.995] <TB2> INFO: 2560 events read in total (295ms).
[16:26:27.996] <TB2> INFO: Test took 1191ms.
[16:26:27.000] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:28.304] <TB2> INFO: Expecting 2560 events.
[16:26:29.200] <TB2> INFO: 2560 events read in total (304ms).
[16:26:29.201] <TB2> INFO: Test took 1201ms.
[16:26:29.203] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:29.509] <TB2> INFO: Expecting 2560 events.
[16:26:30.407] <TB2> INFO: 2560 events read in total (306ms).
[16:26:30.407] <TB2> INFO: Test took 1204ms.
[16:26:30.410] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:30.714] <TB2> INFO: Expecting 2560 events.
[16:26:31.600] <TB2> INFO: 2560 events read in total (294ms).
[16:26:31.600] <TB2> INFO: Test took 1190ms.
[16:26:31.602] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:31.909] <TB2> INFO: Expecting 2560 events.
[16:26:32.800] <TB2> INFO: 2560 events read in total (299ms).
[16:26:32.800] <TB2> INFO: Test took 1198ms.
[16:26:32.804] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:33.108] <TB2> INFO: Expecting 2560 events.
[16:26:33.991] <TB2> INFO: 2560 events read in total (291ms).
[16:26:33.992] <TB2> INFO: Test took 1188ms.
[16:26:33.996] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:34.299] <TB2> INFO: Expecting 2560 events.
[16:26:35.180] <TB2> INFO: 2560 events read in total (289ms).
[16:26:35.181] <TB2> INFO: Test took 1185ms.
[16:26:35.184] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:35.488] <TB2> INFO: Expecting 2560 events.
[16:26:36.375] <TB2> INFO: 2560 events read in total (295ms).
[16:26:36.375] <TB2> INFO: Test took 1191ms.
[16:26:36.377] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:36.684] <TB2> INFO: Expecting 2560 events.
[16:26:37.572] <TB2> INFO: 2560 events read in total (296ms).
[16:26:37.573] <TB2> INFO: Test took 1196ms.
[16:26:37.575] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:37.881] <TB2> INFO: Expecting 2560 events.
[16:26:38.763] <TB2> INFO: 2560 events read in total (290ms).
[16:26:38.763] <TB2> INFO: Test took 1188ms.
[16:26:38.767] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:39.072] <TB2> INFO: Expecting 2560 events.
[16:26:39.960] <TB2> INFO: 2560 events read in total (296ms).
[16:26:39.960] <TB2> INFO: Test took 1194ms.
[16:26:39.963] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:40.268] <TB2> INFO: Expecting 2560 events.
[16:26:41.158] <TB2> INFO: 2560 events read in total (298ms).
[16:26:41.158] <TB2> INFO: Test took 1195ms.
[16:26:41.161] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:41.466] <TB2> INFO: Expecting 2560 events.
[16:26:42.354] <TB2> INFO: 2560 events read in total (296ms).
[16:26:42.355] <TB2> INFO: Test took 1194ms.
[16:26:42.357] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:42.662] <TB2> INFO: Expecting 2560 events.
[16:26:43.551] <TB2> INFO: 2560 events read in total (297ms).
[16:26:43.552] <TB2> INFO: Test took 1195ms.
[16:26:43.555] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:43.861] <TB2> INFO: Expecting 2560 events.
[16:26:44.744] <TB2> INFO: 2560 events read in total (292ms).
[16:26:44.744] <TB2> INFO: Test took 1190ms.
[16:26:44.748] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:45.052] <TB2> INFO: Expecting 2560 events.
[16:26:45.941] <TB2> INFO: 2560 events read in total (297ms).
[16:26:45.941] <TB2> INFO: Test took 1193ms.
[16:26:45.944] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:46.249] <TB2> INFO: Expecting 2560 events.
[16:26:47.137] <TB2> INFO: 2560 events read in total (296ms).
[16:26:47.137] <TB2> INFO: Test took 1193ms.
[16:26:47.139] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:47.447] <TB2> INFO: Expecting 2560 events.
[16:26:48.336] <TB2> INFO: 2560 events read in total (297ms).
[16:26:48.336] <TB2> INFO: Test took 1197ms.
[16:26:48.339] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:48.644] <TB2> INFO: Expecting 2560 events.
[16:26:49.527] <TB2> INFO: 2560 events read in total (291ms).
[16:26:49.527] <TB2> INFO: Test took 1188ms.
[16:26:49.530] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:49.836] <TB2> INFO: Expecting 2560 events.
[16:26:50.728] <TB2> INFO: 2560 events read in total (301ms).
[16:26:50.729] <TB2> INFO: Test took 1199ms.
[16:26:50.732] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:51.037] <TB2> INFO: Expecting 2560 events.
[16:26:51.930] <TB2> INFO: 2560 events read in total (301ms).
[16:26:51.930] <TB2> INFO: Test took 1198ms.
[16:26:51.933] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:52.238] <TB2> INFO: Expecting 2560 events.
[16:26:53.123] <TB2> INFO: 2560 events read in total (294ms).
[16:26:53.123] <TB2> INFO: Test took 1190ms.
[16:26:53.125] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:53.432] <TB2> INFO: Expecting 2560 events.
[16:26:54.326] <TB2> INFO: 2560 events read in total (302ms).
[16:26:54.327] <TB2> INFO: Test took 1202ms.
[16:26:54.330] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:54.636] <TB2> INFO: Expecting 2560 events.
[16:26:55.527] <TB2> INFO: 2560 events read in total (300ms).
[16:26:55.527] <TB2> INFO: Test took 1198ms.
[16:26:55.530] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:55.836] <TB2> INFO: Expecting 2560 events.
[16:26:56.717] <TB2> INFO: 2560 events read in total (290ms).
[16:26:56.718] <TB2> INFO: Test took 1188ms.
[16:26:56.720] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:57.026] <TB2> INFO: Expecting 2560 events.
[16:26:57.911] <TB2> INFO: 2560 events read in total (293ms).
[16:26:57.911] <TB2> INFO: Test took 1192ms.
[16:26:57.913] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:26:58.219] <TB2> INFO: Expecting 2560 events.
[16:26:59.105] <TB2> INFO: 2560 events read in total (294ms).
[16:26:59.106] <TB2> INFO: Test took 1193ms.
[16:26:59.572] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 661 seconds
[16:26:59.572] <TB2> INFO: PH scale (per ROC): 67 66 62 44 71 58 57 45 41 56 69 63 59 69 47 61
[16:26:59.572] <TB2> INFO: PH offset (per ROC): 118 124 124 99 118 123 127 109 106 89 117 127 136 125 97 135
[16:26:59.580] <TB2> INFO: Decoding statistics:
[16:26:59.580] <TB2> INFO: General information:
[16:26:59.580] <TB2> INFO: 16bit words read: 127884
[16:26:59.580] <TB2> INFO: valid events total: 20480
[16:26:59.580] <TB2> INFO: empty events: 17978
[16:26:59.580] <TB2> INFO: valid events with pixels: 2502
[16:26:59.580] <TB2> INFO: valid pixel hits: 2502
[16:26:59.580] <TB2> INFO: Event errors: 0
[16:26:59.580] <TB2> INFO: start marker: 0
[16:26:59.580] <TB2> INFO: stop marker: 0
[16:26:59.580] <TB2> INFO: overflow: 0
[16:26:59.580] <TB2> INFO: invalid 5bit words: 0
[16:26:59.580] <TB2> INFO: invalid XOR eye diagram: 0
[16:26:59.580] <TB2> INFO: frame (failed synchr.): 0
[16:26:59.580] <TB2> INFO: idle data (no TBM trl): 0
[16:26:59.580] <TB2> INFO: no data (only TBM hdr): 0
[16:26:59.580] <TB2> INFO: TBM errors: 0
[16:26:59.580] <TB2> INFO: flawed TBM headers: 0
[16:26:59.580] <TB2> INFO: flawed TBM trailers: 0
[16:26:59.580] <TB2> INFO: event ID mismatches: 0
[16:26:59.580] <TB2> INFO: ROC errors: 0
[16:26:59.580] <TB2> INFO: missing ROC header(s): 0
[16:26:59.580] <TB2> INFO: misplaced readback start: 0
[16:26:59.580] <TB2> INFO: Pixel decoding errors: 0
[16:26:59.580] <TB2> INFO: pixel data incomplete: 0
[16:26:59.580] <TB2> INFO: pixel address: 0
[16:26:59.580] <TB2> INFO: pulse height fill bit: 0
[16:26:59.580] <TB2> INFO: buffer corruption: 0
[16:26:59.741] <TB2> INFO: ######################################################################
[16:26:59.741] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[16:26:59.741] <TB2> INFO: ######################################################################
[16:26:59.755] <TB2> INFO: scanning low vcal = 10
[16:26:59.991] <TB2> INFO: Expecting 41600 events.
[16:27:03.557] <TB2> INFO: 41600 events read in total (2974ms).
[16:27:03.557] <TB2> INFO: Test took 3802ms.
[16:27:03.560] <TB2> INFO: scanning low vcal = 20
[16:27:03.857] <TB2> INFO: Expecting 41600 events.
[16:27:07.438] <TB2> INFO: 41600 events read in total (2990ms).
[16:27:07.439] <TB2> INFO: Test took 3879ms.
[16:27:07.441] <TB2> INFO: scanning low vcal = 30
[16:27:07.736] <TB2> INFO: Expecting 41600 events.
[16:27:11.380] <TB2> INFO: 41600 events read in total (3052ms).
[16:27:11.381] <TB2> INFO: Test took 3940ms.
[16:27:11.384] <TB2> INFO: scanning low vcal = 40
[16:27:11.660] <TB2> INFO: Expecting 41600 events.
[16:27:15.617] <TB2> INFO: 41600 events read in total (3365ms).
[16:27:15.619] <TB2> INFO: Test took 4235ms.
[16:27:15.622] <TB2> INFO: scanning low vcal = 50
[16:27:15.898] <TB2> INFO: Expecting 41600 events.
[16:27:19.875] <TB2> INFO: 41600 events read in total (3385ms).
[16:27:19.876] <TB2> INFO: Test took 4254ms.
[16:27:19.879] <TB2> INFO: scanning low vcal = 60
[16:27:20.155] <TB2> INFO: Expecting 41600 events.
[16:27:24.102] <TB2> INFO: 41600 events read in total (3355ms).
[16:27:24.103] <TB2> INFO: Test took 4224ms.
[16:27:24.106] <TB2> INFO: scanning low vcal = 70
[16:27:24.382] <TB2> INFO: Expecting 41600 events.
[16:27:28.361] <TB2> INFO: 41600 events read in total (3387ms).
[16:27:28.362] <TB2> INFO: Test took 4256ms.
[16:27:28.365] <TB2> INFO: scanning low vcal = 80
[16:27:28.641] <TB2> INFO: Expecting 41600 events.
[16:27:32.669] <TB2> INFO: 41600 events read in total (3436ms).
[16:27:32.669] <TB2> INFO: Test took 4304ms.
[16:27:32.672] <TB2> INFO: scanning low vcal = 90
[16:27:32.956] <TB2> INFO: Expecting 41600 events.
[16:27:36.969] <TB2> INFO: 41600 events read in total (3422ms).
[16:27:36.969] <TB2> INFO: Test took 4296ms.
[16:27:36.973] <TB2> INFO: scanning low vcal = 100
[16:27:37.249] <TB2> INFO: Expecting 41600 events.
[16:27:41.248] <TB2> INFO: 41600 events read in total (3408ms).
[16:27:41.249] <TB2> INFO: Test took 4276ms.
[16:27:41.252] <TB2> INFO: scanning low vcal = 110
[16:27:41.529] <TB2> INFO: Expecting 41600 events.
[16:27:45.522] <TB2> INFO: 41600 events read in total (3402ms).
[16:27:45.523] <TB2> INFO: Test took 4271ms.
[16:27:45.526] <TB2> INFO: scanning low vcal = 120
[16:27:45.824] <TB2> INFO: Expecting 41600 events.
[16:27:49.864] <TB2> INFO: 41600 events read in total (3448ms).
[16:27:49.865] <TB2> INFO: Test took 4339ms.
[16:27:49.868] <TB2> INFO: scanning low vcal = 130
[16:27:50.145] <TB2> INFO: Expecting 41600 events.
[16:27:54.275] <TB2> INFO: 41600 events read in total (3539ms).
[16:27:54.276] <TB2> INFO: Test took 4408ms.
[16:27:54.279] <TB2> INFO: scanning low vcal = 140
[16:27:54.604] <TB2> INFO: Expecting 41600 events.
[16:27:58.562] <TB2> INFO: 41600 events read in total (3366ms).
[16:27:58.562] <TB2> INFO: Test took 4283ms.
[16:27:58.565] <TB2> INFO: scanning low vcal = 150
[16:27:58.868] <TB2> INFO: Expecting 41600 events.
[16:28:02.959] <TB2> INFO: 41600 events read in total (3499ms).
[16:28:02.960] <TB2> INFO: Test took 4394ms.
[16:28:02.963] <TB2> INFO: scanning low vcal = 160
[16:28:03.280] <TB2> INFO: Expecting 41600 events.
[16:28:07.298] <TB2> INFO: 41600 events read in total (3426ms).
[16:28:07.299] <TB2> INFO: Test took 4336ms.
[16:28:07.302] <TB2> INFO: scanning low vcal = 170
[16:28:07.602] <TB2> INFO: Expecting 41600 events.
[16:28:11.567] <TB2> INFO: 41600 events read in total (3373ms).
[16:28:11.567] <TB2> INFO: Test took 4265ms.
[16:28:11.573] <TB2> INFO: scanning low vcal = 180
[16:28:11.878] <TB2> INFO: Expecting 41600 events.
[16:28:15.840] <TB2> INFO: 41600 events read in total (3370ms).
[16:28:15.840] <TB2> INFO: Test took 4267ms.
[16:28:15.843] <TB2> INFO: scanning low vcal = 190
[16:28:16.120] <TB2> INFO: Expecting 41600 events.
[16:28:20.149] <TB2> INFO: 41600 events read in total (3437ms).
[16:28:20.150] <TB2> INFO: Test took 4307ms.
[16:28:20.153] <TB2> INFO: scanning low vcal = 200
[16:28:20.469] <TB2> INFO: Expecting 41600 events.
[16:28:24.466] <TB2> INFO: 41600 events read in total (3405ms).
[16:28:24.467] <TB2> INFO: Test took 4314ms.
[16:28:24.470] <TB2> INFO: scanning low vcal = 210
[16:28:24.746] <TB2> INFO: Expecting 41600 events.
[16:28:28.772] <TB2> INFO: 41600 events read in total (3434ms).
[16:28:28.773] <TB2> INFO: Test took 4303ms.
[16:28:28.776] <TB2> INFO: scanning low vcal = 220
[16:28:29.088] <TB2> INFO: Expecting 41600 events.
[16:28:33.117] <TB2> INFO: 41600 events read in total (3437ms).
[16:28:33.117] <TB2> INFO: Test took 4341ms.
[16:28:33.120] <TB2> INFO: scanning low vcal = 230
[16:28:33.397] <TB2> INFO: Expecting 41600 events.
[16:28:37.352] <TB2> INFO: 41600 events read in total (3363ms).
[16:28:37.353] <TB2> INFO: Test took 4233ms.
[16:28:37.356] <TB2> INFO: scanning low vcal = 240
[16:28:37.633] <TB2> INFO: Expecting 41600 events.
[16:28:41.593] <TB2> INFO: 41600 events read in total (3368ms).
[16:28:41.594] <TB2> INFO: Test took 4238ms.
[16:28:41.597] <TB2> INFO: scanning low vcal = 250
[16:28:41.874] <TB2> INFO: Expecting 41600 events.
[16:28:45.830] <TB2> INFO: 41600 events read in total (3365ms).
[16:28:45.830] <TB2> INFO: Test took 4233ms.
[16:28:45.835] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[16:28:46.111] <TB2> INFO: Expecting 41600 events.
[16:28:50.069] <TB2> INFO: 41600 events read in total (3366ms).
[16:28:50.069] <TB2> INFO: Test took 4234ms.
[16:28:50.072] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[16:28:50.349] <TB2> INFO: Expecting 41600 events.
[16:28:54.299] <TB2> INFO: 41600 events read in total (3358ms).
[16:28:54.299] <TB2> INFO: Test took 4227ms.
[16:28:54.302] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[16:28:54.579] <TB2> INFO: Expecting 41600 events.
[16:28:58.533] <TB2> INFO: 41600 events read in total (3362ms).
[16:28:58.534] <TB2> INFO: Test took 4232ms.
[16:28:58.538] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[16:28:58.814] <TB2> INFO: Expecting 41600 events.
[16:29:02.771] <TB2> INFO: 41600 events read in total (3365ms).
[16:29:02.772] <TB2> INFO: Test took 4234ms.
[16:29:02.775] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[16:29:03.052] <TB2> INFO: Expecting 41600 events.
[16:29:07.010] <TB2> INFO: 41600 events read in total (3366ms).
[16:29:07.011] <TB2> INFO: Test took 4236ms.
[16:29:07.430] <TB2> INFO: PixTestGainPedestal::measure() done
[16:29:38.369] <TB2> INFO: PixTestGainPedestal::fit() done
[16:29:38.369] <TB2> INFO: non-linearity mean: 0.980 0.980 0.980 0.915 0.985 0.979 0.978 0.941 0.915 0.952 0.981 0.982 0.970 0.981 0.947 0.979
[16:29:38.369] <TB2> INFO: non-linearity RMS: 0.006 0.003 0.004 0.124 0.004 0.006 0.006 0.042 0.086 0.053 0.005 0.003 0.007 0.003 0.029 0.004
[16:29:38.369] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[16:29:38.383] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[16:29:38.396] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[16:29:38.409] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[16:29:38.423] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[16:29:38.437] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[16:29:38.450] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[16:29:38.464] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[16:29:38.477] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[16:29:38.491] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[16:29:38.504] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[16:29:38.518] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[16:29:38.531] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[16:29:38.544] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[16:29:38.558] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[16:29:38.571] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1017_FullQualification_2016-10-19_14h13m_1476879208//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[16:29:38.584] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 158 seconds
[16:29:38.584] <TB2> INFO: Decoding statistics:
[16:29:38.584] <TB2> INFO: General information:
[16:29:38.584] <TB2> INFO: 16bit words read: 3327910
[16:29:38.584] <TB2> INFO: valid events total: 332800
[16:29:38.585] <TB2> INFO: empty events: 0
[16:29:38.585] <TB2> INFO: valid events with pixels: 332800
[16:29:38.585] <TB2> INFO: valid pixel hits: 665555
[16:29:38.585] <TB2> INFO: Event errors: 0
[16:29:38.585] <TB2> INFO: start marker: 0
[16:29:38.585] <TB2> INFO: stop marker: 0
[16:29:38.585] <TB2> INFO: overflow: 0
[16:29:38.585] <TB2> INFO: invalid 5bit words: 0
[16:29:38.585] <TB2> INFO: invalid XOR eye diagram: 0
[16:29:38.585] <TB2> INFO: frame (failed synchr.): 0
[16:29:38.585] <TB2> INFO: idle data (no TBM trl): 0
[16:29:38.585] <TB2> INFO: no data (only TBM hdr): 0
[16:29:38.585] <TB2> INFO: TBM errors: 0
[16:29:38.585] <TB2> INFO: flawed TBM headers: 0
[16:29:38.585] <TB2> INFO: flawed TBM trailers: 0
[16:29:38.585] <TB2> INFO: event ID mismatches: 0
[16:29:38.585] <TB2> INFO: ROC errors: 0
[16:29:38.585] <TB2> INFO: missing ROC header(s): 0
[16:29:38.585] <TB2> INFO: misplaced readback start: 0
[16:29:38.585] <TB2> INFO: Pixel decoding errors: 0
[16:29:38.585] <TB2> INFO: pixel data incomplete: 0
[16:29:38.585] <TB2> INFO: pixel address: 0
[16:29:38.585] <TB2> INFO: pulse height fill bit: 0
[16:29:38.585] <TB2> INFO: buffer corruption: 0
[16:29:38.600] <TB2> INFO: Decoding statistics:
[16:29:38.600] <TB2> INFO: General information:
[16:29:38.600] <TB2> INFO: 16bit words read: 3457330
[16:29:38.600] <TB2> INFO: valid events total: 353536
[16:29:38.600] <TB2> INFO: empty events: 18234
[16:29:38.600] <TB2> INFO: valid events with pixels: 335302
[16:29:38.600] <TB2> INFO: valid pixel hits: 668057
[16:29:38.600] <TB2> INFO: Event errors: 0
[16:29:38.600] <TB2> INFO: start marker: 0
[16:29:38.600] <TB2> INFO: stop marker: 0
[16:29:38.600] <TB2> INFO: overflow: 0
[16:29:38.600] <TB2> INFO: invalid 5bit words: 0
[16:29:38.600] <TB2> INFO: invalid XOR eye diagram: 0
[16:29:38.600] <TB2> INFO: frame (failed synchr.): 0
[16:29:38.600] <TB2> INFO: idle data (no TBM trl): 0
[16:29:38.600] <TB2> INFO: no data (only TBM hdr): 0
[16:29:38.600] <TB2> INFO: TBM errors: 0
[16:29:38.600] <TB2> INFO: flawed TBM headers: 0
[16:29:38.600] <TB2> INFO: flawed TBM trailers: 0
[16:29:38.600] <TB2> INFO: event ID mismatches: 0
[16:29:38.600] <TB2> INFO: ROC errors: 0
[16:29:38.600] <TB2> INFO: missing ROC header(s): 0
[16:29:38.600] <TB2> INFO: misplaced readback start: 0
[16:29:38.600] <TB2> INFO: Pixel decoding errors: 0
[16:29:38.600] <TB2> INFO: pixel data incomplete: 0
[16:29:38.600] <TB2> INFO: pixel address: 0
[16:29:38.600] <TB2> INFO: pulse height fill bit: 0
[16:29:38.600] <TB2> INFO: buffer corruption: 0
[16:29:38.600] <TB2> INFO: enter test to run
[16:29:38.600] <TB2> INFO: test: exit no parameter change
[16:29:38.716] <TB2> QUIET: Connection to board 149 closed.
[16:29:38.717] <TB2> INFO: pXar: this is the end, my friend