[11:03:07.348] <TB2> INFO: *** Welcome to pxar ***
[11:03:07.348] <TB2> INFO: *** Today: 2016/10/19
[11:03:07.355] <TB2> INFO: *** Version: c8ba-dirty
[11:03:07.355] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C15.dat
[11:03:07.356] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//tbmParameters_C1b.dat
[11:03:07.356] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//defaultMaskFile.dat
[11:03:07.356] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters_C15.dat
[11:03:07.433] <TB2> INFO: clk: 4
[11:03:07.433] <TB2> INFO: ctr: 4
[11:03:07.433] <TB2> INFO: sda: 19
[11:03:07.433] <TB2> INFO: tin: 9
[11:03:07.433] <TB2> INFO: level: 15
[11:03:07.433] <TB2> INFO: triggerdelay: 0
[11:03:07.433] <TB2> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[11:03:07.433] <TB2> INFO: Log level: INFO
[11:03:07.443] <TB2> INFO: Found DTB DTB_WWXUD2
[11:03:07.450] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[11:03:07.452] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[11:03:07.453] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[11:03:08.947] <TB2> INFO: DUT info:
[11:03:08.947] <TB2> INFO: The DUT currently contains the following objects:
[11:03:08.947] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[11:03:08.947] <TB2> INFO: TBM Core alpha (0): 7 registers set
[11:03:08.947] <TB2> INFO: TBM Core beta (1): 7 registers set
[11:03:08.947] <TB2> INFO: TBM Core alpha (2): 7 registers set
[11:03:08.947] <TB2> INFO: TBM Core beta (3): 7 registers set
[11:03:08.947] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:03:08.947] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:03:08.947] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:03:08.947] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:03:08.947] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:03:08.947] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:03:08.947] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:03:08.947] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:03:08.947] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:03:08.947] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:03:08.947] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:03:08.948] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:03:08.948] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:03:08.948] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:03:08.948] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:03:08.948] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:03:08.948] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:03:09.349] <TB2> INFO: enter 'restricted' command line mode
[11:03:09.349] <TB2> INFO: enter test to run
[11:03:09.349] <TB2> INFO: test: pretest no parameter change
[11:03:09.349] <TB2> INFO: running: pretest
[11:03:09.354] <TB2> INFO: ######################################################################
[11:03:09.354] <TB2> INFO: PixTestPretest::doTest()
[11:03:09.354] <TB2> INFO: ######################################################################
[11:03:09.355] <TB2> INFO: ----------------------------------------------------------------------
[11:03:09.355] <TB2> INFO: PixTestPretest::programROC()
[11:03:09.355] <TB2> INFO: ----------------------------------------------------------------------
[11:03:27.369] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:03:27.369] <TB2> INFO: IA differences per ROC: 22.5 20.1 20.1 17.7 18.5 18.5 19.3 20.9 20.1 19.3 19.3 20.1 18.5 19.3 17.7 21.7
[11:03:27.432] <TB2> INFO: ----------------------------------------------------------------------
[11:03:27.432] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:03:27.432] <TB2> INFO: ----------------------------------------------------------------------
[11:03:33.833] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 377 mA = 23.5625 mA/ROC
[11:03:33.833] <TB2> INFO: i(loss) [mA/ROC]: 19.3 20.1 18.5 19.3 18.5 18.5 18.5 19.3 18.5 19.3 19.3 18.5 18.5 19.3 19.3 18.5
[11:03:33.868] <TB2> INFO: ----------------------------------------------------------------------
[11:03:33.868] <TB2> INFO: PixTestPretest::findTiming()
[11:03:33.868] <TB2> INFO: ----------------------------------------------------------------------
[11:03:33.868] <TB2> INFO: PixTestCmd::init()

[11:04:06.307] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[11:04:06.307] <TB2> INFO: (success/tries = 100/100), width = 3
[11:04:07.813] <TB2> INFO: ----------------------------------------------------------------------
[11:04:07.813] <TB2> INFO: PixTestPretest::findWorkingPixel()
[11:04:07.813] <TB2> INFO: ----------------------------------------------------------------------
[11:04:07.909] <TB2> INFO: Expecting 231680 events.
[11:04:17.924] <TB2> INFO: 231680 events read in total (9424ms).
[11:04:17.933] <TB2> INFO: Test took 10115ms.
[11:04:18.184] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:04:18.222] <TB2> INFO: ----------------------------------------------------------------------
[11:04:18.222] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[11:04:18.222] <TB2> INFO: ----------------------------------------------------------------------
[11:04:18.317] <TB2> INFO: Expecting 231680 events.
[11:04:28.301] <TB2> INFO: 231680 events read in total (9393ms).
[11:04:28.310] <TB2> INFO: Test took 10083ms.
[11:04:28.576] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[11:04:28.576] <TB2> INFO: CalDel: 104 95 87 97 99 101 111 95 101 94 111 96 95 96 96 82
[11:04:28.577] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[11:04:28.579] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C0.dat
[11:04:28.580] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C1.dat
[11:04:28.580] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C2.dat
[11:04:28.580] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C3.dat
[11:04:28.580] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C4.dat
[11:04:28.581] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C5.dat
[11:04:28.581] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C6.dat
[11:04:28.581] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C7.dat
[11:04:28.581] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C8.dat
[11:04:28.581] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C9.dat
[11:04:28.582] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C10.dat
[11:04:28.582] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C11.dat
[11:04:28.582] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C12.dat
[11:04:28.582] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C13.dat
[11:04:28.582] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C14.dat
[11:04:28.582] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters_C15.dat
[11:04:28.583] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//tbmParameters_C0a.dat
[11:04:28.583] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//tbmParameters_C0b.dat
[11:04:28.583] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//tbmParameters_C1a.dat
[11:04:28.583] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//tbmParameters_C1b.dat
[11:04:28.583] <TB2> INFO: PixTestPretest::doTest() done, duration: 79 seconds
[11:04:28.654] <TB2> INFO: enter test to run
[11:04:28.654] <TB2> INFO: test: FullTest no parameter change
[11:04:28.654] <TB2> INFO: running: fulltest
[11:04:28.654] <TB2> INFO: ######################################################################
[11:04:28.655] <TB2> INFO: PixTestFullTest::doTest()
[11:04:28.655] <TB2> INFO: ######################################################################
[11:04:28.656] <TB2> INFO: ######################################################################
[11:04:28.656] <TB2> INFO: PixTestAlive::doTest()
[11:04:28.656] <TB2> INFO: ######################################################################
[11:04:28.657] <TB2> INFO: ----------------------------------------------------------------------
[11:04:28.657] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:04:28.657] <TB2> INFO: ----------------------------------------------------------------------
[11:04:28.899] <TB2> INFO: Expecting 41600 events.
[11:04:32.341] <TB2> INFO: 41600 events read in total (2850ms).
[11:04:32.341] <TB2> INFO: Test took 3683ms.
[11:04:32.574] <TB2> INFO: PixTestAlive::aliveTest() done
[11:04:32.574] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
[11:04:32.575] <TB2> INFO: ----------------------------------------------------------------------
[11:04:32.575] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:04:32.575] <TB2> INFO: ----------------------------------------------------------------------
[11:04:32.857] <TB2> INFO: Expecting 41600 events.
[11:04:35.840] <TB2> INFO: 41600 events read in total (2391ms).
[11:04:35.840] <TB2> INFO: Test took 3263ms.
[11:04:35.840] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:04:36.072] <TB2> INFO: PixTestAlive::maskTest() done
[11:04:36.072] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:04:36.073] <TB2> INFO: ----------------------------------------------------------------------
[11:04:36.073] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:04:36.073] <TB2> INFO: ----------------------------------------------------------------------
[11:04:36.311] <TB2> INFO: Expecting 41600 events.
[11:04:39.910] <TB2> INFO: 41600 events read in total (3007ms).
[11:04:39.911] <TB2> INFO: Test took 3837ms.
[11:04:40.144] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[11:04:40.144] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:04:40.144] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:04:40.144] <TB2> INFO: Decoding statistics:
[11:04:40.144] <TB2> INFO: General information:
[11:04:40.144] <TB2> INFO: 16bit words read: 0
[11:04:40.144] <TB2> INFO: valid events total: 0
[11:04:40.144] <TB2> INFO: empty events: 0
[11:04:40.144] <TB2> INFO: valid events with pixels: 0
[11:04:40.144] <TB2> INFO: valid pixel hits: 0
[11:04:40.144] <TB2> INFO: Event errors: 0
[11:04:40.144] <TB2> INFO: start marker: 0
[11:04:40.144] <TB2> INFO: stop marker: 0
[11:04:40.144] <TB2> INFO: overflow: 0
[11:04:40.144] <TB2> INFO: invalid 5bit words: 0
[11:04:40.144] <TB2> INFO: invalid XOR eye diagram: 0
[11:04:40.144] <TB2> INFO: frame (failed synchr.): 0
[11:04:40.144] <TB2> INFO: idle data (no TBM trl): 0
[11:04:40.144] <TB2> INFO: no data (only TBM hdr): 0
[11:04:40.144] <TB2> INFO: TBM errors: 0
[11:04:40.144] <TB2> INFO: flawed TBM headers: 0
[11:04:40.144] <TB2> INFO: flawed TBM trailers: 0
[11:04:40.144] <TB2> INFO: event ID mismatches: 0
[11:04:40.144] <TB2> INFO: ROC errors: 0
[11:04:40.144] <TB2> INFO: missing ROC header(s): 0
[11:04:40.144] <TB2> INFO: misplaced readback start: 0
[11:04:40.144] <TB2> INFO: Pixel decoding errors: 0
[11:04:40.144] <TB2> INFO: pixel data incomplete: 0
[11:04:40.144] <TB2> INFO: pixel address: 0
[11:04:40.144] <TB2> INFO: pulse height fill bit: 0
[11:04:40.144] <TB2> INFO: buffer corruption: 0
[11:04:40.150] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C15.dat
[11:04:40.150] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[11:04:40.150] <TB2> INFO: ######################################################################
[11:04:40.150] <TB2> INFO: PixTestReadback::doTest()
[11:04:40.150] <TB2> INFO: ######################################################################
[11:04:40.150] <TB2> INFO: ----------------------------------------------------------------------
[11:04:40.150] <TB2> INFO: PixTestReadback::CalibrateVd()
[11:04:40.150] <TB2> INFO: ----------------------------------------------------------------------
[11:04:50.125] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C0.dat
[11:04:50.125] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C1.dat
[11:04:50.126] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C2.dat
[11:04:50.126] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C3.dat
[11:04:50.126] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C4.dat
[11:04:50.126] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C5.dat
[11:04:50.126] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C6.dat
[11:04:50.126] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C7.dat
[11:04:50.126] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C8.dat
[11:04:50.126] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C9.dat
[11:04:50.126] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C10.dat
[11:04:50.126] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C11.dat
[11:04:50.127] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C12.dat
[11:04:50.127] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C13.dat
[11:04:50.127] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C14.dat
[11:04:50.127] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C15.dat
[11:04:50.163] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:04:50.163] <TB2> INFO: ----------------------------------------------------------------------
[11:04:50.163] <TB2> INFO: PixTestReadback::CalibrateVa()
[11:04:50.163] <TB2> INFO: ----------------------------------------------------------------------
[11:05:00.086] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C0.dat
[11:05:00.086] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C1.dat
[11:05:00.086] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C2.dat
[11:05:00.086] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C3.dat
[11:05:00.086] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C4.dat
[11:05:00.086] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C5.dat
[11:05:00.086] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C6.dat
[11:05:00.086] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C7.dat
[11:05:00.086] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C8.dat
[11:05:00.086] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C9.dat
[11:05:00.086] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C10.dat
[11:05:00.086] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C11.dat
[11:05:00.086] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C12.dat
[11:05:00.086] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C13.dat
[11:05:00.086] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C14.dat
[11:05:00.086] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C15.dat
[11:05:00.115] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:05:00.115] <TB2> INFO: ----------------------------------------------------------------------
[11:05:00.115] <TB2> INFO: PixTestReadback::readbackVbg()
[11:05:00.115] <TB2> INFO: ----------------------------------------------------------------------
[11:05:07.781] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:05:07.781] <TB2> INFO: ----------------------------------------------------------------------
[11:05:07.781] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[11:05:07.781] <TB2> INFO: ----------------------------------------------------------------------
[11:05:07.781] <TB2> INFO: Vbg will be calibrated using Vd calibration
[11:05:07.781] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 151.4calibrated Vbg = 1.17794 :::*/*/*/*/
[11:05:07.781] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 152.7calibrated Vbg = 1.18282 :::*/*/*/*/
[11:05:07.781] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 154.6calibrated Vbg = 1.1725 :::*/*/*/*/
[11:05:07.781] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 149.8calibrated Vbg = 1.17307 :::*/*/*/*/
[11:05:07.781] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 155.7calibrated Vbg = 1.17285 :::*/*/*/*/
[11:05:07.781] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 159.1calibrated Vbg = 1.17877 :::*/*/*/*/
[11:05:07.781] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 151.2calibrated Vbg = 1.18342 :::*/*/*/*/
[11:05:07.781] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 152calibrated Vbg = 1.18301 :::*/*/*/*/
[11:05:07.781] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 150.5calibrated Vbg = 1.17935 :::*/*/*/*/
[11:05:07.781] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 158.7calibrated Vbg = 1.17446 :::*/*/*/*/
[11:05:07.781] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 156.4calibrated Vbg = 1.17712 :::*/*/*/*/
[11:05:07.781] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 151.9calibrated Vbg = 1.16825 :::*/*/*/*/
[11:05:07.781] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 147.5calibrated Vbg = 1.16892 :::*/*/*/*/
[11:05:07.781] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 156.5calibrated Vbg = 1.17178 :::*/*/*/*/
[11:05:07.781] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 152.6calibrated Vbg = 1.17389 :::*/*/*/*/
[11:05:07.781] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 152.3calibrated Vbg = 1.17692 :::*/*/*/*/
[11:05:07.784] <TB2> INFO: ----------------------------------------------------------------------
[11:05:07.784] <TB2> INFO: PixTestReadback::CalibrateIa()
[11:05:07.784] <TB2> INFO: ----------------------------------------------------------------------
[11:07:48.623] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C0.dat
[11:07:48.623] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C1.dat
[11:07:48.623] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C2.dat
[11:07:48.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C3.dat
[11:07:48.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C4.dat
[11:07:48.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C5.dat
[11:07:48.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C6.dat
[11:07:48.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C7.dat
[11:07:48.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C8.dat
[11:07:48.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C9.dat
[11:07:48.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C10.dat
[11:07:48.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C11.dat
[11:07:48.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C12.dat
[11:07:48.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C13.dat
[11:07:48.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C14.dat
[11:07:48.624] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//readbackCal_C15.dat
[11:07:48.652] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:07:48.654] <TB2> INFO: PixTestReadback::doTest() done
[11:07:48.654] <TB2> INFO: Decoding statistics:
[11:07:48.654] <TB2> INFO: General information:
[11:07:48.654] <TB2> INFO: 16bit words read: 1536
[11:07:48.654] <TB2> INFO: valid events total: 256
[11:07:48.654] <TB2> INFO: empty events: 256
[11:07:48.654] <TB2> INFO: valid events with pixels: 0
[11:07:48.654] <TB2> INFO: valid pixel hits: 0
[11:07:48.654] <TB2> INFO: Event errors: 0
[11:07:48.654] <TB2> INFO: start marker: 0
[11:07:48.654] <TB2> INFO: stop marker: 0
[11:07:48.654] <TB2> INFO: overflow: 0
[11:07:48.654] <TB2> INFO: invalid 5bit words: 0
[11:07:48.654] <TB2> INFO: invalid XOR eye diagram: 0
[11:07:48.654] <TB2> INFO: frame (failed synchr.): 0
[11:07:48.654] <TB2> INFO: idle data (no TBM trl): 0
[11:07:48.654] <TB2> INFO: no data (only TBM hdr): 0
[11:07:48.654] <TB2> INFO: TBM errors: 0
[11:07:48.654] <TB2> INFO: flawed TBM headers: 0
[11:07:48.654] <TB2> INFO: flawed TBM trailers: 0
[11:07:48.654] <TB2> INFO: event ID mismatches: 0
[11:07:48.654] <TB2> INFO: ROC errors: 0
[11:07:48.654] <TB2> INFO: missing ROC header(s): 0
[11:07:48.654] <TB2> INFO: misplaced readback start: 0
[11:07:48.654] <TB2> INFO: Pixel decoding errors: 0
[11:07:48.654] <TB2> INFO: pixel data incomplete: 0
[11:07:48.654] <TB2> INFO: pixel address: 0
[11:07:48.654] <TB2> INFO: pulse height fill bit: 0
[11:07:48.654] <TB2> INFO: buffer corruption: 0
[11:07:48.705] <TB2> INFO: ######################################################################
[11:07:48.705] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[11:07:48.705] <TB2> INFO: ######################################################################
[11:07:48.708] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[11:07:48.759] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:07:48.759] <TB2> INFO: run 1 of 1
[11:07:48.995] <TB2> INFO: Expecting 3120000 events.
[11:08:19.857] <TB2> INFO: 660660 events read in total (30270ms).











[11:08:49.823] <TB2> INFO: 1316790 events read in total (60237ms).
[11:09:19.680] <TB2> INFO: 1971395 events read in total (90093ms).











[11:09:49.648] <TB2> INFO: 2626445 events read in total (120061ms).











[11:10:11.932] <TB2> INFO: 3120000 events read in total (142345ms).
[11:10:12.010] <TB2> INFO: Test took 143252ms.
[11:10:37.441] <TB2> INFO: PixTestBBMap::doTest() done with 1 decoding errors: , duration: 168 seconds
[11:10:37.441] <TB2> INFO: number of dead bumps (per ROC): 0 3 2 0 1 0 0 0 0 0 0 1 11 29 0 0
[11:10:37.441] <TB2> INFO: separation cut (per ROC): 104 100 103 108 95 95 104 108 93 102 95 105 108 92 101 100
[11:10:37.442] <TB2> INFO: Decoding statistics:
[11:10:37.442] <TB2> INFO: General information:
[11:10:37.442] <TB2> INFO: 16bit words read: 0
[11:10:37.442] <TB2> INFO: valid events total: 0
[11:10:37.442] <TB2> INFO: empty events: 0
[11:10:37.442] <TB2> INFO: valid events with pixels: 0
[11:10:37.442] <TB2> INFO: valid pixel hits: 0
[11:10:37.442] <TB2> INFO: Event errors: 0
[11:10:37.442] <TB2> INFO: start marker: 0
[11:10:37.442] <TB2> INFO: stop marker: 0
[11:10:37.442] <TB2> INFO: overflow: 0
[11:10:37.442] <TB2> INFO: invalid 5bit words: 0
[11:10:37.442] <TB2> INFO: invalid XOR eye diagram: 0
[11:10:37.442] <TB2> INFO: frame (failed synchr.): 0
[11:10:37.442] <TB2> INFO: idle data (no TBM trl): 0
[11:10:37.442] <TB2> INFO: no data (only TBM hdr): 0
[11:10:37.442] <TB2> INFO: TBM errors: 0
[11:10:37.442] <TB2> INFO: flawed TBM headers: 0
[11:10:37.442] <TB2> INFO: flawed TBM trailers: 0
[11:10:37.442] <TB2> INFO: event ID mismatches: 0
[11:10:37.442] <TB2> INFO: ROC errors: 0
[11:10:37.442] <TB2> INFO: missing ROC header(s): 0
[11:10:37.442] <TB2> INFO: misplaced readback start: 0
[11:10:37.442] <TB2> INFO: Pixel decoding errors: 0
[11:10:37.442] <TB2> INFO: pixel data incomplete: 0
[11:10:37.442] <TB2> INFO: pixel address: 0
[11:10:37.442] <TB2> INFO: pulse height fill bit: 0
[11:10:37.442] <TB2> INFO: buffer corruption: 0
[11:10:37.478] <TB2> INFO: ######################################################################
[11:10:37.478] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:10:37.478] <TB2> INFO: ######################################################################
[11:10:37.478] <TB2> INFO: ----------------------------------------------------------------------
[11:10:37.478] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:10:37.478] <TB2> INFO: ----------------------------------------------------------------------
[11:10:37.478] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[11:10:37.491] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[11:10:37.492] <TB2> INFO: run 1 of 1
[11:10:37.730] <TB2> INFO: Expecting 36608000 events.
[11:11:00.630] <TB2> INFO: 662250 events read in total (22309ms).
[11:11:23.121] <TB2> INFO: 1313250 events read in total (44800ms).
[11:11:45.553] <TB2> INFO: 1962950 events read in total (67232ms).
[11:12:08.482] <TB2> INFO: 2612150 events read in total (90161ms).
[11:12:30.968] <TB2> INFO: 3260650 events read in total (112647ms).
[11:12:53.797] <TB2> INFO: 3907400 events read in total (135476ms).
[11:13:16.430] <TB2> INFO: 4554900 events read in total (158109ms).
[11:13:38.889] <TB2> INFO: 5199950 events read in total (180568ms).
[11:14:01.794] <TB2> INFO: 5847550 events read in total (203473ms).
[11:14:24.513] <TB2> INFO: 6493600 events read in total (226192ms).
[11:14:47.141] <TB2> INFO: 7140600 events read in total (248820ms).
[11:15:09.770] <TB2> INFO: 7787500 events read in total (271449ms).
[11:15:32.615] <TB2> INFO: 8436200 events read in total (294294ms).
[11:15:54.964] <TB2> INFO: 9081250 events read in total (316643ms).
[11:16:17.627] <TB2> INFO: 9728500 events read in total (339306ms).
[11:16:40.357] <TB2> INFO: 10372750 events read in total (362036ms).
[11:17:02.889] <TB2> INFO: 11017250 events read in total (384568ms).
[11:17:25.619] <TB2> INFO: 11663800 events read in total (407298ms).
[11:17:48.258] <TB2> INFO: 12309750 events read in total (429937ms).
[11:18:10.893] <TB2> INFO: 12956750 events read in total (452572ms).
[11:18:33.626] <TB2> INFO: 13602250 events read in total (475305ms).
[11:18:56.193] <TB2> INFO: 14246450 events read in total (497872ms).
[11:19:18.641] <TB2> INFO: 14889150 events read in total (520320ms).
[11:19:41.414] <TB2> INFO: 15532450 events read in total (543093ms).
[11:20:03.992] <TB2> INFO: 16173800 events read in total (565671ms).
[11:20:26.524] <TB2> INFO: 16817200 events read in total (588203ms).
[11:20:49.193] <TB2> INFO: 17459550 events read in total (610872ms).
[11:21:11.811] <TB2> INFO: 18101350 events read in total (633490ms).
[11:21:34.593] <TB2> INFO: 18742700 events read in total (656272ms).
[11:21:57.204] <TB2> INFO: 19383900 events read in total (678883ms).
[11:22:19.802] <TB2> INFO: 20024000 events read in total (701481ms).
[11:22:42.255] <TB2> INFO: 20663100 events read in total (723934ms).
[11:23:05.053] <TB2> INFO: 21302450 events read in total (746732ms).
[11:23:27.510] <TB2> INFO: 21942250 events read in total (769189ms).
[11:23:49.939] <TB2> INFO: 22578850 events read in total (791618ms).
[11:24:12.288] <TB2> INFO: 23215850 events read in total (813967ms).
[11:24:34.495] <TB2> INFO: 23853800 events read in total (836174ms).
[11:24:56.767] <TB2> INFO: 24490750 events read in total (858446ms).
[11:25:19.217] <TB2> INFO: 25129200 events read in total (880896ms).
[11:25:41.626] <TB2> INFO: 25766600 events read in total (903305ms).
[11:26:04.102] <TB2> INFO: 26403800 events read in total (925781ms).
[11:26:26.614] <TB2> INFO: 27040600 events read in total (948293ms).
[11:26:49.175] <TB2> INFO: 27679450 events read in total (970854ms).
[11:27:11.631] <TB2> INFO: 28316350 events read in total (993310ms).
[11:27:34.204] <TB2> INFO: 28954450 events read in total (1015883ms).
[11:27:56.476] <TB2> INFO: 29590700 events read in total (1038155ms).
[11:28:19.252] <TB2> INFO: 30227950 events read in total (1060931ms).
[11:28:41.882] <TB2> INFO: 30866050 events read in total (1083561ms).
[11:29:04.322] <TB2> INFO: 31502400 events read in total (1106001ms).
[11:29:26.941] <TB2> INFO: 32138550 events read in total (1128620ms).
[11:29:49.470] <TB2> INFO: 32777000 events read in total (1151149ms).
[11:30:11.917] <TB2> INFO: 33414250 events read in total (1173596ms).
[11:30:34.545] <TB2> INFO: 34053350 events read in total (1196224ms).
[11:30:57.150] <TB2> INFO: 34691300 events read in total (1218829ms).
[11:31:19.549] <TB2> INFO: 35329550 events read in total (1241228ms).
[11:31:41.890] <TB2> INFO: 35969600 events read in total (1263569ms).
[11:32:04.220] <TB2> INFO: 36608000 events read in total (1285899ms).
[11:32:04.358] <TB2> INFO: Test took 1286866ms.
[11:32:04.893] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:32:06.733] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:32:08.627] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:32:10.630] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:32:12.566] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:32:14.264] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:32:16.386] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:32:18.343] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:32:20.799] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:32:22.431] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:32:24.071] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:32:26.215] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:32:27.883] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:32:29.433] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:32:31.412] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:32:33.201] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[11:32:34.698] <TB2> INFO: PixTestScurves::scurves() done
[11:32:34.698] <TB2> INFO: Vcal mean: 110.82 98.80 114.20 100.30 98.22 102.82 109.56 108.75 100.57 105.16 108.35 101.69 130.18 112.66 98.76 103.74
[11:32:34.698] <TB2> INFO: Vcal RMS: 5.29 5.13 5.10 5.71 5.47 5.63 4.87 4.73 5.47 5.28 7.82 5.43 6.86 5.27 5.08 5.10
[11:32:34.698] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1317 seconds
[11:32:34.698] <TB2> INFO: Decoding statistics:
[11:32:34.698] <TB2> INFO: General information:
[11:32:34.698] <TB2> INFO: 16bit words read: 0
[11:32:34.698] <TB2> INFO: valid events total: 0
[11:32:34.698] <TB2> INFO: empty events: 0
[11:32:34.698] <TB2> INFO: valid events with pixels: 0
[11:32:34.698] <TB2> INFO: valid pixel hits: 0
[11:32:34.698] <TB2> INFO: Event errors: 0
[11:32:34.698] <TB2> INFO: start marker: 0
[11:32:34.698] <TB2> INFO: stop marker: 0
[11:32:34.698] <TB2> INFO: overflow: 0
[11:32:34.698] <TB2> INFO: invalid 5bit words: 0
[11:32:34.698] <TB2> INFO: invalid XOR eye diagram: 0
[11:32:34.698] <TB2> INFO: frame (failed synchr.): 0
[11:32:34.698] <TB2> INFO: idle data (no TBM trl): 0
[11:32:34.698] <TB2> INFO: no data (only TBM hdr): 0
[11:32:34.698] <TB2> INFO: TBM errors: 0
[11:32:34.698] <TB2> INFO: flawed TBM headers: 0
[11:32:34.698] <TB2> INFO: flawed TBM trailers: 0
[11:32:34.698] <TB2> INFO: event ID mismatches: 0
[11:32:34.698] <TB2> INFO: ROC errors: 0
[11:32:34.698] <TB2> INFO: missing ROC header(s): 0
[11:32:34.698] <TB2> INFO: misplaced readback start: 0
[11:32:34.698] <TB2> INFO: Pixel decoding errors: 0
[11:32:34.698] <TB2> INFO: pixel data incomplete: 0
[11:32:34.698] <TB2> INFO: pixel address: 0
[11:32:34.698] <TB2> INFO: pulse height fill bit: 0
[11:32:34.698] <TB2> INFO: buffer corruption: 0
[11:32:34.763] <TB2> INFO: ######################################################################
[11:32:34.763] <TB2> INFO: PixTestTrim::doTest()
[11:32:34.763] <TB2> INFO: ######################################################################
[11:32:34.764] <TB2> INFO: ----------------------------------------------------------------------
[11:32:34.764] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[11:32:34.764] <TB2> INFO: ----------------------------------------------------------------------
[11:32:34.804] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[11:32:34.804] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:32:34.818] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:32:34.818] <TB2> INFO: run 1 of 1
[11:32:35.055] <TB2> INFO: Expecting 5025280 events.
[11:33:06.275] <TB2> INFO: 806576 events read in total (30611ms).
[11:33:36.156] <TB2> INFO: 1609584 events read in total (60492ms).
[11:34:06.778] <TB2> INFO: 2411184 events read in total (91114ms).
[11:34:36.953] <TB2> INFO: 3209088 events read in total (121289ms).
[11:35:06.708] <TB2> INFO: 4003936 events read in total (151044ms).
[11:35:36.121] <TB2> INFO: 4796344 events read in total (180457ms).
[11:35:44.904] <TB2> INFO: 5025280 events read in total (189240ms).
[11:35:44.973] <TB2> INFO: Test took 190155ms.
[11:36:03.772] <TB2> INFO: ROC 0 VthrComp = 116
[11:36:03.773] <TB2> INFO: ROC 1 VthrComp = 107
[11:36:03.773] <TB2> INFO: ROC 2 VthrComp = 117
[11:36:03.773] <TB2> INFO: ROC 3 VthrComp = 104
[11:36:03.773] <TB2> INFO: ROC 4 VthrComp = 103
[11:36:03.773] <TB2> INFO: ROC 5 VthrComp = 106
[11:36:03.773] <TB2> INFO: ROC 6 VthrComp = 112
[11:36:03.773] <TB2> INFO: ROC 7 VthrComp = 116
[11:36:03.773] <TB2> INFO: ROC 8 VthrComp = 105
[11:36:03.774] <TB2> INFO: ROC 9 VthrComp = 110
[11:36:03.774] <TB2> INFO: ROC 10 VthrComp = 105
[11:36:03.774] <TB2> INFO: ROC 11 VthrComp = 111
[11:36:03.774] <TB2> INFO: ROC 12 VthrComp = 129
[11:36:03.774] <TB2> INFO: ROC 13 VthrComp = 115
[11:36:03.774] <TB2> INFO: ROC 14 VthrComp = 110
[11:36:03.774] <TB2> INFO: ROC 15 VthrComp = 118
[11:36:04.015] <TB2> INFO: Expecting 41600 events.
[11:36:07.565] <TB2> INFO: 41600 events read in total (2958ms).
[11:36:07.566] <TB2> INFO: Test took 3790ms.
[11:36:07.578] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[11:36:07.578] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[11:36:07.592] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:36:07.592] <TB2> INFO: run 1 of 1
[11:36:07.871] <TB2> INFO: Expecting 5025280 events.
[11:36:34.999] <TB2> INFO: 588824 events read in total (26536ms).
[11:37:00.783] <TB2> INFO: 1176288 events read in total (52320ms).
[11:37:26.643] <TB2> INFO: 1763728 events read in total (78180ms).
[11:37:53.088] <TB2> INFO: 2351416 events read in total (104625ms).
[11:38:19.212] <TB2> INFO: 2937568 events read in total (130749ms).
[11:38:45.463] <TB2> INFO: 3522272 events read in total (157000ms).
[11:39:10.771] <TB2> INFO: 4106832 events read in total (182308ms).
[11:39:36.896] <TB2> INFO: 4691288 events read in total (208433ms).
[11:39:52.178] <TB2> INFO: 5025280 events read in total (223715ms).
[11:39:52.315] <TB2> INFO: Test took 224722ms.
[11:40:16.531] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 59.0869 for pixel 23/72 mean/min/max = 45.58/31.9962/59.1638
[11:40:16.531] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 58.0104 for pixel 11/79 mean/min/max = 46.2898/34.5033/58.0762
[11:40:16.532] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 58.9814 for pixel 0/43 mean/min/max = 45.4803/31.8505/59.1101
[11:40:16.532] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 62.1587 for pixel 17/5 mean/min/max = 47.7615/33.2914/62.2316
[11:40:16.533] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 59.5134 for pixel 2/1 mean/min/max = 46.4351/33.2361/59.6341
[11:40:16.533] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 61.5831 for pixel 8/12 mean/min/max = 47.7953/33.7435/61.8471
[11:40:16.534] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 58.4923 for pixel 9/68 mean/min/max = 45.5196/32.5018/58.5374
[11:40:16.534] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 57.7238 for pixel 0/39 mean/min/max = 45.1743/32.4326/57.9161
[11:40:16.535] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 60.3527 for pixel 23/13 mean/min/max = 47.5834/34.811/60.3558
[11:40:16.535] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 58.9848 for pixel 19/0 mean/min/max = 47.0298/34.9902/59.0694
[11:40:16.536] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 71.9578 for pixel 1/0 mean/min/max = 51.2727/30.5817/71.9638
[11:40:16.536] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 58.2763 for pixel 0/25 mean/min/max = 46.0676/33.7681/58.3672
[11:40:16.537] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 63.4205 for pixel 21/5 mean/min/max = 47.1833/30.8903/63.4763
[11:40:16.537] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 60.1232 for pixel 21/75 mean/min/max = 45.9342/31.6692/60.1993
[11:40:16.538] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 56.9984 for pixel 0/15 mean/min/max = 45.5979/34.0978/57.098
[11:40:16.538] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 55.6873 for pixel 1/69 mean/min/max = 43.715/31.704/55.726
[11:40:16.538] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:40:16.627] <TB2> INFO: Expecting 411648 events.
[11:40:25.878] <TB2> INFO: 411648 events read in total (8659ms).
[11:40:25.886] <TB2> INFO: Expecting 411648 events.
[11:40:34.997] <TB2> INFO: 411648 events read in total (8708ms).
[11:40:35.008] <TB2> INFO: Expecting 411648 events.
[11:40:44.323] <TB2> INFO: 411648 events read in total (8912ms).
[11:40:44.338] <TB2> INFO: Expecting 411648 events.
[11:40:53.649] <TB2> INFO: 411648 events read in total (8907ms).
[11:40:53.665] <TB2> INFO: Expecting 411648 events.
[11:41:02.934] <TB2> INFO: 411648 events read in total (8866ms).
[11:41:02.952] <TB2> INFO: Expecting 411648 events.
[11:41:12.316] <TB2> INFO: 411648 events read in total (8961ms).
[11:41:12.338] <TB2> INFO: Expecting 411648 events.
[11:41:21.651] <TB2> INFO: 411648 events read in total (8910ms).
[11:41:21.676] <TB2> INFO: Expecting 411648 events.
[11:41:30.968] <TB2> INFO: 411648 events read in total (8888ms).
[11:41:30.996] <TB2> INFO: Expecting 411648 events.
[11:41:40.316] <TB2> INFO: 411648 events read in total (8917ms).
[11:41:40.346] <TB2> INFO: Expecting 411648 events.
[11:41:49.706] <TB2> INFO: 411648 events read in total (8957ms).
[11:41:49.738] <TB2> INFO: Expecting 411648 events.
[11:41:59.109] <TB2> INFO: 411648 events read in total (8968ms).
[11:41:59.143] <TB2> INFO: Expecting 411648 events.
[11:42:08.419] <TB2> INFO: 411648 events read in total (8873ms).
[11:42:08.476] <TB2> INFO: Expecting 411648 events.
[11:42:17.897] <TB2> INFO: 411648 events read in total (9017ms).
[11:42:17.941] <TB2> INFO: Expecting 411648 events.
[11:42:27.125] <TB2> INFO: 411648 events read in total (8781ms).
[11:42:27.177] <TB2> INFO: Expecting 411648 events.
[11:42:36.394] <TB2> INFO: 411648 events read in total (8814ms).
[11:42:36.443] <TB2> INFO: Expecting 411648 events.
[11:42:45.910] <TB2> INFO: 411648 events read in total (9064ms).
[11:42:45.995] <TB2> INFO: Test took 149457ms.
[11:42:46.796] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[11:42:46.810] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:42:46.810] <TB2> INFO: run 1 of 1
[11:42:47.048] <TB2> INFO: Expecting 5025280 events.
[11:43:14.113] <TB2> INFO: 582712 events read in total (26474ms).
[11:43:40.200] <TB2> INFO: 1164624 events read in total (52562ms).
[11:44:06.780] <TB2> INFO: 1747224 events read in total (79141ms).
[11:44:33.147] <TB2> INFO: 2329400 events read in total (105509ms).
[11:44:59.427] <TB2> INFO: 2910064 events read in total (131788ms).
[11:45:25.826] <TB2> INFO: 3490600 events read in total (158187ms).
[11:45:52.404] <TB2> INFO: 4071216 events read in total (184765ms).
[11:46:18.631] <TB2> INFO: 4651328 events read in total (210992ms).
[11:46:35.743] <TB2> INFO: 5025280 events read in total (228104ms).
[11:46:35.948] <TB2> INFO: Test took 229138ms.
[11:47:01.431] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 8.109123 .. 145.655027
[11:47:01.757] <TB2> INFO: Expecting 208000 events.
[11:47:11.320] <TB2> INFO: 208000 events read in total (8972ms).
[11:47:11.322] <TB2> INFO: Test took 9890ms.
[11:47:11.370] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 8 .. 155 (-1/-1) hits flags = 528 (plus default)
[11:47:11.384] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:47:11.384] <TB2> INFO: run 1 of 1
[11:47:11.671] <TB2> INFO: Expecting 4925440 events.
[11:47:37.587] <TB2> INFO: 574408 events read in total (25324ms).
[11:48:03.127] <TB2> INFO: 1148312 events read in total (50864ms).
[11:48:28.465] <TB2> INFO: 1722872 events read in total (76202ms).
[11:48:54.008] <TB2> INFO: 2298016 events read in total (101745ms).
[11:49:19.518] <TB2> INFO: 2873152 events read in total (127255ms).
[11:49:45.008] <TB2> INFO: 3447352 events read in total (152746ms).
[11:50:10.195] <TB2> INFO: 4021680 events read in total (177932ms).
[11:50:36.168] <TB2> INFO: 4595784 events read in total (203905ms).
[11:50:51.034] <TB2> INFO: 4925440 events read in total (218771ms).
[11:50:51.154] <TB2> INFO: Test took 219770ms.
[11:51:16.868] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 27.497301 .. 52.314060
[11:51:17.110] <TB2> INFO: Expecting 208000 events.
[11:51:27.019] <TB2> INFO: 208000 events read in total (9318ms).
[11:51:27.020] <TB2> INFO: Test took 10150ms.
[11:51:27.100] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 62 (-1/-1) hits flags = 528 (plus default)
[11:51:27.115] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:51:27.115] <TB2> INFO: run 1 of 1
[11:51:27.439] <TB2> INFO: Expecting 1530880 events.
[11:51:55.328] <TB2> INFO: 635184 events read in total (27298ms).
[11:52:22.409] <TB2> INFO: 1269608 events read in total (54379ms).
[11:52:33.809] <TB2> INFO: 1530880 events read in total (65780ms).
[11:52:33.842] <TB2> INFO: Test took 66728ms.
[11:52:48.463] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 25.862634 .. 47.972445
[11:52:48.725] <TB2> INFO: Expecting 208000 events.
[11:52:58.787] <TB2> INFO: 208000 events read in total (9471ms).
[11:52:58.788] <TB2> INFO: Test took 10324ms.
[11:52:58.857] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 15 .. 57 (-1/-1) hits flags = 528 (plus default)
[11:52:58.874] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:52:58.874] <TB2> INFO: run 1 of 1
[11:52:59.152] <TB2> INFO: Expecting 1431040 events.
[11:53:27.160] <TB2> INFO: 659504 events read in total (27416ms).
[11:53:54.497] <TB2> INFO: 1318328 events read in total (54753ms).
[11:53:59.633] <TB2> INFO: 1431040 events read in total (59889ms).
[11:53:59.671] <TB2> INFO: Test took 60798ms.
[11:54:14.259] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 24.512553 .. 47.356565
[11:54:14.497] <TB2> INFO: Expecting 208000 events.
[11:54:24.235] <TB2> INFO: 208000 events read in total (9146ms).
[11:54:24.236] <TB2> INFO: Test took 9975ms.
[11:54:24.283] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 57 (-1/-1) hits flags = 528 (plus default)
[11:54:24.297] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:54:24.297] <TB2> INFO: run 1 of 1
[11:54:24.574] <TB2> INFO: Expecting 1464320 events.
[11:54:52.635] <TB2> INFO: 663864 events read in total (27469ms).
[11:55:20.517] <TB2> INFO: 1327248 events read in total (55352ms).
[11:55:26.581] <TB2> INFO: 1464320 events read in total (61416ms).
[11:55:26.614] <TB2> INFO: Test took 62318ms.
[11:55:40.049] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[11:55:40.049] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[11:55:40.063] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[11:55:40.063] <TB2> INFO: run 1 of 1
[11:55:40.395] <TB2> INFO: Expecting 1364480 events.
[11:56:08.546] <TB2> INFO: 667792 events read in total (27559ms).
[11:56:36.932] <TB2> INFO: 1334944 events read in total (55945ms).
[11:56:38.570] <TB2> INFO: 1364480 events read in total (57584ms).
[11:56:38.596] <TB2> INFO: Test took 58534ms.
[11:56:51.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C0.dat
[11:56:51.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C1.dat
[11:56:51.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C2.dat
[11:56:51.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C3.dat
[11:56:51.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C4.dat
[11:56:51.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C5.dat
[11:56:51.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C6.dat
[11:56:51.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C7.dat
[11:56:51.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C8.dat
[11:56:51.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C9.dat
[11:56:51.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C10.dat
[11:56:51.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C11.dat
[11:56:51.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C12.dat
[11:56:51.218] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C13.dat
[11:56:51.219] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C14.dat
[11:56:51.219] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C15.dat
[11:56:51.219] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters35_C0.dat
[11:56:51.224] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters35_C1.dat
[11:56:51.229] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters35_C2.dat
[11:56:51.233] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters35_C3.dat
[11:56:51.238] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters35_C4.dat
[11:56:51.243] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters35_C5.dat
[11:56:51.247] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters35_C6.dat
[11:56:51.252] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters35_C7.dat
[11:56:51.256] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters35_C8.dat
[11:56:51.261] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters35_C9.dat
[11:56:51.266] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters35_C10.dat
[11:56:51.271] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters35_C11.dat
[11:56:51.276] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters35_C12.dat
[11:56:51.281] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters35_C13.dat
[11:56:51.286] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters35_C14.dat
[11:56:51.291] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//trimParameters35_C15.dat
[11:56:51.296] <TB2> INFO: PixTestTrim::trimTest() done
[11:56:51.296] <TB2> INFO: vtrim: 128 126 106 140 113 135 122 115 131 117 134 97 139 126 113 115
[11:56:51.296] <TB2> INFO: vthrcomp: 116 107 117 104 103 106 112 116 105 110 105 111 129 115 110 118
[11:56:51.296] <TB2> INFO: vcal mean: 34.99 34.98 35.01 34.96 34.96 34.98 35.01 34.98 35.00 34.98 35.03 35.01 35.19 34.90 34.99 34.96
[11:56:51.296] <TB2> INFO: vcal RMS: 0.95 0.91 1.05 1.07 0.94 0.99 1.03 0.95 1.10 0.92 1.16 0.85 1.40 1.13 0.89 0.95
[11:56:51.296] <TB2> INFO: bits mean: 9.28 8.56 9.01 9.20 9.27 9.09 9.63 9.34 8.79 8.58 8.27 7.98 9.55 9.52 9.06 10.05
[11:56:51.296] <TB2> INFO: bits RMS: 2.81 2.67 2.94 2.51 2.55 2.50 2.59 2.71 2.46 2.60 2.96 2.96 2.77 2.71 2.53 2.59
[11:56:51.304] <TB2> INFO: ----------------------------------------------------------------------
[11:56:51.304] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[11:56:51.304] <TB2> INFO: ----------------------------------------------------------------------
[11:56:51.306] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[11:56:51.321] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:56:51.321] <TB2> INFO: run 1 of 1
[11:56:51.588] <TB2> INFO: Expecting 4160000 events.
[11:57:23.737] <TB2> INFO: 723935 events read in total (31558ms).
[11:57:55.127] <TB2> INFO: 1442895 events read in total (62948ms).
[11:58:26.367] <TB2> INFO: 2158905 events read in total (94189ms).
[11:58:57.751] <TB2> INFO: 2869920 events read in total (125572ms).
[11:59:28.765] <TB2> INFO: 3578910 events read in total (156586ms).
[11:59:54.588] <TB2> INFO: 4160000 events read in total (182409ms).
[11:59:54.676] <TB2> INFO: Test took 183355ms.
[12:00:19.940] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[12:00:19.954] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:00:19.954] <TB2> INFO: run 1 of 1
[12:00:20.235] <TB2> INFO: Expecting 4305600 events.
[12:00:51.626] <TB2> INFO: 693120 events read in total (30799ms).
[12:01:22.314] <TB2> INFO: 1382065 events read in total (61487ms).
[12:01:53.219] <TB2> INFO: 2070215 events read in total (92392ms).
[12:02:23.894] <TB2> INFO: 2754360 events read in total (123067ms).
[12:02:53.836] <TB2> INFO: 3436525 events read in total (153009ms).
[12:03:23.956] <TB2> INFO: 4118675 events read in total (183129ms).
[12:03:32.352] <TB2> INFO: 4305600 events read in total (191525ms).
[12:03:32.564] <TB2> INFO: Test took 192610ms.
[12:04:00.127] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 195 (-1/-1) hits flags = 528 (plus default)
[12:04:00.141] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:04:00.141] <TB2> INFO: run 1 of 1
[12:04:00.379] <TB2> INFO: Expecting 4076800 events.
[12:04:31.868] <TB2> INFO: 705230 events read in total (30898ms).
[12:05:02.212] <TB2> INFO: 1406060 events read in total (61242ms).
[12:05:32.944] <TB2> INFO: 2104795 events read in total (91974ms).
[12:06:03.379] <TB2> INFO: 2799400 events read in total (122409ms).
[12:06:34.197] <TB2> INFO: 3492405 events read in total (153227ms).
[12:07:00.309] <TB2> INFO: 4076800 events read in total (179339ms).
[12:07:00.380] <TB2> INFO: Test took 180239ms.
[12:07:27.828] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 195 (-1/-1) hits flags = 528 (plus default)
[12:07:27.842] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:07:27.842] <TB2> INFO: run 1 of 1
[12:07:28.080] <TB2> INFO: Expecting 4076800 events.
[12:07:59.197] <TB2> INFO: 705200 events read in total (30525ms).
[12:08:29.896] <TB2> INFO: 1405975 events read in total (61224ms).
[12:09:00.694] <TB2> INFO: 2104680 events read in total (92022ms).
[12:09:31.725] <TB2> INFO: 2799160 events read in total (123053ms).
[12:10:02.345] <TB2> INFO: 3492280 events read in total (153673ms).
[12:10:28.522] <TB2> INFO: 4076800 events read in total (179850ms).
[12:10:28.610] <TB2> INFO: Test took 180768ms.
[12:10:53.664] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 195 (-1/-1) hits flags = 528 (plus default)
[12:10:53.677] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:10:53.677] <TB2> INFO: run 1 of 1
[12:10:53.914] <TB2> INFO: Expecting 4076800 events.
[12:11:25.167] <TB2> INFO: 705150 events read in total (30662ms).
[12:11:55.624] <TB2> INFO: 1405800 events read in total (61119ms).
[12:12:26.694] <TB2> INFO: 2104345 events read in total (92189ms).
[12:12:57.657] <TB2> INFO: 2798810 events read in total (123152ms).
[12:13:28.070] <TB2> INFO: 3491625 events read in total (153565ms).
[12:13:53.632] <TB2> INFO: 4076800 events read in total (179127ms).
[12:13:53.708] <TB2> INFO: Test took 180030ms.
[12:14:18.612] <TB2> INFO: PixTestTrim::trimBitTest() done
[12:14:18.613] <TB2> INFO: PixTestTrim::doTest() done, duration: 2503 seconds
[12:14:18.613] <TB2> INFO: Decoding statistics:
[12:14:18.613] <TB2> INFO: General information:
[12:14:18.613] <TB2> INFO: 16bit words read: 0
[12:14:18.613] <TB2> INFO: valid events total: 0
[12:14:18.613] <TB2> INFO: empty events: 0
[12:14:18.613] <TB2> INFO: valid events with pixels: 0
[12:14:18.613] <TB2> INFO: valid pixel hits: 0
[12:14:18.613] <TB2> INFO: Event errors: 0
[12:14:18.613] <TB2> INFO: start marker: 0
[12:14:18.613] <TB2> INFO: stop marker: 0
[12:14:18.613] <TB2> INFO: overflow: 0
[12:14:18.613] <TB2> INFO: invalid 5bit words: 0
[12:14:18.613] <TB2> INFO: invalid XOR eye diagram: 0
[12:14:18.613] <TB2> INFO: frame (failed synchr.): 0
[12:14:18.614] <TB2> INFO: idle data (no TBM trl): 0
[12:14:18.614] <TB2> INFO: no data (only TBM hdr): 0
[12:14:18.614] <TB2> INFO: TBM errors: 0
[12:14:18.614] <TB2> INFO: flawed TBM headers: 0
[12:14:18.614] <TB2> INFO: flawed TBM trailers: 0
[12:14:18.614] <TB2> INFO: event ID mismatches: 0
[12:14:18.614] <TB2> INFO: ROC errors: 0
[12:14:18.614] <TB2> INFO: missing ROC header(s): 0
[12:14:18.614] <TB2> INFO: misplaced readback start: 0
[12:14:18.614] <TB2> INFO: Pixel decoding errors: 0
[12:14:18.614] <TB2> INFO: pixel data incomplete: 0
[12:14:18.614] <TB2> INFO: pixel address: 0
[12:14:18.614] <TB2> INFO: pulse height fill bit: 0
[12:14:18.614] <TB2> INFO: buffer corruption: 0
[12:14:19.220] <TB2> INFO: ######################################################################
[12:14:19.220] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[12:14:19.220] <TB2> INFO: ######################################################################
[12:14:19.457] <TB2> INFO: Expecting 41600 events.
[12:14:22.944] <TB2> INFO: 41600 events read in total (2896ms).
[12:14:22.945] <TB2> INFO: Test took 3724ms.
[12:14:23.389] <TB2> INFO: Expecting 41600 events.
[12:14:26.897] <TB2> INFO: 41600 events read in total (2917ms).
[12:14:26.898] <TB2> INFO: Test took 3749ms.
[12:14:27.188] <TB2> INFO: Expecting 41600 events.
[12:14:30.916] <TB2> INFO: 41600 events read in total (3137ms).
[12:14:30.917] <TB2> INFO: Test took 3995ms.
[12:14:31.208] <TB2> INFO: Expecting 41600 events.
[12:14:34.838] <TB2> INFO: 41600 events read in total (3039ms).
[12:14:34.839] <TB2> INFO: Test took 3897ms.
[12:14:35.132] <TB2> INFO: Expecting 41600 events.
[12:14:38.718] <TB2> INFO: 41600 events read in total (2995ms).
[12:14:38.719] <TB2> INFO: Test took 3854ms.
[12:14:39.009] <TB2> INFO: Expecting 41600 events.
[12:14:42.511] <TB2> INFO: 41600 events read in total (2910ms).
[12:14:42.512] <TB2> INFO: Test took 3769ms.
[12:14:42.804] <TB2> INFO: Expecting 41600 events.
[12:14:46.522] <TB2> INFO: 41600 events read in total (3126ms).
[12:14:46.523] <TB2> INFO: Test took 3985ms.
[12:14:46.815] <TB2> INFO: Expecting 41600 events.
[12:14:50.438] <TB2> INFO: 41600 events read in total (3031ms).
[12:14:50.439] <TB2> INFO: Test took 3890ms.
[12:14:50.729] <TB2> INFO: Expecting 41600 events.
[12:14:54.307] <TB2> INFO: 41600 events read in total (2986ms).
[12:14:54.308] <TB2> INFO: Test took 3845ms.
[12:14:54.597] <TB2> INFO: Expecting 41600 events.
[12:14:58.152] <TB2> INFO: 41600 events read in total (2963ms).
[12:14:58.153] <TB2> INFO: Test took 3821ms.
[12:14:58.442] <TB2> INFO: Expecting 41600 events.
[12:15:01.943] <TB2> INFO: 41600 events read in total (2910ms).
[12:15:01.943] <TB2> INFO: Test took 3765ms.
[12:15:02.233] <TB2> INFO: Expecting 41600 events.
[12:15:05.734] <TB2> INFO: 41600 events read in total (2910ms).
[12:15:05.735] <TB2> INFO: Test took 3767ms.
[12:15:06.024] <TB2> INFO: Expecting 41600 events.
[12:15:09.557] <TB2> INFO: 41600 events read in total (2941ms).
[12:15:09.558] <TB2> INFO: Test took 3799ms.
[12:15:09.865] <TB2> INFO: Expecting 41600 events.
[12:15:13.370] <TB2> INFO: 41600 events read in total (2913ms).
[12:15:13.371] <TB2> INFO: Test took 3789ms.
[12:15:13.660] <TB2> INFO: Expecting 41600 events.
[12:15:17.224] <TB2> INFO: 41600 events read in total (2972ms).
[12:15:17.225] <TB2> INFO: Test took 3830ms.
[12:15:17.516] <TB2> INFO: Expecting 41600 events.
[12:15:21.068] <TB2> INFO: 41600 events read in total (2960ms).
[12:15:21.069] <TB2> INFO: Test took 3819ms.
[12:15:21.361] <TB2> INFO: Expecting 41600 events.
[12:15:24.919] <TB2> INFO: 41600 events read in total (2966ms).
[12:15:24.919] <TB2> INFO: Test took 3823ms.
[12:15:25.227] <TB2> INFO: Expecting 41600 events.
[12:15:28.735] <TB2> INFO: 41600 events read in total (2916ms).
[12:15:28.736] <TB2> INFO: Test took 3793ms.
[12:15:29.025] <TB2> INFO: Expecting 41600 events.
[12:15:32.583] <TB2> INFO: 41600 events read in total (2967ms).
[12:15:32.584] <TB2> INFO: Test took 3824ms.
[12:15:32.874] <TB2> INFO: Expecting 41600 events.
[12:15:36.377] <TB2> INFO: 41600 events read in total (2912ms).
[12:15:36.377] <TB2> INFO: Test took 3770ms.
[12:15:36.667] <TB2> INFO: Expecting 41600 events.
[12:15:40.240] <TB2> INFO: 41600 events read in total (2981ms).
[12:15:40.240] <TB2> INFO: Test took 3838ms.
[12:15:40.530] <TB2> INFO: Expecting 41600 events.
[12:15:44.080] <TB2> INFO: 41600 events read in total (2958ms).
[12:15:44.081] <TB2> INFO: Test took 3817ms.
[12:15:44.371] <TB2> INFO: Expecting 41600 events.
[12:15:47.936] <TB2> INFO: 41600 events read in total (2973ms).
[12:15:47.937] <TB2> INFO: Test took 3832ms.
[12:15:48.229] <TB2> INFO: Expecting 41600 events.
[12:15:51.898] <TB2> INFO: 41600 events read in total (3078ms).
[12:15:51.898] <TB2> INFO: Test took 3935ms.
[12:15:52.189] <TB2> INFO: Expecting 41600 events.
[12:15:55.703] <TB2> INFO: 41600 events read in total (2923ms).
[12:15:55.704] <TB2> INFO: Test took 3781ms.
[12:15:56.017] <TB2> INFO: Expecting 41600 events.
[12:15:59.591] <TB2> INFO: 41600 events read in total (2982ms).
[12:15:59.592] <TB2> INFO: Test took 3864ms.
[12:15:59.883] <TB2> INFO: Expecting 41600 events.
[12:16:03.460] <TB2> INFO: 41600 events read in total (2985ms).
[12:16:03.461] <TB2> INFO: Test took 3843ms.
[12:16:03.752] <TB2> INFO: Expecting 2560 events.
[12:16:04.645] <TB2> INFO: 2560 events read in total (301ms).
[12:16:04.645] <TB2> INFO: Test took 1171ms.
[12:16:04.952] <TB2> INFO: Expecting 2560 events.
[12:16:05.845] <TB2> INFO: 2560 events read in total (301ms).
[12:16:05.845] <TB2> INFO: Test took 1199ms.
[12:16:06.154] <TB2> INFO: Expecting 2560 events.
[12:16:07.039] <TB2> INFO: 2560 events read in total (293ms).
[12:16:07.039] <TB2> INFO: Test took 1193ms.
[12:16:07.347] <TB2> INFO: Expecting 2560 events.
[12:16:08.240] <TB2> INFO: 2560 events read in total (301ms).
[12:16:08.240] <TB2> INFO: Test took 1200ms.
[12:16:08.547] <TB2> INFO: Expecting 2560 events.
[12:16:09.430] <TB2> INFO: 2560 events read in total (291ms).
[12:16:09.430] <TB2> INFO: Test took 1189ms.
[12:16:09.739] <TB2> INFO: Expecting 2560 events.
[12:16:10.623] <TB2> INFO: 2560 events read in total (292ms).
[12:16:10.623] <TB2> INFO: Test took 1192ms.
[12:16:10.931] <TB2> INFO: Expecting 2560 events.
[12:16:11.819] <TB2> INFO: 2560 events read in total (296ms).
[12:16:11.820] <TB2> INFO: Test took 1196ms.
[12:16:12.127] <TB2> INFO: Expecting 2560 events.
[12:16:13.011] <TB2> INFO: 2560 events read in total (292ms).
[12:16:13.011] <TB2> INFO: Test took 1190ms.
[12:16:13.319] <TB2> INFO: Expecting 2560 events.
[12:16:14.200] <TB2> INFO: 2560 events read in total (290ms).
[12:16:14.200] <TB2> INFO: Test took 1188ms.
[12:16:14.507] <TB2> INFO: Expecting 2560 events.
[12:16:15.393] <TB2> INFO: 2560 events read in total (294ms).
[12:16:15.394] <TB2> INFO: Test took 1193ms.
[12:16:15.701] <TB2> INFO: Expecting 2560 events.
[12:16:16.589] <TB2> INFO: 2560 events read in total (296ms).
[12:16:16.590] <TB2> INFO: Test took 1196ms.
[12:16:16.896] <TB2> INFO: Expecting 2560 events.
[12:16:17.788] <TB2> INFO: 2560 events read in total (300ms).
[12:16:17.788] <TB2> INFO: Test took 1197ms.
[12:16:18.096] <TB2> INFO: Expecting 2560 events.
[12:16:18.987] <TB2> INFO: 2560 events read in total (300ms).
[12:16:18.987] <TB2> INFO: Test took 1198ms.
[12:16:19.295] <TB2> INFO: Expecting 2560 events.
[12:16:20.185] <TB2> INFO: 2560 events read in total (298ms).
[12:16:20.186] <TB2> INFO: Test took 1199ms.
[12:16:20.493] <TB2> INFO: Expecting 2560 events.
[12:16:21.375] <TB2> INFO: 2560 events read in total (290ms).
[12:16:21.376] <TB2> INFO: Test took 1189ms.
[12:16:21.683] <TB2> INFO: Expecting 2560 events.
[12:16:22.568] <TB2> INFO: 2560 events read in total (293ms).
[12:16:22.568] <TB2> INFO: Test took 1192ms.
[12:16:22.571] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:16:22.875] <TB2> INFO: Expecting 655360 events.
[12:16:37.620] <TB2> INFO: 655360 events read in total (14153ms).
[12:16:37.636] <TB2> INFO: Expecting 655360 events.
[12:16:52.300] <TB2> INFO: 655360 events read in total (14261ms).
[12:16:52.317] <TB2> INFO: Expecting 655360 events.
[12:17:07.098] <TB2> INFO: 655360 events read in total (14379ms).
[12:17:07.119] <TB2> INFO: Expecting 655360 events.
[12:17:21.856] <TB2> INFO: 655360 events read in total (14334ms).
[12:17:21.881] <TB2> INFO: Expecting 655360 events.
[12:17:36.547] <TB2> INFO: 655360 events read in total (14264ms).
[12:17:36.588] <TB2> INFO: Expecting 655360 events.
[12:17:51.144] <TB2> INFO: 655360 events read in total (14153ms).
[12:17:51.187] <TB2> INFO: Expecting 655360 events.
[12:18:05.732] <TB2> INFO: 655360 events read in total (14142ms).
[12:18:05.770] <TB2> INFO: Expecting 655360 events.
[12:18:20.389] <TB2> INFO: 655360 events read in total (14216ms).
[12:18:20.431] <TB2> INFO: Expecting 655360 events.
[12:18:35.016] <TB2> INFO: 655360 events read in total (14182ms).
[12:18:35.063] <TB2> INFO: Expecting 655360 events.
[12:18:49.679] <TB2> INFO: 655360 events read in total (14213ms).
[12:18:49.732] <TB2> INFO: Expecting 655360 events.
[12:19:04.342] <TB2> INFO: 655360 events read in total (14207ms).
[12:19:04.408] <TB2> INFO: Expecting 655360 events.
[12:19:18.933] <TB2> INFO: 655360 events read in total (14122ms).
[12:19:19.004] <TB2> INFO: Expecting 655360 events.
[12:19:33.684] <TB2> INFO: 655360 events read in total (14277ms).
[12:19:33.778] <TB2> INFO: Expecting 655360 events.
[12:19:48.347] <TB2> INFO: 655360 events read in total (14166ms).
[12:19:48.434] <TB2> INFO: Expecting 655360 events.
[12:20:03.073] <TB2> INFO: 655360 events read in total (14236ms).
[12:20:03.162] <TB2> INFO: Expecting 655360 events.
[12:20:17.938] <TB2> INFO: 655360 events read in total (14373ms).
[12:20:18.158] <TB2> INFO: Test took 235587ms.
[12:20:18.255] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:20:18.513] <TB2> INFO: Expecting 655360 events.
[12:20:33.277] <TB2> INFO: 655360 events read in total (14172ms).
[12:20:33.289] <TB2> INFO: Expecting 655360 events.
[12:20:47.916] <TB2> INFO: 655360 events read in total (14224ms).
[12:20:47.934] <TB2> INFO: Expecting 655360 events.
[12:21:02.517] <TB2> INFO: 655360 events read in total (14180ms).
[12:21:02.538] <TB2> INFO: Expecting 655360 events.
[12:21:17.078] <TB2> INFO: 655360 events read in total (14137ms).
[12:21:17.112] <TB2> INFO: Expecting 655360 events.
[12:21:31.657] <TB2> INFO: 655360 events read in total (14142ms).
[12:21:31.688] <TB2> INFO: Expecting 655360 events.
[12:21:45.848] <TB2> INFO: 655360 events read in total (13757ms).
[12:21:45.881] <TB2> INFO: Expecting 655360 events.
[12:22:00.505] <TB2> INFO: 655360 events read in total (14221ms).
[12:22:00.543] <TB2> INFO: Expecting 655360 events.
[12:22:15.023] <TB2> INFO: 655360 events read in total (14077ms).
[12:22:15.064] <TB2> INFO: Expecting 655360 events.
[12:22:29.708] <TB2> INFO: 655360 events read in total (14241ms).
[12:22:29.754] <TB2> INFO: Expecting 655360 events.
[12:22:44.246] <TB2> INFO: 655360 events read in total (14089ms).
[12:22:44.298] <TB2> INFO: Expecting 655360 events.
[12:22:58.954] <TB2> INFO: 655360 events read in total (14253ms).
[12:22:59.008] <TB2> INFO: Expecting 655360 events.
[12:23:14.012] <TB2> INFO: 655360 events read in total (14601ms).
[12:23:14.216] <TB2> INFO: Expecting 655360 events.
[12:23:28.735] <TB2> INFO: 655360 events read in total (14116ms).
[12:23:28.898] <TB2> INFO: Expecting 655360 events.
[12:23:43.451] <TB2> INFO: 655360 events read in total (14149ms).
[12:23:43.677] <TB2> INFO: Expecting 655360 events.
[12:23:58.778] <TB2> INFO: 655360 events read in total (14698ms).
[12:23:58.872] <TB2> INFO: Expecting 655360 events.
[12:24:13.630] <TB2> INFO: 655360 events read in total (14355ms).
[12:24:13.768] <TB2> INFO: Test took 235513ms.
[12:24:13.996] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:24:13.002] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:24:14.009] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:24:14.015] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:24:14.020] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:24:14.026] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:24:14.032] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:24:14.038] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[12:24:14.044] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[12:24:14.050] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[12:24:14.056] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:24:14.062] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:24:14.068] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:24:14.074] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:24:14.080] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:24:14.085] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:24:14.091] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[12:24:14.097] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[12:24:14.103] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[12:24:14.109] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[12:24:14.115] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[12:24:14.121] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[12:24:14.127] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:24:14.133] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:24:14.139] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:24:14.145] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:24:14.151] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:24:14.157] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[12:24:14.163] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[12:24:14.200] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C0.dat
[12:24:14.201] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C1.dat
[12:24:14.201] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C2.dat
[12:24:14.201] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C3.dat
[12:24:14.201] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C4.dat
[12:24:14.201] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C5.dat
[12:24:14.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C6.dat
[12:24:14.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C7.dat
[12:24:14.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C8.dat
[12:24:14.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C9.dat
[12:24:14.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C10.dat
[12:24:14.203] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C11.dat
[12:24:14.203] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C12.dat
[12:24:14.203] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C13.dat
[12:24:14.203] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C14.dat
[12:24:14.203] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//dacParameters35_C15.dat
[12:24:14.448] <TB2> INFO: Expecting 41600 events.
[12:24:17.669] <TB2> INFO: 41600 events read in total (2629ms).
[12:24:17.670] <TB2> INFO: Test took 3463ms.
[12:24:18.131] <TB2> INFO: Expecting 41600 events.
[12:24:21.254] <TB2> INFO: 41600 events read in total (2531ms).
[12:24:21.255] <TB2> INFO: Test took 3370ms.
[12:24:21.759] <TB2> INFO: Expecting 41600 events.
[12:24:24.951] <TB2> INFO: 41600 events read in total (2600ms).
[12:24:24.952] <TB2> INFO: Test took 3484ms.
[12:24:25.170] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:25.260] <TB2> INFO: Expecting 2560 events.
[12:24:26.154] <TB2> INFO: 2560 events read in total (302ms).
[12:24:26.154] <TB2> INFO: Test took 984ms.
[12:24:26.158] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:26.462] <TB2> INFO: Expecting 2560 events.
[12:24:27.352] <TB2> INFO: 2560 events read in total (298ms).
[12:24:27.353] <TB2> INFO: Test took 1195ms.
[12:24:27.356] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:27.660] <TB2> INFO: Expecting 2560 events.
[12:24:28.554] <TB2> INFO: 2560 events read in total (302ms).
[12:24:28.555] <TB2> INFO: Test took 1199ms.
[12:24:28.559] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:28.862] <TB2> INFO: Expecting 2560 events.
[12:24:29.755] <TB2> INFO: 2560 events read in total (301ms).
[12:24:29.755] <TB2> INFO: Test took 1196ms.
[12:24:29.757] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:30.064] <TB2> INFO: Expecting 2560 events.
[12:24:30.963] <TB2> INFO: 2560 events read in total (308ms).
[12:24:30.964] <TB2> INFO: Test took 1207ms.
[12:24:30.968] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:31.271] <TB2> INFO: Expecting 2560 events.
[12:24:32.161] <TB2> INFO: 2560 events read in total (298ms).
[12:24:32.161] <TB2> INFO: Test took 1193ms.
[12:24:32.164] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:32.470] <TB2> INFO: Expecting 2560 events.
[12:24:33.363] <TB2> INFO: 2560 events read in total (301ms).
[12:24:33.363] <TB2> INFO: Test took 1199ms.
[12:24:33.366] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:33.671] <TB2> INFO: Expecting 2560 events.
[12:24:34.559] <TB2> INFO: 2560 events read in total (296ms).
[12:24:34.560] <TB2> INFO: Test took 1194ms.
[12:24:34.563] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:34.867] <TB2> INFO: Expecting 2560 events.
[12:24:35.756] <TB2> INFO: 2560 events read in total (297ms).
[12:24:35.756] <TB2> INFO: Test took 1193ms.
[12:24:35.759] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:36.064] <TB2> INFO: Expecting 2560 events.
[12:24:36.956] <TB2> INFO: 2560 events read in total (300ms).
[12:24:36.956] <TB2> INFO: Test took 1197ms.
[12:24:36.959] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:37.265] <TB2> INFO: Expecting 2560 events.
[12:24:38.146] <TB2> INFO: 2560 events read in total (290ms).
[12:24:38.146] <TB2> INFO: Test took 1187ms.
[12:24:38.149] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:38.455] <TB2> INFO: Expecting 2560 events.
[12:24:39.346] <TB2> INFO: 2560 events read in total (299ms).
[12:24:39.346] <TB2> INFO: Test took 1197ms.
[12:24:39.350] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:39.653] <TB2> INFO: Expecting 2560 events.
[12:24:40.540] <TB2> INFO: 2560 events read in total (295ms).
[12:24:40.540] <TB2> INFO: Test took 1191ms.
[12:24:40.542] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:40.849] <TB2> INFO: Expecting 2560 events.
[12:24:41.742] <TB2> INFO: 2560 events read in total (301ms).
[12:24:41.742] <TB2> INFO: Test took 1200ms.
[12:24:41.745] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:42.050] <TB2> INFO: Expecting 2560 events.
[12:24:42.939] <TB2> INFO: 2560 events read in total (297ms).
[12:24:42.939] <TB2> INFO: Test took 1194ms.
[12:24:42.942] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:43.247] <TB2> INFO: Expecting 2560 events.
[12:24:44.133] <TB2> INFO: 2560 events read in total (294ms).
[12:24:44.134] <TB2> INFO: Test took 1192ms.
[12:24:44.137] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:44.442] <TB2> INFO: Expecting 2560 events.
[12:24:45.324] <TB2> INFO: 2560 events read in total (290ms).
[12:24:45.324] <TB2> INFO: Test took 1187ms.
[12:24:45.327] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:45.633] <TB2> INFO: Expecting 2560 events.
[12:24:46.520] <TB2> INFO: 2560 events read in total (295ms).
[12:24:46.521] <TB2> INFO: Test took 1194ms.
[12:24:46.523] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:46.829] <TB2> INFO: Expecting 2560 events.
[12:24:47.718] <TB2> INFO: 2560 events read in total (297ms).
[12:24:47.719] <TB2> INFO: Test took 1196ms.
[12:24:47.723] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:48.028] <TB2> INFO: Expecting 2560 events.
[12:24:48.914] <TB2> INFO: 2560 events read in total (295ms).
[12:24:48.914] <TB2> INFO: Test took 1192ms.
[12:24:48.916] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:49.224] <TB2> INFO: Expecting 2560 events.
[12:24:50.115] <TB2> INFO: 2560 events read in total (299ms).
[12:24:50.115] <TB2> INFO: Test took 1199ms.
[12:24:50.119] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:50.423] <TB2> INFO: Expecting 2560 events.
[12:24:51.313] <TB2> INFO: 2560 events read in total (298ms).
[12:24:51.314] <TB2> INFO: Test took 1196ms.
[12:24:51.316] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:51.623] <TB2> INFO: Expecting 2560 events.
[12:24:52.518] <TB2> INFO: 2560 events read in total (303ms).
[12:24:52.519] <TB2> INFO: Test took 1203ms.
[12:24:52.522] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:52.827] <TB2> INFO: Expecting 2560 events.
[12:24:53.714] <TB2> INFO: 2560 events read in total (295ms).
[12:24:53.715] <TB2> INFO: Test took 1193ms.
[12:24:53.717] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:54.024] <TB2> INFO: Expecting 2560 events.
[12:24:54.916] <TB2> INFO: 2560 events read in total (300ms).
[12:24:54.917] <TB2> INFO: Test took 1200ms.
[12:24:54.920] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:55.225] <TB2> INFO: Expecting 2560 events.
[12:24:56.117] <TB2> INFO: 2560 events read in total (301ms).
[12:24:56.118] <TB2> INFO: Test took 1198ms.
[12:24:56.121] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:56.426] <TB2> INFO: Expecting 2560 events.
[12:24:57.316] <TB2> INFO: 2560 events read in total (298ms).
[12:24:57.316] <TB2> INFO: Test took 1195ms.
[12:24:57.319] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:57.625] <TB2> INFO: Expecting 2560 events.
[12:24:58.518] <TB2> INFO: 2560 events read in total (302ms).
[12:24:58.518] <TB2> INFO: Test took 1199ms.
[12:24:58.521] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:24:58.827] <TB2> INFO: Expecting 2560 events.
[12:24:59.718] <TB2> INFO: 2560 events read in total (300ms).
[12:24:59.719] <TB2> INFO: Test took 1198ms.
[12:24:59.721] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:25:00.026] <TB2> INFO: Expecting 2560 events.
[12:25:00.918] <TB2> INFO: 2560 events read in total (300ms).
[12:25:00.918] <TB2> INFO: Test took 1197ms.
[12:25:00.921] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:25:01.227] <TB2> INFO: Expecting 2560 events.
[12:25:02.118] <TB2> INFO: 2560 events read in total (299ms).
[12:25:02.118] <TB2> INFO: Test took 1197ms.
[12:25:02.122] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:25:02.426] <TB2> INFO: Expecting 2560 events.
[12:25:03.320] <TB2> INFO: 2560 events read in total (303ms).
[12:25:03.321] <TB2> INFO: Test took 1200ms.
[12:25:03.801] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 644 seconds
[12:25:03.801] <TB2> INFO: PH scale (per ROC): 46 46 57 58 42 60 53 58 70 49 47 54 60 46 45 63
[12:25:03.801] <TB2> INFO: PH offset (per ROC): 101 103 138 115 109 139 117 127 121 112 112 109 124 116 85 117
[12:25:03.811] <TB2> INFO: Decoding statistics:
[12:25:03.811] <TB2> INFO: General information:
[12:25:03.811] <TB2> INFO: 16bit words read: 127882
[12:25:03.811] <TB2> INFO: valid events total: 20480
[12:25:03.811] <TB2> INFO: empty events: 17979
[12:25:03.811] <TB2> INFO: valid events with pixels: 2501
[12:25:03.811] <TB2> INFO: valid pixel hits: 2501
[12:25:03.811] <TB2> INFO: Event errors: 0
[12:25:03.811] <TB2> INFO: start marker: 0
[12:25:03.811] <TB2> INFO: stop marker: 0
[12:25:03.811] <TB2> INFO: overflow: 0
[12:25:03.811] <TB2> INFO: invalid 5bit words: 0
[12:25:03.811] <TB2> INFO: invalid XOR eye diagram: 0
[12:25:03.811] <TB2> INFO: frame (failed synchr.): 0
[12:25:03.811] <TB2> INFO: idle data (no TBM trl): 0
[12:25:03.811] <TB2> INFO: no data (only TBM hdr): 0
[12:25:03.811] <TB2> INFO: TBM errors: 0
[12:25:03.811] <TB2> INFO: flawed TBM headers: 0
[12:25:03.811] <TB2> INFO: flawed TBM trailers: 0
[12:25:03.811] <TB2> INFO: event ID mismatches: 0
[12:25:03.811] <TB2> INFO: ROC errors: 0
[12:25:03.811] <TB2> INFO: missing ROC header(s): 0
[12:25:03.811] <TB2> INFO: misplaced readback start: 0
[12:25:03.811] <TB2> INFO: Pixel decoding errors: 0
[12:25:03.811] <TB2> INFO: pixel data incomplete: 0
[12:25:03.811] <TB2> INFO: pixel address: 0
[12:25:03.811] <TB2> INFO: pulse height fill bit: 0
[12:25:03.811] <TB2> INFO: buffer corruption: 0
[12:25:03.967] <TB2> INFO: ######################################################################
[12:25:03.967] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[12:25:03.967] <TB2> INFO: ######################################################################
[12:25:03.984] <TB2> INFO: scanning low vcal = 10
[12:25:04.221] <TB2> INFO: Expecting 41600 events.
[12:25:07.812] <TB2> INFO: 41600 events read in total (2999ms).
[12:25:07.812] <TB2> INFO: Test took 3828ms.
[12:25:07.815] <TB2> INFO: scanning low vcal = 20
[12:25:08.111] <TB2> INFO: Expecting 41600 events.
[12:25:11.685] <TB2> INFO: 41600 events read in total (2982ms).
[12:25:11.685] <TB2> INFO: Test took 3870ms.
[12:25:11.687] <TB2> INFO: scanning low vcal = 30
[12:25:11.980] <TB2> INFO: Expecting 41600 events.
[12:25:15.629] <TB2> INFO: 41600 events read in total (3057ms).
[12:25:15.630] <TB2> INFO: Test took 3943ms.
[12:25:15.632] <TB2> INFO: scanning low vcal = 40
[12:25:15.910] <TB2> INFO: Expecting 41600 events.
[12:25:19.895] <TB2> INFO: 41600 events read in total (3393ms).
[12:25:19.896] <TB2> INFO: Test took 4264ms.
[12:25:19.899] <TB2> INFO: scanning low vcal = 50
[12:25:20.177] <TB2> INFO: Expecting 41600 events.
[12:25:24.152] <TB2> INFO: 41600 events read in total (3383ms).
[12:25:24.153] <TB2> INFO: Test took 4253ms.
[12:25:24.156] <TB2> INFO: scanning low vcal = 60
[12:25:24.435] <TB2> INFO: Expecting 41600 events.
[12:25:28.410] <TB2> INFO: 41600 events read in total (3383ms).
[12:25:28.411] <TB2> INFO: Test took 4254ms.
[12:25:28.415] <TB2> INFO: scanning low vcal = 70
[12:25:28.692] <TB2> INFO: Expecting 41600 events.
[12:25:32.739] <TB2> INFO: 41600 events read in total (3455ms).
[12:25:32.740] <TB2> INFO: Test took 4325ms.
[12:25:32.742] <TB2> INFO: scanning low vcal = 80
[12:25:33.039] <TB2> INFO: Expecting 41600 events.
[12:25:37.022] <TB2> INFO: 41600 events read in total (3391ms).
[12:25:37.023] <TB2> INFO: Test took 4280ms.
[12:25:37.026] <TB2> INFO: scanning low vcal = 90
[12:25:37.303] <TB2> INFO: Expecting 41600 events.
[12:25:41.310] <TB2> INFO: 41600 events read in total (3415ms).
[12:25:41.311] <TB2> INFO: Test took 4285ms.
[12:25:41.317] <TB2> INFO: scanning low vcal = 100
[12:25:41.591] <TB2> INFO: Expecting 41600 events.
[12:25:45.525] <TB2> INFO: 41600 events read in total (3342ms).
[12:25:45.526] <TB2> INFO: Test took 4209ms.
[12:25:45.529] <TB2> INFO: scanning low vcal = 110
[12:25:45.806] <TB2> INFO: Expecting 41600 events.
[12:25:49.752] <TB2> INFO: 41600 events read in total (3354ms).
[12:25:49.753] <TB2> INFO: Test took 4224ms.
[12:25:49.756] <TB2> INFO: scanning low vcal = 120
[12:25:50.033] <TB2> INFO: Expecting 41600 events.
[12:25:53.976] <TB2> INFO: 41600 events read in total (3352ms).
[12:25:53.977] <TB2> INFO: Test took 4221ms.
[12:25:53.980] <TB2> INFO: scanning low vcal = 130
[12:25:54.257] <TB2> INFO: Expecting 41600 events.
[12:25:58.201] <TB2> INFO: 41600 events read in total (3353ms).
[12:25:58.202] <TB2> INFO: Test took 4222ms.
[12:25:58.205] <TB2> INFO: scanning low vcal = 140
[12:25:58.482] <TB2> INFO: Expecting 41600 events.
[12:26:02.441] <TB2> INFO: 41600 events read in total (3368ms).
[12:26:02.442] <TB2> INFO: Test took 4237ms.
[12:26:02.445] <TB2> INFO: scanning low vcal = 150
[12:26:02.722] <TB2> INFO: Expecting 41600 events.
[12:26:06.670] <TB2> INFO: 41600 events read in total (3357ms).
[12:26:06.671] <TB2> INFO: Test took 4226ms.
[12:26:06.674] <TB2> INFO: scanning low vcal = 160
[12:26:06.951] <TB2> INFO: Expecting 41600 events.
[12:26:10.907] <TB2> INFO: 41600 events read in total (3364ms).
[12:26:10.908] <TB2> INFO: Test took 4234ms.
[12:26:10.912] <TB2> INFO: scanning low vcal = 170
[12:26:11.188] <TB2> INFO: Expecting 41600 events.
[12:26:15.204] <TB2> INFO: 41600 events read in total (3425ms).
[12:26:15.204] <TB2> INFO: Test took 4292ms.
[12:26:15.210] <TB2> INFO: scanning low vcal = 180
[12:26:15.484] <TB2> INFO: Expecting 41600 events.
[12:26:19.586] <TB2> INFO: 41600 events read in total (3511ms).
[12:26:19.587] <TB2> INFO: Test took 4377ms.
[12:26:19.590] <TB2> INFO: scanning low vcal = 190
[12:26:19.867] <TB2> INFO: Expecting 41600 events.
[12:26:23.859] <TB2> INFO: 41600 events read in total (3401ms).
[12:26:23.860] <TB2> INFO: Test took 4270ms.
[12:26:23.863] <TB2> INFO: scanning low vcal = 200
[12:26:24.161] <TB2> INFO: Expecting 41600 events.
[12:26:28.166] <TB2> INFO: 41600 events read in total (3413ms).
[12:26:28.167] <TB2> INFO: Test took 4304ms.
[12:26:28.170] <TB2> INFO: scanning low vcal = 210
[12:26:28.446] <TB2> INFO: Expecting 41600 events.
[12:26:32.476] <TB2> INFO: 41600 events read in total (3438ms).
[12:26:32.476] <TB2> INFO: Test took 4306ms.
[12:26:32.479] <TB2> INFO: scanning low vcal = 220
[12:26:32.756] <TB2> INFO: Expecting 41600 events.
[12:26:36.713] <TB2> INFO: 41600 events read in total (3366ms).
[12:26:36.713] <TB2> INFO: Test took 4234ms.
[12:26:36.717] <TB2> INFO: scanning low vcal = 230
[12:26:37.015] <TB2> INFO: Expecting 41600 events.
[12:26:40.970] <TB2> INFO: 41600 events read in total (3363ms).
[12:26:40.970] <TB2> INFO: Test took 4253ms.
[12:26:40.974] <TB2> INFO: scanning low vcal = 240
[12:26:41.250] <TB2> INFO: Expecting 41600 events.
[12:26:45.324] <TB2> INFO: 41600 events read in total (3482ms).
[12:26:45.325] <TB2> INFO: Test took 4351ms.
[12:26:45.328] <TB2> INFO: scanning low vcal = 250
[12:26:45.653] <TB2> INFO: Expecting 41600 events.
[12:26:49.619] <TB2> INFO: 41600 events read in total (3374ms).
[12:26:49.619] <TB2> INFO: Test took 4290ms.
[12:26:49.624] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[12:26:49.899] <TB2> INFO: Expecting 41600 events.
[12:26:53.939] <TB2> INFO: 41600 events read in total (3448ms).
[12:26:53.940] <TB2> INFO: Test took 4316ms.
[12:26:53.943] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[12:26:54.220] <TB2> INFO: Expecting 41600 events.
[12:26:58.177] <TB2> INFO: 41600 events read in total (3366ms).
[12:26:58.178] <TB2> INFO: Test took 4235ms.
[12:26:58.181] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[12:26:58.458] <TB2> INFO: Expecting 41600 events.
[12:27:02.449] <TB2> INFO: 41600 events read in total (3400ms).
[12:27:02.450] <TB2> INFO: Test took 4269ms.
[12:27:02.454] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[12:27:02.730] <TB2> INFO: Expecting 41600 events.
[12:27:06.799] <TB2> INFO: 41600 events read in total (3478ms).
[12:27:06.800] <TB2> INFO: Test took 4346ms.
[12:27:06.803] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[12:27:07.097] <TB2> INFO: Expecting 41600 events.
[12:27:11.150] <TB2> INFO: 41600 events read in total (3461ms).
[12:27:11.151] <TB2> INFO: Test took 4347ms.
[12:27:11.886] <TB2> INFO: PixTestGainPedestal::measure() done
[12:27:43.884] <TB2> INFO: PixTestGainPedestal::fit() done
[12:27:43.884] <TB2> INFO: non-linearity mean: 0.910 0.920 0.978 0.981 0.924 0.980 0.983 0.977 0.985 0.947 0.952 0.957 0.985 0.953 0.920 0.982
[12:27:43.884] <TB2> INFO: non-linearity RMS: 0.068 0.111 0.005 0.004 0.184 0.004 0.003 0.003 0.002 0.048 0.027 0.032 0.003 0.179 0.086 0.003
[12:27:43.884] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[12:27:43.897] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[12:27:43.910] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[12:27:43.923] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[12:27:43.936] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[12:27:43.949] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[12:27:43.963] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[12:27:43.976] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[12:27:43.989] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[12:27:43.002] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[12:27:44.015] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[12:27:44.028] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[12:27:44.041] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[12:27:44.054] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[12:27:44.067] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[12:27:44.080] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1013_FullQualification_2016-10-19_09h44m_1476863092//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[12:27:44.094] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 160 seconds
[12:27:44.094] <TB2> INFO: Decoding statistics:
[12:27:44.094] <TB2> INFO: General information:
[12:27:44.094] <TB2> INFO: 16bit words read: 3327832
[12:27:44.094] <TB2> INFO: valid events total: 332800
[12:27:44.094] <TB2> INFO: empty events: 0
[12:27:44.094] <TB2> INFO: valid events with pixels: 332800
[12:27:44.094] <TB2> INFO: valid pixel hits: 665516
[12:27:44.094] <TB2> INFO: Event errors: 0
[12:27:44.094] <TB2> INFO: start marker: 0
[12:27:44.094] <TB2> INFO: stop marker: 0
[12:27:44.094] <TB2> INFO: overflow: 0
[12:27:44.094] <TB2> INFO: invalid 5bit words: 0
[12:27:44.094] <TB2> INFO: invalid XOR eye diagram: 0
[12:27:44.094] <TB2> INFO: frame (failed synchr.): 0
[12:27:44.094] <TB2> INFO: idle data (no TBM trl): 0
[12:27:44.094] <TB2> INFO: no data (only TBM hdr): 0
[12:27:44.094] <TB2> INFO: TBM errors: 0
[12:27:44.094] <TB2> INFO: flawed TBM headers: 0
[12:27:44.094] <TB2> INFO: flawed TBM trailers: 0
[12:27:44.094] <TB2> INFO: event ID mismatches: 0
[12:27:44.094] <TB2> INFO: ROC errors: 0
[12:27:44.094] <TB2> INFO: missing ROC header(s): 0
[12:27:44.094] <TB2> INFO: misplaced readback start: 0
[12:27:44.094] <TB2> INFO: Pixel decoding errors: 0
[12:27:44.094] <TB2> INFO: pixel data incomplete: 0
[12:27:44.094] <TB2> INFO: pixel address: 0
[12:27:44.094] <TB2> INFO: pulse height fill bit: 0
[12:27:44.094] <TB2> INFO: buffer corruption: 0
[12:27:44.108] <TB2> INFO: Decoding statistics:
[12:27:44.108] <TB2> INFO: General information:
[12:27:44.108] <TB2> INFO: 16bit words read: 3457250
[12:27:44.108] <TB2> INFO: valid events total: 353536
[12:27:44.108] <TB2> INFO: empty events: 18235
[12:27:44.108] <TB2> INFO: valid events with pixels: 335301
[12:27:44.108] <TB2> INFO: valid pixel hits: 668017
[12:27:44.108] <TB2> INFO: Event errors: 0
[12:27:44.108] <TB2> INFO: start marker: 0
[12:27:44.108] <TB2> INFO: stop marker: 0
[12:27:44.108] <TB2> INFO: overflow: 0
[12:27:44.108] <TB2> INFO: invalid 5bit words: 0
[12:27:44.108] <TB2> INFO: invalid XOR eye diagram: 0
[12:27:44.108] <TB2> INFO: frame (failed synchr.): 0
[12:27:44.108] <TB2> INFO: idle data (no TBM trl): 0
[12:27:44.108] <TB2> INFO: no data (only TBM hdr): 0
[12:27:44.108] <TB2> INFO: TBM errors: 0
[12:27:44.108] <TB2> INFO: flawed TBM headers: 0
[12:27:44.108] <TB2> INFO: flawed TBM trailers: 0
[12:27:44.108] <TB2> INFO: event ID mismatches: 0
[12:27:44.108] <TB2> INFO: ROC errors: 0
[12:27:44.108] <TB2> INFO: missing ROC header(s): 0
[12:27:44.108] <TB2> INFO: misplaced readback start: 0
[12:27:44.108] <TB2> INFO: Pixel decoding errors: 0
[12:27:44.108] <TB2> INFO: pixel data incomplete: 0
[12:27:44.108] <TB2> INFO: pixel address: 0
[12:27:44.108] <TB2> INFO: pulse height fill bit: 0
[12:27:44.108] <TB2> INFO: buffer corruption: 0
[12:27:44.108] <TB2> INFO: enter test to run
[12:27:44.108] <TB2> INFO: test: exit no parameter change
[12:27:44.229] <TB2> QUIET: Connection to board 149 closed.
[12:27:44.230] <TB2> INFO: pXar: this is the end, my friend