[11:45:39.000] <TB1> INFO: *** Welcome to pxar ***
[11:45:39.000] <TB1> INFO: *** Today: 2016/11/14
[11:45:40.009] <TB1> INFO: *** Version: c8ba-dirty
[11:45:40.009] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C15.dat
[11:45:40.009] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//tbmParameters_C1b.dat
[11:45:40.009] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//defaultMaskFile.dat
[11:45:40.010] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters_C15.dat
[11:45:40.075] <TB1> INFO: clk: 4
[11:45:40.075] <TB1> INFO: ctr: 4
[11:45:40.075] <TB1> INFO: sda: 19
[11:45:40.075] <TB1> INFO: tin: 9
[11:45:40.075] <TB1> INFO: level: 15
[11:45:40.075] <TB1> INFO: triggerdelay: 0
[11:45:40.075] <TB1> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[11:45:40.075] <TB1> INFO: Log level: INFO
[11:45:40.083] <TB1> INFO: Found DTB DTB_WXC03A
[11:45:40.095] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[11:45:40.096] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
------------------------------------------------------
[11:45:40.098] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[11:45:41.589] <TB1> INFO: DUT info:
[11:45:41.589] <TB1> INFO: The DUT currently contains the following objects:
[11:45:41.589] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[11:45:41.589] <TB1> INFO: TBM Core alpha (0): 7 registers set
[11:45:41.589] <TB1> INFO: TBM Core beta (1): 7 registers set
[11:45:41.589] <TB1> INFO: TBM Core alpha (2): 7 registers set
[11:45:41.589] <TB1> INFO: TBM Core beta (3): 7 registers set
[11:45:41.589] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[11:45:41.589] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:41.589] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:41.589] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:41.589] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:41.589] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:41.589] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:41.589] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:41.589] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:41.589] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:41.590] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:41.590] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:41.590] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:41.590] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:41.590] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:41.590] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:41.590] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:45:41.990] <TB1> INFO: enter 'restricted' command line mode
[11:45:41.991] <TB1> INFO: enter test to run
[11:45:41.991] <TB1> INFO: test: pretest no parameter change
[11:45:41.991] <TB1> INFO: running: pretest
[11:45:41.997] <TB1> INFO: ######################################################################
[11:45:41.997] <TB1> INFO: PixTestPretest::doTest()
[11:45:41.997] <TB1> INFO: ######################################################################
[11:45:41.998] <TB1> INFO: ----------------------------------------------------------------------
[11:45:41.998] <TB1> INFO: PixTestPretest::programROC()
[11:45:41.998] <TB1> INFO: ----------------------------------------------------------------------
[11:46:00.011] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:46:00.011] <TB1> INFO: IA differences per ROC: 16.9 19.3 18.5 16.9 17.7 16.9 19.3 20.1 20.1 20.1 20.9 16.9 20.1 20.1 16.9 20.1
[11:46:00.071] <TB1> INFO: ----------------------------------------------------------------------
[11:46:00.071] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:46:00.071] <TB1> INFO: ----------------------------------------------------------------------
[11:46:21.371] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 400.3 mA = 25.0188 mA/ROC
[11:46:21.372] <TB1> INFO: i(loss) [mA/ROC]: 20.1 20.9 20.9 19.3 20.9 20.1 21.7 18.4 20.9 19.3 19.3 19.3 19.3 19.3 20.1 20.9
[11:46:21.407] <TB1> INFO: ----------------------------------------------------------------------
[11:46:21.407] <TB1> INFO: PixTestPretest::findTiming()
[11:46:21.407] <TB1> INFO: ----------------------------------------------------------------------
[11:46:21.407] <TB1> INFO: PixTestCmd::init()

[11:46:53.713] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[11:46:53.713] <TB1> INFO: (success/tries = 100/100), width = 3
[11:46:55.217] <TB1> INFO: ----------------------------------------------------------------------
[11:46:55.217] <TB1> INFO: PixTestPretest::findWorkingPixel()
[11:46:55.217] <TB1> INFO: ----------------------------------------------------------------------
[11:46:55.310] <TB1> INFO: Expecting 231680 events.
[11:47:05.188] <TB1> INFO: 231680 events read in total (9286ms).
[11:47:05.195] <TB1> INFO: Test took 9976ms.
[11:47:05.444] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:47:05.474] <TB1> INFO: ----------------------------------------------------------------------
[11:47:05.474] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[11:47:05.474] <TB1> INFO: ----------------------------------------------------------------------
[11:47:05.569] <TB1> INFO: Expecting 231680 events.
[11:47:15.405] <TB1> INFO: 231680 events read in total (9245ms).
[11:47:15.414] <TB1> INFO: Test took 9934ms.
[11:47:15.677] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[11:47:15.677] <TB1> INFO: CalDel: 86 102 83 91 84 86 81 101 111 96 92 78 99 111 92 99
[11:47:15.677] <TB1> INFO: VthrComp: 51 56 55 52 51 54 54 51 51 54 54 54 52 57 52 56
[11:47:15.682] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C0.dat
[11:47:15.683] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C1.dat
[11:47:15.683] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C2.dat
[11:47:15.683] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C3.dat
[11:47:15.683] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C4.dat
[11:47:15.683] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C5.dat
[11:47:15.684] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C6.dat
[11:47:15.684] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C7.dat
[11:47:15.684] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C8.dat
[11:47:15.684] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C9.dat
[11:47:15.684] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C10.dat
[11:47:15.684] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C11.dat
[11:47:15.685] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C12.dat
[11:47:15.685] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C13.dat
[11:47:15.685] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C14.dat
[11:47:15.685] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters_C15.dat
[11:47:15.685] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//tbmParameters_C0a.dat
[11:47:15.685] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//tbmParameters_C0b.dat
[11:47:15.685] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//tbmParameters_C1a.dat
[11:47:15.685] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//tbmParameters_C1b.dat
[11:47:15.686] <TB1> INFO: PixTestPretest::doTest() done, duration: 93 seconds
[11:47:15.741] <TB1> INFO: enter test to run
[11:47:15.741] <TB1> INFO: test: FullTest no parameter change
[11:47:15.741] <TB1> INFO: running: fulltest
[11:47:15.741] <TB1> INFO: ######################################################################
[11:47:15.741] <TB1> INFO: PixTestFullTest::doTest()
[11:47:15.741] <TB1> INFO: ######################################################################
[11:47:15.742] <TB1> INFO: ######################################################################
[11:47:15.742] <TB1> INFO: PixTestAlive::doTest()
[11:47:15.742] <TB1> INFO: ######################################################################
[11:47:15.743] <TB1> INFO: ----------------------------------------------------------------------
[11:47:15.743] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:47:15.743] <TB1> INFO: ----------------------------------------------------------------------
[11:47:15.980] <TB1> INFO: Expecting 41600 events.
[11:47:19.519] <TB1> INFO: 41600 events read in total (2947ms).
[11:47:19.519] <TB1> INFO: Test took 3774ms.
[11:47:19.751] <TB1> INFO: PixTestAlive::aliveTest() done
[11:47:19.751] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
[11:47:19.753] <TB1> INFO: ----------------------------------------------------------------------
[11:47:19.753] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:47:19.753] <TB1> INFO: ----------------------------------------------------------------------
[11:47:19.998] <TB1> INFO: Expecting 41600 events.
[11:47:23.004] <TB1> INFO: 41600 events read in total (2414ms).
[11:47:23.004] <TB1> INFO: Test took 3249ms.
[11:47:23.004] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:47:23.238] <TB1> INFO: PixTestAlive::maskTest() done
[11:47:23.238] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:47:23.239] <TB1> INFO: ----------------------------------------------------------------------
[11:47:23.239] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:47:23.239] <TB1> INFO: ----------------------------------------------------------------------
[11:47:23.485] <TB1> INFO: Expecting 41600 events.
[11:47:27.018] <TB1> INFO: 41600 events read in total (2941ms).
[11:47:27.019] <TB1> INFO: Test took 3779ms.
[11:47:27.253] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[11:47:27.253] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:47:27.253] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[11:47:27.253] <TB1> INFO: Decoding statistics:
[11:47:27.253] <TB1> INFO: General information:
[11:47:27.253] <TB1> INFO: 16bit words read: 0
[11:47:27.253] <TB1> INFO: valid events total: 0
[11:47:27.253] <TB1> INFO: empty events: 0
[11:47:27.253] <TB1> INFO: valid events with pixels: 0
[11:47:27.253] <TB1> INFO: valid pixel hits: 0
[11:47:27.253] <TB1> INFO: Event errors: 0
[11:47:27.253] <TB1> INFO: start marker: 0
[11:47:27.253] <TB1> INFO: stop marker: 0
[11:47:27.253] <TB1> INFO: overflow: 0
[11:47:27.253] <TB1> INFO: invalid 5bit words: 0
[11:47:27.253] <TB1> INFO: invalid XOR eye diagram: 0
[11:47:27.253] <TB1> INFO: frame (failed synchr.): 0
[11:47:27.253] <TB1> INFO: idle data (no TBM trl): 0
[11:47:27.253] <TB1> INFO: no data (only TBM hdr): 0
[11:47:27.253] <TB1> INFO: TBM errors: 0
[11:47:27.253] <TB1> INFO: flawed TBM headers: 0
[11:47:27.253] <TB1> INFO: flawed TBM trailers: 0
[11:47:27.253] <TB1> INFO: event ID mismatches: 0
[11:47:27.253] <TB1> INFO: ROC errors: 0
[11:47:27.253] <TB1> INFO: missing ROC header(s): 0
[11:47:27.253] <TB1> INFO: misplaced readback start: 0
[11:47:27.253] <TB1> INFO: Pixel decoding errors: 0
[11:47:27.253] <TB1> INFO: pixel data incomplete: 0
[11:47:27.253] <TB1> INFO: pixel address: 0
[11:47:27.253] <TB1> INFO: pulse height fill bit: 0
[11:47:27.253] <TB1> INFO: buffer corruption: 0
[11:47:27.260] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C15.dat
[11:47:27.261] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr_C15.dat

[11:47:27.261] <TB1> INFO: ######################################################################
[11:47:27.261] <TB1> INFO: PixTestReadback::doTest()
[11:47:27.261] <TB1> INFO: ######################################################################
[11:47:27.261] <TB1> INFO: ----------------------------------------------------------------------
[11:47:27.261] <TB1> INFO: PixTestReadback::CalibrateVd()
[11:47:27.261] <TB1> INFO: ----------------------------------------------------------------------
[11:47:37.224] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C0.dat
[11:47:37.224] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C1.dat
[11:47:37.224] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C2.dat
[11:47:37.225] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C3.dat
[11:47:37.225] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C4.dat
[11:47:37.225] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C5.dat
[11:47:37.225] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C6.dat
[11:47:37.225] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C7.dat
[11:47:37.225] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C8.dat
[11:47:37.225] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C9.dat
[11:47:37.225] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C10.dat
[11:47:37.226] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C11.dat
[11:47:37.226] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C12.dat
[11:47:37.226] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C13.dat
[11:47:37.226] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C14.dat
[11:47:37.226] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C15.dat
[11:47:37.256] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:47:37.256] <TB1> INFO: ----------------------------------------------------------------------
[11:47:37.257] <TB1> INFO: PixTestReadback::CalibrateVa()
[11:47:37.257] <TB1> INFO: ----------------------------------------------------------------------
[11:47:47.186] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C0.dat
[11:47:47.186] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C1.dat
[11:47:47.186] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C2.dat
[11:47:47.186] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C3.dat
[11:47:47.186] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C4.dat
[11:47:47.186] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C5.dat
[11:47:47.186] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C6.dat
[11:47:47.186] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C7.dat
[11:47:47.186] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C8.dat
[11:47:47.187] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C9.dat
[11:47:47.187] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C10.dat
[11:47:47.187] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C11.dat
[11:47:47.187] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C12.dat
[11:47:47.187] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C13.dat
[11:47:47.187] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C14.dat
[11:47:47.187] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C15.dat
[11:47:47.217] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:47:47.217] <TB1> INFO: ----------------------------------------------------------------------
[11:47:47.217] <TB1> INFO: PixTestReadback::readbackVbg()
[11:47:47.217] <TB1> INFO: ----------------------------------------------------------------------
[11:47:54.887] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:47:54.887] <TB1> INFO: ----------------------------------------------------------------------
[11:47:54.887] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[11:47:54.887] <TB1> INFO: ----------------------------------------------------------------------
[11:47:54.887] <TB1> INFO: Vbg will be calibrated using Vd calibration
[11:47:54.887] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 158.5calibrated Vbg = 1.198 :::*/*/*/*/
[11:47:54.887] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 163.2calibrated Vbg = 1.19345 :::*/*/*/*/
[11:47:54.887] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 153.2calibrated Vbg = 1.19664 :::*/*/*/*/
[11:47:54.887] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 158.6calibrated Vbg = 1.1902 :::*/*/*/*/
[11:47:54.888] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 157.5calibrated Vbg = 1.18806 :::*/*/*/*/
[11:47:54.888] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 156.4calibrated Vbg = 1.19227 :::*/*/*/*/
[11:47:54.888] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 158.9calibrated Vbg = 1.20228 :::*/*/*/*/
[11:47:54.888] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 150.5calibrated Vbg = 1.19781 :::*/*/*/*/
[11:47:54.888] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 157.9calibrated Vbg = 1.19205 :::*/*/*/*/
[11:47:54.888] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 163.4calibrated Vbg = 1.19107 :::*/*/*/*/
[11:47:54.888] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 162.3calibrated Vbg = 1.18207 :::*/*/*/*/
[11:47:54.888] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 159.2calibrated Vbg = 1.1748 :::*/*/*/*/
[11:47:54.888] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 158.7calibrated Vbg = 1.19346 :::*/*/*/*/
[11:47:54.888] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 159calibrated Vbg = 1.19696 :::*/*/*/*/
[11:47:54.888] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 160calibrated Vbg = 1.19419 :::*/*/*/*/
[11:47:54.888] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 160.1calibrated Vbg = 1.19343 :::*/*/*/*/
[11:47:54.890] <TB1> INFO: ----------------------------------------------------------------------
[11:47:54.890] <TB1> INFO: PixTestReadback::CalibrateIa()
[11:47:54.890] <TB1> INFO: ----------------------------------------------------------------------
[11:50:35.733] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C0.dat
[11:50:35.733] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C1.dat
[11:50:35.733] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C2.dat
[11:50:35.733] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C3.dat
[11:50:35.733] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C4.dat
[11:50:35.733] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C5.dat
[11:50:35.733] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C6.dat
[11:50:35.733] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C7.dat
[11:50:35.733] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C8.dat
[11:50:35.734] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C9.dat
[11:50:35.734] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C10.dat
[11:50:35.734] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C11.dat
[11:50:35.734] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C12.dat
[11:50:35.734] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C13.dat
[11:50:35.734] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C14.dat
[11:50:35.734] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//readbackCal_C15.dat
[11:50:35.764] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[11:50:35.765] <TB1> INFO: PixTestReadback::doTest() done
[11:50:35.766] <TB1> INFO: Decoding statistics:
[11:50:35.766] <TB1> INFO: General information:
[11:50:35.766] <TB1> INFO: 16bit words read: 1536
[11:50:35.766] <TB1> INFO: valid events total: 256
[11:50:35.766] <TB1> INFO: empty events: 256
[11:50:35.766] <TB1> INFO: valid events with pixels: 0
[11:50:35.766] <TB1> INFO: valid pixel hits: 0
[11:50:35.766] <TB1> INFO: Event errors: 0
[11:50:35.766] <TB1> INFO: start marker: 0
[11:50:35.766] <TB1> INFO: stop marker: 0
[11:50:35.766] <TB1> INFO: overflow: 0
[11:50:35.766] <TB1> INFO: invalid 5bit words: 0
[11:50:35.766] <TB1> INFO: invalid XOR eye diagram: 0
[11:50:35.766] <TB1> INFO: frame (failed synchr.): 0
[11:50:35.766] <TB1> INFO: idle data (no TBM trl): 0
[11:50:35.766] <TB1> INFO: no data (only TBM hdr): 0
[11:50:35.766] <TB1> INFO: TBM errors: 0
[11:50:35.766] <TB1> INFO: flawed TBM headers: 0
[11:50:35.766] <TB1> INFO: flawed TBM trailers: 0
[11:50:35.766] <TB1> INFO: event ID mismatches: 0
[11:50:35.766] <TB1> INFO: ROC errors: 0
[11:50:35.766] <TB1> INFO: missing ROC header(s): 0
[11:50:35.766] <TB1> INFO: misplaced readback start: 0
[11:50:35.766] <TB1> INFO: Pixel decoding errors: 0
[11:50:35.766] <TB1> INFO: pixel data incomplete: 0
[11:50:35.766] <TB1> INFO: pixel address: 0
[11:50:35.766] <TB1> INFO: pulse height fill bit: 0
[11:50:35.766] <TB1> INFO: buffer corruption: 0
[11:50:35.819] <TB1> INFO: ######################################################################
[11:50:35.819] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[11:50:35.819] <TB1> INFO: ######################################################################
[11:50:35.822] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[11:50:35.891] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[11:50:35.891] <TB1> INFO: run 1 of 1
[11:50:36.129] <TB1> INFO: Expecting 3120000 events.
[11:51:07.289] <TB1> INFO: 677750 events read in total (30568ms).











[11:51:37.482] <TB1> INFO: 1352135 events read in total (60762ms).











[11:52:07.547] <TB1> INFO: 2023875 events read in total (90827ms).











[11:52:38.107] <TB1> INFO: 2696945 events read in total (121386ms).











[11:52:57.358] <TB1> INFO: 3120000 events read in total (140637ms).
[11:52:57.436] <TB1> INFO: Test took 141546ms.
[11:53:23.871] <TB1> INFO: PixTestBBMap::doTest() done with 4 decoding errors: , duration: 168 seconds
[11:53:23.872] <TB1> INFO: number of dead bumps (per ROC): 12 1 0 0 0 0 0 0 0 3 0 0 0 0 3 3
[11:53:23.872] <TB1> INFO: separation cut (per ROC): 105 133 131 105 101 118 121 96 116 121 128 120 112 108 111 127
[11:53:23.872] <TB1> INFO: Decoding statistics:
[11:53:23.872] <TB1> INFO: General information:
[11:53:23.872] <TB1> INFO: 16bit words read: 0
[11:53:23.872] <TB1> INFO: valid events total: 0
[11:53:23.872] <TB1> INFO: empty events: 0
[11:53:23.872] <TB1> INFO: valid events with pixels: 0
[11:53:23.872] <TB1> INFO: valid pixel hits: 0
[11:53:23.872] <TB1> INFO: Event errors: 0
[11:53:23.872] <TB1> INFO: start marker: 0
[11:53:23.872] <TB1> INFO: stop marker: 0
[11:53:23.872] <TB1> INFO: overflow: 0
[11:53:23.872] <TB1> INFO: invalid 5bit words: 0
[11:53:23.872] <TB1> INFO: invalid XOR eye diagram: 0
[11:53:23.872] <TB1> INFO: frame (failed synchr.): 0
[11:53:23.872] <TB1> INFO: idle data (no TBM trl): 0
[11:53:23.872] <TB1> INFO: no data (only TBM hdr): 0
[11:53:23.872] <TB1> INFO: TBM errors: 0
[11:53:23.872] <TB1> INFO: flawed TBM headers: 0
[11:53:23.872] <TB1> INFO: flawed TBM trailers: 0
[11:53:23.872] <TB1> INFO: event ID mismatches: 0
[11:53:23.872] <TB1> INFO: ROC errors: 0
[11:53:23.872] <TB1> INFO: missing ROC header(s): 0
[11:53:23.872] <TB1> INFO: misplaced readback start: 0
[11:53:23.872] <TB1> INFO: Pixel decoding errors: 0
[11:53:23.872] <TB1> INFO: pixel data incomplete: 0
[11:53:23.872] <TB1> INFO: pixel address: 0
[11:53:23.872] <TB1> INFO: pulse height fill bit: 0
[11:53:23.872] <TB1> INFO: buffer corruption: 0
[11:53:23.918] <TB1> INFO: ######################################################################
[11:53:23.918] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:53:23.918] <TB1> INFO: ######################################################################
[11:53:23.918] <TB1> INFO: ----------------------------------------------------------------------
[11:53:23.918] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:53:23.918] <TB1> INFO: ----------------------------------------------------------------------
[11:53:23.918] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[11:53:23.933] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[11:53:23.934] <TB1> INFO: run 1 of 1
[11:53:24.193] <TB1> INFO: Expecting 36608000 events.
[11:53:47.996] <TB1> INFO: 708650 events read in total (23212ms).
[11:54:11.041] <TB1> INFO: 1401500 events read in total (46257ms).
[11:54:33.922] <TB1> INFO: 2093800 events read in total (69138ms).
[11:54:56.893] <TB1> INFO: 2786900 events read in total (92109ms).
[11:55:19.776] <TB1> INFO: 3478450 events read in total (114992ms).
[11:55:42.658] <TB1> INFO: 4170500 events read in total (137874ms).
[11:56:05.816] <TB1> INFO: 4862700 events read in total (161032ms).
[11:56:28.709] <TB1> INFO: 5552700 events read in total (183925ms).
[11:56:51.660] <TB1> INFO: 6245150 events read in total (206876ms).
[11:57:14.830] <TB1> INFO: 6937300 events read in total (230046ms).
[11:57:37.792] <TB1> INFO: 7627800 events read in total (253008ms).
[11:58:00.584] <TB1> INFO: 8316850 events read in total (275800ms).
[11:58:23.613] <TB1> INFO: 9008650 events read in total (298830ms).
[11:58:46.638] <TB1> INFO: 9699350 events read in total (321854ms).
[11:59:09.644] <TB1> INFO: 10388600 events read in total (344860ms).
[11:59:32.268] <TB1> INFO: 11076600 events read in total (367484ms).
[11:59:55.334] <TB1> INFO: 11764350 events read in total (390550ms).
[12:00:18.531] <TB1> INFO: 12453600 events read in total (413747ms).
[12:00:41.719] <TB1> INFO: 13142200 events read in total (436935ms).
[12:01:04.951] <TB1> INFO: 13830800 events read in total (460167ms).
[12:01:27.931] <TB1> INFO: 14518100 events read in total (483147ms).
[12:01:51.045] <TB1> INFO: 15205300 events read in total (506261ms).
[12:02:14.128] <TB1> INFO: 15891500 events read in total (529344ms).
[12:02:37.254] <TB1> INFO: 16577900 events read in total (552470ms).
[12:03:00.443] <TB1> INFO: 17263900 events read in total (575659ms).
[12:03:23.389] <TB1> INFO: 17948450 events read in total (598605ms).
[12:03:46.412] <TB1> INFO: 18632800 events read in total (621628ms).
[12:04:09.540] <TB1> INFO: 19316750 events read in total (644756ms).
[12:04:32.504] <TB1> INFO: 20000650 events read in total (667720ms).
[12:04:55.317] <TB1> INFO: 20682950 events read in total (690533ms).
[12:05:18.421] <TB1> INFO: 21364500 events read in total (713637ms).
[12:05:41.410] <TB1> INFO: 22045700 events read in total (736626ms).
[12:06:04.680] <TB1> INFO: 22728300 events read in total (759896ms).
[12:06:27.604] <TB1> INFO: 23411350 events read in total (782820ms).
[12:06:50.525] <TB1> INFO: 24093150 events read in total (805741ms).
[12:07:13.764] <TB1> INFO: 24774950 events read in total (828980ms).
[12:07:36.792] <TB1> INFO: 25458050 events read in total (852008ms).
[12:07:59.690] <TB1> INFO: 26139050 events read in total (874906ms).
[12:08:22.693] <TB1> INFO: 26821350 events read in total (897909ms).
[12:08:45.948] <TB1> INFO: 27503600 events read in total (921164ms).
[12:09:08.802] <TB1> INFO: 28184450 events read in total (944018ms).
[12:09:31.715] <TB1> INFO: 28864000 events read in total (966931ms).
[12:09:54.608] <TB1> INFO: 29547500 events read in total (989824ms).
[12:10:17.853] <TB1> INFO: 30227500 events read in total (1013069ms).
[12:10:40.969] <TB1> INFO: 30909000 events read in total (1036185ms).
[12:11:03.752] <TB1> INFO: 31590000 events read in total (1058968ms).
[12:11:26.632] <TB1> INFO: 32272900 events read in total (1081848ms).
[12:11:49.480] <TB1> INFO: 32954950 events read in total (1104696ms).
[12:12:12.499] <TB1> INFO: 33638950 events read in total (1127715ms).
[12:12:35.768] <TB1> INFO: 34320800 events read in total (1150984ms).
[12:12:59.033] <TB1> INFO: 35004500 events read in total (1174249ms).
[12:13:22.077] <TB1> INFO: 35688300 events read in total (1197293ms).
[12:13:45.127] <TB1> INFO: 36382450 events read in total (1220343ms).
[12:13:52.816] <TB1> INFO: 36608000 events read in total (1228032ms).
[12:13:52.887] <TB1> INFO: Test took 1228953ms.
[12:13:53.190] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:13:55.004] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:13:56.997] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:13:58.873] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:14:00.671] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:14:02.313] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:14:03.847] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:14:05.368] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:14:06.955] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:14:08.526] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:14:10.058] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:14:11.693] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:14:13.282] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:14:14.749] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:14:16.263] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:14:17.791] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[12:14:19.760] <TB1> INFO: PixTestScurves::scurves() done
[12:14:19.760] <TB1> INFO: Vcal mean: 128.75 139.99 138.50 125.80 114.05 132.97 134.03 120.27 136.24 136.75 135.61 134.38 137.73 130.90 135.83 135.67
[12:14:19.760] <TB1> INFO: Vcal RMS: 5.98 5.74 6.17 6.69 5.03 6.10 6.12 6.51 6.36 6.23 5.72 6.29 6.18 6.39 6.13 6.28
[12:14:19.760] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1255 seconds
[12:14:19.760] <TB1> INFO: Decoding statistics:
[12:14:19.760] <TB1> INFO: General information:
[12:14:19.760] <TB1> INFO: 16bit words read: 0
[12:14:19.760] <TB1> INFO: valid events total: 0
[12:14:19.760] <TB1> INFO: empty events: 0
[12:14:19.760] <TB1> INFO: valid events with pixels: 0
[12:14:19.760] <TB1> INFO: valid pixel hits: 0
[12:14:19.760] <TB1> INFO: Event errors: 0
[12:14:19.760] <TB1> INFO: start marker: 0
[12:14:19.760] <TB1> INFO: stop marker: 0
[12:14:19.760] <TB1> INFO: overflow: 0
[12:14:19.760] <TB1> INFO: invalid 5bit words: 0
[12:14:19.760] <TB1> INFO: invalid XOR eye diagram: 0
[12:14:19.760] <TB1> INFO: frame (failed synchr.): 0
[12:14:19.760] <TB1> INFO: idle data (no TBM trl): 0
[12:14:19.760] <TB1> INFO: no data (only TBM hdr): 0
[12:14:19.760] <TB1> INFO: TBM errors: 0
[12:14:19.760] <TB1> INFO: flawed TBM headers: 0
[12:14:19.760] <TB1> INFO: flawed TBM trailers: 0
[12:14:19.760] <TB1> INFO: event ID mismatches: 0
[12:14:19.760] <TB1> INFO: ROC errors: 0
[12:14:19.760] <TB1> INFO: missing ROC header(s): 0
[12:14:19.760] <TB1> INFO: misplaced readback start: 0
[12:14:19.760] <TB1> INFO: Pixel decoding errors: 0
[12:14:19.760] <TB1> INFO: pixel data incomplete: 0
[12:14:19.761] <TB1> INFO: pixel address: 0
[12:14:19.761] <TB1> INFO: pulse height fill bit: 0
[12:14:19.761] <TB1> INFO: buffer corruption: 0
[12:14:19.840] <TB1> INFO: ######################################################################
[12:14:19.840] <TB1> INFO: PixTestTrim::doTest()
[12:14:19.840] <TB1> INFO: ######################################################################
[12:14:19.842] <TB1> INFO: ----------------------------------------------------------------------
[12:14:19.842] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[12:14:19.842] <TB1> INFO: ----------------------------------------------------------------------
[12:14:19.900] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:14:19.900] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:14:19.914] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:14:19.915] <TB1> INFO: run 1 of 1
[12:14:20.193] <TB1> INFO: Expecting 5025280 events.
[12:14:52.235] <TB1> INFO: 839384 events read in total (31432ms).
[12:15:22.596] <TB1> INFO: 1676608 events read in total (61793ms).
[12:15:52.628] <TB1> INFO: 2511816 events read in total (91826ms).
[12:16:22.729] <TB1> INFO: 3343288 events read in total (121926ms).
[12:16:52.963] <TB1> INFO: 4172320 events read in total (152160ms).
[12:17:23.320] <TB1> INFO: 5001872 events read in total (182517ms).
[12:17:24.558] <TB1> INFO: 5025280 events read in total (183755ms).
[12:17:24.608] <TB1> INFO: Test took 184693ms.
[12:17:37.515] <TB1> INFO: ROC 0 VthrComp = 124
[12:17:37.515] <TB1> INFO: ROC 1 VthrComp = 136
[12:17:37.515] <TB1> INFO: ROC 2 VthrComp = 134
[12:17:37.515] <TB1> INFO: ROC 3 VthrComp = 128
[12:17:37.515] <TB1> INFO: ROC 4 VthrComp = 113
[12:17:37.515] <TB1> INFO: ROC 5 VthrComp = 133
[12:17:37.515] <TB1> INFO: ROC 6 VthrComp = 132
[12:17:37.516] <TB1> INFO: ROC 7 VthrComp = 113
[12:17:37.516] <TB1> INFO: ROC 8 VthrComp = 132
[12:17:37.516] <TB1> INFO: ROC 9 VthrComp = 133
[12:17:37.516] <TB1> INFO: ROC 10 VthrComp = 134
[12:17:37.516] <TB1> INFO: ROC 11 VthrComp = 131
[12:17:37.516] <TB1> INFO: ROC 12 VthrComp = 133
[12:17:37.516] <TB1> INFO: ROC 13 VthrComp = 129
[12:17:37.516] <TB1> INFO: ROC 14 VthrComp = 130
[12:17:37.516] <TB1> INFO: ROC 15 VthrComp = 136
[12:17:37.779] <TB1> INFO: Expecting 41600 events.
[12:17:41.342] <TB1> INFO: 41600 events read in total (2972ms).
[12:17:41.343] <TB1> INFO: Test took 3825ms.
[12:17:41.353] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:17:41.353] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:17:41.365] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:17:41.365] <TB1> INFO: run 1 of 1
[12:17:41.643] <TB1> INFO: Expecting 5025280 events.
[12:18:08.741] <TB1> INFO: 592808 events read in total (26507ms).
[12:18:34.166] <TB1> INFO: 1184832 events read in total (51932ms).
[12:19:00.233] <TB1> INFO: 1776664 events read in total (77999ms).
[12:19:25.887] <TB1> INFO: 2367856 events read in total (103653ms).
[12:19:52.127] <TB1> INFO: 2956760 events read in total (129893ms).
[12:20:17.729] <TB1> INFO: 3545152 events read in total (155495ms).
[12:20:43.629] <TB1> INFO: 4133288 events read in total (181395ms).
[12:21:09.569] <TB1> INFO: 4721816 events read in total (207335ms).
[12:21:23.271] <TB1> INFO: 5025280 events read in total (221037ms).
[12:21:23.372] <TB1> INFO: Test took 222007ms.
[12:21:46.079] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 63.7376 for pixel 15/9 mean/min/max = 47.7504/31.5517/63.9492
[12:21:46.079] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 69.3979 for pixel 0/1 mean/min/max = 53.3346/36.7077/69.9614
[12:21:46.079] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 70.0699 for pixel 0/31 mean/min/max = 54.7553/38.2926/71.2179
[12:21:46.080] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 62.2583 for pixel 0/9 mean/min/max = 46.9494/31.5741/62.3247
[12:21:46.080] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 60.6427 for pixel 0/1 mean/min/max = 46.949/33.0825/60.8154
[12:21:46.081] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 61.6057 for pixel 0/0 mean/min/max = 46.7028/31.7869/61.6187
[12:21:46.081] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 69.3489 for pixel 0/20 mean/min/max = 53.0932/36.8251/69.3614
[12:21:46.082] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 64.5857 for pixel 0/17 mean/min/max = 48.4795/32.2605/64.6985
[12:21:46.082] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 62.2084 for pixel 51/67 mean/min/max = 47.0868/31.6095/62.564
[12:21:46.082] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 69.4157 for pixel 17/3 mean/min/max = 51.4888/33.4958/69.4818
[12:21:46.083] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 68.6409 for pixel 4/2 mean/min/max = 52.3158/35.6843/68.9473
[12:21:46.083] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 67.0564 for pixel 0/3 mean/min/max = 49.7646/32.3744/67.1547
[12:21:46.083] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 62.6285 for pixel 12/6 mean/min/max = 48.2726/33.7219/62.8233
[12:21:46.084] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 64.8244 for pixel 22/2 mean/min/max = 48.5734/32.2531/64.8937
[12:21:46.084] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 64.3526 for pixel 18/10 mean/min/max = 48.1935/31.8634/64.5236
[12:21:46.085] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 67.9568 for pixel 3/8 mean/min/max = 51.315/34.623/68.0069
[12:21:46.085] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:21:46.174] <TB1> INFO: Expecting 411648 events.
[12:21:55.624] <TB1> INFO: 411648 events read in total (8859ms).
[12:21:55.634] <TB1> INFO: Expecting 411648 events.
[12:22:04.955] <TB1> INFO: 411648 events read in total (8918ms).
[12:22:04.969] <TB1> INFO: Expecting 411648 events.
[12:22:14.481] <TB1> INFO: 411648 events read in total (9109ms).
[12:22:14.500] <TB1> INFO: Expecting 411648 events.
[12:22:23.920] <TB1> INFO: 411648 events read in total (9017ms).
[12:22:23.940] <TB1> INFO: Expecting 411648 events.
[12:22:33.148] <TB1> INFO: 411648 events read in total (8805ms).
[12:22:33.169] <TB1> INFO: Expecting 411648 events.
[12:22:42.398] <TB1> INFO: 411648 events read in total (8826ms).
[12:22:42.420] <TB1> INFO: Expecting 411648 events.
[12:22:51.673] <TB1> INFO: 411648 events read in total (8850ms).
[12:22:51.697] <TB1> INFO: Expecting 411648 events.
[12:23:00.916] <TB1> INFO: 411648 events read in total (8816ms).
[12:23:00.943] <TB1> INFO: Expecting 411648 events.
[12:23:10.351] <TB1> INFO: 411648 events read in total (9005ms).
[12:23:10.397] <TB1> INFO: Expecting 411648 events.
[12:23:19.789] <TB1> INFO: 411648 events read in total (8989ms).
[12:23:19.847] <TB1> INFO: Expecting 411648 events.
[12:23:29.219] <TB1> INFO: 411648 events read in total (8969ms).
[12:23:29.313] <TB1> INFO: Expecting 411648 events.
[12:23:38.580] <TB1> INFO: 411648 events read in total (8865ms).
[12:23:38.629] <TB1> INFO: Expecting 411648 events.
[12:23:47.933] <TB1> INFO: 411648 events read in total (8901ms).
[12:23:48.025] <TB1> INFO: Expecting 411648 events.
[12:23:57.381] <TB1> INFO: 411648 events read in total (8952ms).
[12:23:57.436] <TB1> INFO: Expecting 411648 events.
[12:24:06.793] <TB1> INFO: 411648 events read in total (8954ms).
[12:24:06.853] <TB1> INFO: Expecting 411648 events.
[12:24:16.177] <TB1> INFO: 411648 events read in total (8921ms).
[12:24:16.329] <TB1> INFO: Test took 150244ms.
[12:24:17.019] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:24:17.030] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:24:17.030] <TB1> INFO: run 1 of 1
[12:24:17.269] <TB1> INFO: Expecting 5025280 events.
[12:24:44.154] <TB1> INFO: 594184 events read in total (26293ms).
[12:25:11.017] <TB1> INFO: 1187344 events read in total (53156ms).
[12:25:37.948] <TB1> INFO: 1777392 events read in total (80087ms).
[12:26:04.652] <TB1> INFO: 2368168 events read in total (106791ms).
[12:26:31.291] <TB1> INFO: 2959296 events read in total (133430ms).
[12:26:57.983] <TB1> INFO: 3551288 events read in total (160122ms).
[12:27:25.073] <TB1> INFO: 4142096 events read in total (187212ms).
[12:27:52.394] <TB1> INFO: 4731992 events read in total (214533ms).
[12:28:06.257] <TB1> INFO: 5025280 events read in total (228396ms).
[12:28:06.407] <TB1> INFO: Test took 229379ms.
[12:28:31.972] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 8.714705 .. 147.533609
[12:28:32.213] <TB1> INFO: Expecting 208000 events.
[12:28:42.158] <TB1> INFO: 208000 events read in total (9354ms).
[12:28:42.160] <TB1> INFO: Test took 10186ms.
[12:28:42.224] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 8 .. 157 (-1/-1) hits flags = 528 (plus default)
[12:28:42.239] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:28:42.239] <TB1> INFO: run 1 of 1
[12:28:42.516] <TB1> INFO: Expecting 4992000 events.
[12:29:11.296] <TB1> INFO: 574712 events read in total (28188ms).
[12:29:38.127] <TB1> INFO: 1148424 events read in total (55020ms).
[12:30:04.077] <TB1> INFO: 1722568 events read in total (80969ms).
[12:30:30.513] <TB1> INFO: 2296688 events read in total (107405ms).
[12:30:56.967] <TB1> INFO: 2871480 events read in total (133859ms).
[12:31:23.593] <TB1> INFO: 3446008 events read in total (160485ms).
[12:32:31.543] <TB1> INFO: 4021080 events read in total (228435ms).
[12:33:00.676] <TB1> INFO: 4595776 events read in total (257568ms).
[12:33:19.322] <TB1> INFO: 4992000 events read in total (276214ms).
[12:33:19.432] <TB1> INFO: Test took 277194ms.
[12:33:45.384] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.473144 .. 48.666471
[12:33:45.621] <TB1> INFO: Expecting 208000 events.
[12:33:55.370] <TB1> INFO: 208000 events read in total (9157ms).
[12:33:55.372] <TB1> INFO: Test took 9987ms.
[12:33:55.422] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 58 (-1/-1) hits flags = 528 (plus default)
[12:33:55.435] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:33:55.435] <TB1> INFO: run 1 of 1
[12:33:55.714] <TB1> INFO: Expecting 1397760 events.
[12:34:24.773] <TB1> INFO: 649808 events read in total (28467ms).
[12:34:53.321] <TB1> INFO: 1298336 events read in total (57015ms).
[12:34:57.999] <TB1> INFO: 1397760 events read in total (61694ms).
[12:34:58.042] <TB1> INFO: Test took 62608ms.
[12:35:11.438] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 28.389918 .. 49.112088
[12:35:11.676] <TB1> INFO: Expecting 208000 events.
[12:35:21.698] <TB1> INFO: 208000 events read in total (9431ms).
[12:35:21.699] <TB1> INFO: Test took 10260ms.
[12:35:21.782] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 18 .. 59 (-1/-1) hits flags = 528 (plus default)
[12:35:21.796] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:35:21.796] <TB1> INFO: run 1 of 1
[12:35:22.074] <TB1> INFO: Expecting 1397760 events.
[12:35:49.713] <TB1> INFO: 643072 events read in total (27047ms).
[12:36:17.417] <TB1> INFO: 1285160 events read in total (54752ms).
[12:36:22.561] <TB1> INFO: 1397760 events read in total (59895ms).
[12:36:22.593] <TB1> INFO: Test took 60798ms.
[12:36:35.065] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 27.557888 .. 51.368589
[12:36:35.308] <TB1> INFO: Expecting 208000 events.
[12:36:45.268] <TB1> INFO: 208000 events read in total (9368ms).
[12:36:45.269] <TB1> INFO: Test took 10202ms.
[12:36:45.316] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 17 .. 61 (-1/-1) hits flags = 528 (plus default)
[12:36:45.330] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:36:45.330] <TB1> INFO: run 1 of 1
[12:36:45.608] <TB1> INFO: Expecting 1497600 events.
[12:37:14.032] <TB1> INFO: 639784 events read in total (27833ms).
[12:37:41.288] <TB1> INFO: 1279016 events read in total (55089ms).
[12:37:50.832] <TB1> INFO: 1497600 events read in total (64633ms).
[12:37:50.865] <TB1> INFO: Test took 65536ms.
[12:38:05.602] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:38:05.602] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:38:05.617] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[12:38:05.617] <TB1> INFO: run 1 of 1
[12:38:05.894] <TB1> INFO: Expecting 1364480 events.
[12:38:34.662] <TB1> INFO: 668592 events read in total (28177ms).
[12:39:02.158] <TB1> INFO: 1335520 events read in total (55673ms).
[12:39:03.926] <TB1> INFO: 1364480 events read in total (57442ms).
[12:39:03.954] <TB1> INFO: Test took 58338ms.
[12:39:16.137] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C0.dat
[12:39:16.138] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C1.dat
[12:39:16.138] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C2.dat
[12:39:16.138] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C3.dat
[12:39:16.138] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C4.dat
[12:39:16.138] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C5.dat
[12:39:16.138] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C6.dat
[12:39:16.138] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C7.dat
[12:39:16.138] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C8.dat
[12:39:16.138] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C9.dat
[12:39:16.138] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C10.dat
[12:39:16.139] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C11.dat
[12:39:16.139] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C12.dat
[12:39:16.139] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C13.dat
[12:39:16.139] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C14.dat
[12:39:16.139] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C15.dat
[12:39:16.139] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C0.dat
[12:39:16.144] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C1.dat
[12:39:16.149] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C2.dat
[12:39:16.154] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C3.dat
[12:39:16.159] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C4.dat
[12:39:16.164] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C5.dat
[12:39:16.169] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C6.dat
[12:39:16.173] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C7.dat
[12:39:16.178] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C8.dat
[12:39:16.183] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C9.dat
[12:39:16.188] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C10.dat
[12:39:16.193] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C11.dat
[12:39:16.198] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C12.dat
[12:39:16.202] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C13.dat
[12:39:16.207] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C14.dat
[12:39:16.212] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//trimParameters35_C15.dat
[12:39:16.217] <TB1> INFO: PixTestTrim::trimTest() done
[12:39:16.217] <TB1> INFO: vtrim: 144 165 161 131 123 109 147 120 145 171 162 148 139 147 152 155
[12:39:16.217] <TB1> INFO: vthrcomp: 124 136 134 128 113 133 132 113 132 133 134 131 133 129 130 136
[12:39:16.217] <TB1> INFO: vcal mean: 35.34 35.04 34.98 35.09 34.92 34.95 35.05 35.26 35.11 35.42 35.28 36.23 35.01 35.37 35.40 34.95
[12:39:16.217] <TB1> INFO: vcal RMS: 1.63 1.19 1.09 1.27 0.97 1.18 1.17 1.42 1.27 1.56 1.39 2.31 1.20 1.73 1.61 1.09
[12:39:16.217] <TB1> INFO: bits mean: 10.07 7.11 6.64 9.03 8.62 8.81 7.26 8.85 9.64 8.99 8.20 9.30 9.43 9.52 9.55 7.99
[12:39:16.217] <TB1> INFO: bits RMS: 2.46 2.54 2.38 2.94 2.89 3.00 2.43 2.86 2.65 2.53 2.48 2.82 2.40 2.61 2.66 2.55
[12:39:16.225] <TB1> INFO: ----------------------------------------------------------------------
[12:39:16.225] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[12:39:16.225] <TB1> INFO: ----------------------------------------------------------------------
[12:39:16.228] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:39:16.241] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:39:16.241] <TB1> INFO: run 1 of 1
[12:39:16.543] <TB1> INFO: Expecting 4160000 events.
[12:39:50.412] <TB1> INFO: 793325 events read in total (33277ms).
[12:40:23.129] <TB1> INFO: 1579885 events read in total (65994ms).
[12:40:55.810] <TB1> INFO: 2360235 events read in total (98675ms).
[12:41:28.332] <TB1> INFO: 3136480 events read in total (131197ms).
[12:42:00.639] <TB1> INFO: 3911965 events read in total (163504ms).
[12:42:11.274] <TB1> INFO: 4160000 events read in total (174139ms).
[12:42:11.348] <TB1> INFO: Test took 175108ms.
[12:42:32.680] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[12:42:32.694] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:42:32.694] <TB1> INFO: run 1 of 1
[12:42:32.972] <TB1> INFO: Expecting 5324800 events.
[12:43:03.586] <TB1> INFO: 697600 events read in total (30022ms).
[12:43:34.742] <TB1> INFO: 1392255 events read in total (61178ms).
[12:44:05.095] <TB1> INFO: 2084410 events read in total (91531ms).
[12:44:35.481] <TB1> INFO: 2773980 events read in total (121917ms).
[12:45:05.756] <TB1> INFO: 3460770 events read in total (152192ms).
[12:45:35.823] <TB1> INFO: 4147580 events read in total (182259ms).
[12:46:06.361] <TB1> INFO: 4834270 events read in total (212797ms).
[12:46:28.071] <TB1> INFO: 5324800 events read in total (234507ms).
[12:46:28.214] <TB1> INFO: Test took 235520ms.
[12:46:58.631] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 216 (-1/-1) hits flags = 528 (plus default)
[12:46:58.645] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:46:58.645] <TB1> INFO: run 1 of 1
[12:46:58.884] <TB1> INFO: Expecting 4513600 events.
[12:47:30.648] <TB1> INFO: 738910 events read in total (31172ms).
[12:48:01.956] <TB1> INFO: 1473605 events read in total (62480ms).
[12:48:33.093] <TB1> INFO: 2204105 events read in total (93617ms).
[12:49:04.683] <TB1> INFO: 2929990 events read in total (125207ms).
[12:49:35.790] <TB1> INFO: 3655505 events read in total (156314ms).
[12:50:07.143] <TB1> INFO: 4381080 events read in total (187667ms).
[12:50:13.086] <TB1> INFO: 4513600 events read in total (193610ms).
[12:50:13.166] <TB1> INFO: Test took 194520ms.
[12:50:44.061] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 216 (-1/-1) hits flags = 528 (plus default)
[12:50:44.075] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:50:44.075] <TB1> INFO: run 1 of 1
[12:50:44.316] <TB1> INFO: Expecting 4513600 events.
[12:51:16.362] <TB1> INFO: 739375 events read in total (31454ms).
[12:51:47.650] <TB1> INFO: 1473980 events read in total (62742ms).
[12:52:19.296] <TB1> INFO: 2204625 events read in total (94388ms).
[12:52:50.815] <TB1> INFO: 2930930 events read in total (125907ms).
[12:53:22.349] <TB1> INFO: 3656325 events read in total (157441ms).
[12:53:53.902] <TB1> INFO: 4382040 events read in total (188994ms).
[12:53:59.858] <TB1> INFO: 4513600 events read in total (194950ms).
[12:53:59.955] <TB1> INFO: Test took 195880ms.
[12:54:31.404] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 217 (-1/-1) hits flags = 528 (plus default)
[12:54:31.418] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:54:31.418] <TB1> INFO: run 1 of 1
[12:54:31.670] <TB1> INFO: Expecting 4534400 events.
[12:55:03.829] <TB1> INFO: 737800 events read in total (31568ms).
[12:55:35.462] <TB1> INFO: 1471270 events read in total (63200ms).
[12:56:06.864] <TB1> INFO: 2200770 events read in total (94602ms).
[12:56:38.242] <TB1> INFO: 2925620 events read in total (125980ms).
[12:57:09.914] <TB1> INFO: 3650085 events read in total (157652ms).
[12:57:41.684] <TB1> INFO: 4374580 events read in total (189422ms).
[12:57:48.916] <TB1> INFO: 4534400 events read in total (196654ms).
[12:57:48.996] <TB1> INFO: Test took 197579ms.
[12:58:17.368] <TB1> INFO: PixTestTrim::trimBitTest() done
[12:58:17.369] <TB1> INFO: PixTestTrim::doTest() done, duration: 2637 seconds
[12:58:17.369] <TB1> INFO: Decoding statistics:
[12:58:17.369] <TB1> INFO: General information:
[12:58:17.369] <TB1> INFO: 16bit words read: 0
[12:58:17.369] <TB1> INFO: valid events total: 0
[12:58:17.369] <TB1> INFO: empty events: 0
[12:58:17.369] <TB1> INFO: valid events with pixels: 0
[12:58:17.369] <TB1> INFO: valid pixel hits: 0
[12:58:17.369] <TB1> INFO: Event errors: 0
[12:58:17.369] <TB1> INFO: start marker: 0
[12:58:17.369] <TB1> INFO: stop marker: 0
[12:58:17.369] <TB1> INFO: overflow: 0
[12:58:17.369] <TB1> INFO: invalid 5bit words: 0
[12:58:17.369] <TB1> INFO: invalid XOR eye diagram: 0
[12:58:17.369] <TB1> INFO: frame (failed synchr.): 0
[12:58:17.369] <TB1> INFO: idle data (no TBM trl): 0
[12:58:17.369] <TB1> INFO: no data (only TBM hdr): 0
[12:58:17.369] <TB1> INFO: TBM errors: 0
[12:58:17.369] <TB1> INFO: flawed TBM headers: 0
[12:58:17.369] <TB1> INFO: flawed TBM trailers: 0
[12:58:17.369] <TB1> INFO: event ID mismatches: 0
[12:58:17.369] <TB1> INFO: ROC errors: 0
[12:58:17.369] <TB1> INFO: missing ROC header(s): 0
[12:58:17.369] <TB1> INFO: misplaced readback start: 0
[12:58:17.369] <TB1> INFO: Pixel decoding errors: 0
[12:58:17.369] <TB1> INFO: pixel data incomplete: 0
[12:58:17.369] <TB1> INFO: pixel address: 0
[12:58:17.369] <TB1> INFO: pulse height fill bit: 0
[12:58:17.369] <TB1> INFO: buffer corruption: 0
[12:58:18.076] <TB1> INFO: ######################################################################
[12:58:18.076] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[12:58:18.076] <TB1> INFO: ######################################################################
[12:58:18.318] <TB1> INFO: Expecting 41600 events.
[12:58:21.765] <TB1> INFO: 41600 events read in total (2855ms).
[12:58:21.766] <TB1> INFO: Test took 3689ms.
[12:58:22.205] <TB1> INFO: Expecting 41600 events.
[12:58:25.734] <TB1> INFO: 41600 events read in total (2937ms).
[12:58:25.735] <TB1> INFO: Test took 3765ms.
[12:58:26.022] <TB1> INFO: Expecting 41600 events.
[12:58:29.570] <TB1> INFO: 41600 events read in total (2956ms).
[12:58:29.570] <TB1> INFO: Test took 3825ms.
[12:58:29.858] <TB1> INFO: Expecting 41600 events.
[12:58:33.460] <TB1> INFO: 41600 events read in total (3010ms).
[12:58:33.461] <TB1> INFO: Test took 3881ms.
[12:58:33.749] <TB1> INFO: Expecting 41600 events.
[12:58:37.413] <TB1> INFO: 41600 events read in total (3072ms).
[12:58:37.414] <TB1> INFO: Test took 3943ms.
[12:58:37.703] <TB1> INFO: Expecting 41600 events.
[12:58:41.200] <TB1> INFO: 41600 events read in total (2906ms).
[12:58:41.201] <TB1> INFO: Test took 3776ms.
[12:58:41.489] <TB1> INFO: Expecting 41600 events.
[12:58:45.047] <TB1> INFO: 41600 events read in total (2966ms).
[12:58:45.048] <TB1> INFO: Test took 3837ms.
[12:58:45.336] <TB1> INFO: Expecting 41600 events.
[12:58:48.848] <TB1> INFO: 41600 events read in total (2920ms).
[12:58:48.849] <TB1> INFO: Test took 3790ms.
[12:58:49.138] <TB1> INFO: Expecting 41600 events.
[12:58:52.702] <TB1> INFO: 41600 events read in total (2972ms).
[12:58:52.703] <TB1> INFO: Test took 3843ms.
[12:58:52.992] <TB1> INFO: Expecting 41600 events.
[12:58:56.571] <TB1> INFO: 41600 events read in total (2987ms).
[12:58:56.572] <TB1> INFO: Test took 3859ms.
[12:58:56.865] <TB1> INFO: Expecting 41600 events.
[12:59:00.679] <TB1> INFO: 41600 events read in total (3222ms).
[12:59:00.680] <TB1> INFO: Test took 4094ms.
[12:59:00.968] <TB1> INFO: Expecting 41600 events.
[12:59:04.536] <TB1> INFO: 41600 events read in total (2976ms).
[12:59:04.538] <TB1> INFO: Test took 3848ms.
[12:59:04.826] <TB1> INFO: Expecting 41600 events.
[12:59:08.386] <TB1> INFO: 41600 events read in total (2969ms).
[12:59:08.388] <TB1> INFO: Test took 3841ms.
[12:59:08.679] <TB1> INFO: Expecting 41600 events.
[12:59:12.207] <TB1> INFO: 41600 events read in total (2936ms).
[12:59:12.208] <TB1> INFO: Test took 3806ms.
[12:59:12.504] <TB1> INFO: Expecting 41600 events.
[12:59:16.140] <TB1> INFO: 41600 events read in total (3045ms).
[12:59:16.141] <TB1> INFO: Test took 3919ms.
[12:59:16.431] <TB1> INFO: Expecting 41600 events.
[12:59:19.958] <TB1> INFO: 41600 events read in total (2935ms).
[12:59:19.959] <TB1> INFO: Test took 3800ms.
[12:59:20.247] <TB1> INFO: Expecting 41600 events.
[12:59:23.804] <TB1> INFO: 41600 events read in total (2965ms).
[12:59:23.805] <TB1> INFO: Test took 3836ms.
[12:59:24.094] <TB1> INFO: Expecting 41600 events.
[12:59:27.690] <TB1> INFO: 41600 events read in total (3005ms).
[12:59:27.691] <TB1> INFO: Test took 3876ms.
[12:59:27.979] <TB1> INFO: Expecting 41600 events.
[12:59:31.527] <TB1> INFO: 41600 events read in total (2956ms).
[12:59:31.528] <TB1> INFO: Test took 3827ms.
[12:59:31.819] <TB1> INFO: Expecting 41600 events.
[12:59:35.302] <TB1> INFO: 41600 events read in total (2892ms).
[12:59:35.303] <TB1> INFO: Test took 3762ms.
[12:59:35.596] <TB1> INFO: Expecting 41600 events.
[12:59:39.095] <TB1> INFO: 41600 events read in total (2907ms).
[12:59:39.097] <TB1> INFO: Test took 3783ms.
[12:59:39.399] <TB1> INFO: Expecting 41600 events.
[12:59:42.948] <TB1> INFO: 41600 events read in total (2958ms).
[12:59:42.949] <TB1> INFO: Test took 3837ms.
[12:59:43.237] <TB1> INFO: Expecting 41600 events.
[12:59:46.740] <TB1> INFO: 41600 events read in total (2912ms).
[12:59:46.741] <TB1> INFO: Test took 3782ms.
[12:59:47.031] <TB1> INFO: Expecting 41600 events.
[12:59:50.553] <TB1> INFO: 41600 events read in total (2930ms).
[12:59:50.554] <TB1> INFO: Test took 3800ms.
[12:59:50.846] <TB1> INFO: Expecting 41600 events.
[12:59:54.415] <TB1> INFO: 41600 events read in total (2976ms).
[12:59:54.416] <TB1> INFO: Test took 3849ms.
[12:59:54.707] <TB1> INFO: Expecting 41600 events.
[12:59:58.185] <TB1> INFO: 41600 events read in total (2887ms).
[12:59:58.186] <TB1> INFO: Test took 3757ms.
[12:59:58.473] <TB1> INFO: Expecting 41600 events.
[13:00:02.050] <TB1> INFO: 41600 events read in total (2985ms).
[13:00:02.051] <TB1> INFO: Test took 3855ms.
[13:00:02.338] <TB1> INFO: Expecting 41600 events.
[13:00:05.860] <TB1> INFO: 41600 events read in total (2930ms).
[13:00:05.861] <TB1> INFO: Test took 3800ms.
[13:00:06.151] <TB1> INFO: Expecting 41600 events.
[13:00:09.723] <TB1> INFO: 41600 events read in total (2981ms).
[13:00:09.723] <TB1> INFO: Test took 3852ms.
[13:00:10.012] <TB1> INFO: Expecting 41600 events.
[13:00:13.590] <TB1> INFO: 41600 events read in total (2987ms).
[13:00:13.591] <TB1> INFO: Test took 3857ms.
[13:00:13.879] <TB1> INFO: Expecting 41600 events.
[13:00:17.357] <TB1> INFO: 41600 events read in total (2886ms).
[13:00:17.358] <TB1> INFO: Test took 3757ms.
[13:00:17.646] <TB1> INFO: Expecting 41600 events.
[13:00:21.272] <TB1> INFO: 41600 events read in total (3034ms).
[13:00:21.273] <TB1> INFO: Test took 3905ms.
[13:00:21.563] <TB1> INFO: Expecting 41600 events.
[13:00:25.178] <TB1> INFO: 41600 events read in total (3023ms).
[13:00:25.179] <TB1> INFO: Test took 3894ms.
[13:00:25.471] <TB1> INFO: Expecting 41600 events.
[13:00:29.228] <TB1> INFO: 41600 events read in total (3166ms).
[13:00:29.229] <TB1> INFO: Test took 4037ms.
[13:00:29.518] <TB1> INFO: Expecting 41600 events.
[13:00:33.039] <TB1> INFO: 41600 events read in total (2930ms).
[13:00:33.040] <TB1> INFO: Test took 3801ms.
[13:00:33.328] <TB1> INFO: Expecting 41600 events.
[13:00:36.859] <TB1> INFO: 41600 events read in total (2940ms).
[13:00:36.860] <TB1> INFO: Test took 3810ms.
[13:00:37.149] <TB1> INFO: Expecting 41600 events.
[13:00:40.820] <TB1> INFO: 41600 events read in total (3079ms).
[13:00:40.821] <TB1> INFO: Test took 3950ms.
[13:00:41.109] <TB1> INFO: Expecting 41600 events.
[13:00:44.669] <TB1> INFO: 41600 events read in total (2968ms).
[13:00:44.670] <TB1> INFO: Test took 3839ms.
[13:00:44.963] <TB1> INFO: Expecting 41600 events.
[13:00:48.491] <TB1> INFO: 41600 events read in total (2936ms).
[13:00:48.492] <TB1> INFO: Test took 3807ms.
[13:00:48.783] <TB1> INFO: Expecting 41600 events.
[13:00:52.315] <TB1> INFO: 41600 events read in total (2940ms).
[13:00:52.316] <TB1> INFO: Test took 3811ms.
[13:00:52.609] <TB1> INFO: Expecting 41600 events.
[13:00:56.223] <TB1> INFO: 41600 events read in total (3022ms).
[13:00:56.223] <TB1> INFO: Test took 3893ms.
[13:00:56.512] <TB1> INFO: Expecting 41600 events.
[13:01:00.068] <TB1> INFO: 41600 events read in total (2964ms).
[13:01:00.069] <TB1> INFO: Test took 3835ms.
[13:01:00.358] <TB1> INFO: Expecting 41600 events.
[13:01:03.858] <TB1> INFO: 41600 events read in total (2908ms).
[13:01:03.859] <TB1> INFO: Test took 3779ms.
[13:01:04.150] <TB1> INFO: Expecting 41600 events.
[13:01:07.700] <TB1> INFO: 41600 events read in total (2958ms).
[13:01:07.701] <TB1> INFO: Test took 3829ms.
[13:01:07.989] <TB1> INFO: Expecting 41600 events.
[13:01:11.548] <TB1> INFO: 41600 events read in total (2967ms).
[13:01:11.549] <TB1> INFO: Test took 3838ms.
[13:01:11.837] <TB1> INFO: Expecting 41600 events.
[13:01:15.381] <TB1> INFO: 41600 events read in total (2952ms).
[13:01:15.382] <TB1> INFO: Test took 3823ms.
[13:01:15.672] <TB1> INFO: Expecting 41600 events.
[13:01:19.182] <TB1> INFO: 41600 events read in total (2918ms).
[13:01:19.183] <TB1> INFO: Test took 3789ms.
[13:01:19.472] <TB1> INFO: Expecting 41600 events.
[13:01:23.045] <TB1> INFO: 41600 events read in total (2982ms).
[13:01:23.046] <TB1> INFO: Test took 3853ms.
[13:01:23.335] <TB1> INFO: Expecting 41600 events.
[13:01:26.879] <TB1> INFO: 41600 events read in total (2952ms).
[13:01:26.880] <TB1> INFO: Test took 3823ms.
[13:01:27.168] <TB1> INFO: Expecting 41600 events.
[13:01:30.686] <TB1> INFO: 41600 events read in total (2926ms).
[13:01:30.687] <TB1> INFO: Test took 3797ms.
[13:01:30.975] <TB1> INFO: Expecting 41600 events.
[13:01:34.537] <TB1> INFO: 41600 events read in total (2971ms).
[13:01:34.538] <TB1> INFO: Test took 3841ms.
[13:01:34.827] <TB1> INFO: Expecting 41600 events.
[13:01:38.376] <TB1> INFO: 41600 events read in total (2956ms).
[13:01:38.377] <TB1> INFO: Test took 3828ms.
[13:01:38.666] <TB1> INFO: Expecting 41600 events.
[13:01:42.219] <TB1> INFO: 41600 events read in total (2961ms).
[13:01:42.220] <TB1> INFO: Test took 3832ms.
[13:01:42.235] <TB1> INFO: Max pixel from chip 0 is [14 ,25] phvalue 135
[13:01:42.235] <TB1> INFO: Max pixel from chip 1 is [4 ,29] phvalue 95
[13:01:42.235] <TB1> INFO: Max pixel from chip 2 is [6 ,21] phvalue 64
[13:01:42.236] <TB1> INFO: Max pixel from chip 3 is [22 ,29] phvalue 135
[13:01:42.236] <TB1> INFO: Max pixel from chip 4 is [4 ,13] phvalue 143
[13:01:42.236] <TB1> INFO: Max pixel from chip 5 is [20 ,9] phvalue 105
[13:01:42.236] <TB1> INFO: Max pixel from chip 6 is [14 ,7] phvalue 240
[13:01:42.236] <TB1> INFO: Max pixel from chip 7 is [14 ,42] phvalue 53
[13:01:42.236] <TB1> INFO: Max pixel from chip 8 is [23 ,14] phvalue 128
[13:01:42.237] <TB1> INFO: Max pixel from chip 9 is [4 ,24] phvalue 135
[13:01:42.237] <TB1> INFO: Max pixel from chip 10 is [4 ,5] phvalue 173
[13:01:42.237] <TB1> INFO: Max pixel from chip 11 is [9 ,15] phvalue 102
[13:01:42.237] <TB1> INFO: Max pixel from chip 12 is [22 ,8] phvalue 77
[13:01:42.237] <TB1> INFO: Max pixel from chip 13 is [18 ,19] phvalue 125
[13:01:42.237] <TB1> INFO: Max pixel from chip 14 is [32 ,9] phvalue 72
[13:01:42.238] <TB1> INFO: Max pixel from chip 15 is [4 ,24] phvalue 74
[13:01:42.518] <TB1> INFO: Expecting 41600 events.
[13:01:46.242] <TB1> INFO: 41600 events read in total (3133ms).
[13:01:46.243] <TB1> INFO: Test took 3991ms.
[13:01:46.253] <TB1> INFO: Min pixel from chip 0 is [3 ,5] phvalue 255
[13:01:46.253] <TB1> INFO: Min pixel from chip 1 is [3 ,5] phvalue 255
[13:01:46.253] <TB1> INFO: Min pixel from chip 2 is [38 ,31] phvalue 252
[13:01:46.254] <TB1> INFO: Min pixel from chip 3 is [3 ,5] phvalue 255
[13:01:46.254] <TB1> INFO: Min pixel from chip 4 is [3 ,5] phvalue 255
[13:01:46.254] <TB1> INFO: Min pixel from chip 5 is [3 ,5] phvalue 255
[13:01:46.254] <TB1> INFO: Min pixel from chip 6 is [3 ,5] phvalue 255
[13:01:46.254] <TB1> INFO: Min pixel from chip 7 is [17 ,61] phvalue 247
[13:01:46.254] <TB1> INFO: Min pixel from chip 8 is [3 ,5] phvalue 255
[13:01:46.254] <TB1> INFO: Min pixel from chip 9 is [3 ,5] phvalue 255
[13:01:46.254] <TB1> INFO: Min pixel from chip 10 is [3 ,5] phvalue 255
[13:01:46.254] <TB1> INFO: Min pixel from chip 11 is [3 ,5] phvalue 255
[13:01:46.254] <TB1> INFO: Min pixel from chip 12 is [3 ,5] phvalue 255
[13:01:46.255] <TB1> INFO: Min pixel from chip 13 is [3 ,5] phvalue 255
[13:01:46.255] <TB1> INFO: Min pixel from chip 14 is [25 ,19] phvalue 245
[13:01:46.255] <TB1> INFO: Min pixel from chip 15 is [9 ,43] phvalue 245
[13:01:46.533] <TB1> INFO: Expecting 2560 events.
[13:01:47.420] <TB1> INFO: 2560 events read in total (295ms).
[13:01:47.420] <TB1> INFO: Test took 1163ms.
[13:01:47.728] <TB1> INFO: Expecting 2560 events.
[13:01:48.619] <TB1> INFO: 2560 events read in total (299ms).
[13:01:48.619] <TB1> INFO: Test took 1198ms.
[13:01:48.927] <TB1> INFO: Expecting 2560 events.
[13:01:49.810] <TB1> INFO: 2560 events read in total (291ms).
[13:01:49.810] <TB1> INFO: Test took 1190ms.
[13:01:50.118] <TB1> INFO: Expecting 2560 events.
[13:01:51.006] <TB1> INFO: 2560 events read in total (298ms).
[13:01:51.007] <TB1> INFO: Test took 1196ms.
[13:01:51.314] <TB1> INFO: Expecting 2560 events.
[13:01:52.192] <TB1> INFO: 2560 events read in total (287ms).
[13:01:52.193] <TB1> INFO: Test took 1185ms.
[13:01:52.501] <TB1> INFO: Expecting 2560 events.
[13:01:53.390] <TB1> INFO: 2560 events read in total (297ms).
[13:01:53.390] <TB1> INFO: Test took 1197ms.
[13:01:53.698] <TB1> INFO: Expecting 2560 events.
[13:01:54.579] <TB1> INFO: 2560 events read in total (289ms).
[13:01:54.579] <TB1> INFO: Test took 1189ms.
[13:01:54.887] <TB1> INFO: Expecting 2560 events.
[13:01:55.768] <TB1> INFO: 2560 events read in total (290ms).
[13:01:55.768] <TB1> INFO: Test took 1188ms.
[13:01:56.076] <TB1> INFO: Expecting 2560 events.
[13:01:56.958] <TB1> INFO: 2560 events read in total (290ms).
[13:01:56.958] <TB1> INFO: Test took 1189ms.
[13:01:57.267] <TB1> INFO: Expecting 2560 events.
[13:01:58.156] <TB1> INFO: 2560 events read in total (298ms).
[13:01:58.156] <TB1> INFO: Test took 1197ms.
[13:01:58.463] <TB1> INFO: Expecting 2560 events.
[13:01:59.353] <TB1> INFO: 2560 events read in total (298ms).
[13:01:59.354] <TB1> INFO: Test took 1197ms.
[13:01:59.660] <TB1> INFO: Expecting 2560 events.
[13:02:00.545] <TB1> INFO: 2560 events read in total (293ms).
[13:02:00.546] <TB1> INFO: Test took 1192ms.
[13:02:00.853] <TB1> INFO: Expecting 2560 events.
[13:02:01.743] <TB1> INFO: 2560 events read in total (298ms).
[13:02:01.743] <TB1> INFO: Test took 1197ms.
[13:02:02.052] <TB1> INFO: Expecting 2560 events.
[13:02:02.945] <TB1> INFO: 2560 events read in total (302ms).
[13:02:02.946] <TB1> INFO: Test took 1202ms.
[13:02:03.253] <TB1> INFO: Expecting 2560 events.
[13:02:04.143] <TB1> INFO: 2560 events read in total (299ms).
[13:02:04.143] <TB1> INFO: Test took 1196ms.
[13:02:04.451] <TB1> INFO: Expecting 2560 events.
[13:02:05.338] <TB1> INFO: 2560 events read in total (295ms).
[13:02:05.339] <TB1> INFO: Test took 1196ms.
[13:02:05.343] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:02:05.658] <TB1> INFO: Expecting 655360 events.
[13:02:20.353] <TB1> INFO: 655360 events read in total (14104ms).
[13:02:20.367] <TB1> INFO: Expecting 655360 events.
[13:02:34.932] <TB1> INFO: 655360 events read in total (14162ms).
[13:02:34.948] <TB1> INFO: Expecting 655360 events.
[13:02:49.458] <TB1> INFO: 655360 events read in total (14107ms).
[13:02:49.483] <TB1> INFO: Expecting 655360 events.
[13:03:04.005] <TB1> INFO: 655360 events read in total (14119ms).
[13:03:04.032] <TB1> INFO: Expecting 655360 events.
[13:03:18.548] <TB1> INFO: 655360 events read in total (14113ms).
[13:03:18.577] <TB1> INFO: Expecting 655360 events.
[13:03:33.071] <TB1> INFO: 655360 events read in total (14091ms).
[13:03:33.116] <TB1> INFO: Expecting 655360 events.
[13:03:47.493] <TB1> INFO: 655360 events read in total (13974ms).
[13:03:47.532] <TB1> INFO: Expecting 655360 events.
[13:04:02.056] <TB1> INFO: 655360 events read in total (14121ms).
[13:04:02.147] <TB1> INFO: Expecting 655360 events.
[13:04:16.583] <TB1> INFO: 655360 events read in total (14033ms).
[13:04:16.632] <TB1> INFO: Expecting 655360 events.
[13:04:31.247] <TB1> INFO: 655360 events read in total (14212ms).
[13:04:31.314] <TB1> INFO: Expecting 655360 events.
[13:04:45.655] <TB1> INFO: 655360 events read in total (13938ms).
[13:04:45.742] <TB1> INFO: Expecting 655360 events.
[13:05:00.314] <TB1> INFO: 655360 events read in total (14169ms).
[13:05:00.418] <TB1> INFO: Expecting 655360 events.
[13:05:14.914] <TB1> INFO: 655360 events read in total (14093ms).
[13:05:15.027] <TB1> INFO: Expecting 655360 events.
[13:05:29.518] <TB1> INFO: 655360 events read in total (14087ms).
[13:05:29.605] <TB1> INFO: Expecting 655360 events.
[13:05:44.132] <TB1> INFO: 655360 events read in total (14124ms).
[13:05:44.278] <TB1> INFO: Expecting 655360 events.
[13:05:58.799] <TB1> INFO: 655360 events read in total (14118ms).
[13:05:58.896] <TB1> INFO: Test took 233554ms.
[13:05:58.991] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:05:59.249] <TB1> INFO: Expecting 655360 events.
[13:06:13.463] <TB1> INFO: 655360 events read in total (13622ms).
[13:06:13.474] <TB1> INFO: Expecting 655360 events.
[13:06:27.799] <TB1> INFO: 655360 events read in total (13922ms).
[13:06:27.815] <TB1> INFO: Expecting 655360 events.
[13:06:42.188] <TB1> INFO: 655360 events read in total (13970ms).
[13:06:42.208] <TB1> INFO: Expecting 655360 events.
[13:06:57.021] <TB1> INFO: 655360 events read in total (14410ms).
[13:06:57.053] <TB1> INFO: Expecting 655360 events.
[13:07:11.795] <TB1> INFO: 655360 events read in total (14339ms).
[13:07:11.823] <TB1> INFO: Expecting 655360 events.
[13:07:26.589] <TB1> INFO: 655360 events read in total (14363ms).
[13:07:26.625] <TB1> INFO: Expecting 655360 events.
[13:07:41.250] <TB1> INFO: 655360 events read in total (14222ms).
[13:07:41.287] <TB1> INFO: Expecting 655360 events.
[13:07:55.920] <TB1> INFO: 655360 events read in total (14230ms).
[13:07:56.011] <TB1> INFO: Expecting 655360 events.
[13:08:10.745] <TB1> INFO: 655360 events read in total (14331ms).
[13:08:10.795] <TB1> INFO: Expecting 655360 events.
[13:08:25.466] <TB1> INFO: 655360 events read in total (14268ms).
[13:08:25.532] <TB1> INFO: Expecting 655360 events.
[13:08:40.223] <TB1> INFO: 655360 events read in total (14289ms).
[13:08:40.284] <TB1> INFO: Expecting 655360 events.
[13:08:54.990] <TB1> INFO: 655360 events read in total (14303ms).
[13:08:55.101] <TB1> INFO: Expecting 655360 events.
[13:09:09.967] <TB1> INFO: 655360 events read in total (14463ms).
[13:09:10.093] <TB1> INFO: Expecting 655360 events.
[13:09:24.686] <TB1> INFO: 655360 events read in total (14190ms).
[13:09:24.774] <TB1> INFO: Expecting 655360 events.
[13:09:39.037] <TB1> INFO: 655360 events read in total (13860ms).
[13:09:39.131] <TB1> INFO: Expecting 655360 events.
[13:09:53.528] <TB1> INFO: 655360 events read in total (13994ms).
[13:09:53.631] <TB1> INFO: Test took 234640ms.
[13:09:53.812] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:53.819] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:09:53.825] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:53.831] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:53.837] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:53.843] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:53.849] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:09:53.854] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:09:53.860] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:09:53.867] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:09:53.873] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:53.879] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:53.884] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:09:53.890] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:53.896] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:09:53.902] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:09:53.908] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:09:53.914] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:53.920] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:53.926] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:53.932] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:09:53.940] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:09:53.946] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:09:53.953] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:09:53.959] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:53.965] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:09:53.972] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:09:53.978] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:09:53.984] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:09:53.990] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[13:09:53.996] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:54.003] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:09:54.009] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:09:54.016] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:09:54.023] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:09:54.030] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[13:09:54.039] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[13:09:54.047] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[13:09:54.056] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[13:09:54.063] <TB1> INFO: safety margin for low PH: adding 9, margin is now 29
[13:09:54.071] <TB1> INFO: safety margin for low PH: adding 10, margin is now 30
[13:09:54.079] <TB1> INFO: safety margin for low PH: adding 11, margin is now 31
[13:09:54.087] <TB1> INFO: safety margin for low PH: adding 12, margin is now 32
[13:09:54.094] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:54.100] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:54.106] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:54.142] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C0.dat
[13:09:54.143] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C1.dat
[13:09:54.143] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C2.dat
[13:09:54.143] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C3.dat
[13:09:54.143] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C4.dat
[13:09:54.143] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C5.dat
[13:09:54.143] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C6.dat
[13:09:54.143] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C7.dat
[13:09:54.143] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C8.dat
[13:09:54.144] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C9.dat
[13:09:54.144] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C10.dat
[13:09:54.144] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C11.dat
[13:09:54.144] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C12.dat
[13:09:54.144] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C13.dat
[13:09:54.144] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C14.dat
[13:09:54.144] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//dacParameters35_C15.dat
[13:09:54.389] <TB1> INFO: Expecting 41600 events.
[13:09:57.552] <TB1> INFO: 41600 events read in total (2572ms).
[13:09:57.553] <TB1> INFO: Test took 3405ms.
[13:09:58.033] <TB1> INFO: Expecting 41600 events.
[13:10:01.077] <TB1> INFO: 41600 events read in total (2453ms).
[13:10:01.078] <TB1> INFO: Test took 3312ms.
[13:10:01.549] <TB1> INFO: Expecting 41600 events.
[13:10:04.749] <TB1> INFO: 41600 events read in total (2608ms).
[13:10:04.750] <TB1> INFO: Test took 3460ms.
[13:10:04.971] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:05.060] <TB1> INFO: Expecting 2560 events.
[13:10:05.945] <TB1> INFO: 2560 events read in total (294ms).
[13:10:05.945] <TB1> INFO: Test took 974ms.
[13:10:05.950] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:06.254] <TB1> INFO: Expecting 2560 events.
[13:10:07.139] <TB1> INFO: 2560 events read in total (293ms).
[13:10:07.139] <TB1> INFO: Test took 1189ms.
[13:10:07.141] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:07.447] <TB1> INFO: Expecting 2560 events.
[13:10:08.331] <TB1> INFO: 2560 events read in total (292ms).
[13:10:08.331] <TB1> INFO: Test took 1190ms.
[13:10:08.333] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:08.640] <TB1> INFO: Expecting 2560 events.
[13:10:09.524] <TB1> INFO: 2560 events read in total (293ms).
[13:10:09.524] <TB1> INFO: Test took 1191ms.
[13:10:09.527] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:09.832] <TB1> INFO: Expecting 2560 events.
[13:10:10.717] <TB1> INFO: 2560 events read in total (293ms).
[13:10:10.717] <TB1> INFO: Test took 1190ms.
[13:10:10.719] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:11.025] <TB1> INFO: Expecting 2560 events.
[13:10:11.911] <TB1> INFO: 2560 events read in total (294ms).
[13:10:11.911] <TB1> INFO: Test took 1192ms.
[13:10:11.913] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:12.219] <TB1> INFO: Expecting 2560 events.
[13:10:13.107] <TB1> INFO: 2560 events read in total (296ms).
[13:10:13.107] <TB1> INFO: Test took 1194ms.
[13:10:13.109] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:13.415] <TB1> INFO: Expecting 2560 events.
[13:10:14.303] <TB1> INFO: 2560 events read in total (296ms).
[13:10:14.303] <TB1> INFO: Test took 1194ms.
[13:10:14.305] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:14.612] <TB1> INFO: Expecting 2560 events.
[13:10:15.495] <TB1> INFO: 2560 events read in total (292ms).
[13:10:15.495] <TB1> INFO: Test took 1190ms.
[13:10:15.497] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:15.803] <TB1> INFO: Expecting 2560 events.
[13:10:16.686] <TB1> INFO: 2560 events read in total (292ms).
[13:10:16.686] <TB1> INFO: Test took 1189ms.
[13:10:16.689] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:16.995] <TB1> INFO: Expecting 2560 events.
[13:10:17.878] <TB1> INFO: 2560 events read in total (292ms).
[13:10:17.878] <TB1> INFO: Test took 1189ms.
[13:10:17.881] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:18.186] <TB1> INFO: Expecting 2560 events.
[13:10:19.065] <TB1> INFO: 2560 events read in total (287ms).
[13:10:19.066] <TB1> INFO: Test took 1185ms.
[13:10:19.068] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:19.374] <TB1> INFO: Expecting 2560 events.
[13:10:20.257] <TB1> INFO: 2560 events read in total (291ms).
[13:10:20.257] <TB1> INFO: Test took 1189ms.
[13:10:20.259] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:20.565] <TB1> INFO: Expecting 2560 events.
[13:10:21.447] <TB1> INFO: 2560 events read in total (290ms).
[13:10:21.447] <TB1> INFO: Test took 1188ms.
[13:10:21.450] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:21.756] <TB1> INFO: Expecting 2560 events.
[13:10:22.638] <TB1> INFO: 2560 events read in total (290ms).
[13:10:22.638] <TB1> INFO: Test took 1189ms.
[13:10:22.640] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:22.947] <TB1> INFO: Expecting 2560 events.
[13:10:23.831] <TB1> INFO: 2560 events read in total (292ms).
[13:10:23.832] <TB1> INFO: Test took 1192ms.
[13:10:23.834] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:24.140] <TB1> INFO: Expecting 2560 events.
[13:10:25.023] <TB1> INFO: 2560 events read in total (291ms).
[13:10:25.023] <TB1> INFO: Test took 1189ms.
[13:10:25.026] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:25.331] <TB1> INFO: Expecting 2560 events.
[13:10:26.219] <TB1> INFO: 2560 events read in total (296ms).
[13:10:26.220] <TB1> INFO: Test took 1194ms.
[13:10:26.222] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:26.528] <TB1> INFO: Expecting 2560 events.
[13:10:27.409] <TB1> INFO: 2560 events read in total (289ms).
[13:10:27.409] <TB1> INFO: Test took 1187ms.
[13:10:27.412] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:27.717] <TB1> INFO: Expecting 2560 events.
[13:10:28.600] <TB1> INFO: 2560 events read in total (291ms).
[13:10:28.600] <TB1> INFO: Test took 1188ms.
[13:10:28.602] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:28.909] <TB1> INFO: Expecting 2560 events.
[13:10:29.798] <TB1> INFO: 2560 events read in total (298ms).
[13:10:29.798] <TB1> INFO: Test took 1196ms.
[13:10:29.801] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:30.106] <TB1> INFO: Expecting 2560 events.
[13:10:30.990] <TB1> INFO: 2560 events read in total (292ms).
[13:10:30.990] <TB1> INFO: Test took 1190ms.
[13:10:30.992] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:31.299] <TB1> INFO: Expecting 2560 events.
[13:10:32.179] <TB1> INFO: 2560 events read in total (289ms).
[13:10:32.179] <TB1> INFO: Test took 1187ms.
[13:10:32.181] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:32.488] <TB1> INFO: Expecting 2560 events.
[13:10:33.371] <TB1> INFO: 2560 events read in total (291ms).
[13:10:33.371] <TB1> INFO: Test took 1191ms.
[13:10:33.374] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:33.679] <TB1> INFO: Expecting 2560 events.
[13:10:34.567] <TB1> INFO: 2560 events read in total (296ms).
[13:10:34.567] <TB1> INFO: Test took 1193ms.
[13:10:34.570] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:34.876] <TB1> INFO: Expecting 2560 events.
[13:10:35.768] <TB1> INFO: 2560 events read in total (300ms).
[13:10:35.768] <TB1> INFO: Test took 1198ms.
[13:10:35.771] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:36.076] <TB1> INFO: Expecting 2560 events.
[13:10:36.962] <TB1> INFO: 2560 events read in total (294ms).
[13:10:36.963] <TB1> INFO: Test took 1192ms.
[13:10:36.966] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:37.272] <TB1> INFO: Expecting 2560 events.
[13:10:38.160] <TB1> INFO: 2560 events read in total (297ms).
[13:10:38.160] <TB1> INFO: Test took 1195ms.
[13:10:38.163] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:38.468] <TB1> INFO: Expecting 2560 events.
[13:10:39.355] <TB1> INFO: 2560 events read in total (295ms).
[13:10:39.355] <TB1> INFO: Test took 1192ms.
[13:10:39.358] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:39.664] <TB1> INFO: Expecting 2560 events.
[13:10:40.548] <TB1> INFO: 2560 events read in total (293ms).
[13:10:40.548] <TB1> INFO: Test took 1190ms.
[13:10:40.552] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:40.857] <TB1> INFO: Expecting 2560 events.
[13:10:41.744] <TB1> INFO: 2560 events read in total (296ms).
[13:10:41.744] <TB1> INFO: Test took 1192ms.
[13:10:41.746] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:42.053] <TB1> INFO: Expecting 2560 events.
[13:10:42.939] <TB1> INFO: 2560 events read in total (294ms).
[13:10:42.939] <TB1> INFO: Test took 1193ms.
[13:10:43.408] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 745 seconds
[13:10:43.408] <TB1> INFO: PH scale (per ROC): 42 38 52 50 38 42 43 48 51 30 44 42 46 43 52 57
[13:10:43.408] <TB1> INFO: PH offset (per ROC): 99 108 124 105 94 107 70 129 108 93 90 107 112 106 125 125
[13:10:43.415] <TB1> INFO: Decoding statistics:
[13:10:43.415] <TB1> INFO: General information:
[13:10:43.415] <TB1> INFO: 16bit words read: 127882
[13:10:43.415] <TB1> INFO: valid events total: 20480
[13:10:43.415] <TB1> INFO: empty events: 17979
[13:10:43.415] <TB1> INFO: valid events with pixels: 2501
[13:10:43.415] <TB1> INFO: valid pixel hits: 2501
[13:10:43.415] <TB1> INFO: Event errors: 0
[13:10:43.415] <TB1> INFO: start marker: 0
[13:10:43.415] <TB1> INFO: stop marker: 0
[13:10:43.415] <TB1> INFO: overflow: 0
[13:10:43.415] <TB1> INFO: invalid 5bit words: 0
[13:10:43.415] <TB1> INFO: invalid XOR eye diagram: 0
[13:10:43.415] <TB1> INFO: frame (failed synchr.): 0
[13:10:43.415] <TB1> INFO: idle data (no TBM trl): 0
[13:10:43.415] <TB1> INFO: no data (only TBM hdr): 0
[13:10:43.415] <TB1> INFO: TBM errors: 0
[13:10:43.415] <TB1> INFO: flawed TBM headers: 0
[13:10:43.415] <TB1> INFO: flawed TBM trailers: 0
[13:10:43.415] <TB1> INFO: event ID mismatches: 0
[13:10:43.415] <TB1> INFO: ROC errors: 0
[13:10:43.415] <TB1> INFO: missing ROC header(s): 0
[13:10:43.415] <TB1> INFO: misplaced readback start: 0
[13:10:43.415] <TB1> INFO: Pixel decoding errors: 0
[13:10:43.415] <TB1> INFO: pixel data incomplete: 0
[13:10:43.415] <TB1> INFO: pixel address: 0
[13:10:43.415] <TB1> INFO: pulse height fill bit: 0
[13:10:43.415] <TB1> INFO: buffer corruption: 0
[13:10:43.583] <TB1> INFO: ######################################################################
[13:10:43.583] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:10:43.583] <TB1> INFO: ######################################################################
[13:10:43.598] <TB1> INFO: scanning low vcal = 10
[13:10:43.834] <TB1> INFO: Expecting 41600 events.
[13:10:47.455] <TB1> INFO: 41600 events read in total (3029ms).
[13:10:47.455] <TB1> INFO: Test took 3857ms.
[13:10:47.457] <TB1> INFO: scanning low vcal = 20
[13:10:47.756] <TB1> INFO: Expecting 41600 events.
[13:10:51.382] <TB1> INFO: 41600 events read in total (3035ms).
[13:10:51.382] <TB1> INFO: Test took 3925ms.
[13:10:51.384] <TB1> INFO: scanning low vcal = 30
[13:10:51.680] <TB1> INFO: Expecting 41600 events.
[13:10:55.384] <TB1> INFO: 41600 events read in total (3112ms).
[13:10:55.384] <TB1> INFO: Test took 4000ms.
[13:10:55.387] <TB1> INFO: scanning low vcal = 40
[13:10:55.664] <TB1> INFO: Expecting 41600 events.
[13:10:59.710] <TB1> INFO: 41600 events read in total (3454ms).
[13:10:59.712] <TB1> INFO: Test took 4325ms.
[13:10:59.715] <TB1> INFO: scanning low vcal = 50
[13:11:00.032] <TB1> INFO: Expecting 41600 events.
[13:11:04.087] <TB1> INFO: 41600 events read in total (3463ms).
[13:11:04.088] <TB1> INFO: Test took 4373ms.
[13:11:04.091] <TB1> INFO: scanning low vcal = 60
[13:11:04.368] <TB1> INFO: Expecting 41600 events.
[13:11:08.334] <TB1> INFO: 41600 events read in total (3375ms).
[13:11:08.334] <TB1> INFO: Test took 4243ms.
[13:11:08.338] <TB1> INFO: scanning low vcal = 70
[13:11:08.614] <TB1> INFO: Expecting 41600 events.
[13:11:12.661] <TB1> INFO: 41600 events read in total (3455ms).
[13:11:12.662] <TB1> INFO: Test took 4324ms.
[13:11:12.665] <TB1> INFO: scanning low vcal = 80
[13:11:12.985] <TB1> INFO: Expecting 41600 events.
[13:11:16.975] <TB1> INFO: 41600 events read in total (3398ms).
[13:11:16.976] <TB1> INFO: Test took 4311ms.
[13:11:16.979] <TB1> INFO: scanning low vcal = 90
[13:11:17.256] <TB1> INFO: Expecting 41600 events.
[13:11:21.255] <TB1> INFO: 41600 events read in total (3407ms).
[13:11:21.256] <TB1> INFO: Test took 4276ms.
[13:11:21.260] <TB1> INFO: scanning low vcal = 100
[13:11:21.535] <TB1> INFO: Expecting 41600 events.
[13:11:25.593] <TB1> INFO: 41600 events read in total (3466ms).
[13:11:25.594] <TB1> INFO: Test took 4334ms.
[13:11:25.597] <TB1> INFO: scanning low vcal = 110
[13:11:25.916] <TB1> INFO: Expecting 41600 events.
[13:11:29.972] <TB1> INFO: 41600 events read in total (3464ms).
[13:11:29.973] <TB1> INFO: Test took 4375ms.
[13:11:29.977] <TB1> INFO: scanning low vcal = 120
[13:11:30.253] <TB1> INFO: Expecting 41600 events.
[13:11:34.254] <TB1> INFO: 41600 events read in total (3409ms).
[13:11:34.254] <TB1> INFO: Test took 4277ms.
[13:11:34.258] <TB1> INFO: scanning low vcal = 130
[13:11:34.575] <TB1> INFO: Expecting 41600 events.
[13:11:38.549] <TB1> INFO: 41600 events read in total (3382ms).
[13:11:38.550] <TB1> INFO: Test took 4292ms.
[13:11:38.553] <TB1> INFO: scanning low vcal = 140
[13:11:38.830] <TB1> INFO: Expecting 41600 events.
[13:11:42.859] <TB1> INFO: 41600 events read in total (3438ms).
[13:11:42.860] <TB1> INFO: Test took 4307ms.
[13:11:42.864] <TB1> INFO: scanning low vcal = 150
[13:11:43.140] <TB1> INFO: Expecting 41600 events.
[13:11:47.197] <TB1> INFO: 41600 events read in total (3465ms).
[13:11:47.198] <TB1> INFO: Test took 4334ms.
[13:11:47.201] <TB1> INFO: scanning low vcal = 160
[13:11:47.519] <TB1> INFO: Expecting 41600 events.
[13:11:51.600] <TB1> INFO: 41600 events read in total (3490ms).
[13:11:51.601] <TB1> INFO: Test took 4400ms.
[13:11:51.604] <TB1> INFO: scanning low vcal = 170
[13:11:51.920] <TB1> INFO: Expecting 41600 events.
[13:11:55.878] <TB1> INFO: 41600 events read in total (3367ms).
[13:11:55.879] <TB1> INFO: Test took 4274ms.
[13:11:55.884] <TB1> INFO: scanning low vcal = 180
[13:11:56.159] <TB1> INFO: Expecting 41600 events.
[13:12:00.117] <TB1> INFO: 41600 events read in total (3367ms).
[13:12:00.118] <TB1> INFO: Test took 4234ms.
[13:12:00.121] <TB1> INFO: scanning low vcal = 190
[13:12:00.398] <TB1> INFO: Expecting 41600 events.
[13:12:04.361] <TB1> INFO: 41600 events read in total (3372ms).
[13:12:04.362] <TB1> INFO: Test took 4241ms.
[13:12:04.365] <TB1> INFO: scanning low vcal = 200
[13:12:04.642] <TB1> INFO: Expecting 41600 events.
[13:12:08.596] <TB1> INFO: 41600 events read in total (3362ms).
[13:12:08.597] <TB1> INFO: Test took 4231ms.
[13:12:08.600] <TB1> INFO: scanning low vcal = 210
[13:12:08.877] <TB1> INFO: Expecting 41600 events.
[13:12:12.834] <TB1> INFO: 41600 events read in total (3365ms).
[13:12:12.835] <TB1> INFO: Test took 4235ms.
[13:12:12.838] <TB1> INFO: scanning low vcal = 220
[13:12:13.115] <TB1> INFO: Expecting 41600 events.
[13:12:17.077] <TB1> INFO: 41600 events read in total (3370ms).
[13:12:17.078] <TB1> INFO: Test took 4240ms.
[13:12:17.081] <TB1> INFO: scanning low vcal = 230
[13:12:17.358] <TB1> INFO: Expecting 41600 events.
[13:12:21.319] <TB1> INFO: 41600 events read in total (3369ms).
[13:12:21.320] <TB1> INFO: Test took 4239ms.
[13:12:21.323] <TB1> INFO: scanning low vcal = 240
[13:12:21.600] <TB1> INFO: Expecting 41600 events.
[13:12:25.558] <TB1> INFO: 41600 events read in total (3366ms).
[13:12:25.559] <TB1> INFO: Test took 4236ms.
[13:12:25.562] <TB1> INFO: scanning low vcal = 250
[13:12:25.839] <TB1> INFO: Expecting 41600 events.
[13:12:29.802] <TB1> INFO: 41600 events read in total (3371ms).
[13:12:29.803] <TB1> INFO: Test took 4241ms.
[13:12:29.807] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[13:12:30.083] <TB1> INFO: Expecting 41600 events.
[13:12:34.053] <TB1> INFO: 41600 events read in total (3378ms).
[13:12:34.054] <TB1> INFO: Test took 4247ms.
[13:12:34.057] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[13:12:34.333] <TB1> INFO: Expecting 41600 events.
[13:12:38.293] <TB1> INFO: 41600 events read in total (3368ms).
[13:12:38.294] <TB1> INFO: Test took 4237ms.
[13:12:38.297] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[13:12:38.574] <TB1> INFO: Expecting 41600 events.
[13:12:42.533] <TB1> INFO: 41600 events read in total (3367ms).
[13:12:42.534] <TB1> INFO: Test took 4236ms.
[13:12:42.538] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[13:12:42.814] <TB1> INFO: Expecting 41600 events.
[13:12:46.781] <TB1> INFO: 41600 events read in total (3375ms).
[13:12:46.783] <TB1> INFO: Test took 4245ms.
[13:12:46.786] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:12:47.063] <TB1> INFO: Expecting 41600 events.
[13:12:51.027] <TB1> INFO: 41600 events read in total (3372ms).
[13:12:51.028] <TB1> INFO: Test took 4242ms.
[13:12:51.411] <TB1> INFO: PixTestGainPedestal::measure() done
[13:13:24.407] <TB1> INFO: PixTestGainPedestal::fit() done
[13:13:24.407] <TB1> INFO: non-linearity mean: 0.939 0.945 0.980 0.968 0.939 0.947 0.923 0.984 0.976 1.025 0.950 0.944 0.945 0.955 0.983 0.982
[13:13:24.407] <TB1> INFO: non-linearity RMS: 0.076 0.152 0.006 0.039 0.158 0.116 0.106 0.003 0.007 0.167 0.055 0.082 0.086 0.039 0.004 0.004
[13:13:24.407] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C0.dat
[13:13:24.421] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C1.dat
[13:13:24.435] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C2.dat
[13:13:24.449] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C3.dat
[13:13:24.462] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C4.dat
[13:13:24.476] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C5.dat
[13:13:24.489] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C6.dat
[13:13:24.503] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C7.dat
[13:13:24.516] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C8.dat
[13:13:24.530] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C9.dat
[13:13:24.543] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C10.dat
[13:13:24.556] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C11.dat
[13:13:24.570] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C12.dat
[13:13:24.583] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C13.dat
[13:13:24.597] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C14.dat
[13:13:24.610] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1007_FullQualification_2016-11-14_09h59m_1479113999//002_Fulltest_p17//phCalibrationFitErr35_C15.dat
[13:13:24.624] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 161 seconds
[13:13:24.624] <TB1> INFO: Decoding statistics:
[13:13:24.624] <TB1> INFO: General information:
[13:13:24.624] <TB1> INFO: 16bit words read: 3279640
[13:13:24.624] <TB1> INFO: valid events total: 332800
[13:13:24.624] <TB1> INFO: empty events: 1198
[13:13:24.624] <TB1> INFO: valid events with pixels: 331602
[13:13:24.624] <TB1> INFO: valid pixel hits: 641419
[13:13:24.624] <TB1> INFO: Event errors: 0
[13:13:24.624] <TB1> INFO: start marker: 0
[13:13:24.624] <TB1> INFO: stop marker: 0
[13:13:24.624] <TB1> INFO: overflow: 0
[13:13:24.624] <TB1> INFO: invalid 5bit words: 0
[13:13:24.624] <TB1> INFO: invalid XOR eye diagram: 0
[13:13:24.624] <TB1> INFO: frame (failed synchr.): 0
[13:13:24.624] <TB1> INFO: idle data (no TBM trl): 0
[13:13:24.624] <TB1> INFO: no data (only TBM hdr): 0
[13:13:24.624] <TB1> INFO: TBM errors: 0
[13:13:24.624] <TB1> INFO: flawed TBM headers: 0
[13:13:24.624] <TB1> INFO: flawed TBM trailers: 0
[13:13:24.624] <TB1> INFO: event ID mismatches: 0
[13:13:24.624] <TB1> INFO: ROC errors: 0
[13:13:24.624] <TB1> INFO: missing ROC header(s): 0
[13:13:24.624] <TB1> INFO: misplaced readback start: 0
[13:13:24.624] <TB1> INFO: Pixel decoding errors: 1
[13:13:24.624] <TB1> INFO: pixel data incomplete: 0
[13:13:24.624] <TB1> INFO: pixel address: 0
[13:13:24.624] <TB1> INFO: pulse height fill bit: 0
[13:13:24.624] <TB1> INFO: buffer corruption: 1
[13:13:24.644] <TB1> INFO: Decoding statistics:
[13:13:24.644] <TB1> INFO: General information:
[13:13:24.644] <TB1> INFO: 16bit words read: 3409058
[13:13:24.644] <TB1> INFO: valid events total: 353536
[13:13:24.644] <TB1> INFO: empty events: 19433
[13:13:24.644] <TB1> INFO: valid events with pixels: 334103
[13:13:24.644] <TB1> INFO: valid pixel hits: 643920
[13:13:24.644] <TB1> INFO: Event errors: 0
[13:13:24.644] <TB1> INFO: start marker: 0
[13:13:24.644] <TB1> INFO: stop marker: 0
[13:13:24.644] <TB1> INFO: overflow: 0
[13:13:24.644] <TB1> INFO: invalid 5bit words: 0
[13:13:24.644] <TB1> INFO: invalid XOR eye diagram: 0
[13:13:24.644] <TB1> INFO: frame (failed synchr.): 0
[13:13:24.644] <TB1> INFO: idle data (no TBM trl): 0
[13:13:24.644] <TB1> INFO: no data (only TBM hdr): 0
[13:13:24.644] <TB1> INFO: TBM errors: 0
[13:13:24.644] <TB1> INFO: flawed TBM headers: 0
[13:13:24.644] <TB1> INFO: flawed TBM trailers: 0
[13:13:24.644] <TB1> INFO: event ID mismatches: 0
[13:13:24.644] <TB1> INFO: ROC errors: 0
[13:13:24.644] <TB1> INFO: missing ROC header(s): 0
[13:13:24.644] <TB1> INFO: misplaced readback start: 0
[13:13:24.644] <TB1> INFO: Pixel decoding errors: 1
[13:13:24.644] <TB1> INFO: pixel data incomplete: 0
[13:13:24.644] <TB1> INFO: pixel address: 0
[13:13:24.644] <TB1> INFO: pulse height fill bit: 0
[13:13:24.644] <TB1> INFO: buffer corruption: 1
[13:13:24.644] <TB1> INFO: enter test to run
[13:13:24.644] <TB1> INFO: test: exit no parameter change
[13:13:24.797] <TB1> QUIET: Connection to board 154 closed.
[13:13:24.798] <TB1> INFO: pXar: this is the end, my friend