[17:07:26.671] <TB1> INFO: *** Welcome to pxar ***
[17:07:26.671] <TB1> INFO: *** Today: 2016/11/03
[17:07:26.680] <TB1> INFO: *** Version: c8ba-dirty
[17:07:26.680] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C15.dat
[17:07:26.680] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[17:07:26.680] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//defaultMaskFile.dat
[17:07:26.680] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters_C15.dat
[17:07:26.734] <TB1> INFO: clk: 4
[17:07:26.734] <TB1> INFO: ctr: 4
[17:07:26.734] <TB1> INFO: sda: 19
[17:07:26.734] <TB1> INFO: tin: 9
[17:07:26.734] <TB1> INFO: level: 15
[17:07:26.734] <TB1> INFO: triggerdelay: 0
[17:07:26.735] <TB1> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[17:07:26.735] <TB1> INFO: Log level: INFO
[17:07:26.743] <TB1> INFO: Found DTB DTB_WXBYFL
[17:07:26.753] <TB1> QUIET: Connection to board DTB_WXBYFL opened.
[17:07:26.755] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 153
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXBYFL
MAC address: 40D855118099
Hostname: pixelDTB153
Comment:
------------------------------------------------------
[17:07:26.756] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[17:07:28.308] <TB1> INFO: DUT info:
[17:07:28.309] <TB1> INFO: The DUT currently contains the following objects:
[17:07:28.309] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[17:07:28.309] <TB1> INFO: TBM Core alpha (0): 7 registers set
[17:07:28.309] <TB1> INFO: TBM Core beta (1): 7 registers set
[17:07:28.309] <TB1> INFO: TBM Core alpha (2): 7 registers set
[17:07:28.309] <TB1> INFO: TBM Core beta (3): 7 registers set
[17:07:28.309] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[17:07:28.309] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[17:07:28.309] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[17:07:28.309] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[17:07:28.309] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[17:07:28.309] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[17:07:28.309] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[17:07:28.309] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[17:07:28.309] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[17:07:28.309] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[17:07:28.309] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[17:07:28.309] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[17:07:28.309] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[17:07:28.309] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[17:07:28.309] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[17:07:28.309] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[17:07:28.309] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[17:07:28.709] <TB1> INFO: enter 'restricted' command line mode
[17:07:28.709] <TB1> INFO: enter test to run
[17:07:28.710] <TB1> INFO: test: pretest no parameter change
[17:07:28.710] <TB1> INFO: running: pretest
[17:07:29.254] <TB1> INFO: ######################################################################
[17:07:29.254] <TB1> INFO: PixTestPretest::doTest()
[17:07:29.254] <TB1> INFO: ######################################################################
[17:07:29.255] <TB1> INFO: ----------------------------------------------------------------------
[17:07:29.255] <TB1> INFO: PixTestPretest::programROC()
[17:07:29.255] <TB1> INFO: ----------------------------------------------------------------------
[17:07:47.268] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[17:07:47.268] <TB1> INFO: IA differences per ROC: 16.1 19.3 18.5 16.9 17.7 16.9 19.3 20.1 20.1 20.1 21.7 17.7 19.3 20.1 16.9 19.3
[17:07:47.301] <TB1> INFO: ----------------------------------------------------------------------
[17:07:47.301] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[17:07:47.301] <TB1> INFO: ----------------------------------------------------------------------
[17:08:08.541] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 404.4 mA = 25.275 mA/ROC
[17:08:08.541] <TB1> INFO: i(loss) [mA/ROC]: 20.9 20.9 20.9 20.1 20.1 20.1 21.7 19.3 20.9 19.3 19.3 20.1 20.9 20.1 20.1 20.9
[17:08:08.571] <TB1> INFO: ----------------------------------------------------------------------
[17:08:08.571] <TB1> INFO: PixTestPretest::findTiming()
[17:08:08.571] <TB1> INFO: ----------------------------------------------------------------------
[17:08:08.571] <TB1> INFO: PixTestCmd::init()

[17:08:39.799] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[17:08:39.799] <TB1> INFO: (success/tries = 100/100), width = 3
[17:08:41.299] <TB1> INFO: ----------------------------------------------------------------------
[17:08:41.300] <TB1> INFO: PixTestPretest::findWorkingPixel()
[17:08:41.300] <TB1> INFO: ----------------------------------------------------------------------
[17:08:41.391] <TB1> INFO: Expecting 231680 events.
[17:08:51.048] <TB1> INFO: 231680 events read in total (9066ms).
[17:08:51.055] <TB1> INFO: Test took 9753ms.
[17:08:51.300] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[17:08:51.329] <TB1> INFO: ----------------------------------------------------------------------
[17:08:51.329] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[17:08:51.329] <TB1> INFO: ----------------------------------------------------------------------
[17:08:51.421] <TB1> INFO: Expecting 231680 events.
[17:09:01.085] <TB1> INFO: 231680 events read in total (9072ms).
[17:09:01.092] <TB1> INFO: Test took 9760ms.
[17:09:01.349] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[17:09:01.349] <TB1> INFO: CalDel: 85 102 82 91 84 85 81 101 111 95 92 78 99 110 92 99
[17:09:01.349] <TB1> INFO: VthrComp: 51 56 55 52 51 54 54 51 51 53 54 55 53 57 52 56
[17:09:01.351] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C0.dat
[17:09:01.352] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C1.dat
[17:09:01.352] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C2.dat
[17:09:01.352] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C3.dat
[17:09:01.352] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C4.dat
[17:09:01.352] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C5.dat
[17:09:01.352] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C6.dat
[17:09:01.352] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C7.dat
[17:09:01.352] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C8.dat
[17:09:01.352] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C9.dat
[17:09:01.353] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C10.dat
[17:09:01.353] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C11.dat
[17:09:01.353] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C12.dat
[17:09:01.353] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C13.dat
[17:09:01.353] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C14.dat
[17:09:01.353] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters_C15.dat
[17:09:01.353] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[17:09:01.353] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[17:09:01.353] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[17:09:01.353] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[17:09:01.354] <TB1> INFO: PixTestPretest::doTest() done, duration: 92 seconds
[17:09:01.448] <TB1> INFO: enter test to run
[17:09:01.448] <TB1> INFO: test: fulltest no parameter change
[17:09:01.448] <TB1> INFO: running: fulltest
[17:09:01.448] <TB1> INFO: ######################################################################
[17:09:01.448] <TB1> INFO: PixTestFullTest::doTest()
[17:09:01.448] <TB1> INFO: ######################################################################
[17:09:01.450] <TB1> INFO: ######################################################################
[17:09:01.450] <TB1> INFO: PixTestAlive::doTest()
[17:09:01.450] <TB1> INFO: ######################################################################
[17:09:01.451] <TB1> INFO: ----------------------------------------------------------------------
[17:09:01.451] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[17:09:01.451] <TB1> INFO: ----------------------------------------------------------------------
[17:09:01.684] <TB1> INFO: Expecting 41600 events.
[17:09:05.106] <TB1> INFO: 41600 events read in total (2831ms).
[17:09:05.106] <TB1> INFO: Test took 3654ms.
[17:09:05.332] <TB1> INFO: PixTestAlive::aliveTest() done
[17:09:05.332] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
[17:09:05.333] <TB1> INFO: ----------------------------------------------------------------------
[17:09:05.334] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[17:09:05.334] <TB1> INFO: ----------------------------------------------------------------------
[17:09:05.611] <TB1> INFO: Expecting 41600 events.
[17:09:08.599] <TB1> INFO: 41600 events read in total (2397ms).
[17:09:08.599] <TB1> INFO: Test took 3264ms.
[17:09:08.600] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[17:09:08.836] <TB1> INFO: PixTestAlive::maskTest() done
[17:09:08.836] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[17:09:08.837] <TB1> INFO: ----------------------------------------------------------------------
[17:09:08.837] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[17:09:08.837] <TB1> INFO: ----------------------------------------------------------------------
[17:09:09.092] <TB1> INFO: Expecting 41600 events.
[17:09:12.532] <TB1> INFO: 41600 events read in total (2848ms).
[17:09:12.533] <TB1> INFO: Test took 3694ms.
[17:09:12.760] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[17:09:12.760] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[17:09:12.760] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[17:09:12.760] <TB1> INFO: Decoding statistics:
[17:09:12.760] <TB1> INFO: General information:
[17:09:12.760] <TB1> INFO: 16bit words read: 0
[17:09:12.760] <TB1> INFO: valid events total: 0
[17:09:12.760] <TB1> INFO: empty events: 0
[17:09:12.760] <TB1> INFO: valid events with pixels: 0
[17:09:12.760] <TB1> INFO: valid pixel hits: 0
[17:09:12.760] <TB1> INFO: Event errors: 0
[17:09:12.760] <TB1> INFO: start marker: 0
[17:09:12.760] <TB1> INFO: stop marker: 0
[17:09:12.760] <TB1> INFO: overflow: 0
[17:09:12.760] <TB1> INFO: invalid 5bit words: 0
[17:09:12.760] <TB1> INFO: invalid XOR eye diagram: 0
[17:09:12.760] <TB1> INFO: frame (failed synchr.): 0
[17:09:12.760] <TB1> INFO: idle data (no TBM trl): 0
[17:09:12.760] <TB1> INFO: no data (only TBM hdr): 0
[17:09:12.760] <TB1> INFO: TBM errors: 0
[17:09:12.760] <TB1> INFO: flawed TBM headers: 0
[17:09:12.760] <TB1> INFO: flawed TBM trailers: 0
[17:09:12.760] <TB1> INFO: event ID mismatches: 0
[17:09:12.760] <TB1> INFO: ROC errors: 0
[17:09:12.760] <TB1> INFO: missing ROC header(s): 0
[17:09:12.760] <TB1> INFO: misplaced readback start: 0
[17:09:12.760] <TB1> INFO: Pixel decoding errors: 0
[17:09:12.760] <TB1> INFO: pixel data incomplete: 0
[17:09:12.760] <TB1> INFO: pixel address: 0
[17:09:12.760] <TB1> INFO: pulse height fill bit: 0
[17:09:12.760] <TB1> INFO: buffer corruption: 0
[17:09:12.767] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C15.dat
[17:09:12.767] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[17:09:12.767] <TB1> INFO: ######################################################################
[17:09:12.767] <TB1> INFO: PixTestReadback::doTest()
[17:09:12.767] <TB1> INFO: ######################################################################
[17:09:12.767] <TB1> INFO: ----------------------------------------------------------------------
[17:09:12.768] <TB1> INFO: PixTestReadback::CalibrateVd()
[17:09:12.768] <TB1> INFO: ----------------------------------------------------------------------
[17:09:22.738] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C0.dat
[17:09:22.738] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C1.dat
[17:09:22.739] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C2.dat
[17:09:22.739] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C3.dat
[17:09:22.739] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C4.dat
[17:09:22.739] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C5.dat
[17:09:22.739] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C6.dat
[17:09:22.739] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C7.dat
[17:09:22.739] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C8.dat
[17:09:22.739] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C9.dat
[17:09:22.739] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C10.dat
[17:09:22.739] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C11.dat
[17:09:22.739] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C12.dat
[17:09:22.739] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C13.dat
[17:09:22.739] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C14.dat
[17:09:22.739] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C15.dat
[17:09:22.766] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[17:09:22.766] <TB1> INFO: ----------------------------------------------------------------------
[17:09:22.766] <TB1> INFO: PixTestReadback::CalibrateVa()
[17:09:22.766] <TB1> INFO: ----------------------------------------------------------------------
[17:09:32.655] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C0.dat
[17:09:32.655] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C1.dat
[17:09:32.655] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C2.dat
[17:09:32.655] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C3.dat
[17:09:32.655] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C4.dat
[17:09:32.655] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C5.dat
[17:09:32.656] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C6.dat
[17:09:32.656] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C7.dat
[17:09:32.656] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C8.dat
[17:09:32.656] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C9.dat
[17:09:32.656] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C10.dat
[17:09:32.656] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C11.dat
[17:09:32.656] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C12.dat
[17:09:32.656] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C13.dat
[17:09:32.656] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C14.dat
[17:09:32.656] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C15.dat
[17:09:32.685] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[17:09:32.685] <TB1> INFO: ----------------------------------------------------------------------
[17:09:32.685] <TB1> INFO: PixTestReadback::readbackVbg()
[17:09:32.685] <TB1> INFO: ----------------------------------------------------------------------
[17:09:40.324] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[17:09:40.324] <TB1> INFO: ----------------------------------------------------------------------
[17:09:40.324] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[17:09:40.324] <TB1> INFO: ----------------------------------------------------------------------
[17:09:40.324] <TB1> INFO: Vbg will be calibrated using Vd calibration
[17:09:40.324] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 158.4calibrated Vbg = 1.16157 :::*/*/*/*/
[17:09:40.324] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 163calibrated Vbg = 1.1613 :::*/*/*/*/
[17:09:40.324] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 153.2calibrated Vbg = 1.16364 :::*/*/*/*/
[17:09:40.324] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 158.2calibrated Vbg = 1.14973 :::*/*/*/*/
[17:09:40.324] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 157.8calibrated Vbg = 1.15777 :::*/*/*/*/
[17:09:40.324] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 156.7calibrated Vbg = 1.15899 :::*/*/*/*/
[17:09:40.324] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 158.4calibrated Vbg = 1.16695 :::*/*/*/*/
[17:09:40.324] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 150.7calibrated Vbg = 1.16166 :::*/*/*/*/
[17:09:40.324] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 157.7calibrated Vbg = 1.15567 :::*/*/*/*/
[17:09:40.324] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 163.3calibrated Vbg = 1.15405 :::*/*/*/*/
[17:09:40.324] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 162.3calibrated Vbg = 1.14849 :::*/*/*/*/
[17:09:40.324] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 159.1calibrated Vbg = 1.13934 :::*/*/*/*/
[17:09:40.324] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 158.6calibrated Vbg = 1.16026 :::*/*/*/*/
[17:09:40.324] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 158.9calibrated Vbg = 1.1611 :::*/*/*/*/
[17:09:40.324] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 159.8calibrated Vbg = 1.15749 :::*/*/*/*/
[17:09:40.324] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 159.8calibrated Vbg = 1.15838 :::*/*/*/*/
[17:09:40.326] <TB1> INFO: ----------------------------------------------------------------------
[17:09:40.326] <TB1> INFO: PixTestReadback::CalibrateIa()
[17:09:40.326] <TB1> INFO: ----------------------------------------------------------------------
[17:12:20.615] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C0.dat
[17:12:20.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C1.dat
[17:12:20.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C2.dat
[17:12:20.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C3.dat
[17:12:20.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C4.dat
[17:12:20.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C5.dat
[17:12:20.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C6.dat
[17:12:20.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C7.dat
[17:12:20.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C8.dat
[17:12:20.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C9.dat
[17:12:20.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C10.dat
[17:12:20.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C11.dat
[17:12:20.616] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C12.dat
[17:12:20.617] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C13.dat
[17:12:20.617] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C14.dat
[17:12:20.617] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//readbackCal_C15.dat
[17:12:20.644] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[17:12:20.646] <TB1> INFO: PixTestReadback::doTest() done
[17:12:20.646] <TB1> INFO: Decoding statistics:
[17:12:20.646] <TB1> INFO: General information:
[17:12:20.646] <TB1> INFO: 16bit words read: 1536
[17:12:20.646] <TB1> INFO: valid events total: 256
[17:12:20.646] <TB1> INFO: empty events: 256
[17:12:20.646] <TB1> INFO: valid events with pixels: 0
[17:12:20.646] <TB1> INFO: valid pixel hits: 0
[17:12:20.646] <TB1> INFO: Event errors: 0
[17:12:20.646] <TB1> INFO: start marker: 0
[17:12:20.646] <TB1> INFO: stop marker: 0
[17:12:20.646] <TB1> INFO: overflow: 0
[17:12:20.646] <TB1> INFO: invalid 5bit words: 0
[17:12:20.646] <TB1> INFO: invalid XOR eye diagram: 0
[17:12:20.646] <TB1> INFO: frame (failed synchr.): 0
[17:12:20.646] <TB1> INFO: idle data (no TBM trl): 0
[17:12:20.646] <TB1> INFO: no data (only TBM hdr): 0
[17:12:20.646] <TB1> INFO: TBM errors: 0
[17:12:20.646] <TB1> INFO: flawed TBM headers: 0
[17:12:20.646] <TB1> INFO: flawed TBM trailers: 0
[17:12:20.646] <TB1> INFO: event ID mismatches: 0
[17:12:20.646] <TB1> INFO: ROC errors: 0
[17:12:20.646] <TB1> INFO: missing ROC header(s): 0
[17:12:20.646] <TB1> INFO: misplaced readback start: 0
[17:12:20.646] <TB1> INFO: Pixel decoding errors: 0
[17:12:20.646] <TB1> INFO: pixel data incomplete: 0
[17:12:20.646] <TB1> INFO: pixel address: 0
[17:12:20.646] <TB1> INFO: pulse height fill bit: 0
[17:12:20.646] <TB1> INFO: buffer corruption: 0
[17:12:20.693] <TB1> INFO: ######################################################################
[17:12:20.693] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[17:12:20.693] <TB1> INFO: ######################################################################
[17:12:20.695] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[17:12:20.707] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[17:12:20.707] <TB1> INFO: run 1 of 1
[17:12:20.938] <TB1> INFO: Expecting 3120000 events.
[17:12:51.327] <TB1> INFO: 680915 events read in total (29797ms).











[17:13:21.146] <TB1> INFO: 1355805 events read in total (59616ms).
[17:13:50.992] <TB1> INFO: 2027125 events read in total (89462ms).











[17:14:20.947] <TB1> INFO: 2700340 events read in total (119417ms).











[17:14:39.817] <TB1> INFO: 3120000 events read in total (138287ms).
[17:14:39.867] <TB1> INFO: Test took 139161ms.
[17:15:06.346] <TB1> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 165 seconds
[17:15:06.346] <TB1> INFO: number of dead bumps (per ROC): 10 1 0 0 1 0 0 0 0 3 0 0 0 0 2 3
[17:15:06.346] <TB1> INFO: separation cut (per ROC): 106 132 128 106 101 119 124 100 127 121 127 123 124 107 110 126
[17:15:06.346] <TB1> INFO: Decoding statistics:
[17:15:06.346] <TB1> INFO: General information:
[17:15:06.346] <TB1> INFO: 16bit words read: 0
[17:15:06.347] <TB1> INFO: valid events total: 0
[17:15:06.347] <TB1> INFO: empty events: 0
[17:15:06.347] <TB1> INFO: valid events with pixels: 0
[17:15:06.347] <TB1> INFO: valid pixel hits: 0
[17:15:06.347] <TB1> INFO: Event errors: 0
[17:15:06.347] <TB1> INFO: start marker: 0
[17:15:06.347] <TB1> INFO: stop marker: 0
[17:15:06.347] <TB1> INFO: overflow: 0
[17:15:06.347] <TB1> INFO: invalid 5bit words: 0
[17:15:06.347] <TB1> INFO: invalid XOR eye diagram: 0
[17:15:06.347] <TB1> INFO: frame (failed synchr.): 0
[17:15:06.347] <TB1> INFO: idle data (no TBM trl): 0
[17:15:06.347] <TB1> INFO: no data (only TBM hdr): 0
[17:15:06.347] <TB1> INFO: TBM errors: 0
[17:15:06.347] <TB1> INFO: flawed TBM headers: 0
[17:15:06.347] <TB1> INFO: flawed TBM trailers: 0
[17:15:06.347] <TB1> INFO: event ID mismatches: 0
[17:15:06.347] <TB1> INFO: ROC errors: 0
[17:15:06.347] <TB1> INFO: missing ROC header(s): 0
[17:15:06.347] <TB1> INFO: misplaced readback start: 0
[17:15:06.347] <TB1> INFO: Pixel decoding errors: 0
[17:15:06.347] <TB1> INFO: pixel data incomplete: 0
[17:15:06.347] <TB1> INFO: pixel address: 0
[17:15:06.347] <TB1> INFO: pulse height fill bit: 0
[17:15:06.347] <TB1> INFO: buffer corruption: 0
[17:15:06.388] <TB1> INFO: ######################################################################
[17:15:06.388] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[17:15:06.388] <TB1> INFO: ######################################################################
[17:15:06.389] <TB1> INFO: ----------------------------------------------------------------------
[17:15:06.389] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[17:15:06.389] <TB1> INFO: ----------------------------------------------------------------------
[17:15:06.389] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[17:15:06.399] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[17:15:06.400] <TB1> INFO: run 1 of 1
[17:15:06.637] <TB1> INFO: Expecting 36608000 events.
[17:15:29.836] <TB1> INFO: 709250 events read in total (22604ms).
[17:15:52.245] <TB1> INFO: 1402700 events read in total (45013ms).
[17:16:14.904] <TB1> INFO: 2094550 events read in total (67672ms).
[17:16:37.841] <TB1> INFO: 2787500 events read in total (90609ms).
[17:17:00.392] <TB1> INFO: 3479700 events read in total (113160ms).
[17:17:22.898] <TB1> INFO: 4171300 events read in total (135666ms).
[17:17:45.613] <TB1> INFO: 4863450 events read in total (158381ms).
[17:18:08.332] <TB1> INFO: 5553600 events read in total (181100ms).
[17:18:31.040] <TB1> INFO: 6245600 events read in total (203808ms).
[17:18:53.899] <TB1> INFO: 6937600 events read in total (226667ms).
[17:19:16.509] <TB1> INFO: 7627900 events read in total (249277ms).
[17:19:38.943] <TB1> INFO: 8317050 events read in total (271711ms).
[17:20:01.352] <TB1> INFO: 9008750 events read in total (294120ms).
[17:20:23.967] <TB1> INFO: 9699550 events read in total (316735ms).
[17:20:46.712] <TB1> INFO: 10388850 events read in total (339480ms).
[17:21:09.406] <TB1> INFO: 11076900 events read in total (362174ms).
[17:21:31.924] <TB1> INFO: 11764650 events read in total (384692ms).
[17:21:54.638] <TB1> INFO: 12454200 events read in total (407406ms).
[17:22:17.298] <TB1> INFO: 13142750 events read in total (430066ms).
[17:22:40.056] <TB1> INFO: 13831000 events read in total (452824ms).
[17:23:02.406] <TB1> INFO: 14518000 events read in total (475174ms).
[17:23:24.834] <TB1> INFO: 15205000 events read in total (497602ms).
[17:23:47.514] <TB1> INFO: 15890950 events read in total (520282ms).
[17:24:09.976] <TB1> INFO: 16577200 events read in total (542744ms).
[17:24:32.543] <TB1> INFO: 17263050 events read in total (565311ms).
[17:24:55.176] <TB1> INFO: 17947100 events read in total (587944ms).
[17:25:17.561] <TB1> INFO: 18630850 events read in total (610329ms).
[17:25:40.131] <TB1> INFO: 19315050 events read in total (632899ms).
[17:26:02.731] <TB1> INFO: 19999300 events read in total (655499ms).
[17:26:25.253] <TB1> INFO: 20680650 events read in total (678021ms).
[17:26:47.688] <TB1> INFO: 21363000 events read in total (700456ms).
[17:27:09.914] <TB1> INFO: 22043450 events read in total (722682ms).
[17:27:32.553] <TB1> INFO: 22726400 events read in total (745321ms).
[17:27:55.037] <TB1> INFO: 23407850 events read in total (767805ms).
[17:28:17.585] <TB1> INFO: 24090800 events read in total (790353ms).
[17:28:40.020] <TB1> INFO: 24771200 events read in total (812788ms).
[17:29:02.621] <TB1> INFO: 25455100 events read in total (835389ms).
[17:29:25.261] <TB1> INFO: 26134900 events read in total (858029ms).
[17:29:48.179] <TB1> INFO: 26818200 events read in total (880947ms).
[17:30:10.906] <TB1> INFO: 27498900 events read in total (903674ms).
[17:30:33.423] <TB1> INFO: 28180200 events read in total (926191ms).
[17:30:55.978] <TB1> INFO: 28860800 events read in total (948746ms).
[17:31:18.546] <TB1> INFO: 29542800 events read in total (971314ms).
[17:31:41.438] <TB1> INFO: 30224250 events read in total (994206ms).
[17:32:04.269] <TB1> INFO: 30904550 events read in total (1017037ms).
[17:32:27.037] <TB1> INFO: 31586250 events read in total (1039805ms).
[17:32:49.830] <TB1> INFO: 32268650 events read in total (1062598ms).
[17:33:12.514] <TB1> INFO: 32951900 events read in total (1085282ms).
[17:33:35.029] <TB1> INFO: 33634600 events read in total (1107797ms).
[17:33:57.586] <TB1> INFO: 34317750 events read in total (1130354ms).
[17:34:20.037] <TB1> INFO: 35001200 events read in total (1152805ms).
[17:34:42.604] <TB1> INFO: 35683750 events read in total (1175372ms).
[17:35:05.361] <TB1> INFO: 36378500 events read in total (1198129ms).
[17:35:13.248] <TB1> INFO: 36608000 events read in total (1206016ms).
[17:35:13.296] <TB1> INFO: Test took 1206896ms.
[17:35:13.595] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:35:15.572] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:35:17.419] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:35:19.207] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:35:20.984] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:35:22.488] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:35:24.136] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:35:25.842] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:35:27.534] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:35:29.275] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:35:31.323] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:35:33.061] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:35:35.030] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:35:36.863] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:35:39.130] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:35:41.061] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[17:35:43.126] <TB1> INFO: PixTestScurves::scurves() done
[17:35:43.126] <TB1> INFO: Vcal mean: 130.60 139.51 136.98 125.46 114.40 132.57 135.43 123.36 141.65 137.41 133.91 134.64 140.61 129.65 135.29 135.06
[17:35:43.126] <TB1> INFO: Vcal RMS: 5.97 5.82 6.22 6.72 5.07 6.12 6.12 6.72 5.94 6.19 5.79 6.27 5.96 6.38 6.18 6.32
[17:35:43.126] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1236 seconds
[17:35:43.126] <TB1> INFO: Decoding statistics:
[17:35:43.126] <TB1> INFO: General information:
[17:35:43.126] <TB1> INFO: 16bit words read: 0
[17:35:43.126] <TB1> INFO: valid events total: 0
[17:35:43.126] <TB1> INFO: empty events: 0
[17:35:43.126] <TB1> INFO: valid events with pixels: 0
[17:35:43.126] <TB1> INFO: valid pixel hits: 0
[17:35:43.126] <TB1> INFO: Event errors: 0
[17:35:43.126] <TB1> INFO: start marker: 0
[17:35:43.126] <TB1> INFO: stop marker: 0
[17:35:43.127] <TB1> INFO: overflow: 0
[17:35:43.127] <TB1> INFO: invalid 5bit words: 0
[17:35:43.127] <TB1> INFO: invalid XOR eye diagram: 0
[17:35:43.127] <TB1> INFO: frame (failed synchr.): 0
[17:35:43.127] <TB1> INFO: idle data (no TBM trl): 0
[17:35:43.127] <TB1> INFO: no data (only TBM hdr): 0
[17:35:43.127] <TB1> INFO: TBM errors: 0
[17:35:43.127] <TB1> INFO: flawed TBM headers: 0
[17:35:43.127] <TB1> INFO: flawed TBM trailers: 0
[17:35:43.127] <TB1> INFO: event ID mismatches: 0
[17:35:43.127] <TB1> INFO: ROC errors: 0
[17:35:43.127] <TB1> INFO: missing ROC header(s): 0
[17:35:43.127] <TB1> INFO: misplaced readback start: 0
[17:35:43.127] <TB1> INFO: Pixel decoding errors: 0
[17:35:43.127] <TB1> INFO: pixel data incomplete: 0
[17:35:43.127] <TB1> INFO: pixel address: 0
[17:35:43.127] <TB1> INFO: pulse height fill bit: 0
[17:35:43.127] <TB1> INFO: buffer corruption: 0
[17:35:43.200] <TB1> INFO: ######################################################################
[17:35:43.200] <TB1> INFO: PixTestTrim::doTest()
[17:35:43.200] <TB1> INFO: ######################################################################
[17:35:43.201] <TB1> INFO: ----------------------------------------------------------------------
[17:35:43.201] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[17:35:43.201] <TB1> INFO: ----------------------------------------------------------------------
[17:35:43.253] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[17:35:43.253] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:35:43.263] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:35:43.263] <TB1> INFO: run 1 of 1
[17:35:43.502] <TB1> INFO: Expecting 5025280 events.
[17:36:14.439] <TB1> INFO: 839440 events read in total (30345ms).
[17:36:45.040] <TB1> INFO: 1677232 events read in total (60946ms).
[17:37:14.868] <TB1> INFO: 2512696 events read in total (90774ms).
[17:37:44.721] <TB1> INFO: 3344264 events read in total (120627ms).
[17:38:14.624] <TB1> INFO: 4173512 events read in total (150530ms).
[17:38:44.558] <TB1> INFO: 5003376 events read in total (180464ms).
[17:38:45.753] <TB1> INFO: 5025280 events read in total (181659ms).
[17:38:45.788] <TB1> INFO: Test took 182525ms.
[17:38:57.210] <TB1> INFO: ROC 0 VthrComp = 128
[17:38:57.210] <TB1> INFO: ROC 1 VthrComp = 136
[17:38:57.210] <TB1> INFO: ROC 2 VthrComp = 137
[17:38:57.210] <TB1> INFO: ROC 3 VthrComp = 127
[17:38:57.210] <TB1> INFO: ROC 4 VthrComp = 114
[17:38:57.210] <TB1> INFO: ROC 5 VthrComp = 132
[17:38:57.210] <TB1> INFO: ROC 6 VthrComp = 134
[17:38:57.211] <TB1> INFO: ROC 7 VthrComp = 119
[17:38:57.211] <TB1> INFO: ROC 8 VthrComp = 134
[17:38:57.211] <TB1> INFO: ROC 9 VthrComp = 133
[17:38:57.211] <TB1> INFO: ROC 10 VthrComp = 133
[17:38:57.211] <TB1> INFO: ROC 11 VthrComp = 132
[17:38:57.211] <TB1> INFO: ROC 12 VthrComp = 136
[17:38:57.211] <TB1> INFO: ROC 13 VthrComp = 129
[17:38:57.211] <TB1> INFO: ROC 14 VthrComp = 129
[17:38:57.211] <TB1> INFO: ROC 15 VthrComp = 136
[17:38:57.457] <TB1> INFO: Expecting 41600 events.
[17:39:00.904] <TB1> INFO: 41600 events read in total (2855ms).
[17:39:00.905] <TB1> INFO: Test took 3692ms.
[17:39:00.915] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[17:39:00.915] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:39:00.925] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:39:00.925] <TB1> INFO: run 1 of 1
[17:39:01.203] <TB1> INFO: Expecting 5025280 events.
[17:39:27.367] <TB1> INFO: 593984 events read in total (25572ms).
[17:39:52.591] <TB1> INFO: 1187088 events read in total (50796ms).
[17:40:18.056] <TB1> INFO: 1780000 events read in total (76261ms).
[17:40:43.475] <TB1> INFO: 2372168 events read in total (101680ms).
[17:41:08.763] <TB1> INFO: 2962128 events read in total (126968ms).
[17:41:34.241] <TB1> INFO: 3551504 events read in total (152446ms).
[17:41:59.304] <TB1> INFO: 4140752 events read in total (177509ms).
[17:42:24.396] <TB1> INFO: 4730336 events read in total (202601ms).
[17:42:37.288] <TB1> INFO: 5025280 events read in total (215493ms).
[17:42:37.349] <TB1> INFO: Test took 216425ms.
[17:43:03.904] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 63.644 for pixel 4/9 mean/min/max = 47.6158/31.5684/63.6633
[17:43:03.904] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 69.344 for pixel 50/0 mean/min/max = 53.0305/36.486/69.5751
[17:43:03.904] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 68.7406 for pixel 1/9 mean/min/max = 52.819/36.8841/68.7538
[17:43:03.905] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 61.9615 for pixel 36/2 mean/min/max = 46.5631/31.1592/61.9671
[17:43:03.905] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 60.4607 for pixel 0/1 mean/min/max = 46.8402/33.0403/60.64
[17:43:03.905] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 62.6434 for pixel 1/10 mean/min/max = 48.0569/33.4214/62.6924
[17:43:03.906] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 69.5535 for pixel 6/6 mean/min/max = 53.3232/37.0637/69.5827
[17:43:03.906] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 62.8982 for pixel 0/17 mean/min/max = 46.9079/30.8384/62.9774
[17:43:03.907] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 67.5633 for pixel 17/7 mean/min/max = 51.9042/35.7435/68.0648
[17:43:03.907] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 68.7245 for pixel 17/3 mean/min/max = 51.0501/33.3327/68.7675
[17:43:03.907] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 67.6391 for pixel 37/19 mean/min/max = 51.4459/35.0986/67.7931
[17:43:03.907] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 69.0121 for pixel 11/7 mean/min/max = 51.8096/34.468/69.1512
[17:43:03.908] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 68.6013 for pixel 11/1 mean/min/max = 53.0421/37.4725/68.6118
[17:43:03.908] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 63.9408 for pixel 5/1 mean/min/max = 47.979/31.8364/64.1216
[17:43:03.908] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 65.0972 for pixel 12/5 mean/min/max = 48.7541/32.3722/65.136
[17:43:03.909] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 66.6717 for pixel 0/27 mean/min/max = 50.9102/34.3568/67.4636
[17:43:03.909] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:43:03.998] <TB1> INFO: Expecting 411648 events.
[17:43:13.456] <TB1> INFO: 411648 events read in total (8867ms).
[17:43:13.463] <TB1> INFO: Expecting 411648 events.
[17:43:22.731] <TB1> INFO: 411648 events read in total (8865ms).
[17:43:22.741] <TB1> INFO: Expecting 411648 events.
[17:43:31.982] <TB1> INFO: 411648 events read in total (8838ms).
[17:43:31.998] <TB1> INFO: Expecting 411648 events.
[17:43:41.196] <TB1> INFO: 411648 events read in total (8795ms).
[17:43:41.215] <TB1> INFO: Expecting 411648 events.
[17:43:50.274] <TB1> INFO: 411648 events read in total (8656ms).
[17:43:50.291] <TB1> INFO: Expecting 411648 events.
[17:43:59.342] <TB1> INFO: 411648 events read in total (8648ms).
[17:43:59.367] <TB1> INFO: Expecting 411648 events.
[17:44:08.418] <TB1> INFO: 411648 events read in total (8648ms).
[17:44:08.441] <TB1> INFO: Expecting 411648 events.
[17:44:17.480] <TB1> INFO: 411648 events read in total (8636ms).
[17:44:17.512] <TB1> INFO: Expecting 411648 events.
[17:44:26.604] <TB1> INFO: 411648 events read in total (8690ms).
[17:44:26.637] <TB1> INFO: Expecting 411648 events.
[17:44:35.740] <TB1> INFO: 411648 events read in total (8693ms).
[17:44:35.780] <TB1> INFO: Expecting 411648 events.
[17:44:44.885] <TB1> INFO: 411648 events read in total (8702ms).
[17:44:44.919] <TB1> INFO: Expecting 411648 events.
[17:44:53.967] <TB1> INFO: 411648 events read in total (8645ms).
[17:44:54.003] <TB1> INFO: Expecting 411648 events.
[17:45:03.076] <TB1> INFO: 411648 events read in total (8670ms).
[17:45:03.125] <TB1> INFO: Expecting 411648 events.
[17:45:12.128] <TB1> INFO: 411648 events read in total (8600ms).
[17:45:12.168] <TB1> INFO: Expecting 411648 events.
[17:45:21.232] <TB1> INFO: 411648 events read in total (8661ms).
[17:45:21.275] <TB1> INFO: Expecting 411648 events.
[17:45:30.315] <TB1> INFO: 411648 events read in total (8637ms).
[17:45:30.376] <TB1> INFO: Test took 146467ms.
[17:45:31.058] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[17:45:31.069] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:45:31.069] <TB1> INFO: run 1 of 1
[17:45:31.303] <TB1> INFO: Expecting 5025280 events.
[17:45:57.118] <TB1> INFO: 593624 events read in total (25223ms).
[17:46:22.587] <TB1> INFO: 1186688 events read in total (50692ms).
[17:46:47.988] <TB1> INFO: 1778016 events read in total (76093ms).
[17:47:13.537] <TB1> INFO: 2369352 events read in total (101642ms).
[17:47:39.397] <TB1> INFO: 2963432 events read in total (127502ms).
[17:48:04.890] <TB1> INFO: 3558888 events read in total (152995ms).
[17:48:30.448] <TB1> INFO: 4154392 events read in total (178553ms).
[17:48:56.179] <TB1> INFO: 4746800 events read in total (204285ms).
[17:49:08.752] <TB1> INFO: 5025280 events read in total (216857ms).
[17:49:08.881] <TB1> INFO: Test took 217812ms.
[17:49:32.954] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 2.500000 .. 146.280840
[17:49:33.231] <TB1> INFO: Expecting 208000 events.
[17:49:42.409] <TB1> INFO: 208000 events read in total (8586ms).
[17:49:42.411] <TB1> INFO: Test took 9456ms.
[17:49:42.458] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 2 .. 156 (-1/-1) hits flags = 528 (plus default)
[17:49:42.467] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:49:42.467] <TB1> INFO: run 1 of 1
[17:49:42.745] <TB1> INFO: Expecting 5158400 events.
[17:50:08.845] <TB1> INFO: 584352 events read in total (25508ms).
[17:50:33.914] <TB1> INFO: 1168080 events read in total (50578ms).
[17:50:58.960] <TB1> INFO: 1752120 events read in total (75623ms).
[17:51:23.778] <TB1> INFO: 2336528 events read in total (100442ms).
[17:51:48.788] <TB1> INFO: 2920536 events read in total (125451ms).
[17:52:14.358] <TB1> INFO: 3503952 events read in total (151021ms).
[17:52:39.620] <TB1> INFO: 4087744 events read in total (176283ms).
[17:53:04.869] <TB1> INFO: 4670872 events read in total (201532ms).
[17:53:25.775] <TB1> INFO: 5158400 events read in total (222438ms).
[17:53:25.871] <TB1> INFO: Test took 223404ms.
[17:53:52.923] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 25.826339 .. 46.874307
[17:53:53.171] <TB1> INFO: Expecting 208000 events.
[17:54:03.174] <TB1> INFO: 208000 events read in total (9412ms).
[17:54:03.175] <TB1> INFO: Test took 10251ms.
[17:54:03.223] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 15 .. 56 (-1/-1) hits flags = 528 (plus default)
[17:54:03.234] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:54:03.234] <TB1> INFO: run 1 of 1
[17:54:03.512] <TB1> INFO: Expecting 1397760 events.
[17:54:32.242] <TB1> INFO: 670000 events read in total (28139ms).
[17:54:59.495] <TB1> INFO: 1337488 events read in total (55393ms).
[17:55:02.396] <TB1> INFO: 1397760 events read in total (58293ms).
[17:55:02.424] <TB1> INFO: Test took 59191ms.
[17:55:16.156] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 27.346262 .. 50.649202
[17:55:16.390] <TB1> INFO: Expecting 208000 events.
[17:55:26.070] <TB1> INFO: 208000 events read in total (9088ms).
[17:55:26.070] <TB1> INFO: Test took 9912ms.
[17:55:26.121] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 60 (-1/-1) hits flags = 528 (plus default)
[17:55:26.132] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:55:26.132] <TB1> INFO: run 1 of 1
[17:55:26.410] <TB1> INFO: Expecting 1464320 events.
[17:55:54.294] <TB1> INFO: 645608 events read in total (27292ms).
[17:56:20.983] <TB1> INFO: 1289608 events read in total (53981ms).
[17:56:28.756] <TB1> INFO: 1464320 events read in total (61754ms).
[17:56:28.792] <TB1> INFO: Test took 62661ms.
[17:56:41.387] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 26.077041 .. 53.452638
[17:56:41.621] <TB1> INFO: Expecting 208000 events.
[17:56:51.381] <TB1> INFO: 208000 events read in total (9168ms).
[17:56:51.382] <TB1> INFO: Test took 9994ms.
[17:56:51.448] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 63 (-1/-1) hits flags = 528 (plus default)
[17:56:51.459] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:56:51.459] <TB1> INFO: run 1 of 1
[17:56:51.737] <TB1> INFO: Expecting 1597440 events.
[17:57:19.323] <TB1> INFO: 638504 events read in total (26995ms).
[17:57:45.677] <TB1> INFO: 1276376 events read in total (53350ms).
[17:57:59.526] <TB1> INFO: 1597440 events read in total (67198ms).
[17:57:59.555] <TB1> INFO: Test took 68097ms.
[17:58:13.318] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[17:58:13.318] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[17:58:13.329] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[17:58:13.329] <TB1> INFO: run 1 of 1
[17:58:13.595] <TB1> INFO: Expecting 1364480 events.
[17:58:41.475] <TB1> INFO: 669440 events read in total (27288ms).
[17:59:09.074] <TB1> INFO: 1338232 events read in total (54887ms).
[17:59:10.637] <TB1> INFO: 1364480 events read in total (56450ms).
[17:59:10.663] <TB1> INFO: Test took 57335ms.
[17:59:23.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C0.dat
[17:59:23.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C1.dat
[17:59:23.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C2.dat
[17:59:23.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C3.dat
[17:59:23.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C4.dat
[17:59:23.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C5.dat
[17:59:23.902] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C6.dat
[17:59:23.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C7.dat
[17:59:23.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C8.dat
[17:59:23.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C9.dat
[17:59:23.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C10.dat
[17:59:23.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C11.dat
[17:59:23.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C12.dat
[17:59:23.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C13.dat
[17:59:23.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C14.dat
[17:59:23.903] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C15.dat
[17:59:23.903] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters35_C0.dat
[17:59:23.909] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters35_C1.dat
[17:59:23.915] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters35_C2.dat
[17:59:23.921] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters35_C3.dat
[17:59:23.928] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters35_C4.dat
[17:59:23.936] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters35_C5.dat
[17:59:23.943] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters35_C6.dat
[17:59:23.951] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters35_C7.dat
[17:59:23.958] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters35_C8.dat
[17:59:23.964] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters35_C9.dat
[17:59:23.970] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters35_C10.dat
[17:59:23.975] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters35_C11.dat
[17:59:23.981] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters35_C12.dat
[17:59:23.987] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters35_C13.dat
[17:59:23.993] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters35_C14.dat
[17:59:23.999] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters35_C15.dat
[17:59:24.004] <TB1> INFO: PixTestTrim::trimTest() done
[17:59:24.004] <TB1> INFO: vtrim: 145 198 186 144 136 131 184 125 187 181 182 173 195 144 164 158
[17:59:24.004] <TB1> INFO: vthrcomp: 128 136 137 127 114 132 134 119 134 133 133 132 136 129 129 136
[17:59:24.004] <TB1> INFO: vcal mean: 35.21 35.52 35.09 35.21 35.05 35.20 35.29 35.15 35.32 35.60 35.70 36.28 35.39 35.38 35.62 35.06
[17:59:24.004] <TB1> INFO: vcal RMS: 1.36 1.67 1.20 1.45 0.99 1.28 1.39 1.38 1.48 1.80 1.88 2.55 1.63 1.66 1.81 1.12
[17:59:24.004] <TB1> INFO: bits mean: 9.82 8.72 8.45 9.86 9.23 9.28 8.62 9.51 8.72 9.59 9.51 9.28 9.38 9.61 9.80 8.30
[17:59:24.004] <TB1> INFO: bits RMS: 2.52 2.21 2.12 2.66 2.65 2.54 2.06 2.79 2.25 2.36 2.20 2.55 1.84 2.65 2.48 2.52
[17:59:24.012] <TB1> INFO: ----------------------------------------------------------------------
[17:59:24.012] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[17:59:24.012] <TB1> INFO: ----------------------------------------------------------------------
[17:59:24.014] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[17:59:24.025] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[17:59:24.025] <TB1> INFO: run 1 of 1
[17:59:24.260] <TB1> INFO: Expecting 4160000 events.
[17:59:57.027] <TB1> INFO: 791590 events read in total (32176ms).
[18:00:29.164] <TB1> INFO: 1576420 events read in total (64313ms).
[18:01:00.871] <TB1> INFO: 2355270 events read in total (96020ms).
[18:01:32.779] <TB1> INFO: 3130355 events read in total (127928ms).
[18:02:04.447] <TB1> INFO: 3904505 events read in total (159596ms).
[18:02:15.426] <TB1> INFO: 4160000 events read in total (170575ms).
[18:02:15.475] <TB1> INFO: Test took 171450ms.
[18:02:41.242] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 223 (-1/-1) hits flags = 528 (plus default)
[18:02:41.255] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[18:02:41.255] <TB1> INFO: run 1 of 1
[18:02:41.509] <TB1> INFO: Expecting 4659200 events.
[18:03:13.359] <TB1> INFO: 728950 events read in total (31259ms).
[18:03:44.197] <TB1> INFO: 1453575 events read in total (62097ms).
[18:04:14.544] <TB1> INFO: 2174855 events read in total (92444ms).
[18:04:44.952] <TB1> INFO: 2891785 events read in total (122852ms).
[18:05:15.225] <TB1> INFO: 3607985 events read in total (153125ms).
[18:05:45.498] <TB1> INFO: 4324215 events read in total (183398ms).
[18:06:00.087] <TB1> INFO: 4659200 events read in total (197987ms).
[18:06:00.163] <TB1> INFO: Test took 198908ms.
[18:06:30.704] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 213 (-1/-1) hits flags = 528 (plus default)
[18:06:30.714] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[18:06:30.714] <TB1> INFO: run 1 of 1
[18:06:30.999] <TB1> INFO: Expecting 4451200 events.
[18:07:02.510] <TB1> INFO: 741940 events read in total (30920ms).
[18:07:34.135] <TB1> INFO: 1479465 events read in total (62545ms).
[18:08:04.875] <TB1> INFO: 2212550 events read in total (93285ms).
[18:08:35.727] <TB1> INFO: 2941505 events read in total (124137ms).
[18:09:06.441] <TB1> INFO: 3669385 events read in total (154851ms).
[18:09:37.478] <TB1> INFO: 4399315 events read in total (185888ms).
[18:09:40.049] <TB1> INFO: 4451200 events read in total (188459ms).
[18:09:40.108] <TB1> INFO: Test took 189394ms.
[18:10:09.956] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 216 (-1/-1) hits flags = 528 (plus default)
[18:10:09.968] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[18:10:09.968] <TB1> INFO: run 1 of 1
[18:10:10.200] <TB1> INFO: Expecting 4513600 events.
[18:10:42.382] <TB1> INFO: 738265 events read in total (31590ms).
[18:11:14.067] <TB1> INFO: 1471845 events read in total (63275ms).
[18:11:44.803] <TB1> INFO: 2201290 events read in total (94011ms).
[18:12:15.559] <TB1> INFO: 2926540 events read in total (124767ms).
[18:12:46.170] <TB1> INFO: 3651135 events read in total (155378ms).
[18:13:17.020] <TB1> INFO: 4375990 events read in total (186228ms).
[18:13:23.173] <TB1> INFO: 4513600 events read in total (192381ms).
[18:13:23.229] <TB1> INFO: Test took 193261ms.
[18:13:51.050] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[18:13:51.062] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[18:13:51.062] <TB1> INFO: run 1 of 1
[18:13:51.335] <TB1> INFO: Expecting 4472000 events.
[18:14:22.858] <TB1> INFO: 740765 events read in total (30931ms).
[18:14:53.628] <TB1> INFO: 1476990 events read in total (61701ms).
[18:15:24.529] <TB1> INFO: 2208980 events read in total (92602ms).
[18:15:55.421] <TB1> INFO: 2936865 events read in total (123494ms).
[18:16:26.454] <TB1> INFO: 3663565 events read in total (154527ms).
[18:16:57.631] <TB1> INFO: 4391610 events read in total (185704ms).
[18:17:01.471] <TB1> INFO: 4472000 events read in total (189544ms).
[18:17:01.539] <TB1> INFO: Test took 190477ms.
[18:17:29.992] <TB1> INFO: PixTestTrim::trimBitTest() done
[18:17:29.993] <TB1> INFO: PixTestTrim::doTest() done, duration: 2506 seconds
[18:17:29.993] <TB1> INFO: Decoding statistics:
[18:17:29.993] <TB1> INFO: General information:
[18:17:29.993] <TB1> INFO: 16bit words read: 0
[18:17:29.993] <TB1> INFO: valid events total: 0
[18:17:29.993] <TB1> INFO: empty events: 0
[18:17:29.993] <TB1> INFO: valid events with pixels: 0
[18:17:29.993] <TB1> INFO: valid pixel hits: 0
[18:17:29.993] <TB1> INFO: Event errors: 0
[18:17:29.993] <TB1> INFO: start marker: 0
[18:17:29.993] <TB1> INFO: stop marker: 0
[18:17:29.993] <TB1> INFO: overflow: 0
[18:17:29.993] <TB1> INFO: invalid 5bit words: 0
[18:17:29.993] <TB1> INFO: invalid XOR eye diagram: 0
[18:17:29.993] <TB1> INFO: frame (failed synchr.): 0
[18:17:29.993] <TB1> INFO: idle data (no TBM trl): 0
[18:17:29.993] <TB1> INFO: no data (only TBM hdr): 0
[18:17:29.993] <TB1> INFO: TBM errors: 0
[18:17:29.993] <TB1> INFO: flawed TBM headers: 0
[18:17:29.993] <TB1> INFO: flawed TBM trailers: 0
[18:17:29.993] <TB1> INFO: event ID mismatches: 0
[18:17:29.993] <TB1> INFO: ROC errors: 0
[18:17:29.993] <TB1> INFO: missing ROC header(s): 0
[18:17:29.993] <TB1> INFO: misplaced readback start: 0
[18:17:29.993] <TB1> INFO: Pixel decoding errors: 0
[18:17:29.993] <TB1> INFO: pixel data incomplete: 0
[18:17:29.993] <TB1> INFO: pixel address: 0
[18:17:29.993] <TB1> INFO: pulse height fill bit: 0
[18:17:29.993] <TB1> INFO: buffer corruption: 0
[18:17:30.723] <TB1> INFO: ######################################################################
[18:17:30.723] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[18:17:30.723] <TB1> INFO: ######################################################################
[18:17:30.960] <TB1> INFO: Expecting 41600 events.
[18:17:34.367] <TB1> INFO: 41600 events read in total (2815ms).
[18:17:34.367] <TB1> INFO: Test took 3642ms.
[18:17:34.818] <TB1> INFO: Expecting 41600 events.
[18:17:38.320] <TB1> INFO: 41600 events read in total (2911ms).
[18:17:38.321] <TB1> INFO: Test took 3749ms.
[18:17:38.609] <TB1> INFO: Expecting 41600 events.
[18:17:42.112] <TB1> INFO: 41600 events read in total (2911ms).
[18:17:42.112] <TB1> INFO: Test took 3769ms.
[18:17:42.401] <TB1> INFO: Expecting 41600 events.
[18:17:45.920] <TB1> INFO: 41600 events read in total (2928ms).
[18:17:45.921] <TB1> INFO: Test took 3785ms.
[18:17:46.230] <TB1> INFO: Expecting 41600 events.
[18:17:49.736] <TB1> INFO: 41600 events read in total (2914ms).
[18:17:49.737] <TB1> INFO: Test took 3792ms.
[18:17:50.025] <TB1> INFO: Expecting 41600 events.
[18:17:53.460] <TB1> INFO: 41600 events read in total (2843ms).
[18:17:53.461] <TB1> INFO: Test took 3700ms.
[18:17:53.749] <TB1> INFO: Expecting 41600 events.
[18:17:57.298] <TB1> INFO: 41600 events read in total (2958ms).
[18:17:57.299] <TB1> INFO: Test took 3815ms.
[18:17:57.631] <TB1> INFO: Expecting 41600 events.
[18:18:01.156] <TB1> INFO: 41600 events read in total (2933ms).
[18:18:01.157] <TB1> INFO: Test took 3830ms.
[18:18:01.457] <TB1> INFO: Expecting 41600 events.
[18:18:04.984] <TB1> INFO: 41600 events read in total (2935ms).
[18:18:04.985] <TB1> INFO: Test took 3805ms.
[18:18:05.279] <TB1> INFO: Expecting 41600 events.
[18:18:08.826] <TB1> INFO: 41600 events read in total (2945ms).
[18:18:08.826] <TB1> INFO: Test took 3816ms.
[18:18:09.163] <TB1> INFO: Expecting 41600 events.
[18:18:12.654] <TB1> INFO: 41600 events read in total (2899ms).
[18:18:12.654] <TB1> INFO: Test took 3804ms.
[18:18:12.945] <TB1> INFO: Expecting 41600 events.
[18:18:16.478] <TB1> INFO: 41600 events read in total (2941ms).
[18:18:16.478] <TB1> INFO: Test took 3798ms.
[18:18:16.775] <TB1> INFO: Expecting 41600 events.
[18:18:20.226] <TB1> INFO: 41600 events read in total (2860ms).
[18:18:20.227] <TB1> INFO: Test took 3725ms.
[18:18:20.517] <TB1> INFO: Expecting 41600 events.
[18:18:24.055] <TB1> INFO: 41600 events read in total (2947ms).
[18:18:24.056] <TB1> INFO: Test took 3804ms.
[18:18:24.344] <TB1> INFO: Expecting 41600 events.
[18:18:27.798] <TB1> INFO: 41600 events read in total (2862ms).
[18:18:27.799] <TB1> INFO: Test took 3719ms.
[18:18:28.087] <TB1> INFO: Expecting 41600 events.
[18:18:31.548] <TB1> INFO: 41600 events read in total (2869ms).
[18:18:31.549] <TB1> INFO: Test took 3727ms.
[18:18:31.844] <TB1> INFO: Expecting 41600 events.
[18:18:35.318] <TB1> INFO: 41600 events read in total (2882ms).
[18:18:35.319] <TB1> INFO: Test took 3746ms.
[18:18:35.607] <TB1> INFO: Expecting 41600 events.
[18:18:39.148] <TB1> INFO: 41600 events read in total (2949ms).
[18:18:39.149] <TB1> INFO: Test took 3807ms.
[18:18:39.441] <TB1> INFO: Expecting 41600 events.
[18:18:42.904] <TB1> INFO: 41600 events read in total (2871ms).
[18:18:42.904] <TB1> INFO: Test took 3732ms.
[18:18:43.194] <TB1> INFO: Expecting 41600 events.
[18:18:46.807] <TB1> INFO: 41600 events read in total (3021ms).
[18:18:46.808] <TB1> INFO: Test took 3879ms.
[18:18:47.103] <TB1> INFO: Expecting 41600 events.
[18:18:50.570] <TB1> INFO: 41600 events read in total (2875ms).
[18:18:50.571] <TB1> INFO: Test took 3739ms.
[18:18:50.867] <TB1> INFO: Expecting 41600 events.
[18:18:54.358] <TB1> INFO: 41600 events read in total (2899ms).
[18:18:54.358] <TB1> INFO: Test took 3765ms.
[18:18:54.666] <TB1> INFO: Expecting 41600 events.
[18:18:58.208] <TB1> INFO: 41600 events read in total (2951ms).
[18:18:58.209] <TB1> INFO: Test took 3827ms.
[18:18:58.497] <TB1> INFO: Expecting 41600 events.
[18:19:02.010] <TB1> INFO: 41600 events read in total (2921ms).
[18:19:02.011] <TB1> INFO: Test took 3778ms.
[18:19:02.300] <TB1> INFO: Expecting 41600 events.
[18:19:05.866] <TB1> INFO: 41600 events read in total (2975ms).
[18:19:05.867] <TB1> INFO: Test took 3832ms.
[18:19:06.155] <TB1> INFO: Expecting 41600 events.
[18:19:09.640] <TB1> INFO: 41600 events read in total (2893ms).
[18:19:09.641] <TB1> INFO: Test took 3750ms.
[18:19:09.930] <TB1> INFO: Expecting 41600 events.
[18:19:13.353] <TB1> INFO: 41600 events read in total (2832ms).
[18:19:13.354] <TB1> INFO: Test took 3689ms.
[18:19:13.642] <TB1> INFO: Expecting 41600 events.
[18:19:17.227] <TB1> INFO: 41600 events read in total (2993ms).
[18:19:17.228] <TB1> INFO: Test took 3851ms.
[18:19:17.516] <TB1> INFO: Expecting 41600 events.
[18:19:21.023] <TB1> INFO: 41600 events read in total (2915ms).
[18:19:21.023] <TB1> INFO: Test took 3772ms.
[18:19:21.312] <TB1> INFO: Expecting 41600 events.
[18:19:24.876] <TB1> INFO: 41600 events read in total (2972ms).
[18:19:24.877] <TB1> INFO: Test took 3830ms.
[18:19:25.167] <TB1> INFO: Expecting 41600 events.
[18:19:28.680] <TB1> INFO: 41600 events read in total (2922ms).
[18:19:28.680] <TB1> INFO: Test took 3778ms.
[18:19:28.969] <TB1> INFO: Expecting 2560 events.
[18:19:29.852] <TB1> INFO: 2560 events read in total (291ms).
[18:19:29.852] <TB1> INFO: Test took 1160ms.
[18:19:30.160] <TB1> INFO: Expecting 2560 events.
[18:19:31.045] <TB1> INFO: 2560 events read in total (293ms).
[18:19:31.045] <TB1> INFO: Test took 1192ms.
[18:19:31.353] <TB1> INFO: Expecting 2560 events.
[18:19:32.236] <TB1> INFO: 2560 events read in total (291ms).
[18:19:32.236] <TB1> INFO: Test took 1190ms.
[18:19:32.544] <TB1> INFO: Expecting 2560 events.
[18:19:33.426] <TB1> INFO: 2560 events read in total (291ms).
[18:19:33.426] <TB1> INFO: Test took 1189ms.
[18:19:33.734] <TB1> INFO: Expecting 2560 events.
[18:19:34.612] <TB1> INFO: 2560 events read in total (287ms).
[18:19:34.612] <TB1> INFO: Test took 1186ms.
[18:19:34.920] <TB1> INFO: Expecting 2560 events.
[18:19:35.798] <TB1> INFO: 2560 events read in total (286ms).
[18:19:35.799] <TB1> INFO: Test took 1186ms.
[18:19:36.107] <TB1> INFO: Expecting 2560 events.
[18:19:36.985] <TB1> INFO: 2560 events read in total (287ms).
[18:19:36.985] <TB1> INFO: Test took 1186ms.
[18:19:37.292] <TB1> INFO: Expecting 2560 events.
[18:19:38.172] <TB1> INFO: 2560 events read in total (288ms).
[18:19:38.172] <TB1> INFO: Test took 1187ms.
[18:19:38.480] <TB1> INFO: Expecting 2560 events.
[18:19:39.361] <TB1> INFO: 2560 events read in total (290ms).
[18:19:39.361] <TB1> INFO: Test took 1188ms.
[18:19:39.669] <TB1> INFO: Expecting 2560 events.
[18:19:40.546] <TB1> INFO: 2560 events read in total (286ms).
[18:19:40.546] <TB1> INFO: Test took 1184ms.
[18:19:40.855] <TB1> INFO: Expecting 2560 events.
[18:19:41.733] <TB1> INFO: 2560 events read in total (287ms).
[18:19:41.733] <TB1> INFO: Test took 1186ms.
[18:19:42.042] <TB1> INFO: Expecting 2560 events.
[18:19:42.920] <TB1> INFO: 2560 events read in total (287ms).
[18:19:42.921] <TB1> INFO: Test took 1187ms.
[18:19:43.228] <TB1> INFO: Expecting 2560 events.
[18:19:44.111] <TB1> INFO: 2560 events read in total (291ms).
[18:19:44.111] <TB1> INFO: Test took 1190ms.
[18:19:44.419] <TB1> INFO: Expecting 2560 events.
[18:19:45.303] <TB1> INFO: 2560 events read in total (292ms).
[18:19:45.303] <TB1> INFO: Test took 1191ms.
[18:19:45.611] <TB1> INFO: Expecting 2560 events.
[18:19:46.494] <TB1> INFO: 2560 events read in total (292ms).
[18:19:46.494] <TB1> INFO: Test took 1191ms.
[18:19:46.802] <TB1> INFO: Expecting 2560 events.
[18:19:47.685] <TB1> INFO: 2560 events read in total (291ms).
[18:19:47.685] <TB1> INFO: Test took 1191ms.
[18:19:47.688] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:19:47.994] <TB1> INFO: Expecting 655360 events.
[18:20:02.328] <TB1> INFO: 655360 events read in total (13743ms).
[18:20:02.342] <TB1> INFO: Expecting 655360 events.
[18:20:16.407] <TB1> INFO: 655360 events read in total (13662ms).
[18:20:16.422] <TB1> INFO: Expecting 655360 events.
[18:20:30.691] <TB1> INFO: 655360 events read in total (13866ms).
[18:20:30.716] <TB1> INFO: Expecting 655360 events.
[18:20:45.035] <TB1> INFO: 655360 events read in total (13916ms).
[18:20:45.065] <TB1> INFO: Expecting 655360 events.
[18:20:59.301] <TB1> INFO: 655360 events read in total (13833ms).
[18:20:59.339] <TB1> INFO: Expecting 655360 events.
[18:21:13.394] <TB1> INFO: 655360 events read in total (13652ms).
[18:21:13.425] <TB1> INFO: Expecting 655360 events.
[18:21:27.423] <TB1> INFO: 655360 events read in total (13595ms).
[18:21:27.457] <TB1> INFO: Expecting 655360 events.
[18:21:41.526] <TB1> INFO: 655360 events read in total (13666ms).
[18:21:41.566] <TB1> INFO: Expecting 655360 events.
[18:21:55.684] <TB1> INFO: 655360 events read in total (13715ms).
[18:21:55.728] <TB1> INFO: Expecting 655360 events.
[18:22:09.822] <TB1> INFO: 655360 events read in total (13691ms).
[18:22:09.877] <TB1> INFO: Expecting 655360 events.
[18:22:23.915] <TB1> INFO: 655360 events read in total (13635ms).
[18:22:23.964] <TB1> INFO: Expecting 655360 events.
[18:22:38.064] <TB1> INFO: 655360 events read in total (13697ms).
[18:22:38.142] <TB1> INFO: Expecting 655360 events.
[18:22:52.288] <TB1> INFO: 655360 events read in total (13743ms).
[18:22:52.371] <TB1> INFO: Expecting 655360 events.
[18:23:06.463] <TB1> INFO: 655360 events read in total (13689ms).
[18:23:06.528] <TB1> INFO: Expecting 655360 events.
[18:23:20.589] <TB1> INFO: 655360 events read in total (13658ms).
[18:23:20.686] <TB1> INFO: Expecting 655360 events.
[18:23:34.715] <TB1> INFO: 655360 events read in total (13627ms).
[18:23:34.789] <TB1> INFO: Test took 227101ms.
[18:23:34.867] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:23:35.131] <TB1> INFO: Expecting 655360 events.
[18:23:49.331] <TB1> INFO: 655360 events read in total (13608ms).
[18:23:49.346] <TB1> INFO: Expecting 655360 events.
[18:24:03.171] <TB1> INFO: 655360 events read in total (13422ms).
[18:24:03.184] <TB1> INFO: Expecting 655360 events.
[18:24:17.145] <TB1> INFO: 655360 events read in total (13558ms).
[18:24:17.164] <TB1> INFO: Expecting 655360 events.
[18:24:31.196] <TB1> INFO: 655360 events read in total (13629ms).
[18:24:31.225] <TB1> INFO: Expecting 655360 events.
[18:24:45.159] <TB1> INFO: 655360 events read in total (13531ms).
[18:24:45.197] <TB1> INFO: Expecting 655360 events.
[18:24:59.267] <TB1> INFO: 655360 events read in total (13667ms).
[18:24:59.309] <TB1> INFO: Expecting 655360 events.
[18:25:13.287] <TB1> INFO: 655360 events read in total (13575ms).
[18:25:13.321] <TB1> INFO: Expecting 655360 events.
[18:25:27.166] <TB1> INFO: 655360 events read in total (13442ms).
[18:25:27.205] <TB1> INFO: Expecting 655360 events.
[18:25:41.281] <TB1> INFO: 655360 events read in total (13673ms).
[18:25:41.325] <TB1> INFO: Expecting 655360 events.
[18:25:55.108] <TB1> INFO: 655360 events read in total (13380ms).
[18:25:55.157] <TB1> INFO: Expecting 655360 events.
[18:26:09.066] <TB1> INFO: 655360 events read in total (13506ms).
[18:26:09.118] <TB1> INFO: Expecting 655360 events.
[18:26:23.080] <TB1> INFO: 655360 events read in total (13559ms).
[18:26:23.136] <TB1> INFO: Expecting 655360 events.
[18:26:37.170] <TB1> INFO: 655360 events read in total (13631ms).
[18:26:37.233] <TB1> INFO: Expecting 655360 events.
[18:26:50.961] <TB1> INFO: 655360 events read in total (13325ms).
[18:26:51.048] <TB1> INFO: Expecting 655360 events.
[18:27:04.854] <TB1> INFO: 655360 events read in total (13403ms).
[18:27:04.922] <TB1> INFO: Expecting 655360 events.
[18:27:19.018] <TB1> INFO: 655360 events read in total (13693ms).
[18:27:19.092] <TB1> INFO: Test took 224226ms.
[18:27:19.248] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[18:27:19.253] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[18:27:19.257] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[18:27:19.262] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[18:27:19.266] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[18:27:19.271] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[18:27:19.276] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[18:27:19.280] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[18:27:19.285] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[18:27:19.290] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[18:27:19.294] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[18:27:19.299] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[18:27:19.304] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[18:27:19.308] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[18:27:19.313] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[18:27:19.318] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[18:27:19.323] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[18:27:19.327] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[18:27:19.332] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[18:27:19.337] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[18:27:19.341] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[18:27:19.346] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[18:27:19.350] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[18:27:19.355] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[18:27:19.360] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[18:27:19.364] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[18:27:19.369] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[18:27:19.401] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C0.dat
[18:27:19.402] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C1.dat
[18:27:19.402] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C2.dat
[18:27:19.402] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C3.dat
[18:27:19.402] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C4.dat
[18:27:19.402] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C5.dat
[18:27:19.402] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C6.dat
[18:27:19.402] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C7.dat
[18:27:19.402] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C8.dat
[18:27:19.402] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C9.dat
[18:27:19.403] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C10.dat
[18:27:19.403] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C11.dat
[18:27:19.403] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C12.dat
[18:27:19.403] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C13.dat
[18:27:19.403] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C14.dat
[18:27:19.403] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters35_C15.dat
[18:27:19.638] <TB1> INFO: Expecting 41600 events.
[18:27:22.722] <TB1> INFO: 41600 events read in total (2493ms).
[18:27:22.722] <TB1> INFO: Test took 3316ms.
[18:27:23.184] <TB1> INFO: Expecting 41600 events.
[18:27:26.159] <TB1> INFO: 41600 events read in total (2383ms).
[18:27:26.160] <TB1> INFO: Test took 3226ms.
[18:27:26.602] <TB1> INFO: Expecting 41600 events.
[18:27:29.724] <TB1> INFO: 41600 events read in total (2531ms).
[18:27:29.724] <TB1> INFO: Test took 3354ms.
[18:27:29.940] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:30.028] <TB1> INFO: Expecting 2560 events.
[18:27:30.915] <TB1> INFO: 2560 events read in total (295ms).
[18:27:30.915] <TB1> INFO: Test took 975ms.
[18:27:30.917] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:31.223] <TB1> INFO: Expecting 2560 events.
[18:27:32.109] <TB1> INFO: 2560 events read in total (294ms).
[18:27:32.109] <TB1> INFO: Test took 1192ms.
[18:27:32.111] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:32.418] <TB1> INFO: Expecting 2560 events.
[18:27:33.301] <TB1> INFO: 2560 events read in total (292ms).
[18:27:33.301] <TB1> INFO: Test took 1190ms.
[18:27:33.303] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:33.609] <TB1> INFO: Expecting 2560 events.
[18:27:34.493] <TB1> INFO: 2560 events read in total (292ms).
[18:27:34.493] <TB1> INFO: Test took 1190ms.
[18:27:34.495] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:34.802] <TB1> INFO: Expecting 2560 events.
[18:27:35.685] <TB1> INFO: 2560 events read in total (292ms).
[18:27:35.685] <TB1> INFO: Test took 1190ms.
[18:27:35.687] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:35.994] <TB1> INFO: Expecting 2560 events.
[18:27:36.878] <TB1> INFO: 2560 events read in total (293ms).
[18:27:36.879] <TB1> INFO: Test took 1192ms.
[18:27:36.880] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:37.187] <TB1> INFO: Expecting 2560 events.
[18:27:38.070] <TB1> INFO: 2560 events read in total (291ms).
[18:27:38.070] <TB1> INFO: Test took 1190ms.
[18:27:38.072] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:38.378] <TB1> INFO: Expecting 2560 events.
[18:27:39.260] <TB1> INFO: 2560 events read in total (290ms).
[18:27:39.260] <TB1> INFO: Test took 1188ms.
[18:27:39.262] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:39.569] <TB1> INFO: Expecting 2560 events.
[18:27:40.448] <TB1> INFO: 2560 events read in total (288ms).
[18:27:40.449] <TB1> INFO: Test took 1187ms.
[18:27:40.451] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:40.757] <TB1> INFO: Expecting 2560 events.
[18:27:41.636] <TB1> INFO: 2560 events read in total (288ms).
[18:27:41.636] <TB1> INFO: Test took 1185ms.
[18:27:41.638] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:41.944] <TB1> INFO: Expecting 2560 events.
[18:27:42.826] <TB1> INFO: 2560 events read in total (290ms).
[18:27:42.827] <TB1> INFO: Test took 1189ms.
[18:27:42.828] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:43.135] <TB1> INFO: Expecting 2560 events.
[18:27:44.014] <TB1> INFO: 2560 events read in total (287ms).
[18:27:44.014] <TB1> INFO: Test took 1186ms.
[18:27:44.016] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:44.323] <TB1> INFO: Expecting 2560 events.
[18:27:45.203] <TB1> INFO: 2560 events read in total (289ms).
[18:27:45.203] <TB1> INFO: Test took 1187ms.
[18:27:45.205] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:45.511] <TB1> INFO: Expecting 2560 events.
[18:27:46.392] <TB1> INFO: 2560 events read in total (289ms).
[18:27:46.393] <TB1> INFO: Test took 1189ms.
[18:27:46.395] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:46.701] <TB1> INFO: Expecting 2560 events.
[18:27:47.580] <TB1> INFO: 2560 events read in total (287ms).
[18:27:47.580] <TB1> INFO: Test took 1186ms.
[18:27:47.582] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:47.889] <TB1> INFO: Expecting 2560 events.
[18:27:48.768] <TB1> INFO: 2560 events read in total (288ms).
[18:27:48.768] <TB1> INFO: Test took 1186ms.
[18:27:48.770] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:49.076] <TB1> INFO: Expecting 2560 events.
[18:27:49.959] <TB1> INFO: 2560 events read in total (291ms).
[18:27:49.959] <TB1> INFO: Test took 1189ms.
[18:27:49.961] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:50.267] <TB1> INFO: Expecting 2560 events.
[18:27:51.145] <TB1> INFO: 2560 events read in total (287ms).
[18:27:51.145] <TB1> INFO: Test took 1184ms.
[18:27:51.147] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:51.453] <TB1> INFO: Expecting 2560 events.
[18:27:52.335] <TB1> INFO: 2560 events read in total (290ms).
[18:27:52.335] <TB1> INFO: Test took 1189ms.
[18:27:52.337] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:52.643] <TB1> INFO: Expecting 2560 events.
[18:27:53.523] <TB1> INFO: 2560 events read in total (288ms).
[18:27:53.523] <TB1> INFO: Test took 1186ms.
[18:27:53.524] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:53.831] <TB1> INFO: Expecting 2560 events.
[18:27:54.710] <TB1> INFO: 2560 events read in total (287ms).
[18:27:54.710] <TB1> INFO: Test took 1186ms.
[18:27:54.712] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:55.018] <TB1> INFO: Expecting 2560 events.
[18:27:55.899] <TB1> INFO: 2560 events read in total (289ms).
[18:27:55.900] <TB1> INFO: Test took 1188ms.
[18:27:55.901] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:56.208] <TB1> INFO: Expecting 2560 events.
[18:27:57.089] <TB1> INFO: 2560 events read in total (289ms).
[18:27:57.089] <TB1> INFO: Test took 1188ms.
[18:27:57.091] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:57.398] <TB1> INFO: Expecting 2560 events.
[18:27:58.276] <TB1> INFO: 2560 events read in total (287ms).
[18:27:58.276] <TB1> INFO: Test took 1185ms.
[18:27:58.278] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:58.585] <TB1> INFO: Expecting 2560 events.
[18:27:59.468] <TB1> INFO: 2560 events read in total (292ms).
[18:27:59.468] <TB1> INFO: Test took 1190ms.
[18:27:59.470] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:27:59.776] <TB1> INFO: Expecting 2560 events.
[18:28:00.659] <TB1> INFO: 2560 events read in total (291ms).
[18:28:00.660] <TB1> INFO: Test took 1190ms.
[18:28:00.662] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:28:00.968] <TB1> INFO: Expecting 2560 events.
[18:28:01.850] <TB1> INFO: 2560 events read in total (290ms).
[18:28:01.851] <TB1> INFO: Test took 1189ms.
[18:28:01.852] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:28:02.159] <TB1> INFO: Expecting 2560 events.
[18:28:03.041] <TB1> INFO: 2560 events read in total (291ms).
[18:28:03.041] <TB1> INFO: Test took 1189ms.
[18:28:03.043] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:28:03.350] <TB1> INFO: Expecting 2560 events.
[18:28:04.235] <TB1> INFO: 2560 events read in total (294ms).
[18:28:04.235] <TB1> INFO: Test took 1192ms.
[18:28:04.237] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:28:04.544] <TB1> INFO: Expecting 2560 events.
[18:28:05.429] <TB1> INFO: 2560 events read in total (294ms).
[18:28:05.429] <TB1> INFO: Test took 1192ms.
[18:28:05.431] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:28:05.736] <TB1> INFO: Expecting 2560 events.
[18:28:06.619] <TB1> INFO: 2560 events read in total (291ms).
[18:28:06.619] <TB1> INFO: Test took 1188ms.
[18:28:06.622] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:28:06.928] <TB1> INFO: Expecting 2560 events.
[18:28:07.811] <TB1> INFO: 2560 events read in total (292ms).
[18:28:07.811] <TB1> INFO: Test took 1190ms.
[18:28:08.277] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 637 seconds
[18:28:08.277] <TB1> INFO: PH scale (per ROC): 41 37 52 49 37 42 36 43 48 29 45 44 43 44 51 55
[18:28:08.277] <TB1> INFO: PH offset (per ROC): 99 109 124 106 94 107 74 131 109 94 87 105 111 105 126 125
[18:28:08.283] <TB1> INFO: Decoding statistics:
[18:28:08.283] <TB1> INFO: General information:
[18:28:08.283] <TB1> INFO: 16bit words read: 127880
[18:28:08.283] <TB1> INFO: valid events total: 20480
[18:28:08.283] <TB1> INFO: empty events: 17980
[18:28:08.283] <TB1> INFO: valid events with pixels: 2500
[18:28:08.283] <TB1> INFO: valid pixel hits: 2500
[18:28:08.283] <TB1> INFO: Event errors: 0
[18:28:08.283] <TB1> INFO: start marker: 0
[18:28:08.283] <TB1> INFO: stop marker: 0
[18:28:08.283] <TB1> INFO: overflow: 0
[18:28:08.283] <TB1> INFO: invalid 5bit words: 0
[18:28:08.283] <TB1> INFO: invalid XOR eye diagram: 0
[18:28:08.283] <TB1> INFO: frame (failed synchr.): 0
[18:28:08.283] <TB1> INFO: idle data (no TBM trl): 0
[18:28:08.283] <TB1> INFO: no data (only TBM hdr): 0
[18:28:08.283] <TB1> INFO: TBM errors: 0
[18:28:08.283] <TB1> INFO: flawed TBM headers: 0
[18:28:08.283] <TB1> INFO: flawed TBM trailers: 0
[18:28:08.283] <TB1> INFO: event ID mismatches: 0
[18:28:08.283] <TB1> INFO: ROC errors: 0
[18:28:08.283] <TB1> INFO: missing ROC header(s): 0
[18:28:08.283] <TB1> INFO: misplaced readback start: 0
[18:28:08.283] <TB1> INFO: Pixel decoding errors: 0
[18:28:08.283] <TB1> INFO: pixel data incomplete: 0
[18:28:08.283] <TB1> INFO: pixel address: 0
[18:28:08.283] <TB1> INFO: pulse height fill bit: 0
[18:28:08.283] <TB1> INFO: buffer corruption: 0
[18:28:08.584] <TB1> INFO: ######################################################################
[18:28:08.584] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[18:28:08.584] <TB1> INFO: ######################################################################
[18:28:08.593] <TB1> INFO: scanning low vcal = 10
[18:28:08.870] <TB1> INFO: Expecting 41600 events.
[18:28:12.424] <TB1> INFO: 41600 events read in total (2962ms).
[18:28:12.424] <TB1> INFO: Test took 3831ms.
[18:28:12.425] <TB1> INFO: scanning low vcal = 20
[18:28:12.725] <TB1> INFO: Expecting 41600 events.
[18:28:16.271] <TB1> INFO: 41600 events read in total (2954ms).
[18:28:16.272] <TB1> INFO: Test took 3846ms.
[18:28:16.273] <TB1> INFO: scanning low vcal = 30
[18:28:16.572] <TB1> INFO: Expecting 41600 events.
[18:28:20.195] <TB1> INFO: 41600 events read in total (3031ms).
[18:28:20.196] <TB1> INFO: Test took 3922ms.
[18:28:20.198] <TB1> INFO: scanning low vcal = 40
[18:28:20.476] <TB1> INFO: Expecting 41600 events.
[18:28:24.371] <TB1> INFO: 41600 events read in total (3303ms).
[18:28:24.372] <TB1> INFO: Test took 4174ms.
[18:28:24.375] <TB1> INFO: scanning low vcal = 50
[18:28:24.651] <TB1> INFO: Expecting 41600 events.
[18:28:28.586] <TB1> INFO: 41600 events read in total (3343ms).
[18:28:28.586] <TB1> INFO: Test took 4211ms.
[18:28:28.589] <TB1> INFO: scanning low vcal = 60
[18:28:28.866] <TB1> INFO: Expecting 41600 events.
[18:28:32.823] <TB1> INFO: 41600 events read in total (3366ms).
[18:28:32.824] <TB1> INFO: Test took 4235ms.
[18:28:32.827] <TB1> INFO: scanning low vcal = 70
[18:28:33.103] <TB1> INFO: Expecting 41600 events.
[18:28:37.069] <TB1> INFO: 41600 events read in total (3374ms).
[18:28:37.069] <TB1> INFO: Test took 4243ms.
[18:28:37.072] <TB1> INFO: scanning low vcal = 80
[18:28:37.349] <TB1> INFO: Expecting 41600 events.
[18:28:41.293] <TB1> INFO: 41600 events read in total (3353ms).
[18:28:41.294] <TB1> INFO: Test took 4222ms.
[18:28:41.296] <TB1> INFO: scanning low vcal = 90
[18:28:41.573] <TB1> INFO: Expecting 41600 events.
[18:28:45.532] <TB1> INFO: 41600 events read in total (3368ms).
[18:28:45.533] <TB1> INFO: Test took 4237ms.
[18:28:45.536] <TB1> INFO: scanning low vcal = 100
[18:28:45.812] <TB1> INFO: Expecting 41600 events.
[18:28:49.739] <TB1> INFO: 41600 events read in total (3335ms).
[18:28:49.740] <TB1> INFO: Test took 4204ms.
[18:28:49.742] <TB1> INFO: scanning low vcal = 110
[18:28:50.019] <TB1> INFO: Expecting 41600 events.
[18:28:53.988] <TB1> INFO: 41600 events read in total (3377ms).
[18:28:53.989] <TB1> INFO: Test took 4246ms.
[18:28:53.992] <TB1> INFO: scanning low vcal = 120
[18:28:54.269] <TB1> INFO: Expecting 41600 events.
[18:28:58.211] <TB1> INFO: 41600 events read in total (3351ms).
[18:28:58.211] <TB1> INFO: Test took 4219ms.
[18:28:58.214] <TB1> INFO: scanning low vcal = 130
[18:28:58.491] <TB1> INFO: Expecting 41600 events.
[18:29:02.456] <TB1> INFO: 41600 events read in total (3374ms).
[18:29:02.457] <TB1> INFO: Test took 4243ms.
[18:29:02.459] <TB1> INFO: scanning low vcal = 140
[18:29:02.736] <TB1> INFO: Expecting 41600 events.
[18:29:06.688] <TB1> INFO: 41600 events read in total (3360ms).
[18:29:06.688] <TB1> INFO: Test took 4228ms.
[18:29:06.691] <TB1> INFO: scanning low vcal = 150
[18:29:06.968] <TB1> INFO: Expecting 41600 events.
[18:29:10.941] <TB1> INFO: 41600 events read in total (3382ms).
[18:29:10.942] <TB1> INFO: Test took 4251ms.
[18:29:10.944] <TB1> INFO: scanning low vcal = 160
[18:29:11.221] <TB1> INFO: Expecting 41600 events.
[18:29:15.168] <TB1> INFO: 41600 events read in total (3356ms).
[18:29:15.168] <TB1> INFO: Test took 4224ms.
[18:29:15.171] <TB1> INFO: scanning low vcal = 170
[18:29:15.448] <TB1> INFO: Expecting 41600 events.
[18:29:19.363] <TB1> INFO: 41600 events read in total (3324ms).
[18:29:19.363] <TB1> INFO: Test took 4192ms.
[18:29:19.366] <TB1> INFO: scanning low vcal = 180
[18:29:19.643] <TB1> INFO: Expecting 41600 events.
[18:29:23.589] <TB1> INFO: 41600 events read in total (3354ms).
[18:29:23.590] <TB1> INFO: Test took 4224ms.
[18:29:23.592] <TB1> INFO: scanning low vcal = 190
[18:29:23.869] <TB1> INFO: Expecting 41600 events.
[18:29:27.813] <TB1> INFO: 41600 events read in total (3352ms).
[18:29:27.814] <TB1> INFO: Test took 4222ms.
[18:29:27.816] <TB1> INFO: scanning low vcal = 200
[18:29:28.093] <TB1> INFO: Expecting 41600 events.
[18:29:32.026] <TB1> INFO: 41600 events read in total (3341ms).
[18:29:32.026] <TB1> INFO: Test took 4210ms.
[18:29:32.029] <TB1> INFO: scanning low vcal = 210
[18:29:32.306] <TB1> INFO: Expecting 41600 events.
[18:29:36.237] <TB1> INFO: 41600 events read in total (3339ms).
[18:29:36.238] <TB1> INFO: Test took 4209ms.
[18:29:36.241] <TB1> INFO: scanning low vcal = 220
[18:29:36.518] <TB1> INFO: Expecting 41600 events.
[18:29:40.479] <TB1> INFO: 41600 events read in total (3369ms).
[18:29:40.480] <TB1> INFO: Test took 4238ms.
[18:29:40.483] <TB1> INFO: scanning low vcal = 230
[18:29:40.760] <TB1> INFO: Expecting 41600 events.
[18:29:44.704] <TB1> INFO: 41600 events read in total (3353ms).
[18:29:44.704] <TB1> INFO: Test took 4221ms.
[18:29:44.707] <TB1> INFO: scanning low vcal = 240
[18:29:44.985] <TB1> INFO: Expecting 41600 events.
[18:29:48.921] <TB1> INFO: 41600 events read in total (3345ms).
[18:29:48.921] <TB1> INFO: Test took 4214ms.
[18:29:48.924] <TB1> INFO: scanning low vcal = 250
[18:29:49.200] <TB1> INFO: Expecting 41600 events.
[18:29:53.201] <TB1> INFO: 41600 events read in total (3409ms).
[18:29:53.201] <TB1> INFO: Test took 4277ms.
[18:29:53.205] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[18:29:53.481] <TB1> INFO: Expecting 41600 events.
[18:29:57.430] <TB1> INFO: 41600 events read in total (3357ms).
[18:29:57.431] <TB1> INFO: Test took 4226ms.
[18:29:57.433] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[18:29:57.710] <TB1> INFO: Expecting 41600 events.
[18:30:01.652] <TB1> INFO: 41600 events read in total (3350ms).
[18:30:01.653] <TB1> INFO: Test took 4219ms.
[18:30:01.656] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[18:30:01.933] <TB1> INFO: Expecting 41600 events.
[18:30:05.875] <TB1> INFO: 41600 events read in total (3351ms).
[18:30:05.877] <TB1> INFO: Test took 4221ms.
[18:30:05.880] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[18:30:06.157] <TB1> INFO: Expecting 41600 events.
[18:30:10.108] <TB1> INFO: 41600 events read in total (3360ms).
[18:30:10.109] <TB1> INFO: Test took 4228ms.
[18:30:10.112] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[18:30:10.389] <TB1> INFO: Expecting 41600 events.
[18:30:14.331] <TB1> INFO: 41600 events read in total (3351ms).
[18:30:14.332] <TB1> INFO: Test took 4220ms.
[18:30:14.745] <TB1> INFO: PixTestGainPedestal::measure() done
[18:30:53.168] <TB1> INFO: PixTestGainPedestal::fit() done
[18:30:53.169] <TB1> INFO: non-linearity mean: 0.935 0.937 0.980 0.967 0.941 0.943 0.905 0.978 0.971 1.020 0.949 0.943 0.921 0.954 0.983 0.981
[18:30:53.169] <TB1> INFO: non-linearity RMS: 0.089 0.149 0.005 0.034 0.167 0.111 0.122 0.005 0.008 0.172 0.060 0.079 0.124 0.041 0.003 0.004
[18:30:53.169] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[18:30:53.187] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[18:30:53.207] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[18:30:53.227] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[18:30:53.248] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[18:30:53.267] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[18:30:53.288] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[18:30:53.310] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[18:30:53.331] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[18:30:53.350] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[18:30:53.370] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[18:30:53.390] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[18:30:53.412] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[18:30:53.430] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[18:30:53.450] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[18:30:53.470] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[18:30:53.490] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 164 seconds
[18:30:53.490] <TB1> INFO: Decoding statistics:
[18:30:53.490] <TB1> INFO: General information:
[18:30:53.490] <TB1> INFO: 16bit words read: 3268350
[18:30:53.490] <TB1> INFO: valid events total: 332800
[18:30:53.490] <TB1> INFO: empty events: 2270
[18:30:53.490] <TB1> INFO: valid events with pixels: 330530
[18:30:53.490] <TB1> INFO: valid pixel hits: 635775
[18:30:53.490] <TB1> INFO: Event errors: 0
[18:30:53.490] <TB1> INFO: start marker: 0
[18:30:53.490] <TB1> INFO: stop marker: 0
[18:30:53.490] <TB1> INFO: overflow: 0
[18:30:53.491] <TB1> INFO: invalid 5bit words: 0
[18:30:53.491] <TB1> INFO: invalid XOR eye diagram: 0
[18:30:53.491] <TB1> INFO: frame (failed synchr.): 0
[18:30:53.491] <TB1> INFO: idle data (no TBM trl): 0
[18:30:53.491] <TB1> INFO: no data (only TBM hdr): 0
[18:30:53.491] <TB1> INFO: TBM errors: 0
[18:30:53.491] <TB1> INFO: flawed TBM headers: 0
[18:30:53.491] <TB1> INFO: flawed TBM trailers: 0
[18:30:53.491] <TB1> INFO: event ID mismatches: 0
[18:30:53.491] <TB1> INFO: ROC errors: 0
[18:30:53.491] <TB1> INFO: missing ROC header(s): 0
[18:30:53.491] <TB1> INFO: misplaced readback start: 0
[18:30:53.491] <TB1> INFO: Pixel decoding errors: 0
[18:30:53.491] <TB1> INFO: pixel data incomplete: 0
[18:30:53.491] <TB1> INFO: pixel address: 0
[18:30:53.491] <TB1> INFO: pulse height fill bit: 0
[18:30:53.491] <TB1> INFO: buffer corruption: 0
[18:30:53.511] <TB1> INFO: Decoding statistics:
[18:30:53.511] <TB1> INFO: General information:
[18:30:53.511] <TB1> INFO: 16bit words read: 3397766
[18:30:53.511] <TB1> INFO: valid events total: 353536
[18:30:53.511] <TB1> INFO: empty events: 20506
[18:30:53.511] <TB1> INFO: valid events with pixels: 333030
[18:30:53.511] <TB1> INFO: valid pixel hits: 638275
[18:30:53.511] <TB1> INFO: Event errors: 0
[18:30:53.511] <TB1> INFO: start marker: 0
[18:30:53.511] <TB1> INFO: stop marker: 0
[18:30:53.511] <TB1> INFO: overflow: 0
[18:30:53.511] <TB1> INFO: invalid 5bit words: 0
[18:30:53.511] <TB1> INFO: invalid XOR eye diagram: 0
[18:30:53.511] <TB1> INFO: frame (failed synchr.): 0
[18:30:53.511] <TB1> INFO: idle data (no TBM trl): 0
[18:30:53.511] <TB1> INFO: no data (only TBM hdr): 0
[18:30:53.511] <TB1> INFO: TBM errors: 0
[18:30:53.511] <TB1> INFO: flawed TBM headers: 0
[18:30:53.511] <TB1> INFO: flawed TBM trailers: 0
[18:30:53.511] <TB1> INFO: event ID mismatches: 0
[18:30:53.511] <TB1> INFO: ROC errors: 0
[18:30:53.511] <TB1> INFO: missing ROC header(s): 0
[18:30:53.511] <TB1> INFO: misplaced readback start: 0
[18:30:53.511] <TB1> INFO: Pixel decoding errors: 0
[18:30:53.511] <TB1> INFO: pixel data incomplete: 0
[18:30:53.511] <TB1> INFO: pixel address: 0
[18:30:53.511] <TB1> INFO: pulse height fill bit: 0
[18:30:53.511] <TB1> INFO: buffer corruption: 0
[18:30:53.511] <TB1> INFO: enter test to run
[18:30:53.511] <TB1> INFO: test: Trim80 no parameter change
[18:30:53.511] <TB1> INFO: running: trim80
[18:30:53.535] <TB1> INFO: ######################################################################
[18:30:53.535] <TB1> INFO: PixTestTrim80::doTest()
[18:30:53.535] <TB1> INFO: ######################################################################
[18:30:53.536] <TB1> INFO: ----------------------------------------------------------------------
[18:30:53.536] <TB1> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[18:30:53.536] <TB1> INFO: ----------------------------------------------------------------------
[18:30:53.578] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[18:30:53.578] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[18:30:53.586] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:30:53.586] <TB1> INFO: run 1 of 1
[18:30:53.829] <TB1> INFO: Expecting 5025280 events.
[18:31:21.476] <TB1> INFO: 691928 events read in total (27056ms).
[18:31:48.205] <TB1> INFO: 1380912 events read in total (53785ms).
[18:32:14.953] <TB1> INFO: 2067688 events read in total (80533ms).
[18:32:42.083] <TB1> INFO: 2752840 events read in total (107663ms).
[18:33:08.982] <TB1> INFO: 3437040 events read in total (134562ms).
[18:33:36.038] <TB1> INFO: 4120264 events read in total (161618ms).
[18:34:03.193] <TB1> INFO: 4798112 events read in total (188773ms).
[18:34:12.763] <TB1> INFO: 5025280 events read in total (198343ms).
[18:34:12.823] <TB1> INFO: Test took 199237ms.
[18:34:36.520] <TB1> INFO: ROC 0 VthrComp = 79
[18:34:36.520] <TB1> INFO: ROC 1 VthrComp = 92
[18:34:36.521] <TB1> INFO: ROC 2 VthrComp = 91
[18:34:36.521] <TB1> INFO: ROC 3 VthrComp = 77
[18:34:36.521] <TB1> INFO: ROC 4 VthrComp = 71
[18:34:36.521] <TB1> INFO: ROC 5 VthrComp = 84
[18:34:36.521] <TB1> INFO: ROC 6 VthrComp = 89
[18:34:36.521] <TB1> INFO: ROC 7 VthrComp = 75
[18:34:36.521] <TB1> INFO: ROC 8 VthrComp = 90
[18:34:36.521] <TB1> INFO: ROC 9 VthrComp = 87
[18:34:36.521] <TB1> INFO: ROC 10 VthrComp = 88
[18:34:36.521] <TB1> INFO: ROC 11 VthrComp = 87
[18:34:36.521] <TB1> INFO: ROC 12 VthrComp = 91
[18:34:36.522] <TB1> INFO: ROC 13 VthrComp = 83
[18:34:36.522] <TB1> INFO: ROC 14 VthrComp = 83
[18:34:36.522] <TB1> INFO: ROC 15 VthrComp = 89
[18:34:36.795] <TB1> INFO: Expecting 41600 events.
[18:34:40.209] <TB1> INFO: 41600 events read in total (2823ms).
[18:34:40.210] <TB1> INFO: Test took 3687ms.
[18:34:40.219] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[18:34:40.219] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[18:34:40.227] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:34:40.227] <TB1> INFO: run 1 of 1
[18:34:40.505] <TB1> INFO: Expecting 5025280 events.
[18:35:07.853] <TB1> INFO: 684232 events read in total (26756ms).
[18:35:34.889] <TB1> INFO: 1365120 events read in total (53792ms).
[18:36:01.846] <TB1> INFO: 2044280 events read in total (80749ms).
[18:36:28.449] <TB1> INFO: 2720200 events read in total (107352ms).
[18:36:55.325] <TB1> INFO: 3393024 events read in total (134228ms).
[18:37:22.296] <TB1> INFO: 4065936 events read in total (161199ms).
[18:37:49.268] <TB1> INFO: 4736448 events read in total (188171ms).
[18:38:00.964] <TB1> INFO: 5025280 events read in total (199867ms).
[18:38:01.012] <TB1> INFO: Test took 200784ms.
[18:38:24.919] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 111.768 for pixel 5/79 mean/min/max = 94.856/77.6044/112.108
[18:38:24.919] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 108.995 for pixel 2/33 mean/min/max = 92.0476/75.0287/109.066
[18:38:24.919] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 108.671 for pixel 0/21 mean/min/max = 92.2977/75.914/108.681
[18:38:24.920] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 110.845 for pixel 50/18 mean/min/max = 94.2447/77.4323/111.057
[18:38:24.920] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 104.411 for pixel 6/79 mean/min/max = 88.9521/73.3863/104.518
[18:38:24.921] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 108.118 for pixel 39/0 mean/min/max = 91.7519/75.3634/108.14
[18:38:24.921] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 110.036 for pixel 0/8 mean/min/max = 93.3242/76.4756/110.173
[18:38:24.922] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 110.65 for pixel 5/26 mean/min/max = 93.9134/76.9203/110.907
[18:38:24.922] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 108.887 for pixel 11/75 mean/min/max = 92.5233/75.9842/109.062
[18:38:24.922] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 109.728 for pixel 15/79 mean/min/max = 92.4091/74.9039/109.914
[18:38:24.923] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 109.474 for pixel 0/58 mean/min/max = 93.1086/76.6967/109.52
[18:38:24.923] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 110.123 for pixel 6/0 mean/min/max = 92.5502/74.8926/110.208
[18:38:24.923] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 109.417 for pixel 4/79 mean/min/max = 92.6256/75.6908/109.56
[18:38:24.924] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 109.015 for pixel 51/8 mean/min/max = 91.7513/74.328/109.175
[18:38:24.924] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 108.987 for pixel 0/71 mean/min/max = 92.0092/74.5497/109.469
[18:38:24.924] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 110.011 for pixel 17/1 mean/min/max = 92.9124/75.5657/110.259
[18:38:24.925] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:38:25.013] <TB1> INFO: Expecting 411648 events.
[18:38:34.295] <TB1> INFO: 411648 events read in total (8690ms).
[18:38:34.303] <TB1> INFO: Expecting 411648 events.
[18:38:43.409] <TB1> INFO: 411648 events read in total (8703ms).
[18:38:43.423] <TB1> INFO: Expecting 411648 events.
[18:38:52.603] <TB1> INFO: 411648 events read in total (8777ms).
[18:38:52.619] <TB1> INFO: Expecting 411648 events.
[18:39:01.770] <TB1> INFO: 411648 events read in total (8748ms).
[18:39:01.786] <TB1> INFO: Expecting 411648 events.
[18:39:10.881] <TB1> INFO: 411648 events read in total (8692ms).
[18:39:10.905] <TB1> INFO: Expecting 411648 events.
[18:39:20.075] <TB1> INFO: 411648 events read in total (8767ms).
[18:39:20.095] <TB1> INFO: Expecting 411648 events.
[18:39:29.189] <TB1> INFO: 411648 events read in total (8692ms).
[18:39:29.223] <TB1> INFO: Expecting 411648 events.
[18:39:38.415] <TB1> INFO: 411648 events read in total (8787ms).
[18:39:38.440] <TB1> INFO: Expecting 411648 events.
[18:39:47.575] <TB1> INFO: 411648 events read in total (8732ms).
[18:39:47.602] <TB1> INFO: Expecting 411648 events.
[18:39:56.782] <TB1> INFO: 411648 events read in total (8777ms).
[18:39:56.851] <TB1> INFO: Expecting 411648 events.
[18:40:06.049] <TB1> INFO: 411648 events read in total (8795ms).
[18:40:06.084] <TB1> INFO: Expecting 411648 events.
[18:40:15.161] <TB1> INFO: 411648 events read in total (8674ms).
[18:40:15.202] <TB1> INFO: Expecting 411648 events.
[18:40:24.435] <TB1> INFO: 411648 events read in total (8830ms).
[18:40:24.475] <TB1> INFO: Expecting 411648 events.
[18:40:33.562] <TB1> INFO: 411648 events read in total (8684ms).
[18:40:33.641] <TB1> INFO: Expecting 411648 events.
[18:40:42.786] <TB1> INFO: 411648 events read in total (8742ms).
[18:40:42.886] <TB1> INFO: Expecting 411648 events.
[18:40:52.099] <TB1> INFO: 411648 events read in total (8810ms).
[18:40:52.186] <TB1> INFO: Test took 147261ms.
[18:40:53.670] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[18:40:53.680] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:40:53.680] <TB1> INFO: run 1 of 1
[18:40:53.911] <TB1> INFO: Expecting 5025280 events.
[18:41:21.659] <TB1> INFO: 666256 events read in total (27156ms).
[18:41:48.614] <TB1> INFO: 1328704 events read in total (54111ms).
[18:42:15.235] <TB1> INFO: 1991528 events read in total (80732ms).
[18:42:41.714] <TB1> INFO: 2651592 events read in total (107211ms).
[18:43:08.143] <TB1> INFO: 3307248 events read in total (133640ms).
[18:43:34.588] <TB1> INFO: 3962104 events read in total (160085ms).
[18:44:01.585] <TB1> INFO: 4615728 events read in total (187082ms).
[18:44:18.183] <TB1> INFO: 5025280 events read in total (203680ms).
[18:44:18.264] <TB1> INFO: Test took 204584ms.
[18:44:44.678] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 48.492638 .. 98.890537
[18:44:44.000] <TB1> INFO: Expecting 208000 events.
[18:44:54.825] <TB1> INFO: 208000 events read in total (9234ms).
[18:44:54.825] <TB1> INFO: Test took 10146ms.
[18:44:54.894] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 38 .. 108 (-1/-1) hits flags = 528 (plus default)
[18:44:54.905] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:44:54.906] <TB1> INFO: run 1 of 1
[18:44:55.183] <TB1> INFO: Expecting 2362880 events.
[18:45:23.751] <TB1> INFO: 707160 events read in total (27976ms).
[18:45:51.660] <TB1> INFO: 1409080 events read in total (55885ms).
[18:46:19.430] <TB1> INFO: 2105704 events read in total (83655ms).
[18:46:29.871] <TB1> INFO: 2362880 events read in total (94096ms).
[18:46:29.915] <TB1> INFO: Test took 95010ms.
[18:46:49.300] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 57.380156 .. 90.524517
[18:46:49.536] <TB1> INFO: Expecting 208000 events.
[18:46:59.810] <TB1> INFO: 208000 events read in total (9682ms).
[18:46:59.811] <TB1> INFO: Test took 10510ms.
[18:46:59.878] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 47 .. 100 (-1/-1) hits flags = 528 (plus default)
[18:46:59.889] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:46:59.890] <TB1> INFO: run 1 of 1
[18:47:00.175] <TB1> INFO: Expecting 1797120 events.
[18:47:28.810] <TB1> INFO: 710744 events read in total (28043ms).
[18:47:56.756] <TB1> INFO: 1420384 events read in total (55989ms).
[18:48:12.265] <TB1> INFO: 1797120 events read in total (71498ms).
[18:48:12.293] <TB1> INFO: Test took 72404ms.
[18:48:28.867] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 61.579278 .. 91.858354
[18:48:29.174] <TB1> INFO: Expecting 208000 events.
[18:48:38.901] <TB1> INFO: 208000 events read in total (9136ms).
[18:48:38.901] <TB1> INFO: Test took 10031ms.
[18:48:38.948] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 51 .. 101 (-1/-1) hits flags = 528 (plus default)
[18:48:38.958] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:48:38.958] <TB1> INFO: run 1 of 1
[18:48:39.236] <TB1> INFO: Expecting 1697280 events.
[18:49:08.127] <TB1> INFO: 694760 events read in total (28300ms).
[18:49:35.976] <TB1> INFO: 1389128 events read in total (56150ms).
[18:49:48.800] <TB1> INFO: 1697280 events read in total (68973ms).
[18:49:48.828] <TB1> INFO: Test took 69871ms.
[18:50:05.852] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 65.292445 .. 93.930784
[18:50:06.092] <TB1> INFO: Expecting 208000 events.
[18:50:15.897] <TB1> INFO: 208000 events read in total (9214ms).
[18:50:15.898] <TB1> INFO: Test took 10045ms.
[18:50:15.946] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 55 .. 103 (-1/-1) hits flags = 528 (plus default)
[18:50:15.957] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:50:15.957] <TB1> INFO: run 1 of 1
[18:50:16.235] <TB1> INFO: Expecting 1630720 events.
[18:50:44.845] <TB1> INFO: 675336 events read in total (28019ms).
[18:51:12.677] <TB1> INFO: 1350464 events read in total (55851ms).
[18:51:24.264] <TB1> INFO: 1630720 events read in total (67438ms).
[18:51:24.303] <TB1> INFO: Test took 68347ms.
[18:51:42.436] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[18:51:42.436] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[18:51:42.446] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[18:51:42.446] <TB1> INFO: run 1 of 1
[18:51:42.679] <TB1> INFO: Expecting 1364480 events.
[18:52:11.342] <TB1> INFO: 667768 events read in total (28071ms).
[18:52:39.266] <TB1> INFO: 1330968 events read in total (55995ms).
[18:52:41.119] <TB1> INFO: 1364480 events read in total (57848ms).
[18:52:41.142] <TB1> INFO: Test took 58696ms.
[18:52:58.941] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters80_C0.dat
[18:52:58.941] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters80_C1.dat
[18:52:58.941] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters80_C2.dat
[18:52:58.941] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters80_C3.dat
[18:52:58.941] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters80_C4.dat
[18:52:58.941] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters80_C5.dat
[18:52:58.941] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters80_C6.dat
[18:52:58.942] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters80_C7.dat
[18:52:58.942] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters80_C8.dat
[18:52:58.942] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters80_C9.dat
[18:52:58.942] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters80_C10.dat
[18:52:58.942] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters80_C11.dat
[18:52:58.942] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters80_C12.dat
[18:52:58.942] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters80_C13.dat
[18:52:58.942] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters80_C14.dat
[18:52:58.942] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//dacParameters80_C15.dat
[18:52:58.942] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters80_C0.dat
[18:52:58.950] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters80_C1.dat
[18:52:58.959] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters80_C2.dat
[18:52:58.967] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters80_C3.dat
[18:52:58.974] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters80_C4.dat
[18:52:58.981] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters80_C5.dat
[18:52:58.989] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters80_C6.dat
[18:52:58.996] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters80_C7.dat
[18:52:59.003] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters80_C8.dat
[18:52:59.011] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters80_C9.dat
[18:52:59.019] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters80_C10.dat
[18:52:59.026] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters80_C11.dat
[18:52:59.033] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters80_C12.dat
[18:52:59.038] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters80_C13.dat
[18:52:59.044] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters80_C14.dat
[18:52:59.050] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1122_FullQualification_2016-11-03_14h28m_1478179737//003_FulltestTrim80_p17//trimParameters80_C15.dat
[18:52:59.055] <TB1> INFO: PixTestTrim80::trimTest() done
[18:52:59.055] <TB1> INFO: vtrim: 121 139 125 134 88 109 110 106 123 125 111 122 113 110 122 126
[18:52:59.055] <TB1> INFO: vthrcomp: 79 92 91 77 71 84 89 75 90 87 88 87 91 83 83 89
[18:52:59.055] <TB1> INFO: vcal mean: 79.95 79.96 79.95 79.97 79.97 79.97 80.00 80.00 79.98 79.98 79.99 79.97 79.97 79.94 79.91 79.97
[18:52:59.055] <TB1> INFO: vcal RMS: 0.83 0.85 0.84 0.84 0.74 0.80 0.90 0.84 0.80 0.88 0.73 0.87 0.78 1.49 0.88 0.85
[18:52:59.055] <TB1> INFO: bits mean: 9.86 10.66 10.38 10.27 10.35 10.71 9.63 9.39 9.97 10.43 9.72 10.24 10.28 10.21 10.43 10.29
[18:52:59.055] <TB1> INFO: bits RMS: 2.04 2.07 2.14 1.92 2.61 2.03 2.33 2.34 2.29 2.26 2.26 2.26 2.13 2.33 2.22 2.15
[18:52:59.061] <TB1> INFO: ----------------------------------------------------------------------
[18:52:59.061] <TB1> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[18:52:59.061] <TB1> INFO: ----------------------------------------------------------------------
[18:52:59.064] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[18:52:59.073] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[18:52:59.073] <TB1> INFO: run 1 of 1
[18:52:59.349] <TB1> INFO: Expecting 4160000 events.
[18:53:32.482] <TB1> INFO: 791655 events read in total (32542ms).
[18:54:04.440] <TB1> INFO: 1576490 events read in total (64500ms).
[18:54:36.637] <TB1> INFO: 2355585 events read in total (96697ms).
[18:55:08.558] <TB1> INFO: 3130500 events read in total (128618ms).
[18:55:40.440] <TB1> INFO: 3904575 events read in total (160500ms).
[18:55:51.356] <TB1> INFO: 4160000 events read in total (171416ms).
[18:55:51.434] <TB1> INFO: Test took 172362ms.
[18:56:14.994] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 242 (-1/-1) hits flags = 528 (plus default)
[18:56:15.006] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[18:56:15.006] <TB1> INFO: run 1 of 1
[18:56:15.278] <TB1> INFO: Expecting 5054400 events.
[18:56:46.167] <TB1> INFO: 708565 events read in total (30297ms).
[18:57:16.209] <TB1> INFO: 1413780 events read in total (60339ms).
[18:57:46.472] <TB1> INFO: 2116110 events read in total (90602ms).
[18:58:16.791] <TB1> INFO: 2815535 events read in total (120921ms).
[18:58:46.976] <TB1> INFO: 3512780 events read in total (151106ms).
[18:59:17.824] <TB1> INFO: 4209465 events read in total (181954ms).
[18:59:47.450] <TB1> INFO: 4898700 events read in total (211580ms).
[18:59:54.453] <TB1> INFO: 5054400 events read in total (218583ms).
[18:59:54.601] <TB1> INFO: Test took 219596ms.
[19:00:26.601] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 213 (-1/-1) hits flags = 528 (plus default)
[19:00:26.609] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:00:26.609] <TB1> INFO: run 1 of 1
[19:00:26.882] <TB1> INFO: Expecting 4451200 events.
[19:00:58.973] <TB1> INFO: 742030 events read in total (31500ms).
[19:01:29.916] <TB1> INFO: 1479455 events read in total (62443ms).
[19:02:01.129] <TB1> INFO: 2212410 events read in total (93656ms).
[19:02:32.561] <TB1> INFO: 2941265 events read in total (125088ms).
[19:03:02.846] <TB1> INFO: 3668975 events read in total (155373ms).
[19:03:33.307] <TB1> INFO: 4397555 events read in total (185834ms).
[19:03:35.953] <TB1> INFO: 4451200 events read in total (188480ms).
[19:03:36.081] <TB1> INFO: Test took 189471ms.
[19:04:03.700] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 214 (-1/-1) hits flags = 528 (plus default)
[19:04:03.710] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:04:03.710] <TB1> INFO: run 1 of 1
[19:04:03.942] <TB1> INFO: Expecting 4472000 events.
[19:04:35.642] <TB1> INFO: 740555 events read in total (31109ms).
[19:05:06.712] <TB1> INFO: 1476525 events read in total (62179ms).
[19:05:37.532] <TB1> INFO: 2208110 events read in total (92999ms).
[19:06:08.687] <TB1> INFO: 2935805 events read in total (124154ms).
[19:06:39.861] <TB1> INFO: 3662410 events read in total (155328ms).
[19:07:10.884] <TB1> INFO: 4388670 events read in total (186351ms).
[19:07:14.683] <TB1> INFO: 4472000 events read in total (190150ms).
[19:07:14.773] <TB1> INFO: Test took 191064ms.
[19:07:42.364] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 212 (-1/-1) hits flags = 528 (plus default)
[19:07:42.376] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[19:07:42.376] <TB1> INFO: run 1 of 1
[19:07:42.612] <TB1> INFO: Expecting 4430400 events.
[19:08:14.145] <TB1> INFO: 743395 events read in total (30941ms).
[19:08:44.991] <TB1> INFO: 1482210 events read in total (61787ms).
[19:09:16.059] <TB1> INFO: 2216725 events read in total (92855ms).
[19:09:47.718] <TB1> INFO: 2946545 events read in total (124514ms).
[19:10:19.562] <TB1> INFO: 3675930 events read in total (156358ms).
[19:10:51.554] <TB1> INFO: 4407100 events read in total (188350ms).
[19:10:52.908] <TB1> INFO: 4430400 events read in total (189704ms).
[19:10:52.983] <TB1> INFO: Test took 190607ms.
[19:11:18.718] <TB1> INFO: PixTestTrim80::trimBitTest() done
[19:11:18.720] <TB1> INFO: PixTestTrim80::doTest() done, duration: 2425 seconds
[19:11:19.436] <TB1> INFO: enter test to run
[19:11:19.436] <TB1> INFO: test: exit no parameter change
[19:11:19.531] <TB1> QUIET: Connection to board 153 closed.
[19:11:19.532] <TB1> INFO: pXar: this is the end, my friend