[16:44:07.184] <TB2> INFO: *** Welcome to pxar ***
[16:44:07.185] <TB2> INFO: *** Today: 2016/11/04
[16:44:07.190] <TB2> INFO: *** Version: c8ba-dirty
[16:44:07.190] <TB2> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C15.dat
[16:44:07.191] <TB2> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//tbmParameters_C1b.dat
[16:44:07.191] <TB2> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//defaultMaskFile.dat
[16:44:07.191] <TB2> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters_C15.dat
[16:44:07.245] <TB2> INFO: clk: 4
[16:44:07.245] <TB2> INFO: ctr: 4
[16:44:07.245] <TB2> INFO: sda: 19
[16:44:07.245] <TB2> INFO: tin: 9
[16:44:07.245] <TB2> INFO: level: 15
[16:44:07.245] <TB2> INFO: triggerdelay: 0
[16:44:07.245] <TB2> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[16:44:07.245] <TB2> INFO: Log level: INFO
[16:44:07.253] <TB2> INFO: Found DTB DTB_WXC55Z
[16:44:07.264] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[16:44:07.266] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[16:44:07.268] <TB2> INFO: RPC call hashes of host and DTB match: 486171790
[16:44:08.761] <TB2> INFO: DUT info:
[16:44:08.761] <TB2> INFO: The DUT currently contains the following objects:
[16:44:08.761] <TB2> INFO: 4 TBM Cores tbm10c (4 ON)
[16:44:08.761] <TB2> INFO: TBM Core alpha (0): 7 registers set
[16:44:08.761] <TB2> INFO: TBM Core beta (1): 7 registers set
[16:44:08.761] <TB2> INFO: TBM Core alpha (2): 7 registers set
[16:44:08.761] <TB2> INFO: TBM Core beta (3): 7 registers set
[16:44:08.761] <TB2> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[16:44:08.761] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[16:44:08.761] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[16:44:08.761] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[16:44:08.761] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[16:44:08.761] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[16:44:08.761] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[16:44:08.761] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[16:44:08.761] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[16:44:08.761] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[16:44:08.761] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[16:44:08.761] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[16:44:08.761] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[16:44:08.761] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[16:44:08.761] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[16:44:08.761] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[16:44:08.761] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[16:44:09.162] <TB2> INFO: enter 'restricted' command line mode
[16:44:09.162] <TB2> INFO: enter test to run
[16:44:09.162] <TB2> INFO: test: pretest no parameter change
[16:44:09.162] <TB2> INFO: running: pretest
[16:44:09.690] <TB2> INFO: ######################################################################
[16:44:09.690] <TB2> INFO: PixTestPretest::doTest()
[16:44:09.690] <TB2> INFO: ######################################################################
[16:44:09.691] <TB2> INFO: ----------------------------------------------------------------------
[16:44:09.691] <TB2> INFO: PixTestPretest::programROC()
[16:44:09.691] <TB2> INFO: ----------------------------------------------------------------------
[16:44:27.703] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[16:44:27.703] <TB2> INFO: IA differences per ROC: 17.7 19.3 19.3 19.3 18.5 20.9 20.9 19.3 20.1 20.1 19.3 18.5 17.7 16.9 20.9 21.7
[16:44:27.740] <TB2> INFO: ----------------------------------------------------------------------
[16:44:27.740] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[16:44:27.740] <TB2> INFO: ----------------------------------------------------------------------
[16:44:48.984] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 384.3 mA = 24.0187 mA/ROC
[16:44:48.984] <TB2> INFO: i(loss) [mA/ROC]: 20.1 18.5 20.1 19.3 20.1 19.3 18.5 20.1 18.5 19.3 18.5 20.1 20.1 19.3 17.7 19.3
[16:44:49.013] <TB2> INFO: ----------------------------------------------------------------------
[16:44:49.013] <TB2> INFO: PixTestPretest::findTiming()
[16:44:49.013] <TB2> INFO: ----------------------------------------------------------------------
[16:44:49.013] <TB2> INFO: PixTestCmd::init()

[16:45:20.216] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[16:45:20.216] <TB2> INFO: (success/tries = 100/100), width = 3
[16:45:21.722] <TB2> INFO: ----------------------------------------------------------------------
[16:45:21.722] <TB2> INFO: PixTestPretest::findWorkingPixel()
[16:45:21.722] <TB2> INFO: ----------------------------------------------------------------------
[16:45:21.813] <TB2> INFO: Expecting 231680 events.
[16:45:31.382] <TB2> INFO: 231680 events read in total (8977ms).
[16:45:31.390] <TB2> INFO: Test took 9666ms.
[16:45:31.637] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[16:45:31.666] <TB2> INFO: ----------------------------------------------------------------------
[16:45:31.666] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[16:45:31.666] <TB2> INFO: ----------------------------------------------------------------------
[16:45:31.758] <TB2> INFO: Expecting 231680 events.
[16:45:41.326] <TB2> INFO: 231680 events read in total (8976ms).
[16:45:41.334] <TB2> INFO: Test took 9664ms.
[16:45:41.594] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[16:45:41.594] <TB2> INFO: CalDel: 106 93 116 94 89 109 104 97 115 103 105 93 110 88 105 100
[16:45:41.594] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[16:45:41.596] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C0.dat
[16:45:41.596] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C1.dat
[16:45:41.597] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C2.dat
[16:45:41.597] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C3.dat
[16:45:41.597] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C4.dat
[16:45:41.597] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C5.dat
[16:45:41.597] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C6.dat
[16:45:41.597] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C7.dat
[16:45:41.597] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C8.dat
[16:45:41.597] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C9.dat
[16:45:41.597] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C10.dat
[16:45:41.598] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C11.dat
[16:45:41.598] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C12.dat
[16:45:41.598] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C13.dat
[16:45:41.598] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C14.dat
[16:45:41.598] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters_C15.dat
[16:45:41.598] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//tbmParameters_C0a.dat
[16:45:41.598] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//tbmParameters_C0b.dat
[16:45:41.598] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//tbmParameters_C1a.dat
[16:45:41.598] <TB2> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//tbmParameters_C1b.dat
[16:45:41.598] <TB2> INFO: PixTestPretest::doTest() done, duration: 92 seconds
[16:45:41.710] <TB2> INFO: enter test to run
[16:45:41.710] <TB2> INFO: test: FullTest no parameter change
[16:45:41.710] <TB2> INFO: running: fulltest
[16:45:41.710] <TB2> INFO: ######################################################################
[16:45:41.710] <TB2> INFO: PixTestFullTest::doTest()
[16:45:41.710] <TB2> INFO: ######################################################################
[16:45:41.711] <TB2> INFO: ######################################################################
[16:45:41.711] <TB2> INFO: PixTestAlive::doTest()
[16:45:41.711] <TB2> INFO: ######################################################################
[16:45:41.712] <TB2> INFO: ----------------------------------------------------------------------
[16:45:41.712] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:45:41.712] <TB2> INFO: ----------------------------------------------------------------------
[16:45:41.946] <TB2> INFO: Expecting 41600 events.
[16:45:45.370] <TB2> INFO: 41600 events read in total (2832ms).
[16:45:45.371] <TB2> INFO: Test took 3657ms.
[16:45:45.596] <TB2> INFO: PixTestAlive::aliveTest() done
[16:45:45.596] <TB2> INFO: number of dead pixels (per ROC): 2 0 0 3 0 0 0 2 0 0 0 0 0 0 0 0
[16:45:45.597] <TB2> INFO: ----------------------------------------------------------------------
[16:45:45.597] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:45:45.597] <TB2> INFO: ----------------------------------------------------------------------
[16:45:45.832] <TB2> INFO: Expecting 41600 events.
[16:45:48.866] <TB2> INFO: 41600 events read in total (2443ms).
[16:45:48.866] <TB2> INFO: Test took 3268ms.
[16:45:48.867] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[16:45:49.108] <TB2> INFO: PixTestAlive::maskTest() done
[16:45:49.108] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[16:45:49.110] <TB2> INFO: ----------------------------------------------------------------------
[16:45:49.110] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:45:49.110] <TB2> INFO: ----------------------------------------------------------------------
[16:45:49.343] <TB2> INFO: Expecting 41600 events.
[16:45:52.859] <TB2> INFO: 41600 events read in total (2924ms).
[16:45:52.859] <TB2> INFO: Test took 3748ms.
[16:45:53.087] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[16:45:53.087] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[16:45:53.087] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[16:45:53.087] <TB2> INFO: Decoding statistics:
[16:45:53.087] <TB2> INFO: General information:
[16:45:53.087] <TB2> INFO: 16bit words read: 0
[16:45:53.087] <TB2> INFO: valid events total: 0
[16:45:53.087] <TB2> INFO: empty events: 0
[16:45:53.087] <TB2> INFO: valid events with pixels: 0
[16:45:53.087] <TB2> INFO: valid pixel hits: 0
[16:45:53.087] <TB2> INFO: Event errors: 0
[16:45:53.087] <TB2> INFO: start marker: 0
[16:45:53.087] <TB2> INFO: stop marker: 0
[16:45:53.087] <TB2> INFO: overflow: 0
[16:45:53.087] <TB2> INFO: invalid 5bit words: 0
[16:45:53.087] <TB2> INFO: invalid XOR eye diagram: 0
[16:45:53.087] <TB2> INFO: frame (failed synchr.): 0
[16:45:53.087] <TB2> INFO: idle data (no TBM trl): 0
[16:45:53.088] <TB2> INFO: no data (only TBM hdr): 0
[16:45:53.088] <TB2> INFO: TBM errors: 0
[16:45:53.088] <TB2> INFO: flawed TBM headers: 0
[16:45:53.088] <TB2> INFO: flawed TBM trailers: 0
[16:45:53.088] <TB2> INFO: event ID mismatches: 0
[16:45:53.088] <TB2> INFO: ROC errors: 0
[16:45:53.088] <TB2> INFO: missing ROC header(s): 0
[16:45:53.088] <TB2> INFO: misplaced readback start: 0
[16:45:53.088] <TB2> INFO: Pixel decoding errors: 0
[16:45:53.088] <TB2> INFO: pixel data incomplete: 0
[16:45:53.088] <TB2> INFO: pixel address: 0
[16:45:53.088] <TB2> INFO: pulse height fill bit: 0
[16:45:53.088] <TB2> INFO: buffer corruption: 0
[16:45:53.094] <TB2> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C15.dat
[16:45:53.095] <TB2> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr_C15.dat

[16:45:53.095] <TB2> INFO: ######################################################################
[16:45:53.095] <TB2> INFO: PixTestReadback::doTest()
[16:45:53.095] <TB2> INFO: ######################################################################
[16:45:53.095] <TB2> INFO: ----------------------------------------------------------------------
[16:45:53.095] <TB2> INFO: PixTestReadback::CalibrateVd()
[16:45:53.095] <TB2> INFO: ----------------------------------------------------------------------
[16:46:03.047] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C0.dat
[16:46:03.047] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C1.dat
[16:46:03.047] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C2.dat
[16:46:03.047] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C3.dat
[16:46:03.047] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C4.dat
[16:46:03.047] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C5.dat
[16:46:03.047] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C6.dat
[16:46:03.047] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C7.dat
[16:46:03.047] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C8.dat
[16:46:03.047] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C9.dat
[16:46:03.047] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C10.dat
[16:46:03.048] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C11.dat
[16:46:03.048] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C12.dat
[16:46:03.048] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C13.dat
[16:46:03.048] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C14.dat
[16:46:03.048] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C15.dat
[16:46:03.076] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:46:03.076] <TB2> INFO: ----------------------------------------------------------------------
[16:46:03.076] <TB2> INFO: PixTestReadback::CalibrateVa()
[16:46:03.076] <TB2> INFO: ----------------------------------------------------------------------
[16:46:12.962] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C0.dat
[16:46:12.962] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C1.dat
[16:46:12.962] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C2.dat
[16:46:12.962] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C3.dat
[16:46:12.962] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C4.dat
[16:46:12.962] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C5.dat
[16:46:12.963] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C6.dat
[16:46:12.963] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C7.dat
[16:46:12.963] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C8.dat
[16:46:12.963] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C9.dat
[16:46:12.963] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C10.dat
[16:46:12.963] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C11.dat
[16:46:12.963] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C12.dat
[16:46:12.963] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C13.dat
[16:46:12.963] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C14.dat
[16:46:12.963] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C15.dat
[16:46:12.991] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:46:12.991] <TB2> INFO: ----------------------------------------------------------------------
[16:46:12.991] <TB2> INFO: PixTestReadback::readbackVbg()
[16:46:12.991] <TB2> INFO: ----------------------------------------------------------------------
[16:46:20.632] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:46:20.632] <TB2> INFO: ----------------------------------------------------------------------
[16:46:20.632] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[16:46:20.632] <TB2> INFO: ----------------------------------------------------------------------
[16:46:20.632] <TB2> INFO: Vbg will be calibrated using Vd calibration
[16:46:20.632] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 157.1calibrated Vbg = 1.15782 :::*/*/*/*/
[16:46:20.632] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 151.2calibrated Vbg = 1.16203 :::*/*/*/*/
[16:46:20.632] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 147calibrated Vbg = 1.15618 :::*/*/*/*/
[16:46:20.632] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 150.7calibrated Vbg = 1.14968 :::*/*/*/*/
[16:46:20.632] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 146.3calibrated Vbg = 1.15406 :::*/*/*/*/
[16:46:20.632] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 154.6calibrated Vbg = 1.16249 :::*/*/*/*/
[16:46:20.632] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 141.9calibrated Vbg = 1.15546 :::*/*/*/*/
[16:46:20.632] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 164.7calibrated Vbg = 1.15881 :::*/*/*/*/
[16:46:20.632] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 157.3calibrated Vbg = 1.16637 :::*/*/*/*/
[16:46:20.632] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 155.4calibrated Vbg = 1.15631 :::*/*/*/*/
[16:46:20.632] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 157.9calibrated Vbg = 1.15032 :::*/*/*/*/
[16:46:20.632] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 157.6calibrated Vbg = 1.14466 :::*/*/*/*/
[16:46:20.632] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 148.7calibrated Vbg = 1.15698 :::*/*/*/*/
[16:46:20.632] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 150.2calibrated Vbg = 1.15688 :::*/*/*/*/
[16:46:20.632] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 159.8calibrated Vbg = 1.15713 :::*/*/*/*/
[16:46:20.632] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 155.1calibrated Vbg = 1.15545 :::*/*/*/*/
[16:46:20.634] <TB2> INFO: ----------------------------------------------------------------------
[16:46:20.634] <TB2> INFO: PixTestReadback::CalibrateIa()
[16:46:20.634] <TB2> INFO: ----------------------------------------------------------------------
[16:49:00.902] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C0.dat
[16:49:00.902] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C1.dat
[16:49:00.902] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C2.dat
[16:49:00.902] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C3.dat
[16:49:00.902] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C4.dat
[16:49:00.902] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C5.dat
[16:49:00.902] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C6.dat
[16:49:00.902] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C7.dat
[16:49:00.902] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C8.dat
[16:49:00.902] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C9.dat
[16:49:00.902] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C10.dat
[16:49:00.902] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C11.dat
[16:49:00.903] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C12.dat
[16:49:00.903] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C13.dat
[16:49:00.903] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C14.dat
[16:49:00.903] <TB2> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//readbackCal_C15.dat
[16:49:00.930] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:49:00.931] <TB2> INFO: PixTestReadback::doTest() done
[16:49:00.931] <TB2> INFO: Decoding statistics:
[16:49:00.931] <TB2> INFO: General information:
[16:49:00.931] <TB2> INFO: 16bit words read: 1536
[16:49:00.931] <TB2> INFO: valid events total: 256
[16:49:00.931] <TB2> INFO: empty events: 256
[16:49:00.931] <TB2> INFO: valid events with pixels: 0
[16:49:00.931] <TB2> INFO: valid pixel hits: 0
[16:49:00.931] <TB2> INFO: Event errors: 0
[16:49:00.931] <TB2> INFO: start marker: 0
[16:49:00.931] <TB2> INFO: stop marker: 0
[16:49:00.931] <TB2> INFO: overflow: 0
[16:49:00.931] <TB2> INFO: invalid 5bit words: 0
[16:49:00.931] <TB2> INFO: invalid XOR eye diagram: 0
[16:49:00.931] <TB2> INFO: frame (failed synchr.): 0
[16:49:00.931] <TB2> INFO: idle data (no TBM trl): 0
[16:49:00.931] <TB2> INFO: no data (only TBM hdr): 0
[16:49:00.931] <TB2> INFO: TBM errors: 0
[16:49:00.931] <TB2> INFO: flawed TBM headers: 0
[16:49:00.931] <TB2> INFO: flawed TBM trailers: 0
[16:49:00.931] <TB2> INFO: event ID mismatches: 0
[16:49:00.931] <TB2> INFO: ROC errors: 0
[16:49:00.931] <TB2> INFO: missing ROC header(s): 0
[16:49:00.931] <TB2> INFO: misplaced readback start: 0
[16:49:00.931] <TB2> INFO: Pixel decoding errors: 0
[16:49:00.931] <TB2> INFO: pixel data incomplete: 0
[16:49:00.931] <TB2> INFO: pixel address: 0
[16:49:00.931] <TB2> INFO: pulse height fill bit: 0
[16:49:00.931] <TB2> INFO: buffer corruption: 0
[16:49:00.965] <TB2> INFO: ######################################################################
[16:49:00.965] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[16:49:00.965] <TB2> INFO: ######################################################################
[16:49:00.968] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[16:49:00.980] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[16:49:00.980] <TB2> INFO: run 1 of 1
[16:49:01.212] <TB2> INFO: Expecting 3120000 events.
[16:49:31.284] <TB2> INFO: 655020 events read in total (29480ms).











[16:50:00.477] <TB2> INFO: 1306160 events read in total (58673ms).











[16:50:29.878] <TB2> INFO: 1953535 events read in total (88074ms).
[16:50:58.979] <TB2> INFO: 2600295 events read in total (117175ms).











[16:51:22.613] <TB2> INFO: 3120000 events read in total (140809ms).
[16:51:22.673] <TB2> INFO: Test took 141694ms.
[16:51:49.664] <TB2> INFO: PixTestBBMap::doTest() done with 2 decoding errors: , duration: 168 seconds
[16:51:49.664] <TB2> INFO: number of dead bumps (per ROC): 6 10 21 22 18 5 2 1 1 4 7 31 107 140 30 11
[16:51:49.664] <TB2> INFO: separation cut (per ROC): 102 94 103 88 104 95 97 111 89 94 101 110 84 89 83 105
[16:51:49.664] <TB2> INFO: Decoding statistics:
[16:51:49.664] <TB2> INFO: General information:
[16:51:49.664] <TB2> INFO: 16bit words read: 0
[16:51:49.664] <TB2> INFO: valid events total: 0
[16:51:49.664] <TB2> INFO: empty events: 0
[16:51:49.664] <TB2> INFO: valid events with pixels: 0
[16:51:49.664] <TB2> INFO: valid pixel hits: 0
[16:51:49.664] <TB2> INFO: Event errors: 0
[16:51:49.664] <TB2> INFO: start marker: 0
[16:51:49.664] <TB2> INFO: stop marker: 0
[16:51:49.664] <TB2> INFO: overflow: 0
[16:51:49.664] <TB2> INFO: invalid 5bit words: 0
[16:51:49.664] <TB2> INFO: invalid XOR eye diagram: 0
[16:51:49.664] <TB2> INFO: frame (failed synchr.): 0
[16:51:49.665] <TB2> INFO: idle data (no TBM trl): 0
[16:51:49.665] <TB2> INFO: no data (only TBM hdr): 0
[16:51:49.665] <TB2> INFO: TBM errors: 0
[16:51:49.665] <TB2> INFO: flawed TBM headers: 0
[16:51:49.665] <TB2> INFO: flawed TBM trailers: 0
[16:51:49.665] <TB2> INFO: event ID mismatches: 0
[16:51:49.665] <TB2> INFO: ROC errors: 0
[16:51:49.665] <TB2> INFO: missing ROC header(s): 0
[16:51:49.665] <TB2> INFO: misplaced readback start: 0
[16:51:49.665] <TB2> INFO: Pixel decoding errors: 0
[16:51:49.665] <TB2> INFO: pixel data incomplete: 0
[16:51:49.665] <TB2> INFO: pixel address: 0
[16:51:49.665] <TB2> INFO: pulse height fill bit: 0
[16:51:49.665] <TB2> INFO: buffer corruption: 0
[16:51:49.711] <TB2> INFO: ######################################################################
[16:51:49.711] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:51:49.711] <TB2> INFO: ######################################################################
[16:51:49.711] <TB2> INFO: ----------------------------------------------------------------------
[16:51:49.711] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[16:51:49.711] <TB2> INFO: ----------------------------------------------------------------------
[16:51:49.711] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[16:51:49.722] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[16:51:49.722] <TB2> INFO: run 1 of 1
[16:51:49.992] <TB2> INFO: Expecting 36608000 events.
[16:52:12.958] <TB2> INFO: 666650 events read in total (22374ms).
[16:52:35.140] <TB2> INFO: 1323500 events read in total (44556ms).
[16:52:57.511] <TB2> INFO: 1977500 events read in total (66927ms).
[16:53:19.806] <TB2> INFO: 2632250 events read in total (89222ms).
[16:53:42.347] <TB2> INFO: 3287750 events read in total (111763ms).
[16:54:04.717] <TB2> INFO: 3944000 events read in total (134133ms).
[16:54:27.243] <TB2> INFO: 4599100 events read in total (156659ms).
[16:54:49.360] <TB2> INFO: 5253100 events read in total (178776ms).
[16:55:11.661] <TB2> INFO: 5906650 events read in total (201077ms).
[16:55:34.195] <TB2> INFO: 6560500 events read in total (223611ms).
[16:55:56.736] <TB2> INFO: 7213550 events read in total (246152ms).
[16:56:19.174] <TB2> INFO: 7866550 events read in total (268590ms).
[16:56:41.489] <TB2> INFO: 8521100 events read in total (290905ms).
[16:57:04.029] <TB2> INFO: 9176550 events read in total (313445ms).
[16:57:26.593] <TB2> INFO: 9831700 events read in total (336009ms).
[16:57:48.799] <TB2> INFO: 10485900 events read in total (358215ms).
[16:58:11.137] <TB2> INFO: 11139650 events read in total (380553ms).
[16:58:33.557] <TB2> INFO: 11794450 events read in total (402973ms).
[16:58:55.818] <TB2> INFO: 12449350 events read in total (425235ms).
[16:59:18.399] <TB2> INFO: 13101800 events read in total (447815ms).
[16:59:40.653] <TB2> INFO: 13755050 events read in total (470069ms).
[17:00:02.976] <TB2> INFO: 14407400 events read in total (492392ms).
[17:00:25.426] <TB2> INFO: 15060750 events read in total (514842ms).
[17:00:47.701] <TB2> INFO: 15712750 events read in total (537117ms).
[17:01:10.185] <TB2> INFO: 16363100 events read in total (559601ms).
[17:01:32.602] <TB2> INFO: 17015550 events read in total (582018ms).
[17:01:55.081] <TB2> INFO: 17666400 events read in total (604497ms).
[17:02:17.498] <TB2> INFO: 18315750 events read in total (626914ms).
[17:02:40.077] <TB2> INFO: 18962850 events read in total (649493ms).
[17:03:02.493] <TB2> INFO: 19612500 events read in total (671909ms).
[17:03:25.035] <TB2> INFO: 20261400 events read in total (694451ms).
[17:03:47.692] <TB2> INFO: 20910700 events read in total (717108ms).
[17:04:10.032] <TB2> INFO: 21558200 events read in total (739448ms).
[17:04:32.707] <TB2> INFO: 22206950 events read in total (762123ms).
[17:04:55.230] <TB2> INFO: 22856750 events read in total (784646ms).
[17:05:17.586] <TB2> INFO: 23507550 events read in total (807002ms).
[17:05:40.163] <TB2> INFO: 24156050 events read in total (829579ms).
[17:06:02.308] <TB2> INFO: 24804200 events read in total (851724ms).
[17:06:24.580] <TB2> INFO: 25451400 events read in total (873996ms).
[17:06:46.810] <TB2> INFO: 26099600 events read in total (896226ms).
[17:07:09.359] <TB2> INFO: 26747250 events read in total (918775ms).
[17:07:31.718] <TB2> INFO: 27394800 events read in total (941134ms).
[17:07:54.211] <TB2> INFO: 28043550 events read in total (963627ms).
[17:08:16.822] <TB2> INFO: 28691850 events read in total (986238ms).
[17:08:39.100] <TB2> INFO: 29340150 events read in total (1008516ms).
[17:09:01.568] <TB2> INFO: 29987350 events read in total (1030984ms).
[17:09:23.616] <TB2> INFO: 30634200 events read in total (1053032ms).
[17:09:46.231] <TB2> INFO: 31281800 events read in total (1075647ms).
[17:10:08.536] <TB2> INFO: 31930650 events read in total (1097952ms).
[17:10:31.030] <TB2> INFO: 32579100 events read in total (1120446ms).
[17:10:53.369] <TB2> INFO: 33226800 events read in total (1142785ms).
[17:11:15.892] <TB2> INFO: 33876250 events read in total (1165308ms).
[17:11:37.956] <TB2> INFO: 34523100 events read in total (1187372ms).
[17:12:00.372] <TB2> INFO: 35170900 events read in total (1209788ms).
[17:12:22.643] <TB2> INFO: 35820950 events read in total (1232059ms).
[17:12:45.393] <TB2> INFO: 36481200 events read in total (1254809ms).
[17:12:50.210] <TB2> INFO: 36608000 events read in total (1259626ms).
[17:12:50.266] <TB2> INFO: Test took 1260545ms.
[17:12:50.670] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:12:52.498] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:12:54.442] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:12:56.343] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:12:57.976] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:12:59.475] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:13:01.064] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:13:02.591] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:13:04.099] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:13:06.130] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:13:07.744] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:13:09.771] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:13:11.721] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:13:13.798] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:13:15.826] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:13:17.908] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[17:13:19.738] <TB2> INFO: PixTestScurves::scurves() done
[17:13:19.738] <TB2> INFO: Vcal mean: 105.25 105.07 124.19 108.35 122.99 116.20 104.98 115.46 108.06 117.10 104.48 114.01 111.25 116.34 102.60 119.16
[17:13:19.738] <TB2> INFO: Vcal RMS: 5.53 5.09 6.82 5.89 5.90 5.46 4.82 5.94 5.00 5.85 5.67 5.88 6.04 6.22 6.79 6.38
[17:13:19.738] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1290 seconds
[17:13:19.738] <TB2> INFO: Decoding statistics:
[17:13:19.738] <TB2> INFO: General information:
[17:13:19.738] <TB2> INFO: 16bit words read: 0
[17:13:19.738] <TB2> INFO: valid events total: 0
[17:13:19.738] <TB2> INFO: empty events: 0
[17:13:19.738] <TB2> INFO: valid events with pixels: 0
[17:13:19.738] <TB2> INFO: valid pixel hits: 0
[17:13:19.738] <TB2> INFO: Event errors: 0
[17:13:19.738] <TB2> INFO: start marker: 0
[17:13:19.738] <TB2> INFO: stop marker: 0
[17:13:19.738] <TB2> INFO: overflow: 0
[17:13:19.738] <TB2> INFO: invalid 5bit words: 0
[17:13:19.738] <TB2> INFO: invalid XOR eye diagram: 0
[17:13:19.738] <TB2> INFO: frame (failed synchr.): 0
[17:13:19.738] <TB2> INFO: idle data (no TBM trl): 0
[17:13:19.738] <TB2> INFO: no data (only TBM hdr): 0
[17:13:19.738] <TB2> INFO: TBM errors: 0
[17:13:19.738] <TB2> INFO: flawed TBM headers: 0
[17:13:19.738] <TB2> INFO: flawed TBM trailers: 0
[17:13:19.738] <TB2> INFO: event ID mismatches: 0
[17:13:19.738] <TB2> INFO: ROC errors: 0
[17:13:19.738] <TB2> INFO: missing ROC header(s): 0
[17:13:19.738] <TB2> INFO: misplaced readback start: 0
[17:13:19.738] <TB2> INFO: Pixel decoding errors: 0
[17:13:19.738] <TB2> INFO: pixel data incomplete: 0
[17:13:19.739] <TB2> INFO: pixel address: 0
[17:13:19.739] <TB2> INFO: pulse height fill bit: 0
[17:13:19.739] <TB2> INFO: buffer corruption: 0
[17:13:19.805] <TB2> INFO: ######################################################################
[17:13:19.805] <TB2> INFO: PixTestTrim::doTest()
[17:13:19.805] <TB2> INFO: ######################################################################
[17:13:19.807] <TB2> INFO: ----------------------------------------------------------------------
[17:13:19.807] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[17:13:19.807] <TB2> INFO: ----------------------------------------------------------------------
[17:13:19.847] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[17:13:19.847] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:13:19.856] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:13:19.856] <TB2> INFO: run 1 of 1
[17:13:20.117] <TB2> INFO: Expecting 5025280 events.
[17:13:50.239] <TB2> INFO: 814344 events read in total (29526ms).
[17:14:20.077] <TB2> INFO: 1627016 events read in total (59364ms).
[17:14:49.712] <TB2> INFO: 2437536 events read in total (88999ms).
[17:15:18.883] <TB2> INFO: 3244664 events read in total (118170ms).
[17:15:48.368] <TB2> INFO: 4049192 events read in total (147656ms).
[17:16:17.779] <TB2> INFO: 4851616 events read in total (177066ms).
[17:16:24.446] <TB2> INFO: 5025280 events read in total (183733ms).
[17:16:24.507] <TB2> INFO: Test took 184651ms.
[17:16:44.816] <TB2> INFO: ROC 0 VthrComp = 114
[17:16:44.816] <TB2> INFO: ROC 1 VthrComp = 109
[17:16:44.816] <TB2> INFO: ROC 2 VthrComp = 127
[17:16:44.816] <TB2> INFO: ROC 3 VthrComp = 113
[17:16:44.817] <TB2> INFO: ROC 4 VthrComp = 129
[17:16:44.817] <TB2> INFO: ROC 5 VthrComp = 118
[17:16:44.817] <TB2> INFO: ROC 6 VthrComp = 108
[17:16:44.817] <TB2> INFO: ROC 7 VthrComp = 121
[17:16:44.817] <TB2> INFO: ROC 8 VthrComp = 106
[17:16:44.817] <TB2> INFO: ROC 9 VthrComp = 116
[17:16:44.817] <TB2> INFO: ROC 10 VthrComp = 114
[17:16:44.817] <TB2> INFO: ROC 11 VthrComp = 123
[17:16:44.817] <TB2> INFO: ROC 12 VthrComp = 113
[17:16:44.817] <TB2> INFO: ROC 13 VthrComp = 120
[17:16:44.817] <TB2> INFO: ROC 14 VthrComp = 103
[17:16:44.818] <TB2> INFO: ROC 15 VthrComp = 124
[17:16:45.073] <TB2> INFO: Expecting 41600 events.
[17:16:48.559] <TB2> INFO: 41600 events read in total (2895ms).
[17:16:48.559] <TB2> INFO: Test took 3740ms.
[17:16:48.568] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[17:16:48.568] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[17:16:48.577] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:16:48.577] <TB2> INFO: run 1 of 1
[17:16:48.855] <TB2> INFO: Expecting 5025280 events.
[17:17:15.251] <TB2> INFO: 591384 events read in total (25805ms).
[17:17:40.622] <TB2> INFO: 1181848 events read in total (51175ms).
[17:18:05.790] <TB2> INFO: 1772456 events read in total (76343ms).
[17:18:31.265] <TB2> INFO: 2361480 events read in total (101818ms).
[17:18:56.303] <TB2> INFO: 2949000 events read in total (126856ms).
[17:19:21.743] <TB2> INFO: 3534400 events read in total (152296ms).
[17:19:46.886] <TB2> INFO: 4118528 events read in total (177439ms).
[17:20:12.348] <TB2> INFO: 4702528 events read in total (202901ms).
[17:20:26.632] <TB2> INFO: 5025280 events read in total (217185ms).
[17:20:26.688] <TB2> INFO: Test took 218110ms.
[17:20:53.423] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 58.5212 for pixel 15/4 mean/min/max = 45.3229/31.9708/58.675
[17:20:53.423] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 60.1983 for pixel 33/8 mean/min/max = 47.5723/34.9065/60.2382
[17:20:53.424] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 61.9291 for pixel 11/1 mean/min/max = 46.5651/31.1229/62.0072
[17:20:53.424] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 60.5555 for pixel 0/32 mean/min/max = 46.4028/32.1888/60.6167
[17:20:53.424] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 61.0946 for pixel 8/17 mean/min/max = 46.4436/31.7004/61.1869
[17:20:53.425] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 60.0485 for pixel 21/4 mean/min/max = 45.8312/31.4389/60.2236
[17:20:53.425] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 60.2651 for pixel 50/17 mean/min/max = 47.5262/34.7751/60.2774
[17:20:53.426] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 61.5127 for pixel 1/37 mean/min/max = 46.377/31.2025/61.5515
[17:20:53.426] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 65.7625 for pixel 25/5 mean/min/max = 49.6486/33.4819/65.8154
[17:20:53.426] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 64.3617 for pixel 4/4 mean/min/max = 48.1292/31.4221/64.8363
[17:20:53.427] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 58.5132 for pixel 10/76 mean/min/max = 45.0215/31.5049/58.538
[17:20:53.427] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 60.8981 for pixel 14/14 mean/min/max = 45.8719/30.6322/61.1115
[17:20:53.427] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 61.4205 for pixel 21/78 mean/min/max = 46.4528/31.3957/61.5099
[17:20:53.428] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 60.8582 for pixel 45/10 mean/min/max = 46.0305/30.9363/61.1247
[17:20:53.428] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 63.7163 for pixel 11/4 mean/min/max = 48.25/32.576/63.9239
[17:20:53.429] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 60.5227 for pixel 0/4 mean/min/max = 45.4576/30.216/60.6992
[17:20:53.429] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:20:53.518] <TB2> INFO: Expecting 411648 events.
[17:21:02.757] <TB2> INFO: 411648 events read in total (8648ms).
[17:21:02.766] <TB2> INFO: Expecting 411648 events.
[17:21:11.763] <TB2> INFO: 411648 events read in total (8594ms).
[17:21:11.773] <TB2> INFO: Expecting 411648 events.
[17:21:20.758] <TB2> INFO: 411648 events read in total (8582ms).
[17:21:20.771] <TB2> INFO: Expecting 411648 events.
[17:21:29.779] <TB2> INFO: 411648 events read in total (8605ms).
[17:21:29.798] <TB2> INFO: Expecting 411648 events.
[17:21:38.896] <TB2> INFO: 411648 events read in total (8695ms).
[17:21:38.913] <TB2> INFO: Expecting 411648 events.
[17:21:47.906] <TB2> INFO: 411648 events read in total (8589ms).
[17:21:47.932] <TB2> INFO: Expecting 411648 events.
[17:21:57.026] <TB2> INFO: 411648 events read in total (8691ms).
[17:21:57.048] <TB2> INFO: Expecting 411648 events.
[17:22:06.068] <TB2> INFO: 411648 events read in total (8617ms).
[17:22:06.093] <TB2> INFO: Expecting 411648 events.
[17:22:15.148] <TB2> INFO: 411648 events read in total (8652ms).
[17:22:15.187] <TB2> INFO: Expecting 411648 events.
[17:22:24.291] <TB2> INFO: 411648 events read in total (8702ms).
[17:22:24.324] <TB2> INFO: Expecting 411648 events.
[17:22:33.281] <TB2> INFO: 411648 events read in total (8554ms).
[17:22:33.316] <TB2> INFO: Expecting 411648 events.
[17:22:42.344] <TB2> INFO: 411648 events read in total (8625ms).
[17:22:42.382] <TB2> INFO: Expecting 411648 events.
[17:22:51.439] <TB2> INFO: 411648 events read in total (8654ms).
[17:22:51.500] <TB2> INFO: Expecting 411648 events.
[17:23:00.604] <TB2> INFO: 411648 events read in total (8701ms).
[17:23:00.664] <TB2> INFO: Expecting 411648 events.
[17:23:09.700] <TB2> INFO: 411648 events read in total (8633ms).
[17:23:09.777] <TB2> INFO: Expecting 411648 events.
[17:23:18.841] <TB2> INFO: 411648 events read in total (8661ms).
[17:23:18.904] <TB2> INFO: Test took 145475ms.
[17:23:19.683] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[17:23:19.693] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:23:19.694] <TB2> INFO: run 1 of 1
[17:23:19.925] <TB2> INFO: Expecting 5025280 events.
[17:23:45.858] <TB2> INFO: 587040 events read in total (25341ms).
[17:24:11.296] <TB2> INFO: 1171240 events read in total (50779ms).
[17:24:37.078] <TB2> INFO: 1755936 events read in total (76561ms).
[17:25:02.660] <TB2> INFO: 2340216 events read in total (102143ms).
[17:25:28.270] <TB2> INFO: 2924584 events read in total (127753ms).
[17:25:54.013] <TB2> INFO: 3512032 events read in total (153496ms).
[17:26:19.670] <TB2> INFO: 4095648 events read in total (179153ms).
[17:26:45.405] <TB2> INFO: 4680128 events read in total (204888ms).
[17:27:00.428] <TB2> INFO: 5025280 events read in total (219911ms).
[17:27:00.550] <TB2> INFO: Test took 220857ms.
[17:27:23.759] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 7.878864 .. 147.541518
[17:27:23.992] <TB2> INFO: Expecting 208000 events.
[17:27:33.490] <TB2> INFO: 208000 events read in total (8906ms).
[17:27:33.492] <TB2> INFO: Test took 9731ms.
[17:27:33.537] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 7 .. 157 (-1/-1) hits flags = 528 (plus default)
[17:27:33.547] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:27:33.547] <TB2> INFO: run 1 of 1
[17:27:33.825] <TB2> INFO: Expecting 5025280 events.
[17:27:59.360] <TB2> INFO: 576592 events read in total (24943ms).
[17:28:24.442] <TB2> INFO: 1152832 events read in total (50026ms).
[17:28:49.898] <TB2> INFO: 1728656 events read in total (75481ms).
[17:29:15.114] <TB2> INFO: 2304640 events read in total (100697ms).
[17:29:40.438] <TB2> INFO: 2880504 events read in total (126021ms).
[17:30:05.365] <TB2> INFO: 3455552 events read in total (150948ms).
[17:30:30.640] <TB2> INFO: 4029344 events read in total (176223ms).
[17:30:55.662] <TB2> INFO: 4602856 events read in total (201245ms).
[17:31:14.540] <TB2> INFO: 5025280 events read in total (220123ms).
[17:31:14.644] <TB2> INFO: Test took 221098ms.
[17:31:41.765] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 26.534131 .. 90.294518
[17:31:41.999] <TB2> INFO: Expecting 208000 events.
[17:31:51.701] <TB2> INFO: 208000 events read in total (9110ms).
[17:31:51.702] <TB2> INFO: Test took 9935ms.
[17:31:51.766] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 100 (-1/-1) hits flags = 528 (plus default)
[17:31:51.777] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:31:51.777] <TB2> INFO: run 1 of 1
[17:31:52.079] <TB2> INFO: Expecting 2828800 events.
[17:32:17.860] <TB2> INFO: 586160 events read in total (25189ms).
[17:32:43.457] <TB2> INFO: 1172072 events read in total (50786ms).
[17:33:09.344] <TB2> INFO: 1757760 events read in total (76673ms).
[17:33:34.660] <TB2> INFO: 2342968 events read in total (101989ms).
[17:33:55.987] <TB2> INFO: 2828800 events read in total (123316ms).
[17:33:56.039] <TB2> INFO: Test took 124261ms.
[17:34:16.290] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 24.543199 .. 57.184183
[17:34:16.567] <TB2> INFO: Expecting 208000 events.
[17:34:26.607] <TB2> INFO: 208000 events read in total (9449ms).
[17:34:26.608] <TB2> INFO: Test took 10317ms.
[17:34:26.656] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 14 .. 67 (-1/-1) hits flags = 528 (plus default)
[17:34:26.665] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:34:26.665] <TB2> INFO: run 1 of 1
[17:34:26.943] <TB2> INFO: Expecting 1797120 events.
[17:34:53.763] <TB2> INFO: 634336 events read in total (26229ms).
[17:35:20.300] <TB2> INFO: 1267992 events read in total (52766ms).
[17:35:42.726] <TB2> INFO: 1797120 events read in total (75192ms).
[17:35:42.774] <TB2> INFO: Test took 76110ms.
[17:35:56.938] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 24.447040 .. 55.555943
[17:35:57.175] <TB2> INFO: Expecting 208000 events.
[17:36:06.825] <TB2> INFO: 208000 events read in total (9058ms).
[17:36:06.826] <TB2> INFO: Test took 9886ms.
[17:36:06.892] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 65 (-1/-1) hits flags = 528 (plus default)
[17:36:06.904] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:36:06.904] <TB2> INFO: run 1 of 1
[17:36:07.182] <TB2> INFO: Expecting 1730560 events.
[17:36:34.411] <TB2> INFO: 638368 events read in total (26638ms).
[17:37:01.105] <TB2> INFO: 1276048 events read in total (53332ms).
[17:37:20.140] <TB2> INFO: 1730560 events read in total (72367ms).
[17:37:20.177] <TB2> INFO: Test took 73274ms.
[17:37:34.769] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[17:37:34.769] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[17:37:34.780] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[17:37:34.780] <TB2> INFO: run 1 of 1
[17:37:35.017] <TB2> INFO: Expecting 1364480 events.
[17:38:02.819] <TB2> INFO: 666664 events read in total (27210ms).
[17:38:30.386] <TB2> INFO: 1332888 events read in total (54777ms).
[17:38:32.100] <TB2> INFO: 1364480 events read in total (56492ms).
[17:38:32.122] <TB2> INFO: Test took 57343ms.
[17:38:43.194] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C0.dat
[17:38:43.194] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C1.dat
[17:38:43.194] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C2.dat
[17:38:43.194] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C3.dat
[17:38:43.194] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C4.dat
[17:38:43.194] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C5.dat
[17:38:43.194] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C6.dat
[17:38:43.195] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C7.dat
[17:38:43.195] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C8.dat
[17:38:43.195] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C9.dat
[17:38:43.195] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C10.dat
[17:38:43.195] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C11.dat
[17:38:43.195] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C12.dat
[17:38:43.195] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C13.dat
[17:38:43.195] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C14.dat
[17:38:43.195] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C15.dat
[17:38:43.195] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters35_C0.dat
[17:38:43.201] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters35_C1.dat
[17:38:43.207] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters35_C2.dat
[17:38:43.212] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters35_C3.dat
[17:38:43.218] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters35_C4.dat
[17:38:43.225] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters35_C5.dat
[17:38:43.233] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters35_C6.dat
[17:38:43.240] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters35_C7.dat
[17:38:43.248] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters35_C8.dat
[17:38:43.255] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters35_C9.dat
[17:38:43.262] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters35_C10.dat
[17:38:43.269] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters35_C11.dat
[17:38:43.276] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters35_C12.dat
[17:38:43.284] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters35_C13.dat
[17:38:43.291] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters35_C14.dat
[17:38:43.298] <TB2> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//trimParameters35_C15.dat
[17:38:43.306] <TB2> INFO: PixTestTrim::trimTest() done
[17:38:43.306] <TB2> INFO: vtrim: 145 144 145 130 153 144 139 143 144 158 132 145 145 133 135 113
[17:38:43.306] <TB2> INFO: vthrcomp: 114 109 127 113 129 118 108 121 106 116 114 123 113 120 103 124
[17:38:43.306] <TB2> INFO: vcal mean: 34.98 34.99 34.95 34.96 34.97 34.93 35.00 35.00 34.99 35.02 35.02 34.99 34.95 34.97 35.15 34.91
[17:38:43.306] <TB2> INFO: vcal RMS: 1.23 1.00 1.18 1.30 1.23 1.16 1.00 1.09 1.13 1.21 0.99 1.16 1.10 1.13 1.03 1.13
[17:38:43.306] <TB2> INFO: bits mean: 9.76 9.32 9.99 9.40 10.29 10.26 9.40 9.94 9.16 9.63 10.16 10.29 9.93 10.08 9.05 10.08
[17:38:43.306] <TB2> INFO: bits RMS: 2.59 2.34 2.54 2.73 2.33 2.41 2.29 2.51 2.47 2.57 2.46 2.49 2.52 2.51 2.58 2.65
[17:38:43.313] <TB2> INFO: ----------------------------------------------------------------------
[17:38:43.313] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[17:38:43.313] <TB2> INFO: ----------------------------------------------------------------------
[17:38:43.315] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[17:38:43.324] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:38:43.324] <TB2> INFO: run 1 of 1
[17:38:43.555] <TB2> INFO: Expecting 4160000 events.
[17:39:15.157] <TB2> INFO: 734000 events read in total (31010ms).
[17:39:46.247] <TB2> INFO: 1465680 events read in total (62100ms).
[17:40:17.214] <TB2> INFO: 2192110 events read in total (93067ms).
[17:40:47.881] <TB2> INFO: 2915820 events read in total (123734ms).
[17:41:18.540] <TB2> INFO: 3637925 events read in total (154393ms).
[17:41:41.006] <TB2> INFO: 4160000 events read in total (176859ms).
[17:41:41.078] <TB2> INFO: Test took 177754ms.
[17:42:07.962] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 203 (-1/-1) hits flags = 528 (plus default)
[17:42:07.972] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:42:07.972] <TB2> INFO: run 1 of 1
[17:42:08.204] <TB2> INFO: Expecting 4243200 events.
[17:42:39.094] <TB2> INFO: 706595 events read in total (30299ms).
[17:43:09.223] <TB2> INFO: 1410630 events read in total (60428ms).
[17:43:39.356] <TB2> INFO: 2111455 events read in total (90561ms).
[17:44:09.361] <TB2> INFO: 2809080 events read in total (120566ms).
[17:44:39.824] <TB2> INFO: 3505520 events read in total (151029ms).
[17:45:10.198] <TB2> INFO: 4203405 events read in total (181403ms).
[17:45:12.361] <TB2> INFO: 4243200 events read in total (183566ms).
[17:45:12.484] <TB2> INFO: Test took 184512ms.
[17:45:40.343] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 186 (-1/-1) hits flags = 528 (plus default)
[17:45:40.354] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:45:40.354] <TB2> INFO: run 1 of 1
[17:45:40.626] <TB2> INFO: Expecting 3889600 events.
[17:46:12.041] <TB2> INFO: 728270 events read in total (30824ms).
[17:46:43.200] <TB2> INFO: 1453875 events read in total (61983ms).
[17:47:14.175] <TB2> INFO: 2174590 events read in total (92958ms).
[17:47:45.124] <TB2> INFO: 2892285 events read in total (123907ms).
[17:48:16.438] <TB2> INFO: 3609545 events read in total (155221ms).
[17:48:28.618] <TB2> INFO: 3889600 events read in total (167401ms).
[17:48:28.726] <TB2> INFO: Test took 168372ms.
[17:48:54.049] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 186 (-1/-1) hits flags = 528 (plus default)
[17:48:54.059] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:48:54.059] <TB2> INFO: run 1 of 1
[17:48:54.294] <TB2> INFO: Expecting 3889600 events.
[17:49:25.834] <TB2> INFO: 728825 events read in total (30948ms).
[17:49:57.506] <TB2> INFO: 1454880 events read in total (62620ms).
[17:50:28.069] <TB2> INFO: 2175905 events read in total (93183ms).
[17:50:58.784] <TB2> INFO: 2893990 events read in total (123898ms).
[17:51:29.710] <TB2> INFO: 3611780 events read in total (154824ms).
[17:51:42.021] <TB2> INFO: 3889600 events read in total (167135ms).
[17:51:42.136] <TB2> INFO: Test took 168076ms.
[17:52:07.019] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 185 (-1/-1) hits flags = 528 (plus default)
[17:52:07.030] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[17:52:07.030] <TB2> INFO: run 1 of 1
[17:52:07.298] <TB2> INFO: Expecting 3868800 events.
[17:52:38.875] <TB2> INFO: 730680 events read in total (30986ms).
[17:53:10.530] <TB2> INFO: 1458650 events read in total (62641ms).
[17:53:42.095] <TB2> INFO: 2181280 events read in total (94206ms).
[17:54:13.146] <TB2> INFO: 2901185 events read in total (125257ms).
[17:54:43.921] <TB2> INFO: 3620215 events read in total (156032ms).
[17:54:54.579] <TB2> INFO: 3868800 events read in total (166690ms).
[17:54:54.658] <TB2> INFO: Test took 167628ms.
[17:55:19.515] <TB2> INFO: PixTestTrim::trimBitTest() done
[17:55:19.517] <TB2> INFO: PixTestTrim::doTest() done, duration: 2519 seconds
[17:55:19.517] <TB2> INFO: Decoding statistics:
[17:55:19.517] <TB2> INFO: General information:
[17:55:19.517] <TB2> INFO: 16bit words read: 0
[17:55:19.517] <TB2> INFO: valid events total: 0
[17:55:19.517] <TB2> INFO: empty events: 0
[17:55:19.517] <TB2> INFO: valid events with pixels: 0
[17:55:19.517] <TB2> INFO: valid pixel hits: 0
[17:55:19.517] <TB2> INFO: Event errors: 0
[17:55:19.517] <TB2> INFO: start marker: 0
[17:55:19.517] <TB2> INFO: stop marker: 0
[17:55:19.517] <TB2> INFO: overflow: 0
[17:55:19.517] <TB2> INFO: invalid 5bit words: 0
[17:55:19.517] <TB2> INFO: invalid XOR eye diagram: 0
[17:55:19.517] <TB2> INFO: frame (failed synchr.): 0
[17:55:19.517] <TB2> INFO: idle data (no TBM trl): 0
[17:55:19.517] <TB2> INFO: no data (only TBM hdr): 0
[17:55:19.517] <TB2> INFO: TBM errors: 0
[17:55:19.517] <TB2> INFO: flawed TBM headers: 0
[17:55:19.517] <TB2> INFO: flawed TBM trailers: 0
[17:55:19.517] <TB2> INFO: event ID mismatches: 0
[17:55:19.517] <TB2> INFO: ROC errors: 0
[17:55:19.517] <TB2> INFO: missing ROC header(s): 0
[17:55:19.517] <TB2> INFO: misplaced readback start: 0
[17:55:19.517] <TB2> INFO: Pixel decoding errors: 0
[17:55:19.517] <TB2> INFO: pixel data incomplete: 0
[17:55:19.517] <TB2> INFO: pixel address: 0
[17:55:19.517] <TB2> INFO: pulse height fill bit: 0
[17:55:19.517] <TB2> INFO: buffer corruption: 0
[17:55:20.220] <TB2> INFO: ######################################################################
[17:55:20.220] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[17:55:20.220] <TB2> INFO: ######################################################################
[17:55:20.452] <TB2> INFO: Expecting 41600 events.
[17:55:24.071] <TB2> INFO: 41600 events read in total (3027ms).
[17:55:24.071] <TB2> INFO: Test took 3850ms.
[17:55:24.507] <TB2> INFO: Expecting 41600 events.
[17:55:28.088] <TB2> INFO: 41600 events read in total (2989ms).
[17:55:28.089] <TB2> INFO: Test took 3813ms.
[17:55:28.377] <TB2> INFO: Expecting 41600 events.
[17:55:31.860] <TB2> INFO: 41600 events read in total (2892ms).
[17:55:31.861] <TB2> INFO: Test took 3749ms.
[17:55:32.151] <TB2> INFO: Expecting 41600 events.
[17:55:35.605] <TB2> INFO: 41600 events read in total (2862ms).
[17:55:35.606] <TB2> INFO: Test took 3720ms.
[17:55:35.898] <TB2> INFO: Expecting 41600 events.
[17:55:39.408] <TB2> INFO: 41600 events read in total (2919ms).
[17:55:39.409] <TB2> INFO: Test took 3780ms.
[17:55:39.696] <TB2> INFO: Expecting 41600 events.
[17:55:43.183] <TB2> INFO: 41600 events read in total (2895ms).
[17:55:43.184] <TB2> INFO: Test took 3752ms.
[17:55:43.481] <TB2> INFO: Expecting 41600 events.
[17:55:46.992] <TB2> INFO: 41600 events read in total (2920ms).
[17:55:46.993] <TB2> INFO: Test took 3786ms.
[17:55:47.281] <TB2> INFO: Expecting 41600 events.
[17:55:50.872] <TB2> INFO: 41600 events read in total (2999ms).
[17:55:50.873] <TB2> INFO: Test took 3857ms.
[17:55:51.160] <TB2> INFO: Expecting 41600 events.
[17:55:54.708] <TB2> INFO: 41600 events read in total (2956ms).
[17:55:54.709] <TB2> INFO: Test took 3813ms.
[17:55:54.997] <TB2> INFO: Expecting 41600 events.
[17:55:58.506] <TB2> INFO: 41600 events read in total (2918ms).
[17:55:58.507] <TB2> INFO: Test took 3775ms.
[17:55:58.795] <TB2> INFO: Expecting 41600 events.
[17:56:02.304] <TB2> INFO: 41600 events read in total (2917ms).
[17:56:02.305] <TB2> INFO: Test took 3775ms.
[17:56:02.593] <TB2> INFO: Expecting 41600 events.
[17:56:06.087] <TB2> INFO: 41600 events read in total (2903ms).
[17:56:06.088] <TB2> INFO: Test took 3760ms.
[17:56:06.377] <TB2> INFO: Expecting 41600 events.
[17:56:09.917] <TB2> INFO: 41600 events read in total (2949ms).
[17:56:09.918] <TB2> INFO: Test took 3806ms.
[17:56:10.210] <TB2> INFO: Expecting 41600 events.
[17:56:13.776] <TB2> INFO: 41600 events read in total (2974ms).
[17:56:13.777] <TB2> INFO: Test took 3831ms.
[17:56:14.070] <TB2> INFO: Expecting 41600 events.
[17:56:17.502] <TB2> INFO: 41600 events read in total (2840ms).
[17:56:17.502] <TB2> INFO: Test took 3696ms.
[17:56:17.799] <TB2> INFO: Expecting 41600 events.
[17:56:21.308] <TB2> INFO: 41600 events read in total (2917ms).
[17:56:21.308] <TB2> INFO: Test took 3782ms.
[17:56:21.599] <TB2> INFO: Expecting 41600 events.
[17:56:25.215] <TB2> INFO: 41600 events read in total (3025ms).
[17:56:25.215] <TB2> INFO: Test took 3881ms.
[17:56:25.507] <TB2> INFO: Expecting 41600 events.
[17:56:28.999] <TB2> INFO: 41600 events read in total (2900ms).
[17:56:28.999] <TB2> INFO: Test took 3757ms.
[17:56:29.287] <TB2> INFO: Expecting 41600 events.
[17:56:32.840] <TB2> INFO: 41600 events read in total (2961ms).
[17:56:32.841] <TB2> INFO: Test took 3818ms.
[17:56:33.129] <TB2> INFO: Expecting 41600 events.
[17:56:36.768] <TB2> INFO: 41600 events read in total (3047ms).
[17:56:36.768] <TB2> INFO: Test took 3904ms.
[17:56:37.057] <TB2> INFO: Expecting 41600 events.
[17:56:40.541] <TB2> INFO: 41600 events read in total (2893ms).
[17:56:40.542] <TB2> INFO: Test took 3750ms.
[17:56:40.830] <TB2> INFO: Expecting 41600 events.
[17:56:44.267] <TB2> INFO: 41600 events read in total (2845ms).
[17:56:44.267] <TB2> INFO: Test took 3701ms.
[17:56:44.555] <TB2> INFO: Expecting 41600 events.
[17:56:48.094] <TB2> INFO: 41600 events read in total (2948ms).
[17:56:48.095] <TB2> INFO: Test took 3804ms.
[17:56:48.392] <TB2> INFO: Expecting 41600 events.
[17:56:51.891] <TB2> INFO: 41600 events read in total (2907ms).
[17:56:51.892] <TB2> INFO: Test took 3773ms.
[17:56:52.183] <TB2> INFO: Expecting 41600 events.
[17:56:55.656] <TB2> INFO: 41600 events read in total (2882ms).
[17:56:55.657] <TB2> INFO: Test took 3739ms.
[17:56:55.945] <TB2> INFO: Expecting 41600 events.
[17:56:59.442] <TB2> INFO: 41600 events read in total (2905ms).
[17:56:59.442] <TB2> INFO: Test took 3762ms.
[17:56:59.731] <TB2> INFO: Expecting 41600 events.
[17:57:03.165] <TB2> INFO: 41600 events read in total (2843ms).
[17:57:03.166] <TB2> INFO: Test took 3700ms.
[17:57:03.459] <TB2> INFO: Expecting 41600 events.
[17:57:07.009] <TB2> INFO: 41600 events read in total (2958ms).
[17:57:07.010] <TB2> INFO: Test took 3820ms.
[17:57:07.298] <TB2> INFO: Expecting 41600 events.
[17:57:10.839] <TB2> INFO: 41600 events read in total (2949ms).
[17:57:10.840] <TB2> INFO: Test took 3807ms.
[17:57:11.129] <TB2> INFO: Expecting 41600 events.
[17:57:14.703] <TB2> INFO: 41600 events read in total (2982ms).
[17:57:14.703] <TB2> INFO: Test took 3839ms.
[17:57:14.992] <TB2> INFO: Expecting 41600 events.
[17:57:18.547] <TB2> INFO: 41600 events read in total (2963ms).
[17:57:18.548] <TB2> INFO: Test took 3820ms.
[17:57:18.837] <TB2> INFO: Expecting 2560 events.
[17:57:19.721] <TB2> INFO: 2560 events read in total (292ms).
[17:57:19.721] <TB2> INFO: Test took 1161ms.
[17:57:20.029] <TB2> INFO: Expecting 2560 events.
[17:57:20.911] <TB2> INFO: 2560 events read in total (291ms).
[17:57:20.911] <TB2> INFO: Test took 1189ms.
[17:57:21.219] <TB2> INFO: Expecting 2560 events.
[17:57:22.101] <TB2> INFO: 2560 events read in total (291ms).
[17:57:22.101] <TB2> INFO: Test took 1190ms.
[17:57:22.409] <TB2> INFO: Expecting 2560 events.
[17:57:23.292] <TB2> INFO: 2560 events read in total (292ms).
[17:57:23.292] <TB2> INFO: Test took 1191ms.
[17:57:23.600] <TB2> INFO: Expecting 2560 events.
[17:57:24.479] <TB2> INFO: 2560 events read in total (288ms).
[17:57:24.480] <TB2> INFO: Test took 1188ms.
[17:57:24.788] <TB2> INFO: Expecting 2560 events.
[17:57:25.665] <TB2> INFO: 2560 events read in total (286ms).
[17:57:25.665] <TB2> INFO: Test took 1185ms.
[17:57:25.973] <TB2> INFO: Expecting 2560 events.
[17:57:26.852] <TB2> INFO: 2560 events read in total (287ms).
[17:57:26.853] <TB2> INFO: Test took 1187ms.
[17:57:27.160] <TB2> INFO: Expecting 2560 events.
[17:57:28.041] <TB2> INFO: 2560 events read in total (289ms).
[17:57:28.041] <TB2> INFO: Test took 1188ms.
[17:57:28.349] <TB2> INFO: Expecting 2560 events.
[17:57:29.228] <TB2> INFO: 2560 events read in total (288ms).
[17:57:29.228] <TB2> INFO: Test took 1186ms.
[17:57:29.536] <TB2> INFO: Expecting 2560 events.
[17:57:30.416] <TB2> INFO: 2560 events read in total (288ms).
[17:57:30.416] <TB2> INFO: Test took 1188ms.
[17:57:30.724] <TB2> INFO: Expecting 2560 events.
[17:57:31.606] <TB2> INFO: 2560 events read in total (290ms).
[17:57:31.607] <TB2> INFO: Test took 1191ms.
[17:57:31.914] <TB2> INFO: Expecting 2560 events.
[17:57:32.793] <TB2> INFO: 2560 events read in total (287ms).
[17:57:32.793] <TB2> INFO: Test took 1186ms.
[17:57:33.102] <TB2> INFO: Expecting 2560 events.
[17:57:33.986] <TB2> INFO: 2560 events read in total (293ms).
[17:57:33.986] <TB2> INFO: Test took 1192ms.
[17:57:34.294] <TB2> INFO: Expecting 2560 events.
[17:57:35.176] <TB2> INFO: 2560 events read in total (291ms).
[17:57:35.176] <TB2> INFO: Test took 1190ms.
[17:57:35.484] <TB2> INFO: Expecting 2560 events.
[17:57:36.372] <TB2> INFO: 2560 events read in total (296ms).
[17:57:36.372] <TB2> INFO: Test took 1195ms.
[17:57:36.680] <TB2> INFO: Expecting 2560 events.
[17:57:37.568] <TB2> INFO: 2560 events read in total (296ms).
[17:57:37.568] <TB2> INFO: Test took 1196ms.
[17:57:37.571] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:57:37.877] <TB2> INFO: Expecting 655360 events.
[17:57:52.106] <TB2> INFO: 655360 events read in total (13637ms).
[17:57:52.117] <TB2> INFO: Expecting 655360 events.
[17:58:06.308] <TB2> INFO: 655360 events read in total (13788ms).
[17:58:06.323] <TB2> INFO: Expecting 655360 events.
[17:58:20.330] <TB2> INFO: 655360 events read in total (13604ms).
[17:58:20.350] <TB2> INFO: Expecting 655360 events.
[17:58:34.446] <TB2> INFO: 655360 events read in total (13693ms).
[17:58:34.469] <TB2> INFO: Expecting 655360 events.
[17:58:48.810] <TB2> INFO: 655360 events read in total (13938ms).
[17:58:48.843] <TB2> INFO: Expecting 655360 events.
[17:59:03.301] <TB2> INFO: 655360 events read in total (14055ms).
[17:59:03.349] <TB2> INFO: Expecting 655360 events.
[17:59:17.483] <TB2> INFO: 655360 events read in total (13731ms).
[17:59:17.540] <TB2> INFO: Expecting 655360 events.
[17:59:31.678] <TB2> INFO: 655360 events read in total (13735ms).
[17:59:31.718] <TB2> INFO: Expecting 655360 events.
[17:59:45.865] <TB2> INFO: 655360 events read in total (13744ms).
[17:59:45.922] <TB2> INFO: Expecting 655360 events.
[17:59:59.990] <TB2> INFO: 655360 events read in total (13666ms).
[18:00:00.037] <TB2> INFO: Expecting 655360 events.
[18:00:14.295] <TB2> INFO: 655360 events read in total (13855ms).
[18:00:14.390] <TB2> INFO: Expecting 655360 events.
[18:00:28.476] <TB2> INFO: 655360 events read in total (13683ms).
[18:00:28.570] <TB2> INFO: Expecting 655360 events.
[18:00:42.752] <TB2> INFO: 655360 events read in total (13779ms).
[18:00:42.855] <TB2> INFO: Expecting 655360 events.
[18:00:56.897] <TB2> INFO: 655360 events read in total (13639ms).
[18:00:57.027] <TB2> INFO: Expecting 655360 events.
[18:01:11.153] <TB2> INFO: 655360 events read in total (13723ms).
[18:01:11.274] <TB2> INFO: Expecting 655360 events.
[18:01:25.405] <TB2> INFO: 655360 events read in total (13728ms).
[18:01:25.541] <TB2> INFO: Test took 227970ms.
[18:01:25.635] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:01:25.898] <TB2> INFO: Expecting 655360 events.
[18:01:40.137] <TB2> INFO: 655360 events read in total (13648ms).
[18:01:40.148] <TB2> INFO: Expecting 655360 events.
[18:01:54.134] <TB2> INFO: 655360 events read in total (13583ms).
[18:01:54.149] <TB2> INFO: Expecting 655360 events.
[18:02:08.077] <TB2> INFO: 655360 events read in total (13525ms).
[18:02:08.102] <TB2> INFO: Expecting 655360 events.
[18:02:22.220] <TB2> INFO: 655360 events read in total (13715ms).
[18:02:22.243] <TB2> INFO: Expecting 655360 events.
[18:02:36.133] <TB2> INFO: 655360 events read in total (13487ms).
[18:02:36.160] <TB2> INFO: Expecting 655360 events.
[18:02:49.813] <TB2> INFO: 655360 events read in total (13250ms).
[18:02:49.856] <TB2> INFO: Expecting 655360 events.
[18:03:03.652] <TB2> INFO: 655360 events read in total (13394ms).
[18:03:03.688] <TB2> INFO: Expecting 655360 events.
[18:03:17.537] <TB2> INFO: 655360 events read in total (13446ms).
[18:03:17.576] <TB2> INFO: Expecting 655360 events.
[18:03:31.510] <TB2> INFO: 655360 events read in total (13531ms).
[18:03:31.552] <TB2> INFO: Expecting 655360 events.
[18:03:45.676] <TB2> INFO: 655360 events read in total (13721ms).
[18:03:45.722] <TB2> INFO: Expecting 655360 events.
[18:03:59.926] <TB2> INFO: 655360 events read in total (13801ms).
[18:03:59.979] <TB2> INFO: Expecting 655360 events.
[18:04:13.958] <TB2> INFO: 655360 events read in total (13576ms).
[18:04:14.034] <TB2> INFO: Expecting 655360 events.
[18:04:28.150] <TB2> INFO: 655360 events read in total (13713ms).
[18:04:28.212] <TB2> INFO: Expecting 655360 events.
[18:04:42.234] <TB2> INFO: 655360 events read in total (13619ms).
[18:04:42.299] <TB2> INFO: Expecting 655360 events.
[18:04:56.423] <TB2> INFO: 655360 events read in total (13721ms).
[18:04:56.491] <TB2> INFO: Expecting 655360 events.
[18:05:10.645] <TB2> INFO: 655360 events read in total (13751ms).
[18:05:10.737] <TB2> INFO: Test took 225102ms.
[18:05:10.966] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:05:10.974] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:05:10.980] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:05:10.986] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:05:10.993] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:05:10.999] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:05:11.006] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:05:11.013] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[18:05:11.020] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[18:05:11.027] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:05:11.034] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:05:11.040] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:05:11.046] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:05:11.053] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:05:11.059] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:05:11.066] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[18:05:11.073] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[18:05:11.080] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[18:05:11.086] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[18:05:11.092] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[18:05:11.098] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:05:11.105] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:05:11.111] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[18:05:11.117] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[18:05:11.123] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[18:05:11.129] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[18:05:11.135] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[18:05:11.142] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[18:05:11.148] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:05:11.155] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:05:11.161] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:05:11.167] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[18:05:11.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C0.dat
[18:05:11.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C1.dat
[18:05:11.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C2.dat
[18:05:11.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C3.dat
[18:05:11.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C4.dat
[18:05:11.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C5.dat
[18:05:11.202] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C6.dat
[18:05:11.203] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C7.dat
[18:05:11.203] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C8.dat
[18:05:11.203] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C9.dat
[18:05:11.203] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C10.dat
[18:05:11.203] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C11.dat
[18:05:11.203] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C12.dat
[18:05:11.203] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C13.dat
[18:05:11.203] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C14.dat
[18:05:11.203] <TB2> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//dacParameters35_C15.dat
[18:05:11.440] <TB2> INFO: Expecting 41600 events.
[18:05:14.525] <TB2> INFO: 41600 events read in total (2494ms).
[18:05:14.526] <TB2> INFO: Test took 3319ms.
[18:05:14.980] <TB2> INFO: Expecting 41600 events.
[18:05:18.003] <TB2> INFO: 41600 events read in total (2431ms).
[18:05:18.004] <TB2> INFO: Test took 3269ms.
[18:05:18.446] <TB2> INFO: Expecting 41600 events.
[18:05:21.587] <TB2> INFO: 41600 events read in total (2550ms).
[18:05:21.588] <TB2> INFO: Test took 3373ms.
[18:05:21.806] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:21.895] <TB2> INFO: Expecting 2560 events.
[18:05:22.777] <TB2> INFO: 2560 events read in total (291ms).
[18:05:22.777] <TB2> INFO: Test took 971ms.
[18:05:22.779] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:23.085] <TB2> INFO: Expecting 2560 events.
[18:05:23.972] <TB2> INFO: 2560 events read in total (295ms).
[18:05:23.972] <TB2> INFO: Test took 1193ms.
[18:05:23.974] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:24.280] <TB2> INFO: Expecting 2560 events.
[18:05:25.168] <TB2> INFO: 2560 events read in total (296ms).
[18:05:25.168] <TB2> INFO: Test took 1194ms.
[18:05:25.170] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:25.476] <TB2> INFO: Expecting 2560 events.
[18:05:26.359] <TB2> INFO: 2560 events read in total (291ms).
[18:05:26.360] <TB2> INFO: Test took 1190ms.
[18:05:26.361] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:26.668] <TB2> INFO: Expecting 2560 events.
[18:05:27.556] <TB2> INFO: 2560 events read in total (297ms).
[18:05:27.556] <TB2> INFO: Test took 1195ms.
[18:05:27.558] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:27.865] <TB2> INFO: Expecting 2560 events.
[18:05:28.748] <TB2> INFO: 2560 events read in total (292ms).
[18:05:28.748] <TB2> INFO: Test took 1190ms.
[18:05:28.750] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:29.056] <TB2> INFO: Expecting 2560 events.
[18:05:29.942] <TB2> INFO: 2560 events read in total (294ms).
[18:05:29.943] <TB2> INFO: Test took 1193ms.
[18:05:29.944] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:30.251] <TB2> INFO: Expecting 2560 events.
[18:05:31.133] <TB2> INFO: 2560 events read in total (291ms).
[18:05:31.134] <TB2> INFO: Test took 1190ms.
[18:05:31.135] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:31.442] <TB2> INFO: Expecting 2560 events.
[18:05:32.322] <TB2> INFO: 2560 events read in total (288ms).
[18:05:32.323] <TB2> INFO: Test took 1188ms.
[18:05:32.325] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:32.631] <TB2> INFO: Expecting 2560 events.
[18:05:33.510] <TB2> INFO: 2560 events read in total (288ms).
[18:05:33.510] <TB2> INFO: Test took 1186ms.
[18:05:33.512] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:33.818] <TB2> INFO: Expecting 2560 events.
[18:05:34.696] <TB2> INFO: 2560 events read in total (286ms).
[18:05:34.696] <TB2> INFO: Test took 1184ms.
[18:05:34.698] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:35.005] <TB2> INFO: Expecting 2560 events.
[18:05:35.885] <TB2> INFO: 2560 events read in total (289ms).
[18:05:35.885] <TB2> INFO: Test took 1187ms.
[18:05:35.887] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:36.193] <TB2> INFO: Expecting 2560 events.
[18:05:37.072] <TB2> INFO: 2560 events read in total (287ms).
[18:05:37.072] <TB2> INFO: Test took 1185ms.
[18:05:37.074] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:37.381] <TB2> INFO: Expecting 2560 events.
[18:05:38.258] <TB2> INFO: 2560 events read in total (285ms).
[18:05:38.258] <TB2> INFO: Test took 1184ms.
[18:05:38.260] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:38.567] <TB2> INFO: Expecting 2560 events.
[18:05:39.445] <TB2> INFO: 2560 events read in total (287ms).
[18:05:39.445] <TB2> INFO: Test took 1185ms.
[18:05:39.447] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:39.760] <TB2> INFO: Expecting 2560 events.
[18:05:40.638] <TB2> INFO: 2560 events read in total (287ms).
[18:05:40.638] <TB2> INFO: Test took 1191ms.
[18:05:40.640] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:40.947] <TB2> INFO: Expecting 2560 events.
[18:05:41.828] <TB2> INFO: 2560 events read in total (290ms).
[18:05:41.829] <TB2> INFO: Test took 1189ms.
[18:05:41.830] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:42.137] <TB2> INFO: Expecting 2560 events.
[18:05:43.015] <TB2> INFO: 2560 events read in total (287ms).
[18:05:43.015] <TB2> INFO: Test took 1185ms.
[18:05:43.017] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:43.323] <TB2> INFO: Expecting 2560 events.
[18:05:44.200] <TB2> INFO: 2560 events read in total (285ms).
[18:05:44.201] <TB2> INFO: Test took 1184ms.
[18:05:44.203] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:44.509] <TB2> INFO: Expecting 2560 events.
[18:05:45.388] <TB2> INFO: 2560 events read in total (287ms).
[18:05:45.388] <TB2> INFO: Test took 1186ms.
[18:05:45.390] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:45.696] <TB2> INFO: Expecting 2560 events.
[18:05:46.576] <TB2> INFO: 2560 events read in total (288ms).
[18:05:46.576] <TB2> INFO: Test took 1186ms.
[18:05:46.578] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:46.884] <TB2> INFO: Expecting 2560 events.
[18:05:47.763] <TB2> INFO: 2560 events read in total (287ms).
[18:05:47.763] <TB2> INFO: Test took 1185ms.
[18:05:47.765] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:48.072] <TB2> INFO: Expecting 2560 events.
[18:05:48.953] <TB2> INFO: 2560 events read in total (290ms).
[18:05:48.953] <TB2> INFO: Test took 1188ms.
[18:05:48.956] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:49.262] <TB2> INFO: Expecting 2560 events.
[18:05:50.141] <TB2> INFO: 2560 events read in total (288ms).
[18:05:50.141] <TB2> INFO: Test took 1185ms.
[18:05:50.143] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:50.450] <TB2> INFO: Expecting 2560 events.
[18:05:51.332] <TB2> INFO: 2560 events read in total (290ms).
[18:05:51.332] <TB2> INFO: Test took 1189ms.
[18:05:51.334] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:51.641] <TB2> INFO: Expecting 2560 events.
[18:05:52.528] <TB2> INFO: 2560 events read in total (295ms).
[18:05:52.528] <TB2> INFO: Test took 1194ms.
[18:05:52.530] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:52.836] <TB2> INFO: Expecting 2560 events.
[18:05:53.720] <TB2> INFO: 2560 events read in total (292ms).
[18:05:53.721] <TB2> INFO: Test took 1191ms.
[18:05:53.723] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:54.029] <TB2> INFO: Expecting 2560 events.
[18:05:54.910] <TB2> INFO: 2560 events read in total (290ms).
[18:05:54.911] <TB2> INFO: Test took 1188ms.
[18:05:54.913] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:55.219] <TB2> INFO: Expecting 2560 events.
[18:05:56.102] <TB2> INFO: 2560 events read in total (291ms).
[18:05:56.102] <TB2> INFO: Test took 1190ms.
[18:05:56.104] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:56.410] <TB2> INFO: Expecting 2560 events.
[18:05:57.293] <TB2> INFO: 2560 events read in total (291ms).
[18:05:57.293] <TB2> INFO: Test took 1189ms.
[18:05:57.295] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:57.601] <TB2> INFO: Expecting 2560 events.
[18:05:58.485] <TB2> INFO: 2560 events read in total (292ms).
[18:05:58.485] <TB2> INFO: Test took 1190ms.
[18:05:58.487] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[18:05:58.793] <TB2> INFO: Expecting 2560 events.
[18:05:59.677] <TB2> INFO: 2560 events read in total (292ms).
[18:05:59.677] <TB2> INFO: Test took 1190ms.
[18:06:00.141] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 639 seconds
[18:06:00.141] <TB2> INFO: PH scale (per ROC): 62 59 62 59 49 60 42 49 47 47 53 48 53 50 59 44
[18:06:00.141] <TB2> INFO: PH offset (per ROC): 122 129 105 103 105 127 93 102 100 107 102 106 97 105 121 99
[18:06:00.146] <TB2> INFO: Decoding statistics:
[18:06:00.146] <TB2> INFO: General information:
[18:06:00.146] <TB2> INFO: 16bit words read: 127884
[18:06:00.146] <TB2> INFO: valid events total: 20480
[18:06:00.146] <TB2> INFO: empty events: 17978
[18:06:00.146] <TB2> INFO: valid events with pixels: 2502
[18:06:00.146] <TB2> INFO: valid pixel hits: 2502
[18:06:00.146] <TB2> INFO: Event errors: 0
[18:06:00.146] <TB2> INFO: start marker: 0
[18:06:00.146] <TB2> INFO: stop marker: 0
[18:06:00.146] <TB2> INFO: overflow: 0
[18:06:00.146] <TB2> INFO: invalid 5bit words: 0
[18:06:00.146] <TB2> INFO: invalid XOR eye diagram: 0
[18:06:00.146] <TB2> INFO: frame (failed synchr.): 0
[18:06:00.146] <TB2> INFO: idle data (no TBM trl): 0
[18:06:00.146] <TB2> INFO: no data (only TBM hdr): 0
[18:06:00.146] <TB2> INFO: TBM errors: 0
[18:06:00.146] <TB2> INFO: flawed TBM headers: 0
[18:06:00.146] <TB2> INFO: flawed TBM trailers: 0
[18:06:00.146] <TB2> INFO: event ID mismatches: 0
[18:06:00.146] <TB2> INFO: ROC errors: 0
[18:06:00.146] <TB2> INFO: missing ROC header(s): 0
[18:06:00.146] <TB2> INFO: misplaced readback start: 0
[18:06:00.146] <TB2> INFO: Pixel decoding errors: 0
[18:06:00.146] <TB2> INFO: pixel data incomplete: 0
[18:06:00.146] <TB2> INFO: pixel address: 0
[18:06:00.146] <TB2> INFO: pulse height fill bit: 0
[18:06:00.146] <TB2> INFO: buffer corruption: 0
[18:06:00.405] <TB2> INFO: ######################################################################
[18:06:00.405] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[18:06:00.405] <TB2> INFO: ######################################################################
[18:06:00.417] <TB2> INFO: scanning low vcal = 10
[18:06:00.649] <TB2> INFO: Expecting 41600 events.
[18:06:04.227] <TB2> INFO: 41600 events read in total (2986ms).
[18:06:04.228] <TB2> INFO: Test took 3811ms.
[18:06:04.229] <TB2> INFO: scanning low vcal = 20
[18:06:04.529] <TB2> INFO: Expecting 41600 events.
[18:06:08.071] <TB2> INFO: 41600 events read in total (2951ms).
[18:06:08.072] <TB2> INFO: Test took 3842ms.
[18:06:08.073] <TB2> INFO: scanning low vcal = 30
[18:06:08.372] <TB2> INFO: Expecting 41600 events.
[18:06:11.993] <TB2> INFO: 41600 events read in total (3029ms).
[18:06:11.993] <TB2> INFO: Test took 3919ms.
[18:06:11.996] <TB2> INFO: scanning low vcal = 40
[18:06:12.274] <TB2> INFO: Expecting 41600 events.
[18:06:16.225] <TB2> INFO: 41600 events read in total (3359ms).
[18:06:16.226] <TB2> INFO: Test took 4230ms.
[18:06:16.229] <TB2> INFO: scanning low vcal = 50
[18:06:16.505] <TB2> INFO: Expecting 41600 events.
[18:06:20.478] <TB2> INFO: 41600 events read in total (3381ms).
[18:06:20.478] <TB2> INFO: Test took 4249ms.
[18:06:20.481] <TB2> INFO: scanning low vcal = 60
[18:06:20.758] <TB2> INFO: Expecting 41600 events.
[18:06:24.816] <TB2> INFO: 41600 events read in total (3467ms).
[18:06:24.817] <TB2> INFO: Test took 4336ms.
[18:06:24.819] <TB2> INFO: scanning low vcal = 70
[18:06:25.096] <TB2> INFO: Expecting 41600 events.
[18:06:29.083] <TB2> INFO: 41600 events read in total (3395ms).
[18:06:29.084] <TB2> INFO: Test took 4264ms.
[18:06:29.086] <TB2> INFO: scanning low vcal = 80
[18:06:29.363] <TB2> INFO: Expecting 41600 events.
[18:06:33.299] <TB2> INFO: 41600 events read in total (3344ms).
[18:06:33.299] <TB2> INFO: Test took 4212ms.
[18:06:33.302] <TB2> INFO: scanning low vcal = 90
[18:06:33.579] <TB2> INFO: Expecting 41600 events.
[18:06:37.512] <TB2> INFO: 41600 events read in total (3342ms).
[18:06:37.513] <TB2> INFO: Test took 4211ms.
[18:06:37.516] <TB2> INFO: scanning low vcal = 100
[18:06:37.792] <TB2> INFO: Expecting 41600 events.
[18:06:41.752] <TB2> INFO: 41600 events read in total (3368ms).
[18:06:41.753] <TB2> INFO: Test took 4237ms.
[18:06:41.755] <TB2> INFO: scanning low vcal = 110
[18:06:42.032] <TB2> INFO: Expecting 41600 events.
[18:06:46.066] <TB2> INFO: 41600 events read in total (3442ms).
[18:06:46.067] <TB2> INFO: Test took 4311ms.
[18:06:46.070] <TB2> INFO: scanning low vcal = 120
[18:06:46.346] <TB2> INFO: Expecting 41600 events.
[18:06:50.288] <TB2> INFO: 41600 events read in total (3350ms).
[18:06:50.289] <TB2> INFO: Test took 4219ms.
[18:06:50.292] <TB2> INFO: scanning low vcal = 130
[18:06:50.569] <TB2> INFO: Expecting 41600 events.
[18:06:54.571] <TB2> INFO: 41600 events read in total (3411ms).
[18:06:54.571] <TB2> INFO: Test took 4279ms.
[18:06:54.574] <TB2> INFO: scanning low vcal = 140
[18:06:54.851] <TB2> INFO: Expecting 41600 events.
[18:06:58.869] <TB2> INFO: 41600 events read in total (3427ms).
[18:06:58.870] <TB2> INFO: Test took 4296ms.
[18:06:58.872] <TB2> INFO: scanning low vcal = 150
[18:06:59.149] <TB2> INFO: Expecting 41600 events.
[18:07:03.175] <TB2> INFO: 41600 events read in total (3434ms).
[18:07:03.176] <TB2> INFO: Test took 4304ms.
[18:07:03.178] <TB2> INFO: scanning low vcal = 160
[18:07:03.455] <TB2> INFO: Expecting 41600 events.
[18:07:07.406] <TB2> INFO: 41600 events read in total (3359ms).
[18:07:07.407] <TB2> INFO: Test took 4229ms.
[18:07:07.410] <TB2> INFO: scanning low vcal = 170
[18:07:07.717] <TB2> INFO: Expecting 41600 events.
[18:07:11.705] <TB2> INFO: 41600 events read in total (3396ms).
[18:07:11.706] <TB2> INFO: Test took 4296ms.
[18:07:11.708] <TB2> INFO: scanning low vcal = 180
[18:07:11.985] <TB2> INFO: Expecting 41600 events.
[18:07:15.961] <TB2> INFO: 41600 events read in total (3385ms).
[18:07:15.961] <TB2> INFO: Test took 4253ms.
[18:07:15.964] <TB2> INFO: scanning low vcal = 190
[18:07:16.240] <TB2> INFO: Expecting 41600 events.
[18:07:20.347] <TB2> INFO: 41600 events read in total (3515ms).
[18:07:20.348] <TB2> INFO: Test took 4384ms.
[18:07:20.350] <TB2> INFO: scanning low vcal = 200
[18:07:20.662] <TB2> INFO: Expecting 41600 events.
[18:07:24.612] <TB2> INFO: 41600 events read in total (3358ms).
[18:07:24.613] <TB2> INFO: Test took 4263ms.
[18:07:24.615] <TB2> INFO: scanning low vcal = 210
[18:07:24.892] <TB2> INFO: Expecting 41600 events.
[18:07:28.903] <TB2> INFO: 41600 events read in total (3419ms).
[18:07:28.904] <TB2> INFO: Test took 4289ms.
[18:07:28.907] <TB2> INFO: scanning low vcal = 220
[18:07:29.217] <TB2> INFO: Expecting 41600 events.
[18:07:33.268] <TB2> INFO: 41600 events read in total (3460ms).
[18:07:33.269] <TB2> INFO: Test took 4362ms.
[18:07:33.272] <TB2> INFO: scanning low vcal = 230
[18:07:33.580] <TB2> INFO: Expecting 41600 events.
[18:07:37.573] <TB2> INFO: 41600 events read in total (3401ms).
[18:07:37.574] <TB2> INFO: Test took 4302ms.
[18:07:37.576] <TB2> INFO: scanning low vcal = 240
[18:07:37.887] <TB2> INFO: Expecting 41600 events.
[18:07:41.863] <TB2> INFO: 41600 events read in total (3385ms).
[18:07:41.863] <TB2> INFO: Test took 4287ms.
[18:07:41.866] <TB2> INFO: scanning low vcal = 250
[18:07:42.159] <TB2> INFO: Expecting 41600 events.
[18:07:46.149] <TB2> INFO: 41600 events read in total (3398ms).
[18:07:46.150] <TB2> INFO: Test took 4284ms.
[18:07:46.153] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[18:07:46.429] <TB2> INFO: Expecting 41600 events.
[18:07:50.440] <TB2> INFO: 41600 events read in total (3419ms).
[18:07:50.441] <TB2> INFO: Test took 4287ms.
[18:07:50.443] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[18:07:50.720] <TB2> INFO: Expecting 41600 events.
[18:07:54.759] <TB2> INFO: 41600 events read in total (3447ms).
[18:07:54.760] <TB2> INFO: Test took 4317ms.
[18:07:54.763] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[18:07:55.076] <TB2> INFO: Expecting 41600 events.
[18:07:59.029] <TB2> INFO: 41600 events read in total (3362ms).
[18:07:59.029] <TB2> INFO: Test took 4266ms.
[18:07:59.032] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[18:07:59.309] <TB2> INFO: Expecting 41600 events.
[18:08:03.289] <TB2> INFO: 41600 events read in total (3389ms).
[18:08:03.289] <TB2> INFO: Test took 4257ms.
[18:08:03.292] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[18:08:03.568] <TB2> INFO: Expecting 41600 events.
[18:08:07.564] <TB2> INFO: 41600 events read in total (3404ms).
[18:08:07.565] <TB2> INFO: Test took 4273ms.
[18:08:08.252] <TB2> INFO: PixTestGainPedestal::measure() done
[18:08:52.682] <TB2> INFO: PixTestGainPedestal::fit() done
[18:08:52.682] <TB2> INFO: non-linearity mean: 0.977 0.983 0.976 0.967 0.971 0.970 0.942 0.961 0.925 0.927 0.958 0.912 0.936 0.942 0.987 0.917
[18:08:52.682] <TB2> INFO: non-linearity RMS: 0.005 0.004 0.008 0.025 0.016 0.015 0.155 0.032 0.115 0.095 0.038 0.098 0.142 0.075 0.002 0.094
[18:08:52.682] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr35_C0.dat
[18:08:52.697] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr35_C1.dat
[18:08:52.712] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr35_C2.dat
[18:08:52.726] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr35_C3.dat
[18:08:52.741] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr35_C4.dat
[18:08:52.755] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr35_C5.dat
[18:08:52.778] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr35_C6.dat
[18:08:52.801] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr35_C7.dat
[18:08:52.824] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr35_C8.dat
[18:08:52.847] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr35_C9.dat
[18:08:52.871] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr35_C10.dat
[18:08:52.894] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr35_C11.dat
[18:08:52.917] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr35_C12.dat
[18:08:52.941] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr35_C13.dat
[18:08:52.964] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr35_C14.dat
[18:08:52.982] <TB2> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1002_FullQualification_2016-11-04_10h05m_1478250315//001_Fulltest_m20//phCalibrationFitErr35_C15.dat
[18:08:52.996] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 172 seconds
[18:08:52.996] <TB2> INFO: Decoding statistics:
[18:08:52.996] <TB2> INFO: General information:
[18:08:52.996] <TB2> INFO: 16bit words read: 3327822
[18:08:52.996] <TB2> INFO: valid events total: 332800
[18:08:52.996] <TB2> INFO: empty events: 0
[18:08:52.996] <TB2> INFO: valid events with pixels: 332800
[18:08:52.996] <TB2> INFO: valid pixel hits: 665511
[18:08:52.996] <TB2> INFO: Event errors: 0
[18:08:52.996] <TB2> INFO: start marker: 0
[18:08:52.996] <TB2> INFO: stop marker: 0
[18:08:52.996] <TB2> INFO: overflow: 0
[18:08:52.996] <TB2> INFO: invalid 5bit words: 0
[18:08:52.996] <TB2> INFO: invalid XOR eye diagram: 0
[18:08:52.996] <TB2> INFO: frame (failed synchr.): 0
[18:08:52.996] <TB2> INFO: idle data (no TBM trl): 0
[18:08:52.996] <TB2> INFO: no data (only TBM hdr): 0
[18:08:52.996] <TB2> INFO: TBM errors: 0
[18:08:52.996] <TB2> INFO: flawed TBM headers: 0
[18:08:52.996] <TB2> INFO: flawed TBM trailers: 0
[18:08:52.996] <TB2> INFO: event ID mismatches: 0
[18:08:52.996] <TB2> INFO: ROC errors: 0
[18:08:52.996] <TB2> INFO: missing ROC header(s): 0
[18:08:52.996] <TB2> INFO: misplaced readback start: 0
[18:08:52.996] <TB2> INFO: Pixel decoding errors: 0
[18:08:52.996] <TB2> INFO: pixel data incomplete: 0
[18:08:52.996] <TB2> INFO: pixel address: 0
[18:08:52.996] <TB2> INFO: pulse height fill bit: 0
[18:08:52.996] <TB2> INFO: buffer corruption: 0
[18:08:53.010] <TB2> INFO: Decoding statistics:
[18:08:53.010] <TB2> INFO: General information:
[18:08:53.010] <TB2> INFO: 16bit words read: 3457242
[18:08:53.010] <TB2> INFO: valid events total: 353536
[18:08:53.010] <TB2> INFO: empty events: 18234
[18:08:53.010] <TB2> INFO: valid events with pixels: 335302
[18:08:53.010] <TB2> INFO: valid pixel hits: 668013
[18:08:53.010] <TB2> INFO: Event errors: 0
[18:08:53.010] <TB2> INFO: start marker: 0
[18:08:53.010] <TB2> INFO: stop marker: 0
[18:08:53.010] <TB2> INFO: overflow: 0
[18:08:53.010] <TB2> INFO: invalid 5bit words: 0
[18:08:53.010] <TB2> INFO: invalid XOR eye diagram: 0
[18:08:53.010] <TB2> INFO: frame (failed synchr.): 0
[18:08:53.010] <TB2> INFO: idle data (no TBM trl): 0
[18:08:53.010] <TB2> INFO: no data (only TBM hdr): 0
[18:08:53.010] <TB2> INFO: TBM errors: 0
[18:08:53.010] <TB2> INFO: flawed TBM headers: 0
[18:08:53.010] <TB2> INFO: flawed TBM trailers: 0
[18:08:53.010] <TB2> INFO: event ID mismatches: 0
[18:08:53.010] <TB2> INFO: ROC errors: 0
[18:08:53.010] <TB2> INFO: missing ROC header(s): 0
[18:08:53.010] <TB2> INFO: misplaced readback start: 0
[18:08:53.010] <TB2> INFO: Pixel decoding errors: 0
[18:08:53.010] <TB2> INFO: pixel data incomplete: 0
[18:08:53.010] <TB2> INFO: pixel address: 0
[18:08:53.010] <TB2> INFO: pulse height fill bit: 0
[18:08:53.010] <TB2> INFO: buffer corruption: 0
[18:08:53.010] <TB2> INFO: enter test to run
[18:08:53.010] <TB2> INFO: test: exit no parameter change
[18:08:53.047] <TB2> QUIET: Connection to board 156 closed.
[18:08:53.048] <TB2> INFO: pXar: this is the end, my friend