[08:30:40.862] <TB2> INFO: *** Welcome to pxar ***
[08:30:40.862] <TB2> INFO: *** Today: 2016/06/08
[08:30:41.079] <TB2> INFO: *** Version: 9751-dirty
[08:30:41.079] <TB2> INFO: readRocDacs: /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C0.dat .. /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C15.dat
[08:30:41.094] <TB2> INFO: readTbmDacs: /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//tbmParameters_C0a.dat .. /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//tbmParameters_C0b.dat
[08:30:41.096] <TB2> INFO: readMaskFile: /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//defaultMaskFile.dat
[08:30:41.097] <TB2> INFO: readTrimFile: /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters_C0.dat .. /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters_C15.dat
[08:30:41.200] <TB2> INFO: clk: 4
[08:30:41.200] <TB2> INFO: ctr: 4
[08:30:41.200] <TB2> INFO: sda: 19
[08:30:41.200] <TB2> INFO: tin: 9
[08:30:41.200] <TB2> INFO: level: 15
[08:30:41.200] <TB2> INFO: triggerdelay: 0
[08:30:41.200] <TB2> QUIET: Instanciating API for pxar v2.7.5+40~g4fce89b
[08:30:41.200] <TB2> INFO: Log level: INFO
[08:30:41.206] <TB2> INFO: Found DTB DTB_WWXUD2
[08:30:41.217] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[08:30:41.219] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.4
SW version: 4.6
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[08:30:41.221] <TB2> INFO: RPC call hashes of host and DTB match: 484264910
[08:30:42.742] <TB2> INFO: DUT info:
[08:30:42.742] <TB2> INFO: The DUT currently contains the following objects:
[08:30:42.742] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[08:30:42.742] <TB2> INFO: TBM Core alpha (0): 7 registers set
[08:30:42.742] <TB2> INFO: TBM Core beta (1): 7 registers set
[08:30:42.742] <TB2> INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[08:30:42.742] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[08:30:42.742] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[08:30:42.742] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[08:30:42.742] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[08:30:42.742] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[08:30:42.742] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[08:30:42.742] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[08:30:42.742] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[08:30:42.742] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[08:30:42.742] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[08:30:42.742] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[08:30:42.742] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[08:30:42.742] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[08:30:42.742] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[08:30:42.742] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[08:30:42.742] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[08:30:43.144] <TB2> INFO: enter 'restricted' command line mode
[08:30:43.145] <TB2> INFO: enter test to run
[08:30:43.145] <TB2> INFO: test: pretest no parameter change
[08:30:43.145] <TB2> INFO: running: pretest
[08:30:43.149] <TB2> INFO: ----------------------------------------------------------------------
[08:30:43.149] <TB2> INFO: PixTestPretest::programROC()
[08:30:43.149] <TB2> INFO: ----------------------------------------------------------------------
[08:31:01.167] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[08:31:01.167] <TB2> INFO: IA differences per ROC: 19.3 21.7 20.1 20.1 19.3 19.3 17.7 19.3 20.9 18.5 20.1 20.1 21.7 18.5 20.9 20.1
[08:31:01.283] <TB2> INFO: enter test to run
[08:31:01.283] <TB2> INFO: test: pretest no parameter change
[08:31:01.283] <TB2> INFO: running: pretest
[08:31:01.284] <TB2> INFO: ----------------------------------------------------------------------
[08:31:01.284] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[08:31:01.284] <TB2> INFO: ----------------------------------------------------------------------
[08:31:22.590] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 383.5 mA = 23.9688 mA/ROC
[08:31:22.591] <TB2> INFO: i(loss) [mA/ROC]: 19.3 20.1 18.5 19.3 20.1 20.1 19.3 19.3 20.1 19.3 18.5 19.3 19.3 19.3 17.7 19.3
[08:31:22.636] <TB2> INFO: enter test to run
[08:31:22.636] <TB2> INFO: test: pretest no parameter change
[08:31:22.636] <TB2> INFO: running: pretest
[08:31:22.636] <TB2> INFO: ----------------------------------------------------------------------
[08:31:22.636] <TB2> INFO: PixTestPretest::findTiming()
[08:31:22.636] <TB2> INFO: ----------------------------------------------------------------------
[08:31:22.637] <TB2> INFO: PixTestCmd::init()
[08:31:23.167] <TB2> WARNING: Not unmasking DUT, not setting Calibrate bits!
[08:32:52.951] <TB2> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[08:32:52.951] <TB2> INFO: (success/tries = 100/100), width = 4
[08:32:52.952] <TB2> INFO: enter test to run
[08:32:52.952] <TB2> INFO: test: pretest no parameter change
[08:32:52.953] <TB2> INFO: running: pretest
[08:32:52.954] <TB2> INFO: ----------------------------------------------------------------------
[08:32:52.954] <TB2> INFO: PixTestPretest::findWorkingPixel()
[08:32:52.954] <TB2> INFO: ----------------------------------------------------------------------
[08:32:53.050] <TB2> INFO: Expecting 231680 events.
[08:32:58.827] <TB2> ERROR: <datapipe.cc/CheckEventValidity:L507> Channel 0 Number of ROCs (1) != Token Chain Length (4)
[08:32:58.908] <TB2> ERROR: <datapipe.cc/CheckEventID:L469> Channel 0 Event ID mismatch: local ID (21) != TBM ID (2)
[08:33:03.183] <TB2> INFO: 231680 events read in total (9576ms).
[08:33:03.188] <TB2> INFO: Test took 10228ms.
[08:33:03.415] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[08:33:03.499] <TB2> INFO: enter test to run
[08:33:03.499] <TB2> INFO: test: pretest no parameter change
[08:33:03.499] <TB2> INFO: running: pretest
[08:33:03.500] <TB2> INFO: ----------------------------------------------------------------------
[08:33:03.500] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[08:33:03.500] <TB2> INFO: ----------------------------------------------------------------------
[08:33:03.596] <TB2> INFO: Expecting 231680 events.
[08:33:13.743] <TB2> INFO: 231680 events read in total (9590ms).
[08:33:13.747] <TB2> INFO: Test took 10241ms.
[08:33:14.018] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[08:33:14.018] <TB2> INFO: CalDel: 123 131 143 136 120 136 121 136 143 123 144 156 160 143 151 143
[08:33:14.018] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[08:33:14.052] <TB2> INFO: enter test to run
[08:33:14.052] <TB2> INFO: test: pretest no parameter change
[08:33:14.052] <TB2> INFO: running: pretest
[08:33:14.081] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C0.dat
[08:33:14.157] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C1.dat
[08:33:14.241] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C2.dat
[08:33:14.316] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C3.dat
[08:33:14.391] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C4.dat
[08:33:14.475] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C5.dat
[08:33:14.550] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C6.dat
[08:33:14.617] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C7.dat
[08:33:14.693] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C8.dat
[08:33:14.760] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C9.dat
[08:33:14.827] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C10.dat
[08:33:14.952] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C11.dat
[08:33:15.061] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C12.dat
[08:33:15.163] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C13.dat
[08:33:15.230] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C14.dat
[08:33:15.305] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters_C15.dat
[08:33:15.347] <TB2> INFO: enter test to run
[08:33:15.347] <TB2> INFO: test: fulltest no parameter change
[08:33:15.348] <TB2> INFO: running: fulltest
[08:33:15.348] <TB2> INFO: ######################################################################
[08:33:15.348] <TB2> INFO: PixTestFullTest::doTest()
[08:33:15.348] <TB2> INFO: ######################################################################
[08:33:15.349] <TB2> INFO: ######################################################################
[08:33:15.349] <TB2> INFO: PixTestAlive::doTest()
[08:33:15.349] <TB2> INFO: ######################################################################
[08:33:15.350] <TB2> INFO: ----------------------------------------------------------------------
[08:33:15.350] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:33:15.350] <TB2> INFO: ----------------------------------------------------------------------
[08:33:15.648] <TB2> INFO: Expecting 41600 events.
[08:33:19.380] <TB2> INFO: 41600 events read in total (3175ms).
[08:33:19.381] <TB2> INFO: Test took 4029ms.
[08:33:19.629] <TB2> INFO: PixTestAlive::aliveTest() done
[08:33:19.629] <TB2> INFO: number of dead pixels (per ROC): 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0
[08:33:19.631] <TB2> INFO: ----------------------------------------------------------------------
[08:33:19.631] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:33:19.631] <TB2> INFO: ----------------------------------------------------------------------
[08:33:19.894] <TB2> INFO: Expecting 41600 events.
[08:33:22.853] <TB2> INFO: 41600 events read in total (2402ms).
[08:33:22.854] <TB2> INFO: Test took 3221ms.
[08:33:22.854] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[08:33:23.116] <TB2> INFO: PixTestAlive::maskTest() done
[08:33:23.116] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[08:33:23.117] <TB2> INFO: ----------------------------------------------------------------------
[08:33:23.117] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:33:23.117] <TB2> INFO: ----------------------------------------------------------------------
[08:33:23.381] <TB2> INFO: Expecting 41600 events.
[08:33:27.116] <TB2> INFO: 41600 events read in total (3178ms).
[08:33:27.116] <TB2> INFO: Test took 3996ms.
[08:33:27.365] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[08:33:27.365] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[08:33:27.365] <TB2> INFO: PixTestAlive::doTest() done, duration: 12 seconds
[08:33:27.365] <TB2> INFO: Decoding statistics:
[08:33:27.365] <TB2> INFO: General information:
[08:33:27.365] <TB2> INFO: 16bit words read: 0
[08:33:27.365] <TB2> INFO: valid events total: 0
[08:33:27.365] <TB2> INFO: empty events: 0
[08:33:27.365] <TB2> INFO: valid events with pixels: 0
[08:33:27.365] <TB2> INFO: valid pixel hits: 0
[08:33:27.365] <TB2> INFO: Event errors: 0
[08:33:27.365] <TB2> INFO: start marker: 0
[08:33:27.365] <TB2> INFO: stop marker: 0
[08:33:27.365] <TB2> INFO: overflow: 0
[08:33:27.365] <TB2> INFO: invalid 5bit words: 0
[08:33:27.365] <TB2> INFO: invalid XOR eye diagram: 0
[08:33:27.365] <TB2> INFO: frame (failed synchr.): 0
[08:33:27.365] <TB2> INFO: idle data (no TBM trl): 0
[08:33:27.365] <TB2> INFO: no data (only TBM hdr): 0
[08:33:27.365] <TB2> INFO: TBM errors: 0
[08:33:27.365] <TB2> INFO: flawed TBM headers: 0
[08:33:27.365] <TB2> INFO: flawed TBM trailers: 0
[08:33:27.365] <TB2> INFO: event ID mismatches: 0
[08:33:27.365] <TB2> INFO: ROC errors: 0
[08:33:27.365] <TB2> INFO: missing ROC header(s): 0
[08:33:27.365] <TB2> INFO: misplaced readback start: 0
[08:33:27.365] <TB2> INFO: Pixel decoding errors: 0
[08:33:27.365] <TB2> INFO: pixel data incomplete: 0
[08:33:27.365] <TB2> INFO: pixel address: 0
[08:33:27.365] <TB2> INFO: pulse height fill bit: 0
[08:33:27.365] <TB2> INFO: buffer corruption: 0
[08:33:27.372] <TB2> INFO: ######################################################################
[08:33:27.372] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[08:33:27.372] <TB2> INFO: ######################################################################
[08:33:27.376] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[08:33:27.387] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[08:33:27.387] <TB2> INFO: run 1 of 1
[08:33:27.649] <TB2> INFO: Expecting 3120000 events.
[08:34:09.116] <TB2> INFO: 868035 events read in total (40910ms).
[08:34:49.230] <TB2> INFO: 1726705 events read in total (81025ms).
[08:35:29.961] <TB2> INFO: 2599265 events read in total (121756ms).
[08:35:54.647] <TB2> INFO: 3120000 events read in total (146441ms).
[08:35:54.693] <TB2> INFO: Test took 147306ms.
[08:36:17.051] <TB2> INFO: PixTestBBMap::doTest() done, duration: 169 seconds
[08:36:17.052] <TB2> INFO: number of dead bumps (per ROC): 0 2 6 4 3 4 6 2 0 0 0 0 0 1 0 1
[08:36:17.052] <TB2> INFO: separation cut (per ROC): 91 86 81 93 95 85 84 93 85 88 85 89 89 79 95 97
[08:36:17.052] <TB2> INFO: Decoding statistics:
[08:36:17.052] <TB2> INFO: General information:
[08:36:17.052] <TB2> INFO: 16bit words read: 0
[08:36:17.052] <TB2> INFO: valid events total: 0
[08:36:17.052] <TB2> INFO: empty events: 0
[08:36:17.052] <TB2> INFO: valid events with pixels: 0
[08:36:17.052] <TB2> INFO: valid pixel hits: 0
[08:36:17.052] <TB2> INFO: Event errors: 0
[08:36:17.052] <TB2> INFO: start marker: 0
[08:36:17.052] <TB2> INFO: stop marker: 0
[08:36:17.052] <TB2> INFO: overflow: 0
[08:36:17.052] <TB2> INFO: invalid 5bit words: 0
[08:36:17.052] <TB2> INFO: invalid XOR eye diagram: 0
[08:36:17.052] <TB2> INFO: frame (failed synchr.): 0
[08:36:17.052] <TB2> INFO: idle data (no TBM trl): 0
[08:36:17.052] <TB2> INFO: no data (only TBM hdr): 0
[08:36:17.052] <TB2> INFO: TBM errors: 0
[08:36:17.052] <TB2> INFO: flawed TBM headers: 0
[08:36:17.052] <TB2> INFO: flawed TBM trailers: 0
[08:36:17.052] <TB2> INFO: event ID mismatches: 0
[08:36:17.052] <TB2> INFO: ROC errors: 0
[08:36:17.052] <TB2> INFO: missing ROC header(s): 0
[08:36:17.052] <TB2> INFO: misplaced readback start: 0
[08:36:17.052] <TB2> INFO: Pixel decoding errors: 0
[08:36:17.052] <TB2> INFO: pixel data incomplete: 0
[08:36:17.052] <TB2> INFO: pixel address: 0
[08:36:17.052] <TB2> INFO: pulse height fill bit: 0
[08:36:17.052] <TB2> INFO: buffer corruption: 0
[08:36:17.121] <TB2> INFO: ######################################################################
[08:36:17.121] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[08:36:17.121] <TB2> INFO: ######################################################################
[08:36:17.121] <TB2> INFO: ----------------------------------------------------------------------
[08:36:17.121] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[08:36:17.121] <TB2> INFO: ----------------------------------------------------------------------
[08:36:17.121] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 150 (-1/-1) hits flags = 528 (plus default)
[08:36:17.129] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[08:36:17.129] <TB2> INFO: run 1 of 1
[08:36:17.389] <TB2> INFO: Expecting 26208000 events.
[08:36:51.318] <TB2> INFO: 928400 events read in total (33372ms).
[08:37:24.623] <TB2> INFO: 1840300 events read in total (66677ms).
[08:37:57.357] <TB2> INFO: 2751600 events read in total (99411ms).
[08:38:30.837] <TB2> INFO: 3662400 events read in total (132891ms).
[08:39:04.477] <TB2> INFO: 4573350 events read in total (166531ms).
[08:39:37.793] <TB2> INFO: 5480300 events read in total (199847ms).
[08:40:11.117] <TB2> INFO: 6388650 events read in total (233171ms).
[08:40:44.056] <TB2> INFO: 7296950 events read in total (266110ms).
[08:41:17.593] <TB2> INFO: 8205850 events read in total (299647ms).
[08:41:50.563] <TB2> INFO: 9115050 events read in total (332617ms).
[08:42:23.345] <TB2> INFO: 10020650 events read in total (365399ms).
[08:42:56.670] <TB2> INFO: 10928250 events read in total (398724ms).
[08:43:30.335] <TB2> INFO: 11834250 events read in total (432389ms).
[08:44:03.463] <TB2> INFO: 12739000 events read in total (465517ms).
[08:44:36.220] <TB2> INFO: 13637100 events read in total (498274ms).
[08:45:09.377] <TB2> INFO: 14531600 events read in total (531431ms).
[08:45:43.085] <TB2> INFO: 15426050 events read in total (565139ms).
[08:46:16.210] <TB2> INFO: 16318150 events read in total (598264ms).
[08:46:48.946] <TB2> INFO: 17210600 events read in total (631000ms).
[08:47:21.981] <TB2> INFO: 18101650 events read in total (664035ms).
[08:47:55.375] <TB2> INFO: 18992750 events read in total (697429ms).
[08:48:28.722] <TB2> INFO: 19882550 events read in total (730776ms).
[08:49:01.211] <TB2> INFO: 20774400 events read in total (763265ms).
[08:49:34.183] <TB2> INFO: 21665200 events read in total (796237ms).
[08:50:07.815] <TB2> INFO: 22553900 events read in total (829869ms).
[08:50:41.227] <TB2> INFO: 23448000 events read in total (863281ms).
[08:51:14.740] <TB2> INFO: 24343200 events read in total (896794ms).
[08:51:47.894] <TB2> INFO: 25241250 events read in total (929948ms).
[08:52:21.263] <TB2> INFO: 26155500 events read in total (963317ms).
[08:52:23.560] <TB2> INFO: 26208000 events read in total (965614ms).
[08:52:23.588] <TB2> INFO: Test took 966459ms.
[08:52:23.814] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[08:52:25.281] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[08:52:26.752] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[08:52:28.356] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[08:52:29.862] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[08:52:31.435] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[08:52:32.937] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[08:52:34.400] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[08:52:35.866] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[08:52:37.362] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[08:52:38.911] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[08:52:40.475] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[08:52:41.931] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[08:52:43.421] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[08:52:44.954] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[08:52:46.448] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[08:52:47.928] <TB2> INFO: PixTestScurves::scurves() done
[08:52:47.928] <TB2> INFO: Vcal mean: 95.09 89.93 85.27 95.03 102.88 92.97 86.95 98.59 98.97 97.69 95.14 97.52 89.21 89.37 97.88 98.57
[08:52:47.928] <TB2> INFO: Vcal RMS: 5.32 4.88 5.19 5.47 4.91 5.38 4.71 5.59 5.05 5.50 5.00 5.30 5.53 5.43 6.22 5.17
[08:52:47.928] <TB2> INFO: PixTestScurves::fullTest() done, duration: 990 seconds
[08:52:47.928] <TB2> INFO: Decoding statistics:
[08:52:47.928] <TB2> INFO: General information:
[08:52:47.928] <TB2> INFO: 16bit words read: 0
[08:52:47.928] <TB2> INFO: valid events total: 0
[08:52:47.928] <TB2> INFO: empty events: 0
[08:52:47.928] <TB2> INFO: valid events with pixels: 0
[08:52:47.928] <TB2> INFO: valid pixel hits: 0
[08:52:47.928] <TB2> INFO: Event errors: 0
[08:52:47.928] <TB2> INFO: start marker: 0
[08:52:47.928] <TB2> INFO: stop marker: 0
[08:52:47.928] <TB2> INFO: overflow: 0
[08:52:47.928] <TB2> INFO: invalid 5bit words: 0
[08:52:47.928] <TB2> INFO: invalid XOR eye diagram: 0
[08:52:47.928] <TB2> INFO: frame (failed synchr.): 0
[08:52:47.928] <TB2> INFO: idle data (no TBM trl): 0
[08:52:47.928] <TB2> INFO: no data (only TBM hdr): 0
[08:52:47.928] <TB2> INFO: TBM errors: 0
[08:52:47.928] <TB2> INFO: flawed TBM headers: 0
[08:52:47.928] <TB2> INFO: flawed TBM trailers: 0
[08:52:47.928] <TB2> INFO: event ID mismatches: 0
[08:52:47.928] <TB2> INFO: ROC errors: 0
[08:52:47.928] <TB2> INFO: missing ROC header(s): 0
[08:52:47.928] <TB2> INFO: misplaced readback start: 0
[08:52:47.929] <TB2> INFO: Pixel decoding errors: 0
[08:52:47.929] <TB2> INFO: pixel data incomplete: 0
[08:52:47.929] <TB2> INFO: pixel address: 0
[08:52:47.929] <TB2> INFO: pulse height fill bit: 0
[08:52:47.929] <TB2> INFO: buffer corruption: 0
[08:52:48.007] <TB2> INFO: ######################################################################
[08:52:48.007] <TB2> INFO: PixTestTrim::doTest()
[08:52:48.007] <TB2> INFO: ######################################################################
[08:52:48.008] <TB2> INFO: ----------------------------------------------------------------------
[08:52:48.008] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[08:52:48.008] <TB2> INFO: ----------------------------------------------------------------------
[08:52:48.089] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[08:52:48.089] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[08:52:48.097] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[08:52:48.097] <TB2> INFO: run 1 of 1
[08:52:48.366] <TB2> INFO: Expecting 5025280 events.
[08:53:30.150] <TB2> INFO: 1091776 events read in total (41227ms).
[08:54:10.707] <TB2> INFO: 2178040 events read in total (81784ms).
[08:54:51.963] <TB2> INFO: 3264744 events read in total (123040ms).
[08:55:32.370] <TB2> INFO: 4358864 events read in total (163447ms).
[08:55:57.477] <TB2> INFO: 5025280 events read in total (188554ms).
[08:55:57.509] <TB2> INFO: Test took 189412ms.
[08:56:17.119] <TB2> INFO: ROC 0 VthrComp = 95
[08:56:17.119] <TB2> INFO: ROC 1 VthrComp = 95
[08:56:17.119] <TB2> INFO: ROC 2 VthrComp = 87
[08:56:17.120] <TB2> INFO: ROC 3 VthrComp = 97
[08:56:17.120] <TB2> INFO: ROC 4 VthrComp = 104
[08:56:17.120] <TB2> INFO: ROC 5 VthrComp = 93
[08:56:17.120] <TB2> INFO: ROC 6 VthrComp = 89
[08:56:17.120] <TB2> INFO: ROC 7 VthrComp = 98
[08:56:17.120] <TB2> INFO: ROC 8 VthrComp = 98
[08:56:17.120] <TB2> INFO: ROC 9 VthrComp = 94
[08:56:17.121] <TB2> INFO: ROC 10 VthrComp = 91
[08:56:17.121] <TB2> INFO: ROC 11 VthrComp = 95
[08:56:17.121] <TB2> INFO: ROC 12 VthrComp = 92
[08:56:17.121] <TB2> INFO: ROC 13 VthrComp = 86
[08:56:17.121] <TB2> INFO: ROC 14 VthrComp = 93
[08:56:17.121] <TB2> INFO: ROC 15 VthrComp = 97
[08:56:17.121] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[08:56:17.121] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[08:56:17.129] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[08:56:17.129] <TB2> INFO: run 1 of 1
[08:56:17.394] <TB2> INFO: Expecting 5025280 events.
[08:56:53.593] <TB2> INFO: 754184 events read in total (35642ms).
[08:57:28.779] <TB2> INFO: 1507208 events read in total (70828ms).
[08:58:04.526] <TB2> INFO: 2261256 events read in total (106575ms).
[08:58:40.651] <TB2> INFO: 3011256 events read in total (142700ms).
[08:59:16.416] <TB2> INFO: 3756128 events read in total (178465ms).
[08:59:52.692] <TB2> INFO: 4499592 events read in total (214741ms).
[09:00:18.214] <TB2> INFO: 5025280 events read in total (240263ms).
[09:00:18.267] <TB2> INFO: Test took 241137ms.
[09:00:42.702] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 57.1091 for pixel 7/79 mean/min/max = 44.7469/32.293/57.2009
[09:00:42.702] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 56.2723 for pixel 23/1 mean/min/max = 44.6349/32.9659/56.3039
[09:00:42.702] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 56.6615 for pixel 0/23 mean/min/max = 44.4295/31.9639/56.8951
[09:00:42.703] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 57.7254 for pixel 16/31 mean/min/max = 44.7073/31.5793/57.8352
[09:00:42.703] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 57.5992 for pixel 23/1 mean/min/max = 45.995/34.1488/57.8412
[09:00:42.703] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 58.8062 for pixel 22/1 mean/min/max = 46.1174/33.3653/58.8694
[09:00:42.703] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 56.6854 for pixel 9/4 mean/min/max = 45.2111/33.6721/56.75
[09:00:42.704] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 58.2241 for pixel 9/79 mean/min/max = 44.8821/31.4272/58.337
[09:00:42.704] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 57.5013 for pixel 1/4 mean/min/max = 45.0785/32.5961/57.5608
[09:00:42.704] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 60.2279 for pixel 11/1 mean/min/max = 46.8355/33.3197/60.3513
[09:00:42.704] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 59.2994 for pixel 23/1 mean/min/max = 46.6362/33.9372/59.3352
[09:00:42.705] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 59.6692 for pixel 21/19 mean/min/max = 46.1551/32.6224/59.6879
[09:00:42.705] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 57.7776 for pixel 10/79 mean/min/max = 45.5839/33.1537/58.0141
[09:00:42.705] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 59.6513 for pixel 0/79 mean/min/max = 46.3079/32.8192/59.7966
[09:00:42.705] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 61.7365 for pixel 18/7 mean/min/max = 47.0941/32.299/61.8891
[09:00:42.706] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 58.6402 for pixel 0/9 mean/min/max = 45.6991/32.3644/59.0337
[09:00:42.706] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:00:42.796] <TB2> INFO: Expecting 411648 events.
[09:00:53.234] <TB2> INFO: 411648 events read in total (9882ms).
[09:00:53.238] <TB2> INFO: Expecting 411648 events.
[09:01:03.687] <TB2> INFO: 411648 events read in total (10012ms).
[09:01:03.694] <TB2> INFO: Expecting 411648 events.
[09:01:14.140] <TB2> INFO: 411648 events read in total (10024ms).
[09:01:14.148] <TB2> INFO: Expecting 411648 events.
[09:01:24.701] <TB2> INFO: 411648 events read in total (10124ms).
[09:01:24.711] <TB2> INFO: Expecting 411648 events.
[09:01:35.251] <TB2> INFO: 411648 events read in total (10120ms).
[09:01:35.264] <TB2> INFO: Expecting 411648 events.
[09:01:45.706] <TB2> INFO: 411648 events read in total (10025ms).
[09:01:45.723] <TB2> INFO: Expecting 411648 events.
[09:01:56.159] <TB2> INFO: 411648 events read in total (10023ms).
[09:01:56.174] <TB2> INFO: Expecting 411648 events.
[09:02:06.497] <TB2> INFO: 411648 events read in total (9910ms).
[09:02:06.515] <TB2> INFO: Expecting 411648 events.
[09:02:16.851] <TB2> INFO: 411648 events read in total (9917ms).
[09:02:16.871] <TB2> INFO: Expecting 411648 events.
[09:02:27.458] <TB2> INFO: 411648 events read in total (10169ms).
[09:02:27.480] <TB2> INFO: Expecting 411648 events.
[09:02:37.944] <TB2> INFO: 411648 events read in total (10051ms).
[09:02:37.970] <TB2> INFO: Expecting 411648 events.
[09:02:48.372] <TB2> INFO: 411648 events read in total (9995ms).
[09:02:48.396] <TB2> INFO: Expecting 411648 events.
[09:02:58.745] <TB2> INFO: 411648 events read in total (9937ms).
[09:02:58.770] <TB2> INFO: Expecting 411648 events.
[09:03:09.023] <TB2> INFO: 411648 events read in total (9841ms).
[09:03:09.052] <TB2> INFO: Expecting 411648 events.
[09:03:19.558] <TB2> INFO: 411648 events read in total (10093ms).
[09:03:19.587] <TB2> INFO: Expecting 411648 events.
[09:03:29.907] <TB2> INFO: 411648 events read in total (9913ms).
[09:03:29.939] <TB2> INFO: Test took 167233ms.
[09:03:30.823] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[09:03:30.831] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[09:03:30.831] <TB2> INFO: run 1 of 1
[09:03:31.096] <TB2> INFO: Expecting 5025280 events.
[09:04:07.153] <TB2> INFO: 742096 events read in total (35500ms).
[09:04:42.735] <TB2> INFO: 1483104 events read in total (71082ms).
[09:05:18.255] <TB2> INFO: 2225072 events read in total (106602ms).
[09:05:53.771] <TB2> INFO: 2962944 events read in total (142118ms).
[09:06:29.270] <TB2> INFO: 3694624 events read in total (177617ms).
[09:07:04.343] <TB2> INFO: 4423416 events read in total (212690ms).
[09:07:33.356] <TB2> INFO: 5025280 events read in total (241703ms).
[09:07:33.401] <TB2> INFO: Test took 242570ms.
[09:07:58.352] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 9.025750 .. 255.000000
[09:07:58.448] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 9 .. 255 (-1/-1) hits flags = 528 (plus default)
[09:07:58.456] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[09:07:58.456] <TB2> INFO: run 1 of 1
[09:07:58.739] <TB2> INFO: Expecting 8220160 events.
[09:08:33.828] <TB2> INFO: 700872 events read in total (34532ms).
[09:09:08.750] <TB2> INFO: 1401952 events read in total (69454ms).
[09:09:43.744] <TB2> INFO: 2103104 events read in total (104448ms).
[09:10:18.320] <TB2> INFO: 2804272 events read in total (139024ms).
[09:10:53.085] <TB2> INFO: 3505560 events read in total (173789ms).
[09:11:27.885] <TB2> INFO: 4206536 events read in total (208589ms).
[09:12:02.239] <TB2> INFO: 4907320 events read in total (242943ms).
[09:12:37.160] <TB2> INFO: 5607272 events read in total (277864ms).
[09:13:11.900] <TB2> INFO: 6306672 events read in total (312604ms).
[09:13:47.023] <TB2> INFO: 7005768 events read in total (347727ms).
[09:14:21.784] <TB2> INFO: 7704800 events read in total (382488ms).
[09:14:47.833] <TB2> INFO: 8220160 events read in total (408537ms).
[09:14:47.914] <TB2> INFO: Test took 409458ms.
[09:15:17.739] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 15.497681 .. 116.821416
[09:15:17.815] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 5 .. 126 (-1/-1) hits flags = 528 (plus default)
[09:15:17.823] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[09:15:17.823] <TB2> INFO: run 1 of 1
[09:15:18.085] <TB2> INFO: Expecting 4060160 events.
[09:15:54.823] <TB2> INFO: 756552 events read in total (36181ms).
[09:16:30.643] <TB2> INFO: 1513208 events read in total (72001ms).
[09:17:06.289] <TB2> INFO: 2269688 events read in total (107647ms).
[09:17:42.169] <TB2> INFO: 3025400 events read in total (143527ms).
[09:18:18.036] <TB2> INFO: 3780928 events read in total (179394ms).
[09:18:31.318] <TB2> INFO: 4060160 events read in total (192676ms).
[09:18:31.350] <TB2> INFO: Test took 193527ms.
[09:18:52.882] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 20.874398 .. 43.683957
[09:18:52.964] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 10 .. 53 (-1/-1) hits flags = 528 (plus default)
[09:18:52.972] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[09:18:52.972] <TB2> INFO: run 1 of 1
[09:18:53.238] <TB2> INFO: Expecting 1464320 events.
[09:19:32.751] <TB2> INFO: 927456 events read in total (38956ms).
[09:19:55.337] <TB2> INFO: 1464320 events read in total (61542ms).
[09:19:55.347] <TB2> INFO: Test took 62374ms.
[09:20:08.402] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 23.522676 .. 43.683957
[09:20:08.477] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 13 .. 53 (-1/-1) hits flags = 528 (plus default)
[09:20:08.485] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[09:20:08.485] <TB2> INFO: run 1 of 1
[09:20:08.745] <TB2> INFO: Expecting 1364480 events.
[09:20:48.694] <TB2> INFO: 907704 events read in total (39391ms).
[09:21:08.827] <TB2> INFO: 1364480 events read in total (59525ms).
[09:21:08.844] <TB2> INFO: Test took 60359ms.
[09:21:22.061] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[09:21:22.061] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[09:21:22.069] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[09:21:22.069] <TB2> INFO: run 1 of 1
[09:21:22.330] <TB2> INFO: Expecting 1364480 events.
[09:22:01.646] <TB2> INFO: 878344 events read in total (38759ms).
[09:22:23.270] <TB2> INFO: 1364480 events read in total (60383ms).
[09:22:23.281] <TB2> INFO: Test took 61212ms.
[09:22:36.845] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C0.dat
[09:22:36.851] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C1.dat
[09:22:36.855] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C2.dat
[09:22:36.892] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C3.dat
[09:22:36.896] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C4.dat
[09:22:36.900] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C5.dat
[09:22:36.903] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C6.dat
[09:22:36.907] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C7.dat
[09:22:36.911] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C8.dat
[09:22:36.915] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C9.dat
[09:22:36.918] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C10.dat
[09:22:36.922] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C11.dat
[09:22:36.926] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C12.dat
[09:22:36.930] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C13.dat
[09:22:36.934] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C14.dat
[09:22:36.937] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C15.dat
[09:22:36.941] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters35_C0.dat
[09:22:36.955] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters35_C1.dat
[09:22:36.967] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters35_C2.dat
[09:22:36.978] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters35_C3.dat
[09:22:36.990] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters35_C4.dat
[09:22:37.001] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters35_C5.dat
[09:22:37.013] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters35_C6.dat
[09:22:37.024] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters35_C7.dat
[09:22:37.036] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters35_C8.dat
[09:22:37.048] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters35_C9.dat
[09:22:37.060] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters35_C10.dat
[09:22:37.073] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters35_C11.dat
[09:22:37.085] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters35_C12.dat
[09:22:37.098] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters35_C13.dat
[09:22:37.109] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters35_C14.dat
[09:22:37.122] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//trimParameters35_C15.dat
[09:22:37.133] <TB2> INFO: PixTestTrim::trimTest() done
[09:22:37.133] <TB2> INFO: vtrim: 79 90 84 103 102 103 110 86 89 99 90 98 85 87 107 95
[09:22:37.133] <TB2> INFO: vthrcomp: 95 95 87 97 104 93 89 98 98 94 91 95 92 86 93 97
[09:22:37.133] <TB2> INFO: vcal mean: 34.94 34.99 34.97 34.91 34.98 34.98 34.97 34.95 34.96 35.02 34.98 34.96 34.99 34.97 34.92 35.03
[09:22:37.133] <TB2> INFO: vcal RMS: 0.91 0.90 0.95 1.12 0.91 0.92 0.89 0.96 0.99 1.10 0.95 0.95 0.92 1.00 1.27 0.94
[09:22:37.133] <TB2> INFO: bits mean: 9.43 9.67 9.60 9.79 9.28 9.11 9.79 9.72 9.63 9.11 9.33 9.37 9.03 8.66 9.55 9.19
[09:22:37.133] <TB2> INFO: bits RMS: 2.79 2.57 2.75 2.73 2.51 2.65 2.41 2.75 2.67 2.61 2.48 2.69 2.80 2.93 2.56 2.80
[09:22:37.141] <TB2> INFO: ----------------------------------------------------------------------
[09:22:37.141] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[09:22:37.141] <TB2> INFO: ----------------------------------------------------------------------
[09:22:37.145] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[09:22:37.153] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[09:22:37.153] <TB2> INFO: run 1 of 1
[09:22:37.449] <TB2> INFO: Expecting 4160000 events.
[09:23:20.126] <TB2> INFO: 951880 events read in total (42120ms).
[09:24:02.777] <TB2> INFO: 1898495 events read in total (84771ms).
[09:24:44.362] <TB2> INFO: 2835870 events read in total (126356ms).
[09:25:26.107] <TB2> INFO: 3772465 events read in total (168101ms).
[09:25:43.699] <TB2> INFO: 4160000 events read in total (185693ms).
[09:25:43.729] <TB2> INFO: Test took 186577ms.
[09:26:12.017] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 178 (-1/-1) hits flags = 528 (plus default)
[09:26:12.026] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[09:26:12.026] <TB2> INFO: run 1 of 1
[09:26:12.292] <TB2> INFO: Expecting 3723200 events.
[09:26:55.484] <TB2> INFO: 962685 events read in total (42635ms).
[09:27:37.774] <TB2> INFO: 1918550 events read in total (84925ms).
[09:28:19.657] <TB2> INFO: 2864975 events read in total (126808ms).
[09:28:57.699] <TB2> INFO: 3723200 events read in total (164850ms).
[09:28:57.733] <TB2> INFO: Test took 165707ms.
[09:29:24.734] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 162 (-1/-1) hits flags = 528 (plus default)
[09:29:24.743] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[09:29:24.743] <TB2> INFO: run 1 of 1
[09:29:25.021] <TB2> INFO: Expecting 3390400 events.
[09:30:09.459] <TB2> INFO: 1006225 events read in total (43881ms).
[09:30:52.805] <TB2> INFO: 2001860 events read in total (87227ms).
[09:31:35.702] <TB2> INFO: 2988925 events read in total (130124ms).
[09:31:52.968] <TB2> INFO: 3390400 events read in total (147390ms).
[09:31:52.996] <TB2> INFO: Test took 148252ms.
[09:32:16.974] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 160 (-1/-1) hits flags = 528 (plus default)
[09:32:16.984] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[09:32:16.984] <TB2> INFO: run 1 of 1
[09:32:17.245] <TB2> INFO: Expecting 3348800 events.
[09:33:00.558] <TB2> INFO: 1011745 events read in total (42756ms).
[09:33:42.782] <TB2> INFO: 2012895 events read in total (84980ms).
[09:34:25.397] <TB2> INFO: 3005125 events read in total (127595ms).
[09:34:40.621] <TB2> INFO: 3348800 events read in total (142819ms).
[09:34:40.649] <TB2> INFO: Test took 143665ms.
[09:35:06.347] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 156 (-1/-1) hits flags = 528 (plus default)
[09:35:06.355] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[09:35:06.356] <TB2> INFO: run 1 of 1
[09:35:06.631] <TB2> INFO: Expecting 3265600 events.
[09:35:50.420] <TB2> INFO: 1024350 events read in total (43232ms).
[09:36:33.926] <TB2> INFO: 2036515 events read in total (86738ms).
[09:37:17.111] <TB2> INFO: 3041345 events read in total (129923ms).
[09:37:26.995] <TB2> INFO: 3265600 events read in total (139807ms).
[09:37:27.020] <TB2> INFO: Test took 140664ms.
[09:37:50.807] <TB2> INFO: PixTestTrim::trimBitTest() done
[09:37:50.809] <TB2> INFO: PixTestTrim::doTest() done, duration: 2702 seconds
[09:37:50.809] <TB2> INFO: Decoding statistics:
[09:37:50.809] <TB2> INFO: General information:
[09:37:50.809] <TB2> INFO: 16bit words read: 0
[09:37:50.809] <TB2> INFO: valid events total: 0
[09:37:50.809] <TB2> INFO: empty events: 0
[09:37:50.809] <TB2> INFO: valid events with pixels: 0
[09:37:50.809] <TB2> INFO: valid pixel hits: 0
[09:37:50.809] <TB2> INFO: Event errors: 0
[09:37:50.809] <TB2> INFO: start marker: 0
[09:37:50.809] <TB2> INFO: stop marker: 0
[09:37:50.809] <TB2> INFO: overflow: 0
[09:37:50.809] <TB2> INFO: invalid 5bit words: 0
[09:37:50.809] <TB2> INFO: invalid XOR eye diagram: 0
[09:37:50.809] <TB2> INFO: frame (failed synchr.): 0
[09:37:50.809] <TB2> INFO: idle data (no TBM trl): 0
[09:37:50.809] <TB2> INFO: no data (only TBM hdr): 0
[09:37:50.809] <TB2> INFO: TBM errors: 0
[09:37:50.809] <TB2> INFO: flawed TBM headers: 0
[09:37:50.809] <TB2> INFO: flawed TBM trailers: 0
[09:37:50.809] <TB2> INFO: event ID mismatches: 0
[09:37:50.809] <TB2> INFO: ROC errors: 0
[09:37:50.809] <TB2> INFO: missing ROC header(s): 0
[09:37:50.809] <TB2> INFO: misplaced readback start: 0
[09:37:50.809] <TB2> INFO: Pixel decoding errors: 0
[09:37:50.809] <TB2> INFO: pixel data incomplete: 0
[09:37:50.809] <TB2> INFO: pixel address: 0
[09:37:50.809] <TB2> INFO: pulse height fill bit: 0
[09:37:50.809] <TB2> INFO: buffer corruption: 0
[09:37:51.467] <TB2> INFO: ######################################################################
[09:37:51.467] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[09:37:51.467] <TB2> INFO: ######################################################################
[09:37:51.730] <TB2> INFO: Expecting 41600 events.
[09:37:55.572] <TB2> INFO: 41600 events read in total (3285ms).
[09:37:55.573] <TB2> INFO: Test took 4104ms.
[09:37:56.046] <TB2> INFO: Expecting 41600 events.
[09:37:59.906] <TB2> INFO: 41600 events read in total (3303ms).
[09:37:59.907] <TB2> INFO: Test took 4129ms.
[09:38:00.194] <TB2> INFO: Expecting 41600 events.
[09:38:04.058] <TB2> INFO: 41600 events read in total (3307ms).
[09:38:04.059] <TB2> INFO: Test took 4131ms.
[09:38:04.362] <TB2> INFO: Expecting 41600 events.
[09:38:08.235] <TB2> INFO: 41600 events read in total (3316ms).
[09:38:08.235] <TB2> INFO: Test took 4157ms.
[09:38:08.519] <TB2> INFO: Expecting 41600 events.
[09:38:12.428] <TB2> INFO: 41600 events read in total (3353ms).
[09:38:12.429] <TB2> INFO: Test took 4174ms.
[09:38:12.721] <TB2> INFO: Expecting 41600 events.
[09:38:16.663] <TB2> INFO: 41600 events read in total (3385ms).
[09:38:16.664] <TB2> INFO: Test took 4215ms.
[09:38:16.951] <TB2> INFO: Expecting 41600 events.
[09:38:20.780] <TB2> INFO: 41600 events read in total (3271ms).
[09:38:20.781] <TB2> INFO: Test took 4095ms.
[09:38:21.061] <TB2> INFO: Expecting 41600 events.
[09:38:24.841] <TB2> INFO: 41600 events read in total (3223ms).
[09:38:24.841] <TB2> INFO: Test took 4041ms.
[09:38:25.123] <TB2> INFO: Expecting 41600 events.
[09:38:28.907] <TB2> INFO: 41600 events read in total (3227ms).
[09:38:28.908] <TB2> INFO: Test took 4047ms.
[09:38:29.189] <TB2> INFO: Expecting 41600 events.
[09:38:32.966] <TB2> INFO: 41600 events read in total (3219ms).
[09:38:32.967] <TB2> INFO: Test took 4039ms.
[09:38:33.253] <TB2> INFO: Expecting 41600 events.
[09:38:37.061] <TB2> INFO: 41600 events read in total (3251ms).
[09:38:37.062] <TB2> INFO: Test took 4076ms.
[09:38:37.360] <TB2> INFO: Expecting 41600 events.
[09:38:41.222] <TB2> INFO: 41600 events read in total (3305ms).
[09:38:41.223] <TB2> INFO: Test took 4139ms.
[09:38:41.511] <TB2> INFO: Expecting 41600 events.
[09:38:45.291] <TB2> INFO: 41600 events read in total (3223ms).
[09:38:45.291] <TB2> INFO: Test took 4045ms.
[09:38:45.581] <TB2> INFO: Expecting 41600 events.
[09:38:49.358] <TB2> INFO: 41600 events read in total (3220ms).
[09:38:49.359] <TB2> INFO: Test took 4045ms.
[09:38:49.636] <TB2> INFO: Expecting 41600 events.
[09:38:53.437] <TB2> INFO: 41600 events read in total (3244ms).
[09:38:53.437] <TB2> INFO: Test took 4058ms.
[09:38:53.718] <TB2> INFO: Expecting 41600 events.
[09:38:57.618] <TB2> INFO: 41600 events read in total (3343ms).
[09:38:57.619] <TB2> INFO: Test took 4162ms.
[09:38:57.899] <TB2> INFO: Expecting 41600 events.
[09:39:01.747] <TB2> INFO: 41600 events read in total (3291ms).
[09:39:01.748] <TB2> INFO: Test took 4110ms.
[09:39:02.046] <TB2> INFO: Expecting 41600 events.
[09:39:05.910] <TB2> INFO: 41600 events read in total (3308ms).
[09:39:05.911] <TB2> INFO: Test took 4142ms.
[09:39:06.192] <TB2> INFO: Expecting 41600 events.
[09:39:10.025] <TB2> INFO: 41600 events read in total (3276ms).
[09:39:10.026] <TB2> INFO: Test took 4095ms.
[09:39:10.310] <TB2> INFO: Expecting 41600 events.
[09:39:14.094] <TB2> INFO: 41600 events read in total (3227ms).
[09:39:14.095] <TB2> INFO: Test took 4049ms.
[09:39:14.384] <TB2> INFO: Expecting 41600 events.
[09:39:18.209] <TB2> INFO: 41600 events read in total (3268ms).
[09:39:18.210] <TB2> INFO: Test took 4095ms.
[09:39:18.490] <TB2> INFO: Expecting 41600 events.
[09:39:22.366] <TB2> INFO: 41600 events read in total (3319ms).
[09:39:22.366] <TB2> INFO: Test took 4137ms.
[09:39:22.658] <TB2> INFO: Expecting 41600 events.
[09:39:26.577] <TB2> INFO: 41600 events read in total (3362ms).
[09:39:26.578] <TB2> INFO: Test took 4190ms.
[09:39:26.892] <TB2> INFO: Expecting 41600 events.
[09:39:30.694] <TB2> INFO: 41600 events read in total (3245ms).
[09:39:30.694] <TB2> INFO: Test took 4093ms.
[09:39:30.974] <TB2> INFO: Expecting 41600 events.
[09:39:34.780] <TB2> INFO: 41600 events read in total (3249ms).
[09:39:34.781] <TB2> INFO: Test took 4067ms.
[09:39:35.062] <TB2> INFO: Expecting 41600 events.
[09:39:38.948] <TB2> INFO: 41600 events read in total (3329ms).
[09:39:38.948] <TB2> INFO: Test took 4148ms.
[09:39:39.247] <TB2> INFO: Expecting 41600 events.
[09:39:43.081] <TB2> INFO: 41600 events read in total (3277ms).
[09:39:43.081] <TB2> INFO: Test took 4112ms.
[09:39:43.401] <TB2> INFO: Expecting 41600 events.
[09:39:47.168] <TB2> INFO: 41600 events read in total (3210ms).
[09:39:47.169] <TB2> INFO: Test took 4066ms.
[09:39:47.450] <TB2> INFO: Expecting 41600 events.
[09:39:51.282] <TB2> INFO: 41600 events read in total (3275ms).
[09:39:51.283] <TB2> INFO: Test took 4094ms.
[09:39:51.569] <TB2> INFO: Expecting 41600 events.
[09:39:55.396] <TB2> INFO: 41600 events read in total (3270ms).
[09:39:55.396] <TB2> INFO: Test took 4093ms.
[09:39:55.677] <TB2> INFO: Expecting 41600 events.
[09:39:59.509] <TB2> INFO: 41600 events read in total (3275ms).
[09:39:59.510] <TB2> INFO: Test took 4094ms.
[09:39:59.791] <TB2> INFO: Expecting 41600 events.
[09:40:03.664] <TB2> INFO: 41600 events read in total (3316ms).
[09:40:03.664] <TB2> INFO: Test took 4134ms.
[09:40:03.981] <TB2> INFO: Expecting 41600 events.
[09:40:07.819] <TB2> INFO: 41600 events read in total (3282ms).
[09:40:07.819] <TB2> INFO: Test took 4135ms.
[09:40:08.137] <TB2> INFO: Expecting 41600 events.
[09:40:11.958] <TB2> INFO: 41600 events read in total (3264ms).
[09:40:11.959] <TB2> INFO: Test took 4117ms.
[09:40:12.267] <TB2> INFO: Expecting 41600 events.
[09:40:16.068] <TB2> INFO: 41600 events read in total (3244ms).
[09:40:16.069] <TB2> INFO: Test took 4090ms.
[09:40:16.354] <TB2> INFO: Expecting 41600 events.
[09:40:20.162] <TB2> INFO: 41600 events read in total (3251ms).
[09:40:20.163] <TB2> INFO: Test took 4074ms.
[09:40:20.446] <TB2> INFO: Expecting 41600 events.
[09:40:24.294] <TB2> INFO: 41600 events read in total (3291ms).
[09:40:24.295] <TB2> INFO: Test took 4112ms.
[09:40:24.578] <TB2> INFO: Expecting 41600 events.
[09:40:28.357] <TB2> INFO: 41600 events read in total (3222ms).
[09:40:28.357] <TB2> INFO: Test took 4042ms.
[09:40:28.640] <TB2> INFO: Expecting 41600 events.
[09:40:32.538] <TB2> INFO: 41600 events read in total (3341ms).
[09:40:32.539] <TB2> INFO: Test took 4162ms.
[09:40:32.859] <TB2> INFO: Expecting 41600 events.
[09:40:36.734] <TB2> INFO: 41600 events read in total (3318ms).
[09:40:36.735] <TB2> INFO: Test took 4174ms.
[09:40:37.020] <TB2> INFO: Expecting 41600 events.
[09:40:40.803] <TB2> INFO: 41600 events read in total (3226ms).
[09:40:40.804] <TB2> INFO: Test took 4048ms.
[09:40:41.087] <TB2> INFO: Expecting 41600 events.
[09:40:44.862] <TB2> INFO: 41600 events read in total (3218ms).
[09:40:44.862] <TB2> INFO: Test took 4038ms.
[09:40:45.148] <TB2> INFO: Expecting 41600 events.
[09:40:49.009] <TB2> INFO: 41600 events read in total (3304ms).
[09:40:49.011] <TB2> INFO: Test took 4129ms.
[09:40:49.295] <TB2> INFO: Expecting 41600 events.
[09:40:53.120] <TB2> INFO: 41600 events read in total (3268ms).
[09:40:53.121] <TB2> INFO: Test took 4090ms.
[09:40:53.415] <TB2> INFO: Expecting 41600 events.
[09:40:57.227] <TB2> INFO: 41600 events read in total (3255ms).
[09:40:57.228] <TB2> INFO: Test took 4087ms.
[09:40:57.513] <TB2> INFO: Expecting 41600 events.
[09:41:01.303] <TB2> INFO: 41600 events read in total (3233ms).
[09:41:01.304] <TB2> INFO: Test took 4056ms.
[09:41:01.620] <TB2> INFO: Expecting 41600 events.
[09:41:05.517] <TB2> INFO: 41600 events read in total (3339ms).
[09:41:05.518] <TB2> INFO: Test took 4192ms.
[09:41:05.803] <TB2> INFO: Expecting 41600 events.
[09:41:09.631] <TB2> INFO: 41600 events read in total (3271ms).
[09:41:09.633] <TB2> INFO: Test took 4095ms.
[09:41:09.916] <TB2> INFO: Expecting 41600 events.
[09:41:13.717] <TB2> INFO: 41600 events read in total (3244ms).
[09:41:13.718] <TB2> INFO: Test took 4065ms.
[09:41:14.001] <TB2> INFO: Expecting 41600 events.
[09:41:17.794] <TB2> INFO: 41600 events read in total (3236ms).
[09:41:17.795] <TB2> INFO: Test took 4057ms.
[09:41:18.077] <TB2> INFO: Expecting 41600 events.
[09:41:21.928] <TB2> INFO: 41600 events read in total (3294ms).
[09:41:21.929] <TB2> INFO: Test took 4114ms.
[09:41:22.210] <TB2> INFO: Expecting 41600 events.
[09:41:26.011] <TB2> INFO: 41600 events read in total (3243ms).
[09:41:26.013] <TB2> INFO: Test took 4064ms.
[09:41:26.309] <TB2> INFO: Expecting 41600 events.
[09:41:30.105] <TB2> INFO: 41600 events read in total (3239ms).
[09:41:30.106] <TB2> INFO: Test took 4072ms.
[09:41:30.389] <TB2> INFO: Expecting 41600 events.
[09:41:34.176] <TB2> INFO: 41600 events read in total (3230ms).
[09:41:34.178] <TB2> INFO: Test took 4052ms.
[09:41:34.435] <TB2> INFO: Expecting 2560 events.
[09:41:35.291] <TB2> INFO: 2560 events read in total (299ms).
[09:41:35.291] <TB2> INFO: Test took 1099ms.
[09:41:35.598] <TB2> INFO: Expecting 2560 events.
[09:41:36.454] <TB2> INFO: 2560 events read in total (299ms).
[09:41:36.454] <TB2> INFO: Test took 1162ms.
[09:41:36.761] <TB2> INFO: Expecting 2560 events.
[09:41:37.620] <TB2> INFO: 2560 events read in total (302ms).
[09:41:37.620] <TB2> INFO: Test took 1165ms.
[09:41:37.926] <TB2> INFO: Expecting 2560 events.
[09:41:38.783] <TB2> INFO: 2560 events read in total (299ms).
[09:41:38.784] <TB2> INFO: Test took 1164ms.
[09:41:39.090] <TB2> INFO: Expecting 2560 events.
[09:41:39.944] <TB2> INFO: 2560 events read in total (297ms).
[09:41:39.945] <TB2> INFO: Test took 1161ms.
[09:41:40.251] <TB2> INFO: Expecting 2560 events.
[09:41:41.105] <TB2> INFO: 2560 events read in total (297ms).
[09:41:41.105] <TB2> INFO: Test took 1160ms.
[09:41:41.411] <TB2> INFO: Expecting 2560 events.
[09:41:42.266] <TB2> INFO: 2560 events read in total (298ms).
[09:41:42.266] <TB2> INFO: Test took 1160ms.
[09:41:42.573] <TB2> INFO: Expecting 2560 events.
[09:41:43.428] <TB2> INFO: 2560 events read in total (298ms).
[09:41:43.428] <TB2> INFO: Test took 1161ms.
[09:41:43.734] <TB2> INFO: Expecting 2560 events.
[09:41:44.589] <TB2> INFO: 2560 events read in total (298ms).
[09:41:44.589] <TB2> INFO: Test took 1160ms.
[09:41:44.896] <TB2> INFO: Expecting 2560 events.
[09:41:45.750] <TB2> INFO: 2560 events read in total (298ms).
[09:41:45.750] <TB2> INFO: Test took 1161ms.
[09:41:46.056] <TB2> INFO: Expecting 2560 events.
[09:41:46.914] <TB2> INFO: 2560 events read in total (301ms).
[09:41:46.914] <TB2> INFO: Test took 1164ms.
[09:41:47.220] <TB2> INFO: Expecting 2560 events.
[09:41:48.075] <TB2> INFO: 2560 events read in total (298ms).
[09:41:48.075] <TB2> INFO: Test took 1160ms.
[09:41:48.382] <TB2> INFO: Expecting 2560 events.
[09:41:49.237] <TB2> INFO: 2560 events read in total (299ms).
[09:41:49.238] <TB2> INFO: Test took 1162ms.
[09:41:49.543] <TB2> INFO: Expecting 2560 events.
[09:41:50.398] <TB2> INFO: 2560 events read in total (298ms).
[09:41:50.398] <TB2> INFO: Test took 1160ms.
[09:41:50.704] <TB2> INFO: Expecting 2560 events.
[09:41:51.563] <TB2> INFO: 2560 events read in total (302ms).
[09:41:51.563] <TB2> INFO: Test took 1164ms.
[09:41:51.870] <TB2> INFO: Expecting 2560 events.
[09:41:52.729] <TB2> INFO: 2560 events read in total (302ms).
[09:41:52.729] <TB2> INFO: Test took 1166ms.
[09:41:52.734] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:41:53.037] <TB2> INFO: Expecting 655360 events.
[09:42:09.738] <TB2> INFO: 655360 events read in total (16144ms).
[09:42:09.748] <TB2> INFO: Expecting 655360 events.
[09:42:26.422] <TB2> INFO: 655360 events read in total (16271ms).
[09:42:26.440] <TB2> INFO: Expecting 655360 events.
[09:42:43.087] <TB2> INFO: 655360 events read in total (16244ms).
[09:42:43.104] <TB2> INFO: Expecting 655360 events.
[09:42:59.644] <TB2> INFO: 655360 events read in total (16138ms).
[09:42:59.667] <TB2> INFO: Expecting 655360 events.
[09:43:16.339] <TB2> INFO: 655360 events read in total (16270ms).
[09:43:16.372] <TB2> INFO: Expecting 655360 events.
[09:43:32.955] <TB2> INFO: 655360 events read in total (16180ms).
[09:43:32.982] <TB2> INFO: Expecting 655360 events.
[09:43:49.680] <TB2> INFO: 655360 events read in total (16296ms).
[09:43:49.709] <TB2> INFO: Expecting 655360 events.
[09:44:06.547] <TB2> INFO: 655360 events read in total (16435ms).
[09:44:06.594] <TB2> INFO: Expecting 655360 events.
[09:44:23.365] <TB2> INFO: 655360 events read in total (16368ms).
[09:44:23.403] <TB2> INFO: Expecting 655360 events.
[09:44:40.147] <TB2> INFO: 655360 events read in total (16342ms).
[09:44:40.191] <TB2> INFO: Expecting 655360 events.
[09:44:56.813] <TB2> INFO: 655360 events read in total (16220ms).
[09:44:56.869] <TB2> INFO: Expecting 655360 events.
[09:45:13.591] <TB2> INFO: 655360 events read in total (16320ms).
[09:45:13.639] <TB2> INFO: Expecting 655360 events.
[09:45:30.471] <TB2> INFO: 655360 events read in total (16430ms).
[09:45:30.525] <TB2> INFO: Expecting 655360 events.
[09:45:47.368] <TB2> INFO: 655360 events read in total (16440ms).
[09:45:47.428] <TB2> INFO: Expecting 655360 events.
[09:46:04.209] <TB2> INFO: 655360 events read in total (16378ms).
[09:46:04.283] <TB2> INFO: Expecting 655360 events.
[09:46:21.079] <TB2> INFO: 655360 events read in total (16394ms).
[09:46:21.142] <TB2> INFO: Test took 268408ms.
[09:46:21.220] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:46:21.449] <TB2> INFO: Expecting 655360 events.
[09:46:38.239] <TB2> INFO: 655360 events read in total (16231ms).
[09:46:38.249] <TB2> INFO: Expecting 655360 events.
[09:46:54.746] <TB2> INFO: 655360 events read in total (16094ms).
[09:46:54.759] <TB2> INFO: Expecting 655360 events.
[09:47:11.190] <TB2> INFO: 655360 events read in total (16029ms).
[09:47:11.207] <TB2> INFO: Expecting 655360 events.
[09:47:27.768] <TB2> INFO: 655360 events read in total (16159ms).
[09:47:27.787] <TB2> INFO: Expecting 655360 events.
[09:47:44.561] <TB2> INFO: 655360 events read in total (16372ms).
[09:47:44.585] <TB2> INFO: Expecting 655360 events.
[09:48:01.446] <TB2> INFO: 655360 events read in total (16459ms).
[09:48:01.478] <TB2> INFO: Expecting 655360 events.
[09:48:18.279] <TB2> INFO: 655360 events read in total (16398ms).
[09:48:18.308] <TB2> INFO: Expecting 655360 events.
[09:48:34.934] <TB2> INFO: 655360 events read in total (16223ms).
[09:48:34.972] <TB2> INFO: Expecting 655360 events.
[09:48:51.196] <TB2> INFO: 655360 events read in total (15822ms).
[09:48:51.232] <TB2> INFO: Expecting 655360 events.
[09:49:07.646] <TB2> INFO: 655360 events read in total (16012ms).
[09:49:07.690] <TB2> INFO: Expecting 655360 events.
[09:49:24.434] <TB2> INFO: 655360 events read in total (16342ms).
[09:49:24.480] <TB2> INFO: Expecting 655360 events.
[09:49:41.116] <TB2> INFO: 655360 events read in total (16233ms).
[09:49:41.163] <TB2> INFO: Expecting 655360 events.
[09:49:57.952] <TB2> INFO: 655360 events read in total (16386ms).
[09:49:58.004] <TB2> INFO: Expecting 655360 events.
[09:50:14.731] <TB2> INFO: 655360 events read in total (16324ms).
[09:50:14.784] <TB2> INFO: Expecting 655360 events.
[09:50:31.448] <TB2> INFO: 655360 events read in total (16261ms).
[09:50:31.506] <TB2> INFO: Expecting 655360 events.
[09:50:48.618] <TB2> INFO: 655360 events read in total (16710ms).
[09:50:48.680] <TB2> INFO: Test took 267460ms.
[09:50:48.865] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[09:50:48.872] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[09:50:48.878] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[09:50:48.885] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[09:50:48.891] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[09:50:48.898] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[09:50:48.904] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[09:50:48.911] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[09:50:48.917] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[09:50:48.924] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[09:50:48.930] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[09:50:48.937] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[09:50:48.943] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[09:50:48.950] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[09:50:48.957] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[09:50:48.963] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[09:50:48.970] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[09:50:48.976] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[09:50:48.983] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[09:50:48.989] <TB2> INFO: safety margin for low PH: adding 6, margin is now 26
[09:50:48.996] <TB2> INFO: safety margin for low PH: adding 7, margin is now 27
[09:50:49.003] <TB2> INFO: safety margin for low PH: adding 8, margin is now 28
[09:50:49.009] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[09:50:49.016] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[09:50:49.023] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[09:50:49.029] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[09:50:49.036] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[09:50:49.042] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[09:50:49.049] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[09:50:49.181] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C0.dat
[09:50:49.187] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C1.dat
[09:50:49.193] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C2.dat
[09:50:49.198] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C3.dat
[09:50:49.204] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C4.dat
[09:50:49.209] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C5.dat
[09:50:49.214] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C6.dat
[09:50:49.219] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C7.dat
[09:50:49.225] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C8.dat
[09:50:49.230] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C9.dat
[09:50:49.237] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C10.dat
[09:50:49.244] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C11.dat
[09:50:49.249] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C12.dat
[09:50:49.254] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C13.dat
[09:50:49.260] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C14.dat
[09:50:49.265] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//dacParameters35_C15.dat
[09:50:49.535] <TB2> INFO: Expecting 41600 events.
[09:50:53.048] <TB2> INFO: 41600 events read in total (2956ms).
[09:50:53.049] <TB2> INFO: Test took 3777ms.
[09:50:53.514] <TB2> INFO: Expecting 41600 events.
[09:50:57.006] <TB2> INFO: 41600 events read in total (2934ms).
[09:50:57.007] <TB2> INFO: Test took 3769ms.
[09:50:57.456] <TB2> INFO: Expecting 41600 events.
[09:51:00.962] <TB2> INFO: 41600 events read in total (2949ms).
[09:51:00.964] <TB2> INFO: Test took 3769ms.
[09:51:01.156] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:01.246] <TB2> INFO: Expecting 2560 events.
[09:51:02.102] <TB2> INFO: 2560 events read in total (298ms).
[09:51:02.102] <TB2> INFO: Test took 946ms.
[09:51:02.106] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:02.409] <TB2> INFO: Expecting 2560 events.
[09:51:03.269] <TB2> INFO: 2560 events read in total (302ms).
[09:51:03.270] <TB2> INFO: Test took 1164ms.
[09:51:03.273] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:03.578] <TB2> INFO: Expecting 2560 events.
[09:51:04.438] <TB2> INFO: 2560 events read in total (303ms).
[09:51:04.438] <TB2> INFO: Test took 1165ms.
[09:51:04.441] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:04.745] <TB2> INFO: Expecting 2560 events.
[09:51:05.603] <TB2> INFO: 2560 events read in total (301ms).
[09:51:05.603] <TB2> INFO: Test took 1162ms.
[09:51:05.606] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:05.911] <TB2> INFO: Expecting 2560 events.
[09:51:06.775] <TB2> INFO: 2560 events read in total (307ms).
[09:51:06.775] <TB2> INFO: Test took 1169ms.
[09:51:06.779] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:07.082] <TB2> INFO: Expecting 2560 events.
[09:51:07.944] <TB2> INFO: 2560 events read in total (305ms).
[09:51:07.945] <TB2> INFO: Test took 1166ms.
[09:51:07.948] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:08.253] <TB2> INFO: Expecting 2560 events.
[09:51:09.113] <TB2> INFO: 2560 events read in total (303ms).
[09:51:09.114] <TB2> INFO: Test took 1166ms.
[09:51:09.117] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:09.420] <TB2> INFO: Expecting 2560 events.
[09:51:10.284] <TB2> INFO: 2560 events read in total (306ms).
[09:51:10.284] <TB2> INFO: Test took 1167ms.
[09:51:10.287] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:10.593] <TB2> INFO: Expecting 2560 events.
[09:51:11.452] <TB2> INFO: 2560 events read in total (302ms).
[09:51:11.453] <TB2> INFO: Test took 1166ms.
[09:51:11.456] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:11.759] <TB2> INFO: Expecting 2560 events.
[09:51:12.619] <TB2> INFO: 2560 events read in total (302ms).
[09:51:12.620] <TB2> INFO: Test took 1164ms.
[09:51:12.624] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:12.927] <TB2> INFO: Expecting 2560 events.
[09:51:13.786] <TB2> INFO: 2560 events read in total (302ms).
[09:51:13.787] <TB2> INFO: Test took 1163ms.
[09:51:13.789] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:14.095] <TB2> INFO: Expecting 2560 events.
[09:51:14.955] <TB2> INFO: 2560 events read in total (303ms).
[09:51:14.955] <TB2> INFO: Test took 1166ms.
[09:51:14.958] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:15.262] <TB2> INFO: Expecting 2560 events.
[09:51:16.122] <TB2> INFO: 2560 events read in total (302ms).
[09:51:16.122] <TB2> INFO: Test took 1164ms.
[09:51:16.125] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:16.430] <TB2> INFO: Expecting 2560 events.
[09:51:17.293] <TB2> INFO: 2560 events read in total (306ms).
[09:51:17.293] <TB2> INFO: Test took 1168ms.
[09:51:17.296] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:17.601] <TB2> INFO: Expecting 2560 events.
[09:51:18.461] <TB2> INFO: 2560 events read in total (303ms).
[09:51:18.461] <TB2> INFO: Test took 1165ms.
[09:51:18.464] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:18.768] <TB2> INFO: Expecting 2560 events.
[09:51:19.624] <TB2> INFO: 2560 events read in total (299ms).
[09:51:19.624] <TB2> INFO: Test took 1160ms.
[09:51:19.627] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:19.932] <TB2> INFO: Expecting 2560 events.
[09:51:20.791] <TB2> INFO: 2560 events read in total (302ms).
[09:51:20.791] <TB2> INFO: Test took 1164ms.
[09:51:20.796] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:21.099] <TB2> INFO: Expecting 2560 events.
[09:51:21.955] <TB2> INFO: 2560 events read in total (299ms).
[09:51:21.955] <TB2> INFO: Test took 1159ms.
[09:51:21.960] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:22.263] <TB2> INFO: Expecting 2560 events.
[09:51:23.123] <TB2> INFO: 2560 events read in total (303ms).
[09:51:23.123] <TB2> INFO: Test took 1163ms.
[09:51:23.126] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:23.430] <TB2> INFO: Expecting 2560 events.
[09:51:24.289] <TB2> INFO: 2560 events read in total (302ms).
[09:51:24.290] <TB2> INFO: Test took 1164ms.
[09:51:24.293] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:24.597] <TB2> INFO: Expecting 2560 events.
[09:51:25.457] <TB2> INFO: 2560 events read in total (303ms).
[09:51:25.457] <TB2> INFO: Test took 1164ms.
[09:51:25.460] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:25.764] <TB2> INFO: Expecting 2560 events.
[09:51:26.623] <TB2> INFO: 2560 events read in total (302ms).
[09:51:26.623] <TB2> INFO: Test took 1163ms.
[09:51:26.626] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:26.931] <TB2> INFO: Expecting 2560 events.
[09:51:27.791] <TB2> INFO: 2560 events read in total (303ms).
[09:51:27.791] <TB2> INFO: Test took 1166ms.
[09:51:27.796] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:28.098] <TB2> INFO: Expecting 2560 events.
[09:51:28.955] <TB2> INFO: 2560 events read in total (300ms).
[09:51:28.955] <TB2> INFO: Test took 1159ms.
[09:51:28.959] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:29.263] <TB2> INFO: Expecting 2560 events.
[09:51:30.123] <TB2> INFO: 2560 events read in total (303ms).
[09:51:30.123] <TB2> INFO: Test took 1164ms.
[09:51:30.126] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:30.430] <TB2> INFO: Expecting 2560 events.
[09:51:31.290] <TB2> INFO: 2560 events read in total (302ms).
[09:51:31.290] <TB2> INFO: Test took 1164ms.
[09:51:31.293] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:31.598] <TB2> INFO: Expecting 2560 events.
[09:51:32.455] <TB2> INFO: 2560 events read in total (299ms).
[09:51:32.455] <TB2> INFO: Test took 1162ms.
[09:51:32.459] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:32.763] <TB2> INFO: Expecting 2560 events.
[09:51:33.623] <TB2> INFO: 2560 events read in total (303ms).
[09:51:33.623] <TB2> INFO: Test took 1164ms.
[09:51:33.626] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:33.930] <TB2> INFO: Expecting 2560 events.
[09:51:34.793] <TB2> INFO: 2560 events read in total (306ms).
[09:51:34.793] <TB2> INFO: Test took 1168ms.
[09:51:34.796] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:35.100] <TB2> INFO: Expecting 2560 events.
[09:51:35.960] <TB2> INFO: 2560 events read in total (302ms).
[09:51:35.961] <TB2> INFO: Test took 1166ms.
[09:51:35.965] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:36.268] <TB2> INFO: Expecting 2560 events.
[09:51:37.125] <TB2> INFO: 2560 events read in total (300ms).
[09:51:37.125] <TB2> INFO: Test took 1160ms.
[09:51:37.128] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:37.433] <TB2> INFO: Expecting 2560 events.
[09:51:38.292] <TB2> INFO: 2560 events read in total (302ms).
[09:51:38.292] <TB2> INFO: Test took 1164ms.
[09:51:38.820] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 827 seconds
[09:51:38.820] <TB2> INFO: PH scale (per ROC): 67 79 79 75 79 76 74 72 69 78 63 75 78 68 65 71
[09:51:38.820] <TB2> INFO: PH offset (per ROC): 184 177 167 195 177 176 162 179 176 180 184 171 167 186 174 178
[09:51:38.825] <TB2> INFO: Decoding statistics:
[09:51:38.825] <TB2> INFO: General information:
[09:51:38.825] <TB2> INFO: 16bit words read: 91936
[09:51:38.825] <TB2> INFO: valid events total: 10240
[09:51:38.825] <TB2> INFO: empty events: 7736
[09:51:38.825] <TB2> INFO: valid events with pixels: 2504
[09:51:38.825] <TB2> INFO: valid pixel hits: 2504
[09:51:38.825] <TB2> INFO: Event errors: 0
[09:51:38.825] <TB2> INFO: start marker: 0
[09:51:38.825] <TB2> INFO: stop marker: 0
[09:51:38.825] <TB2> INFO: overflow: 0
[09:51:38.825] <TB2> INFO: invalid 5bit words: 0
[09:51:38.825] <TB2> INFO: invalid XOR eye diagram: 0
[09:51:38.825] <TB2> INFO: frame (failed synchr.): 0
[09:51:38.825] <TB2> INFO: idle data (no TBM trl): 0
[09:51:38.825] <TB2> INFO: no data (only TBM hdr): 0
[09:51:38.825] <TB2> INFO: TBM errors: 0
[09:51:38.825] <TB2> INFO: flawed TBM headers: 0
[09:51:38.825] <TB2> INFO: flawed TBM trailers: 0
[09:51:38.826] <TB2> INFO: event ID mismatches: 0
[09:51:38.826] <TB2> INFO: ROC errors: 0
[09:51:38.826] <TB2> INFO: missing ROC header(s): 0
[09:51:38.826] <TB2> INFO: misplaced readback start: 0
[09:51:38.826] <TB2> INFO: Pixel decoding errors: 0
[09:51:38.826] <TB2> INFO: pixel data incomplete: 0
[09:51:38.826] <TB2> INFO: pixel address: 0
[09:51:38.826] <TB2> INFO: pulse height fill bit: 0
[09:51:38.826] <TB2> INFO: buffer corruption: 0
[09:51:39.006] <TB2> INFO: ######################################################################
[09:51:39.006] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[09:51:39.006] <TB2> INFO: ######################################################################
[09:51:39.017] <TB2> INFO: scanning low vcal = 10
[09:51:39.276] <TB2> INFO: Expecting 41600 events.
[09:51:42.821] <TB2> INFO: 41600 events read in total (2988ms).
[09:51:42.821] <TB2> INFO: Test took 3804ms.
[09:51:42.824] <TB2> INFO: scanning low vcal = 20
[09:51:43.128] <TB2> INFO: Expecting 41600 events.
[09:51:46.684] <TB2> INFO: 41600 events read in total (2999ms).
[09:51:46.685] <TB2> INFO: Test took 3861ms.
[09:51:46.688] <TB2> INFO: scanning low vcal = 30
[09:51:46.991] <TB2> INFO: Expecting 41600 events.
[09:51:50.587] <TB2> INFO: 41600 events read in total (3039ms).
[09:51:50.588] <TB2> INFO: Test took 3900ms.
[09:51:50.591] <TB2> INFO: scanning low vcal = 40
[09:51:50.876] <TB2> INFO: Expecting 41600 events.
[09:51:55.069] <TB2> INFO: 41600 events read in total (3636ms).
[09:51:55.071] <TB2> INFO: Test took 4480ms.
[09:51:55.074] <TB2> INFO: scanning low vcal = 50
[09:51:55.335] <TB2> INFO: Expecting 41600 events.
[09:51:59.578] <TB2> INFO: 41600 events read in total (3685ms).
[09:51:59.579] <TB2> INFO: Test took 4504ms.
[09:51:59.582] <TB2> INFO: scanning low vcal = 60
[09:51:59.874] <TB2> INFO: Expecting 41600 events.
[09:52:04.086] <TB2> INFO: 41600 events read in total (3655ms).
[09:52:04.087] <TB2> INFO: Test took 4505ms.
[09:52:04.090] <TB2> INFO: scanning low vcal = 70
[09:52:04.350] <TB2> INFO: Expecting 41600 events.
[09:52:08.516] <TB2> INFO: 41600 events read in total (3609ms).
[09:52:08.517] <TB2> INFO: Test took 4427ms.
[09:52:08.520] <TB2> INFO: scanning low vcal = 80
[09:52:08.781] <TB2> INFO: Expecting 41600 events.
[09:52:12.953] <TB2> INFO: 41600 events read in total (3615ms).
[09:52:12.954] <TB2> INFO: Test took 4433ms.
[09:52:12.957] <TB2> INFO: scanning low vcal = 90
[09:52:13.214] <TB2> INFO: Expecting 41600 events.
[09:52:17.372] <TB2> INFO: 41600 events read in total (3601ms).
[09:52:17.372] <TB2> INFO: Test took 4415ms.
[09:52:17.376] <TB2> INFO: scanning low vcal = 100
[09:52:17.630] <TB2> INFO: Expecting 41600 events.
[09:52:21.785] <TB2> INFO: 41600 events read in total (3598ms).
[09:52:21.787] <TB2> INFO: Test took 4411ms.
[09:52:21.791] <TB2> INFO: scanning low vcal = 110
[09:52:22.048] <TB2> INFO: Expecting 41600 events.
[09:52:26.207] <TB2> INFO: 41600 events read in total (3602ms).
[09:52:26.208] <TB2> INFO: Test took 4417ms.
[09:52:26.213] <TB2> INFO: scanning low vcal = 120
[09:52:26.470] <TB2> INFO: Expecting 41600 events.
[09:52:30.627] <TB2> INFO: 41600 events read in total (3600ms).
[09:52:30.628] <TB2> INFO: Test took 4415ms.
[09:52:30.632] <TB2> INFO: scanning low vcal = 130
[09:52:30.890] <TB2> INFO: Expecting 41600 events.
[09:52:35.043] <TB2> INFO: 41600 events read in total (3596ms).
[09:52:35.043] <TB2> INFO: Test took 4410ms.
[09:52:35.047] <TB2> INFO: scanning low vcal = 140
[09:52:35.304] <TB2> INFO: Expecting 41600 events.
[09:52:39.457] <TB2> INFO: 41600 events read in total (3596ms).
[09:52:39.458] <TB2> INFO: Test took 4411ms.
[09:52:39.463] <TB2> INFO: scanning low vcal = 150
[09:52:39.720] <TB2> INFO: Expecting 41600 events.
[09:52:43.881] <TB2> INFO: 41600 events read in total (3604ms).
[09:52:43.883] <TB2> INFO: Test took 4420ms.
[09:52:43.886] <TB2> INFO: scanning low vcal = 160
[09:52:44.144] <TB2> INFO: Expecting 41600 events.
[09:52:48.311] <TB2> INFO: 41600 events read in total (3610ms).
[09:52:48.311] <TB2> INFO: Test took 4425ms.
[09:52:48.315] <TB2> INFO: scanning low vcal = 170
[09:52:48.575] <TB2> INFO: Expecting 41600 events.
[09:52:52.737] <TB2> INFO: 41600 events read in total (3605ms).
[09:52:52.737] <TB2> INFO: Test took 4422ms.
[09:52:52.742] <TB2> INFO: scanning low vcal = 180
[09:52:52.999] <TB2> INFO: Expecting 41600 events.
[09:52:57.159] <TB2> INFO: 41600 events read in total (3603ms).
[09:52:57.160] <TB2> INFO: Test took 4418ms.
[09:52:57.163] <TB2> INFO: scanning low vcal = 190
[09:52:57.420] <TB2> INFO: Expecting 41600 events.
[09:53:01.576] <TB2> INFO: 41600 events read in total (3600ms).
[09:53:01.576] <TB2> INFO: Test took 4412ms.
[09:53:01.580] <TB2> INFO: scanning low vcal = 200
[09:53:01.835] <TB2> INFO: Expecting 41600 events.
[09:53:05.995] <TB2> INFO: 41600 events read in total (3603ms).
[09:53:05.996] <TB2> INFO: Test took 4416ms.
[09:53:05.999] <TB2> INFO: scanning low vcal = 210
[09:53:06.259] <TB2> INFO: Expecting 41600 events.
[09:53:10.412] <TB2> INFO: 41600 events read in total (3597ms).
[09:53:10.413] <TB2> INFO: Test took 4413ms.
[09:53:10.416] <TB2> INFO: scanning low vcal = 220
[09:53:10.672] <TB2> INFO: Expecting 41600 events.
[09:53:14.825] <TB2> INFO: 41600 events read in total (3596ms).
[09:53:14.825] <TB2> INFO: Test took 4409ms.
[09:53:14.828] <TB2> INFO: scanning low vcal = 230
[09:53:15.082] <TB2> INFO: Expecting 41600 events.
[09:53:19.236] <TB2> INFO: 41600 events read in total (3597ms).
[09:53:19.238] <TB2> INFO: Test took 4409ms.
[09:53:19.241] <TB2> INFO: scanning low vcal = 240
[09:53:19.496] <TB2> INFO: Expecting 41600 events.
[09:53:23.653] <TB2> INFO: 41600 events read in total (3600ms).
[09:53:23.653] <TB2> INFO: Test took 4412ms.
[09:53:23.656] <TB2> INFO: scanning low vcal = 250
[09:53:23.910] <TB2> INFO: Expecting 41600 events.
[09:53:28.068] <TB2> INFO: 41600 events read in total (3601ms).
[09:53:28.068] <TB2> INFO: Test took 4412ms.
[09:53:28.073] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[09:53:28.327] <TB2> INFO: Expecting 41600 events.
[09:53:32.490] <TB2> INFO: 41600 events read in total (3606ms).
[09:53:32.491] <TB2> INFO: Test took 4418ms.
[09:53:32.495] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[09:53:32.749] <TB2> INFO: Expecting 41600 events.
[09:53:36.912] <TB2> INFO: 41600 events read in total (3606ms).
[09:53:36.913] <TB2> INFO: Test took 4418ms.
[09:53:36.916] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[09:53:37.173] <TB2> INFO: Expecting 41600 events.
[09:53:41.330] <TB2> INFO: 41600 events read in total (3600ms).
[09:53:41.331] <TB2> INFO: Test took 4415ms.
[09:53:41.335] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[09:53:41.592] <TB2> INFO: Expecting 41600 events.
[09:53:45.746] <TB2> INFO: 41600 events read in total (3597ms).
[09:53:45.747] <TB2> INFO: Test took 4412ms.
[09:53:45.750] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[09:53:46.004] <TB2> INFO: Expecting 41600 events.
[09:53:50.158] <TB2> INFO: 41600 events read in total (3597ms).
[09:53:50.158] <TB2> INFO: Test took 4408ms.
[09:53:51.131] <TB2> INFO: PixTestGainPedestal::measure() done
[09:54:21.898] <TB2> INFO: PixTestGainPedestal::fit() done
[09:54:21.898] <TB2> INFO: non-linearity mean: 0.954 0.962 0.958 0.954 0.965 0.960 0.952 0.960 0.959 0.958 0.951 0.958 0.953 0.951 0.954 0.958
[09:54:21.898] <TB2> INFO: non-linearity RMS: 0.008 0.005 0.007 0.008 0.005 0.005 0.006 0.006 0.006 0.006 0.009 0.006 0.007 0.007 0.007 0.007
[09:54:21.899] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//phCalibrationFitErr35_C0.dat
[09:54:21.935] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//phCalibrationFitErr35_C1.dat
[09:54:21.971] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//phCalibrationFitErr35_C2.dat
[09:54:22.006] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//phCalibrationFitErr35_C3.dat
[09:54:22.042] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//phCalibrationFitErr35_C4.dat
[09:54:22.078] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//phCalibrationFitErr35_C5.dat
[09:54:22.121] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//phCalibrationFitErr35_C6.dat
[09:54:22.156] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//phCalibrationFitErr35_C7.dat
[09:54:22.191] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//phCalibrationFitErr35_C8.dat
[09:54:22.227] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//phCalibrationFitErr35_C9.dat
[09:54:22.263] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//phCalibrationFitErr35_C10.dat
[09:54:22.300] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//phCalibrationFitErr35_C11.dat
[09:54:22.335] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//phCalibrationFitErr35_C12.dat
[09:54:22.370] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//phCalibrationFitErr35_C13.dat
[09:54:22.407] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//phCalibrationFitErr35_C14.dat
[09:54:22.442] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//phCalibrationFitErr35_C15.dat
[09:54:22.476] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 163 seconds
[09:54:22.477] <TB2> INFO: Decoding statistics:
[09:54:22.477] <TB2> INFO: General information:
[09:54:22.477] <TB2> INFO: 16bit words read: 2662400
[09:54:22.477] <TB2> INFO: valid events total: 166400
[09:54:22.477] <TB2> INFO: empty events: 0
[09:54:22.477] <TB2> INFO: valid events with pixels: 166400
[09:54:22.477] <TB2> INFO: valid pixel hits: 665560
[09:54:22.477] <TB2> INFO: Event errors: 0
[09:54:22.477] <TB2> INFO: start marker: 0
[09:54:22.477] <TB2> INFO: stop marker: 0
[09:54:22.477] <TB2> INFO: overflow: 0
[09:54:22.477] <TB2> INFO: invalid 5bit words: 0
[09:54:22.477] <TB2> INFO: invalid XOR eye diagram: 0
[09:54:22.477] <TB2> INFO: frame (failed synchr.): 0
[09:54:22.477] <TB2> INFO: idle data (no TBM trl): 0
[09:54:22.477] <TB2> INFO: no data (only TBM hdr): 0
[09:54:22.477] <TB2> INFO: TBM errors: 0
[09:54:22.477] <TB2> INFO: flawed TBM headers: 0
[09:54:22.477] <TB2> INFO: flawed TBM trailers: 0
[09:54:22.477] <TB2> INFO: event ID mismatches: 0
[09:54:22.477] <TB2> INFO: ROC errors: 0
[09:54:22.477] <TB2> INFO: missing ROC header(s): 0
[09:54:22.477] <TB2> INFO: misplaced readback start: 0
[09:54:22.477] <TB2> INFO: Pixel decoding errors: 0
[09:54:22.477] <TB2> INFO: pixel data incomplete: 0
[09:54:22.477] <TB2> INFO: pixel address: 0
[09:54:22.477] <TB2> INFO: pulse height fill bit: 0
[09:54:22.477] <TB2> INFO: buffer corruption: 0
[09:54:22.487] <TB2> INFO: readReadbackCal: /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C0.dat .. /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C15.dat
[09:54:22.557] <TB2> INFO: ######################################################################
[09:54:22.557] <TB2> INFO: PixTestReadback::doTest()
[09:54:22.557] <TB2> INFO: ######################################################################
[09:54:22.557] <TB2> INFO: ----------------------------------------------------------------------
[09:54:22.557] <TB2> INFO: PixTestReadback::CalibrateVd()
[09:54:22.557] <TB2> INFO: ----------------------------------------------------------------------
[09:54:32.118] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C0.dat
[09:54:32.168] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C1.dat
[09:54:32.218] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C2.dat
[09:54:32.269] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C3.dat
[09:54:32.319] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C4.dat
[09:54:32.386] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C5.dat
[09:54:32.453] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C6.dat
[09:54:32.537] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C7.dat
[09:54:32.604] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C8.dat
[09:54:32.704] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C9.dat
[09:54:32.771] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C10.dat
[09:54:32.830] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C11.dat
[09:54:32.897] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C12.dat
[09:54:32.956] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C13.dat
[09:54:33.014] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C14.dat
[09:54:33.073] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C15.dat
[09:54:33.170] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[09:54:33.170] <TB2> INFO: ----------------------------------------------------------------------
[09:54:33.170] <TB2> INFO: PixTestReadback::CalibrateVa()
[09:54:33.170] <TB2> INFO: ----------------------------------------------------------------------
[09:54:42.731] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C0.dat
[09:54:42.737] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C1.dat
[09:54:42.743] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C2.dat
[09:54:42.749] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C3.dat
[09:54:42.755] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C4.dat
[09:54:42.762] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C5.dat
[09:54:42.767] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C6.dat
[09:54:42.774] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C7.dat
[09:54:42.779] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C8.dat
[09:54:42.784] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C9.dat
[09:54:42.789] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C10.dat
[09:54:42.794] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C11.dat
[09:54:42.799] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C12.dat
[09:54:42.803] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C13.dat
[09:54:42.808] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C14.dat
[09:54:42.812] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C15.dat
[09:54:42.861] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[09:54:42.861] <TB2> INFO: ----------------------------------------------------------------------
[09:54:42.861] <TB2> INFO: PixTestReadback::readbackVbg()
[09:54:42.861] <TB2> INFO: ----------------------------------------------------------------------
[09:54:50.165] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[09:54:50.166] <TB2> INFO: ----------------------------------------------------------------------
[09:54:50.166] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[09:54:50.166] <TB2> INFO: ----------------------------------------------------------------------
[09:54:50.166] <TB2> INFO: Vbg will be calibrated using Vd calibration
[09:54:50.166] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 157calibrated Vbg = 1.2355 :::*/*/*/*/
[09:54:50.166] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 153.9calibrated Vbg = 1.23428 :::*/*/*/*/
[09:54:50.166] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 152.9calibrated Vbg = 1.23579 :::*/*/*/*/
[09:54:50.166] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 151.6calibrated Vbg = 1.25098 :::*/*/*/*/
[09:54:50.166] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 152.7calibrated Vbg = 1.24832 :::*/*/*/*/
[09:54:50.166] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 160.2calibrated Vbg = 1.24947 :::*/*/*/*/
[09:54:50.166] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 156.3calibrated Vbg = 1.2469 :::*/*/*/*/
[09:54:50.166] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 161.8calibrated Vbg = 1.25451 :::*/*/*/*/
[09:54:50.166] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 158.3calibrated Vbg = 1.25654 :::*/*/*/*/
[09:54:50.166] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 155.3calibrated Vbg = 1.24862 :::*/*/*/*/
[09:54:50.166] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 156calibrated Vbg = 1.24266 :::*/*/*/*/
[09:54:50.166] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 154calibrated Vbg = 1.23758 :::*/*/*/*/
[09:54:50.166] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 155.9calibrated Vbg = 1.23913 :::*/*/*/*/
[09:54:50.166] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 153calibrated Vbg = 1.22768 :::*/*/*/*/
[09:54:50.166] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 153.9calibrated Vbg = 1.23602 :::*/*/*/*/
[09:54:50.166] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 160.4calibrated Vbg = 1.24109 :::*/*/*/*/
[09:54:50.169] <TB2> INFO: ----------------------------------------------------------------------
[09:54:50.169] <TB2> INFO: PixTestReadback::CalibrateIa()
[09:54:50.169] <TB2> INFO: ----------------------------------------------------------------------
[09:57:26.202] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C0.dat
[09:57:26.207] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C1.dat
[09:57:26.212] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C2.dat
[09:57:26.220] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C3.dat
[09:57:26.227] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C4.dat
[09:57:26.233] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C5.dat
[09:57:26.238] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C6.dat
[09:57:26.243] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C7.dat
[09:57:26.248] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C8.dat
[09:57:26.253] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C9.dat
[09:57:26.259] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C10.dat
[09:57:26.265] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C11.dat
[09:57:26.271] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C12.dat
[09:57:26.276] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C13.dat
[09:57:26.281] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C14.dat
[09:57:26.286] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2243_FullQualification_2016-06-08_08h21m_1465366912//002_FulltestPxar_p17//readbackCal_C15.dat
[09:57:26.335] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[09:57:26.336] <TB2> INFO: PixTestReadback::doTest() done
[09:57:26.336] <TB2> INFO: Decoding statistics:
[09:57:26.336] <TB2> INFO: General information:
[09:57:26.336] <TB2> INFO: 16bit words read: 1024
[09:57:26.336] <TB2> INFO: valid events total: 128
[09:57:26.336] <TB2> INFO: empty events: 128
[09:57:26.336] <TB2> INFO: valid events with pixels: 0
[09:57:26.336] <TB2> INFO: valid pixel hits: 0
[09:57:26.336] <TB2> INFO: Event errors: 0
[09:57:26.336] <TB2> INFO: start marker: 0
[09:57:26.336] <TB2> INFO: stop marker: 0
[09:57:26.336] <TB2> INFO: overflow: 0
[09:57:26.336] <TB2> INFO: invalid 5bit words: 0
[09:57:26.336] <TB2> INFO: invalid XOR eye diagram: 0
[09:57:26.336] <TB2> INFO: frame (failed synchr.): 0
[09:57:26.336] <TB2> INFO: idle data (no TBM trl): 0
[09:57:26.336] <TB2> INFO: no data (only TBM hdr): 0
[09:57:26.336] <TB2> INFO: TBM errors: 0
[09:57:26.336] <TB2> INFO: flawed TBM headers: 0
[09:57:26.336] <TB2> INFO: flawed TBM trailers: 0
[09:57:26.336] <TB2> INFO: event ID mismatches: 0
[09:57:26.336] <TB2> INFO: ROC errors: 0
[09:57:26.336] <TB2> INFO: missing ROC header(s): 0
[09:57:26.336] <TB2> INFO: misplaced readback start: 0
[09:57:26.336] <TB2> INFO: Pixel decoding errors: 0
[09:57:26.336] <TB2> INFO: pixel data incomplete: 0
[09:57:26.336] <TB2> INFO: pixel address: 0
[09:57:26.336] <TB2> INFO: pulse height fill bit: 0
[09:57:26.336] <TB2> INFO: buffer corruption: 0
[09:57:26.360] <TB2> INFO: Decoding statistics:
[09:57:26.360] <TB2> INFO: General information:
[09:57:26.360] <TB2> INFO: 16bit words read: 2755360
[09:57:26.360] <TB2> INFO: valid events total: 176768
[09:57:26.360] <TB2> INFO: empty events: 7864
[09:57:26.360] <TB2> INFO: valid events with pixels: 168904
[09:57:26.360] <TB2> INFO: valid pixel hits: 668064
[09:57:26.360] <TB2> INFO: Event errors: 0
[09:57:26.360] <TB2> INFO: start marker: 0
[09:57:26.360] <TB2> INFO: stop marker: 0
[09:57:26.360] <TB2> INFO: overflow: 0
[09:57:26.360] <TB2> INFO: invalid 5bit words: 0
[09:57:26.360] <TB2> INFO: invalid XOR eye diagram: 0
[09:57:26.360] <TB2> INFO: frame (failed synchr.): 0
[09:57:26.360] <TB2> INFO: idle data (no TBM trl): 0
[09:57:26.360] <TB2> INFO: no data (only TBM hdr): 0
[09:57:26.360] <TB2> INFO: TBM errors: 0
[09:57:26.360] <TB2> INFO: flawed TBM headers: 0
[09:57:26.360] <TB2> INFO: flawed TBM trailers: 0
[09:57:26.360] <TB2> INFO: event ID mismatches: 0
[09:57:26.360] <TB2> INFO: ROC errors: 0
[09:57:26.360] <TB2> INFO: missing ROC header(s): 0
[09:57:26.360] <TB2> INFO: misplaced readback start: 0
[09:57:26.360] <TB2> INFO: Pixel decoding errors: 0
[09:57:26.360] <TB2> INFO: pixel data incomplete: 0
[09:57:26.360] <TB2> INFO: pixel address: 0
[09:57:26.360] <TB2> INFO: pulse height fill bit: 0
[09:57:26.360] <TB2> INFO: buffer corruption: 0
[09:57:26.360] <TB2> INFO: enter test to run
[09:57:26.360] <TB2> INFO: test: exit no parameter change
[09:57:26.448] <TB2> QUIET: Connection to board 149 closed.
[09:57:26.527] <TB2> INFO: pXar: this is the end, my friend