[12:27:49.848] <TB2> INFO: *** Welcome to pxar ***
[12:27:49.848] <TB2> INFO: *** Today: 2016/03/22
[12:27:49.892] <TB2> INFO: *** Version: 9751-dirty
[12:27:49.892] <TB2> INFO: readRocDacs: /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C0.dat .. /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C15.dat
[12:27:49.909] <TB2> INFO: readTbmDacs: /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//tbmParameters_C0a.dat .. /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//tbmParameters_C0b.dat
[12:27:49.912] <TB2> INFO: readMaskFile: /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//defaultMaskFile.dat
[12:27:49.913] <TB2> INFO: readTrimFile: /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters_C0.dat .. /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters_C15.dat
[12:27:50.042] <TB2> INFO: clk: 4
[12:27:50.042] <TB2> INFO: ctr: 4
[12:27:50.042] <TB2> INFO: sda: 19
[12:27:50.042] <TB2> INFO: tin: 9
[12:27:50.042] <TB2> INFO: level: 15
[12:27:50.042] <TB2> INFO: triggerdelay: 0
[12:27:50.042] <TB2> QUIET: Instanciating API for pxar v2.7.5+40~g4fce89b
[12:27:50.042] <TB2> INFO: Log level: INFO
[12:27:50.049] <TB2> INFO: Found DTB DTB_WWXUD2
[12:27:50.060] <TB2> QUIET: Connection to board DTB_WWXUD2 opened.
[12:27:50.062] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 149
HW version: DTB1.2
FW version: 4.4
SW version: 4.6
Options:
USB id: DTB_WWXUD2
MAC address: 40D855118095
Hostname: pixelDTB149
Comment:
------------------------------------------------------
[12:27:50.064] <TB2> INFO: RPC call hashes of host and DTB match: 484264910
[12:27:51.584] <TB2> INFO: DUT info:
[12:27:51.584] <TB2> INFO: The DUT currently contains the following objects:
[12:27:51.584] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:27:51.584] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:27:51.584] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:27:51.584] <TB2> INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[12:27:51.585] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:27:51.585] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:27:51.585] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:27:51.585] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:27:51.585] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:27:51.585] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:27:51.585] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:27:51.585] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:27:51.585] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:27:51.585] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:27:51.585] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:27:51.585] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:27:51.585] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:27:51.585] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:27:51.585] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:27:51.585] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:27:51.987] <TB2> INFO: enter 'restricted' command line mode
[12:27:51.987] <TB2> INFO: enter test to run
[12:27:51.987] <TB2> INFO: test: pretest no parameter change
[12:27:51.987] <TB2> INFO: running: pretest
[12:27:51.994] <TB2> INFO: ----------------------------------------------------------------------
[12:27:51.994] <TB2> INFO: PixTestPretest::programROC()
[12:27:51.994] <TB2> INFO: ----------------------------------------------------------------------
[12:28:10.012] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:28:10.013] <TB2> INFO: IA differences per ROC: 20.9 19.3 19.3 20.1 20.1 20.1 21.7 19.3 19.3 18.5 20.1 18.5 18.5 20.1 20.9 21.7
[12:28:10.139] <TB2> INFO: enter test to run
[12:28:10.139] <TB2> INFO: test: pretest no parameter change
[12:28:10.139] <TB2> INFO: running: pretest
[12:28:10.140] <TB2> INFO: ----------------------------------------------------------------------
[12:28:10.140] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:28:10.140] <TB2> INFO: ----------------------------------------------------------------------
[12:28:31.435] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 383.5 mA = 23.9688 mA/ROC
[12:28:31.435] <TB2> INFO: i(loss) [mA/ROC]: 19.3 20.1 20.1 19.3 18.5 20.1 18.5 19.3 18.5 18.5 18.5 18.5 18.5 18.5 19.3 19.3
[12:28:31.480] <TB2> INFO: enter test to run
[12:28:31.480] <TB2> INFO: test: pretest no parameter change
[12:28:31.480] <TB2> INFO: running: pretest
[12:28:31.480] <TB2> INFO: ----------------------------------------------------------------------
[12:28:31.480] <TB2> INFO: PixTestPretest::findTiming()
[12:28:31.480] <TB2> INFO: ----------------------------------------------------------------------
[12:28:31.480] <TB2> INFO: PixTestCmd::init()

[12:30:01.650] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[12:30:01.650] <TB2> INFO: (success/tries = 100/100), width = 4
[12:30:01.651] <TB2> INFO: enter test to run
[12:30:01.651] <TB2> INFO: test: pretest no parameter change
[12:30:01.651] <TB2> INFO: running: pretest
[12:30:01.652] <TB2> INFO: ----------------------------------------------------------------------
[12:30:01.652] <TB2> INFO: PixTestPretest::findWorkingPixel()
[12:30:01.652] <TB2> INFO: ----------------------------------------------------------------------
[12:30:01.745] <TB2> INFO: Expecting 231680 events.


[12:30:26.139] <TB2> INFO: 231680 events read in total (23837ms).
[12:30:26.143] <TB2> INFO: Test took 24488ms.
[12:30:26.361] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:30:26.439] <TB2> INFO: enter test to run
[12:30:26.439] <TB2> INFO: test: pretest no parameter change
[12:30:26.439] <TB2> INFO: running: pretest
[12:30:26.440] <TB2> INFO: ----------------------------------------------------------------------
[12:30:26.440] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[12:30:26.440] <TB2> INFO: ----------------------------------------------------------------------
[12:30:26.534] <TB2> INFO: Expecting 231680 events.
[12:30:50.932] <TB2> INFO: 231680 events read in total (23841ms).
[12:30:50.937] <TB2> INFO: Test took 24492ms.
[12:30:51.202] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[12:30:51.202] <TB2> INFO: CalDel: 125 171 144 143 167 153 164 141 151 149 121 135 146 136 121 143
[12:30:51.202] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[12:30:51.236] <TB2> INFO: enter test to run
[12:30:51.236] <TB2> INFO: test: pretest no parameter change
[12:30:51.236] <TB2> INFO: running: pretest
[12:30:51.294] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C0.dat
[12:30:51.459] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C1.dat
[12:30:51.628] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C2.dat
[12:30:51.806] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C3.dat
[12:30:52.319] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C4.dat
[12:30:52.379] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C5.dat
[12:30:52.386] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C6.dat
[12:30:52.393] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C7.dat
[12:30:52.398] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C8.dat
[12:30:52.405] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C9.dat
[12:30:52.411] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C10.dat
[12:30:52.417] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C11.dat
[12:30:52.423] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C12.dat
[12:30:52.429] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C13.dat
[12:30:52.435] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C14.dat
[12:30:52.442] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters_C15.dat
[12:30:52.444] <TB2> INFO: enter test to run
[12:30:52.444] <TB2> INFO: test: fulltest no parameter change
[12:30:52.444] <TB2> INFO: running: fulltest
[12:30:52.445] <TB2> INFO: ######################################################################
[12:30:52.445] <TB2> INFO: PixTestFullTest::doTest()
[12:30:52.445] <TB2> INFO: ######################################################################
[12:30:52.446] <TB2> INFO: ######################################################################
[12:30:52.446] <TB2> INFO: PixTestAlive::doTest()
[12:30:52.446] <TB2> INFO: ######################################################################
[12:30:52.447] <TB2> INFO: ----------------------------------------------------------------------
[12:30:52.447] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:30:52.447] <TB2> INFO: ----------------------------------------------------------------------
[12:30:52.735] <TB2> INFO: Expecting 41600 events.
[12:31:00.853] <TB2> INFO: 41600 events read in total (7561ms).
[12:31:00.854] <TB2> INFO: Test took 8404ms.
[12:31:01.097] <TB2> INFO: PixTestAlive::aliveTest() done
[12:31:01.097] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
[12:31:01.098] <TB2> INFO: ----------------------------------------------------------------------
[12:31:01.098] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:31:01.098] <TB2> INFO: ----------------------------------------------------------------------
[12:31:01.368] <TB2> INFO: Expecting 41600 events.
[12:31:06.446] <TB2> INFO: 41600 events read in total (4520ms).
[12:31:06.446] <TB2> INFO: Test took 5346ms.
[12:31:06.446] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:31:06.709] <TB2> INFO: PixTestAlive::maskTest() done
[12:31:06.709] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:31:06.710] <TB2> INFO: ----------------------------------------------------------------------
[12:31:06.710] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:31:06.710] <TB2> INFO: ----------------------------------------------------------------------
[12:31:06.975] <TB2> INFO: Expecting 41600 events.
[12:31:15.076] <TB2> INFO: 41600 events read in total (7544ms).
[12:31:15.076] <TB2> INFO: Test took 8364ms.
[12:31:15.322] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[12:31:15.322] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:31:15.322] <TB2> INFO: PixTestAlive::doTest() done, duration: 22 seconds
[12:31:15.322] <TB2> INFO: Decoding statistics:
[12:31:15.322] <TB2> INFO: General information:
[12:31:15.322] <TB2> INFO: 16bit words read: 0
[12:31:15.322] <TB2> INFO: valid events total: 0
[12:31:15.322] <TB2> INFO: empty events: 0
[12:31:15.322] <TB2> INFO: valid events with pixels: 0
[12:31:15.322] <TB2> INFO: valid pixel hits: 0
[12:31:15.322] <TB2> INFO: Event errors: 0
[12:31:15.322] <TB2> INFO: start marker: 0
[12:31:15.322] <TB2> INFO: stop marker: 0
[12:31:15.322] <TB2> INFO: overflow: 0
[12:31:15.322] <TB2> INFO: invalid 5bit words: 0
[12:31:15.322] <TB2> INFO: invalid XOR eye diagram: 0
[12:31:15.322] <TB2> INFO: frame (failed synchr.): 0
[12:31:15.322] <TB2> INFO: idle data (no TBM trl): 0
[12:31:15.322] <TB2> INFO: no data (only TBM hdr): 0
[12:31:15.322] <TB2> INFO: TBM errors: 0
[12:31:15.322] <TB2> INFO: flawed TBM headers: 0
[12:31:15.322] <TB2> INFO: flawed TBM trailers: 0
[12:31:15.322] <TB2> INFO: event ID mismatches: 0
[12:31:15.322] <TB2> INFO: ROC errors: 0
[12:31:15.322] <TB2> INFO: missing ROC header(s): 0
[12:31:15.322] <TB2> INFO: misplaced readback start: 0
[12:31:15.322] <TB2> INFO: Pixel decoding errors: 0
[12:31:15.323] <TB2> INFO: pixel data incomplete: 0
[12:31:15.323] <TB2> INFO: pixel address: 0
[12:31:15.323] <TB2> INFO: pulse height fill bit: 0
[12:31:15.323] <TB2> INFO: buffer corruption: 0
[12:31:15.329] <TB2> INFO: ######################################################################
[12:31:15.329] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:31:15.329] <TB2> INFO: ######################################################################
[12:31:15.333] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:31:15.344] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:31:15.344] <TB2> INFO: run 1 of 1
[12:31:15.610] <TB2> INFO: Expecting 3120000 events.
[12:33:05.292] <TB2> INFO: 876415 events read in total (109125ms).
[12:34:54.673] <TB2> INFO: 1742885 events read in total (218507ms).
[12:36:44.690] <TB2> INFO: 2618895 events read in total (328524ms).
[12:37:47.283] <TB2> INFO: 3120000 events read in total (391116ms).
[12:37:47.332] <TB2> INFO: Test took 391987ms.
[12:38:11.416] <TB2> INFO: PixTestBBMap::doTest() done, duration: 416 seconds
[12:38:11.416] <TB2> INFO: number of dead bumps (per ROC): 3 0 0 0 1 1 0 0 1 0 1 0 0 0 0 21
[12:38:11.416] <TB2> INFO: separation cut (per ROC): 96 90 83 91 80 102 89 95 91 81 103 99 90 84 103 87
[12:38:11.416] <TB2> INFO: Decoding statistics:
[12:38:11.416] <TB2> INFO: General information:
[12:38:11.416] <TB2> INFO: 16bit words read: 0
[12:38:11.416] <TB2> INFO: valid events total: 0
[12:38:11.416] <TB2> INFO: empty events: 0
[12:38:11.416] <TB2> INFO: valid events with pixels: 0
[12:38:11.416] <TB2> INFO: valid pixel hits: 0
[12:38:11.416] <TB2> INFO: Event errors: 0
[12:38:11.416] <TB2> INFO: start marker: 0
[12:38:11.416] <TB2> INFO: stop marker: 0
[12:38:11.416] <TB2> INFO: overflow: 0
[12:38:11.417] <TB2> INFO: invalid 5bit words: 0
[12:38:11.417] <TB2> INFO: invalid XOR eye diagram: 0
[12:38:11.417] <TB2> INFO: frame (failed synchr.): 0
[12:38:11.417] <TB2> INFO: idle data (no TBM trl): 0
[12:38:11.417] <TB2> INFO: no data (only TBM hdr): 0
[12:38:11.417] <TB2> INFO: TBM errors: 0
[12:38:11.417] <TB2> INFO: flawed TBM headers: 0
[12:38:11.417] <TB2> INFO: flawed TBM trailers: 0
[12:38:11.417] <TB2> INFO: event ID mismatches: 0
[12:38:11.417] <TB2> INFO: ROC errors: 0
[12:38:11.417] <TB2> INFO: missing ROC header(s): 0
[12:38:11.417] <TB2> INFO: misplaced readback start: 0
[12:38:11.417] <TB2> INFO: Pixel decoding errors: 0
[12:38:11.417] <TB2> INFO: pixel data incomplete: 0
[12:38:11.417] <TB2> INFO: pixel address: 0
[12:38:11.417] <TB2> INFO: pulse height fill bit: 0
[12:38:11.417] <TB2> INFO: buffer corruption: 0
[12:38:11.495] <TB2> INFO: ######################################################################
[12:38:11.495] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:38:11.495] <TB2> INFO: ######################################################################
[12:38:11.495] <TB2> INFO: ----------------------------------------------------------------------
[12:38:11.495] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:38:11.495] <TB2> INFO: ----------------------------------------------------------------------
[12:38:11.495] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:38:11.503] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[12:38:11.503] <TB2> INFO: run 1 of 1
[12:38:11.766] <TB2> INFO: Expecting 26208000 events.
[12:39:53.487] <TB2> INFO: 905600 events read in total (101164ms).
[12:41:34.558] <TB2> INFO: 1794750 events read in total (202235ms).
[12:43:15.502] <TB2> INFO: 2681800 events read in total (303179ms).
[12:44:56.584] <TB2> INFO: 3565350 events read in total (404261ms).
[12:46:37.134] <TB2> INFO: 4447550 events read in total (504811ms).
[12:48:18.011] <TB2> INFO: 5330550 events read in total (605688ms).
[12:49:58.754] <TB2> INFO: 6213950 events read in total (706431ms).
[12:51:39.685] <TB2> INFO: 7094850 events read in total (807362ms).
[12:53:19.134] <TB2> INFO: 7974450 events read in total (906811ms).
[12:54:59.292] <TB2> INFO: 8855450 events read in total (1006969ms).
[12:56:39.969] <TB2> INFO: 9737100 events read in total (1107646ms).
[12:58:20.832] <TB2> INFO: 10613900 events read in total (1208509ms).
[13:00:01.447] <TB2> INFO: 11492450 events read in total (1309124ms).
[13:01:42.471] <TB2> INFO: 12372200 events read in total (1410148ms).
[13:03:23.149] <TB2> INFO: 13246850 events read in total (1510826ms).
[13:05:03.946] <TB2> INFO: 14116300 events read in total (1611623ms).
[13:06:44.767] <TB2> INFO: 14983050 events read in total (1712444ms).
[13:08:25.569] <TB2> INFO: 15850100 events read in total (1813246ms).
[13:10:05.925] <TB2> INFO: 16714350 events read in total (1913602ms).
[13:11:46.551] <TB2> INFO: 17577000 events read in total (2014228ms).
[13:13:27.068] <TB2> INFO: 18443700 events read in total (2114745ms).
[13:15:07.632] <TB2> INFO: 19307800 events read in total (2215309ms).
[13:16:48.296] <TB2> INFO: 20170550 events read in total (2315973ms).
[13:18:28.951] <TB2> INFO: 21032650 events read in total (2416628ms).
[13:20:09.705] <TB2> INFO: 21895750 events read in total (2517382ms).
[13:21:50.388] <TB2> INFO: 22757350 events read in total (2618065ms).
[13:23:30.107] <TB2> INFO: 23620150 events read in total (2717784ms).
[13:25:10.712] <TB2> INFO: 24483250 events read in total (2818389ms).
[13:26:51.433] <TB2> INFO: 25346900 events read in total (2919110ms).
[13:28:29.301] <TB2> INFO: 26208000 events read in total (3016978ms).
[13:28:29.338] <TB2> INFO: Test took 3017835ms.
[13:28:29.568] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:28:31.059] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:28:32.623] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:28:34.228] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:28:35.775] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:28:37.327] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:28:39.041] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:28:40.564] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:28:41.994] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:28:43.409] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:28:44.839] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:28:46.234] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:28:47.744] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:28:49.402] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:28:51.064] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:28:52.607] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[13:28:54.222] <TB2> INFO: PixTestScurves::scurves() done
[13:28:54.222] <TB2> INFO: Vcal mean: 90.41 84.06 79.35 88.89 78.36 96.94 89.93 90.14 92.85 85.57 100.17 109.06 91.52 83.66 92.46 99.84
[13:28:54.222] <TB2> INFO: Vcal RMS: 5.68 5.32 4.59 5.66 3.90 5.52 5.35 5.79 5.92 5.09 5.46 6.58 5.79 4.86 6.49 5.62
[13:28:54.222] <TB2> INFO: PixTestScurves::fullTest() done, duration: 3042 seconds
[13:28:54.222] <TB2> INFO: Decoding statistics:
[13:28:54.222] <TB2> INFO: General information:
[13:28:54.222] <TB2> INFO: 16bit words read: 0
[13:28:54.222] <TB2> INFO: valid events total: 0
[13:28:54.222] <TB2> INFO: empty events: 0
[13:28:54.222] <TB2> INFO: valid events with pixels: 0
[13:28:54.223] <TB2> INFO: valid pixel hits: 0
[13:28:54.223] <TB2> INFO: Event errors: 0
[13:28:54.223] <TB2> INFO: start marker: 0
[13:28:54.223] <TB2> INFO: stop marker: 0
[13:28:54.223] <TB2> INFO: overflow: 0
[13:28:54.223] <TB2> INFO: invalid 5bit words: 0
[13:28:54.223] <TB2> INFO: invalid XOR eye diagram: 0
[13:28:54.223] <TB2> INFO: frame (failed synchr.): 0
[13:28:54.223] <TB2> INFO: idle data (no TBM trl): 0
[13:28:54.223] <TB2> INFO: no data (only TBM hdr): 0
[13:28:54.223] <TB2> INFO: TBM errors: 0
[13:28:54.223] <TB2> INFO: flawed TBM headers: 0
[13:28:54.223] <TB2> INFO: flawed TBM trailers: 0
[13:28:54.223] <TB2> INFO: event ID mismatches: 0
[13:28:54.223] <TB2> INFO: ROC errors: 0
[13:28:54.223] <TB2> INFO: missing ROC header(s): 0
[13:28:54.223] <TB2> INFO: misplaced readback start: 0
[13:28:54.223] <TB2> INFO: Pixel decoding errors: 0
[13:28:54.223] <TB2> INFO: pixel data incomplete: 0
[13:28:54.223] <TB2> INFO: pixel address: 0
[13:28:54.223] <TB2> INFO: pulse height fill bit: 0
[13:28:54.223] <TB2> INFO: buffer corruption: 0
[13:28:54.299] <TB2> INFO: ######################################################################
[13:28:54.299] <TB2> INFO: PixTestTrim::doTest()
[13:28:54.299] <TB2> INFO: ######################################################################
[13:28:54.300] <TB2> INFO: ----------------------------------------------------------------------
[13:28:54.300] <TB2> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[13:28:54.300] <TB2> INFO: ----------------------------------------------------------------------
[13:28:54.399] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:28:54.399] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:28:54.408] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:28:54.408] <TB2> INFO: run 1 of 1
[13:28:54.703] <TB2> INFO: Expecting 5025280 events.
[13:30:44.625] <TB2> INFO: 1088704 events read in total (109365ms).
[13:32:34.891] <TB2> INFO: 2169240 events read in total (219631ms).
[13:34:24.661] <TB2> INFO: 3248792 events read in total (329401ms).
[13:36:14.833] <TB2> INFO: 4333056 events read in total (439573ms).
[13:37:24.345] <TB2> INFO: 5025280 events read in total (509085ms).
[13:37:24.368] <TB2> INFO: Test took 509960ms.
[13:37:44.771] <TB2> INFO: ROC 0 VthrComp = 94
[13:37:44.772] <TB2> INFO: ROC 1 VthrComp = 85
[13:37:44.772] <TB2> INFO: ROC 2 VthrComp = 81
[13:37:44.772] <TB2> INFO: ROC 3 VthrComp = 89
[13:37:44.772] <TB2> INFO: ROC 4 VthrComp = 81
[13:37:44.772] <TB2> INFO: ROC 5 VthrComp = 100
[13:37:44.772] <TB2> INFO: ROC 6 VthrComp = 91
[13:37:44.772] <TB2> INFO: ROC 7 VthrComp = 95
[13:37:44.772] <TB2> INFO: ROC 8 VthrComp = 96
[13:37:44.773] <TB2> INFO: ROC 9 VthrComp = 87
[13:37:44.773] <TB2> INFO: ROC 10 VthrComp = 101
[13:37:44.773] <TB2> INFO: ROC 11 VthrComp = 99
[13:37:44.773] <TB2> INFO: ROC 12 VthrComp = 91
[13:37:44.773] <TB2> INFO: ROC 13 VthrComp = 86
[13:37:44.773] <TB2> INFO: ROC 14 VthrComp = 95
[13:37:44.773] <TB2> INFO: ROC 15 VthrComp = 100
[13:37:44.773] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:37:44.773] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:37:44.783] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:37:44.783] <TB2> INFO: run 1 of 1
[13:37:45.057] <TB2> INFO: Expecting 5025280 events.
[13:39:30.133] <TB2> INFO: 756648 events read in total (104519ms).
[13:41:14.745] <TB2> INFO: 1511616 events read in total (209131ms).
[13:42:59.748] <TB2> INFO: 2266912 events read in total (314134ms).
[13:44:44.732] <TB2> INFO: 3018256 events read in total (419118ms).
[13:46:29.385] <TB2> INFO: 3764216 events read in total (523771ms).
[13:48:14.333] <TB2> INFO: 4509248 events read in total (628719ms).
[13:49:26.914] <TB2> INFO: 5025280 events read in total (701300ms).
[13:49:26.956] <TB2> INFO: Test took 702173ms.
[13:49:50.535] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 59.7478 for pixel 20/31 mean/min/max = 45.9543/32.0645/59.8441
[13:49:50.536] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 59.9848 for pixel 0/9 mean/min/max = 46.1553/32.174/60.1366
[13:49:50.536] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 58.7688 for pixel 22/4 mean/min/max = 45.751/32.6402/58.8619
[13:49:50.536] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 60.1302 for pixel 4/7 mean/min/max = 46.1984/32.207/60.1897
[13:49:50.536] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 55.7673 for pixel 15/11 mean/min/max = 44.4128/32.4715/56.3542
[13:49:50.537] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 58.628 for pixel 51/75 mean/min/max = 45.3537/32.0066/58.7008
[13:49:50.537] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 59.3724 for pixel 0/4 mean/min/max = 46.0976/32.8197/59.3754
[13:49:50.537] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 58.6195 for pixel 0/70 mean/min/max = 45.1754/31.6366/58.7141
[13:49:50.537] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 58.7266 for pixel 3/79 mean/min/max = 45.428/32.1206/58.7354
[13:49:50.538] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 58.8282 for pixel 5/3 mean/min/max = 45.7813/32.7264/58.8362
[13:49:50.538] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 58.9064 for pixel 0/55 mean/min/max = 45.3702/31.7474/58.9929
[13:49:50.538] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 68.6083 for pixel 0/57 mean/min/max = 49.7314/30.8398/68.6231
[13:49:50.538] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 60.2721 for pixel 11/4 mean/min/max = 46.6857/32.6401/60.7313
[13:49:50.539] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 57.987 for pixel 7/73 mean/min/max = 45.0472/31.9547/58.1397
[13:49:50.539] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 61.9787 for pixel 0/70 mean/min/max = 46.2443/30.4647/62.0239
[13:49:50.539] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 58.0577 for pixel 16/1 mean/min/max = 45.034/31.8216/58.2464
[13:49:50.539] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:49:50.630] <TB2> INFO: Expecting 411648 events.
[13:50:23.897] <TB2> INFO: 411648 events read in total (32710ms).
[13:50:23.902] <TB2> INFO: Expecting 411648 events.
[13:50:56.679] <TB2> INFO: 411648 events read in total (32357ms).
[13:50:56.685] <TB2> INFO: Expecting 411648 events.
[13:51:29.572] <TB2> INFO: 411648 events read in total (32461ms).
[13:51:29.582] <TB2> INFO: Expecting 411648 events.
[13:52:02.635] <TB2> INFO: 411648 events read in total (32638ms).
[13:52:02.646] <TB2> INFO: Expecting 411648 events.
[13:52:35.343] <TB2> INFO: 411648 events read in total (32276ms).
[13:52:35.355] <TB2> INFO: Expecting 411648 events.
[13:53:07.845] <TB2> INFO: 411648 events read in total (32067ms).
[13:53:07.859] <TB2> INFO: Expecting 411648 events.
[13:53:40.214] <TB2> INFO: 411648 events read in total (31934ms).
[13:53:40.230] <TB2> INFO: Expecting 411648 events.
[13:54:13.371] <TB2> INFO: 411648 events read in total (32721ms).
[13:54:13.388] <TB2> INFO: Expecting 411648 events.
[13:54:46.306] <TB2> INFO: 411648 events read in total (32499ms).
[13:54:46.325] <TB2> INFO: Expecting 411648 events.
[13:55:19.542] <TB2> INFO: 411648 events read in total (32810ms).
[13:55:19.565] <TB2> INFO: Expecting 411648 events.
[13:55:52.618] <TB2> INFO: 411648 events read in total (32642ms).
[13:55:52.640] <TB2> INFO: Expecting 411648 events.
[13:56:25.434] <TB2> INFO: 411648 events read in total (32381ms).
[13:56:25.459] <TB2> INFO: Expecting 411648 events.
[13:56:58.599] <TB2> INFO: 411648 events read in total (32727ms).
[13:56:58.624] <TB2> INFO: Expecting 411648 events.
[13:57:31.717] <TB2> INFO: 411648 events read in total (32690ms).
[13:57:31.748] <TB2> INFO: Expecting 411648 events.
[13:58:04.885] <TB2> INFO: 411648 events read in total (32735ms).
[13:58:04.918] <TB2> INFO: Expecting 411648 events.
[13:58:37.769] <TB2> INFO: 411648 events read in total (32449ms).
[13:58:37.808] <TB2> INFO: Test took 527269ms.
[13:58:38.674] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:58:38.682] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[13:58:38.682] <TB2> INFO: run 1 of 1
[13:58:38.945] <TB2> INFO: Expecting 5025280 events.
[14:00:24.604] <TB2> INFO: 742376 events read in total (105102ms).
[14:02:09.315] <TB2> INFO: 1483776 events read in total (209813ms).
[14:03:53.748] <TB2> INFO: 2225032 events read in total (314246ms).
[14:05:38.369] <TB2> INFO: 2962208 events read in total (418867ms).
[14:07:22.790] <TB2> INFO: 3693624 events read in total (523288ms).
[14:09:06.972] <TB2> INFO: 4422968 events read in total (627470ms).
[14:10:33.096] <TB2> INFO: 5025280 events read in total (713594ms).
[14:10:33.150] <TB2> INFO: Test took 714468ms.
[14:10:56.548] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 5.600229 .. 255.000000
[14:10:56.623] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 5 .. 255 (-1/-1) hits flags = 528 (plus default)
[14:10:56.631] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:10:56.631] <TB2> INFO: run 1 of 1
[14:10:56.894] <TB2> INFO: Expecting 8353280 events.
[14:12:41.518] <TB2> INFO: 705688 events read in total (104067ms).
[14:14:25.083] <TB2> INFO: 1411072 events read in total (207632ms).
[14:16:09.259] <TB2> INFO: 2116864 events read in total (311808ms).
[14:17:52.999] <TB2> INFO: 2822424 events read in total (415548ms).
[14:19:37.384] <TB2> INFO: 3528344 events read in total (519933ms).
[14:21:21.329] <TB2> INFO: 4234080 events read in total (623878ms).
[14:23:04.279] <TB2> INFO: 4939808 events read in total (726828ms).
[14:24:48.053] <TB2> INFO: 5644960 events read in total (830602ms).
[14:26:31.842] <TB2> INFO: 6349760 events read in total (934391ms).
[14:28:16.441] <TB2> INFO: 7053936 events read in total (1038990ms).
[14:30:00.569] <TB2> INFO: 7758360 events read in total (1143118ms).
[14:31:28.567] <TB2> INFO: 8353280 events read in total (1231116ms).
[14:31:28.671] <TB2> INFO: Test took 1232040ms.
[14:31:57.287] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 16.753734 .. 46.673153
[14:31:57.366] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 6 .. 56 (-1/-1) hits flags = 528 (plus default)
[14:31:57.374] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:31:57.374] <TB2> INFO: run 1 of 1
[14:31:57.648] <TB2> INFO: Expecting 1697280 events.
[14:33:46.080] <TB2> INFO: 924560 events read in total (107875ms).
[14:35:16.315] <TB2> INFO: 1697280 events read in total (198110ms).
[14:35:16.333] <TB2> INFO: Test took 198959ms.
[14:35:29.817] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 21.189822 .. 44.404212
[14:35:29.892] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 11 .. 54 (-1/-1) hits flags = 528 (plus default)
[14:35:29.900] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:35:29.900] <TB2> INFO: run 1 of 1
[14:35:30.163] <TB2> INFO: Expecting 1464320 events.
[14:37:18.586] <TB2> INFO: 912344 events read in total (107866ms).
[14:38:24.064] <TB2> INFO: 1464320 events read in total (173344ms).
[14:38:24.081] <TB2> INFO: Test took 174180ms.
[14:38:38.620] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 23.401699 .. 44.404212
[14:38:38.701] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 13 .. 54 (-1/-1) hits flags = 528 (plus default)
[14:38:38.711] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:38:38.711] <TB2> INFO: run 1 of 1
[14:38:38.984] <TB2> INFO: Expecting 1397760 events.
[14:40:27.132] <TB2> INFO: 898984 events read in total (107592ms).
[14:41:27.060] <TB2> INFO: 1397760 events read in total (167520ms).
[14:41:27.077] <TB2> INFO: Test took 168367ms.
[14:41:40.557] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:41:40.558] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[14:41:40.565] <TB2> INFO: dacScan split into 1 runs with ntrig = 8
[14:41:40.565] <TB2> INFO: run 1 of 1
[14:41:40.832] <TB2> INFO: Expecting 1364480 events.
[14:43:27.867] <TB2> INFO: 878968 events read in total (106478ms).
[14:44:26.882] <TB2> INFO: 1364480 events read in total (165493ms).
[14:44:26.893] <TB2> INFO: Test took 166327ms.
[14:44:40.745] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C0.dat
[14:44:40.750] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C1.dat
[14:44:40.754] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C2.dat
[14:44:40.757] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C3.dat
[14:44:40.764] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C4.dat
[14:44:40.768] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C5.dat
[14:44:40.772] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C6.dat
[14:44:40.776] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C7.dat
[14:44:40.780] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C8.dat
[14:44:40.784] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C9.dat
[14:44:40.788] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C10.dat
[14:44:40.791] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C11.dat
[14:44:40.795] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C12.dat
[14:44:40.799] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C13.dat
[14:44:40.803] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C14.dat
[14:44:40.807] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C15.dat
[14:44:40.812] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters35_C0.dat
[14:44:40.825] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters35_C1.dat
[14:44:40.838] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters35_C2.dat
[14:44:40.855] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters35_C3.dat
[14:44:40.868] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters35_C4.dat
[14:44:40.879] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters35_C5.dat
[14:44:40.892] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters35_C6.dat
[14:44:40.904] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters35_C7.dat
[14:44:40.915] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters35_C8.dat
[14:44:40.929] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters35_C9.dat
[14:44:40.943] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters35_C10.dat
[14:44:40.958] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters35_C11.dat
[14:44:40.970] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters35_C12.dat
[14:44:40.982] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters35_C13.dat
[14:44:40.994] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters35_C14.dat
[14:44:41.006] <TB2> INFO: write trim parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//trimParameters35_C15.dat
[14:44:41.017] <TB2> INFO: PixTestTrim::trimTest() done
[14:44:41.017] <TB2> INFO: vtrim: 105 99 106 102 87 93 87 95 90 100 90 111 99 88 104 92
[14:44:41.017] <TB2> INFO: vthrcomp: 94 85 81 89 81 100 91 95 96 87 101 99 91 86 95 100
[14:44:41.017] <TB2> INFO: vcal mean: 34.98 34.96 34.97 34.94 34.98 34.98 34.94 34.97 35.02 34.97 34.98 35.05 34.99 34.97 34.98 34.95
[14:44:41.017] <TB2> INFO: vcal RMS: 0.96 0.93 0.89 0.94 0.87 0.90 0.89 0.92 0.92 0.98 0.91 1.41 0.95 0.88 1.09 0.93
[14:44:41.017] <TB2> INFO: bits mean: 9.68 9.06 9.56 9.56 9.58 9.11 8.93 9.50 9.27 9.33 9.21 8.54 9.21 9.71 9.31 9.76
[14:44:41.017] <TB2> INFO: bits RMS: 2.58 2.81 2.59 2.59 2.69 2.93 2.80 2.78 2.84 2.67 2.86 2.91 2.66 2.70 2.92 2.68
[14:44:41.025] <TB2> INFO: ----------------------------------------------------------------------
[14:44:41.025] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:44:41.025] <TB2> INFO: ----------------------------------------------------------------------
[14:44:41.029] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:44:41.038] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:44:41.038] <TB2> INFO: run 1 of 1
[14:44:41.303] <TB2> INFO: Expecting 4160000 events.
[14:46:30.593] <TB2> INFO: 930855 events read in total (108733ms).
[14:48:19.324] <TB2> INFO: 1854635 events read in total (217464ms).
[14:50:07.256] <TB2> INFO: 2770150 events read in total (325396ms).
[14:51:55.698] <TB2> INFO: 3682815 events read in total (433838ms).
[14:52:52.521] <TB2> INFO: 4160000 events read in total (490661ms).
[14:52:52.565] <TB2> INFO: Test took 491527ms.
[14:53:21.501] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 187 (-1/-1) hits flags = 528 (plus default)
[14:53:21.513] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[14:53:21.513] <TB2> INFO: run 1 of 1
[14:53:21.816] <TB2> INFO: Expecting 3910400 events.
[14:55:11.558] <TB2> INFO: 922905 events read in total (109185ms).
[14:57:00.490] <TB2> INFO: 1838855 events read in total (218117ms).
[14:58:49.742] <TB2> INFO: 2745455 events read in total (327369ms).
[15:00:38.789] <TB2> INFO: 3649030 events read in total (436416ms).
[15:01:10.424] <TB2> INFO: 3910400 events read in total (468051ms).
[15:01:10.465] <TB2> INFO: Test took 468951ms.
[15:01:38.530] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 173 (-1/-1) hits flags = 528 (plus default)
[15:01:38.539] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:01:38.539] <TB2> INFO: run 1 of 1
[15:01:38.803] <TB2> INFO: Expecting 3619200 events.
[15:03:29.234] <TB2> INFO: 951830 events read in total (109874ms).
[15:05:18.429] <TB2> INFO: 1895030 events read in total (219069ms).
[15:07:07.826] <TB2> INFO: 2826985 events read in total (328466ms).
[15:08:41.047] <TB2> INFO: 3619200 events read in total (421687ms).
[15:08:41.083] <TB2> INFO: Test took 422544ms.
[15:09:08.943] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 173 (-1/-1) hits flags = 528 (plus default)
[15:09:08.951] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:09:08.951] <TB2> INFO: run 1 of 1
[15:09:09.219] <TB2> INFO: Expecting 3619200 events.
[15:11:00.147] <TB2> INFO: 951535 events read in total (110371ms).
[15:12:50.246] <TB2> INFO: 1894250 events read in total (220470ms).
[15:14:40.225] <TB2> INFO: 2825695 events read in total (330449ms).
[15:16:13.610] <TB2> INFO: 3619200 events read in total (423834ms).
[15:16:13.645] <TB2> INFO: Test took 424693ms.
[15:16:40.206] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 173 (-1/-1) hits flags = 528 (plus default)
[15:16:40.214] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[15:16:40.214] <TB2> INFO: run 1 of 1
[15:16:40.476] <TB2> INFO: Expecting 3619200 events.
[15:18:30.160] <TB2> INFO: 951325 events read in total (109127ms).
[15:20:19.816] <TB2> INFO: 1893830 events read in total (218783ms).
[15:22:09.626] <TB2> INFO: 2825020 events read in total (328593ms).
[15:23:41.443] <TB2> INFO: 3619200 events read in total (420410ms).
[15:23:41.478] <TB2> INFO: Test took 421264ms.
[15:24:06.912] <TB2> INFO: PixTestTrim::trimBitTest() done
[15:24:06.913] <TB2> INFO: PixTestTrim::doTest() done, duration: 6912 seconds
[15:24:06.913] <TB2> INFO: Decoding statistics:
[15:24:06.913] <TB2> INFO: General information:
[15:24:06.913] <TB2> INFO: 16bit words read: 0
[15:24:06.913] <TB2> INFO: valid events total: 0
[15:24:06.913] <TB2> INFO: empty events: 0
[15:24:06.913] <TB2> INFO: valid events with pixels: 0
[15:24:06.913] <TB2> INFO: valid pixel hits: 0
[15:24:06.913] <TB2> INFO: Event errors: 0
[15:24:06.913] <TB2> INFO: start marker: 0
[15:24:06.913] <TB2> INFO: stop marker: 0
[15:24:06.913] <TB2> INFO: overflow: 0
[15:24:06.913] <TB2> INFO: invalid 5bit words: 0
[15:24:06.913] <TB2> INFO: invalid XOR eye diagram: 0
[15:24:06.913] <TB2> INFO: frame (failed synchr.): 0
[15:24:06.913] <TB2> INFO: idle data (no TBM trl): 0
[15:24:06.913] <TB2> INFO: no data (only TBM hdr): 0
[15:24:06.913] <TB2> INFO: TBM errors: 0
[15:24:06.913] <TB2> INFO: flawed TBM headers: 0
[15:24:06.913] <TB2> INFO: flawed TBM trailers: 0
[15:24:06.913] <TB2> INFO: event ID mismatches: 0
[15:24:06.913] <TB2> INFO: ROC errors: 0
[15:24:06.913] <TB2> INFO: missing ROC header(s): 0
[15:24:06.913] <TB2> INFO: misplaced readback start: 0
[15:24:06.913] <TB2> INFO: Pixel decoding errors: 0
[15:24:06.913] <TB2> INFO: pixel data incomplete: 0
[15:24:06.913] <TB2> INFO: pixel address: 0
[15:24:06.913] <TB2> INFO: pulse height fill bit: 0
[15:24:06.913] <TB2> INFO: buffer corruption: 0
[15:24:07.580] <TB2> INFO: ######################################################################
[15:24:07.580] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[15:24:07.580] <TB2> INFO: ######################################################################
[15:24:07.842] <TB2> INFO: Expecting 41600 events.
[15:24:16.007] <TB2> INFO: 41600 events read in total (7608ms).
[15:24:16.008] <TB2> INFO: Test took 8426ms.
[15:24:16.485] <TB2> INFO: Expecting 41600 events.
[15:24:24.640] <TB2> INFO: 41600 events read in total (7598ms).
[15:24:24.641] <TB2> INFO: Test took 8431ms.
[15:24:24.930] <TB2> INFO: Expecting 41600 events.
[15:24:33.190] <TB2> INFO: 41600 events read in total (7703ms).
[15:24:33.191] <TB2> INFO: Test took 8528ms.
[15:24:33.448] <TB2> INFO: Expecting 2560 events.
[15:24:34.442] <TB2> INFO: 2560 events read in total (437ms).
[15:24:34.442] <TB2> INFO: Test took 1237ms.
[15:24:34.748] <TB2> INFO: Expecting 2560 events.
[15:24:35.740] <TB2> INFO: 2560 events read in total (435ms).
[15:24:35.741] <TB2> INFO: Test took 1298ms.
[15:24:36.047] <TB2> INFO: Expecting 2560 events.
[15:24:37.040] <TB2> INFO: 2560 events read in total (436ms).
[15:24:37.040] <TB2> INFO: Test took 1299ms.
[15:24:37.346] <TB2> INFO: Expecting 2560 events.
[15:24:38.338] <TB2> INFO: 2560 events read in total (435ms).
[15:24:38.339] <TB2> INFO: Test took 1298ms.
[15:24:38.645] <TB2> INFO: Expecting 2560 events.
[15:24:39.637] <TB2> INFO: 2560 events read in total (435ms).
[15:24:39.637] <TB2> INFO: Test took 1298ms.
[15:24:39.944] <TB2> INFO: Expecting 2560 events.
[15:24:40.938] <TB2> INFO: 2560 events read in total (437ms).
[15:24:40.939] <TB2> INFO: Test took 1302ms.
[15:24:41.245] <TB2> INFO: Expecting 2560 events.
[15:24:42.238] <TB2> INFO: 2560 events read in total (436ms).
[15:24:42.239] <TB2> INFO: Test took 1298ms.
[15:24:42.546] <TB2> INFO: Expecting 2560 events.
[15:24:43.535] <TB2> INFO: 2560 events read in total (434ms).
[15:24:43.536] <TB2> INFO: Test took 1297ms.
[15:24:43.842] <TB2> INFO: Expecting 2560 events.
[15:24:44.830] <TB2> INFO: 2560 events read in total (431ms).
[15:24:44.830] <TB2> INFO: Test took 1294ms.
[15:24:45.136] <TB2> INFO: Expecting 2560 events.
[15:24:46.127] <TB2> INFO: 2560 events read in total (434ms).
[15:24:46.128] <TB2> INFO: Test took 1297ms.
[15:24:46.433] <TB2> INFO: Expecting 2560 events.
[15:24:47.423] <TB2> INFO: 2560 events read in total (433ms).
[15:24:47.423] <TB2> INFO: Test took 1295ms.
[15:24:47.730] <TB2> INFO: Expecting 2560 events.
[15:24:48.722] <TB2> INFO: 2560 events read in total (435ms).
[15:24:48.722] <TB2> INFO: Test took 1298ms.
[15:24:49.029] <TB2> INFO: Expecting 2560 events.
[15:24:50.020] <TB2> INFO: 2560 events read in total (434ms).
[15:24:50.020] <TB2> INFO: Test took 1297ms.
[15:24:50.326] <TB2> INFO: Expecting 2560 events.
[15:24:51.316] <TB2> INFO: 2560 events read in total (433ms).
[15:24:51.316] <TB2> INFO: Test took 1296ms.
[15:24:51.623] <TB2> INFO: Expecting 2560 events.
[15:24:52.612] <TB2> INFO: 2560 events read in total (432ms).
[15:24:52.612] <TB2> INFO: Test took 1294ms.
[15:24:52.918] <TB2> INFO: Expecting 2560 events.
[15:24:53.908] <TB2> INFO: 2560 events read in total (432ms).
[15:24:53.908] <TB2> INFO: Test took 1295ms.
[15:24:53.912] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:24:54.215] <TB2> INFO: Expecting 655360 events.
[15:25:48.004] <TB2> INFO: 655360 events read in total (53233ms).
[15:25:48.014] <TB2> INFO: Expecting 655360 events.
[15:26:42.199] <TB2> INFO: 655360 events read in total (53783ms).
[15:26:42.212] <TB2> INFO: Expecting 655360 events.
[15:27:36.401] <TB2> INFO: 655360 events read in total (53787ms).
[15:27:36.418] <TB2> INFO: Expecting 655360 events.
[15:28:30.653] <TB2> INFO: 655360 events read in total (53833ms).
[15:28:30.673] <TB2> INFO: Expecting 655360 events.
[15:29:24.836] <TB2> INFO: 655360 events read in total (53760ms).
[15:29:24.860] <TB2> INFO: Expecting 655360 events.
[15:30:19.103] <TB2> INFO: 655360 events read in total (53841ms).
[15:30:19.131] <TB2> INFO: Expecting 655360 events.
[15:31:13.267] <TB2> INFO: 655360 events read in total (53734ms).
[15:31:13.297] <TB2> INFO: Expecting 655360 events.
[15:32:07.527] <TB2> INFO: 655360 events read in total (53828ms).
[15:32:07.561] <TB2> INFO: Expecting 655360 events.
[15:33:01.734] <TB2> INFO: 655360 events read in total (53771ms).
[15:33:01.775] <TB2> INFO: Expecting 655360 events.
[15:33:55.817] <TB2> INFO: 655360 events read in total (53640ms).
[15:33:55.860] <TB2> INFO: Expecting 655360 events.
[15:34:50.045] <TB2> INFO: 655360 events read in total (53782ms).
[15:34:50.094] <TB2> INFO: Expecting 655360 events.
[15:35:44.151] <TB2> INFO: 655360 events read in total (53654ms).
[15:35:44.203] <TB2> INFO: Expecting 655360 events.
[15:36:38.323] <TB2> INFO: 655360 events read in total (53718ms).
[15:36:38.395] <TB2> INFO: Expecting 655360 events.
[15:37:32.144] <TB2> INFO: 655360 events read in total (53347ms).
[15:37:32.202] <TB2> INFO: Expecting 655360 events.
[15:38:26.356] <TB2> INFO: 655360 events read in total (53751ms).
[15:38:26.413] <TB2> INFO: Expecting 655360 events.
[15:39:20.275] <TB2> INFO: 655360 events read in total (53460ms).
[15:39:20.342] <TB2> INFO: Test took 866430ms.
[15:39:20.421] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:39:20.649] <TB2> INFO: Expecting 655360 events.
[15:40:15.130] <TB2> INFO: 655360 events read in total (53924ms).
[15:40:15.139] <TB2> INFO: Expecting 655360 events.
[15:41:09.273] <TB2> INFO: 655360 events read in total (53732ms).
[15:41:09.287] <TB2> INFO: Expecting 655360 events.
[15:42:03.881] <TB2> INFO: 655360 events read in total (54191ms).
[15:42:03.897] <TB2> INFO: Expecting 655360 events.
[15:42:58.226] <TB2> INFO: 655360 events read in total (53926ms).
[15:42:58.244] <TB2> INFO: Expecting 655360 events.
[15:43:53.205] <TB2> INFO: 655360 events read in total (54558ms).
[15:43:53.236] <TB2> INFO: Expecting 655360 events.
[15:44:47.332] <TB2> INFO: 655360 events read in total (53693ms).
[15:44:47.358] <TB2> INFO: Expecting 655360 events.
[15:45:42.098] <TB2> INFO: 655360 events read in total (54338ms).
[15:45:42.127] <TB2> INFO: Expecting 655360 events.
[15:46:36.646] <TB2> INFO: 655360 events read in total (54117ms).
[15:46:36.683] <TB2> INFO: Expecting 655360 events.
[15:47:31.556] <TB2> INFO: 655360 events read in total (54470ms).
[15:47:31.611] <TB2> INFO: Expecting 655360 events.
[15:48:26.247] <TB2> INFO: 655360 events read in total (54234ms).
[15:48:26.286] <TB2> INFO: Expecting 655360 events.
[15:49:20.525] <TB2> INFO: 655360 events read in total (53837ms).
[15:49:20.568] <TB2> INFO: Expecting 655360 events.
[15:50:14.428] <TB2> INFO: 655360 events read in total (53458ms).
[15:50:14.483] <TB2> INFO: Expecting 655360 events.
[15:51:09.682] <TB2> INFO: 655360 events read in total (54796ms).
[15:51:09.732] <TB2> INFO: Expecting 655360 events.
[15:52:03.663] <TB2> INFO: 655360 events read in total (53529ms).
[15:52:03.737] <TB2> INFO: Expecting 655360 events.
[15:52:57.810] <TB2> INFO: 655360 events read in total (53671ms).
[15:52:57.899] <TB2> INFO: Expecting 655360 events.
[15:53:50.815] <TB2> INFO: 655360 events read in total (52514ms).
[15:53:50.877] <TB2> INFO: Test took 870456ms.
[15:53:51.062] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:53:51.068] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:53:51.075] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:53:51.082] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:53:51.089] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:53:51.095] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:53:51.102] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:53:51.109] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:53:51.116] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:53:51.122] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:53:51.129] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:53:51.136] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:53:51.142] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:53:51.149] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:53:51.156] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:53:51.163] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:53:51.169] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:53:51.176] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:53:51.183] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:53:51.189] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:53:51.196] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:53:51.310] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C0.dat
[15:53:51.333] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C1.dat
[15:53:51.339] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C2.dat
[15:53:51.356] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C3.dat
[15:53:51.361] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C4.dat
[15:53:51.367] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C5.dat
[15:53:51.383] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C6.dat
[15:53:51.388] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C7.dat
[15:53:51.394] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C8.dat
[15:53:51.399] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C9.dat
[15:53:51.417] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C10.dat
[15:53:51.458] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C11.dat
[15:53:51.464] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C12.dat
[15:53:51.469] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C13.dat
[15:53:51.474] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C14.dat
[15:53:51.481] <TB2> INFO: write dac parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//dacParameters35_C15.dat
[15:53:51.778] <TB2> INFO: Expecting 41600 events.
[15:53:59.631] <TB2> INFO: 41600 events read in total (7296ms).
[15:53:59.632] <TB2> INFO: Test took 8144ms.
[15:54:00.085] <TB2> INFO: Expecting 41600 events.
[15:54:07.867] <TB2> INFO: 41600 events read in total (7225ms).
[15:54:07.868] <TB2> INFO: Test took 8048ms.
[15:54:08.346] <TB2> INFO: Expecting 41600 events.
[15:54:16.073] <TB2> INFO: 41600 events read in total (7170ms).
[15:54:16.074] <TB2> INFO: Test took 8018ms.
[15:54:16.267] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:16.357] <TB2> INFO: Expecting 2560 events.
[15:54:17.369] <TB2> INFO: 2560 events read in total (455ms).
[15:54:17.369] <TB2> INFO: Test took 1102ms.
[15:54:17.372] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:17.677] <TB2> INFO: Expecting 2560 events.
[15:54:18.686] <TB2> INFO: 2560 events read in total (452ms).
[15:54:18.687] <TB2> INFO: Test took 1315ms.
[15:54:18.690] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:18.995] <TB2> INFO: Expecting 2560 events.
[15:54:20.002] <TB2> INFO: 2560 events read in total (450ms).
[15:54:20.002] <TB2> INFO: Test took 1312ms.
[15:54:20.004] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:20.312] <TB2> INFO: Expecting 2560 events.
[15:54:21.321] <TB2> INFO: 2560 events read in total (452ms).
[15:54:21.321] <TB2> INFO: Test took 1317ms.
[15:54:21.324] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:21.628] <TB2> INFO: Expecting 2560 events.
[15:54:22.643] <TB2> INFO: 2560 events read in total (458ms).
[15:54:22.643] <TB2> INFO: Test took 1319ms.
[15:54:22.645] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:22.950] <TB2> INFO: Expecting 2560 events.
[15:54:23.965] <TB2> INFO: 2560 events read in total (458ms).
[15:54:23.966] <TB2> INFO: Test took 1321ms.
[15:54:23.969] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:24.275] <TB2> INFO: Expecting 2560 events.
[15:54:25.291] <TB2> INFO: 2560 events read in total (459ms).
[15:54:25.291] <TB2> INFO: Test took 1322ms.
[15:54:25.293] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:25.599] <TB2> INFO: Expecting 2560 events.
[15:54:26.606] <TB2> INFO: 2560 events read in total (450ms).
[15:54:26.607] <TB2> INFO: Test took 1314ms.
[15:54:26.609] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:26.916] <TB2> INFO: Expecting 2560 events.
[15:54:27.924] <TB2> INFO: 2560 events read in total (451ms).
[15:54:27.925] <TB2> INFO: Test took 1316ms.
[15:54:27.927] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:28.233] <TB2> INFO: Expecting 2560 events.
[15:54:29.246] <TB2> INFO: 2560 events read in total (456ms).
[15:54:29.246] <TB2> INFO: Test took 1319ms.
[15:54:29.250] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:29.555] <TB2> INFO: Expecting 2560 events.
[15:54:30.567] <TB2> INFO: 2560 events read in total (456ms).
[15:54:30.567] <TB2> INFO: Test took 1317ms.
[15:54:30.571] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:30.876] <TB2> INFO: Expecting 2560 events.
[15:54:31.885] <TB2> INFO: 2560 events read in total (453ms).
[15:54:31.885] <TB2> INFO: Test took 1315ms.
[15:54:31.888] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:32.193] <TB2> INFO: Expecting 2560 events.
[15:54:33.208] <TB2> INFO: 2560 events read in total (458ms).
[15:54:33.208] <TB2> INFO: Test took 1320ms.
[15:54:33.212] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:33.517] <TB2> INFO: Expecting 2560 events.
[15:54:34.534] <TB2> INFO: 2560 events read in total (460ms).
[15:54:34.535] <TB2> INFO: Test took 1323ms.
[15:54:34.538] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:34.843] <TB2> INFO: Expecting 2560 events.
[15:54:35.857] <TB2> INFO: 2560 events read in total (457ms).
[15:54:35.858] <TB2> INFO: Test took 1320ms.
[15:54:35.861] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:36.165] <TB2> INFO: Expecting 2560 events.
[15:54:37.181] <TB2> INFO: 2560 events read in total (459ms).
[15:54:37.182] <TB2> INFO: Test took 1321ms.
[15:54:37.185] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:37.490] <TB2> INFO: Expecting 2560 events.
[15:54:38.507] <TB2> INFO: 2560 events read in total (460ms).
[15:54:38.508] <TB2> INFO: Test took 1323ms.
[15:54:38.511] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:38.816] <TB2> INFO: Expecting 2560 events.
[15:54:39.831] <TB2> INFO: 2560 events read in total (458ms).
[15:54:39.832] <TB2> INFO: Test took 1321ms.
[15:54:39.835] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:40.139] <TB2> INFO: Expecting 2560 events.
[15:54:41.161] <TB2> INFO: 2560 events read in total (465ms).
[15:54:41.162] <TB2> INFO: Test took 1327ms.
[15:54:41.165] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:41.468] <TB2> INFO: Expecting 2560 events.
[15:54:42.487] <TB2> INFO: 2560 events read in total (462ms).
[15:54:42.487] <TB2> INFO: Test took 1322ms.
[15:54:42.492] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:42.795] <TB2> INFO: Expecting 2560 events.
[15:54:43.811] <TB2> INFO: 2560 events read in total (459ms).
[15:54:43.812] <TB2> INFO: Test took 1321ms.
[15:54:43.815] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:44.120] <TB2> INFO: Expecting 2560 events.
[15:54:45.135] <TB2> INFO: 2560 events read in total (457ms).
[15:54:45.136] <TB2> INFO: Test took 1321ms.
[15:54:45.139] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:45.444] <TB2> INFO: Expecting 2560 events.
[15:54:46.457] <TB2> INFO: 2560 events read in total (456ms).
[15:54:46.458] <TB2> INFO: Test took 1319ms.
[15:54:46.460] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:46.765] <TB2> INFO: Expecting 2560 events.
[15:54:47.777] <TB2> INFO: 2560 events read in total (454ms).
[15:54:47.777] <TB2> INFO: Test took 1317ms.
[15:54:47.783] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:48.086] <TB2> INFO: Expecting 2560 events.
[15:54:49.098] <TB2> INFO: 2560 events read in total (455ms).
[15:54:49.098] <TB2> INFO: Test took 1315ms.
[15:54:49.102] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:49.407] <TB2> INFO: Expecting 2560 events.
[15:54:50.425] <TB2> INFO: 2560 events read in total (461ms).
[15:54:50.425] <TB2> INFO: Test took 1323ms.
[15:54:50.428] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:50.732] <TB2> INFO: Expecting 2560 events.
[15:54:51.742] <TB2> INFO: 2560 events read in total (452ms).
[15:54:51.742] <TB2> INFO: Test took 1314ms.
[15:54:51.745] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:52.049] <TB2> INFO: Expecting 2560 events.
[15:54:53.066] <TB2> INFO: 2560 events read in total (460ms).
[15:54:53.066] <TB2> INFO: Test took 1321ms.
[15:54:53.069] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:53.375] <TB2> INFO: Expecting 2560 events.
[15:54:54.388] <TB2> INFO: 2560 events read in total (456ms).
[15:54:54.389] <TB2> INFO: Test took 1320ms.
[15:54:54.393] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:54.696] <TB2> INFO: Expecting 2560 events.
[15:54:55.711] <TB2> INFO: 2560 events read in total (458ms).
[15:54:55.712] <TB2> INFO: Test took 1319ms.
[15:54:55.715] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:56.020] <TB2> INFO: Expecting 2560 events.
[15:54:57.035] <TB2> INFO: 2560 events read in total (458ms).
[15:54:57.035] <TB2> INFO: Test took 1320ms.
[15:54:57.039] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:54:57.344] <TB2> INFO: Expecting 2560 events.
[15:54:58.363] <TB2> INFO: 2560 events read in total (462ms).
[15:54:58.363] <TB2> INFO: Test took 1324ms.
[15:54:58.916] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 1851 seconds
[15:54:58.916] <TB2> INFO: PH scale (per ROC): 80 75 78 73 80 84 71 79 79 71 78 80 80 80 80 76
[15:54:58.916] <TB2> INFO: PH offset (per ROC): 154 165 166 167 163 159 158 173 164 163 163 173 162 150 157 165
[15:54:58.924] <TB2> INFO: Decoding statistics:
[15:54:58.924] <TB2> INFO: General information:
[15:54:58.924] <TB2> INFO: 16bit words read: 91912
[15:54:58.924] <TB2> INFO: valid events total: 10240
[15:54:58.924] <TB2> INFO: empty events: 7742
[15:54:58.924] <TB2> INFO: valid events with pixels: 2498
[15:54:58.924] <TB2> INFO: valid pixel hits: 2498
[15:54:58.924] <TB2> INFO: Event errors: 0
[15:54:58.924] <TB2> INFO: start marker: 0
[15:54:58.924] <TB2> INFO: stop marker: 0
[15:54:58.924] <TB2> INFO: overflow: 0
[15:54:58.924] <TB2> INFO: invalid 5bit words: 0
[15:54:58.924] <TB2> INFO: invalid XOR eye diagram: 0
[15:54:58.924] <TB2> INFO: frame (failed synchr.): 0
[15:54:58.924] <TB2> INFO: idle data (no TBM trl): 0
[15:54:58.924] <TB2> INFO: no data (only TBM hdr): 0
[15:54:58.924] <TB2> INFO: TBM errors: 0
[15:54:58.924] <TB2> INFO: flawed TBM headers: 0
[15:54:58.924] <TB2> INFO: flawed TBM trailers: 0
[15:54:58.924] <TB2> INFO: event ID mismatches: 0
[15:54:58.924] <TB2> INFO: ROC errors: 0
[15:54:58.924] <TB2> INFO: missing ROC header(s): 0
[15:54:58.924] <TB2> INFO: misplaced readback start: 0
[15:54:58.924] <TB2> INFO: Pixel decoding errors: 0
[15:54:58.924] <TB2> INFO: pixel data incomplete: 0
[15:54:58.924] <TB2> INFO: pixel address: 0
[15:54:58.924] <TB2> INFO: pulse height fill bit: 0
[15:54:58.924] <TB2> INFO: buffer corruption: 0
[15:54:59.131] <TB2> INFO: ######################################################################
[15:54:59.131] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[15:54:59.131] <TB2> INFO: ######################################################################
[15:54:59.142] <TB2> INFO: scanning low vcal = 10
[15:54:59.434] <TB2> INFO: Expecting 41600 events.
[15:55:05.122] <TB2> INFO: 41600 events read in total (5130ms).
[15:55:05.123] <TB2> INFO: Test took 5981ms.
[15:55:05.126] <TB2> INFO: scanning low vcal = 20
[15:55:05.431] <TB2> INFO: Expecting 41600 events.
[15:55:11.108] <TB2> INFO: 41600 events read in total (5120ms).
[15:55:11.108] <TB2> INFO: Test took 5982ms.
[15:55:11.110] <TB2> INFO: scanning low vcal = 30
[15:55:11.416] <TB2> INFO: Expecting 41600 events.
[15:55:17.174] <TB2> INFO: 41600 events read in total (5201ms).
[15:55:17.174] <TB2> INFO: Test took 6064ms.
[15:55:17.177] <TB2> INFO: scanning low vcal = 40
[15:55:17.470] <TB2> INFO: Expecting 41600 events.
[15:55:25.936] <TB2> INFO: 41600 events read in total (7909ms).
[15:55:25.937] <TB2> INFO: Test took 8759ms.
[15:55:25.941] <TB2> INFO: scanning low vcal = 50
[15:55:26.234] <TB2> INFO: Expecting 41600 events.
[15:55:34.616] <TB2> INFO: 41600 events read in total (7825ms).
[15:55:34.617] <TB2> INFO: Test took 8676ms.
[15:55:34.620] <TB2> INFO: scanning low vcal = 60
[15:55:34.878] <TB2> INFO: Expecting 41600 events.
[15:55:43.404] <TB2> INFO: 41600 events read in total (7969ms).
[15:55:43.405] <TB2> INFO: Test took 8784ms.
[15:55:43.409] <TB2> INFO: scanning low vcal = 70
[15:55:43.686] <TB2> INFO: Expecting 41600 events.
[15:55:52.135] <TB2> INFO: 41600 events read in total (7892ms).
[15:55:52.136] <TB2> INFO: Test took 8727ms.
[15:55:52.140] <TB2> INFO: scanning low vcal = 80
[15:55:52.401] <TB2> INFO: Expecting 41600 events.
[15:56:00.918] <TB2> INFO: 41600 events read in total (7960ms).
[15:56:00.919] <TB2> INFO: Test took 8779ms.
[15:56:00.922] <TB2> INFO: scanning low vcal = 90
[15:56:01.182] <TB2> INFO: Expecting 41600 events.
[15:56:09.617] <TB2> INFO: 41600 events read in total (7878ms).
[15:56:09.618] <TB2> INFO: Test took 8696ms.
[15:56:09.622] <TB2> INFO: scanning low vcal = 100
[15:56:09.927] <TB2> INFO: Expecting 41600 events.
[15:56:18.453] <TB2> INFO: 41600 events read in total (7969ms).
[15:56:18.454] <TB2> INFO: Test took 8832ms.
[15:56:18.457] <TB2> INFO: scanning low vcal = 110
[15:56:18.765] <TB2> INFO: Expecting 41600 events.
[15:56:27.242] <TB2> INFO: 41600 events read in total (7920ms).
[15:56:27.243] <TB2> INFO: Test took 8786ms.
[15:56:27.247] <TB2> INFO: scanning low vcal = 120
[15:56:27.511] <TB2> INFO: Expecting 41600 events.
[15:56:36.006] <TB2> INFO: 41600 events read in total (7938ms).
[15:56:36.006] <TB2> INFO: Test took 8759ms.
[15:56:36.010] <TB2> INFO: scanning low vcal = 130
[15:56:36.279] <TB2> INFO: Expecting 41600 events.
[15:56:44.761] <TB2> INFO: 41600 events read in total (7925ms).
[15:56:44.762] <TB2> INFO: Test took 8752ms.
[15:56:44.766] <TB2> INFO: scanning low vcal = 140
[15:56:45.027] <TB2> INFO: Expecting 41600 events.
[15:56:53.528] <TB2> INFO: 41600 events read in total (7944ms).
[15:56:53.529] <TB2> INFO: Test took 8763ms.
[15:56:53.533] <TB2> INFO: scanning low vcal = 150
[15:56:53.795] <TB2> INFO: Expecting 41600 events.
[15:57:02.282] <TB2> INFO: 41600 events read in total (7929ms).
[15:57:02.283] <TB2> INFO: Test took 8750ms.
[15:57:02.287] <TB2> INFO: scanning low vcal = 160
[15:57:02.548] <TB2> INFO: Expecting 41600 events.
[15:57:11.046] <TB2> INFO: 41600 events read in total (7941ms).
[15:57:11.047] <TB2> INFO: Test took 8760ms.
[15:57:11.050] <TB2> INFO: scanning low vcal = 170
[15:57:11.309] <TB2> INFO: Expecting 41600 events.
[15:57:19.791] <TB2> INFO: 41600 events read in total (7926ms).
[15:57:19.792] <TB2> INFO: Test took 8742ms.
[15:57:19.797] <TB2> INFO: scanning low vcal = 180
[15:57:20.056] <TB2> INFO: Expecting 41600 events.
[15:57:28.560] <TB2> INFO: 41600 events read in total (7947ms).
[15:57:28.561] <TB2> INFO: Test took 8764ms.
[15:57:28.564] <TB2> INFO: scanning low vcal = 190
[15:57:28.826] <TB2> INFO: Expecting 41600 events.
[15:57:37.319] <TB2> INFO: 41600 events read in total (7936ms).
[15:57:37.320] <TB2> INFO: Test took 8756ms.
[15:57:37.323] <TB2> INFO: scanning low vcal = 200
[15:57:37.582] <TB2> INFO: Expecting 41600 events.
[15:57:46.078] <TB2> INFO: 41600 events read in total (7939ms).
[15:57:46.079] <TB2> INFO: Test took 8756ms.
[15:57:46.083] <TB2> INFO: scanning low vcal = 210
[15:57:46.365] <TB2> INFO: Expecting 41600 events.
[15:57:54.847] <TB2> INFO: 41600 events read in total (7925ms).
[15:57:54.848] <TB2> INFO: Test took 8765ms.
[15:57:54.851] <TB2> INFO: scanning low vcal = 220
[15:57:55.155] <TB2> INFO: Expecting 41600 events.
[15:58:03.659] <TB2> INFO: 41600 events read in total (7947ms).
[15:58:03.660] <TB2> INFO: Test took 8809ms.
[15:58:03.663] <TB2> INFO: scanning low vcal = 230
[15:58:03.968] <TB2> INFO: Expecting 41600 events.
[15:58:12.404] <TB2> INFO: 41600 events read in total (7880ms).
[15:58:12.406] <TB2> INFO: Test took 8743ms.
[15:58:12.409] <TB2> INFO: scanning low vcal = 240
[15:58:12.703] <TB2> INFO: Expecting 41600 events.
[15:58:21.167] <TB2> INFO: 41600 events read in total (7907ms).
[15:58:21.168] <TB2> INFO: Test took 8758ms.
[15:58:21.171] <TB2> INFO: scanning low vcal = 250
[15:58:21.467] <TB2> INFO: Expecting 41600 events.
[15:58:29.933] <TB2> INFO: 41600 events read in total (7909ms).
[15:58:29.934] <TB2> INFO: Test took 8763ms.
[15:58:29.940] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[15:58:30.241] <TB2> INFO: Expecting 41600 events.
[15:58:38.770] <TB2> INFO: 41600 events read in total (7972ms).
[15:58:38.771] <TB2> INFO: Test took 8831ms.
[15:58:38.774] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[15:58:39.041] <TB2> INFO: Expecting 41600 events.
[15:58:47.533] <TB2> INFO: 41600 events read in total (7935ms).
[15:58:47.534] <TB2> INFO: Test took 8759ms.
[15:58:47.537] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[15:58:47.804] <TB2> INFO: Expecting 41600 events.
[15:58:56.185] <TB2> INFO: 41600 events read in total (7824ms).
[15:58:56.186] <TB2> INFO: Test took 8649ms.
[15:58:56.189] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[15:58:56.452] <TB2> INFO: Expecting 41600 events.
[15:59:04.919] <TB2> INFO: 41600 events read in total (7909ms).
[15:59:04.920] <TB2> INFO: Test took 8730ms.
[15:59:04.924] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[15:59:05.186] <TB2> INFO: Expecting 41600 events.
[15:59:13.606] <TB2> INFO: 41600 events read in total (7863ms).
[15:59:13.607] <TB2> INFO: Test took 8683ms.
[15:59:14.673] <TB2> INFO: PixTestGainPedestal::measure() done
[15:59:47.290] <TB2> INFO: PixTestGainPedestal::fit() done
[15:59:47.290] <TB2> INFO: non-linearity mean: 0.958 0.957 0.946 0.954 0.958 0.961 0.956 0.954 0.955 0.953 0.957 0.967 0.954 0.954 0.958 0.955
[15:59:47.290] <TB2> INFO: non-linearity RMS: 0.006 0.005 0.007 0.005 0.006 0.005 0.006 0.006 0.006 0.006 0.005 0.007 0.006 0.005 0.004 0.006
[15:59:47.291] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//phCalibrationFitErr35_C0.dat
[15:59:47.333] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//phCalibrationFitErr35_C1.dat
[15:59:47.374] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//phCalibrationFitErr35_C2.dat
[15:59:47.415] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//phCalibrationFitErr35_C3.dat
[15:59:47.455] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//phCalibrationFitErr35_C4.dat
[15:59:47.495] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//phCalibrationFitErr35_C5.dat
[15:59:47.540] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//phCalibrationFitErr35_C6.dat
[15:59:47.584] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//phCalibrationFitErr35_C7.dat
[15:59:47.627] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//phCalibrationFitErr35_C8.dat
[15:59:47.683] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//phCalibrationFitErr35_C9.dat
[15:59:47.721] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//phCalibrationFitErr35_C10.dat
[15:59:47.771] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//phCalibrationFitErr35_C11.dat
[15:59:47.811] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//phCalibrationFitErr35_C12.dat
[15:59:47.846] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//phCalibrationFitErr35_C13.dat
[15:59:47.896] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//phCalibrationFitErr35_C14.dat
[15:59:47.934] <TB2> INFO: write gain/ped parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//phCalibrationFitErr35_C15.dat
[15:59:47.976] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 288 seconds
[15:59:47.976] <TB2> INFO: Decoding statistics:
[15:59:47.976] <TB2> INFO: General information:
[15:59:47.976] <TB2> INFO: 16bit words read: 2662400
[15:59:47.976] <TB2> INFO: valid events total: 166400
[15:59:47.976] <TB2> INFO: empty events: 0
[15:59:47.976] <TB2> INFO: valid events with pixels: 166400
[15:59:47.976] <TB2> INFO: valid pixel hits: 665550
[15:59:47.976] <TB2> INFO: Event errors: 0
[15:59:47.976] <TB2> INFO: start marker: 0
[15:59:47.976] <TB2> INFO: stop marker: 0
[15:59:47.976] <TB2> INFO: overflow: 0
[15:59:47.976] <TB2> INFO: invalid 5bit words: 0
[15:59:47.976] <TB2> INFO: invalid XOR eye diagram: 0
[15:59:47.976] <TB2> INFO: frame (failed synchr.): 0
[15:59:47.976] <TB2> INFO: idle data (no TBM trl): 0
[15:59:47.976] <TB2> INFO: no data (only TBM hdr): 0
[15:59:47.976] <TB2> INFO: TBM errors: 0
[15:59:47.976] <TB2> INFO: flawed TBM headers: 0
[15:59:47.976] <TB2> INFO: flawed TBM trailers: 0
[15:59:47.976] <TB2> INFO: event ID mismatches: 0
[15:59:47.976] <TB2> INFO: ROC errors: 0
[15:59:47.976] <TB2> INFO: missing ROC header(s): 0
[15:59:47.976] <TB2> INFO: misplaced readback start: 0
[15:59:47.976] <TB2> INFO: Pixel decoding errors: 0
[15:59:47.976] <TB2> INFO: pixel data incomplete: 0
[15:59:47.976] <TB2> INFO: pixel address: 0
[15:59:47.976] <TB2> INFO: pulse height fill bit: 0
[15:59:47.976] <TB2> INFO: buffer corruption: 0
[15:59:47.984] <TB2> INFO: readReadbackCal: /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C0.dat .. /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C15.dat
[15:59:48.066] <TB2> INFO: ######################################################################
[15:59:48.066] <TB2> INFO: PixTestReadback::doTest()
[15:59:48.066] <TB2> INFO: ######################################################################
[15:59:48.066] <TB2> INFO: ----------------------------------------------------------------------
[15:59:48.066] <TB2> INFO: PixTestReadback::CalibrateVd()
[15:59:48.066] <TB2> INFO: ----------------------------------------------------------------------
[15:59:57.669] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C0.dat
[15:59:57.675] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C1.dat
[15:59:57.680] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C2.dat
[15:59:57.685] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C3.dat
[15:59:57.690] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C4.dat
[15:59:57.695] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C5.dat
[15:59:57.700] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C6.dat
[15:59:57.705] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C7.dat
[15:59:57.710] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C8.dat
[15:59:57.715] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C9.dat
[15:59:57.720] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C10.dat
[15:59:57.725] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C11.dat
[15:59:57.730] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C12.dat
[15:59:57.735] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C13.dat
[15:59:57.740] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C14.dat
[15:59:57.745] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C15.dat
[15:59:57.793] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[15:59:57.793] <TB2> INFO: ----------------------------------------------------------------------
[15:59:57.793] <TB2> INFO: PixTestReadback::CalibrateVa()
[15:59:57.793] <TB2> INFO: ----------------------------------------------------------------------
[16:00:07.426] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C0.dat
[16:00:07.431] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C1.dat
[16:00:07.438] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C2.dat
[16:00:07.443] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C3.dat
[16:00:07.448] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C4.dat
[16:00:07.457] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C5.dat
[16:00:07.462] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C6.dat
[16:00:07.468] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C7.dat
[16:00:07.475] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C8.dat
[16:00:07.480] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C9.dat
[16:00:07.485] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C10.dat
[16:00:07.490] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C11.dat
[16:00:07.495] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C12.dat
[16:00:07.501] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C13.dat
[16:00:07.506] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C14.dat
[16:00:07.511] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C15.dat
[16:00:07.560] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:00:07.560] <TB2> INFO: ----------------------------------------------------------------------
[16:00:07.560] <TB2> INFO: PixTestReadback::readbackVbg()
[16:00:07.560] <TB2> INFO: ----------------------------------------------------------------------
[16:00:14.936] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:00:14.945] <TB2> INFO: ----------------------------------------------------------------------
[16:00:14.945] <TB2> INFO: PixTestReadback::getCalibratedVbg()
[16:00:14.945] <TB2> INFO: ----------------------------------------------------------------------
[16:00:14.945] <TB2> INFO: Vbg will be calibrated using Vd calibration
[16:00:14.945] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 142.9calibrated Vbg = 1.20939 :::*/*/*/*/
[16:00:14.945] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 163.1calibrated Vbg = 1.2122 :::*/*/*/*/
[16:00:14.945] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 162.5calibrated Vbg = 1.21442 :::*/*/*/*/
[16:00:14.945] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 153.4calibrated Vbg = 1.22252 :::*/*/*/*/
[16:00:14.945] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 159calibrated Vbg = 1.23303 :::*/*/*/*/
[16:00:14.945] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 152.8calibrated Vbg = 1.22632 :::*/*/*/*/
[16:00:14.945] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 147.5calibrated Vbg = 1.22879 :::*/*/*/*/
[16:00:14.945] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 154.6calibrated Vbg = 1.22852 :::*/*/*/*/
[16:00:14.945] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 149.8calibrated Vbg = 1.2247 :::*/*/*/*/
[16:00:14.945] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 148.5calibrated Vbg = 1.22682 :::*/*/*/*/
[16:00:14.945] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 149.1calibrated Vbg = 1.21658 :::*/*/*/*/
[16:00:14.945] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 160.5calibrated Vbg = 1.22185 :::*/*/*/*/
[16:00:14.945] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 149.6calibrated Vbg = 1.21099 :::*/*/*/*/
[16:00:14.945] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 151.2calibrated Vbg = 1.21298 :::*/*/*/*/
[16:00:14.945] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 149calibrated Vbg = 1.21604 :::*/*/*/*/
[16:00:14.945] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 150.4calibrated Vbg = 1.21115 :::*/*/*/*/
[16:00:14.947] <TB2> INFO: ----------------------------------------------------------------------
[16:00:14.947] <TB2> INFO: PixTestReadback::CalibrateIa()
[16:00:14.947] <TB2> INFO: ----------------------------------------------------------------------
[16:02:51.362] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C0.dat
[16:02:51.368] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C1.dat
[16:02:51.373] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C2.dat
[16:02:51.378] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C3.dat
[16:02:51.383] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C4.dat
[16:02:51.388] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C5.dat
[16:02:51.393] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C6.dat
[16:02:51.398] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C7.dat
[16:02:51.403] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C8.dat
[16:02:51.408] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C9.dat
[16:02:51.413] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C10.dat
[16:02:51.418] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C11.dat
[16:02:51.425] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C12.dat
[16:02:51.430] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C13.dat
[16:02:51.435] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C14.dat
[16:02:51.440] <TB2> INFO: write readback calibration parameters into /home/Reception/FullQualification/M2186_FullQualification_2016-03-22_13h14m_1458648895//000_FulltestPxar_m20//readbackCal_C15.dat
[16:02:51.487] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[16:02:51.488] <TB2> INFO: PixTestReadback::doTest() done
[16:02:51.488] <TB2> INFO: Decoding statistics:
[16:02:51.488] <TB2> INFO: General information:
[16:02:51.488] <TB2> INFO: 16bit words read: 1024
[16:02:51.488] <TB2> INFO: valid events total: 128
[16:02:51.488] <TB2> INFO: empty events: 128
[16:02:51.488] <TB2> INFO: valid events with pixels: 0
[16:02:51.488] <TB2> INFO: valid pixel hits: 0
[16:02:51.488] <TB2> INFO: Event errors: 0
[16:02:51.488] <TB2> INFO: start marker: 0
[16:02:51.488] <TB2> INFO: stop marker: 0
[16:02:51.488] <TB2> INFO: overflow: 0
[16:02:51.488] <TB2> INFO: invalid 5bit words: 0
[16:02:51.488] <TB2> INFO: invalid XOR eye diagram: 0
[16:02:51.488] <TB2> INFO: frame (failed synchr.): 0
[16:02:51.488] <TB2> INFO: idle data (no TBM trl): 0
[16:02:51.488] <TB2> INFO: no data (only TBM hdr): 0
[16:02:51.488] <TB2> INFO: TBM errors: 0
[16:02:51.488] <TB2> INFO: flawed TBM headers: 0
[16:02:51.488] <TB2> INFO: flawed TBM trailers: 0
[16:02:51.488] <TB2> INFO: event ID mismatches: 0
[16:02:51.488] <TB2> INFO: ROC errors: 0
[16:02:51.488] <TB2> INFO: missing ROC header(s): 0
[16:02:51.488] <TB2> INFO: misplaced readback start: 0
[16:02:51.488] <TB2> INFO: Pixel decoding errors: 0
[16:02:51.488] <TB2> INFO: pixel data incomplete: 0
[16:02:51.488] <TB2> INFO: pixel address: 0
[16:02:51.488] <TB2> INFO: pulse height fill bit: 0
[16:02:51.488] <TB2> INFO: buffer corruption: 0
[16:02:51.506] <TB2> INFO: Decoding statistics:
[16:02:51.506] <TB2> INFO: General information:
[16:02:51.506] <TB2> INFO: 16bit words read: 2755336
[16:02:51.506] <TB2> INFO: valid events total: 176768
[16:02:51.506] <TB2> INFO: empty events: 7870
[16:02:51.507] <TB2> INFO: valid events with pixels: 168898
[16:02:51.507] <TB2> INFO: valid pixel hits: 668048
[16:02:51.507] <TB2> INFO: Event errors: 0
[16:02:51.507] <TB2> INFO: start marker: 0
[16:02:51.507] <TB2> INFO: stop marker: 0
[16:02:51.507] <TB2> INFO: overflow: 0
[16:02:51.507] <TB2> INFO: invalid 5bit words: 0
[16:02:51.507] <TB2> INFO: invalid XOR eye diagram: 0
[16:02:51.507] <TB2> INFO: frame (failed synchr.): 0
[16:02:51.507] <TB2> INFO: idle data (no TBM trl): 0
[16:02:51.507] <TB2> INFO: no data (only TBM hdr): 0
[16:02:51.507] <TB2> INFO: TBM errors: 0
[16:02:51.507] <TB2> INFO: flawed TBM headers: 0
[16:02:51.507] <TB2> INFO: flawed TBM trailers: 0
[16:02:51.507] <TB2> INFO: event ID mismatches: 0
[16:02:51.507] <TB2> INFO: ROC errors: 0
[16:02:51.507] <TB2> INFO: missing ROC header(s): 0
[16:02:51.507] <TB2> INFO: misplaced readback start: 0
[16:02:51.507] <TB2> INFO: Pixel decoding errors: 0
[16:02:51.507] <TB2> INFO: pixel data incomplete: 0
[16:02:51.507] <TB2> INFO: pixel address: 0
[16:02:51.507] <TB2> INFO: pulse height fill bit: 0
[16:02:51.507] <TB2> INFO: buffer corruption: 0
[16:02:51.507] <TB2> INFO: enter test to run
[16:02:51.507] <TB2> INFO: test: exit no parameter change
[16:02:51.550] <TB2> QUIET: Connection to board 149 closed.
[16:02:51.630] <TB2> INFO: pXar: this is the end, my friend