[12:31:09.829] <TB2> INFO: *** Welcome to pxar ***
[12:31:09.829] <TB2> INFO: *** Today: 2015/09/02
[12:31:09.829] <TB2> INFO: readRocDacs: /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C0.dat .. /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C15.dat
[12:31:09.831] <TB2> INFO: readTbmDacs: /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//tbmParameters_C0a.dat .. /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//tbmParameters_C0b.dat
[12:31:09.831] <TB2> INFO: readMaskFile: /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//defaultMaskFile.dat
[12:31:09.831] <TB2> INFO: readTrimFile: /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters_C0.dat .. /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters_C15.dat
[12:31:09.933] <TB2> INFO: clk: 4
[12:31:09.933] <TB2> INFO: ctr: 4
[12:31:09.933] <TB2> INFO: sda: 19
[12:31:09.934] <TB2> INFO: tin: 9
[12:31:09.934] <TB2> INFO: level: 15
[12:31:09.934] <TB2> INFO: triggerdelay: 0
[12:31:09.934] <TB2> QUIET: Instanciating API for pxar prod-10
[12:31:09.934] <TB2> INFO: Log level: INFO
[12:31:09.942] <TB2> INFO: Found DTB DTB_WXC55Z
[12:31:09.953] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[12:31:09.956] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.2
SW version: 4.4
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[12:31:09.959] <TB2> INFO: RPC call hashes of host and DTB match: 397073690
[12:31:11.487] <TB2> INFO: DUT info:
[12:31:11.487] <TB2> INFO: The DUT currently contains the following objects:
[12:31:11.487] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:31:11.487] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:31:11.487] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:31:11.487] <TB2> INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[12:31:11.487] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:31:11.487] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:31:11.487] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:31:11.488] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:31:11.488] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:31:11.488] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:31:11.488] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:31:11.488] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:31:11.488] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:31:11.488] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:31:11.488] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:31:11.488] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:31:11.488] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:31:11.488] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:31:11.488] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:31:11.488] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:31:11.889] <TB2> INFO: enter 'restricted' command line mode
[12:31:11.889] <TB2> INFO: enter test to run
[12:31:11.889] <TB2> INFO: test: pretest no parameter change
[12:31:11.889] <TB2> INFO: running: pretest
[12:31:11.896] <TB2> INFO: ######################################################################
[12:31:11.896] <TB2> INFO: PixTestPretest::doTest()
[12:31:11.896] <TB2> INFO: ######################################################################
[12:31:11.897] <TB2> INFO: ----------------------------------------------------------------------
[12:31:11.897] <TB2> INFO: PixTestPretest::programROC()
[12:31:11.897] <TB2> INFO: ----------------------------------------------------------------------
[12:31:29.914] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:31:29.914] <TB2> INFO: IA differences per ROC: 17.7 19.3 20.9 17.7 16.1 19.3 18.5 17.7 20.9 17.7 19.3 16.9 20.1 18.5 18.5 19.3
[12:31:29.993] <TB2> INFO: ----------------------------------------------------------------------
[12:31:29.993] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:31:29.993] <TB2> INFO: ----------------------------------------------------------------------
[12:31:35.576] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 395.5 mA = 24.7188 mA/ROC
[12:31:35.579] <TB2> INFO: ----------------------------------------------------------------------
[12:31:35.579] <TB2> INFO: PixTestPretest::findWorkingPixel()
[12:31:35.579] <TB2> INFO: ----------------------------------------------------------------------
[12:31:35.718] <TB2> INFO: Expecting 231680 events.
[12:31:45.103] <TB2> INFO: 231680 events read in total (8667ms).
[12:31:45.166] <TB2> INFO: Test took 9581ms.
[12:31:45.417] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:31:45.445] <TB2> INFO: ----------------------------------------------------------------------
[12:31:45.445] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[12:31:45.445] <TB2> INFO: ----------------------------------------------------------------------
[12:31:45.582] <TB2> INFO: Expecting 231680 events.
[12:31:55.294] <TB2> INFO: 231680 events read in total (8996ms).
[12:31:55.298] <TB2> INFO: Test took 9848ms.
[12:31:55.621] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[12:31:55.621] <TB2> INFO: CalDel: 150 155 157 170 168 144 162 172 143 143 149 163 146 134 174 140
[12:31:55.621] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[12:31:55.624] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C0.dat
[12:31:55.624] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C1.dat
[12:31:55.624] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C2.dat
[12:31:55.625] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C3.dat
[12:31:55.625] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C4.dat
[12:31:55.625] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C5.dat
[12:31:55.625] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C6.dat
[12:31:55.626] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C7.dat
[12:31:55.626] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C8.dat
[12:31:55.626] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C9.dat
[12:31:55.626] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C10.dat
[12:31:55.626] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C11.dat
[12:31:55.626] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C12.dat
[12:31:55.626] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C13.dat
[12:31:55.627] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C14.dat
[12:31:55.627] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters_C15.dat
[12:31:55.627] <TB2> INFO: write tbm parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//tbmParameters_C0a.dat
[12:31:55.627] <TB2> INFO: write tbm parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//tbmParameters_C0b.dat
[12:31:55.627] <TB2> INFO: PixTestPretest::doTest() done, duration: 43 seconds
[12:31:55.722] <TB2> INFO: enter test to run
[12:31:55.722] <TB2> INFO: test: fulltest no parameter change
[12:31:55.722] <TB2> INFO: running: fulltest
[12:31:55.722] <TB2> INFO: ######################################################################
[12:31:55.722] <TB2> INFO: PixTestFullTest::doTest()
[12:31:55.722] <TB2> INFO: ######################################################################
[12:31:55.724] <TB2> INFO: ######################################################################
[12:31:55.724] <TB2> INFO: PixTestAlive::doTest()
[12:31:55.724] <TB2> INFO: ######################################################################
[12:31:55.725] <TB2> INFO: ----------------------------------------------------------------------
[12:31:55.725] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:31:55.725] <TB2> INFO: ----------------------------------------------------------------------
[12:31:56.044] <TB2> INFO: Expecting 41600 events.
[12:32:00.469] <TB2> INFO: 41600 events read in total (3709ms).
[12:32:00.469] <TB2> INFO: Test took 4742ms.
[12:32:00.475] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:32:00.765] <TB2> INFO: PixTestAlive::aliveTest() done
[12:32:00.765] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0
[12:32:00.766] <TB2> INFO: ----------------------------------------------------------------------
[12:32:00.766] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:32:00.767] <TB2> INFO: ----------------------------------------------------------------------
[12:32:01.084] <TB2> INFO: Expecting 41600 events.
[12:32:04.263] <TB2> INFO: 41600 events read in total (2463ms).
[12:32:04.264] <TB2> INFO: Test took 3496ms.
[12:32:04.264] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:32:04.264] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:32:04.574] <TB2> INFO: PixTestAlive::maskTest() done
[12:32:04.574] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:32:04.576] <TB2> INFO: ----------------------------------------------------------------------
[12:32:04.576] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:32:04.576] <TB2> INFO: ----------------------------------------------------------------------
[12:32:04.945] <TB2> INFO: Expecting 41600 events.
[12:32:09.415] <TB2> INFO: 41600 events read in total (3754ms).
[12:32:09.415] <TB2> INFO: Test took 4838ms.
[12:32:09.421] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:32:09.708] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[12:32:09.708] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:32:09.708] <TB2> INFO: PixTestAlive::doTest() done, duration: 13 seconds
[12:32:09.714] <TB2> INFO: ######################################################################
[12:32:09.714] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:32:09.715] <TB2> INFO: ######################################################################
[12:32:09.717] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 2 (plus default)
[12:32:09.729] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:32:09.729] <TB2> INFO: run 1 of 1
[12:32:10.039] <TB2> INFO: Expecting 3120000 events.
[12:32:48.235] <TB2> INFO: 837995 events read in total (37479ms).
[12:33:25.798] <TB2> INFO: 1665905 events read in total (75043ms).
[12:34:03.932] <TB2> INFO: 2504105 events read in total (113177ms).
[12:34:30.252] <TB2> INFO: 3120000 events read in total (139496ms).
[12:34:30.306] <TB2> INFO: Test took 140577ms.
[12:34:30.409] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:34:57.313] <TB2> INFO: PixTestBBMap::doTest() done, duration: 167 seconds
[12:34:57.313] <TB2> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 14
[12:34:57.313] <TB2> INFO: separation cut (per ROC): 91 85 84 73 75 93 90 95 92 88 91 75 94 73 69 85
[12:34:57.392] <TB2> INFO: ######################################################################
[12:34:57.392] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:34:57.392] <TB2> INFO: ######################################################################
[12:34:57.393] <TB2> INFO: ----------------------------------------------------------------------
[12:34:57.393] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:34:57.393] <TB2> INFO: ----------------------------------------------------------------------
[12:34:57.393] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 0 .. 149 (-1/-1) hits flags = 16 (plus default)
[12:34:57.402] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[12:34:57.402] <TB2> INFO: run 1 of 1
[12:34:57.730] <TB2> INFO: Expecting 31200000 events.
[12:35:22.621] <TB2> INFO: 957000 events read in total (24174ms).
[12:35:47.117] <TB2> INFO: 1896650 events read in total (48670ms).
[12:36:11.297] <TB2> INFO: 2831900 events read in total (72850ms).
[12:36:36.661] <TB2> INFO: 3769350 events read in total (98214ms).
[12:37:03.316] <TB2> INFO: 4701550 events read in total (124869ms).
[12:37:29.878] <TB2> INFO: 5635650 events read in total (151431ms).
[12:37:56.453] <TB2> INFO: 6565900 events read in total (178006ms).
[12:38:23.339] <TB2> INFO: 7499650 events read in total (204892ms).
[12:38:50.140] <TB2> INFO: 8432000 events read in total (231693ms).
[12:39:16.822] <TB2> INFO: 9362450 events read in total (258375ms).
[12:39:43.221] <TB2> INFO: 10294350 events read in total (284774ms).
[12:40:09.980] <TB2> INFO: 11224400 events read in total (311533ms).
[12:40:37.271] <TB2> INFO: 12154800 events read in total (338824ms).
[12:41:04.293] <TB2> INFO: 13081700 events read in total (365846ms).
[12:41:31.070] <TB2> INFO: 14012250 events read in total (392623ms).
[12:41:57.785] <TB2> INFO: 14939100 events read in total (419338ms).
[12:42:24.227] <TB2> INFO: 15864300 events read in total (445780ms).
[12:42:51.268] <TB2> INFO: 16784300 events read in total (472821ms).
[12:43:17.465] <TB2> INFO: 17704000 events read in total (499018ms).
[12:43:44.484] <TB2> INFO: 18623500 events read in total (526038ms).
[12:44:11.356] <TB2> INFO: 19539250 events read in total (552909ms).
[12:44:37.126] <TB2> INFO: 20457600 events read in total (578679ms).
[12:45:03.858] <TB2> INFO: 21372350 events read in total (605411ms).
[12:45:30.411] <TB2> INFO: 22289500 events read in total (631964ms).
[12:45:56.597] <TB2> INFO: 23203250 events read in total (658150ms).
[12:46:23.776] <TB2> INFO: 24121500 events read in total (685329ms).
[12:46:50.311] <TB2> INFO: 25035000 events read in total (711864ms).
[12:47:16.834] <TB2> INFO: 25951050 events read in total (738387ms).
[12:47:43.637] <TB2> INFO: 26864050 events read in total (765190ms).
[12:48:10.044] <TB2> INFO: 27784200 events read in total (791597ms).
[12:48:35.534] <TB2> INFO: 28700300 events read in total (817087ms).
[12:48:59.175] <TB2> INFO: 29620400 events read in total (840728ms).
[12:49:26.508] <TB2> INFO: 30539150 events read in total (868061ms).
[12:49:46.014] <TB2> INFO: 31200000 events read in total (887567ms).
[12:49:46.039] <TB2> INFO: Test took 888637ms.
[12:49:46.123] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:49:46.219] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:49:47.669] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:49:49.067] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:49:50.650] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:49:52.136] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:49:53.663] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:49:55.168] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:49:56.660] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:49:58.075] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:49:59.492] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:50:00.926] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:50:02.451] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:50:03.848] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:50:05.227] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:50:06.721] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:50:08.279] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:50:09.753] <TB2> INFO: PixTestScurves::scurves() done
[12:50:09.753] <TB2> INFO: Vcal mean: 93.97 86.24 85.92 80.65 82.17 87.22 97.52 94.74 94.67 86.46 83.49 83.51 85.96 76.45 81.71 99.23
[12:50:09.753] <TB2> INFO: Vcal RMS: 6.29 5.19 5.40 4.80 4.55 5.48 5.91 6.66 5.93 5.42 5.22 4.96 4.87 4.69 4.33 5.34
[12:50:09.753] <TB2> INFO: PixTestScurves::fullTest() done, duration: 912 seconds
[12:50:09.829] <TB2> INFO: ######################################################################
[12:50:09.829] <TB2> INFO: PixTestTrim::doTest()
[12:50:09.829] <TB2> INFO: ######################################################################
[12:50:09.830] <TB2> INFO: ----------------------------------------------------------------------
[12:50:09.830] <TB2> INFO: PixTestTrim::trimTest() ntrig = 20, vcal = 35
[12:50:09.830] <TB2> INFO: ----------------------------------------------------------------------
[12:50:09.915] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:50:09.915] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 20 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[12:50:09.924] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[12:50:09.924] <TB2> INFO: run 1 of 1
[12:50:10.233] <TB2> INFO: Expecting 13312000 events.
[12:50:42.225] <TB2> INFO: 1083700 events read in total (31273ms).
[12:51:13.791] <TB2> INFO: 2162900 events read in total (62839ms).
[12:51:45.417] <TB2> INFO: 3239660 events read in total (94465ms).
[12:52:16.990] <TB2> INFO: 4314540 events read in total (126038ms).
[12:52:48.565] <TB2> INFO: 5384740 events read in total (157613ms).
[12:53:20.491] <TB2> INFO: 6450540 events read in total (189539ms).
[12:53:52.215] <TB2> INFO: 7522100 events read in total (221263ms).
[12:54:23.963] <TB2> INFO: 8594560 events read in total (253011ms).
[12:54:54.361] <TB2> INFO: 9669340 events read in total (283409ms).
[12:55:25.800] <TB2> INFO: 10742800 events read in total (314848ms).
[12:55:57.768] <TB2> INFO: 11816760 events read in total (346816ms).
[12:56:29.667] <TB2> INFO: 12892500 events read in total (378715ms).
[12:56:41.367] <TB2> INFO: 13312000 events read in total (390415ms).
[12:56:41.399] <TB2> INFO: Test took 391475ms.
[12:56:41.453] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:57:00.778] <TB2> INFO: ROC 0 VthrComp = 96
[12:57:00.778] <TB2> INFO: ROC 1 VthrComp = 91
[12:57:00.778] <TB2> INFO: ROC 2 VthrComp = 93
[12:57:00.778] <TB2> INFO: ROC 3 VthrComp = 85
[12:57:00.779] <TB2> INFO: ROC 4 VthrComp = 87
[12:57:00.779] <TB2> INFO: ROC 5 VthrComp = 95
[12:57:00.779] <TB2> INFO: ROC 6 VthrComp = 97
[12:57:00.779] <TB2> INFO: ROC 7 VthrComp = 95
[12:57:00.779] <TB2> INFO: ROC 8 VthrComp = 99
[12:57:00.779] <TB2> INFO: ROC 9 VthrComp = 92
[12:57:00.779] <TB2> INFO: ROC 10 VthrComp = 91
[12:57:00.779] <TB2> INFO: ROC 11 VthrComp = 88
[12:57:00.779] <TB2> INFO: ROC 12 VthrComp = 93
[12:57:00.779] <TB2> INFO: ROC 13 VthrComp = 83
[12:57:00.779] <TB2> INFO: ROC 14 VthrComp = 88
[12:57:00.780] <TB2> INFO: ROC 15 VthrComp = 106
[12:57:00.780] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:57:00.780] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 20 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[12:57:00.788] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[12:57:00.789] <TB2> INFO: run 1 of 1
[12:57:01.091] <TB2> INFO: Expecting 13312000 events.
[12:57:29.999] <TB2> INFO: 780620 events read in total (28192ms).
[12:57:58.370] <TB2> INFO: 1557640 events read in total (56563ms).
[12:58:26.597] <TB2> INFO: 2334240 events read in total (84790ms).
[12:58:55.247] <TB2> INFO: 3110060 events read in total (113441ms).
[12:59:23.592] <TB2> INFO: 3886400 events read in total (141785ms).
[12:59:51.256] <TB2> INFO: 4662720 events read in total (169449ms).
[13:00:19.534] <TB2> INFO: 5438680 events read in total (197727ms).
[13:00:47.749] <TB2> INFO: 6214760 events read in total (225942ms).
[13:01:15.962] <TB2> INFO: 6988160 events read in total (254155ms).
[13:01:43.881] <TB2> INFO: 7758800 events read in total (282074ms).
[13:02:12.049] <TB2> INFO: 8527340 events read in total (310242ms).
[13:02:38.025] <TB2> INFO: 9295140 events read in total (336218ms).
[13:03:05.942] <TB2> INFO: 10061800 events read in total (364135ms).
[13:03:33.989] <TB2> INFO: 10828060 events read in total (392182ms).
[13:04:01.989] <TB2> INFO: 11593420 events read in total (420182ms).
[13:04:29.999] <TB2> INFO: 12360300 events read in total (448192ms).
[13:04:58.763] <TB2> INFO: 13128440 events read in total (476956ms).
[13:05:04.785] <TB2> INFO: 13312000 events read in total (482978ms).
[13:05:04.836] <TB2> INFO: Test took 484048ms.
[13:05:05.016] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:05:29.602] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 62.7216 for pixel 15/15 mean/min/max = 47.116/31.5104/62.7217
[13:05:29.603] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 59.5283 for pixel 51/72 mean/min/max = 45.8236/32.0841/59.5632
[13:05:29.603] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 58.2686 for pixel 1/79 mean/min/max = 45.566/32.4006/58.7315
[13:05:29.603] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 57.4936 for pixel 17/6 mean/min/max = 44.7082/31.852/57.5644
[13:05:29.604] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 57.3786 for pixel 26/3 mean/min/max = 44.8083/32.2308/57.3857
[13:05:29.604] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 59.2355 for pixel 27/2 mean/min/max = 45.5838/31.8866/59.2811
[13:05:29.604] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 59.8517 for pixel 8/67 mean/min/max = 45.8853/31.7241/60.0464
[13:05:29.604] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 63.4328 for pixel 27/77 mean/min/max = 47.5538/31.6485/63.459
[13:05:29.605] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 61.4767 for pixel 0/15 mean/min/max = 46.739/31.9817/61.4962
[13:05:29.605] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 59.2685 for pixel 19/1 mean/min/max = 45.6662/31.8701/59.4623
[13:05:29.605] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 58.4134 for pixel 15/4 mean/min/max = 45.4314/32.3809/58.4818
[13:05:29.605] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 58.5226 for pixel 23/38 mean/min/max = 45.5775/32.4699/58.6851
[13:05:29.606] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 56.443 for pixel 6/76 mean/min/max = 44.2269/31.8486/56.6052
[13:05:29.606] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 57.56 for pixel 51/4 mean/min/max = 44.5452/31.3242/57.7663
[13:05:29.606] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 57.4626 for pixel 0/25 mean/min/max = 45.4036/33.3352/57.472
[13:05:29.606] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 59.3706 for pixel 17/2 mean/min/max = 46.4317/33.4835/59.38
[13:05:29.606] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:05:29.737] <TB2> INFO: Expecting 1029120 events.
[13:05:54.707] <TB2> INFO: 1029120 events read in total (24254ms).
[13:05:54.713] <TB2> INFO: Expecting 1029120 events.
[13:06:18.646] <TB2> INFO: 1029120 events read in total (23406ms).
[13:06:18.653] <TB2> INFO: Expecting 1029120 events.
[13:06:44.072] <TB2> INFO: 1029120 events read in total (24879ms).
[13:06:44.081] <TB2> INFO: Expecting 1029120 events.
[13:07:10.737] <TB2> INFO: 1029120 events read in total (26124ms).
[13:07:10.749] <TB2> INFO: Expecting 1029120 events.
[13:07:37.415] <TB2> INFO: 1029120 events read in total (26134ms).
[13:07:37.428] <TB2> INFO: Expecting 1029120 events.
[13:08:03.863] <TB2> INFO: 1029120 events read in total (25905ms).
[13:08:03.879] <TB2> INFO: Expecting 1029120 events.
[13:08:30.338] <TB2> INFO: 1029120 events read in total (25931ms).
[13:08:30.358] <TB2> INFO: Expecting 1029120 events.
[13:08:56.430] <TB2> INFO: 1029120 events read in total (25542ms).
[13:08:56.451] <TB2> INFO: Expecting 1029120 events.
[13:09:22.874] <TB2> INFO: 1029120 events read in total (25895ms).
[13:09:22.894] <TB2> INFO: Expecting 1029120 events.
[13:09:49.610] <TB2> INFO: 1029120 events read in total (26188ms).
[13:09:49.633] <TB2> INFO: Expecting 1029120 events.
[13:10:15.663] <TB2> INFO: 1029120 events read in total (25503ms).
[13:10:15.688] <TB2> INFO: Expecting 1029120 events.
[13:10:41.863] <TB2> INFO: 1029120 events read in total (25648ms).
[13:10:41.896] <TB2> INFO: Expecting 1029120 events.
[13:11:08.177] <TB2> INFO: 1029120 events read in total (25754ms).
[13:11:08.205] <TB2> INFO: Expecting 1029120 events.
[13:11:34.086] <TB2> INFO: 1029120 events read in total (25353ms).
[13:11:34.118] <TB2> INFO: Expecting 1029120 events.
[13:11:59.756] <TB2> INFO: 1029120 events read in total (25110ms).
[13:11:59.788] <TB2> INFO: Expecting 1029120 events.
[13:12:26.662] <TB2> INFO: 1029120 events read in total (26347ms).
[13:12:26.698] <TB2> INFO: Test took 417092ms.
[13:12:27.735] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 20 dacrange: 0 .. 199 (-1/-1) hits flags = 16 (plus default)
[13:12:27.744] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[13:12:27.744] <TB2> INFO: run 1 of 1
[13:12:28.048] <TB2> INFO: Expecting 16640000 events.
[13:12:55.822] <TB2> INFO: 725320 events read in total (27058ms).
[13:13:23.035] <TB2> INFO: 1447100 events read in total (54271ms).
[13:13:50.246] <TB2> INFO: 2169040 events read in total (81482ms).
[13:14:17.672] <TB2> INFO: 2890820 events read in total (108908ms).
[13:14:45.902] <TB2> INFO: 3612040 events read in total (137138ms).
[13:15:13.344] <TB2> INFO: 4333640 events read in total (164580ms).
[13:15:40.741] <TB2> INFO: 5054680 events read in total (191977ms).
[13:16:07.966] <TB2> INFO: 5777060 events read in total (219202ms).
[13:16:35.388] <TB2> INFO: 6498760 events read in total (246624ms).
[13:17:03.301] <TB2> INFO: 7219700 events read in total (274537ms).
[13:17:30.683] <TB2> INFO: 7941740 events read in total (301919ms).
[13:17:58.083] <TB2> INFO: 8660800 events read in total (329319ms).
[13:18:25.021] <TB2> INFO: 9377760 events read in total (356257ms).
[13:18:51.660] <TB2> INFO: 10093560 events read in total (382896ms).
[13:19:18.839] <TB2> INFO: 10808140 events read in total (410075ms).
[13:19:46.401] <TB2> INFO: 11522680 events read in total (437637ms).
[13:20:14.031] <TB2> INFO: 12236960 events read in total (465267ms).
[13:20:41.508] <TB2> INFO: 12950420 events read in total (492744ms).
[13:21:09.138] <TB2> INFO: 13662580 events read in total (520374ms).
[13:21:36.001] <TB2> INFO: 14374440 events read in total (547237ms).
[13:22:03.178] <TB2> INFO: 15088160 events read in total (574414ms).
[13:22:28.966] <TB2> INFO: 15800900 events read in total (600202ms).
[13:22:56.587] <TB2> INFO: 16515240 events read in total (627823ms).
[13:23:00.818] <TB2> INFO: 16640000 events read in total (632054ms).
[13:23:00.891] <TB2> INFO: Test took 633147ms.
[13:23:01.107] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:23:25.932] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 0.098077 .. 54.013291
[13:23:26.029] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 20 dacrange: 0 .. 64 (-1/-1) hits flags = 16 (plus default)
[13:23:26.038] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[13:23:26.038] <TB2> INFO: run 1 of 1
[13:23:26.376] <TB2> INFO: Expecting 5408000 events.
[13:23:56.103] <TB2> INFO: 905960 events read in total (29011ms).
[13:24:25.111] <TB2> INFO: 1813120 events read in total (58019ms).
[13:24:53.437] <TB2> INFO: 2719460 events read in total (86345ms).
[13:25:20.286] <TB2> INFO: 3623060 events read in total (113194ms).
[13:25:49.198] <TB2> INFO: 4521100 events read in total (142106ms).
[13:26:17.337] <TB2> INFO: 5408000 events read in total (170245ms).
[13:26:17.355] <TB2> INFO: Test took 171317ms.
[13:26:17.395] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:26:31.662] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 17.032387 .. 45.912118
[13:26:31.737] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 20 dacrange: 7 .. 55 (-1/-1) hits flags = 16 (plus default)
[13:26:31.746] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[13:26:31.746] <TB2> INFO: run 1 of 1
[13:26:32.054] <TB2> INFO: Expecting 4076800 events.
[13:27:01.488] <TB2> INFO: 927220 events read in total (28718ms).
[13:27:30.053] <TB2> INFO: 1854020 events read in total (57283ms).
[13:27:57.537] <TB2> INFO: 2779220 events read in total (84767ms).
[13:28:26.251] <TB2> INFO: 3702320 events read in total (113481ms).
[13:28:38.921] <TB2> INFO: 4076800 events read in total (126151ms).
[13:28:38.932] <TB2> INFO: Test took 127186ms.
[13:28:38.963] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:28:51.489] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 22.153411 .. 42.483504
[13:28:51.565] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 20 dacrange: 12 .. 52 (-1/-1) hits flags = 16 (plus default)
[13:28:51.573] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[13:28:51.573] <TB2> INFO: run 1 of 1
[13:28:51.876] <TB2> INFO: Expecting 3411200 events.
[13:29:20.997] <TB2> INFO: 923280 events read in total (28405ms).
[13:29:50.539] <TB2> INFO: 1846100 events read in total (57947ms).
[13:30:19.540] <TB2> INFO: 2767360 events read in total (86948ms).
[13:30:40.979] <TB2> INFO: 3411200 events read in total (108387ms).
[13:30:40.988] <TB2> INFO: Test took 109415ms.
[13:30:41.014] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:30:54.017] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 24.984181 .. 41.928984
[13:30:54.093] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 20 dacrange: 14 .. 51 (-1/-1) hits flags = 16 (plus default)
[13:30:54.101] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[13:30:54.101] <TB2> INFO: run 1 of 1
[13:30:54.409] <TB2> INFO: Expecting 3161600 events.
[13:31:21.841] <TB2> INFO: 917880 events read in total (26716ms).
[13:31:50.656] <TB2> INFO: 1835460 events read in total (55531ms).
[13:32:19.335] <TB2> INFO: 2752760 events read in total (84210ms).
[13:32:31.849] <TB2> INFO: 3161600 events read in total (96724ms).
[13:32:31.859] <TB2> INFO: Test took 97758ms.
[13:32:31.886] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:32:44.025] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[13:32:44.025] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 20 dacrange: 15 .. 55 (-1/-1) hits flags = 16 (plus default)
[13:32:44.034] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[13:32:44.034] <TB2> INFO: run 1 of 1
[13:32:44.337] <TB2> INFO: Expecting 3411200 events.
[13:33:14.572] <TB2> INFO: 879360 events read in total (29519ms).
[13:33:44.625] <TB2> INFO: 1758560 events read in total (59572ms).
[13:34:14.629] <TB2> INFO: 2637560 events read in total (89577ms).
[13:34:40.419] <TB2> INFO: 3411200 events read in total (115366ms).
[13:34:40.442] <TB2> INFO: Test took 116408ms.
[13:34:40.481] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:34:54.176] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C0.dat
[13:34:54.176] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C1.dat
[13:34:54.177] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C2.dat
[13:34:54.177] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C3.dat
[13:34:54.177] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C4.dat
[13:34:54.177] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C5.dat
[13:34:54.177] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C6.dat
[13:34:54.178] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C7.dat
[13:34:54.178] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C8.dat
[13:34:54.178] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C9.dat
[13:34:54.178] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C10.dat
[13:34:54.178] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C11.dat
[13:34:54.179] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C12.dat
[13:34:54.179] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C13.dat
[13:34:54.179] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C14.dat
[13:34:54.179] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C15.dat
[13:34:54.179] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters35_C0.dat
[13:34:54.188] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters35_C1.dat
[13:34:54.194] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters35_C2.dat
[13:34:54.200] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters35_C3.dat
[13:34:54.206] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters35_C4.dat
[13:34:54.212] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters35_C5.dat
[13:34:54.218] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters35_C6.dat
[13:34:54.224] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters35_C7.dat
[13:34:54.230] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters35_C8.dat
[13:34:54.236] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters35_C9.dat
[13:34:54.242] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters35_C10.dat
[13:34:54.248] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters35_C11.dat
[13:34:54.254] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters35_C12.dat
[13:34:54.260] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters35_C13.dat
[13:34:54.266] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters35_C14.dat
[13:34:54.272] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//trimParameters35_C15.dat
[13:34:54.278] <TB2> INFO: PixTestTrim::trimTest() done
[13:34:54.278] <TB2> INFO: vtrim: 119 95 94 96 96 96 99 114 111 112 107 98 83 96 85 113
[13:34:54.278] <TB2> INFO: vthrcomp: 96 91 93 85 87 95 97 95 99 92 91 88 93 83 88 106
[13:34:54.278] <TB2> INFO: vcal mean: 35.03 34.98 34.99 34.92 34.96 34.98 34.97 34.97 35.01 34.98 34.97 34.95 34.94 34.96 35.01 34.97
[13:34:54.278] <TB2> INFO: vcal RMS: 0.79 0.68 0.71 1.03 0.67 0.66 0.73 0.84 0.71 0.75 0.69 0.70 0.69 0.68 0.64 0.68
[13:34:54.279] <TB2> INFO: bits mean: 9.29 8.64 8.60 9.81 9.45 9.23 9.14 9.09 8.64 9.47 9.27 9.35 9.39 9.40 8.96 8.99
[13:34:54.279] <TB2> INFO: bits RMS: 2.73 3.01 3.01 2.63 2.72 2.78 2.88 2.79 2.98 2.70 2.77 2.67 2.82 2.90 2.76 2.60
[13:34:54.286] <TB2> INFO: ----------------------------------------------------------------------
[13:34:54.286] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 10, vtrims = 254 126 63 32
[13:34:54.286] <TB2> INFO: ----------------------------------------------------------------------
[13:34:54.288] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 10 dacrange: 0 .. 199 (-1/-1) hits flags = 16 (plus default)
[13:34:54.297] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[13:34:54.297] <TB2> INFO: run 1 of 1
[13:34:54.601] <TB2> INFO: Expecting 8320000 events.
[13:35:25.810] <TB2> INFO: 927130 events read in total (30487ms).
[13:35:56.943] <TB2> INFO: 1845220 events read in total (61620ms).
[13:36:26.092] <TB2> INFO: 2761470 events read in total (90769ms).
[13:36:54.288] <TB2> INFO: 3675280 events read in total (118965ms).
[13:37:25.916] <TB2> INFO: 4584160 events read in total (150593ms).
[13:37:57.489] <TB2> INFO: 5489310 events read in total (182166ms).
[13:38:28.019] <TB2> INFO: 6393240 events read in total (212696ms).
[13:38:57.116] <TB2> INFO: 7296370 events read in total (241793ms).
[13:39:28.815] <TB2> INFO: 8205420 events read in total (273492ms).
[13:39:33.692] <TB2> INFO: 8320000 events read in total (278369ms).
[13:39:33.727] <TB2> INFO: Test took 279429ms.
[13:39:33.850] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:40:01.100] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 10 dacrange: 0 .. 170 (-1/-1) hits flags = 16 (plus default)
[13:40:01.108] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[13:40:01.108] <TB2> INFO: run 1 of 1
[13:40:01.428] <TB2> INFO: Expecting 7113600 events.
[13:40:33.854] <TB2> INFO: 953560 events read in total (31710ms).
[13:41:06.169] <TB2> INFO: 1897430 events read in total (64025ms).
[13:41:36.218] <TB2> INFO: 2838400 events read in total (94074ms).
[13:42:07.575] <TB2> INFO: 3775200 events read in total (125431ms).
[13:42:39.244] <TB2> INFO: 4704040 events read in total (157100ms).
[13:43:11.711] <TB2> INFO: 5632130 events read in total (189567ms).
[13:43:40.682] <TB2> INFO: 6560650 events read in total (218538ms).
[13:44:00.609] <TB2> INFO: 7113600 events read in total (238465ms).
[13:44:00.640] <TB2> INFO: Test took 239532ms.
[13:44:00.725] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:44:25.395] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 10 dacrange: 0 .. 157 (-1/-1) hits flags = 16 (plus default)
[13:44:25.404] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[13:44:25.404] <TB2> INFO: run 1 of 1
[13:44:25.705] <TB2> INFO: Expecting 6572800 events.
[13:44:59.136] <TB2> INFO: 987460 events read in total (32715ms).
[13:45:28.614] <TB2> INFO: 1964560 events read in total (62193ms).
[13:46:01.370] <TB2> INFO: 2938240 events read in total (94949ms).
[13:46:35.114] <TB2> INFO: 3902450 events read in total (128693ms).
[13:47:08.844] <TB2> INFO: 4861490 events read in total (162423ms).
[13:47:42.704] <TB2> INFO: 5820660 events read in total (196283ms).
[13:48:07.400] <TB2> INFO: 6572800 events read in total (220979ms).
[13:48:07.429] <TB2> INFO: Test took 222025ms.
[13:48:07.500] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:48:29.688] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 10 dacrange: 0 .. 157 (-1/-1) hits flags = 16 (plus default)
[13:48:29.697] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[13:48:29.697] <TB2> INFO: run 1 of 1
[13:48:30.012] <TB2> INFO: Expecting 6572800 events.
[13:49:03.395] <TB2> INFO: 986960 events read in total (32667ms).
[13:49:36.190] <TB2> INFO: 1963130 events read in total (65462ms).
[13:50:07.353] <TB2> INFO: 2935880 events read in total (96625ms).
[13:50:35.731] <TB2> INFO: 3899580 events read in total (125003ms).
[13:51:06.964] <TB2> INFO: 4858050 events read in total (156236ms).
[13:51:38.156] <TB2> INFO: 5816640 events read in total (187428ms).
[13:52:00.422] <TB2> INFO: 6572800 events read in total (209694ms).
[13:52:00.449] <TB2> INFO: Test took 210752ms.
[13:52:00.518] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:52:23.856] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 10 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[13:52:23.869] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[13:52:23.869] <TB2> INFO: run 1 of 1
[13:52:24.186] <TB2> INFO: Expecting 6656000 events.
[13:52:56.966] <TB2> INFO: 980210 events read in total (32064ms).
[13:53:28.454] <TB2> INFO: 1949920 events read in total (63553ms).
[13:53:59.992] <TB2> INFO: 2915910 events read in total (95091ms).
[13:54:29.979] <TB2> INFO: 3874720 events read in total (125077ms).
[13:55:00.970] <TB2> INFO: 4826930 events read in total (156068ms).
[13:55:28.868] <TB2> INFO: 5779070 events read in total (183966ms).
[13:56:00.267] <TB2> INFO: 6656000 events read in total (215365ms).
[13:56:00.298] <TB2> INFO: Test took 216429ms.
[13:56:00.373] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:56:23.384] <TB2> INFO: PixTestTrim::trimBitTest() done
[13:56:23.385] <TB2> INFO: PixTestTrim::doTest() done, duration: 3973 seconds
[13:56:24.099] <TB2> INFO: ######################################################################
[13:56:24.099] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:56:24.099] <TB2> INFO: ######################################################################
[13:56:24.412] <TB2> INFO: Expecting 41600 events.
[13:56:29.200] <TB2> INFO: 41600 events read in total (4071ms).
[13:56:29.201] <TB2> INFO: Test took 5101ms.
[13:56:29.209] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:56:29.773] <TB2> INFO: Expecting 41600 events.
[13:56:34.302] <TB2> INFO: 41600 events read in total (3813ms).
[13:56:34.302] <TB2> INFO: Test took 4840ms.
[13:56:34.308] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:56:34.660] <TB2> INFO: Expecting 41600 events.
[13:56:39.222] <TB2> INFO: 41600 events read in total (3846ms).
[13:56:39.222] <TB2> INFO: Test took 4886ms.
[13:56:39.229] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:56:39.236] <TB2> INFO: The DUT currently contains the following objects:
[13:56:39.236] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[13:56:39.236] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:56:39.236] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:56:39.236] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:56:39.236] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:39.236] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:39.236] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:39.236] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:39.236] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:39.236] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:39.236] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:39.236] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:39.236] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:39.236] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:39.236] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:39.236] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:39.236] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:39.236] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:39.236] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:39.236] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:39.569] <TB2> INFO: Expecting 2560 events.
[13:56:40.639] <TB2> INFO: 2560 events read in total (354ms).
[13:56:40.640] <TB2> INFO: Test took 1404ms.
[13:56:40.640] <TB2> INFO: The DUT currently contains the following objects:
[13:56:40.640] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[13:56:40.640] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:56:40.640] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:56:40.640] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:56:40.640] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:40.640] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:40.640] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:40.640] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:40.641] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:40.641] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:40.641] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:40.641] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:40.641] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:40.641] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:40.641] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:40.641] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:40.641] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:40.641] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:40.641] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:40.641] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:41.054] <TB2> INFO: Expecting 2560 events.
[13:56:42.137] <TB2> INFO: 2560 events read in total (366ms).
[13:56:42.137] <TB2> INFO: Test took 1496ms.
[13:56:42.138] <TB2> INFO: The DUT currently contains the following objects:
[13:56:42.138] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[13:56:42.138] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:56:42.138] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:56:42.138] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:56:42.138] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:42.138] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:42.138] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:42.138] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:42.138] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:42.138] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:42.138] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:42.138] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:42.138] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:42.138] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:42.138] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:42.139] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:42.139] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:42.139] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:42.139] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:42.139] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:42.552] <TB2> INFO: Expecting 2560 events.
[13:56:43.660] <TB2> INFO: 2560 events read in total (392ms).
[13:56:43.660] <TB2> INFO: Test took 1521ms.
[13:56:43.661] <TB2> INFO: The DUT currently contains the following objects:
[13:56:43.661] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[13:56:43.661] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:56:43.661] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:56:43.661] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:56:43.661] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:43.661] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:43.661] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:43.661] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:43.661] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:43.661] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:43.661] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:43.661] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:43.661] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:43.662] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:43.662] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:43.662] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:43.662] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:43.662] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:43.662] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:43.662] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:44.075] <TB2> INFO: Expecting 2560 events.
[13:56:45.155] <TB2> INFO: 2560 events read in total (364ms).
[13:56:45.155] <TB2> INFO: Test took 1493ms.
[13:56:45.156] <TB2> INFO: The DUT currently contains the following objects:
[13:56:45.156] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[13:56:45.156] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:56:45.156] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:56:45.156] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:56:45.156] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:45.156] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:45.156] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:45.156] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:45.156] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:45.156] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:45.156] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:45.156] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:45.156] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:45.156] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:45.156] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:45.156] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:45.156] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:45.157] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:45.157] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:45.157] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:45.571] <TB2> INFO: Expecting 2560 events.
[13:56:46.656] <TB2> INFO: 2560 events read in total (369ms).
[13:56:46.656] <TB2> INFO: Test took 1499ms.
[13:56:46.657] <TB2> INFO: The DUT currently contains the following objects:
[13:56:46.657] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[13:56:46.657] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:56:46.657] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:56:46.657] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:56:46.657] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:46.657] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:46.657] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:46.657] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:46.657] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:46.657] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:46.657] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:46.657] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:46.657] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:46.657] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:46.657] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:46.657] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:46.658] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:46.658] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:46.658] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:46.658] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:47.071] <TB2> INFO: Expecting 2560 events.
[13:56:48.153] <TB2> INFO: 2560 events read in total (366ms).
[13:56:48.153] <TB2> INFO: Test took 1495ms.
[13:56:48.153] <TB2> INFO: The DUT currently contains the following objects:
[13:56:48.153] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[13:56:48.153] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:56:48.153] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:56:48.153] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:56:48.153] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:48.154] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:48.154] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:48.154] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:48.154] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:48.154] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:48.154] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:48.154] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:48.154] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:48.154] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:48.154] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:48.154] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:48.154] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:48.154] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:48.154] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:48.154] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:48.568] <TB2> INFO: Expecting 2560 events.
[13:56:49.636] <TB2> INFO: 2560 events read in total (352ms).
[13:56:49.637] <TB2> INFO: Test took 1483ms.
[13:56:49.637] <TB2> INFO: The DUT currently contains the following objects:
[13:56:49.637] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[13:56:49.637] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:56:49.637] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:56:49.637] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:56:49.637] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:49.638] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:49.638] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:49.638] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:49.638] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:49.638] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:49.638] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:49.638] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:49.638] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:49.638] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:49.638] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:49.638] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:49.638] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:49.638] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:49.638] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:49.638] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:50.051] <TB2> INFO: Expecting 2560 events.
[13:56:51.133] <TB2> INFO: 2560 events read in total (365ms).
[13:56:51.134] <TB2> INFO: Test took 1496ms.
[13:56:51.134] <TB2> INFO: The DUT currently contains the following objects:
[13:56:51.134] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[13:56:51.134] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:56:51.134] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:56:51.134] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:56:51.134] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:51.134] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:51.134] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:51.134] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:51.134] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:51.135] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:51.135] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:51.135] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:51.135] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:51.135] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:51.135] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:51.135] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:51.135] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:51.135] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:51.135] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:51.135] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:51.548] <TB2> INFO: Expecting 2560 events.
[13:56:52.630] <TB2> INFO: 2560 events read in total (366ms).
[13:56:52.630] <TB2> INFO: Test took 1495ms.
[13:56:52.631] <TB2> INFO: The DUT currently contains the following objects:
[13:56:52.631] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[13:56:52.631] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:56:52.631] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:56:52.631] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:56:52.631] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:52.631] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:52.631] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:52.631] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:52.631] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:52.631] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:52.631] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:52.631] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:52.631] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:52.632] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:52.632] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:52.632] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:52.632] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:52.632] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:52.632] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:52.632] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:53.045] <TB2> INFO: Expecting 2560 events.
[13:56:54.152] <TB2> INFO: 2560 events read in total (391ms).
[13:56:54.153] <TB2> INFO: Test took 1521ms.
[13:56:54.153] <TB2> INFO: The DUT currently contains the following objects:
[13:56:54.153] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[13:56:54.153] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:56:54.153] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:56:54.153] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:56:54.153] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:54.153] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:54.153] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:54.153] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:54.153] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:54.153] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:54.153] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:54.153] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:54.153] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:54.153] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:54.154] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:54.154] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:54.154] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:54.154] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:54.154] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:54.154] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:54.567] <TB2> INFO: Expecting 2560 events.
[13:56:55.637] <TB2> INFO: 2560 events read in total (354ms).
[13:56:55.637] <TB2> INFO: Test took 1483ms.
[13:56:55.638] <TB2> INFO: The DUT currently contains the following objects:
[13:56:55.638] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[13:56:55.638] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:56:55.638] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:56:55.638] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:56:55.638] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:55.638] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:55.638] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:55.638] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:55.638] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:55.638] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:55.638] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:55.638] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:55.638] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:55.638] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:55.638] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:55.638] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:55.638] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:55.638] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:55.638] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:55.638] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:56.052] <TB2> INFO: Expecting 2560 events.
[13:56:57.163] <TB2> INFO: 2560 events read in total (395ms).
[13:56:57.163] <TB2> INFO: Test took 1525ms.
[13:56:57.163] <TB2> INFO: The DUT currently contains the following objects:
[13:56:57.163] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[13:56:57.163] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:56:57.163] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:56:57.164] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:56:57.164] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:57.164] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:57.164] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:57.164] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:57.164] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:57.164] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:57.164] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:57.164] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:57.164] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:57.164] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:57.164] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:57.164] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:57.164] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:57.164] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:57.164] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:57.164] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:57.578] <TB2> INFO: Expecting 2560 events.
[13:56:58.647] <TB2> INFO: 2560 events read in total (353ms).
[13:56:58.647] <TB2> INFO: Test took 1483ms.
[13:56:58.647] <TB2> INFO: The DUT currently contains the following objects:
[13:56:58.647] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[13:56:58.647] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:56:58.648] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:56:58.648] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:56:58.648] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:58.648] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:58.648] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:58.648] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:58.648] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:58.648] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:58.648] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:58.648] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:58.648] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:58.648] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:58.648] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:58.648] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:58.648] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:58.648] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:58.648] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:58.648] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:56:59.062] <TB2> INFO: Expecting 2560 events.
[13:57:00.131] <TB2> INFO: 2560 events read in total (353ms).
[13:57:00.132] <TB2> INFO: Test took 1484ms.
[13:57:00.132] <TB2> INFO: The DUT currently contains the following objects:
[13:57:00.132] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[13:57:00.132] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:57:00.132] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:57:00.132] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:57:00.132] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:00.132] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:00.132] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:00.132] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:00.132] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:00.133] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:00.133] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:00.133] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:00.133] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:00.133] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:00.133] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:00.133] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:00.133] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:00.133] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:00.133] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:00.133] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:00.546] <TB2> INFO: Expecting 2560 events.
[13:57:01.615] <TB2> INFO: 2560 events read in total (353ms).
[13:57:01.615] <TB2> INFO: Test took 1482ms.
[13:57:01.616] <TB2> INFO: The DUT currently contains the following objects:
[13:57:01.616] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[13:57:01.616] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:57:01.616] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:57:01.616] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:57:01.616] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:01.616] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:01.616] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:01.616] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:01.616] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:01.616] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:01.616] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:01.616] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:01.616] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:01.617] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:01.617] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:01.617] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:01.617] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:01.617] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:01.617] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:01.617] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:57:02.030] <TB2> INFO: Expecting 2560 events.
[13:57:03.098] <TB2> INFO: 2560 events read in total (352ms).
[13:57:03.098] <TB2> INFO: Test took 1481ms.
[13:57:03.103] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:57:03.516] <TB2> INFO: Expecting 655360 events.
[13:57:22.554] <TB2> INFO: 655360 events read in total (18322ms).
[13:57:22.563] <TB2> INFO: Expecting 655360 events.
[13:57:39.681] <TB2> INFO: 655360 events read in total (16591ms).
[13:57:39.693] <TB2> INFO: Expecting 655360 events.
[13:57:58.672] <TB2> INFO: 655360 events read in total (18451ms).
[13:57:58.688] <TB2> INFO: Expecting 655360 events.
[13:58:15.424] <TB2> INFO: 655360 events read in total (16208ms).
[13:58:15.447] <TB2> INFO: Expecting 655360 events.
[13:58:32.429] <TB2> INFO: 655360 events read in total (16455ms).
[13:58:32.452] <TB2> INFO: Expecting 655360 events.
[13:58:48.951] <TB2> INFO: 655360 events read in total (15971ms).
[13:58:48.978] <TB2> INFO: Expecting 655360 events.
[13:59:07.803] <TB2> INFO: 655360 events read in total (18297ms).
[13:59:07.839] <TB2> INFO: Expecting 655360 events.
[13:59:26.765] <TB2> INFO: 655360 events read in total (18398ms).
[13:59:26.800] <TB2> INFO: Expecting 655360 events.
[13:59:42.252] <TB2> INFO: 655360 events read in total (14925ms).
[13:59:42.288] <TB2> INFO: Expecting 655360 events.
[13:59:58.521] <TB2> INFO: 655360 events read in total (15706ms).
[13:59:58.560] <TB2> INFO: Expecting 655360 events.
[14:00:17.772] <TB2> INFO: 655360 events read in total (18684ms).
[14:00:17.814] <TB2> INFO: Expecting 655360 events.
[14:00:34.687] <TB2> INFO: 655360 events read in total (16345ms).
[14:00:34.736] <TB2> INFO: Expecting 655360 events.
[14:00:53.241] <TB2> INFO: 655360 events read in total (17977ms).
[14:00:53.291] <TB2> INFO: Expecting 655360 events.
[14:01:10.082] <TB2> INFO: 655360 events read in total (16263ms).
[14:01:10.136] <TB2> INFO: Expecting 655360 events.
[14:01:28.476] <TB2> INFO: 655360 events read in total (17812ms).
[14:01:28.532] <TB2> INFO: Expecting 655360 events.
[14:01:46.001] <TB2> INFO: 655360 events read in total (16941ms).
[14:01:46.065] <TB2> INFO: Test took 282962ms.
[14:01:46.145] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:01:46.455] <TB2> INFO: Expecting 655360 events.
[14:02:04.187] <TB2> INFO: 655360 events read in total (17015ms).
[14:02:04.200] <TB2> INFO: Expecting 655360 events.
[14:02:21.239] <TB2> INFO: 655360 events read in total (16512ms).
[14:02:21.251] <TB2> INFO: Expecting 655360 events.
[14:02:38.354] <TB2> INFO: 655360 events read in total (16575ms).
[14:02:38.370] <TB2> INFO: Expecting 655360 events.
[14:02:57.156] <TB2> INFO: 655360 events read in total (18259ms).
[14:02:57.177] <TB2> INFO: Expecting 655360 events.
[14:03:13.602] <TB2> INFO: 655360 events read in total (15898ms).
[14:03:13.625] <TB2> INFO: Expecting 655360 events.
[14:03:32.214] <TB2> INFO: 655360 events read in total (18061ms).
[14:03:32.239] <TB2> INFO: Expecting 655360 events.
[14:03:50.102] <TB2> INFO: 655360 events read in total (17335ms).
[14:03:50.133] <TB2> INFO: Expecting 655360 events.
[14:04:05.676] <TB2> INFO: 655360 events read in total (15016ms).
[14:04:05.713] <TB2> INFO: Expecting 655360 events.
[14:04:20.881] <TB2> INFO: 655360 events read in total (14641ms).
[14:04:20.917] <TB2> INFO: Expecting 655360 events.
[14:04:36.867] <TB2> INFO: 655360 events read in total (15422ms).
[14:04:36.910] <TB2> INFO: Expecting 655360 events.
[14:04:53.409] <TB2> INFO: 655360 events read in total (15972ms).
[14:04:53.452] <TB2> INFO: Expecting 655360 events.
[14:05:09.539] <TB2> INFO: 655360 events read in total (15560ms).
[14:05:09.588] <TB2> INFO: Expecting 655360 events.
[14:05:26.542] <TB2> INFO: 655360 events read in total (16427ms).
[14:05:26.596] <TB2> INFO: Expecting 655360 events.
[14:05:43.635] <TB2> INFO: 655360 events read in total (16512ms).
[14:05:43.687] <TB2> INFO: Expecting 655360 events.
[14:05:59.562] <TB2> INFO: 655360 events read in total (15347ms).
[14:05:59.622] <TB2> INFO: Expecting 655360 events.
[14:06:17.448] <TB2> INFO: 655360 events read in total (17299ms).
[14:06:17.507] <TB2> INFO: Test took 271362ms.
[14:06:17.693] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:06:17.700] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:06:17.708] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:06:17.715] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:06:17.723] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:06:17.730] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:06:17.738] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:06:17.745] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:06:17.753] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:06:17.760] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:06:17.768] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:06:17.775] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:06:17.783] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:06:17.791] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:06:17.799] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:06:17.806] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:06:17.814] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:06:17.822] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:06:17.830] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:06:17.838] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:06:17.847] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:06:17.855] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:06:17.863] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:06:17.903] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C0.dat
[14:06:17.903] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C1.dat
[14:06:17.903] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C2.dat
[14:06:17.903] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C3.dat
[14:06:17.903] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C4.dat
[14:06:17.903] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C5.dat
[14:06:17.903] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C6.dat
[14:06:17.904] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C7.dat
[14:06:17.904] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C8.dat
[14:06:17.904] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C9.dat
[14:06:17.904] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C10.dat
[14:06:17.904] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C11.dat
[14:06:17.904] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C12.dat
[14:06:17.904] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C13.dat
[14:06:17.904] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C14.dat
[14:06:17.904] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//dacParameters35_C15.dat
[14:06:18.214] <TB2> INFO: Expecting 41600 events.
[14:06:22.768] <TB2> INFO: 41600 events read in total (3838ms).
[14:06:22.769] <TB2> INFO: Test took 4862ms.
[14:06:23.321] <TB2> INFO: Expecting 41600 events.
[14:06:27.638] <TB2> INFO: 41600 events read in total (3601ms).
[14:06:27.639] <TB2> INFO: Test took 4634ms.
[14:06:28.181] <TB2> INFO: Expecting 41600 events.
[14:06:32.560] <TB2> INFO: 41600 events read in total (3663ms).
[14:06:32.561] <TB2> INFO: Test took 4687ms.
[14:06:32.781] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:32.914] <TB2> INFO: Expecting 2560 events.
[14:06:33.977] <TB2> INFO: 2560 events read in total (347ms).
[14:06:33.977] <TB2> INFO: Test took 1196ms.
[14:06:33.979] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:34.393] <TB2> INFO: Expecting 2560 events.
[14:06:35.455] <TB2> INFO: 2560 events read in total (347ms).
[14:06:35.456] <TB2> INFO: Test took 1477ms.
[14:06:35.458] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:35.871] <TB2> INFO: Expecting 2560 events.
[14:06:36.940] <TB2> INFO: 2560 events read in total (353ms).
[14:06:36.940] <TB2> INFO: Test took 1482ms.
[14:06:36.942] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:37.356] <TB2> INFO: Expecting 2560 events.
[14:06:38.451] <TB2> INFO: 2560 events read in total (379ms).
[14:06:38.452] <TB2> INFO: Test took 1510ms.
[14:06:38.454] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:38.867] <TB2> INFO: Expecting 2560 events.
[14:06:39.935] <TB2> INFO: 2560 events read in total (351ms).
[14:06:39.935] <TB2> INFO: Test took 1481ms.
[14:06:39.937] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:40.350] <TB2> INFO: Expecting 2560 events.
[14:06:41.412] <TB2> INFO: 2560 events read in total (346ms).
[14:06:41.412] <TB2> INFO: Test took 1475ms.
[14:06:41.414] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:41.828] <TB2> INFO: Expecting 2560 events.
[14:06:42.898] <TB2> INFO: 2560 events read in total (354ms).
[14:06:42.898] <TB2> INFO: Test took 1484ms.
[14:06:42.901] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:43.314] <TB2> INFO: Expecting 2560 events.
[14:06:44.395] <TB2> INFO: 2560 events read in total (365ms).
[14:06:44.396] <TB2> INFO: Test took 1495ms.
[14:06:44.398] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:44.811] <TB2> INFO: Expecting 2560 events.
[14:06:45.879] <TB2> INFO: 2560 events read in total (352ms).
[14:06:45.880] <TB2> INFO: Test took 1482ms.
[14:06:45.882] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:46.295] <TB2> INFO: Expecting 2560 events.
[14:06:47.365] <TB2> INFO: 2560 events read in total (353ms).
[14:06:47.366] <TB2> INFO: Test took 1484ms.
[14:06:47.384] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:47.781] <TB2> INFO: Expecting 2560 events.
[14:06:48.852] <TB2> INFO: 2560 events read in total (355ms).
[14:06:48.852] <TB2> INFO: Test took 1469ms.
[14:06:48.855] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:49.269] <TB2> INFO: Expecting 2560 events.
[14:06:50.353] <TB2> INFO: 2560 events read in total (368ms).
[14:06:50.354] <TB2> INFO: Test took 1499ms.
[14:06:50.356] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:50.769] <TB2> INFO: Expecting 2560 events.
[14:06:51.837] <TB2> INFO: 2560 events read in total (352ms).
[14:06:51.838] <TB2> INFO: Test took 1482ms.
[14:06:51.840] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:52.253] <TB2> INFO: Expecting 2560 events.
[14:06:53.336] <TB2> INFO: 2560 events read in total (367ms).
[14:06:53.336] <TB2> INFO: Test took 1496ms.
[14:06:53.338] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:53.752] <TB2> INFO: Expecting 2560 events.
[14:06:54.820] <TB2> INFO: 2560 events read in total (352ms).
[14:06:54.820] <TB2> INFO: Test took 1482ms.
[14:06:54.823] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:55.236] <TB2> INFO: Expecting 2560 events.
[14:06:56.303] <TB2> INFO: 2560 events read in total (351ms).
[14:06:56.303] <TB2> INFO: Test took 1480ms.
[14:06:56.306] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:56.719] <TB2> INFO: Expecting 2560 events.
[14:06:57.786] <TB2> INFO: 2560 events read in total (351ms).
[14:06:57.787] <TB2> INFO: Test took 1481ms.
[14:06:57.791] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:58.202] <TB2> INFO: Expecting 2560 events.
[14:06:59.270] <TB2> INFO: 2560 events read in total (352ms).
[14:06:59.271] <TB2> INFO: Test took 1480ms.
[14:06:59.273] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:06:59.686] <TB2> INFO: Expecting 2560 events.
[14:07:00.753] <TB2> INFO: 2560 events read in total (351ms).
[14:07:00.754] <TB2> INFO: Test took 1481ms.
[14:07:00.756] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:07:01.169] <TB2> INFO: Expecting 2560 events.
[14:07:02.237] <TB2> INFO: 2560 events read in total (351ms).
[14:07:02.237] <TB2> INFO: Test took 1481ms.
[14:07:02.240] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:07:02.653] <TB2> INFO: Expecting 2560 events.
[14:07:03.721] <TB2> INFO: 2560 events read in total (352ms).
[14:07:03.721] <TB2> INFO: Test took 1481ms.
[14:07:03.723] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:07:04.137] <TB2> INFO: Expecting 2560 events.
[14:07:05.204] <TB2> INFO: 2560 events read in total (351ms).
[14:07:05.205] <TB2> INFO: Test took 1482ms.
[14:07:05.207] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:07:05.621] <TB2> INFO: Expecting 2560 events.
[14:07:06.717] <TB2> INFO: 2560 events read in total (380ms).
[14:07:06.718] <TB2> INFO: Test took 1511ms.
[14:07:06.720] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:07:07.134] <TB2> INFO: Expecting 2560 events.
[14:07:08.204] <TB2> INFO: 2560 events read in total (354ms).
[14:07:08.204] <TB2> INFO: Test took 1484ms.
[14:07:08.206] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:07:08.620] <TB2> INFO: Expecting 2560 events.
[14:07:09.702] <TB2> INFO: 2560 events read in total (366ms).
[14:07:09.702] <TB2> INFO: Test took 1496ms.
[14:07:09.704] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:07:10.118] <TB2> INFO: Expecting 2560 events.
[14:07:11.215] <TB2> INFO: 2560 events read in total (381ms).
[14:07:11.216] <TB2> INFO: Test took 1512ms.
[14:07:11.218] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:07:11.631] <TB2> INFO: Expecting 2560 events.
[14:07:12.716] <TB2> INFO: 2560 events read in total (369ms).
[14:07:12.716] <TB2> INFO: Test took 1498ms.
[14:07:12.720] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:07:13.131] <TB2> INFO: Expecting 2560 events.
[14:07:14.200] <TB2> INFO: 2560 events read in total (353ms).
[14:07:14.200] <TB2> INFO: Test took 1480ms.
[14:07:14.203] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:07:14.616] <TB2> INFO: Expecting 2560 events.
[14:07:15.685] <TB2> INFO: 2560 events read in total (353ms).
[14:07:15.685] <TB2> INFO: Test took 1482ms.
[14:07:15.688] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:07:16.101] <TB2> INFO: Expecting 2560 events.
[14:07:17.186] <TB2> INFO: 2560 events read in total (369ms).
[14:07:17.186] <TB2> INFO: Test took 1499ms.
[14:07:17.189] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:07:17.602] <TB2> INFO: Expecting 2560 events.
[14:07:18.681] <TB2> INFO: 2560 events read in total (363ms).
[14:07:18.681] <TB2> INFO: Test took 1493ms.
[14:07:18.683] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:07:19.095] <TB2> INFO: Expecting 2560 events.
[14:07:20.160] <TB2> INFO: 2560 events read in total (348ms).
[14:07:20.161] <TB2> INFO: Test took 1478ms.
[14:07:20.773] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 656 seconds
[14:07:20.773] <TB2> INFO: PH scale (per ROC): 79 80 78 80 85 86 75 79 86 82 85 81 80 86 80 83
[14:07:20.773] <TB2> INFO: PH offset (per ROC): 160 159 165 166 167 150 170 159 160 167 158 164 164 144 152 147
[14:07:20.960] <TB2> INFO: ######################################################################
[14:07:20.961] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[14:07:20.961] <TB2> INFO: ######################################################################
[14:07:20.972] <TB2> INFO: scanning low vcal = 10
[14:07:21.276] <TB2> INFO: Expecting 41600 events.
[14:07:24.911] <TB2> INFO: 41600 events read in total (2918ms).
[14:07:24.912] <TB2> INFO: Test took 3940ms.
[14:07:24.913] <TB2> INFO: scanning low vcal = 20
[14:07:25.326] <TB2> INFO: Expecting 41600 events.
[14:07:29.008] <TB2> INFO: 41600 events read in total (2966ms).
[14:07:29.008] <TB2> INFO: Test took 4095ms.
[14:07:29.010] <TB2> INFO: scanning low vcal = 30
[14:07:29.423] <TB2> INFO: Expecting 41600 events.
[14:07:33.082] <TB2> INFO: 41600 events read in total (2943ms).
[14:07:33.089] <TB2> INFO: Test took 4079ms.
[14:07:33.090] <TB2> INFO: scanning low vcal = 40
[14:07:33.493] <TB2> INFO: Expecting 41600 events.
[14:07:37.953] <TB2> INFO: 41600 events read in total (3744ms).
[14:07:37.954] <TB2> INFO: Test took 4864ms.
[14:07:37.958] <TB2> INFO: scanning low vcal = 50
[14:07:38.309] <TB2> INFO: Expecting 41600 events.
[14:07:42.768] <TB2> INFO: 41600 events read in total (3743ms).
[14:07:42.769] <TB2> INFO: Test took 4811ms.
[14:07:42.772] <TB2> INFO: scanning low vcal = 60
[14:07:43.117] <TB2> INFO: Expecting 41600 events.
[14:07:47.608] <TB2> INFO: 41600 events read in total (3775ms).
[14:07:47.609] <TB2> INFO: Test took 4837ms.
[14:07:47.612] <TB2> INFO: scanning low vcal = 70
[14:07:47.961] <TB2> INFO: Expecting 41600 events.
[14:07:52.420] <TB2> INFO: 41600 events read in total (3742ms).
[14:07:52.421] <TB2> INFO: Test took 4809ms.
[14:07:52.424] <TB2> INFO: scanning low vcal = 80
[14:07:52.779] <TB2> INFO: Expecting 41600 events.
[14:07:57.012] <TB2> INFO: 41600 events read in total (3517ms).
[14:07:57.013] <TB2> INFO: Test took 4589ms.
[14:07:57.016] <TB2> INFO: scanning low vcal = 90
[14:07:57.367] <TB2> INFO: Expecting 41600 events.
[14:08:01.701] <TB2> INFO: 41600 events read in total (3618ms).
[14:08:01.702] <TB2> INFO: Test took 4686ms.
[14:08:01.706] <TB2> INFO: scanning low vcal = 100
[14:08:02.051] <TB2> INFO: Expecting 41600 events.
[14:08:06.497] <TB2> INFO: 41600 events read in total (3730ms).
[14:08:06.497] <TB2> INFO: Test took 4791ms.
[14:08:06.504] <TB2> INFO: scanning low vcal = 110
[14:08:06.845] <TB2> INFO: Expecting 41600 events.
[14:08:11.320] <TB2> INFO: 41600 events read in total (3759ms).
[14:08:11.321] <TB2> INFO: Test took 4817ms.
[14:08:11.323] <TB2> INFO: scanning low vcal = 120
[14:08:11.673] <TB2> INFO: Expecting 41600 events.
[14:08:15.715] <TB2> INFO: 41600 events read in total (3326ms).
[14:08:15.715] <TB2> INFO: Test took 4392ms.
[14:08:15.718] <TB2> INFO: scanning low vcal = 130
[14:08:16.072] <TB2> INFO: Expecting 41600 events.
[14:08:20.139] <TB2> INFO: 41600 events read in total (3351ms).
[14:08:20.140] <TB2> INFO: Test took 4422ms.
[14:08:20.143] <TB2> INFO: scanning low vcal = 140
[14:08:20.488] <TB2> INFO: Expecting 41600 events.
[14:08:24.596] <TB2> INFO: 41600 events read in total (3392ms).
[14:08:24.597] <TB2> INFO: Test took 4454ms.
[14:08:24.600] <TB2> INFO: scanning low vcal = 150
[14:08:24.936] <TB2> INFO: Expecting 41600 events.
[14:08:29.017] <TB2> INFO: 41600 events read in total (3365ms).
[14:08:29.017] <TB2> INFO: Test took 4417ms.
[14:08:29.020] <TB2> INFO: scanning low vcal = 160
[14:08:29.359] <TB2> INFO: Expecting 41600 events.
[14:08:33.460] <TB2> INFO: 41600 events read in total (3385ms).
[14:08:33.460] <TB2> INFO: Test took 4440ms.
[14:08:33.464] <TB2> INFO: scanning low vcal = 170
[14:08:33.845] <TB2> INFO: Expecting 41600 events.
[14:08:37.973] <TB2> INFO: 41600 events read in total (3412ms).
[14:08:37.975] <TB2> INFO: Test took 4511ms.
[14:08:37.981] <TB2> INFO: scanning low vcal = 180
[14:08:38.328] <TB2> INFO: Expecting 41600 events.
[14:08:42.550] <TB2> INFO: 41600 events read in total (3506ms).
[14:08:42.550] <TB2> INFO: Test took 4569ms.
[14:08:42.553] <TB2> INFO: scanning low vcal = 190
[14:08:42.904] <TB2> INFO: Expecting 41600 events.
[14:08:47.179] <TB2> INFO: 41600 events read in total (3559ms).
[14:08:47.180] <TB2> INFO: Test took 4627ms.
[14:08:47.182] <TB2> INFO: scanning low vcal = 200
[14:08:47.525] <TB2> INFO: Expecting 41600 events.
[14:08:51.784] <TB2> INFO: 41600 events read in total (3543ms).
[14:08:51.784] <TB2> INFO: Test took 4602ms.
[14:08:51.787] <TB2> INFO: scanning low vcal = 210
[14:08:52.140] <TB2> INFO: Expecting 41600 events.
[14:08:56.389] <TB2> INFO: 41600 events read in total (3533ms).
[14:08:56.390] <TB2> INFO: Test took 4603ms.
[14:08:56.392] <TB2> INFO: scanning low vcal = 220
[14:08:56.742] <TB2> INFO: Expecting 41600 events.
[14:09:00.976] <TB2> INFO: 41600 events read in total (3518ms).
[14:09:00.976] <TB2> INFO: Test took 4584ms.
[14:09:00.980] <TB2> INFO: scanning low vcal = 230
[14:09:01.321] <TB2> INFO: Expecting 41600 events.
[14:09:05.384] <TB2> INFO: 41600 events read in total (3347ms).
[14:09:05.385] <TB2> INFO: Test took 4405ms.
[14:09:05.387] <TB2> INFO: scanning low vcal = 240
[14:09:05.740] <TB2> INFO: Expecting 41600 events.
[14:09:09.824] <TB2> INFO: 41600 events read in total (3368ms).
[14:09:09.825] <TB2> INFO: Test took 4438ms.
[14:09:09.830] <TB2> INFO: scanning low vcal = 250
[14:09:10.180] <TB2> INFO: Expecting 41600 events.
[14:09:14.276] <TB2> INFO: 41600 events read in total (3380ms).
[14:09:14.277] <TB2> INFO: Test took 4447ms.
[14:09:14.281] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[14:09:14.634] <TB2> INFO: Expecting 41600 events.
[14:09:18.713] <TB2> INFO: 41600 events read in total (3363ms).
[14:09:18.713] <TB2> INFO: Test took 4432ms.
[14:09:18.716] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[14:09:19.069] <TB2> INFO: Expecting 41600 events.
[14:09:23.091] <TB2> INFO: 41600 events read in total (3306ms).
[14:09:23.093] <TB2> INFO: Test took 4377ms.
[14:09:23.097] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[14:09:23.443] <TB2> INFO: Expecting 41600 events.
[14:09:27.871] <TB2> INFO: 41600 events read in total (3712ms).
[14:09:27.872] <TB2> INFO: Test took 4775ms.
[14:09:27.875] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[14:09:28.218] <TB2> INFO: Expecting 41600 events.
[14:09:33.007] <TB2> INFO: 41600 events read in total (4073ms).
[14:09:33.008] <TB2> INFO: Test took 5133ms.
[14:09:33.011] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[14:09:33.358] <TB2> INFO: Expecting 41600 events.
[14:09:37.556] <TB2> INFO: 41600 events read in total (3483ms).
[14:09:37.557] <TB2> INFO: Test took 4546ms.
[14:09:38.133] <TB2> INFO: PixTestGainPedestal::measure() done
[14:10:10.935] <TB2> INFO: PixTestGainPedestal::fit() done
[14:10:10.935] <TB2> INFO: non-linearity mean: 0.960 0.960 0.957 0.961 0.959 0.958 0.963 0.955 0.960 0.959 0.948 0.956 0.959 0.960 0.959 0.946
[14:10:10.935] <TB2> INFO: non-linearity RMS: 0.006 0.005 0.005 0.005 0.006 0.005 0.006 0.006 0.007 0.007 0.007 0.006 0.005 0.004 0.006 0.006
[14:10:10.935] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//phCalibrationFitErr35_C0.dat
[14:10:10.955] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//phCalibrationFitErr35_C1.dat
[14:10:10.975] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//phCalibrationFitErr35_C2.dat
[14:10:10.995] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//phCalibrationFitErr35_C3.dat
[14:10:11.014] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//phCalibrationFitErr35_C4.dat
[14:10:11.033] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//phCalibrationFitErr35_C5.dat
[14:10:11.052] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//phCalibrationFitErr35_C6.dat
[14:10:11.071] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//phCalibrationFitErr35_C7.dat
[14:10:11.091] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//phCalibrationFitErr35_C8.dat
[14:10:11.110] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//phCalibrationFitErr35_C9.dat
[14:10:11.129] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//phCalibrationFitErr35_C10.dat
[14:10:11.148] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//phCalibrationFitErr35_C11.dat
[14:10:11.167] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//phCalibrationFitErr35_C12.dat
[14:10:11.186] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//phCalibrationFitErr35_C13.dat
[14:10:11.205] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//phCalibrationFitErr35_C14.dat
[14:10:11.224] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//phCalibrationFitErr35_C15.dat
[14:10:11.243] <TB2> INFO: PixTestGainPedestal::doTest() done, duration: 170 seconds
[14:10:11.250] <TB2> INFO: readReadbackCal: /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C0.dat .. /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C15.dat
[14:10:11.251] <TB2> INFO: PixTestReadback::doTest() start.
[14:10:11.252] <TB2> INFO: PixTestReadback::RES sent once
[14:10:33.043] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C0.dat
[14:10:33.043] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C1.dat
[14:10:33.043] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C2.dat
[14:10:33.044] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C3.dat
[14:10:33.044] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C4.dat
[14:10:33.044] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C5.dat
[14:10:33.044] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C6.dat
[14:10:33.044] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C7.dat
[14:10:33.044] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C8.dat
[14:10:33.044] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C9.dat
[14:10:33.044] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C10.dat
[14:10:33.044] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C11.dat
[14:10:33.044] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C12.dat
[14:10:33.045] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C13.dat
[14:10:33.045] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C14.dat
[14:10:33.045] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C15.dat
[14:10:33.075] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:10:33.075] <TB2> INFO: PixTestReadback::RES sent once
[14:10:54.775] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C0.dat
[14:10:54.776] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C1.dat
[14:10:54.776] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C2.dat
[14:10:54.776] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C3.dat
[14:10:54.776] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C4.dat
[14:10:54.776] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C5.dat
[14:10:54.776] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C6.dat
[14:10:54.776] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C7.dat
[14:10:54.776] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C8.dat
[14:10:54.776] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C9.dat
[14:10:54.776] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C10.dat
[14:10:54.776] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C11.dat
[14:10:54.776] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C12.dat
[14:10:54.776] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C13.dat
[14:10:54.777] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C14.dat
[14:10:54.777] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C15.dat
[14:10:54.801] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:10:54.801] <TB2> INFO: PixTestReadback::RES sent once
[14:11:11.665] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:11:11.665] <TB2> INFO: Vbg will be calibrated using Vd calibration
[14:11:11.665] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 159calibrated Vbg = 1.19591 :::*/*/*/*/
[14:11:11.665] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 152.1calibrated Vbg = 1.18973 :::*/*/*/*/
[14:11:11.665] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 146.2calibrated Vbg = 1.19662 :::*/*/*/*/
[14:11:11.665] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 255calibrated Vbg = 1.1775 :::*/*/*/*/
[14:11:11.665] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 150.5calibrated Vbg = 1.19918 :::*/*/*/*/
[14:11:11.665] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 153.8calibrated Vbg = 1.20098 :::*/*/*/*/
[14:11:11.665] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 149.2calibrated Vbg = 1.20359 :::*/*/*/*/
[14:11:11.665] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 255calibrated Vbg = 1.1775 :::*/*/*/*/
[14:11:11.665] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 148calibrated Vbg = 1.20135 :::*/*/*/*/
[14:11:11.665] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 154.3calibrated Vbg = 1.20028 :::*/*/*/*/
[14:11:11.665] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 149.8calibrated Vbg = 1.20192 :::*/*/*/*/
[14:11:11.665] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 255calibrated Vbg = 1.1775 :::*/*/*/*/
[14:11:11.665] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 150calibrated Vbg = 1.19274 :::*/*/*/*/
[14:11:11.665] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 152.8calibrated Vbg = 1.19205 :::*/*/*/*/
[14:11:11.665] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 152calibrated Vbg = 1.20333 :::*/*/*/*/
[14:11:11.665] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 255calibrated Vbg = 1.1775 :::*/*/*/*/
[14:11:11.669] <TB2> INFO: PixTestReadback::RES sent once
[14:15:51.910] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C0.dat
[14:15:51.911] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C1.dat
[14:15:51.911] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C2.dat
[14:15:51.911] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C3.dat
[14:15:51.911] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C4.dat
[14:15:51.911] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C5.dat
[14:15:51.911] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C6.dat
[14:15:51.911] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C7.dat
[14:15:51.912] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C8.dat
[14:15:51.912] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C9.dat
[14:15:51.912] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C10.dat
[14:15:51.912] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C11.dat
[14:15:51.912] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C12.dat
[14:15:51.912] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C13.dat
[14:15:51.912] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C14.dat
[14:15:51.912] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2101_FullQualification_2015-09-02_10h55m_1441184145//002_FulltestPxar_m20//readbackCal_C15.dat
[14:15:51.944] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:15:51.946] <TB2> INFO: PixTestReadback::doTest() done
[14:15:51.959] <TB2> INFO: enter test to run
[14:15:51.959] <TB2> INFO: test: exit no parameter change
[14:15:52.550] <TB2> QUIET: Connection to board 156 closed.
[14:15:52.629] <TB2> INFO: pXar: this is the end, my friend