[12:34:56.150] <TB2> INFO: *** Welcome to pxar ***
[12:34:56.150] <TB2> INFO: *** Today: 2015/08/31
[12:34:56.150] <TB2> INFO: readRocDacs: /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C0.dat .. /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C15.dat
[12:34:56.151] <TB2> INFO: readTbmDacs: /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//tbmParameters_C0a.dat .. /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//tbmParameters_C0b.dat
[12:34:56.151] <TB2> INFO: readMaskFile: /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//defaultMaskFile.dat
[12:34:56.151] <TB2> INFO: readTrimFile: /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters_C0.dat .. /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters_C15.dat
[12:34:56.242] <TB2> INFO: clk: 4
[12:34:56.242] <TB2> INFO: ctr: 4
[12:34:56.242] <TB2> INFO: sda: 19
[12:34:56.242] <TB2> INFO: tin: 9
[12:34:56.242] <TB2> INFO: level: 15
[12:34:56.242] <TB2> INFO: triggerdelay: 0
[12:34:56.242] <TB2> QUIET: Instanciating API for pxar v2.5+57~g44d0777
[12:34:56.242] <TB2> INFO: Log level: INFO
[12:34:56.250] <TB2> INFO: Found DTB DTB_WXC55Z
[12:34:56.261] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[12:34:56.264] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.2
SW version: 4.4
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[12:34:56.267] <TB2> INFO: RPC call hashes of host and DTB match: 397073690
[12:34:57.791] <TB2> INFO: DUT info:
[12:34:57.791] <TB2> INFO: The DUT currently contains the following objects:
[12:34:57.791] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[12:34:57.791] <TB2> INFO: TBM Core alpha (0): 7 registers set
[12:34:57.791] <TB2> INFO: TBM Core beta (1): 7 registers set
[12:34:57.791] <TB2> INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[12:34:57.791] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:34:57.791] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:34:57.791] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:34:57.791] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:34:57.791] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:34:57.791] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:34:57.792] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:34:57.792] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:34:57.792] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:34:57.792] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:34:57.792] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:34:57.792] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:34:57.792] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:34:57.792] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:34:57.792] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:34:57.792] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:34:58.193] <TB2> INFO: enter 'restricted' command line mode
[12:34:58.193] <TB2> INFO: enter test to run
[12:34:58.193] <TB2> INFO: test: pretest no parameter change
[12:34:58.193] <TB2> INFO: running: pretest
[12:34:58.200] <TB2> INFO: ######################################################################
[12:34:58.200] <TB2> INFO: PixTestPretest::doTest()
[12:34:58.200] <TB2> INFO: ######################################################################
[12:34:58.202] <TB2> INFO: ----------------------------------------------------------------------
[12:34:58.202] <TB2> INFO: PixTestPretest::programROC()
[12:34:58.202] <TB2> INFO: ----------------------------------------------------------------------
[12:35:16.219] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:35:16.219] <TB2> INFO: IA differences per ROC: 18.5 16.9 19.3 18.5 20.1 16.9 20.9 19.3 17.7 17.7 20.9 20.9 20.9 18.5 17.7 17.7
[12:35:16.298] <TB2> INFO: ----------------------------------------------------------------------
[12:35:16.298] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:35:16.298] <TB2> INFO: ----------------------------------------------------------------------
[12:35:20.762] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 384.3 mA = 24.0187 mA/ROC
[12:35:20.764] <TB2> INFO: ----------------------------------------------------------------------
[12:35:20.764] <TB2> INFO: PixTestPretest::findTiming()
[12:35:20.764] <TB2> INFO: ----------------------------------------------------------------------
[12:35:20.764] <TB2> INFO: PixTestCmd::init()

[12:37:08.686] <TB2> INFO: TBM phases: 160MHz: 0, 400MHz: 6, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[12:37:08.686] <TB2> INFO: (success/tries = 100/100), width = 4
[12:37:08.687] <TB2> INFO: ----------------------------------------------------------------------
[12:37:08.688] <TB2> INFO: PixTestPretest::findWorkingPixel()
[12:37:08.688] <TB2> INFO: ----------------------------------------------------------------------
[12:37:08.828] <TB2> INFO: Expecting 231680 events.
[12:37:17.745] <TB2> INFO: 231680 events read in total (8200ms).
[12:37:17.749] <TB2> INFO: Test took 9055ms.
[12:37:18.066] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:37:18.098] <TB2> INFO: ----------------------------------------------------------------------
[12:37:18.098] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[12:37:18.098] <TB2> INFO: ----------------------------------------------------------------------
[12:37:18.234] <TB2> INFO: Expecting 231680 events.
[12:37:27.608] <TB2> INFO: 231680 events read in total (8657ms).
[12:37:27.612] <TB2> INFO: Test took 9510ms.
[12:37:27.944] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[12:37:27.944] <TB2> INFO: CalDel: 143 138 146 170 131 148 152 139 139 153 158 141 154 159 131 150
[12:37:27.944] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[12:37:27.948] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C0.dat
[12:37:27.948] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C1.dat
[12:37:27.948] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C2.dat
[12:37:27.948] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C3.dat
[12:37:27.949] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C4.dat
[12:37:27.949] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C5.dat
[12:37:27.949] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C6.dat
[12:37:27.950] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C7.dat
[12:37:27.950] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C8.dat
[12:37:27.950] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C9.dat
[12:37:27.950] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C10.dat
[12:37:27.950] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C11.dat
[12:37:27.951] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C12.dat
[12:37:27.951] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C13.dat
[12:37:27.951] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C14.dat
[12:37:27.951] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters_C15.dat
[12:37:27.952] <TB2> INFO: write tbm parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//tbmParameters_C0a.dat
[12:37:27.952] <TB2> INFO: write tbm parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//tbmParameters_C0b.dat
[12:37:27.952] <TB2> INFO: PixTestPretest::doTest() done, duration: 149 seconds
[12:37:28.017] <TB2> INFO: enter test to run
[12:37:28.018] <TB2> INFO: test: fulltest no parameter change
[12:37:28.018] <TB2> INFO: running: fulltest
[12:37:28.018] <TB2> INFO: ######################################################################
[12:37:28.018] <TB2> INFO: PixTestFullTest::doTest()
[12:37:28.018] <TB2> INFO: ######################################################################
[12:37:28.019] <TB2> INFO: ######################################################################
[12:37:28.019] <TB2> INFO: PixTestAlive::doTest()
[12:37:28.019] <TB2> INFO: ######################################################################
[12:37:28.021] <TB2> INFO: ----------------------------------------------------------------------
[12:37:28.021] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:37:28.021] <TB2> INFO: ----------------------------------------------------------------------
[12:37:28.345] <TB2> INFO: Expecting 41600 events.
[12:37:33.116] <TB2> INFO: 41600 events read in total (4054ms).
[12:37:33.116] <TB2> INFO: Test took 5094ms.
[12:37:33.122] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:37:33.415] <TB2> INFO: PixTestAlive::aliveTest() done
[12:37:33.415] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0
[12:37:33.418] <TB2> INFO: ----------------------------------------------------------------------
[12:37:33.418] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:37:33.418] <TB2> INFO: ----------------------------------------------------------------------
[12:37:33.734] <TB2> INFO: Expecting 41600 events.
[12:37:36.947] <TB2> INFO: 41600 events read in total (2497ms).
[12:37:36.947] <TB2> INFO: Test took 3527ms.
[12:37:36.947] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:37:36.948] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:37:37.264] <TB2> INFO: PixTestAlive::maskTest() done
[12:37:37.264] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:37:37.268] <TB2> INFO: ----------------------------------------------------------------------
[12:37:37.268] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:37:37.268] <TB2> INFO: ----------------------------------------------------------------------
[12:37:37.580] <TB2> INFO: Expecting 41600 events.
[12:37:41.999] <TB2> INFO: 41600 events read in total (3703ms).
[12:37:41.999] <TB2> INFO: Test took 4730ms.
[12:37:42.005] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:37:42.300] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[12:37:42.300] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:37:42.300] <TB2> INFO: PixTestAlive::doTest() done, duration: 14 seconds
[12:37:42.315] <TB2> INFO: ######################################################################
[12:37:42.315] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:37:42.315] <TB2> INFO: ######################################################################
[12:37:42.317] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 2 (plus default)
[12:37:42.329] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[12:37:42.329] <TB2> INFO: run 1 of 1
[12:37:42.640] <TB2> INFO: Expecting 3120000 events.
[12:38:20.661] <TB2> INFO: 841425 events read in total (37304ms).
[12:38:57.620] <TB2> INFO: 1669080 events read in total (74264ms).
[12:39:34.928] <TB2> INFO: 2506170 events read in total (111572ms).
[12:40:00.481] <TB2> INFO: 3120000 events read in total (137124ms).
[12:40:00.529] <TB2> INFO: Test took 138200ms.
[12:40:00.627] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:40:24.899] <TB2> INFO: PixTestBBMap::doTest() done, duration: 162 seconds
[12:40:24.900] <TB2> INFO: number of dead bumps (per ROC): 7 0 0 0 0 0 0 0 1 0 0 0 0 8 0 3
[12:40:24.900] <TB2> INFO: separation cut (per ROC): 77 77 77 76 84 87 101 95 98 95 85 77 73 79 98 67
[12:40:24.970] <TB2> INFO: ######################################################################
[12:40:24.970] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:40:24.970] <TB2> INFO: ######################################################################
[12:40:24.970] <TB2> INFO: ----------------------------------------------------------------------
[12:40:24.970] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:40:24.970] <TB2> INFO: ----------------------------------------------------------------------
[12:40:24.970] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 0 .. 149 (-1/-1) hits flags = 16 (plus default)
[12:40:24.979] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[12:40:24.979] <TB2> INFO: run 1 of 1
[12:40:25.281] <TB2> INFO: Expecting 31200000 events.
[12:40:51.719] <TB2> INFO: 945300 events read in total (25722ms).
[12:41:18.185] <TB2> INFO: 1875550 events read in total (52188ms).
[12:41:44.403] <TB2> INFO: 2799050 events read in total (78406ms).
[12:42:11.330] <TB2> INFO: 3723550 events read in total (105333ms).
[12:42:37.892] <TB2> INFO: 4642150 events read in total (131895ms).
[12:43:04.367] <TB2> INFO: 5564100 events read in total (158370ms).
[12:43:30.964] <TB2> INFO: 6481800 events read in total (184967ms).
[12:43:57.586] <TB2> INFO: 7403650 events read in total (211589ms).
[12:44:23.554] <TB2> INFO: 8321650 events read in total (237557ms).
[12:44:49.787] <TB2> INFO: 9239700 events read in total (263790ms).
[12:45:16.283] <TB2> INFO: 10156000 events read in total (290286ms).
[12:45:42.420] <TB2> INFO: 11075600 events read in total (316423ms).
[12:46:08.740] <TB2> INFO: 11991350 events read in total (342743ms).
[12:46:35.084] <TB2> INFO: 12907150 events read in total (369087ms).
[12:47:01.555] <TB2> INFO: 13821800 events read in total (395558ms).
[12:47:28.225] <TB2> INFO: 14735550 events read in total (422228ms).
[12:47:55.326] <TB2> INFO: 15649650 events read in total (449329ms).
[12:48:21.403] <TB2> INFO: 16553800 events read in total (475406ms).
[12:48:47.875] <TB2> INFO: 17459600 events read in total (501878ms).
[12:49:11.503] <TB2> INFO: 18364350 events read in total (525506ms).
[12:49:35.203] <TB2> INFO: 19268500 events read in total (549206ms).
[12:49:58.875] <TB2> INFO: 20171900 events read in total (572878ms).
[12:50:22.904] <TB2> INFO: 21075000 events read in total (596907ms).
[12:50:46.617] <TB2> INFO: 21978000 events read in total (620620ms).
[12:51:10.401] <TB2> INFO: 22879800 events read in total (644404ms).
[12:51:34.056] <TB2> INFO: 23780750 events read in total (668059ms).
[12:51:57.715] <TB2> INFO: 24681600 events read in total (691718ms).
[12:52:21.522] <TB2> INFO: 25581250 events read in total (715525ms).
[12:52:45.328] <TB2> INFO: 26482550 events read in total (739331ms).
[12:53:08.972] <TB2> INFO: 27384050 events read in total (762975ms).
[12:53:32.827] <TB2> INFO: 28287350 events read in total (786830ms).
[12:53:56.492] <TB2> INFO: 29188450 events read in total (810495ms).
[12:54:18.204] <TB2> INFO: 30095500 events read in total (832207ms).
[12:54:41.395] <TB2> INFO: 31012050 events read in total (855398ms).
[12:54:46.665] <TB2> INFO: 31200000 events read in total (860668ms).
[12:54:46.694] <TB2> INFO: Test took 861715ms.
[12:54:46.775] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:54:46.875] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:54:48.357] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:54:49.919] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:54:51.472] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:54:53.102] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:54:54.801] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:54:56.439] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:54:58.099] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:54:59.648] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:01.286] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:02.730] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:04.429] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:06.254] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:07.882] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:09.357] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:11.112] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:55:12.654] <TB2> INFO: PixTestScurves::scurves() done
[12:55:12.654] <TB2> INFO: Vcal mean: 85.42 84.47 78.23 74.82 81.13 89.16 92.72 93.12 93.16 89.43 80.67 77.18 80.14 97.41 93.15 83.71
[12:55:12.654] <TB2> INFO: Vcal RMS: 4.95 5.43 4.22 4.82 4.77 5.36 6.21 5.72 5.26 6.44 4.82 4.15 4.99 5.41 5.78 4.57
[12:55:12.654] <TB2> INFO: PixTestScurves::fullTest() done, duration: 887 seconds
[12:55:12.734] <TB2> INFO: ######################################################################
[12:55:12.734] <TB2> INFO: PixTestTrim::doTest()
[12:55:12.734] <TB2> INFO: ######################################################################
[12:55:12.735] <TB2> INFO: ----------------------------------------------------------------------
[12:55:12.735] <TB2> INFO: PixTestTrim::trimTest() ntrig = 20, vcal = 35
[12:55:12.735] <TB2> INFO: ----------------------------------------------------------------------
[12:55:12.821] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:55:12.821] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 20 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[12:55:12.831] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[12:55:12.831] <TB2> INFO: run 1 of 1
[12:55:13.148] <TB2> INFO: Expecting 13312000 events.
[12:55:41.192] <TB2> INFO: 1070420 events read in total (27327ms).
[12:56:08.789] <TB2> INFO: 2133300 events read in total (54924ms).
[12:56:36.298] <TB2> INFO: 3194880 events read in total (82433ms).
[12:57:03.496] <TB2> INFO: 4254240 events read in total (109631ms).
[12:57:30.785] <TB2> INFO: 5308660 events read in total (136920ms).
[12:57:58.056] <TB2> INFO: 6360160 events read in total (164191ms).
[12:58:25.458] <TB2> INFO: 7413640 events read in total (191593ms).
[12:58:52.707] <TB2> INFO: 8471580 events read in total (218842ms).
[12:59:19.961] <TB2> INFO: 9530560 events read in total (246096ms).
[12:59:47.079] <TB2> INFO: 10591260 events read in total (273214ms).
[13:00:13.612] <TB2> INFO: 11653720 events read in total (299747ms).
[13:00:40.470] <TB2> INFO: 12715740 events read in total (326605ms).
[13:00:55.874] <TB2> INFO: 13312000 events read in total (342009ms).
[13:00:55.904] <TB2> INFO: Test took 343073ms.
[13:00:55.954] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:01:14.072] <TB2> INFO: ROC 0 VthrComp = 91
[13:01:14.072] <TB2> INFO: ROC 1 VthrComp = 89
[13:01:14.072] <TB2> INFO: ROC 2 VthrComp = 85
[13:01:14.073] <TB2> INFO: ROC 3 VthrComp = 78
[13:01:14.073] <TB2> INFO: ROC 4 VthrComp = 89
[13:01:14.073] <TB2> INFO: ROC 5 VthrComp = 92
[13:01:14.073] <TB2> INFO: ROC 6 VthrComp = 100
[13:01:14.073] <TB2> INFO: ROC 7 VthrComp = 97
[13:01:14.073] <TB2> INFO: ROC 8 VthrComp = 96
[13:01:14.073] <TB2> INFO: ROC 9 VthrComp = 93
[13:01:14.073] <TB2> INFO: ROC 10 VthrComp = 86
[13:01:14.073] <TB2> INFO: ROC 11 VthrComp = 81
[13:01:14.074] <TB2> INFO: ROC 12 VthrComp = 83
[13:01:14.074] <TB2> INFO: ROC 13 VthrComp = 97
[13:01:14.074] <TB2> INFO: ROC 14 VthrComp = 95
[13:01:14.074] <TB2> INFO: ROC 15 VthrComp = 88
[13:01:14.074] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:01:14.074] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 20 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[13:01:14.085] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[13:01:14.085] <TB2> INFO: run 1 of 1
[13:01:14.401] <TB2> INFO: Expecting 13312000 events.
[13:01:40.042] <TB2> INFO: 780660 events read in total (24925ms).
[13:02:04.887] <TB2> INFO: 1557460 events read in total (49770ms).
[13:02:29.772] <TB2> INFO: 2333680 events read in total (74655ms).
[13:02:54.398] <TB2> INFO: 3109700 events read in total (99281ms).
[13:03:19.305] <TB2> INFO: 3885820 events read in total (124188ms).
[13:03:44.320] <TB2> INFO: 4662160 events read in total (149203ms).
[13:04:09.077] <TB2> INFO: 5438840 events read in total (173960ms).
[13:04:33.991] <TB2> INFO: 6215480 events read in total (198874ms).
[13:04:58.857] <TB2> INFO: 6988420 events read in total (223740ms).
[13:05:21.207] <TB2> INFO: 7758700 events read in total (246090ms).
[13:05:43.481] <TB2> INFO: 8527120 events read in total (268364ms).
[13:06:05.995] <TB2> INFO: 9294920 events read in total (290878ms).
[13:06:28.376] <TB2> INFO: 10060640 events read in total (313259ms).
[13:06:52.788] <TB2> INFO: 10825960 events read in total (337671ms).
[13:07:17.513] <TB2> INFO: 11591360 events read in total (362396ms).
[13:07:39.982] <TB2> INFO: 12356720 events read in total (384865ms).
[13:08:04.311] <TB2> INFO: 13124240 events read in total (409194ms).
[13:08:10.710] <TB2> INFO: 13312000 events read in total (415593ms).
[13:08:10.759] <TB2> INFO: Test took 416674ms.
[13:08:10.904] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:08:33.073] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 58.6358 for pixel 5/76 mean/min/max = 45.5042/32.274/58.7343
[13:08:33.074] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 60.6386 for pixel 0/42 mean/min/max = 46.3422/31.7945/60.8899
[13:08:33.074] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 55.8739 for pixel 13/27 mean/min/max = 44.1004/31.9132/56.2875
[13:08:33.074] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 59.5916 for pixel 0/5 mean/min/max = 46.9002/34.1101/59.6903
[13:08:33.074] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 58.5961 for pixel 25/12 mean/min/max = 45.3071/32.0106/58.6036
[13:08:33.075] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 58.19 for pixel 32/2 mean/min/max = 45.2026/32.1931/58.2122
[13:08:33.075] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 59.7821 for pixel 1/79 mean/min/max = 45.6004/31.3178/59.8829
[13:08:33.075] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 59.0984 for pixel 23/0 mean/min/max = 45.2822/31.4354/59.1289
[13:08:33.076] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 60.1571 for pixel 0/72 mean/min/max = 45.9033/31.6419/60.1648
[13:08:33.076] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 59.3858 for pixel 2/7 mean/min/max = 45.7362/32.0116/59.4608
[13:08:33.076] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 59.0655 for pixel 23/44 mean/min/max = 45.6039/32.1081/59.0998
[13:08:33.076] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 56.7353 for pixel 22/57 mean/min/max = 44.8256/32.8513/56.7999
[13:08:33.077] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 59.0236 for pixel 17/66 mean/min/max = 45.317/31.4819/59.1522
[13:08:33.077] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 58.8256 for pixel 43/0 mean/min/max = 45.27/31.5851/58.9549
[13:08:33.077] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 60.5631 for pixel 47/79 mean/min/max = 46.025/31.4107/60.6392
[13:08:33.077] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 57.4948 for pixel 2/14 mean/min/max = 45.3049/33.1018/57.5079
[13:08:33.078] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:08:33.210] <TB2> INFO: Expecting 1029120 events.
[13:08:57.200] <TB2> INFO: 1029120 events read in total (23274ms).
[13:08:57.206] <TB2> INFO: Expecting 1029120 events.
[13:09:20.770] <TB2> INFO: 1029120 events read in total (23019ms).
[13:09:20.776] <TB2> INFO: Expecting 1029120 events.
[13:09:44.473] <TB2> INFO: 1029120 events read in total (23158ms).
[13:09:44.481] <TB2> INFO: Expecting 1029120 events.
[13:10:07.908] <TB2> INFO: 1029120 events read in total (22884ms).
[13:10:07.920] <TB2> INFO: Expecting 1029120 events.
[13:10:32.072] <TB2> INFO: 1029120 events read in total (23624ms).
[13:10:32.085] <TB2> INFO: Expecting 1029120 events.
[13:10:55.914] <TB2> INFO: 1029120 events read in total (23302ms).
[13:10:55.932] <TB2> INFO: Expecting 1029120 events.
[13:11:20.005] <TB2> INFO: 1029120 events read in total (23545ms).
[13:11:20.022] <TB2> INFO: Expecting 1029120 events.
[13:11:44.004] <TB2> INFO: 1029120 events read in total (23455ms).
[13:11:44.024] <TB2> INFO: Expecting 1029120 events.
[13:12:07.643] <TB2> INFO: 1029120 events read in total (23093ms).
[13:12:07.669] <TB2> INFO: Expecting 1029120 events.
[13:12:31.520] <TB2> INFO: 1029120 events read in total (23323ms).
[13:12:31.542] <TB2> INFO: Expecting 1029120 events.
[13:12:55.396] <TB2> INFO: 1029120 events read in total (23327ms).
[13:12:55.420] <TB2> INFO: Expecting 1029120 events.
[13:13:19.176] <TB2> INFO: 1029120 events read in total (23228ms).
[13:13:19.207] <TB2> INFO: Expecting 1029120 events.
[13:13:43.031] <TB2> INFO: 1029120 events read in total (23296ms).
[13:13:43.067] <TB2> INFO: Expecting 1029120 events.
[13:14:06.724] <TB2> INFO: 1029120 events read in total (23129ms).
[13:14:06.756] <TB2> INFO: Expecting 1029120 events.
[13:14:30.491] <TB2> INFO: 1029120 events read in total (23208ms).
[13:14:30.530] <TB2> INFO: Expecting 1029120 events.
[13:14:54.021] <TB2> INFO: 1029120 events read in total (22963ms).
[13:14:54.055] <TB2> INFO: Test took 380977ms.
[13:14:55.092] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 20 dacrange: 0 .. 199 (-1/-1) hits flags = 16 (plus default)
[13:14:55.100] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[13:14:55.101] <TB2> INFO: run 1 of 1
[13:14:55.424] <TB2> INFO: Expecting 16640000 events.
[13:15:20.521] <TB2> INFO: 725120 events read in total (24381ms).
[13:15:44.712] <TB2> INFO: 1447020 events read in total (48573ms).
[13:16:09.007] <TB2> INFO: 2169020 events read in total (72867ms).
[13:16:33.275] <TB2> INFO: 2890880 events read in total (97135ms).
[13:16:57.605] <TB2> INFO: 3612680 events read in total (121465ms).
[13:17:21.960] <TB2> INFO: 4334140 events read in total (145820ms).
[13:17:46.271] <TB2> INFO: 5055560 events read in total (170131ms).
[13:18:10.733] <TB2> INFO: 5778480 events read in total (194593ms).
[13:18:35.423] <TB2> INFO: 6500880 events read in total (219283ms).
[13:18:59.942] <TB2> INFO: 7222420 events read in total (243802ms).
[13:19:24.119] <TB2> INFO: 7944040 events read in total (267979ms).
[13:19:48.519] <TB2> INFO: 8663480 events read in total (292379ms).
[13:20:12.761] <TB2> INFO: 9380560 events read in total (316621ms).
[13:20:36.975] <TB2> INFO: 10096300 events read in total (340835ms).
[13:21:01.151] <TB2> INFO: 10810860 events read in total (365011ms).
[13:21:25.387] <TB2> INFO: 11526000 events read in total (389247ms).
[13:21:49.515] <TB2> INFO: 12240000 events read in total (413375ms).
[13:22:13.899] <TB2> INFO: 12953000 events read in total (437759ms).
[13:22:38.117] <TB2> INFO: 13665740 events read in total (461977ms).
[13:23:02.422] <TB2> INFO: 14378080 events read in total (486282ms).
[13:23:26.658] <TB2> INFO: 15091560 events read in total (510518ms).
[13:23:48.561] <TB2> INFO: 15804380 events read in total (532421ms).
[13:24:11.698] <TB2> INFO: 16518740 events read in total (555558ms).
[13:24:16.220] <TB2> INFO: 16640000 events read in total (560080ms).
[13:24:16.280] <TB2> INFO: Test took 561179ms.
[13:24:16.483] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:24:40.644] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 1.701107 .. 255.000000
[13:24:40.720] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 20 dacrange: 1 .. 255 (-1/-1) hits flags = 16 (plus default)
[13:24:40.729] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[13:24:40.729] <TB2> INFO: run 1 of 1
[13:24:41.033] <TB2> INFO: Expecting 21216000 events.
[13:25:06.027] <TB2> INFO: 710680 events read in total (24277ms).
[13:25:30.099] <TB2> INFO: 1421720 events read in total (48349ms).
[13:25:54.241] <TB2> INFO: 2133240 events read in total (72491ms).
[13:26:18.288] <TB2> INFO: 2844240 events read in total (96538ms).
[13:26:40.403] <TB2> INFO: 3555700 events read in total (118653ms).
[13:27:04.450] <TB2> INFO: 4266560 events read in total (142700ms).
[13:27:28.468] <TB2> INFO: 4978100 events read in total (166718ms).
[13:27:52.512] <TB2> INFO: 5689380 events read in total (190762ms).
[13:28:16.631] <TB2> INFO: 6400420 events read in total (214881ms).
[13:28:40.638] <TB2> INFO: 7111900 events read in total (238888ms).
[13:29:02.981] <TB2> INFO: 7822740 events read in total (261231ms).
[13:29:26.963] <TB2> INFO: 8534640 events read in total (285213ms).
[13:29:51.261] <TB2> INFO: 9246040 events read in total (309511ms).
[13:30:15.552] <TB2> INFO: 9957440 events read in total (333802ms).
[13:30:39.493] <TB2> INFO: 10668720 events read in total (357743ms).
[13:31:01.806] <TB2> INFO: 11379720 events read in total (380056ms).
[13:31:26.005] <TB2> INFO: 12090540 events read in total (404255ms).
[13:31:50.285] <TB2> INFO: 12801800 events read in total (428535ms).
[13:32:14.621] <TB2> INFO: 13512020 events read in total (452871ms).
[13:32:38.671] <TB2> INFO: 14222240 events read in total (476921ms).
[13:33:01.792] <TB2> INFO: 14932460 events read in total (500042ms).
[13:33:25.883] <TB2> INFO: 15642760 events read in total (524133ms).
[13:33:50.043] <TB2> INFO: 16352280 events read in total (548293ms).
[13:34:14.019] <TB2> INFO: 17061340 events read in total (572269ms).
[13:34:37.318] <TB2> INFO: 17771100 events read in total (595568ms).
[13:35:00.857] <TB2> INFO: 18480460 events read in total (619107ms).
[13:35:22.623] <TB2> INFO: 19190200 events read in total (640873ms).
[13:35:44.263] <TB2> INFO: 19899440 events read in total (662513ms).
[13:36:06.310] <TB2> INFO: 20609360 events read in total (684560ms).
[13:36:25.298] <TB2> INFO: 21216000 events read in total (703548ms).
[13:36:25.410] <TB2> INFO: Test took 704681ms.
[13:36:25.715] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:36:54.617] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 16.099154 .. 46.121564
[13:36:54.692] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 20 dacrange: 6 .. 56 (-1/-1) hits flags = 16 (plus default)
[13:36:54.701] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[13:36:54.701] <TB2> INFO: run 1 of 1
[13:36:55.005] <TB2> INFO: Expecting 4243200 events.
[13:37:22.000] <TB2> INFO: 925920 events read in total (26268ms).
[13:37:48.127] <TB2> INFO: 1852180 events read in total (52395ms).
[13:38:14.618] <TB2> INFO: 2777160 events read in total (78887ms).
[13:38:40.836] <TB2> INFO: 3699120 events read in total (105104ms).
[13:38:56.646] <TB2> INFO: 4243200 events read in total (120914ms).
[13:38:56.669] <TB2> INFO: Test took 121968ms.
[13:38:56.710] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:39:12.076] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 11.500000 .. 43.290038
[13:39:12.179] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 20 dacrange: 1 .. 53 (-1/-1) hits flags = 16 (plus default)
[13:39:12.189] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[13:39:12.189] <TB2> INFO: run 1 of 1
[13:39:12.529] <TB2> INFO: Expecting 4409600 events.
[13:39:38.180] <TB2> INFO: 978060 events read in total (24935ms).
[13:40:04.965] <TB2> INFO: 1955960 events read in total (51720ms).
[13:40:30.415] <TB2> INFO: 2933360 events read in total (77170ms).
[13:40:56.994] <TB2> INFO: 3909020 events read in total (103749ms).
[13:41:10.869] <TB2> INFO: 4409600 events read in total (117624ms).
[13:41:10.886] <TB2> INFO: Test took 118698ms.
[13:41:10.920] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:41:23.840] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 11.500000 .. 43.139572
[13:41:23.915] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 20 dacrange: 1 .. 53 (-1/-1) hits flags = 16 (plus default)
[13:41:23.924] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[13:41:23.924] <TB2> INFO: run 1 of 1
[13:41:24.252] <TB2> INFO: Expecting 4409600 events.
[13:41:51.974] <TB2> INFO: 978240 events read in total (27005ms).
[13:42:18.852] <TB2> INFO: 1956720 events read in total (53883ms).
[13:42:45.515] <TB2> INFO: 2934840 events read in total (80546ms).
[13:43:12.261] <TB2> INFO: 3912240 events read in total (107292ms).
[13:43:25.070] <TB2> INFO: 4409600 events read in total (120101ms).
[13:43:25.088] <TB2> INFO: Test took 121164ms.
[13:43:25.125] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:43:38.773] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[13:43:38.773] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 20 dacrange: 15 .. 55 (-1/-1) hits flags = 16 (plus default)
[13:43:38.783] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[13:43:38.783] <TB2> INFO: run 1 of 1
[13:43:39.087] <TB2> INFO: Expecting 3411200 events.
[13:44:04.947] <TB2> INFO: 879600 events read in total (25144ms).
[13:44:30.347] <TB2> INFO: 1759220 events read in total (50544ms).
[13:44:56.278] <TB2> INFO: 2638300 events read in total (76476ms).
[13:45:19.265] <TB2> INFO: 3411200 events read in total (99462ms).
[13:45:19.290] <TB2> INFO: Test took 100507ms.
[13:45:19.328] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:45:35.182] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C0.dat
[13:45:35.183] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C1.dat
[13:45:35.183] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C2.dat
[13:45:35.183] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C3.dat
[13:45:35.183] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C4.dat
[13:45:35.184] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C5.dat
[13:45:35.184] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C6.dat
[13:45:35.184] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C7.dat
[13:45:35.184] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C8.dat
[13:45:35.185] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C9.dat
[13:45:35.185] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C10.dat
[13:45:35.185] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C11.dat
[13:45:35.185] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C12.dat
[13:45:35.186] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C13.dat
[13:45:35.186] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C14.dat
[13:45:35.186] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C15.dat
[13:45:35.187] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters35_C0.dat
[13:45:35.201] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters35_C1.dat
[13:45:35.211] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters35_C2.dat
[13:45:35.221] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters35_C3.dat
[13:45:35.231] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters35_C4.dat
[13:45:35.239] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters35_C5.dat
[13:45:35.248] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters35_C6.dat
[13:45:35.259] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters35_C7.dat
[13:45:35.269] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters35_C8.dat
[13:45:35.280] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters35_C9.dat
[13:45:35.287] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters35_C10.dat
[13:45:35.293] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters35_C11.dat
[13:45:35.302] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters35_C12.dat
[13:45:35.310] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters35_C13.dat
[13:45:35.320] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters35_C14.dat
[13:45:35.329] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//trimParameters35_C15.dat
[13:45:35.339] <TB2> INFO: PixTestTrim::trimTest() done
[13:45:35.339] <TB2> INFO: vtrim: 100 96 86 90 113 100 111 110 97 97 103 86 100 90 97 83
[13:45:35.339] <TB2> INFO: vthrcomp: 91 89 85 78 89 92 100 97 96 93 86 81 83 97 95 88
[13:45:35.339] <TB2> INFO: vcal mean: 34.98 34.99 34.96 35.05 34.99 34.97 34.99 34.99 34.98 34.94 34.98 34.99 35.00 34.95 34.99 34.97
[13:45:35.339] <TB2> INFO: vcal RMS: 0.73 0.72 0.68 0.65 0.71 0.73 0.75 0.74 0.71 1.41 0.70 0.65 0.74 0.88 0.73 0.68
[13:45:35.339] <TB2> INFO: bits mean: 9.37 8.53 9.79 8.27 9.59 9.42 9.19 9.50 8.77 8.94 9.36 9.49 9.51 9.38 8.85 9.25
[13:45:35.339] <TB2> INFO: bits RMS: 2.74 3.10 2.66 2.79 2.68 2.70 2.93 2.80 3.01 2.94 2.74 2.61 2.78 2.80 3.03 2.67
[13:45:35.347] <TB2> INFO: ----------------------------------------------------------------------
[13:45:35.347] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 10, vtrims = 254 126 63 32
[13:45:35.347] <TB2> INFO: ----------------------------------------------------------------------
[13:45:35.350] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 10 dacrange: 0 .. 199 (-1/-1) hits flags = 16 (plus default)
[13:45:35.361] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[13:45:35.361] <TB2> INFO: run 1 of 1
[13:45:35.664] <TB2> INFO: Expecting 8320000 events.
[13:46:05.784] <TB2> INFO: 918300 events read in total (29404ms).
[13:46:34.900] <TB2> INFO: 1826920 events read in total (58520ms).
[13:47:04.118] <TB2> INFO: 2733330 events read in total (87738ms).
[13:47:30.588] <TB2> INFO: 3637180 events read in total (114208ms).
[13:47:59.535] <TB2> INFO: 4536660 events read in total (143155ms).
[13:48:28.669] <TB2> INFO: 5431470 events read in total (172289ms).
[13:48:57.672] <TB2> INFO: 6325150 events read in total (201292ms).
[13:49:26.236] <TB2> INFO: 7217800 events read in total (229856ms).
[13:49:54.971] <TB2> INFO: 8113710 events read in total (258591ms).
[13:50:01.881] <TB2> INFO: 8320000 events read in total (265501ms).
[13:50:01.922] <TB2> INFO: Test took 266561ms.
[13:50:02.033] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:50:27.334] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 10 dacrange: 0 .. 165 (-1/-1) hits flags = 16 (plus default)
[13:50:27.343] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[13:50:27.343] <TB2> INFO: run 1 of 1
[13:50:27.649] <TB2> INFO: Expecting 6905600 events.
[13:50:57.488] <TB2> INFO: 954890 events read in total (29123ms).
[13:51:25.192] <TB2> INFO: 1898180 events read in total (56827ms).
[13:51:54.601] <TB2> INFO: 2838150 events read in total (86236ms).
[13:52:23.935] <TB2> INFO: 3771130 events read in total (115570ms).
[13:52:53.215] <TB2> INFO: 4697210 events read in total (144850ms).
[13:53:22.637] <TB2> INFO: 5620680 events read in total (174272ms).
[13:53:52.141] <TB2> INFO: 6546200 events read in total (203776ms).
[13:54:03.481] <TB2> INFO: 6905600 events read in total (215116ms).
[13:54:03.511] <TB2> INFO: Test took 216168ms.
[13:54:03.592] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:54:26.362] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 10 dacrange: 0 .. 152 (-1/-1) hits flags = 16 (plus default)
[13:54:26.371] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[13:54:26.371] <TB2> INFO: run 1 of 1
[13:54:26.673] <TB2> INFO: Expecting 6364800 events.
[13:54:55.703] <TB2> INFO: 990570 events read in total (28314ms).
[13:55:24.980] <TB2> INFO: 1968050 events read in total (57591ms).
[13:55:54.859] <TB2> INFO: 2940550 events read in total (87471ms).
[13:56:24.583] <TB2> INFO: 3901710 events read in total (117194ms).
[13:56:54.203] <TB2> INFO: 4858660 events read in total (146814ms).
[13:57:23.695] <TB2> INFO: 5814230 events read in total (176306ms).
[13:57:40.883] <TB2> INFO: 6364800 events read in total (193494ms).
[13:57:40.914] <TB2> INFO: Test took 194543ms.
[13:57:40.988] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:58:02.197] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 10 dacrange: 0 .. 153 (-1/-1) hits flags = 16 (plus default)
[13:58:02.206] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[13:58:02.206] <TB2> INFO: run 1 of 1
[13:58:02.509] <TB2> INFO: Expecting 6406400 events.
[13:58:31.070] <TB2> INFO: 986890 events read in total (27844ms).
[13:59:01.207] <TB2> INFO: 1960980 events read in total (57981ms).
[13:59:31.008] <TB2> INFO: 2930200 events read in total (87783ms).
[14:00:00.745] <TB2> INFO: 3888610 events read in total (117519ms).
[14:00:30.411] <TB2> INFO: 4842510 events read in total (147185ms).
[14:01:00.171] <TB2> INFO: 5794740 events read in total (176945ms).
[14:01:19.363] <TB2> INFO: 6406400 events read in total (196137ms).
[14:01:19.395] <TB2> INFO: Test took 197189ms.
[14:01:19.463] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:01:42.719] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 10 dacrange: 0 .. 152 (-1/-1) hits flags = 16 (plus default)
[14:01:42.728] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[14:01:42.728] <TB2> INFO: run 1 of 1
[14:01:43.048] <TB2> INFO: Expecting 6364800 events.
[14:02:11.412] <TB2> INFO: 989500 events read in total (27647ms).
[14:02:41.492] <TB2> INFO: 1965970 events read in total (57728ms).
[14:03:11.291] <TB2> INFO: 2937390 events read in total (87526ms).
[14:03:41.247] <TB2> INFO: 3897470 events read in total (117482ms).
[14:04:10.997] <TB2> INFO: 4852950 events read in total (147232ms).
[14:04:40.649] <TB2> INFO: 5807400 events read in total (176884ms).
[14:04:58.148] <TB2> INFO: 6364800 events read in total (194383ms).
[14:04:58.185] <TB2> INFO: Test took 195457ms.
[14:04:58.260] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:05:20.640] <TB2> INFO: PixTestTrim::trimBitTest() done
[14:05:20.642] <TB2> INFO: PixTestTrim::doTest() done, duration: 4207 seconds
[14:05:21.354] <TB2> INFO: ######################################################################
[14:05:21.354] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[14:05:21.354] <TB2> INFO: ######################################################################
[14:05:21.664] <TB2> INFO: Expecting 41600 events.
[14:05:25.946] <TB2> INFO: 41600 events read in total (3566ms).
[14:05:25.947] <TB2> INFO: Test took 4592ms.
[14:05:25.953] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:05:26.521] <TB2> INFO: Expecting 41600 events.
[14:05:30.861] <TB2> INFO: 41600 events read in total (3624ms).
[14:05:30.861] <TB2> INFO: Test took 4649ms.
[14:05:30.867] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:05:31.205] <TB2> INFO: Expecting 41600 events.
[14:05:35.574] <TB2> INFO: 41600 events read in total (3653ms).
[14:05:35.575] <TB2> INFO: Test took 4694ms.
[14:05:35.583] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:05:35.593] <TB2> INFO: The DUT currently contains the following objects:
[14:05:35.593] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[14:05:35.593] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:05:35.593] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:05:35.593] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:05:35.593] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:35.593] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:35.593] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:35.593] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:35.593] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:35.593] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:35.593] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:35.593] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:35.593] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:35.594] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:35.594] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:35.594] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:35.594] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:35.594] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:35.594] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:35.594] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:35.914] <TB2> INFO: Expecting 2560 events.
[14:05:36.978] <TB2> INFO: 2560 events read in total (348ms).
[14:05:36.978] <TB2> INFO: Test took 1384ms.
[14:05:36.979] <TB2> INFO: The DUT currently contains the following objects:
[14:05:36.979] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[14:05:36.979] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:05:36.979] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:05:36.979] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:05:36.979] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:36.979] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:36.979] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:36.979] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:36.979] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:36.979] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:36.979] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:36.979] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:36.979] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:36.979] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:36.979] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:36.979] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:36.979] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:36.979] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:36.979] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:36.979] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:37.393] <TB2> INFO: Expecting 2560 events.
[14:05:38.470] <TB2> INFO: 2560 events read in total (361ms).
[14:05:38.471] <TB2> INFO: Test took 1492ms.
[14:05:38.471] <TB2> INFO: The DUT currently contains the following objects:
[14:05:38.471] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[14:05:38.471] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:05:38.471] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:05:38.471] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:05:38.471] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:38.471] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:38.471] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:38.471] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:38.471] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:38.471] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:38.471] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:38.471] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:38.471] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:38.471] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:38.471] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:38.471] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:38.471] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:38.471] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:38.471] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:38.471] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:38.885] <TB2> INFO: Expecting 2560 events.
[14:05:39.949] <TB2> INFO: 2560 events read in total (348ms).
[14:05:39.949] <TB2> INFO: Test took 1478ms.
[14:05:39.949] <TB2> INFO: The DUT currently contains the following objects:
[14:05:39.949] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[14:05:39.950] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:05:39.950] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:05:39.950] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:05:39.950] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:39.950] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:39.950] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:39.950] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:39.950] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:39.950] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:39.950] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:39.950] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:39.950] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:39.950] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:39.950] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:39.950] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:39.950] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:39.950] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:39.950] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:39.950] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:40.364] <TB2> INFO: Expecting 2560 events.
[14:05:41.441] <TB2> INFO: 2560 events read in total (361ms).
[14:05:41.441] <TB2> INFO: Test took 1491ms.
[14:05:41.441] <TB2> INFO: The DUT currently contains the following objects:
[14:05:41.441] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[14:05:41.441] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:05:41.441] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:05:41.441] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:05:41.441] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:41.441] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:41.441] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:41.441] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:41.441] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:41.441] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:41.441] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:41.441] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:41.441] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:41.441] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:41.441] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:41.441] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:41.441] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:41.442] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:41.442] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:41.442] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:41.855] <TB2> INFO: Expecting 2560 events.
[14:05:42.918] <TB2> INFO: 2560 events read in total (346ms).
[14:05:42.918] <TB2> INFO: Test took 1476ms.
[14:05:42.918] <TB2> INFO: The DUT currently contains the following objects:
[14:05:42.918] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[14:05:42.919] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:05:42.919] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:05:42.919] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:05:42.919] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:42.919] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:42.919] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:42.919] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:42.919] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:42.919] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:42.919] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:42.919] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:42.919] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:42.919] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:42.919] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:42.919] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:42.919] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:42.919] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:42.919] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:42.919] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:43.333] <TB2> INFO: Expecting 2560 events.
[14:05:44.397] <TB2> INFO: 2560 events read in total (348ms).
[14:05:44.397] <TB2> INFO: Test took 1478ms.
[14:05:44.398] <TB2> INFO: The DUT currently contains the following objects:
[14:05:44.398] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[14:05:44.398] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:05:44.398] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:05:44.398] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:05:44.398] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:44.398] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:44.398] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:44.398] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:44.398] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:44.398] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:44.398] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:44.398] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:44.398] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:44.398] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:44.398] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:44.398] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:44.398] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:44.398] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:44.398] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:44.398] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:44.812] <TB2> INFO: Expecting 2560 events.
[14:05:45.891] <TB2> INFO: 2560 events read in total (363ms).
[14:05:45.891] <TB2> INFO: Test took 1493ms.
[14:05:45.892] <TB2> INFO: The DUT currently contains the following objects:
[14:05:45.892] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[14:05:45.892] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:05:45.892] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:05:45.892] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:05:45.892] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:45.892] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:45.892] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:45.892] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:45.892] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:45.892] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:45.892] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:45.892] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:45.892] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:45.892] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:45.892] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:45.892] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:45.892] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:45.892] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:45.892] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:45.892] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:46.306] <TB2> INFO: Expecting 2560 events.
[14:05:47.370] <TB2> INFO: 2560 events read in total (348ms).
[14:05:47.370] <TB2> INFO: Test took 1478ms.
[14:05:47.370] <TB2> INFO: The DUT currently contains the following objects:
[14:05:47.370] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[14:05:47.370] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:05:47.370] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:05:47.370] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:05:47.370] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:47.370] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:47.370] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:47.371] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:47.371] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:47.371] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:47.371] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:47.371] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:47.371] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:47.371] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:47.371] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:47.371] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:47.371] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:47.371] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:47.371] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:47.371] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:47.785] <TB2> INFO: Expecting 2560 events.
[14:05:48.849] <TB2> INFO: 2560 events read in total (348ms).
[14:05:48.849] <TB2> INFO: Test took 1478ms.
[14:05:48.849] <TB2> INFO: The DUT currently contains the following objects:
[14:05:48.849] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[14:05:48.849] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:05:48.849] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:05:48.849] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:05:48.849] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:48.849] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:48.849] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:48.849] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:48.849] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:48.849] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:48.849] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:48.849] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:48.849] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:48.849] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:48.849] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:48.849] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:48.849] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:48.849] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:48.849] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:48.850] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:49.264] <TB2> INFO: Expecting 2560 events.
[14:05:50.327] <TB2> INFO: 2560 events read in total (347ms).
[14:05:50.327] <TB2> INFO: Test took 1477ms.
[14:05:50.327] <TB2> INFO: The DUT currently contains the following objects:
[14:05:50.327] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[14:05:50.327] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:05:50.327] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:05:50.327] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:05:50.327] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:50.327] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:50.327] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:50.327] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:50.327] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:50.327] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:50.327] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:50.327] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:50.327] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:50.327] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:50.327] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:50.327] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:50.327] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:50.327] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:50.328] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:50.328] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:50.742] <TB2> INFO: Expecting 2560 events.
[14:05:51.804] <TB2> INFO: 2560 events read in total (346ms).
[14:05:51.804] <TB2> INFO: Test took 1476ms.
[14:05:51.804] <TB2> INFO: The DUT currently contains the following objects:
[14:05:51.804] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[14:05:51.804] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:05:51.804] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:05:51.804] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:05:51.804] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:51.804] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:51.804] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:51.804] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:51.804] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:51.804] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:51.804] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:51.804] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:51.804] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:51.804] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:51.804] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:51.804] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:51.804] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:51.804] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:51.804] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:51.804] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:52.218] <TB2> INFO: Expecting 2560 events.
[14:05:53.280] <TB2> INFO: 2560 events read in total (346ms).
[14:05:53.280] <TB2> INFO: Test took 1476ms.
[14:05:53.281] <TB2> INFO: The DUT currently contains the following objects:
[14:05:53.281] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[14:05:53.281] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:05:53.281] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:05:53.281] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:05:53.281] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:53.281] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:53.281] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:53.281] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:53.281] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:53.281] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:53.281] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:53.281] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:53.281] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:53.281] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:53.281] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:53.281] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:53.281] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:53.281] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:53.281] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:53.281] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:53.695] <TB2> INFO: Expecting 2560 events.
[14:05:54.757] <TB2> INFO: 2560 events read in total (346ms).
[14:05:54.757] <TB2> INFO: Test took 1476ms.
[14:05:54.757] <TB2> INFO: The DUT currently contains the following objects:
[14:05:54.757] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[14:05:54.757] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:05:54.757] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:05:54.757] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:05:54.757] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:54.757] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:54.757] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:54.757] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:54.757] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:54.757] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:54.757] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:54.757] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:54.757] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:54.757] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:54.757] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:54.758] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:54.758] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:54.758] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:54.758] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:54.758] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:55.171] <TB2> INFO: Expecting 2560 events.
[14:05:56.233] <TB2> INFO: 2560 events read in total (346ms).
[14:05:56.233] <TB2> INFO: Test took 1475ms.
[14:05:56.234] <TB2> INFO: The DUT currently contains the following objects:
[14:05:56.234] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[14:05:56.234] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:05:56.234] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:05:56.234] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:05:56.234] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:56.234] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:56.234] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:56.234] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:56.234] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:56.234] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:56.234] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:56.234] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:56.234] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:56.234] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:56.234] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:56.234] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:56.234] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:56.234] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:56.234] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:56.234] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:56.648] <TB2> INFO: Expecting 2560 events.
[14:05:57.712] <TB2> INFO: 2560 events read in total (348ms).
[14:05:57.712] <TB2> INFO: Test took 1478ms.
[14:05:57.712] <TB2> INFO: The DUT currently contains the following objects:
[14:05:57.712] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[14:05:57.712] <TB2> INFO: TBM Core alpha (0): 7 registers set
[14:05:57.712] <TB2> INFO: TBM Core beta (1): 7 registers set
[14:05:57.712] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[14:05:57.712] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:57.712] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:57.712] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:57.712] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:57.712] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:57.713] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:57.713] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:57.713] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:57.713] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:57.713] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:57.713] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:57.713] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:57.713] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:57.713] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:57.713] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:57.713] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[14:05:58.127] <TB2> INFO: Expecting 2560 events.
[14:05:59.189] <TB2> INFO: 2560 events read in total (346ms).
[14:05:59.190] <TB2> INFO: Test took 1477ms.
[14:05:59.192] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:05:59.606] <TB2> INFO: Expecting 655360 events.
[14:06:14.862] <TB2> INFO: 655360 events read in total (14540ms).
[14:06:14.871] <TB2> INFO: Expecting 655360 events.
[14:06:30.038] <TB2> INFO: 655360 events read in total (14640ms).
[14:06:30.053] <TB2> INFO: Expecting 655360 events.
[14:06:45.828] <TB2> INFO: 655360 events read in total (15248ms).
[14:06:45.844] <TB2> INFO: Expecting 655360 events.
[14:07:02.287] <TB2> INFO: 655360 events read in total (15915ms).
[14:07:02.309] <TB2> INFO: Expecting 655360 events.
[14:07:18.479] <TB2> INFO: 655360 events read in total (15643ms).
[14:07:18.501] <TB2> INFO: Expecting 655360 events.
[14:07:34.767] <TB2> INFO: 655360 events read in total (15739ms).
[14:07:34.795] <TB2> INFO: Expecting 655360 events.
[14:07:51.127] <TB2> INFO: 655360 events read in total (15804ms).
[14:07:51.155] <TB2> INFO: Expecting 655360 events.
[14:08:06.137] <TB2> INFO: 655360 events read in total (14454ms).
[14:08:06.169] <TB2> INFO: Expecting 655360 events.
[14:08:21.060] <TB2> INFO: 655360 events read in total (14364ms).
[14:08:21.097] <TB2> INFO: Expecting 655360 events.
[14:08:37.618] <TB2> INFO: 655360 events read in total (15994ms).
[14:08:37.667] <TB2> INFO: Expecting 655360 events.
[14:08:54.038] <TB2> INFO: 655360 events read in total (15843ms).
[14:08:54.081] <TB2> INFO: Expecting 655360 events.
[14:09:09.230] <TB2> INFO: 655360 events read in total (14621ms).
[14:09:09.280] <TB2> INFO: Expecting 655360 events.
[14:09:24.398] <TB2> INFO: 655360 events read in total (14590ms).
[14:09:24.446] <TB2> INFO: Expecting 655360 events.
[14:09:40.853] <TB2> INFO: 655360 events read in total (15880ms).
[14:09:40.913] <TB2> INFO: Expecting 655360 events.
[14:09:57.564] <TB2> INFO: 655360 events read in total (16124ms).
[14:09:57.624] <TB2> INFO: Expecting 655360 events.
[14:10:14.358] <TB2> INFO: 655360 events read in total (16207ms).
[14:10:14.427] <TB2> INFO: Test took 255235ms.
[14:10:14.519] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:10:14.826] <TB2> INFO: Expecting 655360 events.
[14:10:31.646] <TB2> INFO: 655360 events read in total (16103ms).
[14:10:31.657] <TB2> INFO: Expecting 655360 events.
[14:10:48.055] <TB2> INFO: 655360 events read in total (15870ms).
[14:10:48.067] <TB2> INFO: Expecting 655360 events.
[14:11:04.563] <TB2> INFO: 655360 events read in total (15968ms).
[14:11:04.581] <TB2> INFO: Expecting 655360 events.
[14:11:21.123] <TB2> INFO: 655360 events read in total (16014ms).
[14:11:21.144] <TB2> INFO: Expecting 655360 events.
[14:11:37.629] <TB2> INFO: 655360 events read in total (15957ms).
[14:11:37.654] <TB2> INFO: Expecting 655360 events.
[14:11:54.118] <TB2> INFO: 655360 events read in total (15936ms).
[14:11:54.144] <TB2> INFO: Expecting 655360 events.
[14:12:10.740] <TB2> INFO: 655360 events read in total (16069ms).
[14:12:10.777] <TB2> INFO: Expecting 655360 events.
[14:12:27.173] <TB2> INFO: 655360 events read in total (15869ms).
[14:12:27.205] <TB2> INFO: Expecting 655360 events.
[14:12:43.560] <TB2> INFO: 655360 events read in total (15828ms).
[14:12:43.596] <TB2> INFO: Expecting 655360 events.
[14:13:00.199] <TB2> INFO: 655360 events read in total (16076ms).
[14:13:00.245] <TB2> INFO: Expecting 655360 events.
[14:13:16.501] <TB2> INFO: 655360 events read in total (15728ms).
[14:13:16.543] <TB2> INFO: Expecting 655360 events.
[14:13:32.912] <TB2> INFO: 655360 events read in total (15841ms).
[14:13:32.972] <TB2> INFO: Expecting 655360 events.
[14:13:49.505] <TB2> INFO: 655360 events read in total (16006ms).
[14:13:49.557] <TB2> INFO: Expecting 655360 events.
[14:14:06.178] <TB2> INFO: 655360 events read in total (16093ms).
[14:14:06.232] <TB2> INFO: Expecting 655360 events.
[14:14:22.657] <TB2> INFO: 655360 events read in total (15898ms).
[14:14:22.713] <TB2> INFO: Expecting 655360 events.
[14:14:39.389] <TB2> INFO: 655360 events read in total (16148ms).
[14:14:39.448] <TB2> INFO: Test took 264929ms.
[14:14:39.644] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:14:39.654] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:14:39.665] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:14:39.674] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:14:39.685] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:14:39.695] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:14:39.706] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:14:39.717] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:14:39.728] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:14:39.738] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:14:39.747] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:14:39.757] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:14:39.768] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[14:14:39.778] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[14:14:39.789] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[14:14:39.799] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:14:39.810] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:14:39.817] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:14:39.824] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[14:14:39.868] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C0.dat
[14:14:39.869] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C1.dat
[14:14:39.869] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C2.dat
[14:14:39.869] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C3.dat
[14:14:39.869] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C4.dat
[14:14:39.869] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C5.dat
[14:14:39.869] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C6.dat
[14:14:39.870] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C7.dat
[14:14:39.870] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C8.dat
[14:14:39.870] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C9.dat
[14:14:39.870] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C10.dat
[14:14:39.870] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C11.dat
[14:14:39.870] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C12.dat
[14:14:39.870] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C13.dat
[14:14:39.871] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C14.dat
[14:14:39.871] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//dacParameters35_C15.dat
[14:14:40.193] <TB2> INFO: Expecting 41600 events.
[14:14:44.692] <TB2> INFO: 41600 events read in total (3783ms).
[14:14:44.692] <TB2> INFO: Test took 4819ms.
[14:14:45.275] <TB2> INFO: Expecting 41600 events.
[14:14:49.798] <TB2> INFO: 41600 events read in total (3806ms).
[14:14:49.798] <TB2> INFO: Test took 4885ms.
[14:14:50.342] <TB2> INFO: Expecting 41600 events.
[14:14:54.788] <TB2> INFO: 41600 events read in total (3730ms).
[14:14:54.789] <TB2> INFO: Test took 4748ms.
[14:14:55.033] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:14:55.166] <TB2> INFO: Expecting 2560 events.
[14:14:56.234] <TB2> INFO: 2560 events read in total (352ms).
[14:14:56.235] <TB2> INFO: Test took 1202ms.
[14:14:56.237] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:14:56.650] <TB2> INFO: Expecting 2560 events.
[14:14:57.722] <TB2> INFO: 2560 events read in total (355ms).
[14:14:57.722] <TB2> INFO: Test took 1485ms.
[14:14:57.725] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:14:58.138] <TB2> INFO: Expecting 2560 events.
[14:14:59.209] <TB2> INFO: 2560 events read in total (355ms).
[14:14:59.209] <TB2> INFO: Test took 1484ms.
[14:14:59.212] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:14:59.625] <TB2> INFO: Expecting 2560 events.
[14:15:00.697] <TB2> INFO: 2560 events read in total (355ms).
[14:15:00.698] <TB2> INFO: Test took 1486ms.
[14:15:00.700] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:01.113] <TB2> INFO: Expecting 2560 events.
[14:15:02.183] <TB2> INFO: 2560 events read in total (353ms).
[14:15:02.183] <TB2> INFO: Test took 1483ms.
[14:15:02.186] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:02.599] <TB2> INFO: Expecting 2560 events.
[14:15:03.670] <TB2> INFO: 2560 events read in total (354ms).
[14:15:03.671] <TB2> INFO: Test took 1485ms.
[14:15:03.673] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:04.087] <TB2> INFO: Expecting 2560 events.
[14:15:05.159] <TB2> INFO: 2560 events read in total (356ms).
[14:15:05.159] <TB2> INFO: Test took 1486ms.
[14:15:05.162] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:05.576] <TB2> INFO: Expecting 2560 events.
[14:15:06.647] <TB2> INFO: 2560 events read in total (355ms).
[14:15:06.648] <TB2> INFO: Test took 1486ms.
[14:15:06.651] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:07.063] <TB2> INFO: Expecting 2560 events.
[14:15:08.131] <TB2> INFO: 2560 events read in total (352ms).
[14:15:08.132] <TB2> INFO: Test took 1481ms.
[14:15:08.135] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:08.548] <TB2> INFO: Expecting 2560 events.
[14:15:09.616] <TB2> INFO: 2560 events read in total (352ms).
[14:15:09.616] <TB2> INFO: Test took 1482ms.
[14:15:09.619] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:10.032] <TB2> INFO: Expecting 2560 events.
[14:15:11.100] <TB2> INFO: 2560 events read in total (351ms).
[14:15:11.101] <TB2> INFO: Test took 1483ms.
[14:15:11.104] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:11.517] <TB2> INFO: Expecting 2560 events.
[14:15:12.582] <TB2> INFO: 2560 events read in total (349ms).
[14:15:12.582] <TB2> INFO: Test took 1479ms.
[14:15:12.585] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:12.998] <TB2> INFO: Expecting 2560 events.
[14:15:14.068] <TB2> INFO: 2560 events read in total (354ms).
[14:15:14.068] <TB2> INFO: Test took 1483ms.
[14:15:14.071] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:14.483] <TB2> INFO: Expecting 2560 events.
[14:15:15.551] <TB2> INFO: 2560 events read in total (351ms).
[14:15:15.552] <TB2> INFO: Test took 1481ms.
[14:15:15.553] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:15.968] <TB2> INFO: Expecting 2560 events.
[14:15:17.036] <TB2> INFO: 2560 events read in total (352ms).
[14:15:17.036] <TB2> INFO: Test took 1483ms.
[14:15:17.039] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:17.452] <TB2> INFO: Expecting 2560 events.
[14:15:18.522] <TB2> INFO: 2560 events read in total (353ms).
[14:15:18.522] <TB2> INFO: Test took 1483ms.
[14:15:18.525] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:18.938] <TB2> INFO: Expecting 2560 events.
[14:15:20.008] <TB2> INFO: 2560 events read in total (353ms).
[14:15:20.008] <TB2> INFO: Test took 1483ms.
[14:15:20.011] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:20.424] <TB2> INFO: Expecting 2560 events.
[14:15:21.491] <TB2> INFO: 2560 events read in total (351ms).
[14:15:21.491] <TB2> INFO: Test took 1480ms.
[14:15:21.493] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:21.908] <TB2> INFO: Expecting 2560 events.
[14:15:22.979] <TB2> INFO: 2560 events read in total (355ms).
[14:15:22.980] <TB2> INFO: Test took 1487ms.
[14:15:22.983] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:23.395] <TB2> INFO: Expecting 2560 events.
[14:15:24.463] <TB2> INFO: 2560 events read in total (352ms).
[14:15:24.463] <TB2> INFO: Test took 1481ms.
[14:15:24.465] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:24.879] <TB2> INFO: Expecting 2560 events.
[14:15:25.946] <TB2> INFO: 2560 events read in total (351ms).
[14:15:25.947] <TB2> INFO: Test took 1482ms.
[14:15:25.949] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:26.363] <TB2> INFO: Expecting 2560 events.
[14:15:27.430] <TB2> INFO: 2560 events read in total (351ms).
[14:15:27.431] <TB2> INFO: Test took 1482ms.
[14:15:27.433] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:27.846] <TB2> INFO: Expecting 2560 events.
[14:15:28.918] <TB2> INFO: 2560 events read in total (356ms).
[14:15:28.919] <TB2> INFO: Test took 1486ms.
[14:15:28.921] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:29.334] <TB2> INFO: Expecting 2560 events.
[14:15:30.402] <TB2> INFO: 2560 events read in total (352ms).
[14:15:30.402] <TB2> INFO: Test took 1481ms.
[14:15:30.405] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:30.818] <TB2> INFO: Expecting 2560 events.
[14:15:31.884] <TB2> INFO: 2560 events read in total (349ms).
[14:15:31.885] <TB2> INFO: Test took 1480ms.
[14:15:31.901] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:32.300] <TB2> INFO: Expecting 2560 events.
[14:15:33.373] <TB2> INFO: 2560 events read in total (356ms).
[14:15:33.374] <TB2> INFO: Test took 1473ms.
[14:15:33.377] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:33.790] <TB2> INFO: Expecting 2560 events.
[14:15:34.854] <TB2> INFO: 2560 events read in total (348ms).
[14:15:34.855] <TB2> INFO: Test took 1478ms.
[14:15:34.857] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:35.271] <TB2> INFO: Expecting 2560 events.
[14:15:36.343] <TB2> INFO: 2560 events read in total (356ms).
[14:15:36.343] <TB2> INFO: Test took 1486ms.
[14:15:36.346] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:36.759] <TB2> INFO: Expecting 2560 events.
[14:15:37.832] <TB2> INFO: 2560 events read in total (356ms).
[14:15:37.833] <TB2> INFO: Test took 1487ms.
[14:15:37.836] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:38.248] <TB2> INFO: Expecting 2560 events.
[14:15:39.316] <TB2> INFO: 2560 events read in total (352ms).
[14:15:39.317] <TB2> INFO: Test took 1482ms.
[14:15:39.320] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:39.732] <TB2> INFO: Expecting 2560 events.
[14:15:40.799] <TB2> INFO: 2560 events read in total (351ms).
[14:15:40.800] <TB2> INFO: Test took 1480ms.
[14:15:40.803] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:15:41.215] <TB2> INFO: Expecting 2560 events.
[14:15:42.282] <TB2> INFO: 2560 events read in total (351ms).
[14:15:42.282] <TB2> INFO: Test took 1480ms.
[14:15:42.908] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 621 seconds
[14:15:42.908] <TB2> INFO: PH scale (per ROC): 80 80 93 80 83 78 84 79 77 82 85 80 74 76 76 86
[14:15:42.908] <TB2> INFO: PH offset (per ROC): 153 158 162 155 159 159 180 169 159 158 149 147 165 166 179 149
[14:15:43.085] <TB2> INFO: ######################################################################
[14:15:43.085] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[14:15:43.085] <TB2> INFO: ######################################################################
[14:15:43.095] <TB2> INFO: scanning low vcal = 10
[14:15:43.398] <TB2> INFO: Expecting 41600 events.
[14:15:47.028] <TB2> INFO: 41600 events read in total (2914ms).
[14:15:47.028] <TB2> INFO: Test took 3933ms.
[14:15:47.031] <TB2> INFO: scanning low vcal = 20
[14:15:47.444] <TB2> INFO: Expecting 41600 events.
[14:15:51.035] <TB2> INFO: 41600 events read in total (2875ms).
[14:15:51.035] <TB2> INFO: Test took 4004ms.
[14:15:51.038] <TB2> INFO: scanning low vcal = 30
[14:15:51.451] <TB2> INFO: Expecting 41600 events.
[14:15:55.066] <TB2> INFO: 41600 events read in total (2898ms).
[14:15:55.066] <TB2> INFO: Test took 4028ms.
[14:15:55.070] <TB2> INFO: scanning low vcal = 40
[14:15:55.475] <TB2> INFO: Expecting 41600 events.
[14:15:59.725] <TB2> INFO: 41600 events read in total (3534ms).
[14:15:59.726] <TB2> INFO: Test took 4656ms.
[14:15:59.729] <TB2> INFO: scanning low vcal = 50
[14:16:00.081] <TB2> INFO: Expecting 41600 events.
[14:16:04.265] <TB2> INFO: 41600 events read in total (3467ms).
[14:16:04.266] <TB2> INFO: Test took 4537ms.
[14:16:04.268] <TB2> INFO: scanning low vcal = 60
[14:16:04.622] <TB2> INFO: Expecting 41600 events.
[14:16:08.847] <TB2> INFO: 41600 events read in total (3509ms).
[14:16:08.847] <TB2> INFO: Test took 4579ms.
[14:16:08.850] <TB2> INFO: scanning low vcal = 70
[14:16:09.192] <TB2> INFO: Expecting 41600 events.
[14:16:13.405] <TB2> INFO: 41600 events read in total (3496ms).
[14:16:13.405] <TB2> INFO: Test took 4555ms.
[14:16:13.408] <TB2> INFO: scanning low vcal = 80
[14:16:13.766] <TB2> INFO: Expecting 41600 events.
[14:16:18.002] <TB2> INFO: 41600 events read in total (3520ms).
[14:16:18.003] <TB2> INFO: Test took 4595ms.
[14:16:18.006] <TB2> INFO: scanning low vcal = 90
[14:16:18.334] <TB2> INFO: Expecting 41600 events.
[14:16:22.622] <TB2> INFO: 41600 events read in total (3571ms).
[14:16:22.622] <TB2> INFO: Test took 4616ms.
[14:16:22.625] <TB2> INFO: scanning low vcal = 100
[14:16:22.983] <TB2> INFO: Expecting 41600 events.
[14:16:27.149] <TB2> INFO: 41600 events read in total (3450ms).
[14:16:27.149] <TB2> INFO: Test took 4524ms.
[14:16:27.152] <TB2> INFO: scanning low vcal = 110
[14:16:27.509] <TB2> INFO: Expecting 41600 events.
[14:16:31.695] <TB2> INFO: 41600 events read in total (3470ms).
[14:16:31.696] <TB2> INFO: Test took 4544ms.
[14:16:31.698] <TB2> INFO: scanning low vcal = 120
[14:16:32.053] <TB2> INFO: Expecting 41600 events.
[14:16:36.208] <TB2> INFO: 41600 events read in total (3438ms).
[14:16:36.209] <TB2> INFO: Test took 4511ms.
[14:16:36.212] <TB2> INFO: scanning low vcal = 130
[14:16:36.569] <TB2> INFO: Expecting 41600 events.
[14:16:40.772] <TB2> INFO: 41600 events read in total (3487ms).
[14:16:40.772] <TB2> INFO: Test took 4560ms.
[14:16:40.775] <TB2> INFO: scanning low vcal = 140
[14:16:41.121] <TB2> INFO: Expecting 41600 events.
[14:16:45.372] <TB2> INFO: 41600 events read in total (3535ms).
[14:16:45.372] <TB2> INFO: Test took 4597ms.
[14:16:45.375] <TB2> INFO: scanning low vcal = 150
[14:16:45.719] <TB2> INFO: Expecting 41600 events.
[14:16:49.953] <TB2> INFO: 41600 events read in total (3518ms).
[14:16:49.954] <TB2> INFO: Test took 4579ms.
[14:16:49.957] <TB2> INFO: scanning low vcal = 160
[14:16:50.310] <TB2> INFO: Expecting 41600 events.
[14:16:54.539] <TB2> INFO: 41600 events read in total (3513ms).
[14:16:54.540] <TB2> INFO: Test took 4583ms.
[14:16:54.542] <TB2> INFO: scanning low vcal = 170
[14:16:54.900] <TB2> INFO: Expecting 41600 events.
[14:16:59.139] <TB2> INFO: 41600 events read in total (3523ms).
[14:16:59.139] <TB2> INFO: Test took 4597ms.
[14:16:59.144] <TB2> INFO: scanning low vcal = 180
[14:16:59.497] <TB2> INFO: Expecting 41600 events.
[14:17:03.638] <TB2> INFO: 41600 events read in total (3424ms).
[14:17:03.638] <TB2> INFO: Test took 4494ms.
[14:17:03.641] <TB2> INFO: scanning low vcal = 190
[14:17:03.999] <TB2> INFO: Expecting 41600 events.
[14:17:08.197] <TB2> INFO: 41600 events read in total (3482ms).
[14:17:08.198] <TB2> INFO: Test took 4557ms.
[14:17:08.200] <TB2> INFO: scanning low vcal = 200
[14:17:08.537] <TB2> INFO: Expecting 41600 events.
[14:17:12.776] <TB2> INFO: 41600 events read in total (3522ms).
[14:17:12.776] <TB2> INFO: Test took 4576ms.
[14:17:12.780] <TB2> INFO: scanning low vcal = 210
[14:17:13.133] <TB2> INFO: Expecting 41600 events.
[14:17:17.389] <TB2> INFO: 41600 events read in total (3540ms).
[14:17:17.389] <TB2> INFO: Test took 4609ms.
[14:17:17.392] <TB2> INFO: scanning low vcal = 220
[14:17:17.749] <TB2> INFO: Expecting 41600 events.
[14:17:21.949] <TB2> INFO: 41600 events read in total (3483ms).
[14:17:21.949] <TB2> INFO: Test took 4557ms.
[14:17:21.952] <TB2> INFO: scanning low vcal = 230
[14:17:22.304] <TB2> INFO: Expecting 41600 events.
[14:17:26.586] <TB2> INFO: 41600 events read in total (3565ms).
[14:17:26.586] <TB2> INFO: Test took 4634ms.
[14:17:26.589] <TB2> INFO: scanning low vcal = 240
[14:17:26.939] <TB2> INFO: Expecting 41600 events.
[14:17:31.096] <TB2> INFO: 41600 events read in total (3441ms).
[14:17:31.096] <TB2> INFO: Test took 4507ms.
[14:17:31.100] <TB2> INFO: scanning low vcal = 250
[14:17:31.457] <TB2> INFO: Expecting 41600 events.
[14:17:35.720] <TB2> INFO: 41600 events read in total (3548ms).
[14:17:35.721] <TB2> INFO: Test took 4621ms.
[14:17:35.725] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[14:17:36.054] <TB2> INFO: Expecting 41600 events.
[14:17:40.224] <TB2> INFO: 41600 events read in total (3453ms).
[14:17:40.225] <TB2> INFO: Test took 4500ms.
[14:17:40.227] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[14:17:40.581] <TB2> INFO: Expecting 41600 events.
[14:17:44.827] <TB2> INFO: 41600 events read in total (3530ms).
[14:17:44.827] <TB2> INFO: Test took 4600ms.
[14:17:44.830] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[14:17:45.186] <TB2> INFO: Expecting 41600 events.
[14:17:49.378] <TB2> INFO: 41600 events read in total (3476ms).
[14:17:49.379] <TB2> INFO: Test took 4549ms.
[14:17:49.382] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[14:17:49.733] <TB2> INFO: Expecting 41600 events.
[14:17:54.080] <TB2> INFO: 41600 events read in total (3631ms).
[14:17:54.080] <TB2> INFO: Test took 4698ms.
[14:17:54.083] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[14:17:54.441] <TB2> INFO: Expecting 41600 events.
[14:17:58.596] <TB2> INFO: 41600 events read in total (3438ms).
[14:17:58.597] <TB2> INFO: Test took 4514ms.
[14:17:59.063] <TB2> INFO: PixTestGainPedestal::measure() done
[14:18:31.535] <TB2> INFO: PixTestGainPedestal::fit() done
[14:18:31.535] <TB2> INFO: non-linearity mean: 0.958 0.966 0.955 0.950 0.958 0.958 0.954 0.964 0.956 0.956 0.951 0.960 0.955 0.956 0.961 0.952
[14:18:31.535] <TB2> INFO: non-linearity RMS: 0.007 0.005 0.006 0.005 0.006 0.006 0.006 0.005 0.006 0.006 0.006 0.004 0.006 0.007 0.006 0.006
[14:18:31.535] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//phCalibrationFitErr35_C0.dat
[14:18:31.554] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//phCalibrationFitErr35_C1.dat
[14:18:31.573] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//phCalibrationFitErr35_C2.dat
[14:18:31.592] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//phCalibrationFitErr35_C3.dat
[14:18:31.611] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//phCalibrationFitErr35_C4.dat
[14:18:31.630] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//phCalibrationFitErr35_C5.dat
[14:18:31.649] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//phCalibrationFitErr35_C6.dat
[14:18:31.669] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//phCalibrationFitErr35_C7.dat
[14:18:31.688] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//phCalibrationFitErr35_C8.dat
[14:18:31.708] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//phCalibrationFitErr35_C9.dat
[14:18:31.727] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//phCalibrationFitErr35_C10.dat
[14:18:31.746] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//phCalibrationFitErr35_C11.dat
[14:18:31.765] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//phCalibrationFitErr35_C12.dat
[14:18:31.784] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//phCalibrationFitErr35_C13.dat
[14:18:31.804] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//phCalibrationFitErr35_C14.dat
[14:18:31.823] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//phCalibrationFitErr35_C15.dat
[14:18:31.842] <TB2> INFO: PixTestGainPedestal::doTest() done, duration: 168 seconds
[14:18:31.848] <TB2> INFO: readReadbackCal: /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C0.dat .. /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C15.dat
[14:18:31.849] <TB2> INFO: PixTestReadback::doTest() start.
[14:18:31.850] <TB2> INFO: PixTestReadback::RES sent once
[14:18:43.168] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C0.dat
[14:18:43.168] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C1.dat
[14:18:43.168] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C2.dat
[14:18:43.168] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C3.dat
[14:18:43.168] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C4.dat
[14:18:43.168] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C5.dat
[14:18:43.168] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C6.dat
[14:18:43.169] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C7.dat
[14:18:43.169] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C8.dat
[14:18:43.169] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C9.dat
[14:18:43.169] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C10.dat
[14:18:43.169] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C11.dat
[14:18:43.169] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C12.dat
[14:18:43.169] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C13.dat
[14:18:43.169] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C14.dat
[14:18:43.169] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C15.dat
[14:18:43.201] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:18:43.201] <TB2> INFO: PixTestReadback::RES sent once
[14:18:54.432] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C0.dat
[14:18:54.433] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C1.dat
[14:18:54.433] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C2.dat
[14:18:54.433] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C3.dat
[14:18:54.434] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C4.dat
[14:18:54.434] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C5.dat
[14:18:54.434] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C6.dat
[14:18:54.434] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C7.dat
[14:18:54.435] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C8.dat
[14:18:54.435] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C9.dat
[14:18:54.435] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C10.dat
[14:18:54.435] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C11.dat
[14:18:54.435] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C12.dat
[14:18:54.435] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C13.dat
[14:18:54.435] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C14.dat
[14:18:54.436] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C15.dat
[14:18:54.466] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:18:54.466] <TB2> INFO: PixTestReadback::RES sent once
[14:19:03.098] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:19:03.098] <TB2> INFO: Vbg will be calibrated using Vd calibration
[14:19:03.098] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 162.1calibrated Vbg = 1.19075 :::*/*/*/*/
[14:19:03.098] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 155.9calibrated Vbg = 1.18362 :::*/*/*/*/
[14:19:03.098] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 154.5calibrated Vbg = 1.19148 :::*/*/*/*/
[14:19:03.098] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 152.6calibrated Vbg = 1.19026 :::*/*/*/*/
[14:19:03.098] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 151calibrated Vbg = 1.20486 :::*/*/*/*/
[14:19:03.098] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 156.1calibrated Vbg = 1.20003 :::*/*/*/*/
[14:19:03.098] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 150.1calibrated Vbg = 1.20271 :::*/*/*/*/
[14:19:03.098] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 164calibrated Vbg = 1.20589 :::*/*/*/*/
[14:19:03.098] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 154.2calibrated Vbg = 1.20488 :::*/*/*/*/
[14:19:03.098] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 153.7calibrated Vbg = 1.2013 :::*/*/*/*/
[14:19:03.098] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 147calibrated Vbg = 1.19434 :::*/*/*/*/
[14:19:03.098] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 151.9calibrated Vbg = 1.1984 :::*/*/*/*/
[14:19:03.099] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 158.3calibrated Vbg = 1.20088 :::*/*/*/*/
[14:19:03.099] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 159.9calibrated Vbg = 1.19316 :::*/*/*/*/
[14:19:03.099] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 151.2calibrated Vbg = 1.19161 :::*/*/*/*/
[14:19:03.099] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 147.9calibrated Vbg = 1.18383 :::*/*/*/*/
[14:19:03.103] <TB2> INFO: PixTestReadback::RES sent once
[14:21:57.951] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C0.dat
[14:21:57.951] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C1.dat
[14:21:57.951] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C2.dat
[14:21:57.951] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C3.dat
[14:21:57.951] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C4.dat
[14:21:57.951] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C5.dat
[14:21:57.951] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C6.dat
[14:21:57.951] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C7.dat
[14:21:57.951] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C8.dat
[14:21:57.952] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C9.dat
[14:21:57.952] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C10.dat
[14:21:57.952] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C11.dat
[14:21:57.952] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C12.dat
[14:21:57.952] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C13.dat
[14:21:57.952] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C14.dat
[14:21:57.952] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//002_FulltestPxar_m20//readbackCal_C15.dat
[14:21:57.983] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[14:21:57.985] <TB2> INFO: PixTestReadback::doTest() done
[14:21:57.998] <TB2> INFO: enter test to run
[14:21:57.998] <TB2> INFO: test: exit no parameter change
[14:21:58.624] <TB2> QUIET: Connection to board 156 closed.
[14:21:58.703] <TB2> INFO: pXar: this is the end, my friend