[09:14:57.860] <TB2> INFO: *** Welcome to pxar ***
[09:14:57.860] <TB2> INFO: *** Today: 2015/08/31
[09:14:57.860] <TB2> INFO: readRocDacs: /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C0.dat .. /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C15.dat
[09:14:57.862] <TB2> INFO: readTbmDacs: /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//tbmParameters_C0a.dat .. /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//tbmParameters_C0b.dat
[09:14:57.862] <TB2> INFO: readMaskFile: /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//defaultMaskFile.dat
[09:14:57.862] <TB2> INFO: readTrimFile: /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters_C0.dat .. /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters_C15.dat
[09:14:57.949] <TB2> INFO: clk: 4
[09:14:57.949] <TB2> INFO: ctr: 4
[09:14:57.949] <TB2> INFO: sda: 19
[09:14:57.949] <TB2> INFO: tin: 9
[09:14:57.949] <TB2> INFO: level: 15
[09:14:57.949] <TB2> INFO: triggerdelay: 0
[09:14:57.949] <TB2> QUIET: Instanciating API for pxar v2.5+57~g44d0777
[09:14:57.949] <TB2> INFO: Log level: INFO
[09:14:57.958] <TB2> INFO: Found DTB DTB_WXC55Z
[09:14:57.968] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[09:14:57.971] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.2
SW version: 4.4
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[09:14:57.975] <TB2> INFO: RPC call hashes of host and DTB match: 397073690
[09:14:59.508] <TB2> INFO: DUT info:
[09:14:59.508] <TB2> INFO: The DUT currently contains the following objects:
[09:14:59.508] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:14:59.508] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:14:59.508] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:14:59.508] <TB2> INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[09:14:59.508] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[09:14:59.508] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[09:14:59.508] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[09:14:59.508] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[09:14:59.508] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[09:14:59.508] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[09:14:59.508] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[09:14:59.508] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[09:14:59.508] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[09:14:59.508] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[09:14:59.508] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[09:14:59.508] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[09:14:59.508] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[09:14:59.508] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[09:14:59.508] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[09:14:59.508] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[09:14:59.909] <TB2> INFO: enter 'restricted' command line mode
[09:14:59.909] <TB2> INFO: enter test to run
[09:14:59.910] <TB2> INFO: test: pretest no parameter change
[09:14:59.910] <TB2> INFO: running: pretest
[09:14:59.916] <TB2> INFO: ######################################################################
[09:14:59.916] <TB2> INFO: PixTestPretest::doTest()
[09:14:59.916] <TB2> INFO: ######################################################################
[09:14:59.918] <TB2> INFO: ----------------------------------------------------------------------
[09:14:59.918] <TB2> INFO: PixTestPretest::programROC()
[09:14:59.918] <TB2> INFO: ----------------------------------------------------------------------
[09:15:17.935] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[09:15:17.935] <TB2> INFO: IA differences per ROC: 18.5 18.5 20.1 19.3 20.9 17.7 21.7 20.1 18.5 18.5 21.7 20.9 21.7 19.3 17.7 18.5
[09:15:18.003] <TB2> INFO: ----------------------------------------------------------------------
[09:15:18.003] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[09:15:18.003] <TB2> INFO: ----------------------------------------------------------------------
[09:15:22.480] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 385.1 mA = 24.0688 mA/ROC
[09:15:22.481] <TB2> INFO: ----------------------------------------------------------------------
[09:15:22.481] <TB2> INFO: PixTestPretest::findTiming()
[09:15:22.481] <TB2> INFO: ----------------------------------------------------------------------
[09:15:22.482] <TB2> INFO: PixTestCmd::init()

[09:17:46.438] <TB2> INFO: TBM phases: 160MHz: 3, 400MHz: 6, TBM delays: ROC(0/1):2, header/trailer: 1, token: 0
[09:17:46.438] <TB2> INFO: (success/tries = 100/100), width = 3
[09:17:46.440] <TB2> INFO: ----------------------------------------------------------------------
[09:17:46.440] <TB2> INFO: PixTestPretest::findWorkingPixel()
[09:17:46.440] <TB2> INFO: ----------------------------------------------------------------------
[09:17:46.577] <TB2> INFO: Expecting 231680 events.
[09:17:55.591] <TB2> INFO: 231680 events read in total (8297ms).
[09:17:55.595] <TB2> INFO: Test took 9152ms.
[09:17:55.898] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[09:17:55.944] <TB2> INFO: ----------------------------------------------------------------------
[09:17:55.944] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[09:17:55.944] <TB2> INFO: ----------------------------------------------------------------------
[09:17:56.082] <TB2> INFO: Expecting 231680 events.
[09:18:06.253] <TB2> INFO: 231680 events read in total (9455ms).
[09:18:06.256] <TB2> INFO: Test took 10307ms.
[09:18:06.573] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[09:18:06.573] <TB2> INFO: CalDel: 143 139 146 171 131 149 152 139 139 153 158 142 154 158 131 150
[09:18:06.573] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[09:18:06.577] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C0.dat
[09:18:06.577] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C1.dat
[09:18:06.577] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C2.dat
[09:18:06.577] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C3.dat
[09:18:06.578] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C4.dat
[09:18:06.578] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C5.dat
[09:18:06.578] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C6.dat
[09:18:06.578] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C7.dat
[09:18:06.579] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C8.dat
[09:18:06.579] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C9.dat
[09:18:06.579] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C10.dat
[09:18:06.579] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C11.dat
[09:18:06.580] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C12.dat
[09:18:06.580] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C13.dat
[09:18:06.580] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C14.dat
[09:18:06.580] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters_C15.dat
[09:18:06.580] <TB2> INFO: write tbm parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//tbmParameters_C0a.dat
[09:18:06.581] <TB2> INFO: write tbm parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//tbmParameters_C0b.dat
[09:18:06.581] <TB2> INFO: PixTestPretest::doTest() done, duration: 186 seconds
[09:18:06.648] <TB2> INFO: enter test to run
[09:18:06.648] <TB2> INFO: test: fulltest no parameter change
[09:18:06.648] <TB2> INFO: running: fulltest
[09:18:06.648] <TB2> INFO: ######################################################################
[09:18:06.648] <TB2> INFO: PixTestFullTest::doTest()
[09:18:06.648] <TB2> INFO: ######################################################################
[09:18:06.650] <TB2> INFO: ######################################################################
[09:18:06.650] <TB2> INFO: PixTestAlive::doTest()
[09:18:06.650] <TB2> INFO: ######################################################################
[09:18:06.651] <TB2> INFO: ----------------------------------------------------------------------
[09:18:06.651] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:18:06.651] <TB2> INFO: ----------------------------------------------------------------------
[09:18:06.974] <TB2> INFO: Expecting 41600 events.
[09:18:11.476] <TB2> INFO: 41600 events read in total (3786ms).
[09:18:11.477] <TB2> INFO: Test took 4825ms.
[09:18:11.483] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:18:11.766] <TB2> INFO: PixTestAlive::aliveTest() done
[09:18:11.766] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0
[09:18:11.767] <TB2> INFO: ----------------------------------------------------------------------
[09:18:11.767] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:18:11.767] <TB2> INFO: ----------------------------------------------------------------------
[09:18:12.089] <TB2> INFO: Expecting 41600 events.
[09:18:15.352] <TB2> INFO: 41600 events read in total (2547ms).
[09:18:15.353] <TB2> INFO: Test took 3584ms.
[09:18:15.353] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:18:15.354] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[09:18:15.670] <TB2> INFO: PixTestAlive::maskTest() done
[09:18:15.670] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:18:15.672] <TB2> INFO: ----------------------------------------------------------------------
[09:18:15.672] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:18:15.672] <TB2> INFO: ----------------------------------------------------------------------
[09:18:15.982] <TB2> INFO: Expecting 41600 events.
[09:18:20.426] <TB2> INFO: 41600 events read in total (3728ms).
[09:18:20.426] <TB2> INFO: Test took 4753ms.
[09:18:20.433] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:18:20.718] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[09:18:20.718] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:18:20.718] <TB2> INFO: PixTestAlive::doTest() done, duration: 14 seconds
[09:18:20.729] <TB2> INFO: ######################################################################
[09:18:20.729] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[09:18:20.729] <TB2> INFO: ######################################################################
[09:18:20.732] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 2 (plus default)
[09:18:20.743] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[09:18:20.743] <TB2> INFO: run 1 of 1
[09:18:21.051] <TB2> INFO: Expecting 3120000 events.
[09:18:57.900] <TB2> INFO: 841095 events read in total (36133ms).
[09:19:33.787] <TB2> INFO: 1669315 events read in total (72021ms).
[09:20:07.112] <TB2> INFO: 2509760 events read in total (105346ms).
[09:20:32.691] <TB2> INFO: 3120000 events read in total (130924ms).
[09:20:32.746] <TB2> INFO: Test took 132002ms.
[09:20:32.851] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:20:55.645] <TB2> INFO: PixTestBBMap::doTest() done, duration: 154 seconds
[09:20:55.645] <TB2> INFO: number of dead bumps (per ROC): 6 0 0 0 0 0 0 0 1 0 0 0 0 8 0 3
[09:20:55.645] <TB2> INFO: separation cut (per ROC): 78 76 76 81 84 88 97 95 98 96 86 84 74 78 97 69
[09:20:55.714] <TB2> INFO: ######################################################################
[09:20:55.714] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[09:20:55.714] <TB2> INFO: ######################################################################
[09:20:55.714] <TB2> INFO: ----------------------------------------------------------------------
[09:20:55.714] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[09:20:55.714] <TB2> INFO: ----------------------------------------------------------------------
[09:20:55.714] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 0 .. 149 (-1/-1) hits flags = 16 (plus default)
[09:20:55.723] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[09:20:55.723] <TB2> INFO: run 1 of 1
[09:20:56.025] <TB2> INFO: Expecting 31200000 events.
[09:21:20.291] <TB2> INFO: 947350 events read in total (23550ms).
[09:21:46.201] <TB2> INFO: 1879400 events read in total (49460ms).
[09:22:12.427] <TB2> INFO: 2803350 events read in total (75686ms).
[09:22:38.745] <TB2> INFO: 3727800 events read in total (102004ms).
[09:23:04.992] <TB2> INFO: 4648900 events read in total (128251ms).
[09:23:31.226] <TB2> INFO: 5571800 events read in total (154485ms).
[09:23:57.580] <TB2> INFO: 6491700 events read in total (180839ms).
[09:24:23.950] <TB2> INFO: 7414600 events read in total (207209ms).
[09:24:50.434] <TB2> INFO: 8332200 events read in total (233693ms).
[09:25:17.145] <TB2> INFO: 9253200 events read in total (260404ms).
[09:25:43.886] <TB2> INFO: 10170300 events read in total (287145ms).
[09:26:10.371] <TB2> INFO: 11090950 events read in total (313630ms).
[09:26:36.691] <TB2> INFO: 12008600 events read in total (339950ms).
[09:27:03.663] <TB2> INFO: 12926850 events read in total (366922ms).
[09:27:29.954] <TB2> INFO: 13842750 events read in total (393213ms).
[09:27:56.448] <TB2> INFO: 14757600 events read in total (419707ms).
[09:28:22.675] <TB2> INFO: 15672550 events read in total (445934ms).
[09:28:49.339] <TB2> INFO: 16579450 events read in total (472598ms).
[09:29:15.695] <TB2> INFO: 17487000 events read in total (498954ms).
[09:29:42.256] <TB2> INFO: 18392100 events read in total (525515ms).
[09:30:08.412] <TB2> INFO: 19298300 events read in total (551671ms).
[09:30:34.593] <TB2> INFO: 20202850 events read in total (577852ms).
[09:31:00.819] <TB2> INFO: 21109250 events read in total (604078ms).
[09:31:27.296] <TB2> INFO: 22011800 events read in total (630555ms).
[09:31:53.309] <TB2> INFO: 22915850 events read in total (656568ms).
[09:32:19.561] <TB2> INFO: 23818000 events read in total (682820ms).
[09:32:45.622] <TB2> INFO: 24719950 events read in total (708881ms).
[09:33:12.007] <TB2> INFO: 25621500 events read in total (735266ms).
[09:33:39.030] <TB2> INFO: 26525200 events read in total (762289ms).
[09:34:04.274] <TB2> INFO: 27426650 events read in total (787533ms).
[09:34:27.370] <TB2> INFO: 28331850 events read in total (810629ms).
[09:34:52.382] <TB2> INFO: 29233850 events read in total (835641ms).
[09:35:17.075] <TB2> INFO: 30141750 events read in total (860334ms).
[09:35:40.613] <TB2> INFO: 31062150 events read in total (883872ms).
[09:35:44.886] <TB2> INFO: 31200000 events read in total (888145ms).
[09:35:44.916] <TB2> INFO: Test took 889193ms.
[09:35:45.000] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:35:45.206] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:35:46.752] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:35:48.382] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:35:49.955] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:35:51.372] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:35:52.946] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:35:54.503] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:35:56.021] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:35:57.505] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:35:58.994] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:36:00.458] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:36:01.943] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:36:03.472] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:36:05.003] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:36:06.515] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:36:08.022] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:36:09.518] <TB2> INFO: PixTestScurves::scurves() done
[09:36:09.518] <TB2> INFO: Vcal mean: 85.34 82.66 78.27 78.23 81.17 89.40 89.58 93.11 93.15 90.57 80.63 80.18 80.26 97.22 92.22 84.61
[09:36:09.518] <TB2> INFO: Vcal RMS: 4.94 5.22 4.23 4.63 4.78 5.45 6.10 5.73 5.27 6.49 4.83 4.21 5.02 5.41 5.78 4.70
[09:36:09.518] <TB2> INFO: PixTestScurves::fullTest() done, duration: 913 seconds
[09:36:09.590] <TB2> INFO: ######################################################################
[09:36:09.590] <TB2> INFO: PixTestTrim::doTest()
[09:36:09.590] <TB2> INFO: ######################################################################
[09:36:09.592] <TB2> INFO: ----------------------------------------------------------------------
[09:36:09.592] <TB2> INFO: PixTestTrim::trimTest() ntrig = 20, vcal = 35
[09:36:09.592] <TB2> INFO: ----------------------------------------------------------------------
[09:36:09.672] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[09:36:09.672] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 20 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[09:36:09.681] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[09:36:09.681] <TB2> INFO: run 1 of 1
[09:36:09.988] <TB2> INFO: Expecting 13312000 events.
[09:36:38.957] <TB2> INFO: 1074320 events read in total (28253ms).
[09:37:09.634] <TB2> INFO: 2141280 events read in total (58930ms).
[09:37:40.700] <TB2> INFO: 3207280 events read in total (89996ms).
[09:38:10.737] <TB2> INFO: 4271120 events read in total (120033ms).
[09:38:40.253] <TB2> INFO: 5330200 events read in total (149549ms).
[09:39:10.138] <TB2> INFO: 6385180 events read in total (179434ms).
[09:39:40.025] <TB2> INFO: 7444400 events read in total (209321ms).
[09:40:09.044] <TB2> INFO: 8507860 events read in total (238340ms).
[09:40:40.291] <TB2> INFO: 9572040 events read in total (269587ms).
[09:41:09.626] <TB2> INFO: 10638960 events read in total (298922ms).
[09:41:39.766] <TB2> INFO: 11706580 events read in total (329062ms).
[09:42:09.654] <TB2> INFO: 12773860 events read in total (358950ms).
[09:42:25.439] <TB2> INFO: 13312000 events read in total (374735ms).
[09:42:25.471] <TB2> INFO: Test took 375790ms.
[09:42:25.520] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:42:44.686] <TB2> INFO: ROC 0 VthrComp = 90
[09:42:44.686] <TB2> INFO: ROC 1 VthrComp = 87
[09:42:44.686] <TB2> INFO: ROC 2 VthrComp = 85
[09:42:44.686] <TB2> INFO: ROC 3 VthrComp = 82
[09:42:44.686] <TB2> INFO: ROC 4 VthrComp = 89
[09:42:44.686] <TB2> INFO: ROC 5 VthrComp = 92
[09:42:44.686] <TB2> INFO: ROC 6 VthrComp = 96
[09:42:44.686] <TB2> INFO: ROC 7 VthrComp = 97
[09:42:44.686] <TB2> INFO: ROC 8 VthrComp = 96
[09:42:44.686] <TB2> INFO: ROC 9 VthrComp = 94
[09:42:44.686] <TB2> INFO: ROC 10 VthrComp = 86
[09:42:44.686] <TB2> INFO: ROC 11 VthrComp = 85
[09:42:44.687] <TB2> INFO: ROC 12 VthrComp = 83
[09:42:44.687] <TB2> INFO: ROC 13 VthrComp = 97
[09:42:44.687] <TB2> INFO: ROC 14 VthrComp = 94
[09:42:44.687] <TB2> INFO: ROC 15 VthrComp = 89
[09:42:44.687] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[09:42:44.687] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 20 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[09:42:44.697] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[09:42:44.697] <TB2> INFO: run 1 of 1
[09:42:45.025] <TB2> INFO: Expecting 13312000 events.
[09:43:14.478] <TB2> INFO: 780440 events read in total (28737ms).
[09:43:42.999] <TB2> INFO: 1557020 events read in total (57258ms).
[09:44:11.392] <TB2> INFO: 2332620 events read in total (85651ms).
[09:44:39.918] <TB2> INFO: 3108940 events read in total (114177ms).
[09:45:08.385] <TB2> INFO: 3884440 events read in total (142644ms).
[09:45:37.088] <TB2> INFO: 4661120 events read in total (171347ms).
[09:46:05.327] <TB2> INFO: 5437680 events read in total (199586ms).
[09:46:33.648] <TB2> INFO: 6213460 events read in total (227907ms).
[09:47:01.744] <TB2> INFO: 6986680 events read in total (256003ms).
[09:47:28.681] <TB2> INFO: 7756060 events read in total (282940ms).
[09:47:54.423] <TB2> INFO: 8524080 events read in total (308682ms).
[09:48:19.619] <TB2> INFO: 9291480 events read in total (333878ms).
[09:48:45.889] <TB2> INFO: 10056780 events read in total (360148ms).
[09:49:13.266] <TB2> INFO: 10821420 events read in total (387525ms).
[09:49:39.923] <TB2> INFO: 11586240 events read in total (414182ms).
[09:50:07.416] <TB2> INFO: 12351200 events read in total (441675ms).
[09:50:34.903] <TB2> INFO: 13118140 events read in total (469162ms).
[09:50:42.359] <TB2> INFO: 13312000 events read in total (476618ms).
[09:50:42.403] <TB2> INFO: Test took 477706ms.
[09:50:42.549] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:51:06.270] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 59.2266 for pixel 24/1 mean/min/max = 46.2656/33.1539/59.3772
[09:51:06.270] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 59.8506 for pixel 10/79 mean/min/max = 45.5524/31.0576/60.0472
[09:51:06.271] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 55.8684 for pixel 13/27 mean/min/max = 44.0699/31.865/56.2748
[09:51:06.271] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 57.6367 for pixel 0/5 mean/min/max = 45.2877/32.3192/58.2563
[09:51:06.271] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 58.5937 for pixel 0/76 mean/min/max = 45.2906/31.9594/58.6218
[09:51:06.271] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 57.9241 for pixel 15/76 mean/min/max = 45.2883/32.2825/58.2941
[09:51:06.272] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 59.8493 for pixel 0/79 mean/min/max = 45.8192/31.7041/59.9344
[09:51:06.272] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 58.9615 for pixel 23/10 mean/min/max = 45.19/31.3282/59.0518
[09:51:06.272] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 59.9346 for pixel 47/74 mean/min/max = 45.8076/31.5053/60.1099
[09:51:06.273] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 59.3384 for pixel 27/2 mean/min/max = 45.7684/31.9647/59.5722
[09:51:06.273] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 58.9133 for pixel 0/45 mean/min/max = 45.5311/31.973/59.0892
[09:51:06.273] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 56.2826 for pixel 14/2 mean/min/max = 44.5473/32.4226/56.672
[09:51:06.273] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 59.1048 for pixel 4/77 mean/min/max = 45.3352/31.518/59.1524
[09:51:06.274] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 58.7463 for pixel 2/7 mean/min/max = 45.2107/31.4822/58.9392
[09:51:06.274] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 60.403 for pixel 47/79 mean/min/max = 45.977/31.4417/60.5124
[09:51:06.274] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 57.3701 for pixel 24/0 mean/min/max = 45.3017/33.0712/57.5321
[09:51:06.274] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:51:06.407] <TB2> INFO: Expecting 1029120 events.
[09:51:32.526] <TB2> INFO: 1029120 events read in total (25400ms).
[09:51:32.532] <TB2> INFO: Expecting 1029120 events.
[09:51:57.702] <TB2> INFO: 1029120 events read in total (24635ms).
[09:51:57.712] <TB2> INFO: Expecting 1029120 events.
[09:52:23.603] <TB2> INFO: 1029120 events read in total (25354ms).
[09:52:23.616] <TB2> INFO: Expecting 1029120 events.
[09:52:49.077] <TB2> INFO: 1029120 events read in total (24934ms).
[09:52:49.092] <TB2> INFO: Expecting 1029120 events.
[09:53:14.776] <TB2> INFO: 1029120 events read in total (25157ms).
[09:53:14.792] <TB2> INFO: Expecting 1029120 events.
[09:53:40.306] <TB2> INFO: 1029120 events read in total (24987ms).
[09:53:40.324] <TB2> INFO: Expecting 1029120 events.
[09:54:05.797] <TB2> INFO: 1029120 events read in total (24946ms).
[09:54:05.816] <TB2> INFO: Expecting 1029120 events.
[09:54:31.429] <TB2> INFO: 1029120 events read in total (25085ms).
[09:54:31.451] <TB2> INFO: Expecting 1029120 events.
[09:54:57.378] <TB2> INFO: 1029120 events read in total (25399ms).
[09:54:57.402] <TB2> INFO: Expecting 1029120 events.
[09:55:22.843] <TB2> INFO: 1029120 events read in total (24914ms).
[09:55:22.876] <TB2> INFO: Expecting 1029120 events.
[09:55:48.316] <TB2> INFO: 1029120 events read in total (24913ms).
[09:55:48.343] <TB2> INFO: Expecting 1029120 events.
[09:56:14.131] <TB2> INFO: 1029120 events read in total (25260ms).
[09:56:14.167] <TB2> INFO: Expecting 1029120 events.
[09:56:39.652] <TB2> INFO: 1029120 events read in total (24958ms).
[09:56:39.686] <TB2> INFO: Expecting 1029120 events.
[09:57:05.246] <TB2> INFO: 1029120 events read in total (25032ms).
[09:57:05.280] <TB2> INFO: Expecting 1029120 events.
[09:57:30.775] <TB2> INFO: 1029120 events read in total (24967ms).
[09:57:30.814] <TB2> INFO: Expecting 1029120 events.
[09:57:55.807] <TB2> INFO: 1029120 events read in total (24465ms).
[09:57:55.847] <TB2> INFO: Test took 409573ms.
[09:57:56.920] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 20 dacrange: 0 .. 199 (-1/-1) hits flags = 16 (plus default)
[09:57:56.929] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[09:57:56.929] <TB2> INFO: run 1 of 1
[09:57:57.233] <TB2> INFO: Expecting 16640000 events.
[09:58:24.850] <TB2> INFO: 725380 events read in total (26901ms).
[09:58:51.360] <TB2> INFO: 1447460 events read in total (53411ms).
[09:59:18.621] <TB2> INFO: 2169620 events read in total (80672ms).
[09:59:45.589] <TB2> INFO: 2891720 events read in total (107640ms).
[10:00:12.929] <TB2> INFO: 3613760 events read in total (134980ms).
[10:00:39.893] <TB2> INFO: 4335440 events read in total (161944ms).
[10:01:06.145] <TB2> INFO: 5057480 events read in total (188196ms).
[10:01:32.790] <TB2> INFO: 5780660 events read in total (214841ms).
[10:02:00.109] <TB2> INFO: 6503040 events read in total (242161ms).
[10:02:26.807] <TB2> INFO: 7225140 events read in total (268858ms).
[10:02:54.014] <TB2> INFO: 7947300 events read in total (296065ms).
[10:03:21.245] <TB2> INFO: 8667060 events read in total (323296ms).
[10:03:46.523] <TB2> INFO: 9384680 events read in total (348574ms).
[10:04:11.120] <TB2> INFO: 10101180 events read in total (373171ms).
[10:04:35.060] <TB2> INFO: 10816580 events read in total (397111ms).
[10:05:02.721] <TB2> INFO: 11532060 events read in total (424772ms).
[10:05:26.845] <TB2> INFO: 12246780 events read in total (448896ms).
[10:05:50.063] <TB2> INFO: 12960200 events read in total (472114ms).
[10:06:14.553] <TB2> INFO: 13673700 events read in total (496604ms).
[10:06:39.491] <TB2> INFO: 14386540 events read in total (521542ms).
[10:07:05.876] <TB2> INFO: 15100800 events read in total (547927ms).
[10:07:32.589] <TB2> INFO: 15813860 events read in total (574640ms).
[10:07:59.136] <TB2> INFO: 16529060 events read in total (601187ms).
[10:08:04.004] <TB2> INFO: 16640000 events read in total (606055ms).
[10:08:04.078] <TB2> INFO: Test took 607149ms.
[10:08:04.298] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:08:32.009] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 0.199892 .. 255.000000
[10:08:32.092] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 20 dacrange: 0 .. 255 (-1/-1) hits flags = 16 (plus default)
[10:08:32.101] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[10:08:32.101] <TB2> INFO: run 1 of 1
[10:08:32.418] <TB2> INFO: Expecting 21299200 events.
[10:09:00.458] <TB2> INFO: 711660 events read in total (27323ms).
[10:09:29.030] <TB2> INFO: 1424440 events read in total (55895ms).
[10:09:57.105] <TB2> INFO: 2137020 events read in total (83970ms).
[10:10:23.825] <TB2> INFO: 2849280 events read in total (110690ms).
[10:10:49.582] <TB2> INFO: 3561760 events read in total (136447ms).
[10:11:17.452] <TB2> INFO: 4274000 events read in total (164317ms).
[10:11:45.405] <TB2> INFO: 4986600 events read in total (192270ms).
[10:12:12.954] <TB2> INFO: 5699480 events read in total (219819ms).
[10:12:40.592] <TB2> INFO: 6411780 events read in total (247457ms).
[10:13:08.218] <TB2> INFO: 7124300 events read in total (275083ms).
[10:13:35.753] <TB2> INFO: 7836400 events read in total (302618ms).
[10:14:03.277] <TB2> INFO: 8549240 events read in total (330142ms).
[10:14:30.422] <TB2> INFO: 9261740 events read in total (357287ms).
[10:14:57.004] <TB2> INFO: 9974560 events read in total (383869ms).
[10:15:23.777] <TB2> INFO: 10687200 events read in total (410642ms).
[10:15:49.050] <TB2> INFO: 11399320 events read in total (435915ms).
[10:16:13.224] <TB2> INFO: 12111380 events read in total (460089ms).
[10:16:39.592] <TB2> INFO: 12823720 events read in total (486457ms).
[10:17:06.039] <TB2> INFO: 13535060 events read in total (512904ms).
[10:17:32.868] <TB2> INFO: 14246720 events read in total (539733ms).
[10:17:59.199] <TB2> INFO: 14958540 events read in total (566064ms).
[10:18:25.809] <TB2> INFO: 15670080 events read in total (592674ms).
[10:18:51.036] <TB2> INFO: 16381020 events read in total (617901ms).
[10:19:17.553] <TB2> INFO: 17091700 events read in total (644418ms).
[10:19:42.923] <TB2> INFO: 17802860 events read in total (669788ms).
[10:20:08.823] <TB2> INFO: 18513240 events read in total (695688ms).
[10:20:33.778] <TB2> INFO: 19224080 events read in total (720643ms).
[10:21:01.022] <TB2> INFO: 19934920 events read in total (747887ms).
[10:21:29.090] <TB2> INFO: 20646180 events read in total (775955ms).
[10:21:55.222] <TB2> INFO: 21299200 events read in total (802087ms).
[10:21:55.313] <TB2> INFO: Test took 803212ms.
[10:21:55.572] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:22:22.702] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 16.094407 .. 46.667090
[10:22:22.782] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 20 dacrange: 6 .. 56 (-1/-1) hits flags = 16 (plus default)
[10:22:22.791] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[10:22:22.791] <TB2> INFO: run 1 of 1
[10:22:23.109] <TB2> INFO: Expecting 4243200 events.
[10:22:50.394] <TB2> INFO: 925960 events read in total (26566ms).
[10:23:17.006] <TB2> INFO: 1852240 events read in total (53178ms).
[10:23:45.443] <TB2> INFO: 2776900 events read in total (81616ms).
[10:24:14.285] <TB2> INFO: 3698800 events read in total (110457ms).
[10:24:30.693] <TB2> INFO: 4243200 events read in total (126865ms).
[10:24:30.715] <TB2> INFO: Test took 127925ms.
[10:24:30.754] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:24:44.553] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 3.500000 .. 44.204242
[10:24:44.639] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 20 dacrange: 3 .. 54 (-1/-1) hits flags = 16 (plus default)
[10:24:44.648] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[10:24:44.648] <TB2> INFO: run 1 of 1
[10:24:44.955] <TB2> INFO: Expecting 4326400 events.
[10:25:14.357] <TB2> INFO: 959600 events read in total (28686ms).
[10:25:43.603] <TB2> INFO: 1919420 events read in total (57932ms).
[10:26:12.436] <TB2> INFO: 2878180 events read in total (86766ms).
[10:26:41.415] <TB2> INFO: 3835400 events read in total (115744ms).
[10:26:57.127] <TB2> INFO: 4326400 events read in total (131456ms).
[10:26:57.144] <TB2> INFO: Test took 132496ms.
[10:26:57.179] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:27:11.113] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 6.080658 .. 44.204242
[10:27:11.197] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 20 dacrange: 6 .. 54 (-1/-1) hits flags = 16 (plus default)
[10:27:11.206] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[10:27:11.206] <TB2> INFO: run 1 of 1
[10:27:11.518] <TB2> INFO: Expecting 4076800 events.
[10:27:42.819] <TB2> INFO: 943540 events read in total (30585ms).
[10:28:12.926] <TB2> INFO: 1887260 events read in total (60692ms).
[10:28:39.422] <TB2> INFO: 2830100 events read in total (87189ms).
[10:29:05.775] <TB2> INFO: 3772780 events read in total (113541ms).
[10:29:14.205] <TB2> INFO: 4076800 events read in total (121971ms).
[10:29:14.218] <TB2> INFO: Test took 123012ms.
[10:29:14.249] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:29:27.136] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[10:29:27.136] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 20 dacrange: 15 .. 55 (-1/-1) hits flags = 16 (plus default)
[10:29:27.145] <TB2> INFO: dacScan split into 1 runs with ntrig = 20
[10:29:27.145] <TB2> INFO: run 1 of 1
[10:29:27.457] <TB2> INFO: Expecting 3411200 events.
[10:29:51.779] <TB2> INFO: 879620 events read in total (23606ms).
[10:30:17.803] <TB2> INFO: 1759460 events read in total (49630ms).
[10:30:43.644] <TB2> INFO: 2638940 events read in total (75471ms).
[10:31:06.590] <TB2> INFO: 3411200 events read in total (98417ms).
[10:31:06.605] <TB2> INFO: Test took 99461ms.
[10:31:06.637] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:31:19.034] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C0.dat
[10:31:19.034] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C1.dat
[10:31:19.035] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C2.dat
[10:31:19.035] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C3.dat
[10:31:19.035] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C4.dat
[10:31:19.035] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C5.dat
[10:31:19.035] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C6.dat
[10:31:19.035] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C7.dat
[10:31:19.036] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C8.dat
[10:31:19.036] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C9.dat
[10:31:19.036] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C10.dat
[10:31:19.037] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C11.dat
[10:31:19.037] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C12.dat
[10:31:19.037] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C13.dat
[10:31:19.037] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C14.dat
[10:31:19.038] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C15.dat
[10:31:19.038] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters35_C0.dat
[10:31:19.048] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters35_C1.dat
[10:31:19.055] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters35_C2.dat
[10:31:19.062] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters35_C3.dat
[10:31:19.069] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters35_C4.dat
[10:31:19.075] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters35_C5.dat
[10:31:19.082] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters35_C6.dat
[10:31:19.088] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters35_C7.dat
[10:31:19.095] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters35_C8.dat
[10:31:19.102] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters35_C9.dat
[10:31:19.110] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters35_C10.dat
[10:31:19.117] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters35_C11.dat
[10:31:19.126] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters35_C12.dat
[10:31:19.136] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters35_C13.dat
[10:31:19.143] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters35_C14.dat
[10:31:19.151] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//trimParameters35_C15.dat
[10:31:19.160] <TB2> INFO: PixTestTrim::trimTest() done
[10:31:19.160] <TB2> INFO: vtrim: 98 95 86 88 101 99 96 112 109 103 94 83 94 89 96 80
[10:31:19.160] <TB2> INFO: vthrcomp: 90 87 85 82 89 92 96 97 96 94 86 85 83 97 94 89
[10:31:19.160] <TB2> INFO: vcal mean: 35.06 35.00 35.00 35.03 35.00 35.07 35.02 35.01 35.00 35.00 35.03 35.00 35.01 34.95 35.02 35.05
[10:31:19.160] <TB2> INFO: vcal RMS: 0.72 0.74 0.67 0.66 0.70 0.73 0.79 0.74 0.73 1.41 0.69 0.64 0.73 0.76 0.80 0.68
[10:31:19.160] <TB2> INFO: bits mean: 8.82 9.07 9.78 8.85 8.88 9.33 8.42 9.74 9.45 9.25 8.85 9.31 9.13 9.34 8.90 9.02
[10:31:19.160] <TB2> INFO: bits RMS: 2.79 3.05 2.66 2.96 2.99 2.71 3.21 2.70 2.74 2.81 2.99 2.78 2.94 2.84 3.02 2.78
[10:31:19.168] <TB2> INFO: ----------------------------------------------------------------------
[10:31:19.168] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 10, vtrims = 254 126 63 32
[10:31:19.168] <TB2> INFO: ----------------------------------------------------------------------
[10:31:19.171] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 10 dacrange: 0 .. 199 (-1/-1) hits flags = 16 (plus default)
[10:31:19.183] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:31:19.183] <TB2> INFO: run 1 of 1
[10:31:19.531] <TB2> INFO: Expecting 8320000 events.
[10:31:49.375] <TB2> INFO: 919910 events read in total (29128ms).
[10:32:18.476] <TB2> INFO: 1830110 events read in total (58229ms).
[10:32:47.714] <TB2> INFO: 2738220 events read in total (87467ms).
[10:33:16.728] <TB2> INFO: 3643780 events read in total (116481ms).
[10:33:43.475] <TB2> INFO: 4545110 events read in total (143228ms).
[10:34:10.645] <TB2> INFO: 5441470 events read in total (170398ms).
[10:34:39.543] <TB2> INFO: 6336270 events read in total (199296ms).
[10:35:08.079] <TB2> INFO: 7230980 events read in total (227832ms).
[10:35:34.622] <TB2> INFO: 8128270 events read in total (254375ms).
[10:35:40.602] <TB2> INFO: 8320000 events read in total (260355ms).
[10:35:40.635] <TB2> INFO: Test took 261452ms.
[10:35:40.749] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:36:07.505] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 10 dacrange: 0 .. 164 (-1/-1) hits flags = 16 (plus default)
[10:36:07.513] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:36:07.513] <TB2> INFO: run 1 of 1
[10:36:07.825] <TB2> INFO: Expecting 6864000 events.
[10:36:36.685] <TB2> INFO: 959630 events read in total (28144ms).
[10:37:05.825] <TB2> INFO: 1906940 events read in total (57284ms).
[10:37:32.709] <TB2> INFO: 2851140 events read in total (84168ms).
[10:38:02.219] <TB2> INFO: 3788010 events read in total (113678ms).
[10:38:31.755] <TB2> INFO: 4717810 events read in total (143214ms).
[10:39:01.302] <TB2> INFO: 5645720 events read in total (172761ms).
[10:39:30.825] <TB2> INFO: 6575090 events read in total (202284ms).
[10:39:40.193] <TB2> INFO: 6864000 events read in total (211652ms).
[10:39:40.223] <TB2> INFO: Test took 212709ms.
[10:39:40.307] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:40:05.468] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 10 dacrange: 0 .. 153 (-1/-1) hits flags = 16 (plus default)
[10:40:05.478] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:40:05.478] <TB2> INFO: run 1 of 1
[10:40:05.824] <TB2> INFO: Expecting 6406400 events.
[10:40:36.642] <TB2> INFO: 989910 events read in total (30101ms).
[10:41:03.925] <TB2> INFO: 1966520 events read in total (57384ms).
[10:41:32.188] <TB2> INFO: 2938200 events read in total (85648ms).
[10:42:01.914] <TB2> INFO: 3899230 events read in total (115373ms).
[10:42:31.559] <TB2> INFO: 4855560 events read in total (145018ms).
[10:43:01.200] <TB2> INFO: 5810850 events read in total (174659ms).
[10:43:19.610] <TB2> INFO: 6406400 events read in total (193069ms).
[10:43:19.636] <TB2> INFO: Test took 194158ms.
[10:43:19.703] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:43:45.335] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 10 dacrange: 0 .. 151 (-1/-1) hits flags = 16 (plus default)
[10:43:45.344] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:43:45.344] <TB2> INFO: run 1 of 1
[10:43:45.661] <TB2> INFO: Expecting 6323200 events.
[10:44:16.584] <TB2> INFO: 995650 events read in total (30207ms).
[10:44:44.302] <TB2> INFO: 1978180 events read in total (57925ms).
[10:45:12.390] <TB2> INFO: 2955100 events read in total (86014ms).
[10:45:42.246] <TB2> INFO: 3920740 events read in total (115869ms).
[10:46:12.148] <TB2> INFO: 4881790 events read in total (145771ms).
[10:46:41.808] <TB2> INFO: 5841460 events read in total (175431ms).
[10:46:56.893] <TB2> INFO: 6323200 events read in total (190516ms).
[10:46:56.922] <TB2> INFO: Test took 191577ms.
[10:46:56.987] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:47:18.996] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 10 dacrange: 0 .. 152 (-1/-1) hits flags = 16 (plus default)
[10:47:19.005] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:47:19.005] <TB2> INFO: run 1 of 1
[10:47:19.309] <TB2> INFO: Expecting 6364800 events.
[10:47:50.042] <TB2> INFO: 992150 events read in total (30015ms).
[10:48:20.279] <TB2> INFO: 1970980 events read in total (60252ms).
[10:48:50.210] <TB2> INFO: 2944740 events read in total (90184ms).
[10:49:20.024] <TB2> INFO: 3906920 events read in total (119997ms).
[10:49:49.888] <TB2> INFO: 4864620 events read in total (149861ms).
[10:50:19.464] <TB2> INFO: 5821320 events read in total (179437ms).
[10:50:36.355] <TB2> INFO: 6364800 events read in total (196328ms).
[10:50:36.390] <TB2> INFO: Test took 197385ms.
[10:50:36.462] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:50:58.448] <TB2> INFO: PixTestTrim::trimBitTest() done
[10:50:58.450] <TB2> INFO: PixTestTrim::doTest() done, duration: 4488 seconds
[10:50:59.268] <TB2> INFO: ######################################################################
[10:50:59.268] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[10:50:59.268] <TB2> INFO: ######################################################################
[10:50:59.615] <TB2> INFO: Expecting 41600 events.
[10:51:03.998] <TB2> INFO: 41600 events read in total (3667ms).
[10:51:03.999] <TB2> INFO: Test took 4728ms.
[10:51:04.005] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:51:04.580] <TB2> INFO: Expecting 41600 events.
[10:51:09.072] <TB2> INFO: 41600 events read in total (3776ms).
[10:51:09.072] <TB2> INFO: Test took 4801ms.
[10:51:09.083] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:51:09.432] <TB2> INFO: Expecting 41600 events.
[10:51:13.899] <TB2> INFO: 41600 events read in total (3751ms).
[10:51:13.900] <TB2> INFO: Test took 4806ms.
[10:51:13.908] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:51:13.915] <TB2> INFO: The DUT currently contains the following objects:
[10:51:13.915] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:51:13.915] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:51:13.915] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:51:13.915] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:51:13.915] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:13.915] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:13.915] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:13.915] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:13.915] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:13.915] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:13.915] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:13.915] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:13.915] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:13.915] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:13.915] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:13.915] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:13.915] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:13.915] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:13.915] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:13.915] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:14.251] <TB2> INFO: Expecting 2560 events.
[10:51:15.320] <TB2> INFO: 2560 events read in total (353ms).
[10:51:15.320] <TB2> INFO: Test took 1405ms.
[10:51:15.321] <TB2> INFO: The DUT currently contains the following objects:
[10:51:15.321] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:51:15.321] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:51:15.321] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:51:15.321] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:51:15.321] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:15.321] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:15.321] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:15.321] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:15.321] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:15.321] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:15.322] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:15.322] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:15.322] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:15.322] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:15.322] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:15.322] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:15.322] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:15.322] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:15.322] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:15.322] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:15.735] <TB2> INFO: Expecting 2560 events.
[10:51:16.803] <TB2> INFO: 2560 events read in total (352ms).
[10:51:16.803] <TB2> INFO: Test took 1481ms.
[10:51:16.804] <TB2> INFO: The DUT currently contains the following objects:
[10:51:16.804] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:51:16.804] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:51:16.804] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:51:16.804] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:51:16.804] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:16.804] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:16.804] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:16.804] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:16.804] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:16.804] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:16.804] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:16.804] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:16.804] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:16.804] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:16.804] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:16.804] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:16.804] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:16.804] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:16.804] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:16.804] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:17.218] <TB2> INFO: Expecting 2560 events.
[10:51:18.286] <TB2> INFO: 2560 events read in total (352ms).
[10:51:18.286] <TB2> INFO: Test took 1482ms.
[10:51:18.286] <TB2> INFO: The DUT currently contains the following objects:
[10:51:18.286] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:51:18.287] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:51:18.287] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:51:18.287] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:51:18.287] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:18.287] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:18.287] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:18.287] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:18.287] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:18.287] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:18.287] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:18.287] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:18.287] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:18.287] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:18.287] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:18.287] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:18.287] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:18.287] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:18.287] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:18.287] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:18.701] <TB2> INFO: Expecting 2560 events.
[10:51:19.768] <TB2> INFO: 2560 events read in total (351ms).
[10:51:19.768] <TB2> INFO: Test took 1481ms.
[10:51:19.774] <TB2> INFO: The DUT currently contains the following objects:
[10:51:19.774] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:51:19.774] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:51:19.774] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:51:19.774] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:51:19.774] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:19.774] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:19.774] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:19.774] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:19.774] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:19.774] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:19.774] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:19.774] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:19.774] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:19.774] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:19.774] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:19.775] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:19.775] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:19.775] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:19.775] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:19.775] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:20.183] <TB2> INFO: Expecting 2560 events.
[10:51:21.249] <TB2> INFO: 2560 events read in total (350ms).
[10:51:21.250] <TB2> INFO: Test took 1475ms.
[10:51:21.250] <TB2> INFO: The DUT currently contains the following objects:
[10:51:21.250] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:51:21.250] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:51:21.250] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:51:21.250] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:51:21.250] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:21.250] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:21.251] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:21.251] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:21.251] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:21.251] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:21.251] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:21.251] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:21.251] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:21.251] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:21.251] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:21.251] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:21.251] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:21.251] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:21.251] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:21.251] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:21.665] <TB2> INFO: Expecting 2560 events.
[10:51:22.732] <TB2> INFO: 2560 events read in total (351ms).
[10:51:22.732] <TB2> INFO: Test took 1481ms.
[10:51:22.733] <TB2> INFO: The DUT currently contains the following objects:
[10:51:22.733] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:51:22.733] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:51:22.733] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:51:22.733] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:51:22.733] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:22.733] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:22.733] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:22.733] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:22.733] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:22.733] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:22.733] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:22.733] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:22.733] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:22.734] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:22.734] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:22.734] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:22.734] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:22.734] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:22.734] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:22.734] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:23.147] <TB2> INFO: Expecting 2560 events.
[10:51:24.215] <TB2> INFO: 2560 events read in total (352ms).
[10:51:24.216] <TB2> INFO: Test took 1482ms.
[10:51:24.216] <TB2> INFO: The DUT currently contains the following objects:
[10:51:24.216] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:51:24.216] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:51:24.216] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:51:24.216] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:51:24.216] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:24.216] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:24.216] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:24.217] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:24.217] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:24.217] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:24.217] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:24.217] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:24.217] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:24.217] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:24.217] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:24.217] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:24.217] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:24.217] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:24.217] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:24.217] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:24.630] <TB2> INFO: Expecting 2560 events.
[10:51:25.698] <TB2> INFO: 2560 events read in total (351ms).
[10:51:25.698] <TB2> INFO: Test took 1481ms.
[10:51:25.698] <TB2> INFO: The DUT currently contains the following objects:
[10:51:25.698] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:51:25.698] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:51:25.698] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:51:25.698] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:51:25.698] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:25.698] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:25.698] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:25.698] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:25.699] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:25.699] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:25.699] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:25.699] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:25.699] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:25.699] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:25.699] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:25.699] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:25.699] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:25.699] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:25.699] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:25.699] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:26.112] <TB2> INFO: Expecting 2560 events.
[10:51:27.182] <TB2> INFO: 2560 events read in total (353ms).
[10:51:27.182] <TB2> INFO: Test took 1483ms.
[10:51:27.182] <TB2> INFO: The DUT currently contains the following objects:
[10:51:27.182] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:51:27.182] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:51:27.182] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:51:27.182] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:51:27.183] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:27.183] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:27.183] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:27.183] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:27.183] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:27.183] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:27.183] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:27.183] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:27.183] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:27.183] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:27.183] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:27.183] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:27.183] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:27.183] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:27.183] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:27.183] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:27.597] <TB2> INFO: Expecting 2560 events.
[10:51:28.666] <TB2> INFO: 2560 events read in total (353ms).
[10:51:28.666] <TB2> INFO: Test took 1483ms.
[10:51:28.666] <TB2> INFO: The DUT currently contains the following objects:
[10:51:28.666] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:51:28.666] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:51:28.666] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:51:28.666] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:51:28.666] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:28.667] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:28.667] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:28.667] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:28.667] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:28.667] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:28.667] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:28.667] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:28.667] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:28.667] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:28.667] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:28.667] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:28.667] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:28.667] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:28.667] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:28.667] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:29.080] <TB2> INFO: Expecting 2560 events.
[10:51:30.165] <TB2> INFO: 2560 events read in total (369ms).
[10:51:30.166] <TB2> INFO: Test took 1499ms.
[10:51:30.166] <TB2> INFO: The DUT currently contains the following objects:
[10:51:30.166] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:51:30.166] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:51:30.166] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:51:30.166] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:51:30.166] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:30.166] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:30.166] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:30.167] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:30.167] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:30.167] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:30.167] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:30.167] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:30.167] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:30.167] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:30.167] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:30.167] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:30.167] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:30.167] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:30.167] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:30.167] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:30.580] <TB2> INFO: Expecting 2560 events.
[10:51:31.649] <TB2> INFO: 2560 events read in total (352ms).
[10:51:31.649] <TB2> INFO: Test took 1482ms.
[10:51:31.649] <TB2> INFO: The DUT currently contains the following objects:
[10:51:31.649] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:51:31.649] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:51:31.649] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:51:31.649] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:51:31.650] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:31.650] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:31.650] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:31.650] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:31.650] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:31.650] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:31.650] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:31.650] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:31.650] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:31.650] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:31.650] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:31.650] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:31.650] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:31.650] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:31.650] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:31.650] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:32.064] <TB2> INFO: Expecting 2560 events.
[10:51:33.132] <TB2> INFO: 2560 events read in total (352ms).
[10:51:33.132] <TB2> INFO: Test took 1482ms.
[10:51:33.133] <TB2> INFO: The DUT currently contains the following objects:
[10:51:33.133] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:51:33.133] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:51:33.133] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:51:33.133] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:51:33.133] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:33.133] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:33.133] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:33.133] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:33.133] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:33.133] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:33.133] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:33.133] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:33.133] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:33.133] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:33.133] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:33.133] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:33.133] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:33.133] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:33.133] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:33.133] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:33.548] <TB2> INFO: Expecting 2560 events.
[10:51:34.615] <TB2> INFO: 2560 events read in total (351ms).
[10:51:34.615] <TB2> INFO: Test took 1482ms.
[10:51:34.615] <TB2> INFO: The DUT currently contains the following objects:
[10:51:34.615] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:51:34.615] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:51:34.615] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:51:34.615] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:51:34.615] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:34.615] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:34.615] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:34.615] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:34.615] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:34.615] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:34.615] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:34.615] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:34.615] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:34.615] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:34.615] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:34.616] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:34.616] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:34.616] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:34.616] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:34.616] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:35.029] <TB2> INFO: Expecting 2560 events.
[10:51:36.101] <TB2> INFO: 2560 events read in total (355ms).
[10:51:36.102] <TB2> INFO: Test took 1486ms.
[10:51:36.102] <TB2> INFO: The DUT currently contains the following objects:
[10:51:36.102] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[10:51:36.102] <TB2> INFO: TBM Core alpha (0): 7 registers set
[10:51:36.102] <TB2> INFO: TBM Core beta (1): 7 registers set
[10:51:36.102] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[10:51:36.102] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:36.102] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:36.103] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:36.103] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:36.103] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:36.103] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:36.103] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:36.103] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:36.103] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:36.103] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:36.103] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:36.103] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:36.103] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:36.103] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:36.103] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:36.103] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[10:51:36.517] <TB2> INFO: Expecting 2560 events.
[10:51:37.587] <TB2> INFO: 2560 events read in total (354ms).
[10:51:37.588] <TB2> INFO: Test took 1485ms.
[10:51:37.592] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:51:38.005] <TB2> INFO: Expecting 655360 events.
[10:51:54.434] <TB2> INFO: 655360 events read in total (15713ms).
[10:51:54.445] <TB2> INFO: Expecting 655360 events.
[10:52:10.681] <TB2> INFO: 655360 events read in total (15708ms).
[10:52:10.693] <TB2> INFO: Expecting 655360 events.
[10:52:27.118] <TB2> INFO: 655360 events read in total (15897ms).
[10:52:27.136] <TB2> INFO: Expecting 655360 events.
[10:52:43.476] <TB2> INFO: 655360 events read in total (15813ms).
[10:52:43.500] <TB2> INFO: Expecting 655360 events.
[10:53:00.024] <TB2> INFO: 655360 events read in total (15997ms).
[10:53:00.045] <TB2> INFO: Expecting 655360 events.
[10:53:16.627] <TB2> INFO: 655360 events read in total (16054ms).
[10:53:16.652] <TB2> INFO: Expecting 655360 events.
[10:53:33.107] <TB2> INFO: 655360 events read in total (15928ms).
[10:53:33.135] <TB2> INFO: Expecting 655360 events.
[10:53:49.667] <TB2> INFO: 655360 events read in total (16004ms).
[10:53:49.701] <TB2> INFO: Expecting 655360 events.
[10:54:06.069] <TB2> INFO: 655360 events read in total (15840ms).
[10:54:06.108] <TB2> INFO: Expecting 655360 events.
[10:54:22.360] <TB2> INFO: 655360 events read in total (15725ms).
[10:54:22.402] <TB2> INFO: Expecting 655360 events.
[10:54:38.584] <TB2> INFO: 655360 events read in total (15655ms).
[10:54:38.632] <TB2> INFO: Expecting 655360 events.
[10:54:54.906] <TB2> INFO: 655360 events read in total (15747ms).
[10:54:54.952] <TB2> INFO: Expecting 655360 events.
[10:55:11.514] <TB2> INFO: 655360 events read in total (16035ms).
[10:55:11.565] <TB2> INFO: Expecting 655360 events.
[10:55:27.992] <TB2> INFO: 655360 events read in total (15899ms).
[10:55:28.057] <TB2> INFO: Expecting 655360 events.
[10:55:44.489] <TB2> INFO: 655360 events read in total (15905ms).
[10:55:44.559] <TB2> INFO: Expecting 655360 events.
[10:56:00.981] <TB2> INFO: 655360 events read in total (15894ms).
[10:56:01.048] <TB2> INFO: Test took 263456ms.
[10:56:01.129] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:56:01.439] <TB2> INFO: Expecting 655360 events.
[10:56:18.061] <TB2> INFO: 655360 events read in total (15905ms).
[10:56:18.069] <TB2> INFO: Expecting 655360 events.
[10:56:34.499] <TB2> INFO: 655360 events read in total (15902ms).
[10:56:34.510] <TB2> INFO: Expecting 655360 events.
[10:56:50.730] <TB2> INFO: 655360 events read in total (15692ms).
[10:56:50.745] <TB2> INFO: Expecting 655360 events.
[10:57:07.197] <TB2> INFO: 655360 events read in total (15924ms).
[10:57:07.221] <TB2> INFO: Expecting 655360 events.
[10:57:23.551] <TB2> INFO: 655360 events read in total (15803ms).
[10:57:23.575] <TB2> INFO: Expecting 655360 events.
[10:57:39.652] <TB2> INFO: 655360 events read in total (15549ms).
[10:57:39.677] <TB2> INFO: Expecting 655360 events.
[10:57:54.655] <TB2> INFO: 655360 events read in total (14451ms).
[10:57:54.690] <TB2> INFO: Expecting 655360 events.
[10:58:09.819] <TB2> INFO: 655360 events read in total (14601ms).
[10:58:09.863] <TB2> INFO: Expecting 655360 events.
[10:58:24.714] <TB2> INFO: 655360 events read in total (14324ms).
[10:58:24.754] <TB2> INFO: Expecting 655360 events.
[10:58:41.097] <TB2> INFO: 655360 events read in total (15816ms).
[10:58:41.145] <TB2> INFO: Expecting 655360 events.
[10:58:57.609] <TB2> INFO: 655360 events read in total (15936ms).
[10:58:57.652] <TB2> INFO: Expecting 655360 events.
[10:59:13.994] <TB2> INFO: 655360 events read in total (15814ms).
[10:59:14.056] <TB2> INFO: Expecting 655360 events.
[10:59:30.475] <TB2> INFO: 655360 events read in total (15892ms).
[10:59:30.525] <TB2> INFO: Expecting 655360 events.
[10:59:46.851] <TB2> INFO: 655360 events read in total (15798ms).
[10:59:46.904] <TB2> INFO: Expecting 655360 events.
[11:00:03.249] <TB2> INFO: 655360 events read in total (15817ms).
[11:00:03.307] <TB2> INFO: Expecting 655360 events.
[11:00:19.344] <TB2> INFO: 655360 events read in total (15510ms).
[11:00:19.406] <TB2> INFO: Test took 258277ms.
[11:00:19.592] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:00:19.599] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:00:19.606] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:00:19.613] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:00:19.620] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:00:19.627] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:00:19.634] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:00:19.641] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:00:19.648] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:00:19.655] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:00:19.662] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:00:19.669] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:00:19.676] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:00:19.683] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:00:19.690] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:00:19.697] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:00:19.704] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:00:19.711] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:00:19.750] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C0.dat
[11:00:19.750] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C1.dat
[11:00:19.750] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C2.dat
[11:00:19.750] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C3.dat
[11:00:19.750] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C4.dat
[11:00:19.750] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C5.dat
[11:00:19.750] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C6.dat
[11:00:19.751] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C7.dat
[11:00:19.751] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C8.dat
[11:00:19.751] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C9.dat
[11:00:19.751] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C10.dat
[11:00:19.751] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C11.dat
[11:00:19.751] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C12.dat
[11:00:19.751] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C13.dat
[11:00:19.752] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C14.dat
[11:00:19.752] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//dacParameters35_C15.dat
[11:00:20.077] <TB2> INFO: Expecting 41600 events.
[11:00:24.555] <TB2> INFO: 41600 events read in total (3762ms).
[11:00:24.555] <TB2> INFO: Test took 4800ms.
[11:00:25.088] <TB2> INFO: Expecting 41600 events.
[11:00:29.552] <TB2> INFO: 41600 events read in total (3747ms).
[11:00:29.553] <TB2> INFO: Test took 4769ms.
[11:00:30.113] <TB2> INFO: Expecting 41600 events.
[11:00:34.579] <TB2> INFO: 41600 events read in total (3749ms).
[11:00:34.579] <TB2> INFO: Test took 4800ms.
[11:00:34.804] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:00:34.936] <TB2> INFO: Expecting 2560 events.
[11:00:36.004] <TB2> INFO: 2560 events read in total (352ms).
[11:00:36.005] <TB2> INFO: Test took 1201ms.
[11:00:36.007] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:00:36.420] <TB2> INFO: Expecting 2560 events.
[11:00:37.503] <TB2> INFO: 2560 events read in total (366ms).
[11:00:37.504] <TB2> INFO: Test took 1497ms.
[11:00:37.506] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:00:37.920] <TB2> INFO: Expecting 2560 events.
[11:00:38.989] <TB2> INFO: 2560 events read in total (353ms).
[11:00:38.989] <TB2> INFO: Test took 1483ms.
[11:00:38.991] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:00:39.405] <TB2> INFO: Expecting 2560 events.
[11:00:40.474] <TB2> INFO: 2560 events read in total (352ms).
[11:00:40.474] <TB2> INFO: Test took 1483ms.
[11:00:40.477] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:00:40.890] <TB2> INFO: Expecting 2560 events.
[11:00:41.958] <TB2> INFO: 2560 events read in total (352ms).
[11:00:41.959] <TB2> INFO: Test took 1483ms.
[11:00:41.961] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:00:42.374] <TB2> INFO: Expecting 2560 events.
[11:00:43.442] <TB2> INFO: 2560 events read in total (351ms).
[11:00:43.443] <TB2> INFO: Test took 1482ms.
[11:00:43.445] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:00:43.858] <TB2> INFO: Expecting 2560 events.
[11:00:44.926] <TB2> INFO: 2560 events read in total (351ms).
[11:00:44.927] <TB2> INFO: Test took 1482ms.
[11:00:44.929] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:00:45.343] <TB2> INFO: Expecting 2560 events.
[11:00:46.411] <TB2> INFO: 2560 events read in total (352ms).
[11:00:46.411] <TB2> INFO: Test took 1482ms.
[11:00:46.413] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:00:46.827] <TB2> INFO: Expecting 2560 events.
[11:00:47.897] <TB2> INFO: 2560 events read in total (354ms).
[11:00:47.897] <TB2> INFO: Test took 1484ms.
[11:00:47.899] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:00:48.312] <TB2> INFO: Expecting 2560 events.
[11:00:49.380] <TB2> INFO: 2560 events read in total (351ms).
[11:00:49.380] <TB2> INFO: Test took 1481ms.
[11:00:49.382] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:00:49.796] <TB2> INFO: Expecting 2560 events.
[11:00:50.863] <TB2> INFO: 2560 events read in total (351ms).
[11:00:50.863] <TB2> INFO: Test took 1481ms.
[11:00:50.866] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:00:51.279] <TB2> INFO: Expecting 2560 events.
[11:00:52.347] <TB2> INFO: 2560 events read in total (352ms).
[11:00:52.348] <TB2> INFO: Test took 1483ms.
[11:00:52.350] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:00:52.763] <TB2> INFO: Expecting 2560 events.
[11:00:53.832] <TB2> INFO: 2560 events read in total (352ms).
[11:00:53.832] <TB2> INFO: Test took 1482ms.
[11:00:53.835] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:00:54.248] <TB2> INFO: Expecting 2560 events.
[11:00:55.317] <TB2> INFO: 2560 events read in total (353ms).
[11:00:55.317] <TB2> INFO: Test took 1482ms.
[11:00:55.320] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:00:55.733] <TB2> INFO: Expecting 2560 events.
[11:00:56.801] <TB2> INFO: 2560 events read in total (352ms).
[11:00:56.801] <TB2> INFO: Test took 1481ms.
[11:00:56.806] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:00:57.217] <TB2> INFO: Expecting 2560 events.
[11:00:58.288] <TB2> INFO: 2560 events read in total (355ms).
[11:00:58.288] <TB2> INFO: Test took 1482ms.
[11:00:58.291] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:00:58.704] <TB2> INFO: Expecting 2560 events.
[11:00:59.774] <TB2> INFO: 2560 events read in total (354ms).
[11:00:59.775] <TB2> INFO: Test took 1484ms.
[11:00:59.777] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:01:00.191] <TB2> INFO: Expecting 2560 events.
[11:01:01.260] <TB2> INFO: 2560 events read in total (353ms).
[11:01:01.260] <TB2> INFO: Test took 1483ms.
[11:01:01.263] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:01:01.678] <TB2> INFO: Expecting 2560 events.
[11:01:02.748] <TB2> INFO: 2560 events read in total (354ms).
[11:01:02.749] <TB2> INFO: Test took 1486ms.
[11:01:02.752] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:01:03.164] <TB2> INFO: Expecting 2560 events.
[11:01:04.233] <TB2> INFO: 2560 events read in total (353ms).
[11:01:04.233] <TB2> INFO: Test took 1482ms.
[11:01:04.236] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:01:04.650] <TB2> INFO: Expecting 2560 events.
[11:01:05.721] <TB2> INFO: 2560 events read in total (355ms).
[11:01:05.722] <TB2> INFO: Test took 1486ms.
[11:01:05.725] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:01:06.138] <TB2> INFO: Expecting 2560 events.
[11:01:07.210] <TB2> INFO: 2560 events read in total (356ms).
[11:01:07.210] <TB2> INFO: Test took 1485ms.
[11:01:07.213] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:01:07.626] <TB2> INFO: Expecting 2560 events.
[11:01:08.696] <TB2> INFO: 2560 events read in total (354ms).
[11:01:08.696] <TB2> INFO: Test took 1484ms.
[11:01:08.699] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:01:09.112] <TB2> INFO: Expecting 2560 events.
[11:01:10.183] <TB2> INFO: 2560 events read in total (354ms).
[11:01:10.184] <TB2> INFO: Test took 1485ms.
[11:01:10.186] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:01:10.599] <TB2> INFO: Expecting 2560 events.
[11:01:11.667] <TB2> INFO: 2560 events read in total (351ms).
[11:01:11.668] <TB2> INFO: Test took 1482ms.
[11:01:11.670] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:01:12.084] <TB2> INFO: Expecting 2560 events.
[11:01:13.152] <TB2> INFO: 2560 events read in total (352ms).
[11:01:13.152] <TB2> INFO: Test took 1482ms.
[11:01:13.154] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:01:13.568] <TB2> INFO: Expecting 2560 events.
[11:01:14.636] <TB2> INFO: 2560 events read in total (351ms).
[11:01:14.637] <TB2> INFO: Test took 1483ms.
[11:01:14.639] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:01:15.053] <TB2> INFO: Expecting 2560 events.
[11:01:16.123] <TB2> INFO: 2560 events read in total (354ms).
[11:01:16.123] <TB2> INFO: Test took 1484ms.
[11:01:16.127] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:01:16.539] <TB2> INFO: Expecting 2560 events.
[11:01:17.609] <TB2> INFO: 2560 events read in total (354ms).
[11:01:17.609] <TB2> INFO: Test took 1482ms.
[11:01:17.611] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:01:18.025] <TB2> INFO: Expecting 2560 events.
[11:01:19.093] <TB2> INFO: 2560 events read in total (352ms).
[11:01:19.093] <TB2> INFO: Test took 1482ms.
[11:01:19.098] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:01:19.509] <TB2> INFO: Expecting 2560 events.
[11:01:20.578] <TB2> INFO: 2560 events read in total (352ms).
[11:01:20.578] <TB2> INFO: Test took 1480ms.
[11:01:20.581] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:01:20.994] <TB2> INFO: Expecting 2560 events.
[11:01:22.063] <TB2> INFO: 2560 events read in total (352ms).
[11:01:22.063] <TB2> INFO: Test took 1482ms.
[11:01:22.681] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 623 seconds
[11:01:22.681] <TB2> INFO: PH scale (per ROC): 80 79 91 80 83 77 84 78 79 82 86 80 74 76 73 87
[11:01:22.681] <TB2> INFO: PH offset (per ROC): 153 159 163 155 158 159 180 169 158 158 148 147 165 165 179 149
[11:01:22.873] <TB2> INFO: ######################################################################
[11:01:22.873] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[11:01:22.873] <TB2> INFO: ######################################################################
[11:01:22.883] <TB2> INFO: scanning low vcal = 10
[11:01:23.193] <TB2> INFO: Expecting 41600 events.
[11:01:26.800] <TB2> INFO: 41600 events read in total (2890ms).
[11:01:26.800] <TB2> INFO: Test took 3917ms.
[11:01:26.804] <TB2> INFO: scanning low vcal = 20
[11:01:27.215] <TB2> INFO: Expecting 41600 events.
[11:01:30.833] <TB2> INFO: 41600 events read in total (2902ms).
[11:01:30.833] <TB2> INFO: Test took 4029ms.
[11:01:30.835] <TB2> INFO: scanning low vcal = 30
[11:01:31.249] <TB2> INFO: Expecting 41600 events.
[11:01:34.896] <TB2> INFO: 41600 events read in total (2931ms).
[11:01:34.897] <TB2> INFO: Test took 4062ms.
[11:01:34.899] <TB2> INFO: scanning low vcal = 40
[11:01:35.306] <TB2> INFO: Expecting 41600 events.
[11:01:39.477] <TB2> INFO: 41600 events read in total (3456ms).
[11:01:39.479] <TB2> INFO: Test took 4580ms.
[11:01:39.482] <TB2> INFO: scanning low vcal = 50
[11:01:39.833] <TB2> INFO: Expecting 41600 events.
[11:01:44.066] <TB2> INFO: 41600 events read in total (3517ms).
[11:01:44.067] <TB2> INFO: Test took 4585ms.
[11:01:44.070] <TB2> INFO: scanning low vcal = 60
[11:01:44.426] <TB2> INFO: Expecting 41600 events.
[11:01:48.639] <TB2> INFO: 41600 events read in total (3496ms).
[11:01:48.639] <TB2> INFO: Test took 4569ms.
[11:01:48.641] <TB2> INFO: scanning low vcal = 70
[11:01:48.997] <TB2> INFO: Expecting 41600 events.
[11:01:53.159] <TB2> INFO: 41600 events read in total (3446ms).
[11:01:53.159] <TB2> INFO: Test took 4517ms.
[11:01:53.162] <TB2> INFO: scanning low vcal = 80
[11:01:53.519] <TB2> INFO: Expecting 41600 events.
[11:01:57.549] <TB2> INFO: 41600 events read in total (3313ms).
[11:01:57.549] <TB2> INFO: Test took 4387ms.
[11:01:57.552] <TB2> INFO: scanning low vcal = 90
[11:01:57.912] <TB2> INFO: Expecting 41600 events.
[11:02:02.061] <TB2> INFO: 41600 events read in total (3433ms).
[11:02:02.062] <TB2> INFO: Test took 4510ms.
[11:02:02.065] <TB2> INFO: scanning low vcal = 100
[11:02:02.425] <TB2> INFO: Expecting 41600 events.
[11:02:06.437] <TB2> INFO: 41600 events read in total (3296ms).
[11:02:06.438] <TB2> INFO: Test took 4373ms.
[11:02:06.441] <TB2> INFO: scanning low vcal = 110
[11:02:06.801] <TB2> INFO: Expecting 41600 events.
[11:02:10.811] <TB2> INFO: 41600 events read in total (3293ms).
[11:02:10.812] <TB2> INFO: Test took 4371ms.
[11:02:10.815] <TB2> INFO: scanning low vcal = 120
[11:02:11.174] <TB2> INFO: Expecting 41600 events.
[11:02:15.189] <TB2> INFO: 41600 events read in total (3298ms).
[11:02:15.189] <TB2> INFO: Test took 4374ms.
[11:02:15.192] <TB2> INFO: scanning low vcal = 130
[11:02:15.552] <TB2> INFO: Expecting 41600 events.
[11:02:19.575] <TB2> INFO: 41600 events read in total (3306ms).
[11:02:19.576] <TB2> INFO: Test took 4384ms.
[11:02:19.578] <TB2> INFO: scanning low vcal = 140
[11:02:19.939] <TB2> INFO: Expecting 41600 events.
[11:02:23.967] <TB2> INFO: 41600 events read in total (3312ms).
[11:02:23.968] <TB2> INFO: Test took 4390ms.
[11:02:23.971] <TB2> INFO: scanning low vcal = 150
[11:02:24.330] <TB2> INFO: Expecting 41600 events.
[11:02:28.354] <TB2> INFO: 41600 events read in total (3308ms).
[11:02:28.355] <TB2> INFO: Test took 4384ms.
[11:02:28.358] <TB2> INFO: scanning low vcal = 160
[11:02:28.717] <TB2> INFO: Expecting 41600 events.
[11:02:32.756] <TB2> INFO: 41600 events read in total (3323ms).
[11:02:32.756] <TB2> INFO: Test took 4398ms.
[11:02:32.759] <TB2> INFO: scanning low vcal = 170
[11:02:33.119] <TB2> INFO: Expecting 41600 events.
[11:02:37.145] <TB2> INFO: 41600 events read in total (3310ms).
[11:02:37.145] <TB2> INFO: Test took 4386ms.
[11:02:37.149] <TB2> INFO: scanning low vcal = 180
[11:02:37.508] <TB2> INFO: Expecting 41600 events.
[11:02:41.517] <TB2> INFO: 41600 events read in total (3292ms).
[11:02:41.518] <TB2> INFO: Test took 4369ms.
[11:02:41.520] <TB2> INFO: scanning low vcal = 190
[11:02:41.881] <TB2> INFO: Expecting 41600 events.
[11:02:45.888] <TB2> INFO: 41600 events read in total (3290ms).
[11:02:45.889] <TB2> INFO: Test took 4368ms.
[11:02:45.892] <TB2> INFO: scanning low vcal = 200
[11:02:46.252] <TB2> INFO: Expecting 41600 events.
[11:02:50.308] <TB2> INFO: 41600 events read in total (3339ms).
[11:02:50.309] <TB2> INFO: Test took 4417ms.
[11:02:50.312] <TB2> INFO: scanning low vcal = 210
[11:02:50.671] <TB2> INFO: Expecting 41600 events.
[11:02:54.697] <TB2> INFO: 41600 events read in total (3309ms).
[11:02:54.697] <TB2> INFO: Test took 4385ms.
[11:02:54.700] <TB2> INFO: scanning low vcal = 220
[11:02:55.060] <TB2> INFO: Expecting 41600 events.
[11:02:59.069] <TB2> INFO: 41600 events read in total (3293ms).
[11:02:59.069] <TB2> INFO: Test took 4369ms.
[11:02:59.072] <TB2> INFO: scanning low vcal = 230
[11:02:59.432] <TB2> INFO: Expecting 41600 events.
[11:03:03.440] <TB2> INFO: 41600 events read in total (3292ms).
[11:03:03.441] <TB2> INFO: Test took 4369ms.
[11:03:03.443] <TB2> INFO: scanning low vcal = 240
[11:03:03.802] <TB2> INFO: Expecting 41600 events.
[11:03:07.810] <TB2> INFO: 41600 events read in total (3291ms).
[11:03:07.810] <TB2> INFO: Test took 4366ms.
[11:03:07.813] <TB2> INFO: scanning low vcal = 250
[11:03:08.172] <TB2> INFO: Expecting 41600 events.
[11:03:12.182] <TB2> INFO: 41600 events read in total (3293ms).
[11:03:12.182] <TB2> INFO: Test took 4369ms.
[11:03:12.186] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[11:03:12.545] <TB2> INFO: Expecting 41600 events.
[11:03:16.568] <TB2> INFO: 41600 events read in total (3306ms).
[11:03:16.568] <TB2> INFO: Test took 4382ms.
[11:03:16.571] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[11:03:16.932] <TB2> INFO: Expecting 41600 events.
[11:03:20.941] <TB2> INFO: 41600 events read in total (3293ms).
[11:03:20.942] <TB2> INFO: Test took 4371ms.
[11:03:20.945] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[11:03:21.304] <TB2> INFO: Expecting 41600 events.
[11:03:25.318] <TB2> INFO: 41600 events read in total (3298ms).
[11:03:25.318] <TB2> INFO: Test took 4373ms.
[11:03:25.321] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[11:03:25.679] <TB2> INFO: Expecting 41600 events.
[11:03:29.828] <TB2> INFO: 41600 events read in total (3433ms).
[11:03:29.829] <TB2> INFO: Test took 4508ms.
[11:03:29.831] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[11:03:30.191] <TB2> INFO: Expecting 41600 events.
[11:03:34.200] <TB2> INFO: 41600 events read in total (3293ms).
[11:03:34.201] <TB2> INFO: Test took 4370ms.
[11:03:34.626] <TB2> INFO: PixTestGainPedestal::measure() done
[11:04:05.409] <TB2> INFO: PixTestGainPedestal::fit() done
[11:04:05.409] <TB2> INFO: non-linearity mean: 0.958 0.963 0.955 0.949 0.956 0.956 0.954 0.962 0.957 0.956 0.951 0.960 0.956 0.955 0.955 0.953
[11:04:05.409] <TB2> INFO: non-linearity RMS: 0.007 0.004 0.006 0.005 0.007 0.006 0.006 0.006 0.006 0.006 0.006 0.004 0.006 0.006 0.007 0.005
[11:04:05.409] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//phCalibrationFitErr35_C0.dat
[11:04:05.427] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//phCalibrationFitErr35_C1.dat
[11:04:05.444] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//phCalibrationFitErr35_C2.dat
[11:04:05.462] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//phCalibrationFitErr35_C3.dat
[11:04:05.480] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//phCalibrationFitErr35_C4.dat
[11:04:05.498] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//phCalibrationFitErr35_C5.dat
[11:04:05.515] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//phCalibrationFitErr35_C6.dat
[11:04:05.533] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//phCalibrationFitErr35_C7.dat
[11:04:05.550] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//phCalibrationFitErr35_C8.dat
[11:04:05.568] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//phCalibrationFitErr35_C9.dat
[11:04:05.586] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//phCalibrationFitErr35_C10.dat
[11:04:05.603] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//phCalibrationFitErr35_C11.dat
[11:04:05.621] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//phCalibrationFitErr35_C12.dat
[11:04:05.638] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//phCalibrationFitErr35_C13.dat
[11:04:05.656] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//phCalibrationFitErr35_C14.dat
[11:04:05.674] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//phCalibrationFitErr35_C15.dat
[11:04:05.691] <TB2> INFO: PixTestGainPedestal::doTest() done, duration: 162 seconds
[11:04:05.697] <TB2> INFO: readReadbackCal: /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C0.dat .. /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C15.dat
[11:04:05.698] <TB2> INFO: PixTestReadback::doTest() start.
[11:04:05.699] <TB2> INFO: PixTestReadback::RES sent once
[11:04:16.931] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C0.dat
[11:04:16.931] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C1.dat
[11:04:16.931] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C2.dat
[11:04:16.931] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C3.dat
[11:04:16.931] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C4.dat
[11:04:16.932] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C5.dat
[11:04:16.932] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C6.dat
[11:04:16.932] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C7.dat
[11:04:16.932] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C8.dat
[11:04:16.932] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C9.dat
[11:04:16.932] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C10.dat
[11:04:16.932] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C11.dat
[11:04:16.932] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C12.dat
[11:04:16.932] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C13.dat
[11:04:16.932] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C14.dat
[11:04:16.933] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C15.dat
[11:04:16.961] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:04:16.961] <TB2> INFO: PixTestReadback::RES sent once
[11:04:28.164] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C0.dat
[11:04:28.164] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C1.dat
[11:04:28.164] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C2.dat
[11:04:28.164] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C3.dat
[11:04:28.164] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C4.dat
[11:04:28.164] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C5.dat
[11:04:28.164] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C6.dat
[11:04:28.164] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C7.dat
[11:04:28.165] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C8.dat
[11:04:28.165] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C9.dat
[11:04:28.165] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C10.dat
[11:04:28.165] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C11.dat
[11:04:28.165] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C12.dat
[11:04:28.165] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C13.dat
[11:04:28.165] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C14.dat
[11:04:28.165] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C15.dat
[11:04:28.193] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:04:28.194] <TB2> INFO: PixTestReadback::RES sent once
[11:04:36.812] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:04:36.812] <TB2> INFO: Vbg will be calibrated using Vd calibration
[11:04:36.812] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 162calibrated Vbg = 1.18772 :::*/*/*/*/
[11:04:36.812] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 155.9calibrated Vbg = 1.184 :::*/*/*/*/
[11:04:36.812] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 154.6calibrated Vbg = 1.19263 :::*/*/*/*/
[11:04:36.812] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 152.4calibrated Vbg = 1.19339 :::*/*/*/*/
[11:04:36.812] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 150.3calibrated Vbg = 1.20361 :::*/*/*/*/
[11:04:36.812] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 156.6calibrated Vbg = 1.20798 :::*/*/*/*/
[11:04:36.812] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 150.2calibrated Vbg = 1.20081 :::*/*/*/*/
[11:04:36.812] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 164calibrated Vbg = 1.20681 :::*/*/*/*/
[11:04:36.812] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 154calibrated Vbg = 1.20289 :::*/*/*/*/
[11:04:36.812] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 153.9calibrated Vbg = 1.20665 :::*/*/*/*/
[11:04:36.812] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 147.4calibrated Vbg = 1.19637 :::*/*/*/*/
[11:04:36.812] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 151.5calibrated Vbg = 1.19885 :::*/*/*/*/
[11:04:36.812] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 157.8calibrated Vbg = 1.19853 :::*/*/*/*/
[11:04:36.812] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 160calibrated Vbg = 1.1959 :::*/*/*/*/
[11:04:36.813] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 151.4calibrated Vbg = 1.19398 :::*/*/*/*/
[11:04:36.813] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 148calibrated Vbg = 1.18677 :::*/*/*/*/
[11:04:36.815] <TB2> INFO: PixTestReadback::RES sent once
[11:07:31.306] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C0.dat
[11:07:31.306] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C1.dat
[11:07:31.306] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C2.dat
[11:07:31.306] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C3.dat
[11:07:31.306] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C4.dat
[11:07:31.306] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C5.dat
[11:07:31.306] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C6.dat
[11:07:31.306] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C7.dat
[11:07:31.306] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C8.dat
[11:07:31.306] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C9.dat
[11:07:31.306] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C10.dat
[11:07:31.307] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C11.dat
[11:07:31.307] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C12.dat
[11:07:31.307] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C13.dat
[11:07:31.307] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C14.dat
[11:07:31.307] <TB2> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2094_FullQualification_2015-08-31_11h07m_1441012069//000_FulltestPxar_m20//readbackCal_C15.dat
[11:07:31.334] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:07:31.334] <TB2> INFO: PixTestReadback::doTest() done
[11:07:31.346] <TB2> INFO: enter test to run
[11:07:31.346] <TB2> INFO: test: exit no parameter change
[11:07:31.918] <TB2> QUIET: Connection to board 156 closed.
[11:07:31.997] <TB2> INFO: pXar: this is the end, my friend