[12:28:07.549] <TB3> INFO: *** Welcome to pxar ***
[12:28:07.549] <TB3> INFO: *** Today: 2015/08/13
[12:28:07.549] <TB3> INFO: readRocDacs: /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C0.dat .. /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C15.dat
[12:28:07.550] <TB3> INFO: readTbmDacs: /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//tbmParameters_C0a.dat .. /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//tbmParameters_C0b.dat
[12:28:07.550] <TB3> INFO: readMaskFile: /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//defaultMaskFile.dat
[12:28:07.550] <TB3> INFO: readTrimFile: /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters_C0.dat .. /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters_C15.dat
[12:28:07.623] <TB3> INFO: clk: 4
[12:28:07.623] <TB3> INFO: ctr: 4
[12:28:07.623] <TB3> INFO: sda: 19
[12:28:07.623] <TB3> INFO: tin: 9
[12:28:07.623] <TB3> INFO: level: 15
[12:28:07.623] <TB3> INFO: triggerdelay: 0
[12:28:07.623] <TB3> QUIET: Instanciating API for pxar v2.2.5+88~g694c14c
[12:28:07.623] <TB3> INFO: Log level: INFO
[12:28:07.630] <TB3> INFO: Found DTB DTB_WZ4I6J
[12:28:07.641] <TB3> QUIET: Connection to board DTB_WZ4I6J opened.
[12:28:07.644] <TB3> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 170
HW version: DTB1.2
FW version: 4.0
SW version: 4.0
USB id: DTB_WZ4I6J
MAC address: 40D8551180AA
Hostname: pixelDTB170
Comment:
------------------------------------------------------
[12:28:07.647] <TB3> INFO: RPC call hashes of host and DTB match: 447413373
[12:28:09.187] <TB3> INFO: DUT info:
[12:28:09.187] <TB3> INFO: The DUT currently contains the following objects:
[12:28:09.187] <TB3> INFO: 2 TBM Cores tbm09c (2 ON)
[12:28:09.187] <TB3> INFO: TBM Core alpha (0): 7 registers set
[12:28:09.187] <TB3> INFO: TBM Core beta (1): 7 registers set
[12:28:09.187] <TB3> INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[12:28:09.187] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:28:09.187] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:28:09.187] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:28:09.187] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:28:09.187] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:28:09.187] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:28:09.187] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:28:09.187] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:28:09.187] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:28:09.187] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:28:09.187] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:28:09.188] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:28:09.188] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:28:09.188] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:28:09.194] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:28:09.194] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:28:09.595] <TB3> INFO: enter 'restricted' command line mode
[12:28:09.595] <TB3> INFO: enter test to run
[12:28:09.595] <TB3> INFO: test: pretest no parameter change
[12:28:09.595] <TB3> INFO: running: pretest
[12:28:09.602] <TB3> INFO: ######################################################################
[12:28:09.602] <TB3> INFO: PixTestPretest::doTest()
[12:28:09.602] <TB3> INFO: ######################################################################
[12:28:09.603] <TB3> INFO: ----------------------------------------------------------------------
[12:28:09.603] <TB3> INFO: PixTestPretest::programROC()
[12:28:09.603] <TB3> INFO: ----------------------------------------------------------------------
[12:28:27.621] <TB3> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:28:27.621] <TB3> INFO: IA differences per ROC: 17.7 16.1 19.3 16.9 16.9 18.5 19.3 19.3 17.7 17.7 17.7 19.3 19.3 17.7 17.7 18.5
[12:28:27.689] <TB3> INFO: ----------------------------------------------------------------------
[12:28:27.689] <TB3> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:28:27.689] <TB3> INFO: ----------------------------------------------------------------------
[12:28:47.270] <TB3> INFO: PixTestPretest::setVana() done, Module Ia 381 mA = 23.8125 mA/ROC
[12:28:47.273] <TB3> INFO: ----------------------------------------------------------------------
[12:28:47.273] <TB3> INFO: PixTestPretest::findWorkingPixel()
[12:28:47.273] <TB3> INFO: ----------------------------------------------------------------------
[12:28:55.537] <TB3> INFO: Test took 8258ms.
[12:28:55.842] <TB3> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:28:55.885] <TB3> INFO: ----------------------------------------------------------------------
[12:28:55.885] <TB3> INFO: PixTestPretest::setVthrCompCalDel()
[12:28:55.885] <TB3> INFO: ----------------------------------------------------------------------
[12:29:04.200] <TB3> INFO: Test took 8306ms.
[12:29:04.520] <TB3> INFO: PixTestPretest::setVthrCompCalDel() done
[12:29:04.520] <TB3> INFO: CalDel: 120 115 112 128 112 128 143 113 142 139 142 130 123 121 137 133
[12:29:04.520] <TB3> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[12:29:04.524] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C0.dat
[12:29:04.525] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C1.dat
[12:29:04.525] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C2.dat
[12:29:04.525] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C3.dat
[12:29:04.526] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C4.dat
[12:29:04.526] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C5.dat
[12:29:04.526] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C6.dat
[12:29:04.526] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C7.dat
[12:29:04.527] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C8.dat
[12:29:04.527] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C9.dat
[12:29:04.527] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C10.dat
[12:29:04.527] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C11.dat
[12:29:04.528] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C12.dat
[12:29:04.528] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C13.dat
[12:29:04.528] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C14.dat
[12:29:04.528] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters_C15.dat
[12:29:04.529] <TB3> INFO: PixTestPretest::doTest() done, duration: 54 seconds
[12:29:04.632] <TB3> INFO: enter test to run
[12:29:04.632] <TB3> INFO: test: fulltest no parameter change
[12:29:04.632] <TB3> INFO: running: fulltest
[12:29:04.632] <TB3> INFO: ######################################################################
[12:29:04.632] <TB3> INFO: PixTestFullTest::doTest()
[12:29:04.632] <TB3> INFO: ######################################################################
[12:29:04.633] <TB3> INFO: ######################################################################
[12:29:04.633] <TB3> INFO: PixTestAlive::doTest()
[12:29:04.633] <TB3> INFO: ######################################################################
[12:29:04.635] <TB3> INFO: ----------------------------------------------------------------------
[12:29:04.635] <TB3> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:29:04.635] <TB3> INFO: ----------------------------------------------------------------------
[12:29:08.097] <TB3> INFO: Test took 3460ms.
[12:29:08.123] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:29:08.355] <TB3> INFO: PixTestAlive::aliveTest() done
[12:29:08.356] <TB3> INFO: number of dead pixels (per ROC): 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0
[12:29:08.357] <TB3> INFO: ----------------------------------------------------------------------
[12:29:08.357] <TB3> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:29:08.357] <TB3> INFO: ----------------------------------------------------------------------
[12:29:11.140] <TB3> INFO: Test took 2781ms.
[12:29:11.144] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:29:11.144] <TB3> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:29:11.375] <TB3> INFO: PixTestAlive::maskTest() done
[12:29:11.375] <TB3> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:29:11.377] <TB3> INFO: ----------------------------------------------------------------------
[12:29:11.377] <TB3> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:29:11.377] <TB3> INFO: ----------------------------------------------------------------------
[12:29:14.864] <TB3> INFO: Test took 3485ms.
[12:29:14.882] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:29:15.115] <TB3> INFO: PixTestAlive::addressDecodingTest() done
[12:29:15.115] <TB3> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:29:15.115] <TB3> INFO: PixTestAlive::doTest() done, duration: 10 seconds
[12:29:15.129] <TB3> INFO: ######################################################################
[12:29:15.129] <TB3> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:29:15.129] <TB3> INFO: ######################################################################
[12:29:15.133] <TB3> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (30) hits flags = 2 (plus default)
[12:29:15.148] <TB3> INFO: dacScan step from 0 .. 29
[12:29:36.647] <TB3> INFO: Test took 21499ms.
[12:29:36.682] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:29:36.684] <TB3> INFO: dacScan step from 30 .. 59
[12:29:58.655] <TB3> INFO: Test took 21971ms.
[12:29:58.703] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:29:58.719] <TB3> INFO: dacScan step from 60 .. 89
[12:30:26.859] <TB3> INFO: Test took 28139ms.
[12:30:27.159] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:30:27.219] <TB3> INFO: dacScan step from 90 .. 119
[12:30:55.135] <TB3> INFO: Test took 27916ms.
[12:30:55.498] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:30:55.587] <TB3> INFO: dacScan step from 120 .. 149
[12:31:20.985] <TB3> INFO: Test took 25398ms.
[12:31:21.230] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:31:45.164] <TB3> INFO: PixTestBBMap::doTest() done, duration: 150 seconds
[12:31:45.164] <TB3> INFO: number of dead bumps (per ROC): 7 0 0 0 0 0 0 1 0 0 0 0 0 0 2 10
[12:31:45.164] <TB3> INFO: separation cut (per ROC): 93 89 99 93 93 92 88 113 85 91 99 88 98 95 91 78
[12:31:45.245] <TB3> INFO: ######################################################################
[12:31:45.245] <TB3> INFO: PixTestScurves::fullTest() ntrig = 50
[12:31:45.245] <TB3> INFO: ######################################################################
[12:31:45.245] <TB3> INFO: ----------------------------------------------------------------------
[12:31:45.245] <TB3> INFO: PixTestScurves::scurves(Vcal), ntrig = 50
[12:31:45.245] <TB3> INFO: ----------------------------------------------------------------------
[12:31:45.245] <TB3> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 0 .. 149 (4) hits flags = 16 (plus default)
[12:31:45.255] <TB3> INFO: dacScan step from 0 .. 3
[12:32:04.400] <TB3> INFO: Test took 19145ms.
[12:32:04.431] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:32:04.431] <TB3> INFO: dacScan step from 4 .. 7
[12:32:23.626] <TB3> INFO: Test took 19195ms.
[12:32:23.658] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:32:23.658] <TB3> INFO: dacScan step from 8 .. 11
[12:32:42.903] <TB3> INFO: Test took 19245ms.
[12:32:42.932] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:32:42.932] <TB3> INFO: dacScan step from 12 .. 15
[12:33:01.970] <TB3> INFO: Test took 19038ms.
[12:33:01.998] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:33:01.998] <TB3> INFO: dacScan step from 16 .. 19
[12:33:21.152] <TB3> INFO: Test took 19154ms.
[12:33:21.181] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:33:21.181] <TB3> INFO: dacScan step from 20 .. 23
[12:33:40.293] <TB3> INFO: Test took 19112ms.
[12:33:40.320] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:33:40.320] <TB3> INFO: dacScan step from 24 .. 27
[12:33:59.373] <TB3> INFO: Test took 19053ms.
[12:33:59.403] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:33:59.403] <TB3> INFO: dacScan step from 28 .. 31
[12:34:18.517] <TB3> INFO: Test took 19113ms.
[12:34:18.548] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:34:18.548] <TB3> INFO: dacScan step from 32 .. 35
[12:34:37.521] <TB3> INFO: Test took 18972ms.
[12:34:37.550] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:34:37.550] <TB3> INFO: dacScan step from 36 .. 39
[12:34:56.569] <TB3> INFO: Test took 19019ms.
[12:34:56.599] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:34:56.600] <TB3> INFO: dacScan step from 40 .. 43
[12:35:14.606] <TB3> INFO: Test took 18006ms.
[12:35:14.634] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:35:14.634] <TB3> INFO: dacScan step from 44 .. 47
[12:35:32.757] <TB3> INFO: Test took 18123ms.
[12:35:32.788] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:35:32.788] <TB3> INFO: dacScan step from 48 .. 51
[12:35:50.165] <TB3> INFO: Test took 17377ms.
[12:35:50.191] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:35:50.193] <TB3> INFO: dacScan step from 52 .. 55
[12:36:08.018] <TB3> INFO: Test took 17825ms.
[12:36:08.044] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:36:08.044] <TB3> INFO: dacScan step from 56 .. 59
[12:36:25.686] <TB3> INFO: Test took 17642ms.
[12:36:25.713] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:36:25.713] <TB3> INFO: dacScan step from 60 .. 63
[12:36:43.335] <TB3> INFO: Test took 17622ms.
[12:36:43.368] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:36:43.368] <TB3> INFO: dacScan step from 64 .. 67
[12:37:02.388] <TB3> INFO: Test took 19020ms.
[12:37:02.419] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:37:02.419] <TB3> INFO: dacScan step from 68 .. 71
[12:37:21.430] <TB3> INFO: Test took 19011ms.
[12:37:21.459] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:37:21.459] <TB3> INFO: dacScan step from 72 .. 75
[12:37:40.546] <TB3> INFO: Test took 19087ms.
[12:37:40.572] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:37:40.573] <TB3> INFO: dacScan step from 76 .. 79
[12:37:59.656] <TB3> INFO: Test took 19083ms.
[12:37:59.693] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:37:59.694] <TB3> INFO: dacScan step from 80 .. 83
[12:38:19.576] <TB3> INFO: Test took 19882ms.
[12:38:19.643] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:38:19.646] <TB3> INFO: dacScan step from 84 .. 87
[12:38:40.663] <TB3> INFO: Test took 21017ms.
[12:38:40.763] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:38:40.769] <TB3> INFO: dacScan step from 88 .. 91
[12:39:03.119] <TB3> INFO: Test took 22350ms.
[12:39:03.248] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:39:03.256] <TB3> INFO: dacScan step from 92 .. 95
[12:39:27.652] <TB3> INFO: Test took 24396ms.
[12:39:27.825] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:39:27.835] <TB3> INFO: dacScan step from 96 .. 99
[12:39:54.842] <TB3> INFO: Test took 27006ms.
[12:39:55.081] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:39:55.095] <TB3> INFO: dacScan step from 100 .. 103
[12:40:23.462] <TB3> INFO: Test took 28366ms.
[12:40:23.685] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:40:23.696] <TB3> INFO: dacScan step from 104 .. 107
[12:40:52.466] <TB3> ERROR: <datapipe.cc/CheckEventID:L420> Channel 3 Event ID mismatch: local ID (38) != TBM ID (0)
[12:40:52.466] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (3) != Token Chain Length (4)
[12:40:52.466] <TB3> ERROR: <datapipe.cc/CheckEventID:L420> Channel 3 Event ID mismatch: local ID (1) != TBM ID (39)
[12:40:52.755] <TB3> INFO: Test took 29059ms.
[12:40:52.994] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:40:53.006] <TB3> INFO: dacScan step from 108 .. 111
[12:41:21.526] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (8) != Token Chain Length (4)
[12:41:21.526] <TB3> ERROR: <datapipe.cc/CheckEventID:L420> Channel 3 Event ID mismatch: local ID (98) != TBM ID (99)
[12:41:21.531] <TB3> WARNING: Channel 3 ROC 1: Readback start marker after 15 readouts!
[12:41:21.532] <TB3> WARNING: Channel 3 ROC 2: Readback start marker after 15 readouts!
[12:41:21.532] <TB3> WARNING: Channel 3 ROC 3: Readback start marker after 15 readouts!
[12:41:22.525] <TB3> INFO: Test took 29519ms.
[12:41:22.758] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:41:22.770] <TB3> INFO: dacScan step from 112 .. 115
[12:41:51.183] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (2) != Token Chain Length (4)
[12:41:51.184] <TB3> WARNING: Channel 3 ROC 3: Readback start marker after 15 readouts!
[12:41:52.425] <TB3> INFO: Test took 29655ms.
[12:41:52.676] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:41:52.691] <TB3> INFO: dacScan step from 116 .. 119
[12:42:20.842] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (8) != Token Chain Length (4)
[12:42:20.842] <TB3> ERROR: <datapipe.cc/CheckEventID:L420> Channel 3 Event ID mismatch: local ID (246) != TBM ID (247)
[12:42:20.842] <TB3> WARNING: Channel 3 ROC 1: Readback start marker after 15 readouts!
[12:42:20.842] <TB3> WARNING: Channel 3 ROC 2: Readback start marker after 15 readouts!
[12:42:20.842] <TB3> WARNING: Channel 3 ROC 3: Readback start marker after 15 readouts!
[12:42:22.096] <TB3> INFO: Test took 29406ms.
[12:42:22.365] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:42:22.379] <TB3> INFO: dacScan step from 120 .. 123
[12:42:50.543] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (3) != Token Chain Length (4)
[12:42:51.822] <TB3> INFO: Test took 29443ms.
[12:42:52.061] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:42:52.074] <TB3> INFO: dacScan step from 124 .. 127
[12:43:20.370] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (3) != Token Chain Length (4)
[12:43:21.651] <TB3> INFO: Test took 29577ms.
[12:43:21.892] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:43:21.907] <TB3> INFO: dacScan step from 128 .. 131
[12:43:29.394] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 0 Number of ROCs (2) != Token Chain Length (4)
[12:43:29.394] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 1 Number of ROCs (2) != Token Chain Length (4)
[12:43:29.394] <TB3> WARNING: Channel 0 ROC 3: Readback start marker after 15 readouts!
[12:43:29.395] <TB3> WARNING: Channel 1 ROC 2: Readback start marker after 15 readouts!
[12:43:51.519] <TB3> INFO: Test took 29612ms.
[12:43:51.782] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:43:51.794] <TB3> INFO: dacScan step from 132 .. 135
[12:44:21.166] <TB3> INFO: Test took 29372ms.
[12:44:21.404] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:44:21.419] <TB3> INFO: dacScan step from 136 .. 139
[12:44:50.975] <TB3> INFO: Test took 29556ms.
[12:44:51.229] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:44:51.241] <TB3> INFO: dacScan step from 140 .. 143
[12:45:20.567] <TB3> INFO: Test took 29326ms.
[12:45:20.838] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:45:20.852] <TB3> INFO: dacScan step from 144 .. 147
[12:45:49.262] <TB3> INFO: Test took 28410ms.
[12:45:49.479] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:45:49.492] <TB3> INFO: dacScan step from 148 .. 149
[12:46:04.172] <TB3> INFO: Test took 14680ms.
[12:46:04.283] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:46:04.289] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:46:05.736] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:46:07.187] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:46:08.542] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:46:09.910] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:46:11.253] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:46:12.720] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:46:14.202] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:46:15.647] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:46:17.135] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:46:18.621] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:46:20.185] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:46:21.616] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:46:22.979] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:46:24.363] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:46:25.714] <TB3> INFO: dumping ASCII scurve output file: SCurveData
[12:46:27.197] <TB3> INFO: PixTestScurves::scurves() done
[12:46:27.197] <TB3> INFO: Vcal mean: 95.76 87.58 93.86 95.97 96.25 93.75 92.01 109.25 91.18 90.84 108.25 94.43 96.96 100.48 98.45 84.84
[12:46:27.197] <TB3> INFO: Vcal RMS: 6.36 5.30 5.12 5.10 5.09 5.67 5.24 5.85 5.75 4.94 5.22 4.68 5.26 5.74 5.34 5.34
[12:46:27.197] <TB3> INFO: PixTestScurves::fullTest() done, duration: 881 seconds
[12:46:27.275] <TB3> INFO: ######################################################################
[12:46:27.275] <TB3> INFO: PixTestTrim::doTest()
[12:46:27.275] <TB3> INFO: ######################################################################
[12:46:27.276] <TB3> INFO: ----------------------------------------------------------------------
[12:46:27.276] <TB3> INFO: PixTestTrim::trimTest() ntrig = 10, vcal = 35
[12:46:27.276] <TB3> INFO: ----------------------------------------------------------------------
[12:46:27.360] <TB3> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:46:27.360] <TB3> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 5 dacrange: 0 .. 159 (20) hits flags = 16 (plus default)
[12:46:27.369] <TB3> INFO: dacScan step from 0 .. 19
[12:46:42.480] <TB3> INFO: Test took 15111ms.
[12:46:42.506] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:46:42.506] <TB3> INFO: dacScan step from 20 .. 39
[12:46:57.112] <TB3> INFO: Test took 14606ms.
[12:46:57.140] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:46:57.140] <TB3> INFO: dacScan step from 40 .. 59
[12:47:11.535] <TB3> INFO: Test took 14395ms.
[12:47:11.556] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:47:11.556] <TB3> INFO: dacScan step from 60 .. 79
[12:47:26.001] <TB3> INFO: Test took 14445ms.
[12:47:26.024] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:47:26.033] <TB3> INFO: dacScan step from 80 .. 99
[12:47:40.656] <TB3> INFO: Test took 14623ms.
[12:47:40.690] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:47:40.693] <TB3> INFO: dacScan step from 100 .. 119
[12:47:59.115] <TB3> INFO: Test took 18422ms.
[12:47:59.268] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:47:59.295] <TB3> INFO: dacScan step from 120 .. 139
[12:48:18.130] <TB3> INFO: Test took 18835ms.
[12:48:18.302] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:48:18.343] <TB3> INFO: dacScan step from 140 .. 159
[12:48:33.862] <TB3> INFO: Test took 15519ms.
[12:48:33.936] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:48:56.035] <TB3> INFO: ROC 0 VthrComp = 95
[12:48:56.036] <TB3> INFO: ROC 1 VthrComp = 89
[12:48:56.036] <TB3> INFO: ROC 2 VthrComp = 99
[12:48:56.036] <TB3> INFO: ROC 3 VthrComp = 97
[12:48:56.036] <TB3> INFO: ROC 4 VthrComp = 99
[12:48:56.036] <TB3> INFO: ROC 5 VthrComp = 95
[12:48:56.036] <TB3> INFO: ROC 6 VthrComp = 94
[12:48:56.037] <TB3> INFO: ROC 7 VthrComp = 106
[12:48:56.037] <TB3> INFO: ROC 8 VthrComp = 91
[12:48:56.037] <TB3> INFO: ROC 9 VthrComp = 95
[12:48:56.037] <TB3> INFO: ROC 10 VthrComp = 105
[12:48:56.037] <TB3> INFO: ROC 11 VthrComp = 98
[12:48:56.037] <TB3> INFO: ROC 12 VthrComp = 101
[12:48:56.038] <TB3> INFO: ROC 13 VthrComp = 99
[12:48:56.038] <TB3> INFO: ROC 14 VthrComp = 100
[12:48:56.038] <TB3> INFO: ROC 15 VthrComp = 87
[12:48:56.038] <TB3> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:48:56.038] <TB3> INFO: ---> dac: vcal name: TrimThr1 ntrig: 5 dacrange: 0 .. 159 (20) hits flags = 16 (plus default)
[12:48:56.055] <TB3> INFO: dacScan step from 0 .. 19
[12:49:11.215] <TB3> INFO: Test took 15160ms.
[12:49:11.243] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:49:11.243] <TB3> INFO: dacScan step from 20 .. 39
[12:49:26.554] <TB3> INFO: Test took 15311ms.
[12:49:26.587] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:49:26.590] <TB3> INFO: dacScan step from 40 .. 59
[12:49:44.136] <TB3> INFO: Test took 17546ms.
[12:49:44.287] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:49:44.329] <TB3> INFO: dacScan step from 60 .. 79
[12:50:03.020] <TB3> INFO: Test took 18691ms.
[12:50:03.284] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:50:03.373] <TB3> INFO: dacScan step from 80 .. 99
[12:50:23.211] <TB3> INFO: Test took 19838ms.
[12:50:23.391] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:50:23.448] <TB3> INFO: dacScan step from 100 .. 119
[12:50:43.705] <TB3> INFO: Test took 20257ms.
[12:50:43.869] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:50:43.922] <TB3> INFO: dacScan step from 120 .. 139
[12:51:04.200] <TB3> INFO: Test took 20278ms.
[12:51:04.365] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:51:04.417] <TB3> INFO: dacScan step from 140 .. 159
[12:51:23.313] <TB3> INFO: Test took 18896ms.
[12:51:23.475] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:51:49.132] <TB3> INFO: roc 0 with ID = 0 has maximal Vcal 63.0589 for pixel 14/69 mean/min/max = 47.3944/31.6202/63.1687
[12:51:49.132] <TB3> INFO: roc 1 with ID = 1 has maximal Vcal 59.6556 for pixel 5/79 mean/min/max = 46.6674/33.6556/59.6792
[12:51:49.139] <TB3> INFO: roc 2 with ID = 2 has maximal Vcal 56.4489 for pixel 6/13 mean/min/max = 44.4111/32.2902/56.532
[12:51:49.139] <TB3> INFO: roc 3 with ID = 3 has maximal Vcal 57.4681 for pixel 15/1 mean/min/max = 45.2992/33.0995/57.4988
[12:51:49.140] <TB3> INFO: roc 4 with ID = 4 has maximal Vcal 56.1013 for pixel 17/4 mean/min/max = 44.2892/31.8666/56.7117
[12:51:49.140] <TB3> INFO: roc 5 with ID = 5 has maximal Vcal 59.1027 for pixel 17/69 mean/min/max = 45.2637/31.4074/59.12
[12:51:49.141] <TB3> INFO: roc 6 with ID = 6 has maximal Vcal 58.5832 for pixel 2/65 mean/min/max = 45.7763/32.928/58.6245
[12:51:49.141] <TB3> INFO: roc 7 with ID = 7 has maximal Vcal 63.1175 for pixel 2/74 mean/min/max = 48.7749/34.2485/63.3013
[12:51:49.142] <TB3> INFO: roc 8 with ID = 8 has maximal Vcal 59.9186 for pixel 6/2 mean/min/max = 46.4852/32.9268/60.0437
[12:51:49.142] <TB3> INFO: roc 9 with ID = 9 has maximal Vcal 56.3595 for pixel 19/76 mean/min/max = 44.7657/32.9418/56.5895
[12:51:49.143] <TB3> INFO: roc 10 with ID = 10 has maximal Vcal 63.1981 for pixel 2/4 mean/min/max = 48.7596/34.1403/63.379
[12:51:49.143] <TB3> INFO: roc 11 with ID = 11 has maximal Vcal 56.9184 for pixel 51/14 mean/min/max = 44.6381/32.1484/57.1279
[12:51:49.144] <TB3> INFO: roc 12 with ID = 12 has maximal Vcal 57.9399 for pixel 2/53 mean/min/max = 44.8985/31.6826/58.1145
[12:51:49.144] <TB3> INFO: roc 13 with ID = 13 has maximal Vcal 60.6104 for pixel 9/78 mean/min/max = 46.0403/31.4303/60.6502
[12:51:49.145] <TB3> INFO: roc 14 with ID = 14 has maximal Vcal 57.7117 for pixel 7/75 mean/min/max = 45.0047/32.0667/57.9426
[12:51:49.145] <TB3> INFO: roc 15 with ID = 15 has maximal Vcal 58.9797 for pixel 24/79 mean/min/max = 45.4313/31.8805/58.9822
[12:51:49.145] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:53:19.869] <TB3> INFO: Test took 90724ms.
[12:53:21.492] <TB3> INFO: ---> dac: vcal name: TrimThr2 ntrig: 10 dacrange: 0 .. 199 (20) hits flags = 16 (plus default)
[12:53:21.501] <TB3> INFO: dacScan step from 0 .. 19
[12:53:44.414] <TB3> INFO: Test took 22913ms.
[12:53:44.467] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:53:44.470] <TB3> INFO: dacScan step from 20 .. 39
[12:54:12.997] <TB3> INFO: Test took 28527ms.
[12:54:13.231] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:54:13.263] <TB3> INFO: dacScan step from 40 .. 59
[12:54:44.929] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (2) != Token Chain Length (4)
[12:54:44.929] <TB3> WARNING: Channel 3 ROC 3: Readback start marker after 15 readouts!
[12:54:46.192] <TB3> INFO: Test took 32929ms.
[12:54:46.500] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:54:46.559] <TB3> INFO: dacScan step from 60 .. 79
[12:55:18.203] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (2) != Token Chain Length (4)
[12:55:18.203] <TB3> WARNING: Channel 3 ROC 3: Readback start marker after 15 readouts!
[12:55:19.453] <TB3> INFO: Test took 32894ms.
[12:55:19.741] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:55:19.802] <TB3> INFO: dacScan step from 80 .. 99
[12:55:51.819] <TB3> ERROR: <datapipe.cc/CheckEventID:L420> Channel 3 Event ID mismatch: local ID (216) != TBM ID (0)
[12:55:51.819] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (3) != Token Chain Length (4)
[12:55:51.819] <TB3> ERROR: <datapipe.cc/CheckEventID:L420> Channel 3 Event ID mismatch: local ID (1) != TBM ID (217)
[12:55:53.127] <TB3> INFO: Test took 33325ms.
[12:55:53.415] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:55:53.468] <TB3> INFO: dacScan step from 100 .. 119
[12:56:26.685] <TB3> INFO: Test took 33216ms.
[12:56:26.975] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:56:27.029] <TB3> INFO: dacScan step from 120 .. 139
[12:56:58.965] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (3) != Token Chain Length (4)
[12:57:00.244] <TB3> INFO: Test took 33215ms.
[12:57:00.548] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:57:00.603] <TB3> INFO: dacScan step from 140 .. 159
[12:57:33.671] <TB3> INFO: Test took 33068ms.
[12:57:33.938] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:57:33.989] <TB3> INFO: dacScan step from 160 .. 179
[12:58:07.430] <TB3> INFO: Test took 33441ms.
[12:58:07.772] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:58:07.833] <TB3> INFO: dacScan step from 180 .. 199
[12:58:39.876] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (2) != Token Chain Length (4)
[12:58:39.876] <TB3> WARNING: Channel 3 ROC 3: Readback start marker after 15 readouts!
[12:58:41.008] <TB3> INFO: Test took 33175ms.
[12:58:41.459] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:59:07.491] <TB3> INFO: ---> TrimStepCorr4 extremal thresholds: 0.033461 .. 255.000000
[12:59:07.572] <TB3> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 4 dacrange: 0 .. 255 (20) hits flags = 16 (plus default)
[12:59:07.582] <TB3> INFO: dacScan step from 0 .. 19
[12:59:21.247] <TB3> INFO: Test took 13665ms.
[12:59:21.271] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:59:21.271] <TB3> INFO: dacScan step from 20 .. 39
[12:59:36.193] <TB3> INFO: Test took 14922ms.
[12:59:36.291] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:59:36.310] <TB3> INFO: dacScan step from 40 .. 59
[12:59:53.995] <TB3> INFO: Test took 17685ms.
[12:59:54.182] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:59:54.234] <TB3> INFO: dacScan step from 60 .. 79
[13:00:11.956] <TB3> INFO: Test took 17722ms.
[13:00:12.113] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:00:12.165] <TB3> INFO: dacScan step from 80 .. 99
[13:00:28.683] <TB3> INFO: Test took 16518ms.
[13:00:28.823] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:00:28.868] <TB3> INFO: dacScan step from 100 .. 119
[13:00:45.479] <TB3> INFO: Test took 16611ms.
[13:00:45.706] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:00:45.775] <TB3> INFO: dacScan step from 120 .. 139
[13:01:02.362] <TB3> INFO: Test took 16587ms.
[13:01:02.504] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:01:02.548] <TB3> INFO: dacScan step from 140 .. 159
[13:01:20.216] <TB3> INFO: Test took 17668ms.
[13:01:20.380] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:01:20.427] <TB3> INFO: dacScan step from 160 .. 179
[13:01:38.251] <TB3> INFO: Test took 17824ms.
[13:01:38.404] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:01:38.450] <TB3> INFO: dacScan step from 180 .. 199
[13:01:56.970] <TB3> INFO: Test took 18520ms.
[13:01:57.121] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:01:57.165] <TB3> INFO: dacScan step from 200 .. 219
[13:02:14.710] <TB3> INFO: Test took 17545ms.
[13:02:14.895] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:02:14.946] <TB3> INFO: dacScan step from 220 .. 239
[13:02:32.486] <TB3> INFO: Test took 17540ms.
[13:02:32.664] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:02:32.713] <TB3> INFO: dacScan step from 240 .. 255
[13:02:46.935] <TB3> INFO: Test took 14222ms.
[13:02:47.052] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:03:18.001] <TB3> INFO: ---> TrimStepCorr2 extremal thresholds: 14.714343 .. 198.474593
[13:03:18.076] <TB3> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 4 dacrange: 4 .. 208 (20) hits flags = 16 (plus default)
[13:03:18.085] <TB3> INFO: dacScan step from 4 .. 23
[13:03:31.685] <TB3> INFO: Test took 13600ms.
[13:03:31.713] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:03:31.713] <TB3> INFO: dacScan step from 24 .. 43
[13:03:47.242] <TB3> INFO: Test took 15529ms.
[13:03:47.361] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:03:47.391] <TB3> INFO: dacScan step from 44 .. 63
[13:04:04.109] <TB3> INFO: Test took 16718ms.
[13:04:04.266] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:04:04.314] <TB3> INFO: dacScan step from 64 .. 83
[13:04:22.050] <TB3> INFO: Test took 17736ms.
[13:04:22.208] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:04:22.260] <TB3> INFO: dacScan step from 84 .. 103
[13:04:40.069] <TB3> INFO: Test took 17809ms.
[13:04:40.225] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:04:40.278] <TB3> INFO: dacScan step from 104 .. 123
[13:04:56.930] <TB3> INFO: Test took 16652ms.
[13:04:57.071] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:04:57.122] <TB3> INFO: dacScan step from 124 .. 143
[13:05:14.015] <TB3> INFO: Test took 16893ms.
[13:05:14.250] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:05:14.351] <TB3> INFO: dacScan step from 144 .. 163
[13:05:31.106] <TB3> INFO: Test took 16755ms.
[13:05:31.259] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:05:31.319] <TB3> INFO: dacScan step from 164 .. 183
[13:05:48.189] <TB3> INFO: Test took 16870ms.
[13:05:48.429] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:05:48.486] <TB3> INFO: dacScan step from 184 .. 203
[13:06:06.094] <TB3> INFO: Test took 17608ms.
[13:06:06.251] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:06:06.303] <TB3> INFO: dacScan step from 204 .. 208
[13:06:12.584] <TB3> INFO: Test took 6281ms.
[13:06:12.620] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:06:43.565] <TB3> INFO: ---> TrimStepCorr1a extremal thresholds: 17.871714 .. 44.117522
[13:06:43.640] <TB3> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 4 dacrange: 7 .. 54 (20) hits flags = 16 (plus default)
[13:06:43.648] <TB3> INFO: dacScan step from 7 .. 26
[13:06:56.671] <TB3> INFO: Test took 13023ms.
[13:06:56.690] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:06:56.690] <TB3> INFO: dacScan step from 27 .. 46
[13:07:11.786] <TB3> INFO: Test took 15096ms.
[13:07:11.913] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:07:11.945] <TB3> INFO: dacScan step from 47 .. 54
[13:07:20.236] <TB3> INFO: Test took 8291ms.
[13:07:20.291] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:07:36.908] <TB3> INFO: ---> TrimStepCorr1b extremal thresholds: 1.592767 .. 43.541379
[13:07:36.993] <TB3> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 4 dacrange: 1 .. 53 (20) hits flags = 16 (plus default)
[13:07:37.001] <TB3> INFO: dacScan step from 1 .. 20
[13:07:49.983] <TB3> INFO: Test took 12982ms.
[13:07:50.002] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:07:50.002] <TB3> INFO: dacScan step from 21 .. 40
[13:08:04.623] <TB3> INFO: Test took 14621ms.
[13:08:04.701] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:08:04.723] <TB3> INFO: dacScan step from 41 .. 53
[13:08:16.432] <TB3> INFO: Test took 11709ms.
[13:08:16.537] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:08:32.192] <TB3> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[13:08:32.192] <TB3> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 10 dacrange: 15 .. 55 (20) hits flags = 16 (plus default)
[13:08:32.202] <TB3> INFO: dacScan step from 15 .. 34
[13:08:55.527] <TB3> INFO: Test took 23325ms.
[13:08:55.601] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:08:55.611] <TB3> INFO: dacScan step from 35 .. 54
[13:09:25.532] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (2) != Token Chain Length (4)
[13:09:25.533] <TB3> WARNING: Channel 3 ROC 3: Readback start marker after 15 readouts!
[13:09:26.194] <TB3> INFO: Test took 30583ms.
[13:09:26.567] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:09:26.618] <TB3> INFO: dacScan step from 55 .. 55
[13:09:30.831] <TB3> INFO: Test took 4212ms.
[13:09:30.848] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:09:44.396] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C0.dat
[13:09:44.396] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C1.dat
[13:09:44.397] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C2.dat
[13:09:44.397] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C3.dat
[13:09:44.397] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C4.dat
[13:09:44.397] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C5.dat
[13:09:44.398] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C6.dat
[13:09:44.398] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C7.dat
[13:09:44.398] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C8.dat
[13:09:44.399] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C9.dat
[13:09:44.399] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C10.dat
[13:09:44.399] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C11.dat
[13:09:44.399] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C12.dat
[13:09:44.400] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C13.dat
[13:09:44.400] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C14.dat
[13:09:44.400] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C15.dat
[13:09:44.400] <TB3> INFO: write trim parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters35_C0.dat
[13:09:44.411] <TB3> INFO: write trim parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters35_C1.dat
[13:09:44.417] <TB3> INFO: write trim parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters35_C2.dat
[13:09:44.423] <TB3> INFO: write trim parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters35_C3.dat
[13:09:44.429] <TB3> INFO: write trim parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters35_C4.dat
[13:09:44.435] <TB3> INFO: write trim parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters35_C5.dat
[13:09:44.441] <TB3> INFO: write trim parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters35_C6.dat
[13:09:44.448] <TB3> INFO: write trim parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters35_C7.dat
[13:09:44.454] <TB3> INFO: write trim parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters35_C8.dat
[13:09:44.460] <TB3> INFO: write trim parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters35_C9.dat
[13:09:44.466] <TB3> INFO: write trim parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters35_C10.dat
[13:09:44.472] <TB3> INFO: write trim parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters35_C11.dat
[13:09:44.478] <TB3> INFO: write trim parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters35_C12.dat
[13:09:44.484] <TB3> INFO: write trim parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters35_C13.dat
[13:09:44.490] <TB3> INFO: write trim parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters35_C14.dat
[13:09:44.496] <TB3> INFO: write trim parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//trimParameters35_C15.dat
[13:09:44.502] <TB3> INFO: PixTestTrim::trimTest() done
[13:09:44.502] <TB3> INFO: vtrim: 134 108 101 104 102 114 110 130 102 97 125 105 116 125 103 103
[13:09:44.502] <TB3> INFO: vthrcomp: 95 89 99 97 99 95 94 106 91 95 105 98 101 99 100 87
[13:09:44.502] <TB3> INFO: vcal mean: 35.15 35.12 35.06 35.17 35.09 35.05 35.08 35.18 35.10 35.09 35.11 35.09 35.07 35.09 35.09 35.08
[13:09:44.502] <TB3> INFO: vcal RMS: 1.14 1.04 1.04 1.04 1.18 1.08 1.01 1.26 1.07 1.02 1.11 0.98 1.08 1.11 1.06 1.03
[13:09:44.503] <TB3> INFO: bits mean: 9.39 9.45 10.27 9.74 10.42 10.10 9.35 9.20 9.70 9.78 9.16 9.67 10.51 10.09 10.23 9.75
[13:09:44.503] <TB3> INFO: bits RMS: 2.73 2.49 2.41 2.53 2.37 2.60 2.64 2.33 2.44 2.51 2.43 2.70 2.35 2.49 2.41 2.62
[13:09:44.511] <TB3> INFO: ----------------------------------------------------------------------
[13:09:44.511] <TB3> INFO: PixTestTrim::trimBitTest() ntrig = 10, vtrims = 254 126 63 32
[13:09:44.511] <TB3> INFO: ----------------------------------------------------------------------
[13:09:44.514] <TB3> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 10 dacrange: 0 .. 199 (20) hits flags = 16 (plus default)
[13:09:44.528] <TB3> INFO: dacScan step from 0 .. 19
[13:10:07.269] <TB3> INFO: Test took 22741ms.
[13:10:07.306] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:10:07.306] <TB3> INFO: dacScan step from 20 .. 39
[13:10:30.105] <TB3> INFO: Test took 22799ms.
[13:10:30.142] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:10:30.142] <TB3> INFO: dacScan step from 40 .. 59
[13:10:53.100] <TB3> INFO: Test took 22958ms.
[13:10:53.137] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:10:53.137] <TB3> INFO: dacScan step from 60 .. 79
[13:11:15.876] <TB3> INFO: Test took 22739ms.
[13:11:15.913] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:11:15.913] <TB3> INFO: dacScan step from 80 .. 99
[13:11:38.792] <TB3> INFO: Test took 22879ms.
[13:11:38.839] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:11:38.840] <TB3> INFO: dacScan step from 100 .. 119
[13:12:01.677] <TB3> INFO: Test took 22837ms.
[13:12:01.798] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:12:01.808] <TB3> INFO: dacScan step from 120 .. 139
[13:12:33.159] <TB3> INFO: Test took 31351ms.
[13:12:33.440] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:12:33.475] <TB3> INFO: dacScan step from 140 .. 159
[13:13:05.555] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (2) != Token Chain Length (4)
[13:13:05.555] <TB3> WARNING: Channel 3 ROC 3: Readback start marker after 15 readouts!
[13:13:06.777] <TB3> INFO: Test took 33302ms.
[13:13:07.115] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:13:07.161] <TB3> INFO: dacScan step from 160 .. 179
[13:13:40.366] <TB3> INFO: Test took 33205ms.
[13:13:40.664] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:13:40.712] <TB3> INFO: dacScan step from 180 .. 199
[13:14:14.197] <TB3> INFO: Test took 33485ms.
[13:14:14.488] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:14:41.902] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 10 dacrange: 0 .. 174 (20) hits flags = 16 (plus default)
[13:14:41.910] <TB3> INFO: dacScan step from 0 .. 19
[13:15:04.373] <TB3> INFO: Test took 22463ms.
[13:15:04.416] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:15:04.416] <TB3> INFO: dacScan step from 20 .. 39
[13:15:27.232] <TB3> INFO: Test took 22816ms.
[13:15:27.269] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:15:27.269] <TB3> INFO: dacScan step from 40 .. 59
[13:15:50.120] <TB3> INFO: Test took 22851ms.
[13:15:50.159] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:15:50.159] <TB3> INFO: dacScan step from 60 .. 79
[13:16:11.490] <TB3> INFO: Test took 21331ms.
[13:16:11.525] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:16:11.525] <TB3> INFO: dacScan step from 80 .. 99
[13:16:34.034] <TB3> INFO: Test took 22509ms.
[13:16:34.087] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:16:34.089] <TB3> INFO: dacScan step from 100 .. 119
[13:17:01.837] <TB3> INFO: Test took 27748ms.
[13:17:02.039] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:17:02.062] <TB3> INFO: dacScan step from 120 .. 139
[13:17:34.206] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (2) != Token Chain Length (4)
[13:17:34.206] <TB3> WARNING: Channel 3 ROC 3: Readback start marker after 15 readouts!
[13:17:35.152] <TB3> INFO: Test took 33090ms.
[13:17:35.479] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:17:35.521] <TB3> INFO: dacScan step from 140 .. 159
[13:18:07.453] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (2) != Token Chain Length (4)
[13:18:07.454] <TB3> WARNING: Channel 3 ROC 3: Readback start marker after 15 readouts!
[13:18:08.698] <TB3> INFO: Test took 33177ms.
[13:18:09.056] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:18:09.108] <TB3> INFO: dacScan step from 160 .. 174
[13:18:34.676] <TB3> INFO: Test took 25568ms.
[13:18:34.898] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:19:00.716] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 10 dacrange: 0 .. 161 (20) hits flags = 16 (plus default)
[13:19:00.725] <TB3> INFO: dacScan step from 0 .. 19
[13:19:21.816] <TB3> INFO: Test took 21091ms.
[13:19:21.853] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:19:21.853] <TB3> INFO: dacScan step from 20 .. 39
[13:19:44.772] <TB3> INFO: Test took 22918ms.
[13:19:44.811] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:19:44.811] <TB3> INFO: dacScan step from 40 .. 59
[13:20:06.256] <TB3> INFO: Test took 21445ms.
[13:20:06.294] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:20:06.294] <TB3> INFO: dacScan step from 60 .. 79
[13:20:28.944] <TB3> INFO: Test took 22650ms.
[13:20:28.980] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:20:28.980] <TB3> INFO: dacScan step from 80 .. 99
[13:20:51.986] <TB3> INFO: Test took 23006ms.
[13:20:52.043] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:20:52.044] <TB3> INFO: dacScan step from 100 .. 119
[13:21:19.677] <TB3> INFO: Test took 27633ms.
[13:21:19.900] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:21:19.924] <TB3> INFO: dacScan step from 120 .. 139
[13:21:52.078] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (2) != Token Chain Length (4)
[13:21:52.078] <TB3> WARNING: Channel 3 ROC 3: Readback start marker after 15 readouts!
[13:21:53.001] <TB3> INFO: Test took 33077ms.
[13:21:53.354] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:21:53.403] <TB3> INFO: dacScan step from 140 .. 159
[13:22:26.697] <TB3> INFO: Test took 33294ms.
[13:22:27.027] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:22:27.074] <TB3> INFO: dacScan step from 160 .. 161
[13:22:32.986] <TB3> INFO: Test took 5912ms.
[13:22:33.020] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:22:56.368] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 10 dacrange: 0 .. 162 (20) hits flags = 16 (plus default)
[13:22:56.377] <TB3> INFO: dacScan step from 0 .. 19
[13:23:17.914] <TB3> INFO: Test took 21537ms.
[13:23:17.952] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:23:17.953] <TB3> INFO: dacScan step from 20 .. 39
[13:23:40.785] <TB3> INFO: Test took 22832ms.
[13:23:40.820] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:23:40.820] <TB3> INFO: dacScan step from 40 .. 59
[13:24:02.225] <TB3> INFO: Test took 21405ms.
[13:24:02.271] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:24:02.271] <TB3> INFO: dacScan step from 60 .. 79
[13:24:25.095] <TB3> INFO: Test took 22824ms.
[13:24:25.138] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:24:25.138] <TB3> INFO: dacScan step from 80 .. 99
[13:24:48.054] <TB3> INFO: Test took 22916ms.
[13:24:48.107] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:24:48.108] <TB3> INFO: dacScan step from 100 .. 119
[13:25:15.832] <TB3> INFO: Test took 27724ms.
[13:25:16.038] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:25:16.061] <TB3> INFO: dacScan step from 120 .. 139
[13:25:48.136] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (2) != Token Chain Length (4)
[13:25:48.137] <TB3> WARNING: Channel 3 ROC 3: Readback start marker after 15 readouts!
[13:25:49.079] <TB3> INFO: Test took 33018ms.
[13:25:49.431] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:25:49.481] <TB3> INFO: dacScan step from 140 .. 159
[13:26:21.508] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (2) != Token Chain Length (4)
[13:26:21.508] <TB3> WARNING: Channel 3 ROC 3: Readback start marker after 31 readouts!
[13:26:22.797] <TB3> INFO: Test took 33316ms.
[13:26:23.087] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:26:23.138] <TB3> INFO: dacScan step from 160 .. 162
[13:26:30.571] <TB3> INFO: Test took 7432ms.
[13:26:30.623] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:26:55.036] <TB3> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 10 dacrange: 0 .. 163 (20) hits flags = 16 (plus default)
[13:26:55.045] <TB3> INFO: dacScan step from 0 .. 19
[13:27:17.045] <TB3> INFO: Test took 22000ms.
[13:27:17.081] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:27:17.081] <TB3> INFO: dacScan step from 20 .. 39
[13:27:38.684] <TB3> INFO: Test took 21603ms.
[13:27:38.729] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:27:38.729] <TB3> INFO: dacScan step from 40 .. 59
[13:28:00.017] <TB3> INFO: Test took 21288ms.
[13:28:00.057] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:28:00.057] <TB3> INFO: dacScan step from 60 .. 79
[13:28:22.850] <TB3> INFO: Test took 22793ms.
[13:28:22.887] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:28:22.887] <TB3> INFO: dacScan step from 80 .. 99
[13:28:45.766] <TB3> INFO: Test took 22879ms.
[13:28:45.819] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:28:45.821] <TB3> INFO: dacScan step from 100 .. 119
[13:29:13.589] <TB3> INFO: Test took 27768ms.
[13:29:13.788] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:29:13.810] <TB3> INFO: dacScan step from 120 .. 139
[13:29:45.698] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (8) != Token Chain Length (4)
[13:29:45.698] <TB3> ERROR: <datapipe.cc/CheckEventID:L420> Channel 3 Event ID mismatch: local ID (182) != TBM ID (183)
[13:29:45.698] <TB3> WARNING: Channel 3 ROC 1: Readback start marker after 15 readouts!
[13:29:45.698] <TB3> WARNING: Channel 3 ROC 2: Readback start marker after 15 readouts!
[13:29:45.698] <TB3> WARNING: Channel 3 ROC 3: Readback start marker after 15 readouts!
[13:29:46.660] <TB3> INFO: Test took 32850ms.
[13:29:46.965] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:29:47.011] <TB3> INFO: dacScan step from 140 .. 159
[13:30:18.865] <TB3> ERROR: <datapipe.cc/CheckEventValidity:L437> Channel 3 Number of ROCs (2) != Token Chain Length (4)
[13:30:18.865] <TB3> WARNING: Channel 3 ROC 3: Readback start marker after 31 readouts!
[13:30:20.124] <TB3> INFO: Test took 33113ms.
[13:30:20.402] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:30:20.449] <TB3> INFO: dacScan step from 160 .. 163
[13:30:29.373] <TB3> INFO: Test took 8924ms.
[13:30:29.433] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:30:52.089] <TB3> INFO: PixTestTrim::trimBitTest() done
[13:30:52.091] <TB3> INFO: PixTestTrim::doTest() done, duration: 2664 seconds
[13:30:52.751] <TB3> INFO: ######################################################################
[13:30:52.751] <TB3> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:30:52.751] <TB3> INFO: ######################################################################
[13:30:56.170] <TB3> INFO: Test took 3417ms.
[13:30:56.190] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:30:59.903] <TB3> INFO: Test took 3515ms.
[13:30:59.973] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:31:03.430] <TB3> INFO: Test took 3447ms.
[13:31:03.495] <TB3> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:31:03.502] <TB3> INFO: The DUT currently contains the following objects:
[13:31:03.502] <TB3> INFO: 2 TBM Cores tbm09c (2 ON)
[13:31:03.502] <TB3> INFO: TBM Core alpha (0): 7 registers set
[13:31:03.502] <TB3> INFO: TBM Core beta (1): 7 registers set
[13:31:03.502] <TB3> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:31:03.502] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:03.502] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:03.502] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:03.502] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:03.502] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:03.502] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:03.502] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:03.502] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:03.502] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:03.502] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:03.502] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:03.502] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:03.502] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:03.502] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:03.502] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:03.502] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:04.611] <TB3> INFO: Test took 1109ms.
[13:31:04.613] <TB3> INFO: The DUT currently contains the following objects:
[13:31:04.613] <TB3> INFO: 2 TBM Cores tbm09c (2 ON)
[13:31:04.613] <TB3> INFO: TBM Core alpha (0): 7 registers set
[13:31:04.613] <TB3> INFO: TBM Core beta (1): 7 registers set
[13:31:04.613] <TB3> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:31:04.613] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:04.613] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:04.613] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:04.613] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:04.614] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:04.614] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:04.614] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:04.614] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:04.614] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:04.614] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:04.614] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:04.614] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:04.614] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:04.614] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:04.614] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:04.614] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:05.735] <TB3> INFO: Test took 1121ms.
[13:31:05.736] <TB3> INFO: The DUT currently contains the following objects:
[13:31:05.736] <TB3> INFO: 2 TBM Cores tbm09c (2 ON)
[13:31:05.736] <TB3> INFO: TBM Core alpha (0): 7 registers set
[13:31:05.736] <TB3> INFO: TBM Core beta (1): 7 registers set
[13:31:05.736] <TB3> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:31:05.736] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:05.736] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:05.736] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:05.736] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:05.736] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:05.736] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:05.736] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:05.736] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:05.737] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:05.737] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:05.737] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:05.737] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:05.737] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:05.737] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:05.737] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:05.737] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:06.844] <TB3> INFO: Test took 1107ms.
[13:31:06.846] <TB3> INFO: The DUT currently contains the following objects:
[13:31:06.846] <TB3> INFO: 2 TBM Cores tbm09c (2 ON)
[13:31:06.846] <TB3> INFO: TBM Core alpha (0): 7 registers set
[13:31:06.846] <TB3> INFO: TBM Core beta (1): 7 registers set
[13:31:06.846] <TB3> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:31:06.846] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:06.846] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:06.846] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:06.846] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:06.846] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:06.846] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:06.846] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:06.846] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:06.846] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:06.847] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:06.847] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:06.847] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:06.847] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:06.847] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:06.847] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:06.847] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:07.955] <TB3> INFO: Test took 1108ms.
[13:31:07.956] <TB3> INFO: The DUT currently contains the following objects:
[13:31:07.956] <TB3> INFO: 2 TBM Cores tbm09c (2 ON)
[13:31:07.956] <TB3> INFO: TBM Core alpha (0): 7 registers set
[13:31:07.956] <TB3> INFO: TBM Core beta (1): 7 registers set
[13:31:07.956] <TB3> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:31:07.956] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:07.956] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:07.956] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:07.956] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:07.956] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:07.956] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:07.956] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:07.956] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:07.956] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:07.956] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:07.956] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:07.957] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:07.957] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:07.957] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:07.957] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:07.957] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:09.059] <TB3> INFO: Test took 1102ms.
[13:31:09.059] <TB3> INFO: The DUT currently contains the following objects:
[13:31:09.059] <TB3> INFO: 2 TBM Cores tbm09c (2 ON)
[13:31:09.059] <TB3> INFO: TBM Core alpha (0): 7 registers set
[13:31:09.059] <TB3> INFO: TBM Core beta (1): 7 registers set
[13:31:09.059] <TB3> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:31:09.059] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:09.059] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:09.060] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:09.060] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:09.060] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:09.060] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:09.060] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:09.060] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:09.060] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:09.060] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:09.060] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:09.060] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:09.060] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:09.060] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:09.060] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:09.060] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:10.162] <TB3> INFO: Test took 1102ms.
[13:31:10.162] <TB3> INFO: The DUT currently contains the following objects:
[13:31:10.162] <TB3> INFO: 2 TBM Cores tbm09c (2 ON)
[13:31:10.162] <TB3> INFO: TBM Core alpha (0): 7 registers set
[13:31:10.162] <TB3> INFO: TBM Core beta (1): 7 registers set
[13:31:10.162] <TB3> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:31:10.162] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:10.162] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:10.162] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:10.162] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:10.163] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:10.163] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:10.163] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:10.163] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:10.163] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:10.163] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:10.163] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:10.163] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:10.163] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:10.163] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:10.163] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:10.163] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:11.269] <TB3> INFO: Test took 1106ms.
[13:31:11.270] <TB3> INFO: The DUT currently contains the following objects:
[13:31:11.270] <TB3> INFO: 2 TBM Cores tbm09c (2 ON)
[13:31:11.270] <TB3> INFO: TBM Core alpha (0): 7 registers set
[13:31:11.270] <TB3> INFO: TBM Core beta (1): 7 registers set
[13:31:11.270] <TB3> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:31:11.270] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:11.270] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:11.270] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:11.271] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:11.271] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:11.271] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:11.271] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:11.271] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:11.271] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:11.271] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:11.271] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:11.271] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:11.271] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:11.271] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:11.271] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:11.271] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:12.381] <TB3> INFO: Test took 1110ms.
[13:31:12.382] <TB3> INFO: The DUT currently contains the following objects:
[13:31:12.382] <TB3> INFO: 2 TBM Cores tbm09c (2 ON)
[13:31:12.382] <TB3> INFO: TBM Core alpha (0): 7 registers set
[13:31:12.382] <TB3> INFO: TBM Core beta (1): 7 registers set
[13:31:12.382] <TB3> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:31:12.382] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:12.382] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:12.382] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:12.382] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:12.382] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:12.382] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:12.382] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:12.382] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:12.383] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:12.383] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:12.383] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:12.383] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:12.383] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:12.383] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:12.383] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:12.383] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:13.505] <TB3> INFO: Test took 1122ms.
[13:31:13.506] <TB3> INFO: The DUT currently contains the following objects:
[13:31:13.506] <TB3> INFO: 2 TBM Cores tbm09c (2 ON)
[13:31:13.506] <TB3> INFO: TBM Core alpha (0): 7 registers set
[13:31:13.506] <TB3> INFO: TBM Core beta (1): 7 registers set
[13:31:13.506] <TB3> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:31:13.506] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:13.506] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:13.506] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:13.506] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:13.506] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:13.506] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:13.506] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:13.506] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:13.506] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:13.506] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:13.507] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:13.507] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:13.507] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:13.507] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:13.507] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:13.507] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:14.614] <TB3> INFO: Test took 1107ms.
[13:31:14.616] <TB3> INFO: The DUT currently contains the following objects:
[13:31:14.616] <TB3> INFO: 2 TBM Cores tbm09c (2 ON)
[13:31:14.616] <TB3> INFO: TBM Core alpha (0): 7 registers set
[13:31:14.616] <TB3> INFO: TBM Core beta (1): 7 registers set
[13:31:14.616] <TB3> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:31:14.616] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:14.616] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:14.616] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:14.616] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:14.616] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:14.616] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:14.616] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:14.616] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:14.616] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:14.616] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:14.616] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:14.616] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:14.616] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:14.616] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:14.616] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:14.616] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:15.723] <TB3> INFO: Test took 1107ms.
[13:31:15.724] <TB3> INFO: The DUT currently contains the following objects:
[13:31:15.724] <TB3> INFO: 2 TBM Cores tbm09c (2 ON)
[13:31:15.724] <TB3> INFO: TBM Core alpha (0): 7 registers set
[13:31:15.724] <TB3> INFO: TBM Core beta (1): 7 registers set
[13:31:15.724] <TB3> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:31:15.725] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:15.725] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:15.725] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:15.725] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:15.725] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:15.725] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:15.725] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:15.725] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:15.725] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:15.725] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:15.725] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:15.725] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:15.725] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:15.725] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:15.725] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:15.725] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:16.827] <TB3> INFO: Test took 1102ms.
[13:31:16.827] <TB3> INFO: The DUT currently contains the following objects:
[13:31:16.827] <TB3> INFO: 2 TBM Cores tbm09c (2 ON)
[13:31:16.827] <TB3> INFO: TBM Core alpha (0): 7 registers set
[13:31:16.827] <TB3> INFO: TBM Core beta (1): 7 registers set
[13:31:16.827] <TB3> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:31:16.827] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:16.827] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:16.827] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:16.827] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:16.827] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:16.827] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:16.827] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:16.827] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:16.827] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:16.827] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:16.827] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:16.827] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:16.827] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:16.827] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:16.827] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:16.827] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:17.929] <TB3> INFO: Test took 1102ms.
[13:31:17.929] <TB3> INFO: The DUT currently contains the following objects:
[13:31:17.929] <TB3> INFO: 2 TBM Cores tbm09c (2 ON)
[13:31:17.929] <TB3> INFO: TBM Core alpha (0): 7 registers set
[13:31:17.929] <TB3> INFO: TBM Core beta (1): 7 registers set
[13:31:17.929] <TB3> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:31:17.929] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:17.929] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:17.929] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:17.929] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:17.929] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:17.929] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:17.929] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:17.930] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:17.930] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:17.930] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:17.930] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:17.930] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:17.930] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:17.930] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:17.930] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:17.930] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:19.032] <TB3> INFO: Test took 1102ms.
[13:31:19.032] <TB3> INFO: The DUT currently contains the following objects:
[13:31:19.032] <TB3> INFO: 2 TBM Cores tbm09c (2 ON)
[13:31:19.032] <TB3> INFO: TBM Core alpha (0): 7 registers set
[13:31:19.032] <TB3> INFO: TBM Core beta (1): 7 registers set
[13:31:19.032] <TB3> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:31:19.032] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:19.032] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:19.032] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:19.032] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:19.033] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:19.033] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:19.033] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:19.033] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:19.033] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:19.033] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:19.033] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:19.033] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:19.033] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:19.033] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:19.033] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:19.033] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:20.133] <TB3> INFO: Test took 1100ms.
[13:31:20.134] <TB3> INFO: The DUT currently contains the following objects:
[13:31:20.134] <TB3> INFO: 2 TBM Cores tbm09c (2 ON)
[13:31:20.134] <TB3> INFO: TBM Core alpha (0): 7 registers set
[13:31:20.134] <TB3> INFO: TBM Core beta (1): 7 registers set
[13:31:20.134] <TB3> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[13:31:20.134] <TB3> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:20.134] <TB3> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:20.134] <TB3> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:20.134] <TB3> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:20.134] <TB3> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:20.134] <TB3> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:20.134] <TB3> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:20.134] <TB3> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:20.134] <TB3> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:20.134] <TB3> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:20.134] <TB3> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:20.134] <TB3> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:20.134] <TB3> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:20.134] <TB3> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:20.134] <TB3> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:20.134] <TB3> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[13:31:21.236] <TB3> INFO: Test took 1102ms.
[13:31:21.239] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:35:05.183] <TB3> INFO: Test took 223944ms.
[13:35:06.780] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:38:43.342] <TB3> INFO: Test took 216562ms.
[13:38:45.195] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:38:45.203] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:38:45.211] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[13:38:45.218] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[13:38:45.225] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[13:38:45.232] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[13:38:45.239] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:38:45.246] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:38:45.253] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[13:38:45.261] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[13:38:45.268] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[13:38:45.275] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[13:38:45.281] <TB3> INFO: safety margin for low PH: adding 5, margin is now 25
[13:38:45.288] <TB3> INFO: safety margin for low PH: adding 6, margin is now 26
[13:38:45.296] <TB3> INFO: safety margin for low PH: adding 7, margin is now 27
[13:38:45.303] <TB3> INFO: safety margin for low PH: adding 8, margin is now 28
[13:38:45.310] <TB3> INFO: safety margin for low PH: adding 9, margin is now 29
[13:38:45.318] <TB3> INFO: safety margin for low PH: adding 10, margin is now 30
[13:38:45.326] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:38:45.333] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:38:45.341] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:38:45.348] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:38:45.355] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:38:45.362] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:38:45.369] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:38:45.376] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:38:45.383] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:38:45.391] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:38:45.399] <TB3> INFO: safety margin for low PH: adding 1, margin is now 21
[13:38:45.406] <TB3> INFO: safety margin for low PH: adding 2, margin is now 22
[13:38:45.414] <TB3> INFO: safety margin for low PH: adding 3, margin is now 23
[13:38:45.422] <TB3> INFO: safety margin for low PH: adding 4, margin is now 24
[13:38:45.429] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:38:45.436] <TB3> INFO: safety margin for low PH: adding 0, margin is now 20
[13:38:45.487] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C0.dat
[13:38:45.487] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C1.dat
[13:38:45.488] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C2.dat
[13:38:45.488] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C3.dat
[13:38:45.488] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C4.dat
[13:38:45.488] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C5.dat
[13:38:45.492] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C6.dat
[13:38:45.492] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C7.dat
[13:38:45.492] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C8.dat
[13:38:45.493] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C9.dat
[13:38:45.493] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C10.dat
[13:38:45.493] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C11.dat
[13:38:45.493] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C12.dat
[13:38:45.494] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C13.dat
[13:38:45.494] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C14.dat
[13:38:45.495] <TB3> INFO: write dac parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//dacParameters35_C15.dat
[13:38:48.932] <TB3> INFO: Test took 3433ms.
[13:38:52.666] <TB3> INFO: Test took 3454ms.
[13:38:56.263] <TB3> INFO: Test took 3326ms.
[13:38:56.537] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:38:57.449] <TB3> INFO: Test took 912ms.
[13:38:57.451] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:38:58.553] <TB3> INFO: Test took 1102ms.
[13:38:58.556] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:38:59.657] <TB3> INFO: Test took 1101ms.
[13:38:59.660] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:00.761] <TB3> INFO: Test took 1101ms.
[13:39:00.764] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:01.866] <TB3> INFO: Test took 1102ms.
[13:39:01.868] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:02.971] <TB3> INFO: Test took 1103ms.
[13:39:02.974] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:04.074] <TB3> INFO: Test took 1100ms.
[13:39:04.077] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:05.179] <TB3> INFO: Test took 1102ms.
[13:39:05.181] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:06.284] <TB3> INFO: Test took 1103ms.
[13:39:06.287] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:07.389] <TB3> INFO: Test took 1102ms.
[13:39:07.393] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:08.495] <TB3> INFO: Test took 1102ms.
[13:39:08.498] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:09.601] <TB3> INFO: Test took 1104ms.
[13:39:09.603] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:10.705] <TB3> INFO: Test took 1102ms.
[13:39:10.708] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:11.809] <TB3> INFO: Test took 1101ms.
[13:39:11.812] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:12.912] <TB3> INFO: Test took 1100ms.
[13:39:12.914] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:14.016] <TB3> INFO: Test took 1102ms.
[13:39:14.019] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:15.120] <TB3> INFO: Test took 1101ms.
[13:39:15.122] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:16.223] <TB3> INFO: Test took 1101ms.
[13:39:16.226] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:17.327] <TB3> INFO: Test took 1101ms.
[13:39:17.331] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:18.431] <TB3> INFO: Test took 1100ms.
[13:39:18.434] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:19.535] <TB3> INFO: Test took 1101ms.
[13:39:19.537] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:20.639] <TB3> INFO: Test took 1102ms.
[13:39:20.641] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:21.742] <TB3> INFO: Test took 1101ms.
[13:39:21.745] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:22.846] <TB3> INFO: Test took 1101ms.
[13:39:22.849] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:23.950] <TB3> INFO: Test took 1101ms.
[13:39:23.953] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:25.054] <TB3> INFO: Test took 1101ms.
[13:39:25.057] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:26.157] <TB3> INFO: Test took 1100ms.
[13:39:26.160] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:27.261] <TB3> INFO: Test took 1101ms.
[13:39:27.263] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:28.364] <TB3> INFO: Test took 1101ms.
[13:39:28.366] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:29.467] <TB3> INFO: Test took 1101ms.
[13:39:29.470] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:30.570] <TB3> INFO: Test took 1100ms.
[13:39:30.574] <TB3> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:39:31.675] <TB3> INFO: Test took 1101ms.
[13:39:32.240] <TB3> INFO: PixTestPhOptimization::doTest() done, duration: 519 seconds
[13:39:32.240] <TB3> INFO: PH scale (per ROC): 73 77 74 82 77 80 74 71 71 72 68 75 76 71 67 70
[13:39:32.240] <TB3> INFO: PH offset (per ROC): 181 176 178 176 175 187 179 189 174 179 186 179 179 208 176 160
[13:39:32.418] <TB3> INFO: ######################################################################
[13:39:32.418] <TB3> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:39:32.418] <TB3> INFO: ######################################################################
[13:39:32.431] <TB3> INFO: scanning low vcal = 10
[13:39:36.288] <TB3> INFO: Test took 3856ms.
[13:39:36.294] <TB3> INFO: scanning low vcal = 20
[13:39:40.172] <TB3> INFO: Test took 3878ms.
[13:39:40.177] <TB3> INFO: scanning low vcal = 30
[13:39:44.053] <TB3> INFO: Test took 3876ms.
[13:39:44.067] <TB3> INFO: scanning low vcal = 40
[13:39:48.434] <TB3> INFO: Test took 4366ms.
[13:39:48.500] <TB3> INFO: scanning low vcal = 50
[13:39:52.898] <TB3> INFO: Test took 4398ms.
[13:39:52.960] <TB3> INFO: scanning low vcal = 60
[13:39:57.333] <TB3> INFO: Test took 4373ms.
[13:39:57.398] <TB3> INFO: scanning low vcal = 70
[13:40:01.756] <TB3> INFO: Test took 4358ms.
[13:40:01.817] <TB3> INFO: scanning low vcal = 80
[13:40:06.178] <TB3> INFO: Test took 4361ms.
[13:40:06.239] <TB3> INFO: scanning low vcal = 90
[13:40:10.582] <TB3> INFO: Test took 4343ms.
[13:40:10.655] <TB3> INFO: scanning low vcal = 100
[13:40:15.011] <TB3> INFO: Test took 4356ms.
[13:40:15.074] <TB3> INFO: scanning low vcal = 110
[13:40:19.445] <TB3> INFO: Test took 4371ms.
[13:40:19.505] <TB3> INFO: scanning low vcal = 120
[13:40:23.863] <TB3> INFO: Test took 4358ms.
[13:40:23.931] <TB3> INFO: scanning low vcal = 130
[13:40:28.294] <TB3> INFO: Test took 4363ms.
[13:40:28.361] <TB3> INFO: scanning low vcal = 140
[13:40:32.637] <TB3> INFO: Test took 4276ms.
[13:40:32.698] <TB3> INFO: scanning low vcal = 150
[13:40:37.032] <TB3> INFO: Test took 4334ms.
[13:40:37.097] <TB3> INFO: scanning low vcal = 160
[13:40:41.467] <TB3> INFO: Test took 4370ms.
[13:40:41.547] <TB3> INFO: scanning low vcal = 170
[13:40:45.926] <TB3> INFO: Test took 4379ms.
[13:40:45.999] <TB3> INFO: scanning low vcal = 180
[13:40:50.348] <TB3> INFO: Test took 4349ms.
[13:40:50.407] <TB3> INFO: scanning low vcal = 190
[13:40:54.887] <TB3> INFO: Test took 4480ms.
[13:40:54.952] <TB3> INFO: scanning low vcal = 200
[13:40:59.353] <TB3> INFO: Test took 4401ms.
[13:40:59.419] <TB3> INFO: scanning low vcal = 210
[13:41:03.791] <TB3> INFO: Test took 4372ms.
[13:41:03.855] <TB3> INFO: scanning low vcal = 220
[13:41:08.230] <TB3> INFO: Test took 4375ms.
[13:41:08.293] <TB3> INFO: scanning low vcal = 230
[13:41:12.637] <TB3> INFO: Test took 4344ms.
[13:41:12.697] <TB3> INFO: scanning low vcal = 240
[13:41:17.008] <TB3> INFO: Test took 4311ms.
[13:41:17.069] <TB3> INFO: scanning low vcal = 250
[13:41:21.393] <TB3> INFO: Test took 4324ms.
[13:41:21.471] <TB3> INFO: scanning high vcal = 30 (= 210 in low range)
[13:41:25.797] <TB3> INFO: Test took 4326ms.
[13:41:25.856] <TB3> INFO: scanning high vcal = 50 (= 350 in low range)
[13:41:30.204] <TB3> INFO: Test took 4348ms.
[13:41:30.268] <TB3> INFO: scanning high vcal = 70 (= 490 in low range)
[13:41:34.619] <TB3> INFO: Test took 4351ms.
[13:41:34.709] <TB3> INFO: scanning high vcal = 90 (= 630 in low range)
[13:41:39.066] <TB3> INFO: Test took 4357ms.
[13:41:39.124] <TB3> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:41:43.487] <TB3> INFO: Test took 4363ms.
[13:41:43.991] <TB3> INFO: PixTestGainPedestal::measure() done
[13:42:17.412] <TB3> INFO: PixTestGainPedestal::fit() done
[13:42:17.412] <TB3> INFO: non-linearity mean: 0.955 0.954 0.958 0.967 0.952 0.956 0.959 0.958 0.957 0.953 0.956 0.960 0.954 0.961 0.962 0.957
[13:42:17.412] <TB3> INFO: non-linearity RMS: 0.007 0.005 0.005 0.003 0.007 0.006 0.006 0.007 0.006 0.007 0.006 0.007 0.007 0.006 0.006 0.006
[13:42:17.412] <TB3> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//phCalibrationFitErr35_C0.dat
[13:42:17.431] <TB3> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//phCalibrationFitErr35_C1.dat
[13:42:17.449] <TB3> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//phCalibrationFitErr35_C2.dat
[13:42:17.468] <TB3> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//phCalibrationFitErr35_C3.dat
[13:42:17.487] <TB3> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//phCalibrationFitErr35_C4.dat
[13:42:17.506] <TB3> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//phCalibrationFitErr35_C5.dat
[13:42:17.525] <TB3> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//phCalibrationFitErr35_C6.dat
[13:42:17.545] <TB3> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//phCalibrationFitErr35_C7.dat
[13:42:17.571] <TB3> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//phCalibrationFitErr35_C8.dat
[13:42:17.593] <TB3> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//phCalibrationFitErr35_C9.dat
[13:42:17.615] <TB3> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//phCalibrationFitErr35_C10.dat
[13:42:17.634] <TB3> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//phCalibrationFitErr35_C11.dat
[13:42:17.658] <TB3> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//phCalibrationFitErr35_C12.dat
[13:42:17.679] <TB3> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//phCalibrationFitErr35_C13.dat
[13:42:17.702] <TB3> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//phCalibrationFitErr35_C14.dat
[13:42:17.721] <TB3> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2073_FullQualification_2015-08-13_09h40m_1439451613//004_FulltestPxar_p17//phCalibrationFitErr35_C15.dat
[13:42:17.741] <TB3> INFO: PixTestGainPedestal::doTest() done, duration: 165 seconds
[13:42:17.747] <TB3> INFO: enter test to run
[13:42:17.747] <TB3> INFO: test: exit no parameter change
[13:42:18.201] <TB3> QUIET: Connection to board 170 closed.
[13:42:18.281] <TB3> INFO: pXar: this is the end, my friend