[08:49:50.909] <TB2> INFO: *** Welcome to pxar ***
[08:49:50.909] <TB2> INFO: *** Today: 2015/07/24
[08:49:50.909] <TB2> INFO: readRocDacs: /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C0.dat .. /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C15.dat
[08:49:50.910] <TB2> INFO: readTbmDacs: /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//tbmParameters_C0a.dat .. /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//tbmParameters_C0b.dat
[08:49:50.910] <TB2> INFO: readMaskFile: /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//defaultMaskFile.dat
[08:49:50.910] <TB2> INFO: readTrimFile: /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters_C0.dat .. /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters_C15.dat
[08:49:50.985] <TB2> INFO: clk: 4
[08:49:50.985] <TB2> INFO: ctr: 4
[08:49:50.985] <TB2> INFO: sda: 19
[08:49:50.985] <TB2> INFO: tin: 9
[08:49:50.985] <TB2> INFO: level: 15
[08:49:50.985] <TB2> INFO: triggerdelay: 0
[08:49:50.985] <TB2> QUIET: Instanciating API for pxar v2.2.5+46~gdbe75a1
[08:49:50.985] <TB2> INFO: Log level: INFO
[08:49:50.993] <TB2> INFO: Found DTB DTB_WXC55Z
[08:49:51.005] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[08:49:51.008] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.0
SW version: 4.0
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[08:49:51.011] <TB2> INFO: RPC call hashes of host and DTB match: 447413373
[08:49:52.547] <TB2> INFO: DUT info:
[08:49:52.547] <TB2> INFO: The DUT currently contains the following objects:
[08:49:52.547] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[08:49:52.547] <TB2> INFO: TBM Core alpha (0): 7 registers set
[08:49:52.547] <TB2> INFO: TBM Core beta (1): 7 registers set
[08:49:52.547] <TB2> INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[08:49:52.547] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[08:49:52.547] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[08:49:52.547] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[08:49:52.547] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[08:49:52.547] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[08:49:52.547] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[08:49:52.547] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[08:49:52.547] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[08:49:52.547] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[08:49:52.547] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[08:49:52.547] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[08:49:52.547] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[08:49:52.547] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[08:49:52.547] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[08:49:52.547] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[08:49:52.547] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[08:49:52.948] <TB2> INFO: enter 'restricted' command line mode
[08:49:52.948] <TB2> INFO: enter test to run
[08:49:52.948] <TB2> INFO: test: pretest no parameter change
[08:49:52.949] <TB2> INFO: running: pretest
[08:49:52.954] <TB2> INFO: ######################################################################
[08:49:52.954] <TB2> INFO: PixTestPretest::doTest()
[08:49:52.954] <TB2> INFO: ######################################################################
[08:49:52.956] <TB2> INFO: ----------------------------------------------------------------------
[08:49:52.956] <TB2> INFO: PixTestPretest::programROC()
[08:49:52.956] <TB2> INFO: ----------------------------------------------------------------------
[08:50:10.973] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[08:50:10.973] <TB2> INFO: IA differences per ROC: 17.7 20.1 21.7 17.7 18.5 16.9 18.5 17.7 18.5 18.5 16.9 19.3 19.3 19.3 16.1 17.7
[08:50:11.046] <TB2> INFO: ----------------------------------------------------------------------
[08:50:11.046] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[08:50:11.046] <TB2> INFO: ----------------------------------------------------------------------
[08:50:30.596] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 382.7 mA = 23.9187 mA/ROC
[08:50:30.599] <TB2> INFO: ----------------------------------------------------------------------
[08:50:30.599] <TB2> INFO: PixTestPretest::findWorkingPixel()
[08:50:30.599] <TB2> INFO: ----------------------------------------------------------------------
[08:50:39.836] <TB2> INFO: Test took 9233ms.
[08:50:40.134] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[08:50:40.170] <TB2> INFO: ----------------------------------------------------------------------
[08:50:40.170] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[08:50:40.170] <TB2> INFO: ----------------------------------------------------------------------
[08:50:49.429] <TB2> INFO: Test took 9254ms.
[08:50:49.714] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[08:50:49.714] <TB2> INFO: CalDel: 124 133 129 133 136 141 122 130 139 123 122 145 138 143 142 144
[08:50:49.714] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[08:50:49.718] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C0.dat
[08:50:49.718] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C1.dat
[08:50:49.719] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C2.dat
[08:50:49.719] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C3.dat
[08:50:49.719] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C4.dat
[08:50:49.719] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C5.dat
[08:50:49.719] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C6.dat
[08:50:49.720] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C7.dat
[08:50:49.720] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C8.dat
[08:50:49.720] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C9.dat
[08:50:49.720] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C10.dat
[08:50:49.721] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C11.dat
[08:50:49.721] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C12.dat
[08:50:49.721] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C13.dat
[08:50:49.721] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C14.dat
[08:50:49.721] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters_C15.dat
[08:50:49.722] <TB2> INFO: PixTestPretest::doTest() done, duration: 56 seconds
[08:50:49.833] <TB2> INFO: enter test to run
[08:50:49.833] <TB2> INFO: test: fulltest no parameter change
[08:50:49.833] <TB2> INFO: running: fulltest
[08:50:49.833] <TB2> INFO: ######################################################################
[08:50:49.833] <TB2> INFO: PixTestFullTest::doTest()
[08:50:49.833] <TB2> INFO: ######################################################################
[08:50:49.834] <TB2> INFO: ######################################################################
[08:50:49.834] <TB2> INFO: PixTestAlive::doTest()
[08:50:49.834] <TB2> INFO: ######################################################################
[08:50:49.836] <TB2> INFO: ----------------------------------------------------------------------
[08:50:49.836] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:50:49.836] <TB2> INFO: ----------------------------------------------------------------------
[08:50:53.603] <TB2> INFO: Test took 3766ms.
[08:50:53.625] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:50:53.850] <TB2> INFO: PixTestAlive::aliveTest() done
[08:50:53.850] <TB2> INFO: number of dead pixels (per ROC): 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
[08:50:53.852] <TB2> INFO: ----------------------------------------------------------------------
[08:50:53.852] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:50:53.852] <TB2> INFO: ----------------------------------------------------------------------
[08:50:56.862] <TB2> INFO: Test took 3009ms.
[08:50:56.865] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:50:56.866] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[08:50:57.094] <TB2> INFO: PixTestAlive::maskTest() done
[08:50:57.094] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[08:50:57.096] <TB2> INFO: ----------------------------------------------------------------------
[08:50:57.096] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:50:57.096] <TB2> INFO: ----------------------------------------------------------------------
[08:51:00.749] <TB2> INFO: Test took 3652ms.
[08:51:00.779] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:51:01.008] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[08:51:01.009] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[08:51:01.009] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[08:51:01.022] <TB2> INFO: ######################################################################
[08:51:01.023] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[08:51:01.023] <TB2> INFO: ######################################################################
[08:51:01.025] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (30) hits flags = 2 (plus default)
[08:51:01.036] <TB2> INFO: dacScan step from 0 .. 29
[08:51:24.631] <TB2> INFO: Test took 23594ms.
[08:51:24.660] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:51:24.660] <TB2> INFO: dacScan step from 30 .. 59
[08:51:53.042] <TB2> INFO: Test took 28382ms.
[08:51:53.169] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:51:53.205] <TB2> INFO: dacScan step from 60 .. 89
[08:52:26.792] <TB2> INFO: Test took 33587ms.
[08:52:27.089] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:52:27.165] <TB2> INFO: dacScan step from 90 .. 119
[08:52:58.557] <TB2> INFO: Test took 31392ms.
[08:52:58.952] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:52:59.034] <TB2> INFO: dacScan step from 120 .. 149
[08:53:26.618] <TB2> INFO: Test took 27584ms.
[08:53:26.784] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:53:49.716] <TB2> INFO: PixTestBBMap::doTest() done, duration: 168 seconds
[08:53:49.716] <TB2> INFO: number of dead bumps (per ROC): 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0
[08:53:49.716] <TB2> INFO: separation cut (per ROC): 72 108 99 81 81 74 93 72 80 68 79 90 69 71 66 72
[08:53:49.794] <TB2> INFO: ######################################################################
[08:53:49.794] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50
[08:53:49.794] <TB2> INFO: ######################################################################
[08:53:49.794] <TB2> INFO: ----------------------------------------------------------------------
[08:53:49.794] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50
[08:53:49.794] <TB2> INFO: ----------------------------------------------------------------------
[08:53:49.794] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 0 .. 149 (4) hits flags = 16 (plus default)
[08:53:49.803] <TB2> INFO: dacScan step from 0 .. 3
[08:54:11.235] <TB2> INFO: Test took 21432ms.
[08:54:11.261] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:54:11.261] <TB2> INFO: dacScan step from 4 .. 7
[08:54:32.871] <TB2> INFO: Test took 21610ms.
[08:54:32.895] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:54:32.895] <TB2> INFO: dacScan step from 8 .. 11
[08:54:54.063] <TB2> INFO: Test took 21168ms.
[08:54:54.092] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:54:54.092] <TB2> INFO: dacScan step from 12 .. 15
[08:55:15.713] <TB2> INFO: Test took 21621ms.
[08:55:15.734] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:55:15.739] <TB2> INFO: dacScan step from 16 .. 19
[08:55:37.044] <TB2> INFO: Test took 21305ms.
[08:55:37.077] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:55:37.077] <TB2> INFO: dacScan step from 20 .. 23
[08:55:58.493] <TB2> INFO: Test took 21416ms.
[08:55:58.518] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:55:58.518] <TB2> INFO: dacScan step from 24 .. 27
[08:56:20.089] <TB2> INFO: Test took 21571ms.
[08:56:20.117] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:56:20.117] <TB2> INFO: dacScan step from 28 .. 31
[08:56:41.738] <TB2> INFO: Test took 21621ms.
[08:56:41.766] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:56:41.766] <TB2> INFO: dacScan step from 32 .. 35
[08:57:03.436] <TB2> INFO: Test took 21670ms.
[08:57:03.465] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:57:03.465] <TB2> INFO: dacScan step from 36 .. 39
[08:57:24.900] <TB2> INFO: Test took 21435ms.
[08:57:24.926] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:57:24.926] <TB2> INFO: dacScan step from 40 .. 43
[08:57:46.360] <TB2> INFO: Test took 21434ms.
[08:57:46.385] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:57:46.385] <TB2> INFO: dacScan step from 44 .. 47
[08:58:08.024] <TB2> INFO: Test took 21639ms.
[08:58:08.055] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:58:08.055] <TB2> INFO: dacScan step from 48 .. 51
[08:58:29.542] <TB2> INFO: Test took 21487ms.
[08:58:29.574] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:58:29.574] <TB2> INFO: dacScan step from 52 .. 55
[08:58:50.930] <TB2> INFO: Test took 21356ms.
[08:58:50.959] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:58:50.959] <TB2> INFO: dacScan step from 56 .. 59
[08:59:13.206] <TB2> INFO: Test took 22247ms.
[08:59:13.244] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:59:13.244] <TB2> INFO: dacScan step from 60 .. 63
[08:59:35.540] <TB2> INFO: Test took 22296ms.
[08:59:35.591] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:59:35.592] <TB2> INFO: dacScan step from 64 .. 67
[08:59:58.863] <TB2> INFO: Test took 23270ms.
[08:59:58.932] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:59:58.935] <TB2> INFO: dacScan step from 68 .. 71
[09:00:23.749] <TB2> INFO: Test took 24814ms.
[09:00:23.852] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:00:23.857] <TB2> INFO: dacScan step from 72 .. 75
[09:00:50.804] <TB2> INFO: Test took 26947ms.
[09:00:50.900] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:00:50.905] <TB2> INFO: dacScan step from 76 .. 79
[09:01:20.054] <TB2> INFO: Test took 29149ms.
[09:01:20.181] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:01:20.188] <TB2> INFO: dacScan step from 80 .. 83


[09:01:52.115] <TB2> INFO: Test took 31927ms.
[09:01:52.284] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:01:52.294] <TB2> INFO: dacScan step from 84 .. 87


[09:02:25.677] <TB2> INFO: Test took 33383ms.
[09:02:25.881] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:02:25.890] <TB2> INFO: dacScan step from 88 .. 91





[09:02:59.700] <TB2> INFO: Test took 33810ms.
[09:02:59.924] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:02:59.934] <TB2> INFO: dacScan step from 92 .. 95


[09:03:33.912] <TB2> INFO: Test took 33978ms.
[09:03:34.186] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:03:34.196] <TB2> INFO: dacScan step from 96 .. 99



[09:04:08.042] <TB2> INFO: Test took 33846ms.
[09:04:08.288] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:04:08.299] <TB2> INFO: dacScan step from 100 .. 103



[09:04:42.868] <TB2> INFO: Test took 34569ms.
[09:04:43.104] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:04:43.116] <TB2> INFO: dacScan step from 104 .. 107


[09:05:17.269] <TB2> INFO: Test took 34153ms.
[09:05:17.527] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:05:17.538] <TB2> INFO: dacScan step from 108 .. 111





[09:05:51.281] <TB2> INFO: Test took 33743ms.
[09:05:51.506] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:05:51.516] <TB2> INFO: dacScan step from 112 .. 115
[09:06:25.933] <TB2> INFO: Test took 34416ms.
[09:06:26.151] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:06:26.161] <TB2> INFO: dacScan step from 116 .. 119
[09:06:59.362] <TB2> INFO: Test took 33201ms.
[09:06:59.579] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:06:59.588] <TB2> INFO: dacScan step from 120 .. 123
[09:07:33.667] <TB2> INFO: Test took 34079ms.
[09:07:33.890] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:07:33.901] <TB2> INFO: dacScan step from 124 .. 127
[09:08:05.115] <TB2> INFO: Test took 31214ms.
[09:08:05.330] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:08:05.340] <TB2> INFO: dacScan step from 128 .. 131
[09:08:36.403] <TB2> INFO: Test took 31063ms.
[09:08:36.688] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:08:36.700] <TB2> INFO: dacScan step from 132 .. 135
[09:09:09.659] <TB2> INFO: Test took 32959ms.
[09:09:09.900] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:09:09.909] <TB2> INFO: dacScan step from 136 .. 139
[09:09:44.443] <TB2> INFO: Test took 34534ms.
[09:09:44.726] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:09:44.736] <TB2> INFO: dacScan step from 140 .. 143
[09:10:18.329] <TB2> INFO: Test took 33593ms.
[09:10:18.549] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:10:18.560] <TB2> INFO: dacScan step from 144 .. 147
[09:10:50.261] <TB2> INFO: Test took 31701ms.
[09:10:50.475] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:10:50.486] <TB2> INFO: dacScan step from 148 .. 149
[09:11:08.326] <TB2> INFO: Test took 17840ms.
[09:11:08.434] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:11:08.440] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:11:10.045] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:11:11.487] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:11:12.966] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:11:14.523] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:11:15.937] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:11:17.311] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:11:18.676] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:11:20.087] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:11:21.450] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:11:22.949] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:11:24.413] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:11:25.829] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:11:27.243] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:11:28.655] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:11:30.069] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:11:31.491] <TB2> INFO: PixTestScurves::scurves() done
[09:11:31.491] <TB2> INFO: Vcal mean: 79.58 105.17 91.33 81.88 89.75 85.35 86.13 70.27 87.13 72.76 83.59 84.89 63.40 77.50 74.30 78.46
[09:11:31.491] <TB2> INFO: Vcal RMS: 4.18 6.47 5.41 5.31 5.26 5.24 5.74 4.60 4.77 4.83 5.17 4.92 4.67 4.52 4.14 3.84
[09:11:31.491] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1061 seconds
[09:11:31.563] <TB2> INFO: ######################################################################
[09:11:31.563] <TB2> INFO: PixTestTrim::doTest()
[09:11:31.563] <TB2> INFO: ######################################################################
[09:11:31.564] <TB2> INFO: ----------------------------------------------------------------------
[09:11:31.564] <TB2> INFO: PixTestTrim::trimTest() ntrig = 10, vcal = 35
[09:11:31.564] <TB2> INFO: ----------------------------------------------------------------------
[09:11:31.647] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[09:11:31.647] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 5 dacrange: 0 .. 159 (20) hits flags = 16 (plus default)
[09:11:31.655] <TB2> INFO: dacScan step from 0 .. 19
[09:11:47.940] <TB2> INFO: Test took 16285ms.
[09:11:47.967] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:11:47.967] <TB2> INFO: dacScan step from 20 .. 39
[09:12:04.252] <TB2> INFO: Test took 16285ms.
[09:12:04.277] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:12:04.277] <TB2> INFO: dacScan step from 40 .. 59
[09:12:20.672] <TB2> INFO: Test took 16395ms.
[09:12:20.701] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:12:20.701] <TB2> INFO: dacScan step from 60 .. 79
[09:12:37.251] <TB2> INFO: Test took 16550ms.
[09:12:37.279] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:12:37.280] <TB2> INFO: dacScan step from 80 .. 99
[09:12:56.482] <TB2> INFO: Test took 19202ms.
[09:12:56.573] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:12:56.586] <TB2> INFO: dacScan step from 100 .. 119
[09:13:18.083] <TB2> INFO: Test took 21497ms.
[09:13:18.243] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:13:18.273] <TB2> INFO: dacScan step from 120 .. 139
[09:13:38.853] <TB2> INFO: Test took 20580ms.
[09:13:38.991] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:13:39.014] <TB2> INFO: dacScan step from 140 .. 159
[09:13:56.247] <TB2> INFO: Test took 17233ms.
[09:13:56.340] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:14:19.076] <TB2> INFO: ROC 0 VthrComp = 84
[09:14:19.076] <TB2> INFO: ROC 1 VthrComp = 106
[09:14:19.076] <TB2> INFO: ROC 2 VthrComp = 100
[09:14:19.076] <TB2> INFO: ROC 3 VthrComp = 86
[09:14:19.076] <TB2> INFO: ROC 4 VthrComp = 93
[09:14:19.076] <TB2> INFO: ROC 5 VthrComp = 90
[09:14:19.076] <TB2> INFO: ROC 6 VthrComp = 92
[09:14:19.076] <TB2> INFO: ROC 7 VthrComp = 77
[09:14:19.076] <TB2> INFO: ROC 8 VthrComp = 96
[09:14:19.076] <TB2> INFO: ROC 9 VthrComp = 79
[09:14:19.076] <TB2> INFO: ROC 10 VthrComp = 87
[09:14:19.077] <TB2> INFO: ROC 11 VthrComp = 95
[09:14:19.077] <TB2> INFO: ROC 12 VthrComp = 72
[09:14:19.077] <TB2> INFO: ROC 13 VthrComp = 82
[09:14:19.077] <TB2> INFO: ROC 14 VthrComp = 79
[09:14:19.077] <TB2> INFO: ROC 15 VthrComp = 85
[09:14:19.077] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[09:14:19.077] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 5 dacrange: 0 .. 159 (20) hits flags = 16 (plus default)
[09:14:19.086] <TB2> INFO: dacScan step from 0 .. 19
[09:14:35.616] <TB2> INFO: Test took 16529ms.
[09:14:35.646] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:14:35.647] <TB2> INFO: dacScan step from 20 .. 39
[09:14:52.134] <TB2> INFO: Test took 16487ms.
[09:14:52.175] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:14:52.178] <TB2> INFO: dacScan step from 40 .. 59
[09:15:13.831] <TB2> INFO: Test took 21653ms.
[09:15:13.995] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:15:14.028] <TB2> INFO: dacScan step from 60 .. 79
[09:15:36.735] <TB2> INFO: Test took 22707ms.
[09:15:36.901] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:15:36.935] <TB2> INFO: dacScan step from 80 .. 99
[09:15:59.692] <TB2> INFO: Test took 22756ms.
[09:15:59.846] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:15:59.878] <TB2> INFO: dacScan step from 100 .. 119
[09:16:22.514] <TB2> INFO: Test took 22636ms.
[09:16:22.691] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:16:22.726] <TB2> INFO: dacScan step from 120 .. 139
[09:16:45.116] <TB2> INFO: Test took 22390ms.
[09:16:45.274] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:16:45.308] <TB2> INFO: dacScan step from 140 .. 159
[09:17:08.011] <TB2> INFO: Test took 22703ms.
[09:17:08.186] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:17:36.620] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 57.5832 for pixel 2/1 mean/min/max = 45.2284/32.8488/57.608
[09:17:36.620] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 66.5958 for pixel 0/34 mean/min/max = 50.1817/33.7203/66.6431
[09:17:36.621] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 57.8444 for pixel 0/75 mean/min/max = 44.9488/31.6675/58.23
[09:17:36.621] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 59.4988 for pixel 0/31 mean/min/max = 45.605/31.6237/59.5862
[09:17:36.621] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 58.7012 for pixel 19/68 mean/min/max = 45.375/32.0123/58.7378
[09:17:36.621] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 59.9637 for pixel 2/29 mean/min/max = 46.0787/32.1688/59.9885
[09:17:36.622] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 60.6868 for pixel 0/10 mean/min/max = 46.2939/31.7347/60.8532
[09:17:36.622] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 57.3107 for pixel 26/0 mean/min/max = 45.9062/34.46/57.3523
[09:17:36.622] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 56.4167 for pixel 0/11 mean/min/max = 44.1102/31.7288/56.4916
[09:17:36.623] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 58.8495 for pixel 9/65 mean/min/max = 46.927/34.8585/58.9955
[09:17:36.623] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 58.4338 for pixel 13/78 mean/min/max = 45.3156/32.1634/58.4679
[09:17:36.623] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 56.4335 for pixel 8/79 mean/min/max = 44.4618/32.3343/56.5894
[09:17:36.623] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 55.969 for pixel 15/79 mean/min/max = 44.6183/33.0565/56.1802
[09:17:36.624] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 57.1269 for pixel 2/73 mean/min/max = 44.6022/32.0057/57.1987
[09:17:36.624] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 56.6904 for pixel 21/1 mean/min/max = 45.6686/34.5945/56.7426
[09:17:36.624] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 55.3675 for pixel 23/79 mean/min/max = 44.1034/32.6244/55.5823
[09:17:36.624] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:19:26.412] <TB2> INFO: Test took 109788ms.
[09:19:27.865] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 10 dacrange: 0 .. 199 (20) hits flags = 16 (plus default)
[09:19:27.875] <TB2> INFO: dacScan step from 0 .. 19
[09:19:53.357] <TB2> INFO: Test took 25482ms.
[09:19:53.399] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:19:53.400] <TB2> INFO: dacScan step from 20 .. 39
[09:20:26.361] <TB2> INFO: Test took 32961ms.
[09:20:26.618] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:20:26.654] <TB2> INFO: dacScan step from 40 .. 59
[09:21:02.565] <TB2> INFO: Test took 35911ms.
[09:21:02.869] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:21:02.912] <TB2> INFO: dacScan step from 60 .. 79
[09:21:38.360] <TB2> INFO: Test took 35447ms.
[09:21:38.627] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:21:38.664] <TB2> INFO: dacScan step from 80 .. 99
[09:22:16.329] <TB2> INFO: Test took 37665ms.
[09:22:16.594] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:22:16.631] <TB2> INFO: dacScan step from 100 .. 119
[09:22:53.782] <TB2> INFO: Test took 37151ms.
[09:22:54.060] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:22:54.096] <TB2> INFO: dacScan step from 120 .. 139


[09:23:31.440] <TB2> INFO: Test took 37344ms.
[09:23:31.781] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:23:31.835] <TB2> INFO: dacScan step from 140 .. 159
[09:24:08.165] <TB2> INFO: Test took 36330ms.
[09:24:08.427] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:24:08.464] <TB2> INFO: dacScan step from 160 .. 179
[09:24:44.683] <TB2> INFO: Test took 36219ms.
[09:24:44.969] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:24:45.011] <TB2> INFO: dacScan step from 180 .. 199
[09:25:22.073] <TB2> INFO: Test took 37062ms.
[09:25:22.413] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:25:47.885] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 0.005294 .. 52.866089
[09:25:47.967] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 4 dacrange: 0 .. 62 (20) hits flags = 16 (plus default)
[09:25:47.975] <TB2> INFO: dacScan step from 0 .. 19
[09:26:02.558] <TB2> INFO: Test took 14583ms.
[09:26:02.577] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:26:02.577] <TB2> INFO: dacScan step from 20 .. 39
[09:26:18.971] <TB2> INFO: Test took 16393ms.
[09:26:19.066] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:26:19.085] <TB2> INFO: dacScan step from 40 .. 59
[09:26:38.584] <TB2> INFO: Test took 19499ms.
[09:26:38.750] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:26:38.802] <TB2> INFO: dacScan step from 60 .. 62
[09:26:44.103] <TB2> INFO: Test took 5301ms.
[09:26:44.137] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:27:01.642] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 17.282720 .. 43.500012
[09:27:01.719] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 4 dacrange: 7 .. 53 (20) hits flags = 16 (plus default)
[09:27:01.727] <TB2> INFO: dacScan step from 7 .. 26
[09:27:16.157] <TB2> INFO: Test took 14430ms.
[09:27:16.184] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:27:16.184] <TB2> INFO: dacScan step from 27 .. 46
[09:27:33.241] <TB2> INFO: Test took 17057ms.
[09:27:33.396] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:27:33.429] <TB2> INFO: dacScan step from 47 .. 53
[09:27:41.787] <TB2> INFO: Test took 8357ms.
[09:27:41.836] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:27:58.894] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 20.830282 .. 40.867519
[09:27:59.014] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 4 dacrange: 10 .. 50 (20) hits flags = 16 (plus default)
[09:27:59.025] <TB2> INFO: dacScan step from 10 .. 29
[09:28:12.953] <TB2> INFO: Test took 13928ms.
[09:28:12.973] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:28:12.974] <TB2> INFO: dacScan step from 30 .. 49
[09:28:31.567] <TB2> INFO: Test took 18593ms.
[09:28:31.706] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:28:31.739] <TB2> INFO: dacScan step from 50 .. 50
[09:28:35.527] <TB2> INFO: Test took 3788ms.
[09:28:35.544] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:28:52.118] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 24.580434 .. 40.867519
[09:28:52.206] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 4 dacrange: 14 .. 50 (20) hits flags = 16 (plus default)
[09:28:52.214] <TB2> INFO: dacScan step from 14 .. 33
[09:29:07.000] <TB2> INFO: Test took 14786ms.
[09:29:07.033] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:29:07.037] <TB2> INFO: dacScan step from 34 .. 50
[09:29:23.912] <TB2> INFO: Test took 16875ms.
[09:29:24.037] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:29:40.208] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[09:29:40.208] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 10 dacrange: 15 .. 55 (20) hits flags = 16 (plus default)
[09:29:40.216] <TB2> INFO: dacScan step from 15 .. 34
[09:30:06.992] <TB2> INFO: Test took 26776ms.
[09:30:07.064] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:30:07.076] <TB2> INFO: dacScan step from 35 .. 54


[09:30:44.536] <TB2> INFO: Test took 37460ms.
[09:30:44.826] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:30:44.868] <TB2> INFO: dacScan step from 55 .. 55
[09:30:49.544] <TB2> INFO: Test took 4675ms.
[09:30:49.570] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:31:03.182] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C0.dat
[09:31:03.182] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C1.dat
[09:31:03.182] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C2.dat
[09:31:03.182] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C3.dat
[09:31:03.182] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C4.dat
[09:31:03.183] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C5.dat
[09:31:03.183] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C6.dat
[09:31:03.183] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C7.dat
[09:31:03.183] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C8.dat
[09:31:03.183] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C9.dat
[09:31:03.183] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C10.dat
[09:31:03.183] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C11.dat
[09:31:03.184] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C12.dat
[09:31:03.184] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C13.dat
[09:31:03.184] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C14.dat
[09:31:03.184] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C15.dat
[09:31:03.184] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters35_C0.dat
[09:31:03.191] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters35_C1.dat
[09:31:03.197] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters35_C2.dat
[09:31:03.203] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters35_C3.dat
[09:31:03.209] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters35_C4.dat
[09:31:03.216] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters35_C5.dat
[09:31:03.222] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters35_C6.dat
[09:31:03.228] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters35_C7.dat
[09:31:03.235] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters35_C8.dat
[09:31:03.242] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters35_C9.dat
[09:31:03.249] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters35_C10.dat
[09:31:03.255] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters35_C11.dat
[09:31:03.263] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters35_C12.dat
[09:31:03.270] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters35_C13.dat
[09:31:03.277] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters35_C14.dat
[09:31:03.284] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//trimParameters35_C15.dat
[09:31:03.291] <TB2> INFO: PixTestTrim::trimTest() done
[09:31:03.291] <TB2> INFO: vtrim: 96 139 119 111 117 117 119 104 107 117 112 102 90 110 106 100
[09:31:03.291] <TB2> INFO: vthrcomp: 84 106 100 86 93 90 92 77 96 79 87 95 72 82 79 85
[09:31:03.291] <TB2> INFO: vcal mean: 35.04 35.09 34.96 35.00 35.04 35.14 35.06 35.06 35.03 35.01 35.03 35.04 35.01 35.05 35.04 35.00
[09:31:03.291] <TB2> INFO: vcal RMS: 1.00 1.22 1.00 1.14 1.08 1.05 1.01 0.92 1.00 0.97 1.07 0.97 0.92 1.10 0.92 1.00
[09:31:03.291] <TB2> INFO: bits mean: 9.68 8.78 9.89 9.50 10.15 9.84 9.54 9.15 10.25 9.23 9.98 9.98 9.72 10.33 9.44 9.92
[09:31:03.291] <TB2> INFO: bits RMS: 2.53 2.45 2.60 2.77 2.36 2.51 2.66 2.49 2.49 2.33 2.44 2.52 2.53 2.36 2.33 2.54
[09:31:03.298] <TB2> INFO: ----------------------------------------------------------------------
[09:31:03.298] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 10, vtrims = 254 126 63 32
[09:31:03.298] <TB2> INFO: ----------------------------------------------------------------------
[09:31:03.301] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 10 dacrange: 0 .. 199 (20) hits flags = 16 (plus default)
[09:31:03.309] <TB2> INFO: dacScan step from 0 .. 19
[09:31:28.934] <TB2> INFO: Test took 25625ms.
[09:31:28.971] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:31:28.971] <TB2> INFO: dacScan step from 20 .. 39
[09:31:54.558] <TB2> INFO: Test took 25587ms.
[09:31:54.603] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:31:54.603] <TB2> INFO: dacScan step from 40 .. 59
[09:32:19.752] <TB2> INFO: Test took 25149ms.
[09:32:19.791] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:32:19.791] <TB2> INFO: dacScan step from 60 .. 79
[09:32:43.964] <TB2> INFO: Test took 24173ms.
[09:32:44.012] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:32:44.012] <TB2> INFO: dacScan step from 80 .. 99
[09:33:12.180] <TB2> INFO: Test took 28168ms.
[09:33:12.286] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:33:12.293] <TB2> INFO: dacScan step from 100 .. 119



[09:33:48.481] <TB2> INFO: Test took 36188ms.
[09:33:48.752] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:33:48.778] <TB2> INFO: dacScan step from 120 .. 139
[09:34:25.920] <TB2> INFO: Test took 37142ms.
[09:34:26.372] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:34:26.435] <TB2> INFO: dacScan step from 140 .. 159
[09:35:02.589] <TB2> INFO: Test took 36154ms.
[09:35:02.880] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:35:02.916] <TB2> INFO: dacScan step from 160 .. 179
[09:35:39.880] <TB2> INFO: Test took 36964ms.
[09:35:40.179] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:35:40.227] <TB2> INFO: dacScan step from 180 .. 199
[09:36:16.688] <TB2> INFO: Test took 36461ms.
[09:36:16.937] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:36:43.884] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 10 dacrange: 0 .. 177 (20) hits flags = 16 (plus default)
[09:36:43.894] <TB2> INFO: dacScan step from 0 .. 19
[09:37:08.979] <TB2> INFO: Test took 25085ms.
[09:37:09.019] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:37:09.019] <TB2> INFO: dacScan step from 20 .. 39
[09:37:34.177] <TB2> INFO: Test took 25158ms.
[09:37:34.211] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:37:34.211] <TB2> INFO: dacScan step from 40 .. 59
[09:37:57.837] <TB2> INFO: Test took 23626ms.
[09:37:57.876] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:37:57.876] <TB2> INFO: dacScan step from 60 .. 79
[09:38:23.105] <TB2> INFO: Test took 25229ms.
[09:38:23.157] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:38:23.159] <TB2> INFO: dacScan step from 80 .. 99
[09:38:53.066] <TB2> INFO: Test took 29907ms.
[09:38:53.226] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:38:53.247] <TB2> INFO: dacScan step from 100 .. 119


[09:39:31.578] <TB2> INFO: Test took 38332ms.
[09:39:31.868] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:39:31.904] <TB2> INFO: dacScan step from 120 .. 139


[09:40:08.951] <TB2> INFO: Test took 37047ms.
[09:40:09.224] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:40:09.262] <TB2> INFO: dacScan step from 140 .. 159
[09:40:45.719] <TB2> INFO: Test took 36457ms.
[09:40:46.047] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:40:46.094] <TB2> INFO: dacScan step from 160 .. 177
[09:41:20.559] <TB2> INFO: Test took 34465ms.
[09:41:20.823] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:41:46.616] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 10 dacrange: 0 .. 164 (20) hits flags = 16 (plus default)
[09:41:46.624] <TB2> INFO: dacScan step from 0 .. 19
[09:42:11.868] <TB2> INFO: Test took 25244ms.
[09:42:11.902] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:42:11.902] <TB2> INFO: dacScan step from 20 .. 39
[09:42:35.809] <TB2> INFO: Test took 23906ms.
[09:42:35.846] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:42:35.846] <TB2> INFO: dacScan step from 40 .. 59
[09:42:59.786] <TB2> INFO: Test took 23940ms.
[09:42:59.819] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:42:59.819] <TB2> INFO: dacScan step from 60 .. 79
[09:43:25.327] <TB2> INFO: Test took 25508ms.
[09:43:25.379] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:43:25.380] <TB2> INFO: dacScan step from 80 .. 99
[09:43:57.579] <TB2> INFO: Test took 32199ms.
[09:43:57.740] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:43:57.758] <TB2> INFO: dacScan step from 100 .. 119



[09:44:34.221] <TB2> INFO: Test took 36462ms.
[09:44:34.533] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:44:34.564] <TB2> INFO: dacScan step from 120 .. 139


[09:45:12.738] <TB2> INFO: Test took 38174ms.
[09:45:13.040] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:45:13.075] <TB2> INFO: dacScan step from 140 .. 159
[09:45:50.309] <TB2> INFO: Test took 37234ms.
[09:45:50.647] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:45:50.685] <TB2> INFO: dacScan step from 160 .. 164
[09:46:02.014] <TB2> INFO: Test took 11329ms.
[09:46:02.085] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:46:26.764] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 10 dacrange: 0 .. 164 (20) hits flags = 16 (plus default)
[09:46:26.772] <TB2> INFO: dacScan step from 0 .. 19
[09:46:50.783] <TB2> INFO: Test took 24011ms.
[09:46:50.816] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:46:50.816] <TB2> INFO: dacScan step from 20 .. 39
[09:47:14.860] <TB2> INFO: Test took 24044ms.
[09:47:14.894] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:47:14.894] <TB2> INFO: dacScan step from 40 .. 59
[09:47:39.862] <TB2> INFO: Test took 24968ms.
[09:47:39.900] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:47:39.900] <TB2> INFO: dacScan step from 60 .. 79
[09:48:04.389] <TB2> INFO: Test took 24489ms.
[09:48:04.437] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:48:04.438] <TB2> INFO: dacScan step from 80 .. 99
[09:48:36.847] <TB2> INFO: Test took 32408ms.
[09:48:37.010] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:48:37.026] <TB2> INFO: dacScan step from 100 .. 119


[09:49:14.881] <TB2> INFO: Test took 37855ms.
[09:49:15.167] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:49:15.200] <TB2> INFO: dacScan step from 120 .. 139


[09:49:52.686] <TB2> INFO: Test took 37486ms.
[09:49:53.015] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:49:53.056] <TB2> INFO: dacScan step from 140 .. 159
[09:50:29.501] <TB2> INFO: Test took 36445ms.
[09:50:29.823] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:50:29.867] <TB2> INFO: dacScan step from 160 .. 164
[09:50:40.726] <TB2> INFO: Test took 10859ms.
[09:50:40.791] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:51:05.851] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 10 dacrange: 0 .. 164 (20) hits flags = 16 (plus default)
[09:51:05.864] <TB2> INFO: dacScan step from 0 .. 19
[09:51:31.178] <TB2> INFO: Test took 25314ms.
[09:51:31.215] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:51:31.215] <TB2> INFO: dacScan step from 20 .. 39
[09:51:55.088] <TB2> INFO: Test took 23873ms.
[09:51:55.130] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:51:55.130] <TB2> INFO: dacScan step from 40 .. 59
[09:52:20.318] <TB2> INFO: Test took 25188ms.
[09:52:20.356] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:52:20.356] <TB2> INFO: dacScan step from 60 .. 79
[09:52:46.344] <TB2> INFO: Test took 25988ms.
[09:52:46.406] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:52:46.407] <TB2> INFO: dacScan step from 80 .. 99
[09:53:18.995] <TB2> INFO: Test took 32587ms.
[09:53:19.163] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:53:19.181] <TB2> INFO: dacScan step from 100 .. 119





[09:53:57.584] <TB2> INFO: Test took 38403ms.
[09:53:57.882] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:53:57.915] <TB2> INFO: dacScan step from 120 .. 139


[09:54:35.373] <TB2> INFO: Test took 37458ms.
[09:54:35.662] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:54:35.702] <TB2> INFO: dacScan step from 140 .. 159
[09:55:13.714] <TB2> INFO: Test took 38012ms.
[09:55:13.992] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:55:14.031] <TB2> INFO: dacScan step from 160 .. 164
[09:55:25.563] <TB2> INFO: Test took 11532ms.
[09:55:25.635] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:55:49.908] <TB2> INFO: PixTestTrim::trimBitTest() done
[09:55:49.910] <TB2> INFO: PixTestTrim::doTest() done, duration: 2658 seconds
[09:55:50.608] <TB2> INFO: ######################################################################
[09:55:50.608] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[09:55:50.608] <TB2> INFO: ######################################################################
[09:55:54.333] <TB2> INFO: Test took 3724ms.
[09:55:54.357] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:55:58.217] <TB2> INFO: Test took 3663ms.
[09:55:58.288] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:56:01.953] <TB2> INFO: Test took 3652ms.
[09:56:02.015] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:56:02.022] <TB2> INFO: The DUT currently contains the following objects:
[09:56:02.022] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:56:02.022] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:56:02.022] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:56:02.022] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:56:02.022] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:02.022] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:02.022] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:02.022] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:02.022] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:02.022] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:02.022] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:02.022] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:02.022] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:02.022] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:02.022] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:02.022] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:02.022] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:02.022] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:02.022] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:02.022] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:03.129] <TB2> INFO: Test took 1107ms.
[09:56:03.130] <TB2> INFO: The DUT currently contains the following objects:
[09:56:03.130] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:56:03.130] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:56:03.130] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:56:03.130] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:56:03.130] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:03.130] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:03.130] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:03.130] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:03.130] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:03.130] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:03.130] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:03.130] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:03.130] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:03.130] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:03.130] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:03.130] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:03.130] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:03.131] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:03.131] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:03.131] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:04.252] <TB2> INFO: Test took 1121ms.
[09:56:04.253] <TB2> INFO: The DUT currently contains the following objects:
[09:56:04.253] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:56:04.253] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:56:04.253] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:56:04.254] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:56:04.254] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:04.254] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:04.254] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:04.254] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:04.254] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:04.254] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:04.254] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:04.254] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:04.254] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:04.254] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:04.254] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:04.254] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:04.254] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:04.254] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:04.254] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:04.254] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:05.401] <TB2> INFO: Test took 1147ms.
[09:56:05.402] <TB2> INFO: The DUT currently contains the following objects:
[09:56:05.402] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:56:05.402] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:56:05.402] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:56:05.402] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:56:05.403] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:05.403] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:05.403] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:05.403] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:05.403] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:05.403] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:05.403] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:05.403] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:05.403] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:05.403] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:05.403] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:05.403] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:05.403] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:05.403] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:05.403] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:05.403] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:06.540] <TB2> INFO: Test took 1137ms.
[09:56:06.541] <TB2> INFO: The DUT currently contains the following objects:
[09:56:06.541] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:56:06.541] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:56:06.541] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:56:06.541] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:56:06.541] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:06.541] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:06.541] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:06.541] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:06.541] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:06.541] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:06.542] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:06.542] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:06.542] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:06.542] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:06.542] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:06.542] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:06.542] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:06.542] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:06.542] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:06.542] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:07.662] <TB2> INFO: Test took 1120ms.
[09:56:07.663] <TB2> INFO: The DUT currently contains the following objects:
[09:56:07.663] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:56:07.663] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:56:07.663] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:56:07.664] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:56:07.664] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:07.664] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:07.664] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:07.664] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:07.664] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:07.664] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:07.664] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:07.664] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:07.664] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:07.664] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:07.664] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:07.664] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:07.664] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:07.664] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:07.664] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:07.664] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:08.786] <TB2> INFO: Test took 1122ms.
[09:56:08.787] <TB2> INFO: The DUT currently contains the following objects:
[09:56:08.787] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:56:08.787] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:56:08.787] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:56:08.787] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:56:08.787] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:08.787] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:08.787] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:08.787] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:08.787] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:08.787] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:08.787] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:08.787] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:08.787] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:08.788] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:08.788] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:08.788] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:08.788] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:08.788] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:08.788] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:08.788] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:09.909] <TB2> INFO: Test took 1121ms.
[09:56:09.910] <TB2> INFO: The DUT currently contains the following objects:
[09:56:09.910] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:56:09.910] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:56:09.911] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:56:09.911] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:56:09.911] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:09.911] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:09.911] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:09.911] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:09.911] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:09.911] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:09.911] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:09.911] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:09.911] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:09.911] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:09.911] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:09.911] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:09.911] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:09.911] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:09.911] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:09.911] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:11.027] <TB2> INFO: Test took 1116ms.
[09:56:11.028] <TB2> INFO: The DUT currently contains the following objects:
[09:56:11.028] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:56:11.028] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:56:11.028] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:56:11.028] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:56:11.028] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:11.028] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:11.028] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:11.028] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:11.028] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:11.028] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:11.028] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:11.028] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:11.028] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:11.028] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:11.028] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:11.029] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:11.029] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:11.029] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:11.029] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:11.029] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:12.130] <TB2> INFO: Test took 1101ms.
[09:56:12.131] <TB2> INFO: The DUT currently contains the following objects:
[09:56:12.131] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:56:12.131] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:56:12.131] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:56:12.131] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:56:12.131] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:12.131] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:12.131] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:12.131] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:12.131] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:12.131] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:12.131] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:12.131] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:12.131] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:12.131] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:12.131] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:12.131] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:12.131] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:12.131] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:12.131] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:12.131] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:13.252] <TB2> INFO: Test took 1121ms.
[09:56:13.253] <TB2> INFO: The DUT currently contains the following objects:
[09:56:13.253] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:56:13.253] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:56:13.253] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:56:13.253] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:56:13.253] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:13.253] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:13.253] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:13.253] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:13.253] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:13.253] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:13.253] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:13.253] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:13.253] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:13.253] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:13.253] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:13.254] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:13.254] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:13.254] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:13.254] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:13.254] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:14.373] <TB2> INFO: Test took 1119ms.
[09:56:14.374] <TB2> INFO: The DUT currently contains the following objects:
[09:56:14.374] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:56:14.374] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:56:14.374] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:56:14.374] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:56:14.374] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:14.374] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:14.374] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:14.374] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:14.374] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:14.374] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:14.374] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:14.374] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:14.374] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:14.374] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:14.374] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:14.374] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:14.374] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:14.374] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:14.374] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:14.374] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:15.483] <TB2> INFO: Test took 1109ms.
[09:56:15.484] <TB2> INFO: The DUT currently contains the following objects:
[09:56:15.484] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:56:15.484] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:56:15.484] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:56:15.485] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:56:15.485] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:15.485] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:15.485] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:15.485] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:15.485] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:15.485] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:15.485] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:15.485] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:15.485] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:15.485] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:15.485] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:15.485] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:15.485] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:15.485] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:15.485] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:15.485] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:16.591] <TB2> INFO: Test took 1106ms.
[09:56:16.591] <TB2> INFO: The DUT currently contains the following objects:
[09:56:16.591] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:56:16.591] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:56:16.591] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:56:16.591] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:56:16.591] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:16.591] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:16.591] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:16.592] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:16.592] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:16.592] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:16.592] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:16.592] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:16.592] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:16.592] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:16.592] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:16.592] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:16.592] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:16.592] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:16.592] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:16.592] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:17.738] <TB2> INFO: Test took 1146ms.
[09:56:17.738] <TB2> INFO: The DUT currently contains the following objects:
[09:56:17.738] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:56:17.738] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:56:17.738] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:56:17.738] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:56:17.738] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:17.738] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:17.738] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:17.738] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:17.738] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:17.738] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:17.738] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:17.738] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:17.738] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:17.738] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:17.738] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:17.738] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:17.738] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:17.738] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:17.738] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:17.739] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:18.843] <TB2> INFO: Test took 1104ms.
[09:56:18.843] <TB2> INFO: The DUT currently contains the following objects:
[09:56:18.843] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[09:56:18.843] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:56:18.843] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:56:18.843] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:56:18.843] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:18.843] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:18.843] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:18.843] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:18.843] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:18.843] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:18.843] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:18.843] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:18.843] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:18.843] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:18.843] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:18.843] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:18.843] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:18.843] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:18.843] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:18.843] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:56:19.950] <TB2> INFO: Test took 1107ms.
[09:56:19.954] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:00:47.915] <TB2> INFO: Test took 267961ms.
[10:00:49.767] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:02.233] <TB2> INFO: Test took 252466ms.
[10:05:03.800] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:05:03.807] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:05:03.813] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:05:03.820] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:05:03.826] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:05:03.833] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:05:03.839] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:05:03.845] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:05:03.852] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:05:03.858] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:05:03.865] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:05:03.872] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:05:03.878] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:05:03.885] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:05:03.891] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:05:03.897] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[10:05:03.942] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C0.dat
[10:05:03.943] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C1.dat
[10:05:03.943] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C2.dat
[10:05:03.943] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C3.dat
[10:05:03.949] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C4.dat
[10:05:03.949] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C5.dat
[10:05:03.950] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C6.dat
[10:05:03.959] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C7.dat
[10:05:03.960] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C8.dat
[10:05:03.964] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C9.dat
[10:05:03.965] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C10.dat
[10:05:03.970] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C11.dat
[10:05:03.971] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C12.dat
[10:05:03.971] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C13.dat
[10:05:03.971] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C14.dat
[10:05:03.971] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//dacParameters35_C15.dat
[10:05:07.586] <TB2> INFO: Test took 3612ms.
[10:05:11.389] <TB2> INFO: Test took 3540ms.
[10:05:15.223] <TB2> INFO: Test took 3573ms.
[10:05:15.489] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:16.401] <TB2> INFO: Test took 912ms.
[10:05:16.403] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:17.505] <TB2> INFO: Test took 1102ms.
[10:05:17.507] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:18.608] <TB2> INFO: Test took 1101ms.
[10:05:18.610] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:19.711] <TB2> INFO: Test took 1101ms.
[10:05:19.713] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:20.814] <TB2> INFO: Test took 1101ms.
[10:05:20.816] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:21.918] <TB2> INFO: Test took 1102ms.
[10:05:21.920] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:23.051] <TB2> INFO: Test took 1131ms.
[10:05:23.053] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:24.169] <TB2> INFO: Test took 1116ms.
[10:05:24.171] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:25.286] <TB2> INFO: Test took 1115ms.
[10:05:25.288] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:26.419] <TB2> INFO: Test took 1131ms.
[10:05:26.421] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:27.537] <TB2> INFO: Test took 1116ms.
[10:05:27.539] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:28.669] <TB2> INFO: Test took 1130ms.
[10:05:28.671] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:29.787] <TB2> INFO: Test took 1116ms.
[10:05:29.789] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:30.889] <TB2> INFO: Test took 1100ms.
[10:05:30.891] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:32.006] <TB2> INFO: Test took 1115ms.
[10:05:32.008] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:33.123] <TB2> INFO: Test took 1115ms.
[10:05:33.125] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:34.225] <TB2> INFO: Test took 1100ms.
[10:05:34.227] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:35.327] <TB2> INFO: Test took 1100ms.
[10:05:35.329] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:36.444] <TB2> INFO: Test took 1115ms.
[10:05:36.446] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:37.560] <TB2> INFO: Test took 1114ms.
[10:05:37.562] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:38.691] <TB2> INFO: Test took 1129ms.
[10:05:38.693] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:39.821] <TB2> INFO: Test took 1128ms.
[10:05:39.823] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:40.923] <TB2> INFO: Test took 1100ms.
[10:05:40.925] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:42.040] <TB2> INFO: Test took 1115ms.
[10:05:42.042] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:43.142] <TB2> INFO: Test took 1100ms.
[10:05:43.144] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:44.244] <TB2> INFO: Test took 1100ms.
[10:05:44.246] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:45.360] <TB2> INFO: Test took 1114ms.
[10:05:45.362] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:46.492] <TB2> INFO: Test took 1130ms.
[10:05:46.494] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:47.608] <TB2> INFO: Test took 1114ms.
[10:05:47.610] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:48.739] <TB2> INFO: Test took 1129ms.
[10:05:48.741] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:49.842] <TB2> INFO: Test took 1101ms.
[10:05:49.844] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:05:50.975] <TB2> INFO: Test took 1131ms.
[10:05:51.493] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 600 seconds
[10:05:51.493] <TB2> INFO: PH scale (per ROC): 90 93 93 90 76 89 86 93 81 98 82 91 99 71 95 92
[10:05:51.493] <TB2> INFO: PH offset (per ROC): 162 157 160 147 166 162 158 146 157 127 150 164 129 154 137 134
[10:05:51.671] <TB2> INFO: ######################################################################
[10:05:51.671] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[10:05:51.671] <TB2> INFO: ######################################################################
[10:05:51.680] <TB2> INFO: scanning low vcal = 10
[10:05:55.601] <TB2> INFO: Test took 3921ms.
[10:05:55.604] <TB2> INFO: scanning low vcal = 20
[10:05:59.531] <TB2> INFO: Test took 3927ms.
[10:05:59.533] <TB2> INFO: scanning low vcal = 30
[10:06:03.431] <TB2> INFO: Test took 3898ms.
[10:06:03.436] <TB2> INFO: scanning low vcal = 40
[10:06:08.013] <TB2> INFO: Test took 4577ms.
[10:06:08.066] <TB2> INFO: scanning low vcal = 50
[10:06:12.569] <TB2> INFO: Test took 4503ms.
[10:06:12.623] <TB2> INFO: scanning low vcal = 60
[10:06:17.183] <TB2> INFO: Test took 4560ms.
[10:06:17.236] <TB2> INFO: scanning low vcal = 70
[10:06:21.854] <TB2> INFO: Test took 4618ms.
[10:06:21.908] <TB2> INFO: scanning low vcal = 80
[10:06:26.440] <TB2> INFO: Test took 4532ms.
[10:06:26.493] <TB2> INFO: scanning low vcal = 90
[10:06:30.940] <TB2> INFO: Test took 4447ms.
[10:06:30.994] <TB2> INFO: scanning low vcal = 100
[10:06:35.449] <TB2> INFO: Test took 4455ms.
[10:06:35.503] <TB2> INFO: scanning low vcal = 110
[10:06:39.979] <TB2> INFO: Test took 4476ms.
[10:06:40.033] <TB2> INFO: scanning low vcal = 120
[10:06:44.493] <TB2> INFO: Test took 4460ms.
[10:06:44.546] <TB2> INFO: scanning low vcal = 130
[10:06:49.092] <TB2> INFO: Test took 4546ms.
[10:06:49.145] <TB2> INFO: scanning low vcal = 140
[10:06:53.521] <TB2> INFO: Test took 4376ms.
[10:06:53.574] <TB2> INFO: scanning low vcal = 150
[10:06:58.002] <TB2> INFO: Test took 4428ms.
[10:06:58.058] <TB2> INFO: scanning low vcal = 160
[10:07:02.533] <TB2> INFO: Test took 4475ms.
[10:07:02.586] <TB2> INFO: scanning low vcal = 170
[10:07:07.103] <TB2> INFO: Test took 4517ms.
[10:07:07.157] <TB2> INFO: scanning low vcal = 180
[10:07:11.577] <TB2> INFO: Test took 4420ms.
[10:07:11.631] <TB2> INFO: scanning low vcal = 190
[10:07:16.220] <TB2> INFO: Test took 4589ms.
[10:07:16.274] <TB2> INFO: scanning low vcal = 200
[10:07:20.780] <TB2> INFO: Test took 4506ms.
[10:07:20.834] <TB2> INFO: scanning low vcal = 210
[10:07:25.343] <TB2> INFO: Test took 4509ms.
[10:07:25.396] <TB2> INFO: scanning low vcal = 220
[10:07:29.800] <TB2> INFO: Test took 4404ms.
[10:07:29.853] <TB2> INFO: scanning low vcal = 230
[10:07:34.282] <TB2> INFO: Test took 4429ms.
[10:07:34.336] <TB2> INFO: scanning low vcal = 240
[10:07:38.767] <TB2> INFO: Test took 4431ms.
[10:07:38.821] <TB2> INFO: scanning low vcal = 250
[10:07:43.254] <TB2> INFO: Test took 4433ms.
[10:07:43.308] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[10:07:47.800] <TB2> INFO: Test took 4492ms.
[10:07:47.855] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[10:07:52.351] <TB2> INFO: Test took 4496ms.
[10:07:52.404] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[10:07:56.832] <TB2> INFO: Test took 4428ms.
[10:07:56.886] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[10:08:01.429] <TB2> INFO: Test took 4543ms.
[10:08:01.484] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[10:08:05.876] <TB2> INFO: Test took 4392ms.
[10:08:06.355] <TB2> INFO: PixTestGainPedestal::measure() done
[10:08:36.463] <TB2> INFO: PixTestGainPedestal::fit() done
[10:08:36.463] <TB2> INFO: non-linearity mean: 0.948 0.957 0.951 0.950 0.950 0.954 0.947 0.961 0.953 0.955 0.950 0.951 0.952 0.948 0.956 0.956
[10:08:36.463] <TB2> INFO: non-linearity RMS: 0.007 0.005 0.006 0.006 0.008 0.006 0.006 0.006 0.006 0.005 0.007 0.007 0.006 0.007 0.006 0.006
[10:08:36.463] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//phCalibrationFitErr35_C0.dat
[10:08:36.480] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//phCalibrationFitErr35_C1.dat
[10:08:36.497] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//phCalibrationFitErr35_C2.dat
[10:08:36.515] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//phCalibrationFitErr35_C3.dat
[10:08:36.532] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//phCalibrationFitErr35_C4.dat
[10:08:36.549] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//phCalibrationFitErr35_C5.dat
[10:08:36.566] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//phCalibrationFitErr35_C6.dat
[10:08:36.583] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//phCalibrationFitErr35_C7.dat
[10:08:36.601] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//phCalibrationFitErr35_C8.dat
[10:08:36.618] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//phCalibrationFitErr35_C9.dat
[10:08:36.635] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//phCalibrationFitErr35_C10.dat
[10:08:36.652] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//phCalibrationFitErr35_C11.dat
[10:08:36.670] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//phCalibrationFitErr35_C12.dat
[10:08:36.687] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//phCalibrationFitErr35_C13.dat
[10:08:36.705] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//phCalibrationFitErr35_C14.dat
[10:08:36.723] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2048_FullQualification_2015-07-24_10h42m_1437727338//000_FulltestPxar_m20//phCalibrationFitErr35_C15.dat
[10:08:36.740] <TB2> INFO: PixTestGainPedestal::doTest() done, duration: 165 seconds
[10:08:36.746] <TB2> INFO: enter test to run
[10:08:36.746] <TB2> INFO: test: exit no parameter change
[10:08:37.258] <TB2> QUIET: Connection to board 156 closed.
[10:08:37.338] <TB2> INFO: pXar: this is the end, my friend