[15:44:05.177] <TB1> INFO: *** Welcome to pxar ***
[15:44:05.177] <TB1> INFO: *** Today: 2015/10/30
[15:44:05.192] <TB1> INFO: *** Version: 9da6-dirty
[15:44:05.192] <TB1> INFO: readRocDacs: /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C0.dat .. /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C15.dat
[15:44:05.193] <TB1> INFO: readTbmDacs: /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//tbmParameters_C0a.dat .. /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//tbmParameters_C0b.dat
[15:44:05.194] <TB1> INFO: readMaskFile: /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//defaultMaskFile.dat
[15:44:05.196] <TB1> INFO: readTrimFile: /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters_C0.dat .. /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters_C15.dat
[15:44:05.370] <TB1> INFO: clk: 4
[15:44:05.370] <TB1> INFO: ctr: 4
[15:44:05.370] <TB1> INFO: sda: 19
[15:44:05.370] <TB1> INFO: tin: 9
[15:44:05.370] <TB1> INFO: level: 15
[15:44:05.370] <TB1> INFO: triggerdelay: 0
[15:44:05.370] <TB1> QUIET: Instanciating API for pxar prod-11
[15:44:05.370] <TB1> INFO: Log level: INFO
[15:44:05.378] <TB1> INFO: Found DTB DTB_WWVH60
[15:44:05.388] <TB1> QUIET: Connection to board DTB_WWVH60 opened.
[15:44:05.394] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 129
HW version: DTB1.2
FW version: 4.2
SW version: 4.4
USB id: DTB_WWVH60
MAC address: 40D855118081
Hostname: pixelDTB129
Comment:
------------------------------------------------------
[15:44:05.397] <TB1> INFO: RPC call hashes of host and DTB match: 397073690
[15:44:07.011] <TB1> INFO: DUT info:
[15:44:07.011] <TB1> INFO: The DUT currently contains the following objects:
[15:44:07.011] <TB1> INFO: 2 TBM Cores tbm08c (2 ON)
[15:44:07.011] <TB1> INFO: TBM Core alpha (0): 7 registers set
[15:44:07.011] <TB1> INFO: TBM Core beta (1): 7 registers set
[15:44:07.011] <TB1> INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[15:44:07.011] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[15:44:07.011] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[15:44:07.011] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[15:44:07.011] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[15:44:07.011] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[15:44:07.011] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[15:44:07.011] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[15:44:07.011] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[15:44:07.012] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[15:44:07.012] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[15:44:07.012] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[15:44:07.012] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[15:44:07.012] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[15:44:07.012] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[15:44:07.012] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[15:44:07.012] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[15:44:07.415] <TB1> INFO: enter 'restricted' command line mode
[15:44:07.415] <TB1> INFO: enter test to run
[15:44:07.415] <TB1> INFO: test: FullTest no parameter change
[15:44:07.415] <TB1> INFO: running: fulltest
[15:44:07.420] <TB1> INFO: ######################################################################
[15:44:07.420] <TB1> INFO: PixTestFullTest::doTest()
[15:44:07.420] <TB1> INFO: ######################################################################
[15:44:07.423] <TB1> INFO: ######################################################################
[15:44:07.423] <TB1> INFO: PixTestPretest::doTest()
[15:44:07.424] <TB1> INFO: ######################################################################
[15:44:07.425] <TB1> INFO: ----------------------------------------------------------------------
[15:44:07.425] <TB1> INFO: PixTestPretest::programROC()
[15:44:07.425] <TB1> INFO: ----------------------------------------------------------------------
[15:44:25.456] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[15:44:25.456] <TB1> INFO: IA differences per ROC: 16.1 18.5 16.9 16.9 19.3 16.1 18.5 16.9 18.5 17.7 18.5 19.3 17.7 18.5 21.7 18.5
[15:44:25.531] <TB1> INFO: ----------------------------------------------------------------------
[15:44:25.531] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[15:44:25.531] <TB1> INFO: ----------------------------------------------------------------------
[15:44:45.125] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 385.1 mA = 24.0688 mA/ROC
[15:44:45.129] <TB1> INFO: ----------------------------------------------------------------------
[15:44:45.129] <TB1> INFO: PixTestPretest::findTiming()
[15:44:45.129] <TB1> INFO: ----------------------------------------------------------------------
[15:44:45.130] <TB1> INFO: PixTestCmd::init()
[15:44:45.763] <TB1> WARNING: Not unmasking DUT, not setting Calibrate bits!
[15:46:18.259] <TB1> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[15:46:18.259] <TB1> INFO: (success/tries = 100/100), width = 4
[15:46:18.261] <TB1> INFO: ----------------------------------------------------------------------
[15:46:18.261] <TB1> INFO: PixTestPretest::findWorkingPixel()
[15:46:18.261] <TB1> INFO: ----------------------------------------------------------------------
[15:46:18.404] <TB1> INFO: Expecting 231680 events.
[15:46:23.600] <TB1> ERROR: <datapipe.cc/CheckEventValidity:L484> Channel 0 Number of ROCs (1) != Token Chain Length (8)
[15:46:23.603] <TB1> ERROR: <datapipe.cc/CheckEventID:L457> Channel 0 Event ID mismatch: local ID (21) != TBM ID (2)
[15:46:26.437] <TB1> INFO: 231680 events read in total (7255ms).
[15:46:26.450] <TB1> INFO: Test took 8184ms.
[15:46:26.903] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[15:46:26.940] <TB1> INFO: ----------------------------------------------------------------------
[15:46:26.941] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[15:46:26.941] <TB1> INFO: ----------------------------------------------------------------------
[15:46:27.089] <TB1> INFO: Expecting 231680 events.
[15:46:35.099] <TB1> INFO: 231680 events read in total (7231ms).
[15:46:35.112] <TB1> INFO: Test took 8159ms.
[15:46:35.587] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[15:46:35.587] <TB1> INFO: CalDel: 133 145 118 143 125 130 146 154 136 129 127 118 134 117 113 143
[15:46:35.587] <TB1> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[15:46:35.594] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C0.dat
[15:46:35.595] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C1.dat
[15:46:35.595] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C2.dat
[15:46:35.595] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C3.dat
[15:46:35.595] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C4.dat
[15:46:35.596] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C5.dat
[15:46:35.596] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C6.dat
[15:46:35.596] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C7.dat
[15:46:35.596] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C8.dat
[15:46:35.596] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C9.dat
[15:46:35.597] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C10.dat
[15:46:35.597] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C11.dat
[15:46:35.597] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C12.dat
[15:46:35.597] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C13.dat
[15:46:35.597] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C14.dat
[15:46:35.598] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters_C15.dat
[15:46:35.598] <TB1> INFO: write tbm parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//tbmParameters_C0a.dat
[15:46:35.598] <TB1> INFO: write tbm parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//tbmParameters_C0b.dat
[15:46:35.598] <TB1> INFO: PixTestPretest::doTest() done, duration: 148 seconds
[15:46:35.598] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:46:35.598] <TB1> INFO: Decoding statistics:
[15:46:35.598] <TB1> INFO: General information:
[15:46:35.598] <TB1> INFO: 16bit words read: 6995666
[15:46:35.598] <TB1> INFO: valid events total: 463360
[15:46:35.598] <TB1> INFO: empty events: 301902
[15:46:35.598] <TB1> INFO: valid events with pixels: 161458
[15:46:35.598] <TB1> INFO: valid pixel hits: 717673
[15:46:35.598] <TB1> INFO: Event errors: 0
[15:46:35.598] <TB1> INFO: start marker: 0
[15:46:35.598] <TB1> INFO: stop marker: 0
[15:46:35.598] <TB1> INFO: overflow: 0
[15:46:35.598] <TB1> INFO: invalid 5bit words: 0
[15:46:35.598] <TB1> INFO: invalid XOR eye diagram: 0
[15:46:35.598] <TB1> INFO: TBM errors: 0
[15:46:35.598] <TB1> INFO: flawed TBM headers: 0
[15:46:35.598] <TB1> INFO: flawed TBM trailers: 0
[15:46:35.598] <TB1> INFO: event ID mismatches: 0
[15:46:35.599] <TB1> INFO: ROC errors: 0
[15:46:35.599] <TB1> INFO: missing ROC header(s): 0
[15:46:35.599] <TB1> INFO: misplaced readback start: 0
[15:46:35.599] <TB1> INFO: Pixel decoding errors: 0
[15:46:35.599] <TB1> INFO: pixel data incomplete: 0
[15:46:35.599] <TB1> INFO: pixel address: 0
[15:46:35.599] <TB1> INFO: pulse height fill bit: 0
[15:46:35.599] <TB1> INFO: buffer corruption: 0
[15:46:35.748] <TB1> INFO: ######################################################################
[15:46:35.748] <TB1> INFO: PixTestAlive::doTest()
[15:46:35.748] <TB1> INFO: ######################################################################
[15:46:35.750] <TB1> INFO: ----------------------------------------------------------------------
[15:46:35.750] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:46:35.750] <TB1> INFO: ----------------------------------------------------------------------
[15:46:36.168] <TB1> INFO: Expecting 41600 events.
[15:46:41.942] <TB1> INFO: 41600 events read in total (4995ms).
[15:46:41.952] <TB1> INFO: Test took 6200ms.
[15:46:41.003] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:46:42.343] <TB1> INFO: PixTestAlive::aliveTest() done
[15:46:42.343] <TB1> INFO: number of dead pixels (per ROC): 1 89 58 3 1 10 39 3 12 44 32 0 0 17 7 0
[15:46:42.345] <TB1> INFO: ----------------------------------------------------------------------
[15:46:42.345] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:46:42.345] <TB1> INFO: ----------------------------------------------------------------------
[15:46:42.715] <TB1> INFO: Expecting 41600 events.
[15:46:46.125] <TB1> INFO: 41600 events read in total (2631ms).
[15:46:46.126] <TB1> INFO: Test took 3779ms.
[15:46:46.126] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:46:46.127] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[15:46:46.595] <TB1> INFO: PixTestAlive::maskTest() done
[15:46:46.595] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:46:46.598] <TB1> INFO: ----------------------------------------------------------------------
[15:46:46.598] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:46:46.598] <TB1> INFO: ----------------------------------------------------------------------
[15:46:47.004] <TB1> INFO: Expecting 41600 events.
[15:46:51.932] <TB1> INFO: 41600 events read in total (4150ms).
[15:46:51.933] <TB1> INFO: Test took 5331ms.
[15:46:51.949] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:46:52.371] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[15:46:52.371] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:46:52.374] <TB1> INFO: PixTestAlive::doTest() done, duration: 16 seconds
[15:46:52.374] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:46:52.374] <TB1> INFO: Decoding statistics:
[15:46:52.374] <TB1> INFO: General information:
[15:46:52.374] <TB1> INFO: 16bit words read: 0
[15:46:52.374] <TB1> INFO: valid events total: 0
[15:46:52.374] <TB1> INFO: empty events: 0
[15:46:52.374] <TB1> INFO: valid events with pixels: 0
[15:46:52.374] <TB1> INFO: valid pixel hits: 0
[15:46:52.374] <TB1> INFO: Event errors: 0
[15:46:52.374] <TB1> INFO: start marker: 0
[15:46:52.374] <TB1> INFO: stop marker: 0
[15:46:52.374] <TB1> INFO: overflow: 0
[15:46:52.374] <TB1> INFO: invalid 5bit words: 0
[15:46:52.374] <TB1> INFO: invalid XOR eye diagram: 0
[15:46:52.374] <TB1> INFO: TBM errors: 0
[15:46:52.375] <TB1> INFO: flawed TBM headers: 0
[15:46:52.375] <TB1> INFO: flawed TBM trailers: 0
[15:46:52.375] <TB1> INFO: event ID mismatches: 0
[15:46:52.375] <TB1> INFO: ROC errors: 0
[15:46:52.375] <TB1> INFO: missing ROC header(s): 0
[15:46:52.375] <TB1> INFO: misplaced readback start: 0
[15:46:52.375] <TB1> INFO: Pixel decoding errors: 0
[15:46:52.375] <TB1> INFO: pixel data incomplete: 0
[15:46:52.375] <TB1> INFO: pixel address: 0
[15:46:52.375] <TB1> INFO: pulse height fill bit: 0
[15:46:52.375] <TB1> INFO: buffer corruption: 0
[15:46:52.390] <TB1> INFO: ######################################################################
[15:46:52.390] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[15:46:52.390] <TB1> INFO: ######################################################################
[15:46:52.396] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[15:46:52.419] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[15:46:52.419] <TB1> INFO: run 1 of 1
[15:46:52.822] <TB1> INFO: Expecting 3120000 events.
[15:47:47.081] <TB1> INFO: 1205500 events read in total (53480ms).
[15:48:39.203] <TB1> INFO: 2407090 events read in total (105604ms).
[15:49:12.211] <TB1> INFO: 3120000 events read in total (138611ms).
[15:49:12.334] <TB1> INFO: Test took 139916ms.
[15:49:12.537] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:50:13.132] <TB1> INFO: PixTestBBMap::doTest() done, duration: 200 seconds
[15:50:13.132] <TB1> INFO: number of dead bumps (per ROC): 0 10 4 0 0 0 6 0 0 6 1 0 0 0 0 0
[15:50:13.132] <TB1> INFO: separation cut (per ROC): 105 135 127 121 124 119 123 113 125 126 128 128 108 141 139 118
[15:50:13.133] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:50:13.133] <TB1> INFO: Decoding statistics:
[15:50:13.133] <TB1> INFO: General information:
[15:50:13.133] <TB1> INFO: 16bit words read: 0
[15:50:13.133] <TB1> INFO: valid events total: 0
[15:50:13.133] <TB1> INFO: empty events: 0
[15:50:13.133] <TB1> INFO: valid events with pixels: 0
[15:50:13.133] <TB1> INFO: valid pixel hits: 0
[15:50:13.133] <TB1> INFO: Event errors: 0
[15:50:13.133] <TB1> INFO: start marker: 0
[15:50:13.133] <TB1> INFO: stop marker: 0
[15:50:13.133] <TB1> INFO: overflow: 0
[15:50:13.133] <TB1> INFO: invalid 5bit words: 0
[15:50:13.133] <TB1> INFO: invalid XOR eye diagram: 0
[15:50:13.133] <TB1> INFO: TBM errors: 0
[15:50:13.133] <TB1> INFO: flawed TBM headers: 0
[15:50:13.133] <TB1> INFO: flawed TBM trailers: 0
[15:50:13.133] <TB1> INFO: event ID mismatches: 0
[15:50:13.133] <TB1> INFO: ROC errors: 0
[15:50:13.133] <TB1> INFO: missing ROC header(s): 0
[15:50:13.133] <TB1> INFO: misplaced readback start: 0
[15:50:13.133] <TB1> INFO: Pixel decoding errors: 0
[15:50:13.133] <TB1> INFO: pixel data incomplete: 0
[15:50:13.133] <TB1> INFO: pixel address: 0
[15:50:13.133] <TB1> INFO: pulse height fill bit: 0
[15:50:13.133] <TB1> INFO: buffer corruption: 0
[15:50:13.333] <TB1> INFO: ######################################################################
[15:50:13.333] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[15:50:13.333] <TB1> INFO: ######################################################################
[15:50:13.333] <TB1> INFO: ----------------------------------------------------------------------
[15:50:13.333] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[15:50:13.338] <TB1> INFO: ----------------------------------------------------------------------
[15:50:13.338] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 150 (-1/-1) hits flags = 528 (plus default)
[15:50:13.398] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[15:50:13.398] <TB1> INFO: run 1 of 1
[15:50:14.132] <TB1> INFO: Expecting 26208000 events.
[15:50:51.351] <TB1> INFO: 1127400 events read in total (36440ms).
[15:51:28.097] <TB1> INFO: 2231200 events read in total (73186ms).
[15:52:04.836] <TB1> INFO: 3336000 events read in total (109925ms).
[15:52:41.756] <TB1> INFO: 4435250 events read in total (146845ms).
[15:53:18.706] <TB1> INFO: 5534150 events read in total (183795ms).
[15:53:55.666] <TB1> INFO: 6633050 events read in total (220755ms).
[15:54:34.877] <TB1> INFO: 7727050 events read in total (259966ms).
[15:55:18.829] <TB1> INFO: 8818300 events read in total (303918ms).
[15:56:01.162] <TB1> INFO: 9909400 events read in total (346251ms).
[15:56:47.638] <TB1> INFO: 10998150 events read in total (392727ms).
[15:57:35.223] <TB1> INFO: 12087650 events read in total (440312ms).
[15:58:18.083] <TB1> INFO: 13170700 events read in total (483172ms).
[15:58:55.525] <TB1> INFO: 14242200 events read in total (520614ms).
[15:59:33.093] <TB1> INFO: 15312950 events read in total (558182ms).
[16:00:14.568] <TB1> INFO: 16379050 events read in total (599657ms).
[16:00:58.357] <TB1> INFO: 17445900 events read in total (643446ms).
[16:01:37.386] <TB1> INFO: 18512900 events read in total (682475ms).
[16:02:17.143] <TB1> INFO: 19576900 events read in total (722232ms).
[16:02:53.788] <TB1> INFO: 20644100 events read in total (758877ms).
[16:03:35.267] <TB1> INFO: 21714150 events read in total (800356ms).
[16:04:12.317] <TB1> INFO: 22779200 events read in total (837406ms).
[16:04:49.212] <TB1> INFO: 23848800 events read in total (874301ms).
[16:05:30.521] <TB1> INFO: 24917250 events read in total (915610ms).
[16:06:08.971] <TB1> INFO: 26001950 events read in total (954060ms).
[16:06:16.958] <TB1> INFO: 26208000 events read in total (962047ms).
[16:06:17.047] <TB1> INFO: Test took 963648ms.
[16:06:17.223] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[16:06:17.797] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:06:21.208] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:06:24.334] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:06:27.804] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:06:31.132] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:06:34.523] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:06:38.094] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:06:41.487] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:06:45.210] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:06:49.894] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:06:54.492] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:07:01.366] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:07:06.905] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:07:11.718] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:07:15.551] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:07:19.540] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[16:07:23.710] <TB1> INFO: PixTestScurves::scurves() done
[16:07:23.710] <TB1> INFO: Vcal mean: 79.48 93.12 91.09 88.05 87.56 94.52 89.65 89.79 97.15 87.17 96.59 92.15 73.74 97.24 95.24 98.45
[16:07:23.710] <TB1> INFO: Vcal RMS: 4.12 15.90 12.05 5.32 5.34 7.09 10.07 6.13 7.68 10.19 11.00 5.89 4.60 7.93 6.62 5.26
[16:07:23.711] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1030 seconds
[16:07:23.711] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[16:07:23.711] <TB1> INFO: Decoding statistics:
[16:07:23.711] <TB1> INFO: General information:
[16:07:23.711] <TB1> INFO: 16bit words read: 0
[16:07:23.711] <TB1> INFO: valid events total: 0
[16:07:23.711] <TB1> INFO: empty events: 0
[16:07:23.711] <TB1> INFO: valid events with pixels: 0
[16:07:23.711] <TB1> INFO: valid pixel hits: 0
[16:07:23.711] <TB1> INFO: Event errors: 0
[16:07:23.711] <TB1> INFO: start marker: 0
[16:07:23.711] <TB1> INFO: stop marker: 0
[16:07:23.711] <TB1> INFO: overflow: 0
[16:07:23.712] <TB1> INFO: invalid 5bit words: 0
[16:07:23.712] <TB1> INFO: invalid XOR eye diagram: 0
[16:07:23.712] <TB1> INFO: TBM errors: 0
[16:07:23.712] <TB1> INFO: flawed TBM headers: 0
[16:07:23.712] <TB1> INFO: flawed TBM trailers: 0
[16:07:23.712] <TB1> INFO: event ID mismatches: 0
[16:07:23.712] <TB1> INFO: ROC errors: 0
[16:07:23.712] <TB1> INFO: missing ROC header(s): 0
[16:07:23.712] <TB1> INFO: misplaced readback start: 0
[16:07:23.712] <TB1> INFO: Pixel decoding errors: 0
[16:07:23.712] <TB1> INFO: pixel data incomplete: 0
[16:07:23.712] <TB1> INFO: pixel address: 0
[16:07:23.712] <TB1> INFO: pulse height fill bit: 0
[16:07:23.712] <TB1> INFO: buffer corruption: 0
[16:07:23.973] <TB1> INFO: ######################################################################
[16:07:23.973] <TB1> INFO: PixTestTrim::doTest()
[16:07:23.973] <TB1> INFO: ######################################################################
[16:07:23.978] <TB1> INFO: ----------------------------------------------------------------------
[16:07:23.978] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[16:07:23.978] <TB1> INFO: ----------------------------------------------------------------------
[16:07:24.187] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[16:07:24.192] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[16:07:24.231] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[16:07:24.248] <TB1> INFO: run 1 of 1
[16:07:24.852] <TB1> INFO: Expecting 5025280 events.
[16:08:18.103] <TB1> INFO: 1402536 events read in total (52459ms).
[16:09:08.065] <TB1> INFO: 2792608 events read in total (102421ms).
[16:10:01.447] <TB1> INFO: 4190216 events read in total (155804ms).
[16:10:33.834] <TB1> INFO: 5025280 events read in total (188190ms).
[16:10:33.929] <TB1> INFO: Test took 189669ms.
[16:10:34.065] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[16:11:28.146] <TB1> INFO: ROC 0 VthrComp = 83
[16:11:28.151] <TB1> INFO: ROC 1 VthrComp = 91
[16:11:28.151] <TB1> INFO: ROC 2 VthrComp = 95
[16:11:28.154] <TB1> INFO: ROC 3 VthrComp = 96
[16:11:28.157] <TB1> INFO: ROC 4 VthrComp = 96
[16:11:28.160] <TB1> INFO: ROC 5 VthrComp = 96
[16:11:28.163] <TB1> INFO: ROC 6 VthrComp = 92
[16:11:28.169] <TB1> INFO: ROC 7 VthrComp = 93
[16:11:28.172] <TB1> INFO: ROC 8 VthrComp = 100
[16:11:28.175] <TB1> INFO: ROC 9 VthrComp = 94
[16:11:28.193] <TB1> INFO: ROC 10 VthrComp = 96
[16:11:28.194] <TB1> INFO: ROC 11 VthrComp = 98
[16:11:28.196] <TB1> INFO: ROC 12 VthrComp = 79
[16:11:28.202] <TB1> INFO: ROC 13 VthrComp = 106
[16:11:28.205] <TB1> INFO: ROC 14 VthrComp = 103
[16:11:28.208] <TB1> INFO: ROC 15 VthrComp = 99
[16:11:28.211] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[16:11:28.214] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[16:11:28.270] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[16:11:28.270] <TB1> INFO: run 1 of 1
[16:11:28.703] <TB1> INFO: Expecting 5025280 events.
[16:12:13.514] <TB1> INFO: 892568 events read in total (44027ms).
[16:12:54.043] <TB1> INFO: 1781296 events read in total (84557ms).
[16:13:37.708] <TB1> INFO: 2668136 events read in total (128222ms).
[16:14:22.598] <TB1> INFO: 3547120 events read in total (173111ms).
[16:15:08.687] <TB1> INFO: 4425296 events read in total (219200ms).
[16:15:42.740] <TB1> INFO: 5025280 events read in total (253253ms).
[16:15:42.888] <TB1> INFO: Test took 254618ms.
[16:15:43.284] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[16:17:04.616] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 57.0873 for pixel 48/2 mean/min/max = 45.13/33.112/57.148
[16:17:04.616] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 70.6489 for pixel 5/63 mean/min/max = 51.7301/32.7833/70.677
[16:17:04.617] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 61.1977 for pixel 10/74 mean/min/max = 47.9204/34.6276/61.2132
[16:17:04.618] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 56.1757 for pixel 9/2 mean/min/max = 44.3719/32.3139/56.4299
[16:17:04.618] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 57.6074 for pixel 0/1 mean/min/max = 44.5719/31.5308/57.613
[16:17:04.619] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 59.2264 for pixel 6/9 mean/min/max = 45.808/32.3882/59.2278
[16:17:04.620] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 60.2576 for pixel 24/0 mean/min/max = 47.0374/33.7933/60.2815
[16:17:04.621] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 60.8308 for pixel 13/3 mean/min/max = 46.6864/32.4868/60.886
[16:17:04.622] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 58.8982 for pixel 51/58 mean/min/max = 45.8893/32.7687/59.0099
[16:17:04.623] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 57.3262 for pixel 14/14 mean/min/max = 45.5615/33.6479/57.475
[16:17:04.623] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 63.5858 for pixel 0/56 mean/min/max = 48.0429/31.9838/64.102
[16:17:04.624] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 60.2367 for pixel 1/54 mean/min/max = 45.9667/31.6708/60.2626
[16:17:04.625] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 57.2061 for pixel 0/73 mean/min/max = 45.9238/34.4341/57.4135
[16:17:04.626] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 61.1865 for pixel 27/0 mean/min/max = 46.262/30.4453/62.0787
[16:17:04.626] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 57.912 for pixel 51/23 mean/min/max = 45.1862/32.3119/58.0604
[16:17:04.627] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 59.7816 for pixel 11/4 mean/min/max = 46.1254/32.4589/59.792
[16:17:04.628] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:17:04.775] <TB1> INFO: Expecting 411648 events.
[16:17:15.140] <TB1> INFO: 411648 events read in total (9578ms).
[16:17:15.170] <TB1> INFO: Expecting 411648 events.
[16:17:25.091] <TB1> INFO: 411648 events read in total (9390ms).
[16:17:25.109] <TB1> INFO: Expecting 411648 events.
[16:17:34.570] <TB1> INFO: 411648 events read in total (8834ms).
[16:17:34.592] <TB1> INFO: Expecting 411648 events.
[16:17:43.984] <TB1> INFO: 411648 events read in total (8765ms).
[16:17:44.009] <TB1> INFO: Expecting 411648 events.
[16:17:53.335] <TB1> INFO: 411648 events read in total (8697ms).
[16:17:53.371] <TB1> INFO: Expecting 411648 events.
[16:18:02.565] <TB1> INFO: 411648 events read in total (8579ms).
[16:18:02.600] <TB1> INFO: Expecting 411648 events.
[16:18:12.776] <TB1> INFO: 411648 events read in total (9556ms).
[16:18:12.812] <TB1> INFO: Expecting 411648 events.
[16:18:23.665] <TB1> INFO: 411648 events read in total (10269ms).
[16:18:23.708] <TB1> INFO: Expecting 411648 events.
[16:18:32.497] <TB1> INFO: 411648 events read in total (8187ms).
[16:18:32.541] <TB1> INFO: Expecting 411648 events.
[16:18:41.365] <TB1> INFO: 411648 events read in total (8213ms).
[16:18:41.431] <TB1> INFO: Expecting 411648 events.
[16:18:50.429] <TB1> INFO: 411648 events read in total (8412ms).
[16:18:50.485] <TB1> INFO: Expecting 411648 events.
[16:18:59.259] <TB1> INFO: 411648 events read in total (8179ms).
[16:18:59.314] <TB1> INFO: Expecting 411648 events.
[16:19:08.732] <TB1> INFO: 411648 events read in total (8823ms).
[16:19:08.809] <TB1> INFO: Expecting 411648 events.
[16:19:17.854] <TB1> INFO: 411648 events read in total (8485ms).
[16:19:17.927] <TB1> INFO: Expecting 411648 events.
[16:19:27.798] <TB1> INFO: 411648 events read in total (9301ms).
[16:19:27.884] <TB1> INFO: Expecting 411648 events.
[16:19:37.451] <TB1> INFO: 411648 events read in total (9009ms).
[16:19:37.521] <TB1> INFO: Test took 152893ms.
[16:19:39.411] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[16:19:39.432] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[16:19:39.432] <TB1> INFO: run 1 of 1
[16:19:39.811] <TB1> INFO: Expecting 5025280 events.
[16:20:23.348] <TB1> INFO: 872992 events read in total (42751ms).
[16:21:03.340] <TB1> INFO: 1742688 events read in total (82743ms).
[16:21:43.946] <TB1> INFO: 2610936 events read in total (123350ms).
[16:22:28.700] <TB1> INFO: 3469760 events read in total (168103ms).
[16:23:13.005] <TB1> INFO: 4327696 events read in total (213409ms).
[16:23:53.081] <TB1> INFO: 5025280 events read in total (252484ms).
[16:23:53.253] <TB1> INFO: Test took 253821ms.
[16:23:53.680] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[16:24:54.752] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 0.049654 .. 255.000000
[16:24:54.866] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[16:24:54.891] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[16:24:54.891] <TB1> INFO: run 1 of 1
[16:24:55.339] <TB1> INFO: Expecting 8519680 events.
[16:25:41.393] <TB1> INFO: 830192 events read in total (45275ms).
[16:26:20.252] <TB1> INFO: 1658208 events read in total (84134ms).
[16:26:58.002] <TB1> INFO: 2485968 events read in total (122885ms).
[16:27:42.743] <TB1> INFO: 3313144 events read in total (166625ms).
[16:28:22.841] <TB1> INFO: 4141544 events read in total (206723ms).
[16:29:01.035] <TB1> INFO: 4968016 events read in total (244917ms).
[16:29:39.289] <TB1> INFO: 5794872 events read in total (283171ms).
[16:30:17.962] <TB1> INFO: 6622144 events read in total (321845ms).
[16:31:05.394] <TB1> INFO: 7449600 events read in total (369276ms).
[16:31:49.715] <TB1> INFO: 8277464 events read in total (413597ms).
[16:32:01.441] <TB1> INFO: 8519680 events read in total (425324ms).
[16:32:01.640] <TB1> INFO: Test took 426750ms.
[16:32:02.193] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[16:33:06.675] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 1.791642 .. 167.332152
[16:33:06.789] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 1 .. 177 (-1/-1) hits flags = 528 (plus default)
[16:33:06.811] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[16:33:06.811] <TB1> INFO: run 1 of 1
[16:33:07.267] <TB1> INFO: Expecting 5890560 events.
[16:33:48.327] <TB1> INFO: 858848 events read in total (40264ms).
[16:34:27.948] <TB1> INFO: 1715880 events read in total (79885ms).
[16:35:11.706] <TB1> INFO: 2572536 events read in total (123643ms).
[16:35:53.047] <TB1> INFO: 3428768 events read in total (164984ms).
[16:36:39.830] <TB1> INFO: 4285512 events read in total (211767ms).
[16:37:34.264] <TB1> INFO: 5143368 events read in total (266201ms).
[16:38:17.845] <TB1> INFO: 5890560 events read in total (309782ms).
[16:38:18.016] <TB1> INFO: Test took 311206ms.
[16:38:18.360] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[16:39:30.802] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 1.500000 .. 82.230417
[16:39:31.065] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 1 .. 92 (-1/-1) hits flags = 528 (plus default)
[16:39:31.089] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[16:39:31.089] <TB1> INFO: run 1 of 1
[16:39:31.557] <TB1> INFO: Expecting 3061760 events.
[16:40:15.566] <TB1> INFO: 972616 events read in total (43229ms).
[16:41:03.861] <TB1> INFO: 1943944 events read in total (91526ms).
[16:42:03.897] <TB1> INFO: 2916256 events read in total (151561ms).
[16:42:13.180] <TB1> INFO: 3061760 events read in total (160843ms).
[16:42:13.278] <TB1> INFO: Test took 162190ms.
[16:42:13.488] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[16:43:02.747] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 0.292689 .. 67.759279
[16:43:02.850] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 0 .. 77 (-1/-1) hits flags = 528 (plus default)
[16:43:02.872] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[16:43:02.872] <TB1> INFO: run 1 of 1
[16:43:03.304] <TB1> INFO: Expecting 2595840 events.
[16:43:51.374] <TB1> INFO: 1034432 events read in total (47288ms).
[16:44:39.016] <TB1> INFO: 2068312 events read in total (94930ms).
[16:45:03.080] <TB1> INFO: 2595840 events read in total (118994ms).
[16:45:03.137] <TB1> INFO: Test took 120264ms.
[16:45:03.249] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[16:45:42.702] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[16:45:42.702] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[16:45:42.733] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[16:45:42.733] <TB1> INFO: run 1 of 1
[16:45:43.185] <TB1> INFO: Expecting 1364480 events.
[16:46:33.662] <TB1> INFO: 1077456 events read in total (49690ms).
[16:46:47.750] <TB1> INFO: 1364480 events read in total (63778ms).
[16:46:47.833] <TB1> INFO: Test took 65101ms.
[16:46:48.008] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[16:47:18.597] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C0.dat
[16:47:18.598] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C1.dat
[16:47:18.598] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C2.dat
[16:47:18.598] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C3.dat
[16:47:18.598] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C4.dat
[16:47:18.599] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C5.dat
[16:47:18.599] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C6.dat
[16:47:18.599] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C7.dat
[16:47:18.599] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C8.dat
[16:47:18.599] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C9.dat
[16:47:18.599] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C10.dat
[16:47:18.600] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C11.dat
[16:47:18.600] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C12.dat
[16:47:18.600] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C13.dat
[16:47:18.600] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C14.dat
[16:47:18.600] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C15.dat
[16:47:18.601] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters35_C0.dat
[16:47:18.616] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters35_C1.dat
[16:47:18.628] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters35_C2.dat
[16:47:18.640] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters35_C3.dat
[16:47:18.652] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters35_C4.dat
[16:47:18.665] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters35_C5.dat
[16:47:18.678] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters35_C6.dat
[16:47:18.692] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters35_C7.dat
[16:47:18.715] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters35_C8.dat
[16:47:18.728] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters35_C9.dat
[16:47:18.744] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters35_C10.dat
[16:47:18.756] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters35_C11.dat
[16:47:18.769] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters35_C12.dat
[16:47:18.791] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters35_C13.dat
[16:47:18.802] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters35_C14.dat
[16:47:18.815] <TB1> INFO: write trim parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//trimParameters35_C15.dat
[16:47:18.835] <TB1> INFO: PixTestTrim::trimTest() done
[16:47:18.835] <TB1> INFO: vtrim: 95 149 115 104 102 102 108 132 93 107 122 117 92 123 115 100
[16:47:18.835] <TB1> INFO: vthrcomp: 83 91 95 96 96 96 92 93 100 94 96 98 79 106 103 99
[16:47:18.835] <TB1> INFO: vcal mean: 34.99 34.26 34.55 34.97 34.98 34.90 34.70 34.97 34.91 34.63 34.77 35.01 34.99 34.87 34.91 35.04
[16:47:18.835] <TB1> INFO: vcal RMS: 1.06 5.07 4.18 1.29 1.07 1.89 3.40 1.63 2.12 3.65 3.25 0.95 0.84 2.37 1.68 0.99
[16:47:18.835] <TB1> INFO: bits mean: 9.58 8.41 9.04 9.78 9.55 9.41 9.03 9.68 9.17 9.14 8.80 9.70 8.63 9.78 9.63 8.94
[16:47:18.835] <TB1> INFO: bits RMS: 2.56 2.70 2.51 2.57 2.81 2.67 2.63 2.47 2.68 2.67 2.90 2.62 2.66 2.30 2.63 2.86
[16:47:18.851] <TB1> INFO: ----------------------------------------------------------------------
[16:47:18.851] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[16:47:18.851] <TB1> INFO: ----------------------------------------------------------------------
[16:47:18.861] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[16:47:18.886] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[16:47:18.886] <TB1> INFO: run 1 of 1
[16:47:19.279] <TB1> INFO: Expecting 4160000 events.
[16:48:09.562] <TB1> INFO: 1151730 events read in total (49504ms).
[16:49:04.970] <TB1> INFO: 2286785 events read in total (104912ms).
[16:50:03.913] <TB1> INFO: 3410405 events read in total (163855ms).
[16:50:36.757] <TB1> INFO: 4160000 events read in total (196699ms).
[16:50:36.864] <TB1> INFO: Test took 197978ms.
[16:50:37.089] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[16:51:44.428] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 196 (-1/-1) hits flags = 528 (plus default)
[16:51:44.484] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[16:51:44.484] <TB1> INFO: run 1 of 1
[16:51:45.150] <TB1> INFO: Expecting 4097600 events.
[16:52:46.018] <TB1> INFO: 1115810 events read in total (60083ms).
[16:53:41.366] <TB1> INFO: 2217375 events read in total (115431ms).
[16:54:38.157] <TB1> INFO: 3307870 events read in total (172222ms).
[16:55:14.665] <TB1> INFO: 4097600 events read in total (208730ms).
[16:55:14.816] <TB1> INFO: Test took 210331ms.
[16:55:15.050] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[16:56:17.243] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 181 (-1/-1) hits flags = 528 (plus default)
[16:56:17.274] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[16:56:17.277] <TB1> INFO: run 1 of 1
[16:56:17.722] <TB1> INFO: Expecting 3785600 events.
[16:57:33.054] <TB1> INFO: 1158725 events read in total (74553ms).
[16:58:26.167] <TB1> INFO: 2299090 events read in total (127666ms).
[16:59:16.764] <TB1> INFO: 3430340 events read in total (178263ms).
[16:59:34.656] <TB1> INFO: 3785600 events read in total (196155ms).
[16:59:34.754] <TB1> INFO: Test took 197474ms.
[16:59:34.953] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[17:00:32.099] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 186 (-1/-1) hits flags = 528 (plus default)
[17:00:32.135] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[17:00:32.135] <TB1> INFO: run 1 of 1
[17:00:32.554] <TB1> INFO: Expecting 3889600 events.
[17:01:35.063] <TB1> INFO: 1142460 events read in total (61730ms).
[17:02:21.339] <TB1> INFO: 2268540 events read in total (108006ms).
[17:03:07.717] <TB1> INFO: 3384450 events read in total (154384ms).
[17:03:29.707] <TB1> INFO: 3889600 events read in total (176374ms).
[17:03:29.777] <TB1> INFO: Test took 177641ms.
[17:03:29.963] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[17:04:27.084] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 179 (-1/-1) hits flags = 528 (plus default)
[17:04:27.109] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[17:04:27.109] <TB1> INFO: run 1 of 1
[17:04:27.530] <TB1> INFO: Expecting 3744000 events.
[17:05:26.971] <TB1> INFO: 1164090 events read in total (58663ms).
[17:06:15.473] <TB1> INFO: 2308920 events read in total (107165ms).
[17:07:02.137] <TB1> INFO: 3444585 events read in total (153829ms).
[17:07:14.811] <TB1> INFO: 3744000 events read in total (166503ms).
[17:07:14.889] <TB1> INFO: Test took 167780ms.
[17:07:15.065] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[17:08:10.328] <TB1> INFO: PixTestTrim::trimBitTest() done
[17:08:10.330] <TB1> INFO: PixTestTrim::doTest() done, duration: 3646 seconds
[17:08:10.330] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[17:08:10.332] <TB1> INFO: Decoding statistics:
[17:08:10.332] <TB1> INFO: General information:
[17:08:10.332] <TB1> INFO: 16bit words read: 0
[17:08:10.332] <TB1> INFO: valid events total: 0
[17:08:10.332] <TB1> INFO: empty events: 0
[17:08:10.332] <TB1> INFO: valid events with pixels: 0
[17:08:10.332] <TB1> INFO: valid pixel hits: 0
[17:08:10.332] <TB1> INFO: Event errors: 0
[17:08:10.332] <TB1> INFO: start marker: 0
[17:08:10.332] <TB1> INFO: stop marker: 0
[17:08:10.332] <TB1> INFO: overflow: 0
[17:08:10.332] <TB1> INFO: invalid 5bit words: 0
[17:08:10.332] <TB1> INFO: invalid XOR eye diagram: 0
[17:08:10.332] <TB1> INFO: TBM errors: 0
[17:08:10.333] <TB1> INFO: flawed TBM headers: 0
[17:08:10.333] <TB1> INFO: flawed TBM trailers: 0
[17:08:10.333] <TB1> INFO: event ID mismatches: 0
[17:08:10.333] <TB1> INFO: ROC errors: 0
[17:08:10.333] <TB1> INFO: missing ROC header(s): 0
[17:08:10.333] <TB1> INFO: misplaced readback start: 0
[17:08:10.333] <TB1> INFO: Pixel decoding errors: 0
[17:08:10.333] <TB1> INFO: pixel data incomplete: 0
[17:08:10.333] <TB1> INFO: pixel address: 0
[17:08:10.333] <TB1> INFO: pulse height fill bit: 0
[17:08:10.333] <TB1> INFO: buffer corruption: 0
[17:08:11.749] <TB1> INFO: ######################################################################
[17:08:11.749] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[17:08:11.749] <TB1> INFO: ######################################################################
[17:08:12.123] <TB1> INFO: Expecting 41600 events.
[17:08:16.701] <TB1> INFO: 41600 events read in total (3799ms).
[17:08:16.704] <TB1> INFO: Test took 4894ms.
[17:08:16.716] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[17:08:17.495] <TB1> INFO: Expecting 41600 events.
[17:08:22.280] <TB1> INFO: 41600 events read in total (4006ms).
[17:08:22.281] <TB1> INFO: Test took 5174ms.
[17:08:22.293] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[17:08:22.733] <TB1> INFO: Expecting 41600 events.
[17:08:27.378] <TB1> INFO: 41600 events read in total (3866ms).
[17:08:27.380] <TB1> INFO: Test took 5035ms.
[17:08:27.391] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[17:08:27.857] <TB1> INFO: Expecting 2560 events.
[17:08:28.885] <TB1> INFO: 2560 events read in total (250ms).
[17:08:28.886] <TB1> INFO: Test took 1483ms.
[17:08:29.459] <TB1> INFO: Expecting 2560 events.
[17:08:30.485] <TB1> INFO: 2560 events read in total (248ms).
[17:08:30.485] <TB1> INFO: Test took 1598ms.
[17:08:31.057] <TB1> INFO: Expecting 2560 events.
[17:08:32.083] <TB1> INFO: 2560 events read in total (247ms).
[17:08:32.084] <TB1> INFO: Test took 1598ms.
[17:08:32.656] <TB1> INFO: Expecting 2560 events.
[17:08:33.687] <TB1> INFO: 2560 events read in total (248ms).
[17:08:33.687] <TB1> INFO: Test took 1599ms.
[17:08:34.259] <TB1> INFO: Expecting 2560 events.
[17:08:35.285] <TB1> INFO: 2560 events read in total (247ms).
[17:08:35.286] <TB1> INFO: Test took 1598ms.
[17:08:35.858] <TB1> INFO: Expecting 2560 events.
[17:08:36.888] <TB1> INFO: 2560 events read in total (251ms).
[17:08:36.888] <TB1> INFO: Test took 1602ms.
[17:08:37.460] <TB1> INFO: Expecting 2560 events.
[17:08:38.487] <TB1> INFO: 2560 events read in total (249ms).
[17:08:38.491] <TB1> INFO: Test took 1603ms.
[17:08:39.059] <TB1> INFO: Expecting 2560 events.
[17:08:40.086] <TB1> INFO: 2560 events read in total (248ms).
[17:08:40.087] <TB1> INFO: Test took 1596ms.
[17:08:40.659] <TB1> INFO: Expecting 2560 events.
[17:08:41.687] <TB1> INFO: 2560 events read in total (250ms).
[17:08:41.688] <TB1> INFO: Test took 1601ms.
[17:08:42.260] <TB1> INFO: Expecting 2560 events.
[17:08:43.289] <TB1> INFO: 2560 events read in total (250ms).
[17:08:43.289] <TB1> INFO: Test took 1601ms.
[17:08:43.861] <TB1> INFO: Expecting 2560 events.
[17:08:44.891] <TB1> INFO: 2560 events read in total (251ms).
[17:08:44.891] <TB1> INFO: Test took 1599ms.
[17:08:45.463] <TB1> INFO: Expecting 2560 events.
[17:08:46.490] <TB1> INFO: 2560 events read in total (248ms).
[17:08:46.490] <TB1> INFO: Test took 1598ms.
[17:08:47.062] <TB1> INFO: Expecting 2560 events.
[17:08:48.090] <TB1> INFO: 2560 events read in total (249ms).
[17:08:48.090] <TB1> INFO: Test took 1599ms.
[17:08:48.662] <TB1> INFO: Expecting 2560 events.
[17:08:49.689] <TB1> INFO: 2560 events read in total (248ms).
[17:08:49.690] <TB1> INFO: Test took 1599ms.
[17:08:50.262] <TB1> INFO: Expecting 2560 events.
[17:08:51.288] <TB1> INFO: 2560 events read in total (248ms).
[17:08:51.289] <TB1> INFO: Test took 1597ms.
[17:08:51.860] <TB1> INFO: Expecting 2560 events.
[17:08:52.887] <TB1> INFO: 2560 events read in total (248ms).
[17:08:52.889] <TB1> INFO: Test took 1599ms.
[17:08:52.895] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:08:53.461] <TB1> INFO: Expecting 655360 events.
[17:09:07.265] <TB1> INFO: 655360 events read in total (13025ms).
[17:09:07.282] <TB1> INFO: Expecting 655360 events.
[17:09:20.717] <TB1> INFO: 655360 events read in total (12909ms).
[17:09:20.747] <TB1> INFO: Expecting 655360 events.
[17:09:34.277] <TB1> INFO: 655360 events read in total (13003ms).
[17:09:34.312] <TB1> INFO: Expecting 655360 events.
[17:09:47.836] <TB1> INFO: 655360 events read in total (12997ms).
[17:09:47.869] <TB1> INFO: Expecting 655360 events.
[17:10:01.345] <TB1> INFO: 655360 events read in total (12949ms).
[17:10:01.395] <TB1> INFO: Expecting 655360 events.
[17:10:14.835] <TB1> INFO: 655360 events read in total (12913ms).
[17:10:14.878] <TB1> INFO: Expecting 655360 events.
[17:10:28.313] <TB1> INFO: 655360 events read in total (12908ms).
[17:10:28.373] <TB1> INFO: Expecting 655360 events.
[17:10:41.825] <TB1> INFO: 655360 events read in total (12925ms).
[17:10:41.882] <TB1> INFO: Expecting 655360 events.
[17:10:55.409] <TB1> INFO: 655360 events read in total (13000ms).
[17:10:55.488] <TB1> INFO: Expecting 655360 events.
[17:11:08.932] <TB1> INFO: 655360 events read in total (12917ms).
[17:11:09.018] <TB1> INFO: Expecting 655360 events.
[17:11:23.134] <TB1> INFO: 655360 events read in total (13590ms).
[17:11:23.235] <TB1> INFO: Expecting 655360 events.
[17:11:36.768] <TB1> INFO: 655360 events read in total (13006ms).
[17:11:36.865] <TB1> INFO: Expecting 655360 events.
[17:11:50.390] <TB1> INFO: 655360 events read in total (12999ms).
[17:11:50.497] <TB1> INFO: Expecting 655360 events.
[17:12:04.022] <TB1> INFO: 655360 events read in total (12998ms).
[17:12:04.129] <TB1> INFO: Expecting 655360 events.
[17:12:17.696] <TB1> INFO: 655360 events read in total (13040ms).
[17:12:17.822] <TB1> INFO: Expecting 655360 events.
[17:12:31.252] <TB1> INFO: 655360 events read in total (12904ms).
[17:12:31.394] <TB1> INFO: Test took 218499ms.
[17:12:31.563] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:12:31.928] <TB1> INFO: Expecting 655360 events.
[17:12:45.306] <TB1> INFO: 655360 events read in total (12600ms).
[17:12:45.330] <TB1> INFO: Expecting 655360 events.
[17:12:58.222] <TB1> INFO: 655360 events read in total (12355ms).
[17:12:58.252] <TB1> INFO: Expecting 655360 events.
[17:13:11.986] <TB1> INFO: 655360 events read in total (13151ms).
[17:13:12.025] <TB1> INFO: Expecting 655360 events.
[17:13:25.439] <TB1> INFO: 655360 events read in total (12888ms).
[17:13:25.487] <TB1> INFO: Expecting 655360 events.
[17:13:41.754] <TB1> INFO: 655360 events read in total (15741ms).
[17:13:41.825] <TB1> INFO: Expecting 655360 events.
[17:13:56.306] <TB1> INFO: 655360 events read in total (13954ms).
[17:13:56.355] <TB1> INFO: Expecting 655360 events.
[17:14:09.863] <TB1> INFO: 655360 events read in total (12982ms).
[17:14:09.927] <TB1> INFO: Expecting 655360 events.
[17:14:23.159] <TB1> INFO: 655360 events read in total (12706ms).
[17:14:23.231] <TB1> INFO: Expecting 655360 events.
[17:14:38.676] <TB1> INFO: 655360 events read in total (14919ms).
[17:14:38.833] <TB1> INFO: Expecting 655360 events.
[17:14:54.098] <TB1> INFO: 655360 events read in total (14736ms).
[17:14:54.173] <TB1> INFO: Expecting 655360 events.
[17:15:07.577] <TB1> INFO: 655360 events read in total (12877ms).
[17:15:07.659] <TB1> INFO: Expecting 655360 events.
[17:15:20.958] <TB1> INFO: 655360 events read in total (12772ms).
[17:15:21.086] <TB1> INFO: Expecting 655360 events.
[17:15:34.649] <TB1> INFO: 655360 events read in total (13036ms).
[17:15:34.791] <TB1> INFO: Expecting 655360 events.
[17:15:48.407] <TB1> INFO: 655360 events read in total (13090ms).
[17:15:48.544] <TB1> INFO: Expecting 655360 events.
[17:16:01.943] <TB1> INFO: 655360 events read in total (12872ms).
[17:16:02.089] <TB1> INFO: Expecting 655360 events.
[17:16:15.494] <TB1> INFO: 655360 events read in total (12878ms).
[17:16:15.629] <TB1> INFO: Test took 224066ms.
[17:16:16.021] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:16.038] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:16.057] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:16.078] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:16.098] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:16.119] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:16.140] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:16.160] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:16.181] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:16.201] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:16.221] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:16.240] <TB1> INFO: For ROC 10: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[17:16:16.244] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[17:16:16.263] <TB1> INFO: For ROC 10: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[17:16:16.268] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[17:16:16.288] <TB1> INFO: For ROC 10: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[17:16:16.293] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[17:16:16.312] <TB1> INFO: For ROC 10: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[17:16:16.319] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[17:16:16.340] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:16.360] <TB1> INFO: For ROC 11: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[17:16:16.366] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[17:16:16.383] <TB1> INFO: For ROC 11: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[17:16:16.387] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[17:16:16.402] <TB1> INFO: For ROC 11: No solutions with PhScale > 20 could be found. Looking for a solution with PhScale < 20.
[17:16:16.406] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[17:16:16.426] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:16.445] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:16.466] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:16.487] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[17:16:16.552] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C0.dat
[17:16:16.552] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C1.dat
[17:16:16.552] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C2.dat
[17:16:16.552] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C3.dat
[17:16:16.552] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C4.dat
[17:16:16.553] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C5.dat
[17:16:16.553] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C6.dat
[17:16:16.553] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C7.dat
[17:16:16.553] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C8.dat
[17:16:16.553] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C9.dat
[17:16:16.554] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C10.dat
[17:16:16.554] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C11.dat
[17:16:16.554] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C12.dat
[17:16:16.554] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C13.dat
[17:16:16.554] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C14.dat
[17:16:16.554] <TB1> INFO: write dac parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//dacParameters35_C15.dat
[17:16:16.945] <TB1> INFO: Expecting 41600 events.
[17:16:21.188] <TB1> INFO: 41600 events read in total (3464ms).
[17:16:21.190] <TB1> INFO: Test took 4628ms.
[17:16:22.047] <TB1> INFO: Expecting 41600 events.
[17:16:26.263] <TB1> INFO: 41600 events read in total (3437ms).
[17:16:26.265] <TB1> INFO: Test took 4727ms.
[17:16:26.980] <TB1> INFO: Expecting 41600 events.
[17:16:31.301] <TB1> INFO: 41600 events read in total (3542ms).
[17:16:31.316] <TB1> INFO: Test took 4712ms.
[17:16:31.627] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:31.760] <TB1> INFO: Expecting 2560 events.
[17:16:32.795] <TB1> INFO: 2560 events read in total (256ms).
[17:16:32.804] <TB1> INFO: Test took 1177ms.
[17:16:32.822] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:33.368] <TB1> INFO: Expecting 2560 events.
[17:16:34.394] <TB1> INFO: 2560 events read in total (248ms).
[17:16:34.395] <TB1> INFO: Test took 1573ms.
[17:16:34.398] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:34.968] <TB1> INFO: Expecting 2560 events.
[17:16:36.016] <TB1> INFO: 2560 events read in total (270ms).
[17:16:36.023] <TB1> INFO: Test took 1625ms.
[17:16:36.031] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:36.590] <TB1> INFO: Expecting 2560 events.
[17:16:37.616] <TB1> INFO: 2560 events read in total (247ms).
[17:16:37.617] <TB1> INFO: Test took 1586ms.
[17:16:37.626] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:38.189] <TB1> INFO: Expecting 2560 events.
[17:16:39.220] <TB1> INFO: 2560 events read in total (250ms).
[17:16:39.221] <TB1> INFO: Test took 1595ms.
[17:16:39.231] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:39.793] <TB1> INFO: Expecting 2560 events.
[17:16:40.820] <TB1> INFO: 2560 events read in total (248ms).
[17:16:40.820] <TB1> INFO: Test took 1590ms.
[17:16:40.826] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:41.393] <TB1> INFO: Expecting 2560 events.
[17:16:42.420] <TB1> INFO: 2560 events read in total (248ms).
[17:16:42.420] <TB1> INFO: Test took 1594ms.
[17:16:42.428] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:42.994] <TB1> INFO: Expecting 2560 events.
[17:16:44.020] <TB1> INFO: 2560 events read in total (247ms).
[17:16:44.021] <TB1> INFO: Test took 1593ms.
[17:16:44.029] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:44.596] <TB1> INFO: Expecting 2560 events.
[17:16:45.624] <TB1> INFO: 2560 events read in total (249ms).
[17:16:45.624] <TB1> INFO: Test took 1595ms.
[17:16:45.629] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:46.210] <TB1> INFO: Expecting 2560 events.
[17:16:47.245] <TB1> INFO: 2560 events read in total (249ms).
[17:16:47.249] <TB1> INFO: Test took 1621ms.
[17:16:47.256] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:47.820] <TB1> INFO: Expecting 2560 events.
[17:16:48.862] <TB1> INFO: 2560 events read in total (252ms).
[17:16:48.867] <TB1> INFO: Test took 1611ms.
[17:16:48.875] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:49.434] <TB1> INFO: Expecting 2560 events.
[17:16:50.461] <TB1> INFO: 2560 events read in total (248ms).
[17:16:50.462] <TB1> INFO: Test took 1587ms.
[17:16:50.472] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:51.033] <TB1> INFO: Expecting 2560 events.
[17:16:52.060] <TB1> INFO: 2560 events read in total (248ms).
[17:16:52.060] <TB1> INFO: Test took 1589ms.
[17:16:52.068] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:52.645] <TB1> INFO: Expecting 2560 events.
[17:16:53.679] <TB1> INFO: 2560 events read in total (248ms).
[17:16:53.679] <TB1> INFO: Test took 1611ms.
[17:16:53.687] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:54.253] <TB1> INFO: Expecting 2560 events.
[17:16:55.297] <TB1> INFO: 2560 events read in total (256ms).
[17:16:55.298] <TB1> INFO: Test took 1611ms.
[17:16:55.307] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:55.870] <TB1> INFO: Expecting 2560 events.
[17:16:56.907] <TB1> INFO: 2560 events read in total (251ms).
[17:16:56.916] <TB1> INFO: Test took 1609ms.
[17:16:56.931] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:57.480] <TB1> INFO: Expecting 2560 events.
[17:16:58.512] <TB1> INFO: 2560 events read in total (254ms).
[17:16:58.520] <TB1> INFO: Test took 1589ms.
[17:16:58.528] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:16:59.085] <TB1> INFO: Expecting 2560 events.
[17:17:00.123] <TB1> INFO: 2560 events read in total (252ms).
[17:17:00.124] <TB1> INFO: Test took 1597ms.
[17:17:00.126] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:00.702] <TB1> INFO: Expecting 2560 events.
[17:17:01.735] <TB1> INFO: 2560 events read in total (255ms).
[17:17:01.746] <TB1> INFO: Test took 1620ms.
[17:17:01.760] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:02.308] <TB1> INFO: Expecting 2560 events.
[17:17:03.339] <TB1> INFO: 2560 events read in total (252ms).
[17:17:03.348] <TB1> INFO: Test took 1588ms.
[17:17:03.370] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:03.912] <TB1> INFO: Expecting 2560 events.
[17:17:04.941] <TB1> INFO: 2560 events read in total (251ms).
[17:17:04.948] <TB1> INFO: Test took 1579ms.
[17:17:04.957] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:05.529] <TB1> INFO: Expecting 2560 events.
[17:17:06.559] <TB1> INFO: 2560 events read in total (251ms).
[17:17:06.560] <TB1> INFO: Test took 1603ms.
[17:17:06.562] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:07.140] <TB1> INFO: Expecting 2560 events.
[17:17:08.171] <TB1> INFO: 2560 events read in total (252ms).
[17:17:08.171] <TB1> INFO: Test took 1609ms.
[17:17:08.174] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:08.745] <TB1> INFO: Expecting 2560 events.
[17:17:09.773] <TB1> INFO: 2560 events read in total (250ms).
[17:17:09.773] <TB1> INFO: Test took 1600ms.
[17:17:09.776] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:10.346] <TB1> INFO: Expecting 2560 events.
[17:17:11.377] <TB1> INFO: 2560 events read in total (252ms).
[17:17:11.377] <TB1> INFO: Test took 1601ms.
[17:17:11.380] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:11.950] <TB1> INFO: Expecting 2560 events.
[17:17:12.980] <TB1> INFO: 2560 events read in total (252ms).
[17:17:12.980] <TB1> INFO: Test took 1600ms.
[17:17:12.983] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:13.554] <TB1> INFO: Expecting 2560 events.
[17:17:14.585] <TB1> INFO: 2560 events read in total (253ms).
[17:17:14.585] <TB1> INFO: Test took 1602ms.
[17:17:14.588] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:15.159] <TB1> INFO: Expecting 2560 events.
[17:17:16.199] <TB1> INFO: 2560 events read in total (261ms).
[17:17:16.200] <TB1> INFO: Test took 1612ms.
[17:17:16.202] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:16.773] <TB1> INFO: Expecting 2560 events.
[17:17:17.812] <TB1> INFO: 2560 events read in total (260ms).
[17:17:17.812] <TB1> INFO: Test took 1610ms.
[17:17:17.815] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:18.385] <TB1> INFO: Expecting 2560 events.
[17:17:19.415] <TB1> INFO: 2560 events read in total (252ms).
[17:17:19.416] <TB1> INFO: Test took 1601ms.
[17:17:19.419] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:19.990] <TB1> INFO: Expecting 2560 events.
[17:17:21.022] <TB1> INFO: 2560 events read in total (253ms).
[17:17:21.022] <TB1> INFO: Test took 1604ms.
[17:17:21.025] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:17:21.598] <TB1> INFO: Expecting 2560 events.
[17:17:22.632] <TB1> INFO: 2560 events read in total (256ms).
[17:17:22.632] <TB1> INFO: Test took 1607ms.
[17:17:23.409] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 551 seconds
[17:17:23.410] <TB1> INFO: PH scale (per ROC): 84 73 85 96 83 82 81 84 84 85 82 80 87 85 85 80
[17:17:23.410] <TB1> INFO: PH offset (per ROC): 143 169 157 162 151 174 154 157 143 150 176 158 148 144 163 156
[17:17:23.429] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[17:17:23.429] <TB1> INFO: Decoding statistics:
[17:17:23.429] <TB1> INFO: General information:
[17:17:23.429] <TB1> INFO: 16bit words read: 66436
[17:17:23.429] <TB1> INFO: valid events total: 5120
[17:17:23.430] <TB1> INFO: empty events: 2622
[17:17:23.430] <TB1> INFO: valid events with pixels: 2498
[17:17:23.430] <TB1> INFO: valid pixel hits: 2498
[17:17:23.430] <TB1> INFO: Event errors: 0
[17:17:23.430] <TB1> INFO: start marker: 0
[17:17:23.430] <TB1> INFO: stop marker: 0
[17:17:23.430] <TB1> INFO: overflow: 0
[17:17:23.430] <TB1> INFO: invalid 5bit words: 0
[17:17:23.430] <TB1> INFO: invalid XOR eye diagram: 0
[17:17:23.430] <TB1> INFO: TBM errors: 0
[17:17:23.430] <TB1> INFO: flawed TBM headers: 0
[17:17:23.430] <TB1> INFO: flawed TBM trailers: 0
[17:17:23.430] <TB1> INFO: event ID mismatches: 0
[17:17:23.430] <TB1> INFO: ROC errors: 0
[17:17:23.430] <TB1> INFO: missing ROC header(s): 0
[17:17:23.430] <TB1> INFO: misplaced readback start: 0
[17:17:23.430] <TB1> INFO: Pixel decoding errors: 0
[17:17:23.430] <TB1> INFO: pixel data incomplete: 0
[17:17:23.430] <TB1> INFO: pixel address: 0
[17:17:23.430] <TB1> INFO: pulse height fill bit: 0
[17:17:23.430] <TB1> INFO: buffer corruption: 0
[17:17:24.087] <TB1> INFO: ######################################################################
[17:17:24.087] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[17:17:24.087] <TB1> INFO: ######################################################################
[17:17:24.128] <TB1> INFO: scanning low vcal = 10
[17:17:24.793] <TB1> INFO: Expecting 41600 events.
[17:17:28.376] <TB1> INFO: 41600 events read in total (2804ms).
[17:17:28.376] <TB1> INFO: Test took 4248ms.
[17:17:28.378] <TB1> INFO: scanning low vcal = 20
[17:17:28.961] <TB1> INFO: Expecting 41600 events.
[17:17:32.398] <TB1> INFO: 41600 events read in total (2655ms).
[17:17:32.399] <TB1> INFO: Test took 4021ms.
[17:17:32.402] <TB1> INFO: scanning low vcal = 30
[17:17:32.976] <TB1> INFO: Expecting 41600 events.
[17:17:36.420] <TB1> INFO: 41600 events read in total (2666ms).
[17:17:36.421] <TB1> INFO: Test took 4016ms.
[17:17:36.423] <TB1> INFO: scanning low vcal = 40
[17:17:36.983] <TB1> INFO: Expecting 41600 events.
[17:17:40.929] <TB1> INFO: 41600 events read in total (3168ms).
[17:17:40.931] <TB1> INFO: Test took 4508ms.
[17:17:40.937] <TB1> INFO: scanning low vcal = 50
[17:17:41.396] <TB1> INFO: Expecting 41600 events.
[17:17:45.559] <TB1> INFO: 41600 events read in total (3385ms).
[17:17:45.560] <TB1> INFO: Test took 4623ms.
[17:17:45.568] <TB1> INFO: scanning low vcal = 60
[17:17:45.997] <TB1> INFO: Expecting 41600 events.
[17:17:50.082] <TB1> INFO: 41600 events read in total (3307ms).
[17:17:50.091] <TB1> INFO: Test took 4522ms.
[17:17:50.109] <TB1> INFO: scanning low vcal = 70
[17:17:50.546] <TB1> INFO: Expecting 41600 events.
[17:17:54.608] <TB1> INFO: 41600 events read in total (3284ms).
[17:17:54.609] <TB1> INFO: Test took 4500ms.
[17:17:54.616] <TB1> INFO: scanning low vcal = 80
[17:17:55.056] <TB1> INFO: Expecting 41600 events.
[17:17:59.065] <TB1> INFO: 41600 events read in total (3230ms).
[17:17:59.067] <TB1> INFO: Test took 4451ms.
[17:17:59.079] <TB1> INFO: scanning low vcal = 90
[17:17:59.550] <TB1> INFO: Expecting 41600 events.
[17:18:03.839] <TB1> INFO: 41600 events read in total (3510ms).
[17:18:03.840] <TB1> INFO: Test took 4762ms.
[17:18:03.850] <TB1> INFO: scanning low vcal = 100
[17:18:04.273] <TB1> INFO: Expecting 41600 events.
[17:18:08.288] <TB1> INFO: 41600 events read in total (3236ms).
[17:18:08.290] <TB1> INFO: Test took 4440ms.
[17:18:08.296] <TB1> INFO: scanning low vcal = 110
[17:18:08.765] <TB1> INFO: Expecting 41600 events.
[17:18:12.832] <TB1> INFO: 41600 events read in total (3288ms).
[17:18:12.833] <TB1> INFO: Test took 4537ms.
[17:18:12.845] <TB1> INFO: scanning low vcal = 120
[17:18:13.277] <TB1> INFO: Expecting 41600 events.
[17:18:17.371] <TB1> INFO: 41600 events read in total (3315ms).
[17:18:17.377] <TB1> INFO: Test took 4531ms.
[17:18:17.393] <TB1> INFO: scanning low vcal = 130
[17:18:17.791] <TB1> INFO: Expecting 41600 events.
[17:18:21.877] <TB1> INFO: 41600 events read in total (3307ms).
[17:18:21.879] <TB1> INFO: Test took 4486ms.
[17:18:21.884] <TB1> INFO: scanning low vcal = 140
[17:18:22.341] <TB1> INFO: Expecting 41600 events.
[17:18:26.478] <TB1> INFO: 41600 events read in total (3352ms).
[17:18:26.480] <TB1> INFO: Test took 4596ms.
[17:18:26.492] <TB1> INFO: scanning low vcal = 150
[17:18:26.958] <TB1> INFO: Expecting 41600 events.
[17:18:30.995] <TB1> INFO: 41600 events read in total (3258ms).
[17:18:30.000] <TB1> INFO: Test took 4497ms.
[17:18:31.013] <TB1> INFO: scanning low vcal = 160
[17:18:31.445] <TB1> INFO: Expecting 41600 events.
[17:18:35.541] <TB1> INFO: 41600 events read in total (3318ms).
[17:18:35.548] <TB1> INFO: Test took 4535ms.
[17:18:35.557] <TB1> INFO: scanning low vcal = 170
[17:18:35.978] <TB1> INFO: Expecting 41600 events.
[17:18:40.155] <TB1> INFO: 41600 events read in total (3399ms).
[17:18:40.157] <TB1> INFO: Test took 4599ms.
[17:18:40.174] <TB1> INFO: scanning low vcal = 180
[17:18:40.657] <TB1> INFO: Expecting 41600 events.
[17:18:44.734] <TB1> INFO: 41600 events read in total (3298ms).
[17:18:44.735] <TB1> INFO: Test took 4562ms.
[17:18:44.749] <TB1> INFO: scanning low vcal = 190
[17:18:45.168] <TB1> INFO: Expecting 41600 events.
[17:18:49.269] <TB1> INFO: 41600 events read in total (3317ms).
[17:18:49.270] <TB1> INFO: Test took 4521ms.
[17:18:49.286] <TB1> INFO: scanning low vcal = 200
[17:18:49.716] <TB1> INFO: Expecting 41600 events.
[17:18:53.765] <TB1> INFO: 41600 events read in total (3269ms).
[17:18:53.769] <TB1> INFO: Test took 4482ms.
[17:18:53.782] <TB1> INFO: scanning low vcal = 210
[17:18:54.229] <TB1> INFO: Expecting 41600 events.
[17:18:58.260] <TB1> INFO: 41600 events read in total (3252ms).
[17:18:58.262] <TB1> INFO: Test took 4480ms.
[17:18:58.269] <TB1> INFO: scanning low vcal = 220
[17:18:58.704] <TB1> INFO: Expecting 41600 events.
[17:19:02.712] <TB1> INFO: 41600 events read in total (3229ms).
[17:19:02.713] <TB1> INFO: Test took 4444ms.
[17:19:02.720] <TB1> INFO: scanning low vcal = 230
[17:19:03.192] <TB1> INFO: Expecting 41600 events.
[17:19:07.250] <TB1> INFO: 41600 events read in total (3280ms).
[17:19:07.251] <TB1> INFO: Test took 4531ms.
[17:19:07.259] <TB1> INFO: scanning low vcal = 240
[17:19:07.680] <TB1> INFO: Expecting 41600 events.
[17:19:11.662] <TB1> INFO: 41600 events read in total (3203ms).
[17:19:11.663] <TB1> INFO: Test took 4403ms.
[17:19:11.669] <TB1> INFO: scanning low vcal = 250
[17:19:12.146] <TB1> INFO: Expecting 41600 events.
[17:19:16.176] <TB1> INFO: 41600 events read in total (3252ms).
[17:19:16.177] <TB1> INFO: Test took 4508ms.
[17:19:16.186] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[17:19:16.628] <TB1> INFO: Expecting 41600 events.
[17:19:20.632] <TB1> INFO: 41600 events read in total (3224ms).
[17:19:20.634] <TB1> INFO: Test took 4448ms.
[17:19:20.639] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[17:19:21.110] <TB1> INFO: Expecting 41600 events.
[17:19:25.096] <TB1> INFO: 41600 events read in total (3208ms).
[17:19:25.097] <TB1> INFO: Test took 4458ms.
[17:19:25.105] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[17:19:25.580] <TB1> INFO: Expecting 41600 events.
[17:19:29.588] <TB1> INFO: 41600 events read in total (3229ms).
[17:19:29.589] <TB1> INFO: Test took 4484ms.
[17:19:29.600] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[17:19:30.060] <TB1> INFO: Expecting 41600 events.
[17:19:34.133] <TB1> INFO: 41600 events read in total (3294ms).
[17:19:34.134] <TB1> INFO: Test took 4533ms.
[17:19:34.140] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[17:19:34.616] <TB1> INFO: Expecting 41600 events.
[17:19:38.613] <TB1> INFO: 41600 events read in total (3218ms).
[17:19:38.614] <TB1> INFO: Test took 4474ms.
[17:19:39.284] <TB1> INFO: PixTestGainPedestal::measure() done
[17:20:34.968] <TB1> INFO: PixTestGainPedestal::fit() done
[17:20:34.968] <TB1> INFO: non-linearity mean: 0.962 0.922 0.956 0.960 0.953 0.962 0.957 0.953 0.959 0.955 0.960 0.956 0.952 0.958 0.959 0.957
[17:20:34.968] <TB1> INFO: non-linearity RMS: 0.006 0.029 0.007 0.005 0.005 0.006 0.008 0.007 0.006 0.007 0.005 0.005 0.007 0.006 0.006 0.006
[17:20:34.969] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//phCalibrationFitErr35_C0.dat
[17:20:34.995] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//phCalibrationFitErr35_C1.dat
[17:20:35.018] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//phCalibrationFitErr35_C2.dat
[17:20:35.040] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//phCalibrationFitErr35_C3.dat
[17:20:35.064] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//phCalibrationFitErr35_C4.dat
[17:20:35.087] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//phCalibrationFitErr35_C5.dat
[17:20:35.110] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//phCalibrationFitErr35_C6.dat
[17:20:35.134] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//phCalibrationFitErr35_C7.dat
[17:20:35.157] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//phCalibrationFitErr35_C8.dat
[17:20:35.180] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//phCalibrationFitErr35_C9.dat
[17:20:35.203] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//phCalibrationFitErr35_C10.dat
[17:20:35.226] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//phCalibrationFitErr35_C11.dat
[17:20:35.249] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//phCalibrationFitErr35_C12.dat
[17:20:35.273] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//phCalibrationFitErr35_C13.dat
[17:20:35.297] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//phCalibrationFitErr35_C14.dat
[17:20:35.321] <TB1> INFO: write gain/ped parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//phCalibrationFitErr35_C15.dat
[17:20:35.346] <TB1> INFO: PixTestGainPedestal::doTest() done, duration: 191 seconds
[17:20:35.346] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[17:20:35.346] <TB1> INFO: Decoding statistics:
[17:20:35.346] <TB1> INFO: General information:
[17:20:35.346] <TB1> INFO: 16bit words read: 2325424
[17:20:35.346] <TB1> INFO: valid events total: 83200
[17:20:35.346] <TB1> INFO: empty events: 0
[17:20:35.346] <TB1> INFO: valid events with pixels: 83200
[17:20:35.346] <TB1> INFO: valid pixel hits: 663512
[17:20:35.346] <TB1> INFO: Event errors: 0
[17:20:35.346] <TB1> INFO: start marker: 0
[17:20:35.347] <TB1> INFO: stop marker: 0
[17:20:35.347] <TB1> INFO: overflow: 0
[17:20:35.347] <TB1> INFO: invalid 5bit words: 0
[17:20:35.347] <TB1> INFO: invalid XOR eye diagram: 0
[17:20:35.347] <TB1> INFO: TBM errors: 0
[17:20:35.347] <TB1> INFO: flawed TBM headers: 0
[17:20:35.347] <TB1> INFO: flawed TBM trailers: 0
[17:20:35.347] <TB1> INFO: event ID mismatches: 0
[17:20:35.347] <TB1> INFO: ROC errors: 0
[17:20:35.347] <TB1> INFO: missing ROC header(s): 0
[17:20:35.347] <TB1> INFO: misplaced readback start: 0
[17:20:35.347] <TB1> INFO: Pixel decoding errors: 0
[17:20:35.347] <TB1> INFO: pixel data incomplete: 0
[17:20:35.347] <TB1> INFO: pixel address: 0
[17:20:35.347] <TB1> INFO: pulse height fill bit: 0
[17:20:35.347] <TB1> INFO: buffer corruption: 0
[17:20:35.360] <TB1> INFO: readReadbackCal: /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C0.dat .. /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C15.dat
[17:20:35.409] <TB1> INFO: ######################################################################
[17:20:35.409] <TB1> INFO: PixTestTrim::doTest()
[17:20:35.409] <TB1> INFO: ######################################################################
[17:20:35.410] <TB1> INFO: PixTestReadback::RES sent once
[17:20:49.949] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C0.dat
[17:20:49.951] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C1.dat
[17:20:49.951] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C2.dat
[17:20:49.951] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C3.dat
[17:20:49.951] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C4.dat
[17:20:49.951] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C5.dat
[17:20:49.951] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C6.dat
[17:20:49.951] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C7.dat
[17:20:49.952] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C8.dat
[17:20:49.952] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C9.dat
[17:20:49.952] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C10.dat
[17:20:49.952] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C11.dat
[17:20:49.952] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C12.dat
[17:20:49.952] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C13.dat
[17:20:49.952] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C14.dat
[17:20:49.953] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C15.dat
[17:20:49.989] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[17:20:49.991] <TB1> INFO: PixTestReadback::RES sent once
[17:21:02.556] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C0.dat
[17:21:02.556] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C1.dat
[17:21:02.556] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C2.dat
[17:21:02.556] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C3.dat
[17:21:02.556] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C4.dat
[17:21:02.556] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C5.dat
[17:21:02.557] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C6.dat
[17:21:02.557] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C7.dat
[17:21:02.557] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C8.dat
[17:21:02.557] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C9.dat
[17:21:02.557] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C10.dat
[17:21:02.557] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C11.dat
[17:21:02.557] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C12.dat
[17:21:02.557] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C13.dat
[17:21:02.557] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C14.dat
[17:21:02.558] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C15.dat
[17:21:02.600] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[17:21:02.600] <TB1> INFO: PixTestReadback::RES sent once
[17:21:12.260] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[17:21:12.260] <TB1> INFO: Vbg will be calibrated using Vd calibration
[17:21:12.260] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 147.1calibrated Vbg = 1.20577 :::*/*/*/*/
[17:21:12.260] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 151.4calibrated Vbg = 1.2032 :::*/*/*/*/
[17:21:12.260] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 162.2calibrated Vbg = 1.20761 :::*/*/*/*/
[17:21:12.260] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 147.8calibrated Vbg = 1.20987 :::*/*/*/*/
[17:21:12.261] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 152.8calibrated Vbg = 1.21762 :::*/*/*/*/
[17:21:12.261] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 156.3calibrated Vbg = 1.21612 :::*/*/*/*/
[17:21:12.261] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 154.6calibrated Vbg = 1.2107 :::*/*/*/*/
[17:21:12.261] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 152calibrated Vbg = 1.2157 :::*/*/*/*/
[17:21:12.261] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 146.6calibrated Vbg = 1.21396 :::*/*/*/*/
[17:21:12.261] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 151.6calibrated Vbg = 1.22305 :::*/*/*/*/
[17:21:12.261] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 162calibrated Vbg = 1.21969 :::*/*/*/*/
[17:21:12.261] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 152.2calibrated Vbg = 1.22136 :::*/*/*/*/
[17:21:12.261] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 149.9calibrated Vbg = 1.20778 :::*/*/*/*/
[17:21:12.261] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 152.5calibrated Vbg = 1.20014 :::*/*/*/*/
[17:21:12.261] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 160.4calibrated Vbg = 1.20653 :::*/*/*/*/
[17:21:12.261] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 150.2calibrated Vbg = 1.19953 :::*/*/*/*/
[17:21:12.268] <TB1> INFO: PixTestReadback::RES sent once
[17:24:22.040] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C0.dat
[17:24:22.040] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C1.dat
[17:24:22.040] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C2.dat
[17:24:22.040] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C3.dat
[17:24:22.041] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C4.dat
[17:24:22.041] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C5.dat
[17:24:22.041] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C6.dat
[17:24:22.041] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C7.dat
[17:24:22.041] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C8.dat
[17:24:22.041] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C9.dat
[17:24:22.041] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C10.dat
[17:24:22.041] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C11.dat
[17:24:22.041] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C12.dat
[17:24:22.041] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C13.dat
[17:24:22.041] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C14.dat
[17:24:22.042] <TB1> INFO: write readback calibration parameters into /home/michelecms/DTB/elComandante/DATA/M3518_FullQualification_2015-10-30_10h46m_1446198407//002_Fulltest_m20//readbackCal_C15.dat
[17:24:22.075] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[17:24:22.076] <TB1> INFO: PixTestReadback::doTest() done
[17:24:22.076] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[17:24:22.076] <TB1> INFO: Decoding statistics:
[17:24:22.076] <TB1> INFO: General information:
[17:24:22.076] <TB1> INFO: 16bit words read: 768
[17:24:22.076] <TB1> INFO: valid events total: 64
[17:24:22.076] <TB1> INFO: empty events: 64
[17:24:22.076] <TB1> INFO: valid events with pixels: 0
[17:24:22.076] <TB1> INFO: valid pixel hits: 0
[17:24:22.076] <TB1> INFO: Event errors: 0
[17:24:22.076] <TB1> INFO: start marker: 0
[17:24:22.076] <TB1> INFO: stop marker: 0
[17:24:22.076] <TB1> INFO: overflow: 0
[17:24:22.076] <TB1> INFO: invalid 5bit words: 0
[17:24:22.076] <TB1> INFO: invalid XOR eye diagram: 0
[17:24:22.076] <TB1> INFO: TBM errors: 0
[17:24:22.077] <TB1> INFO: flawed TBM headers: 0
[17:24:22.077] <TB1> INFO: flawed TBM trailers: 0
[17:24:22.077] <TB1> INFO: event ID mismatches: 0
[17:24:22.077] <TB1> INFO: ROC errors: 0
[17:24:22.077] <TB1> INFO: missing ROC header(s): 0
[17:24:22.077] <TB1> INFO: misplaced readback start: 0
[17:24:22.077] <TB1> INFO: Pixel decoding errors: 0
[17:24:22.077] <TB1> INFO: pixel data incomplete: 0
[17:24:22.077] <TB1> INFO: pixel address: 0
[17:24:22.077] <TB1> INFO: pulse height fill bit: 0
[17:24:22.077] <TB1> INFO: buffer corruption: 0
[17:24:22.311] <TB1> INFO: Decoding statistics:
[17:24:22.311] <TB1> INFO: General information:
[17:24:22.312] <TB1> INFO: 16bit words read: 9388294
[17:24:22.312] <TB1> INFO: valid events total: 551744
[17:24:22.312] <TB1> INFO: empty events: 304588
[17:24:22.312] <TB1> INFO: valid events with pixels: 247156
[17:24:22.312] <TB1> INFO: valid pixel hits: 1383683
[17:24:22.312] <TB1> INFO: Event errors: 0
[17:24:22.312] <TB1> INFO: start marker: 0
[17:24:22.312] <TB1> INFO: stop marker: 0
[17:24:22.312] <TB1> INFO: overflow: 0
[17:24:22.312] <TB1> INFO: invalid 5bit words: 0
[17:24:22.312] <TB1> INFO: invalid XOR eye diagram: 0
[17:24:22.312] <TB1> INFO: TBM errors: 0
[17:24:22.312] <TB1> INFO: flawed TBM headers: 0
[17:24:22.312] <TB1> INFO: flawed TBM trailers: 0
[17:24:22.312] <TB1> INFO: event ID mismatches: 0
[17:24:22.312] <TB1> INFO: ROC errors: 0
[17:24:22.312] <TB1> INFO: missing ROC header(s): 0
[17:24:22.312] <TB1> INFO: misplaced readback start: 0
[17:24:22.312] <TB1> INFO: Pixel decoding errors: 0
[17:24:22.312] <TB1> INFO: pixel data incomplete: 0
[17:24:22.312] <TB1> INFO: pixel address: 0
[17:24:22.312] <TB1> INFO: pulse height fill bit: 0
[17:24:22.312] <TB1> INFO: buffer corruption: 0
[17:24:22.318] <TB1> INFO: enter test to run
[17:24:22.319] <TB1> INFO: test: no parameter change
[17:24:23.613] <TB1> QUIET: Connection to board 129 closed.
[17:24:23.662] <TB1> INFO: pXar: this is the end, my friend