[09:39:25.836] <TB2> INFO: *** Welcome to pxar ***
[09:39:25.836] <TB2> INFO: *** Today: 2015/11/03
[09:39:26.213] <TB2> INFO: *** Version: 9da6
[09:39:26.213] <TB2> INFO: readRocDacs: /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C0.dat .. /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C15.dat
[09:39:26.215] <TB2> INFO: readTbmDacs: /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//tbmParameters_C0a.dat .. /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//tbmParameters_C0b.dat
[09:39:26.215] <TB2> INFO: readMaskFile: /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//defaultMaskFile.dat
[09:39:26.215] <TB2> INFO: readTrimFile: /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters_C0.dat .. /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters_C15.dat
[09:39:26.295] <TB2> INFO: clk: 4
[09:39:26.295] <TB2> INFO: ctr: 4
[09:39:26.295] <TB2> INFO: sda: 19
[09:39:26.295] <TB2> INFO: tin: 9
[09:39:26.295] <TB2> INFO: level: 15
[09:39:26.295] <TB2> INFO: triggerdelay: 0
[09:39:26.295] <TB2> QUIET: Instanciating API for pxar v2.6.0+26~g89693ff
[09:39:26.295] <TB2> INFO: Log level: INFO
[09:39:26.303] <TB2> INFO: Found DTB DTB_WXC55Z
[09:39:26.313] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[09:39:26.316] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.2
SW version: 4.5
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[09:39:26.318] <TB2> INFO: RPC call hashes of host and DTB match: 398089610
[09:39:27.876] <TB2> INFO: DUT info:
[09:39:27.876] <TB2> INFO: The DUT currently contains the following objects:
[09:39:27.876] <TB2> INFO: 2 TBM Cores tbm08c (2 ON)
[09:39:27.876] <TB2> INFO: TBM Core alpha (0): 7 registers set
[09:39:27.876] <TB2> INFO: TBM Core beta (1): 7 registers set
[09:39:27.876] <TB2> INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[09:39:27.876] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[09:39:27.876] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[09:39:27.876] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[09:39:27.876] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[09:39:27.876] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[09:39:27.876] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[09:39:27.876] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[09:39:27.876] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[09:39:27.876] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[09:39:27.876] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[09:39:27.876] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[09:39:27.876] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[09:39:27.876] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[09:39:27.876] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[09:39:27.876] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[09:39:27.876] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[09:39:28.278] <TB2> INFO: enter 'restricted' command line mode
[09:39:28.278] <TB2> INFO: enter test to run
[09:39:28.278] <TB2> INFO: test: pretest no parameter change
[09:39:28.278] <TB2> INFO: running: pretest
[09:39:28.287] <TB2> INFO: ######################################################################
[09:39:28.287] <TB2> INFO: PixTestPretest::doTest()
[09:39:28.287] <TB2> INFO: ######################################################################
[09:39:28.288] <TB2> INFO: ----------------------------------------------------------------------
[09:39:28.288] <TB2> INFO: PixTestPretest::programROC()
[09:39:28.288] <TB2> INFO: ----------------------------------------------------------------------
[09:39:46.306] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[09:39:46.306] <TB2> INFO: IA differences per ROC: 16.0 16.0 18.4 16.8 16.0 15.2 16.0 15.2 18.4 15.2 17.6 16.8 18.4 16.8 16.0 16.8
[09:39:46.381] <TB2> INFO: ----------------------------------------------------------------------
[09:39:46.381] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[09:39:46.381] <TB2> INFO: ----------------------------------------------------------------------
[09:40:07.655] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 370.6 mA = 23.1625 mA/ROC
[09:40:07.655] <TB2> INFO: i(loss) [mA/ROC]: 18.5 19.3 19.3 19.3 20.1 19.3 19.3 20.1 19.3 20.1 19.3 20.1 17.7 18.5 18.5 18.5
[09:40:07.690] <TB2> INFO: ----------------------------------------------------------------------
[09:40:07.690] <TB2> INFO: PixTestPretest::findTiming()
[09:40:07.690] <TB2> INFO: ----------------------------------------------------------------------
[09:40:07.690] <TB2> INFO: PixTestCmd::init()
[09:40:08.284] <TB2> WARNING: Not unmasking DUT, not setting Calibrate bits!
[09:41:55.247] <TB2> INFO: TBM phases: 160MHz: 5, 400MHz: 2, TBM delays: ROC(0/1):2, header/trailer: 1, token: 0
[09:41:55.247] <TB2> INFO: (success/tries = 100/100), width = 3
[09:41:55.249] <TB2> INFO: ----------------------------------------------------------------------
[09:41:55.249] <TB2> INFO: PixTestPretest::findWorkingPixel()
[09:41:55.249] <TB2> INFO: ----------------------------------------------------------------------
[09:41:55.390] <TB2> INFO: Expecting 231680 events.
[09:41:59.999] <TB2> ERROR: <datapipe.cc/CheckEventValidity:L488> Channel 0 Number of ROCs (1) != Token Chain Length (8)
[09:42:00.002] <TB2> ERROR: <datapipe.cc/CheckEventID:L461> Channel 0 Event ID mismatch: local ID (21) != TBM ID (2)
[09:42:03.105] <TB2> INFO: 231680 events read in total (7000ms).
[09:42:03.110] <TB2> INFO: Test took 7854ms.
[09:42:03.517] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[09:42:03.549] <TB2> INFO: ----------------------------------------------------------------------
[09:42:03.549] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[09:42:03.549] <TB2> INFO: ----------------------------------------------------------------------
[09:42:03.684] <TB2> INFO: Expecting 231680 events.
[09:42:12.250] <TB2> INFO: 231680 events read in total (7851ms).
[09:42:12.255] <TB2> INFO: Test took 8703ms.
[09:42:12.654] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[09:42:12.654] <TB2> INFO: CalDel: 94 117 144 123 115 83 112 111 118 132 115 117 127 128 122 103
[09:42:12.654] <TB2> INFO: VthrComp: 51 51 56 51 52 51 51 52 51 52 51 53 52 52 51 59
[09:42:12.658] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C0.dat
[09:42:12.658] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C1.dat
[09:42:12.658] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C2.dat
[09:42:12.659] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C3.dat
[09:42:12.659] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C4.dat
[09:42:12.659] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C5.dat
[09:42:12.659] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C6.dat
[09:42:12.660] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C7.dat
[09:42:12.660] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C8.dat
[09:42:12.660] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C9.dat
[09:42:12.660] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C10.dat
[09:42:12.660] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C11.dat
[09:42:12.661] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C12.dat
[09:42:12.661] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C13.dat
[09:42:12.661] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C14.dat
[09:42:12.661] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters_C15.dat
[09:42:12.661] <TB2> INFO: write tbm parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//tbmParameters_C0a.dat
[09:42:12.662] <TB2> INFO: write tbm parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//tbmParameters_C0b.dat
[09:42:12.662] <TB2> INFO: PixTestPretest::doTest() done, duration: 164 seconds
[09:42:12.741] <TB2> INFO: enter test to run
[09:42:12.741] <TB2> INFO: test: fulltest no parameter change
[09:42:12.741] <TB2> INFO: running: fulltest
[09:42:12.741] <TB2> INFO: ######################################################################
[09:42:12.741] <TB2> INFO: PixTestFullTest::doTest()
[09:42:12.741] <TB2> INFO: ######################################################################
[09:42:12.742] <TB2> INFO: ######################################################################
[09:42:12.742] <TB2> INFO: PixTestAlive::doTest()
[09:42:12.742] <TB2> INFO: ######################################################################
[09:42:12.744] <TB2> INFO: ----------------------------------------------------------------------
[09:42:12.744] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:42:12.744] <TB2> INFO: ----------------------------------------------------------------------
[09:42:13.052] <TB2> INFO: Expecting 41600 events.
[09:42:17.359] <TB2> INFO: 41600 events read in total (3592ms).
[09:42:17.360] <TB2> INFO: Test took 4615ms.
[09:42:17.367] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:42:17.740] <TB2> INFO: PixTestAlive::aliveTest() done
[09:42:17.740] <TB2> INFO: number of dead pixels (per ROC): 2 3 0 3 0 0 3 0 0 1 0 0 1 0 1 2
[09:42:17.744] <TB2> INFO: ----------------------------------------------------------------------
[09:42:17.744] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:42:17.744] <TB2> INFO: ----------------------------------------------------------------------
[09:42:18.059] <TB2> INFO: Expecting 41600 events.
[09:42:21.106] <TB2> INFO: 41600 events read in total (2332ms).
[09:42:21.106] <TB2> INFO: Test took 3360ms.
[09:42:21.106] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:42:21.107] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[09:42:21.509] <TB2> INFO: PixTestAlive::maskTest() done
[09:42:21.509] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:42:21.510] <TB2> INFO: ----------------------------------------------------------------------
[09:42:21.510] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[09:42:21.510] <TB2> INFO: ----------------------------------------------------------------------
[09:42:21.827] <TB2> INFO: Expecting 41600 events.
[09:42:26.240] <TB2> INFO: 41600 events read in total (3698ms).
[09:42:26.240] <TB2> INFO: Test took 4728ms.
[09:42:26.247] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:42:26.622] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[09:42:26.622] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:42:26.622] <TB2> INFO: PixTestAlive::doTest() done, duration: 13 seconds
[09:42:26.622] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:42:26.622] <TB2> INFO: Decoding statistics:
[09:42:26.622] <TB2> INFO: General information:
[09:42:26.622] <TB2> INFO: 16bit words read: 0
[09:42:26.622] <TB2> INFO: valid events total: 0
[09:42:26.622] <TB2> INFO: empty events: 0
[09:42:26.622] <TB2> INFO: valid events with pixels: 0
[09:42:26.622] <TB2> INFO: valid pixel hits: 0
[09:42:26.622] <TB2> INFO: Event errors: 0
[09:42:26.622] <TB2> INFO: start marker: 0
[09:42:26.622] <TB2> INFO: stop marker: 0
[09:42:26.622] <TB2> INFO: overflow: 0
[09:42:26.622] <TB2> INFO: invalid 5bit words: 0
[09:42:26.622] <TB2> INFO: invalid XOR eye diagram: 0
[09:42:26.622] <TB2> INFO: TBM errors: 0
[09:42:26.622] <TB2> INFO: flawed TBM headers: 0
[09:42:26.622] <TB2> INFO: flawed TBM trailers: 0
[09:42:26.622] <TB2> INFO: event ID mismatches: 0
[09:42:26.622] <TB2> INFO: ROC errors: 0
[09:42:26.622] <TB2> INFO: missing ROC header(s): 0
[09:42:26.622] <TB2> INFO: misplaced readback start: 0
[09:42:26.623] <TB2> INFO: Pixel decoding errors: 0
[09:42:26.623] <TB2> INFO: pixel data incomplete: 0
[09:42:26.623] <TB2> INFO: pixel address: 0
[09:42:26.623] <TB2> INFO: pulse height fill bit: 0
[09:42:26.623] <TB2> INFO: buffer corruption: 0
[09:42:26.637] <TB2> INFO: ######################################################################
[09:42:26.637] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[09:42:26.637] <TB2> INFO: ######################################################################
[09:42:26.640] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[09:42:26.662] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[09:42:26.662] <TB2> INFO: run 1 of 1
[09:42:26.970] <TB2> INFO: Expecting 3120000 events.
[09:43:21.667] <TB2> INFO: 1272240 events read in total (53982ms).
[09:44:12.737] <TB2> INFO: 2530850 events read in total (105052ms).
[09:44:36.510] <TB2> INFO: 3120000 events read in total (128825ms).
[09:44:36.560] <TB2> INFO: Test took 129899ms.
[09:44:36.641] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:45:01.250] <TB2> INFO: PixTestBBMap::doTest() done, duration: 154 seconds
[09:45:01.250] <TB2> INFO: number of dead bumps (per ROC): 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[09:45:01.250] <TB2> INFO: separation cut (per ROC): 135 137 139 132 133 144 129 144 142 139 134 144 131 138 131 143
[09:45:01.250] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:45:01.250] <TB2> INFO: Decoding statistics:
[09:45:01.250] <TB2> INFO: General information:
[09:45:01.250] <TB2> INFO: 16bit words read: 0
[09:45:01.250] <TB2> INFO: valid events total: 0
[09:45:01.250] <TB2> INFO: empty events: 0
[09:45:01.250] <TB2> INFO: valid events with pixels: 0
[09:45:01.250] <TB2> INFO: valid pixel hits: 0
[09:45:01.250] <TB2> INFO: Event errors: 0
[09:45:01.250] <TB2> INFO: start marker: 0
[09:45:01.250] <TB2> INFO: stop marker: 0
[09:45:01.250] <TB2> INFO: overflow: 0
[09:45:01.250] <TB2> INFO: invalid 5bit words: 0
[09:45:01.250] <TB2> INFO: invalid XOR eye diagram: 0
[09:45:01.250] <TB2> INFO: TBM errors: 0
[09:45:01.250] <TB2> INFO: flawed TBM headers: 0
[09:45:01.250] <TB2> INFO: flawed TBM trailers: 0
[09:45:01.250] <TB2> INFO: event ID mismatches: 0
[09:45:01.250] <TB2> INFO: ROC errors: 0
[09:45:01.250] <TB2> INFO: missing ROC header(s): 0
[09:45:01.250] <TB2> INFO: misplaced readback start: 0
[09:45:01.250] <TB2> INFO: Pixel decoding errors: 0
[09:45:01.250] <TB2> INFO: pixel data incomplete: 0
[09:45:01.250] <TB2> INFO: pixel address: 0
[09:45:01.250] <TB2> INFO: pulse height fill bit: 0
[09:45:01.250] <TB2> INFO: buffer corruption: 0
[09:45:01.336] <TB2> INFO: ######################################################################
[09:45:01.337] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[09:45:01.337] <TB2> INFO: ######################################################################
[09:45:01.337] <TB2> INFO: ----------------------------------------------------------------------
[09:45:01.337] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[09:45:01.337] <TB2> INFO: ----------------------------------------------------------------------
[09:45:01.337] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 150 (-1/-1) hits flags = 528 (plus default)
[09:45:01.347] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[09:45:01.347] <TB2> INFO: run 1 of 1
[09:45:01.661] <TB2> INFO: Expecting 26208000 events.
[09:45:38.620] <TB2> INFO: 1360100 events read in total (36245ms).
[09:46:14.791] <TB2> INFO: 2690050 events read in total (72416ms).
[09:46:49.898] <TB2> INFO: 4015850 events read in total (107523ms).
[09:47:26.509] <TB2> INFO: 5339200 events read in total (144134ms).
[09:48:02.926] <TB2> INFO: 6663150 events read in total (180551ms).
[09:48:39.546] <TB2> INFO: 7978200 events read in total (217171ms).
[09:49:15.217] <TB2> INFO: 9296100 events read in total (252842ms).
[09:49:50.675] <TB2> INFO: 10607200 events read in total (288300ms).
[09:50:26.695] <TB2> INFO: 11911750 events read in total (324320ms).
[09:51:03.137] <TB2> INFO: 13212700 events read in total (360762ms).
[09:51:39.184] <TB2> INFO: 14489500 events read in total (396809ms).
[09:52:15.210] <TB2> INFO: 15767700 events read in total (432835ms).
[09:52:51.100] <TB2> INFO: 17037850 events read in total (468725ms).
[09:53:27.062] <TB2> INFO: 18307800 events read in total (504687ms).
[09:54:03.098] <TB2> INFO: 19573750 events read in total (540723ms).
[09:54:38.658] <TB2> INFO: 20840900 events read in total (576283ms).
[09:55:14.493] <TB2> INFO: 22103250 events read in total (612118ms).
[09:55:50.926] <TB2> INFO: 23367600 events read in total (648551ms).
[09:56:25.664] <TB2> INFO: 24630000 events read in total (683289ms).
[09:57:02.321] <TB2> INFO: 25905500 events read in total (719946ms).
[09:57:11.416] <TB2> INFO: 26208000 events read in total (729041ms).
[09:57:11.441] <TB2> INFO: Test took 730094ms.
[09:57:11.491] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:57:11.575] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:57:13.030] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:57:14.410] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:57:15.868] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:57:17.302] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:57:18.713] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:57:20.052] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:57:21.443] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:57:22.812] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:57:24.315] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:57:25.682] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:57:27.073] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:57:28.527] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:57:30.084] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:57:31.459] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:57:32.893] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[09:57:34.471] <TB2> INFO: PixTestScurves::scurves() done
[09:57:34.471] <TB2> INFO: Vcal mean: 106.72 116.34 119.50 113.86 114.10 122.21 109.58 119.70 114.26 117.97 120.17 119.83 119.07 118.92 113.00 125.73
[09:57:34.471] <TB2> INFO: Vcal RMS: 5.36 6.68 8.44 6.69 5.17 6.02 5.97 6.58 5.45 5.98 5.90 6.02 6.18 6.76 5.47 7.07
[09:57:34.471] <TB2> INFO: PixTestScurves::fullTest() done, duration: 753 seconds
[09:57:34.471] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:57:34.471] <TB2> INFO: Decoding statistics:
[09:57:34.471] <TB2> INFO: General information:
[09:57:34.471] <TB2> INFO: 16bit words read: 0
[09:57:34.471] <TB2> INFO: valid events total: 0
[09:57:34.471] <TB2> INFO: empty events: 0
[09:57:34.471] <TB2> INFO: valid events with pixels: 0
[09:57:34.471] <TB2> INFO: valid pixel hits: 0
[09:57:34.471] <TB2> INFO: Event errors: 0
[09:57:34.471] <TB2> INFO: start marker: 0
[09:57:34.471] <TB2> INFO: stop marker: 0
[09:57:34.471] <TB2> INFO: overflow: 0
[09:57:34.471] <TB2> INFO: invalid 5bit words: 0
[09:57:34.471] <TB2> INFO: invalid XOR eye diagram: 0
[09:57:34.471] <TB2> INFO: TBM errors: 0
[09:57:34.471] <TB2> INFO: flawed TBM headers: 0
[09:57:34.471] <TB2> INFO: flawed TBM trailers: 0
[09:57:34.471] <TB2> INFO: event ID mismatches: 0
[09:57:34.471] <TB2> INFO: ROC errors: 0
[09:57:34.471] <TB2> INFO: missing ROC header(s): 0
[09:57:34.471] <TB2> INFO: misplaced readback start: 0
[09:57:34.471] <TB2> INFO: Pixel decoding errors: 0
[09:57:34.471] <TB2> INFO: pixel data incomplete: 0
[09:57:34.471] <TB2> INFO: pixel address: 0
[09:57:34.471] <TB2> INFO: pulse height fill bit: 0
[09:57:34.471] <TB2> INFO: buffer corruption: 0
[09:57:34.555] <TB2> INFO: ######################################################################
[09:57:34.555] <TB2> INFO: PixTestTrim::doTest()
[09:57:34.555] <TB2> INFO: ######################################################################
[09:57:34.556] <TB2> INFO: ----------------------------------------------------------------------
[09:57:34.556] <TB2> INFO: PixTestTrim::trimTest() ntrig = 10, vcal = 35
[09:57:34.556] <TB2> INFO: ----------------------------------------------------------------------
[09:57:34.659] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[09:57:34.659] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 10 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[09:57:34.669] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[09:57:34.669] <TB2> INFO: run 1 of 1
[09:57:35.008] <TB2> INFO: Expecting 6281600 events.
[09:58:17.909] <TB2> INFO: 1465830 events read in total (42186ms).
[09:59:05.978] <TB2> INFO: 2921570 events read in total (90255ms).
[09:59:50.277] <TB2> INFO: 4368880 events read in total (134555ms).
[10:00:37.431] <TB2> INFO: 5816910 events read in total (181708ms).
[10:00:52.786] <TB2> INFO: 6281600 events read in total (197063ms).
[10:00:52.815] <TB2> INFO: Test took 198147ms.
[10:00:52.866] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:01:12.926] <TB2> INFO: ROC 0 VthrComp = 105
[10:01:12.927] <TB2> INFO: ROC 1 VthrComp = 107
[10:01:12.927] <TB2> INFO: ROC 2 VthrComp = 107
[10:01:12.927] <TB2> INFO: ROC 3 VthrComp = 103
[10:01:12.927] <TB2> INFO: ROC 4 VthrComp = 108
[10:01:12.927] <TB2> INFO: ROC 5 VthrComp = 108
[10:01:12.927] <TB2> INFO: ROC 6 VthrComp = 104
[10:01:12.927] <TB2> INFO: ROC 7 VthrComp = 111
[10:01:12.927] <TB2> INFO: ROC 8 VthrComp = 109
[10:01:12.928] <TB2> INFO: ROC 9 VthrComp = 109
[10:01:12.928] <TB2> INFO: ROC 10 VthrComp = 109
[10:01:12.928] <TB2> INFO: ROC 11 VthrComp = 112
[10:01:12.928] <TB2> INFO: ROC 12 VthrComp = 105
[10:01:12.928] <TB2> INFO: ROC 13 VthrComp = 109
[10:01:12.928] <TB2> INFO: ROC 14 VthrComp = 105
[10:01:12.928] <TB2> INFO: ROC 15 VthrComp = 112
[10:01:12.929] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[10:01:12.929] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 10 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[10:01:12.938] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:01:12.938] <TB2> INFO: run 1 of 1
[10:01:13.250] <TB2> INFO: Expecting 6281600 events.
[10:01:47.812] <TB2> INFO: 914870 events read in total (33847ms).
[10:02:27.923] <TB2> INFO: 1827350 events read in total (73958ms).
[10:03:08.108] <TB2> INFO: 2739100 events read in total (114143ms).
[10:03:47.211] <TB2> INFO: 3644410 events read in total (153246ms).
[10:04:24.844] <TB2> INFO: 4539660 events read in total (190879ms).
[10:05:04.674] <TB2> INFO: 5429620 events read in total (230709ms).
[10:05:43.485] <TB2> INFO: 6281600 events read in total (269520ms).
[10:05:43.555] <TB2> INFO: Test took 270618ms.
[10:05:43.712] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:06:11.737] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 61.202 for pixel 22/4 mean/min/max = 48.0772/34.945/61.2095
[10:06:11.738] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 64.9799 for pixel 23/57 mean/min/max = 49.9448/34.8203/65.0692
[10:06:11.738] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 73.544 for pixel 5/1 mean/min/max = 54.2703/34.8311/73.7095
[10:06:11.738] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 64.6344 for pixel 0/3 mean/min/max = 48.987/33.2714/64.7025
[10:06:11.739] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 62.2613 for pixel 5/57 mean/min/max = 48.6175/34.7338/62.5012
[10:06:11.739] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 73.3412 for pixel 23/79 mean/min/max = 56.6196/39.8576/73.3816
[10:06:11.739] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 63.7254 for pixel 6/15 mean/min/max = 48.879/34.0165/63.7415
[10:06:11.739] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 69.764 for pixel 0/70 mean/min/max = 53.4093/36.9426/69.876
[10:06:11.740] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 65.4255 for pixel 24/13 mean/min/max = 50.6041/35.7122/65.496
[10:06:11.740] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 66.4424 for pixel 4/30 mean/min/max = 50.9518/35.3644/66.5393
[10:06:11.740] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 66.4779 for pixel 0/55 mean/min/max = 50.9332/35.0919/66.7746
[10:06:11.741] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 67.2844 for pixel 3/79 mean/min/max = 51.2746/35.2478/67.3013
[10:06:11.741] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 66.7695 for pixel 20/75 mean/min/max = 50.9733/34.8949/67.0517
[10:06:11.741] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 66.5896 for pixel 1/25 mean/min/max = 50.5138/34.3606/66.667
[10:06:11.741] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 63.0963 for pixel 36/1 mean/min/max = 48.8916/34.5724/63.2108
[10:06:11.742] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 73.6848 for pixel 0/69 mean/min/max = 55.6288/37.3652/73.8925
[10:06:11.742] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:06:11.874] <TB2> INFO: Expecting 514560 events.
[10:06:22.551] <TB2> INFO: 514560 events read in total (9962ms).
[10:06:22.556] <TB2> INFO: Expecting 514560 events.
[10:06:32.045] <TB2> INFO: 514560 events read in total (8823ms).
[10:06:32.052] <TB2> INFO: Expecting 514560 events.
[10:06:40.933] <TB2> INFO: 514560 events read in total (8211ms).
[10:06:40.943] <TB2> INFO: Expecting 514560 events.
[10:06:49.756] <TB2> INFO: 514560 events read in total (8146ms).
[10:06:49.767] <TB2> INFO: Expecting 514560 events.
[10:06:59.032] <TB2> INFO: 514560 events read in total (8599ms).
[10:06:59.044] <TB2> INFO: Expecting 514560 events.
[10:07:09.041] <TB2> INFO: 514560 events read in total (9339ms).
[10:07:09.058] <TB2> INFO: Expecting 514560 events.
[10:07:18.980] <TB2> INFO: 514560 events read in total (9279ms).
[10:07:18.996] <TB2> INFO: Expecting 514560 events.
[10:07:29.272] <TB2> INFO: 514560 events read in total (9616ms).
[10:07:29.292] <TB2> INFO: Expecting 514560 events.
[10:07:39.513] <TB2> INFO: 514560 events read in total (9572ms).
[10:07:39.534] <TB2> INFO: Expecting 514560 events.
[10:07:50.000] <TB2> INFO: 514560 events read in total (9815ms).
[10:07:50.022] <TB2> INFO: Expecting 514560 events.
[10:08:00.033] <TB2> INFO: 514560 events read in total (9361ms).
[10:08:00.063] <TB2> INFO: Expecting 514560 events.
[10:08:10.473] <TB2> INFO: 514560 events read in total (9774ms).
[10:08:10.505] <TB2> INFO: Expecting 514560 events.
[10:08:20.830] <TB2> INFO: 514560 events read in total (9689ms).
[10:08:20.859] <TB2> INFO: Expecting 514560 events.
[10:08:31.326] <TB2> INFO: 514560 events read in total (9821ms).
[10:08:31.364] <TB2> INFO: Expecting 514560 events.
[10:08:41.451] <TB2> INFO: 514560 events read in total (9462ms).
[10:08:41.485] <TB2> INFO: Expecting 514560 events.
[10:08:52.108] <TB2> INFO: 514560 events read in total (9981ms).
[10:08:52.184] <TB2> INFO: Test took 160442ms.
[10:08:53.238] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 10 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[10:08:53.247] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:08:53.247] <TB2> INFO: run 1 of 1
[10:08:53.571] <TB2> INFO: Expecting 6281600 events.
[10:09:34.174] <TB2> INFO: 881430 events read in total (39888ms).
[10:10:12.315] <TB2> INFO: 1759950 events read in total (78029ms).
[10:10:49.694] <TB2> INFO: 2638490 events read in total (115408ms).
[10:11:26.794] <TB2> INFO: 3513580 events read in total (152508ms).
[10:12:01.270] <TB2> INFO: 4378240 events read in total (186984ms).
[10:12:38.173] <TB2> INFO: 5237770 events read in total (223887ms).
[10:13:15.289] <TB2> INFO: 6095920 events read in total (261003ms).
[10:13:23.742] <TB2> INFO: 6281600 events read in total (269456ms).
[10:13:23.802] <TB2> INFO: Test took 270555ms.
[10:13:23.948] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:13:50.889] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 0.034099 .. 255.000000
[10:13:50.973] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 10 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[10:13:50.982] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:13:50.982] <TB2> INFO: run 1 of 1
[10:13:51.293] <TB2> INFO: Expecting 10649600 events.
[10:14:24.911] <TB2> INFO: 826020 events read in total (32903ms).
[10:15:00.277] <TB2> INFO: 1652200 events read in total (68269ms).
[10:15:36.592] <TB2> INFO: 2478240 events read in total (104584ms).
[10:16:13.492] <TB2> INFO: 3304700 events read in total (141484ms).
[10:16:50.247] <TB2> INFO: 4131240 events read in total (178239ms).
[10:17:26.653] <TB2> INFO: 4957950 events read in total (214645ms).
[10:18:03.931] <TB2> INFO: 5785480 events read in total (251923ms).
[10:18:41.361] <TB2> INFO: 6613940 events read in total (289353ms).
[10:19:17.074] <TB2> INFO: 7442390 events read in total (325066ms).
[10:19:50.545] <TB2> INFO: 8270150 events read in total (358537ms).
[10:20:26.813] <TB2> INFO: 9098220 events read in total (394805ms).
[10:21:02.627] <TB2> INFO: 9926470 events read in total (430619ms).
[10:21:34.069] <TB2> INFO: 10649600 events read in total (462061ms).
[10:21:34.250] <TB2> INFO: Test took 463269ms.
[10:21:34.554] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:22:05.538] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 16.302887 .. 49.242373
[10:22:05.626] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 10 dacrange: 6 .. 59 (-1/-1) hits flags = 528 (plus default)
[10:22:05.635] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:22:05.635] <TB2> INFO: run 1 of 1
[10:22:05.955] <TB2> INFO: Expecting 2246400 events.
[10:22:42.378] <TB2> INFO: 1117020 events read in total (35709ms).
[10:23:24.281] <TB2> INFO: 2232720 events read in total (77612ms).
[10:23:25.186] <TB2> INFO: 2246400 events read in total (78518ms).
[10:23:25.207] <TB2> INFO: Test took 79573ms.
[10:23:25.250] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:23:40.286] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 1.030593 .. 46.207054
[10:23:40.366] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 10 dacrange: 1 .. 56 (-1/-1) hits flags = 528 (plus default)
[10:23:40.374] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:23:40.375] <TB2> INFO: run 1 of 1
[10:23:40.679] <TB2> INFO: Expecting 2329600 events.
[10:24:22.901] <TB2> INFO: 1185310 events read in total (41507ms).
[10:25:04.571] <TB2> INFO: 2329600 events read in total (83177ms).
[10:25:04.589] <TB2> INFO: Test took 84215ms.
[10:25:04.628] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:25:19.561] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 5.500000 .. 46.012754
[10:25:19.642] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 10 dacrange: 5 .. 56 (-1/-1) hits flags = 528 (plus default)
[10:25:19.651] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:25:19.651] <TB2> INFO: run 1 of 1
[10:25:19.956] <TB2> INFO: Expecting 2163200 events.
[10:26:00.694] <TB2> INFO: 1158010 events read in total (40023ms).
[10:26:37.566] <TB2> INFO: 2163200 events read in total (76895ms).
[10:26:37.586] <TB2> INFO: Test took 77935ms.
[10:26:37.620] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:26:52.143] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[10:26:52.143] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 10 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[10:26:52.152] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:26:52.152] <TB2> INFO: run 1 of 1
[10:26:52.490] <TB2> INFO: Expecting 1705600 events.
[10:27:33.577] <TB2> INFO: 1077230 events read in total (40373ms).
[10:27:57.553] <TB2> INFO: 1705600 events read in total (64349ms).
[10:27:57.574] <TB2> INFO: Test took 65421ms.
[10:27:57.612] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:28:10.938] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C0.dat
[10:28:10.938] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C1.dat
[10:28:10.938] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C2.dat
[10:28:10.938] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C3.dat
[10:28:10.939] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C4.dat
[10:28:10.939] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C5.dat
[10:28:10.939] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C6.dat
[10:28:10.939] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C7.dat
[10:28:10.939] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C8.dat
[10:28:10.939] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C9.dat
[10:28:10.939] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C10.dat
[10:28:10.939] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C11.dat
[10:28:10.939] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C12.dat
[10:28:10.939] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C13.dat
[10:28:10.940] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C14.dat
[10:28:10.940] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C15.dat
[10:28:10.940] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters35_C0.dat
[10:28:10.948] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters35_C1.dat
[10:28:10.957] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters35_C2.dat
[10:28:10.965] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters35_C3.dat
[10:28:10.971] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters35_C4.dat
[10:28:10.980] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters35_C5.dat
[10:28:10.988] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters35_C6.dat
[10:28:10.997] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters35_C7.dat
[10:28:11.005] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters35_C8.dat
[10:28:11.011] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters35_C9.dat
[10:28:11.017] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters35_C10.dat
[10:28:11.023] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters35_C11.dat
[10:28:11.029] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters35_C12.dat
[10:28:11.035] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters35_C13.dat
[10:28:11.041] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters35_C14.dat
[10:28:11.047] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//trimParameters35_C15.dat
[10:28:11.055] <TB2> INFO: PixTestTrim::trimTest() done
[10:28:11.055] <TB2> INFO: vtrim: 109 116 115 114 118 154 115 134 135 119 119 121 120 131 119 139
[10:28:11.055] <TB2> INFO: vthrcomp: 105 107 107 103 108 108 104 111 109 109 109 112 105 109 105 112
[10:28:11.055] <TB2> INFO: vcal mean: 35.01 34.95 34.91 34.95 35.01 35.01 34.94 34.98 34.98 34.98 34.99 35.04 35.00 34.95 34.98 34.92
[10:28:11.055] <TB2> INFO: vcal RMS: 3.61 1.35 1.03 1.33 1.03 1.03 1.54 0.99 0.96 1.10 1.01 0.93 1.14 1.15 1.15 1.33
[10:28:11.055] <TB2> INFO: bits mean: 8.72 8.47 7.43 8.77 8.70 6.85 9.06 6.95 8.56 8.29 8.30 7.40 8.33 8.81 8.71 7.26
[10:28:11.055] <TB2> INFO: bits RMS: 2.45 2.43 2.52 2.59 2.44 2.08 2.34 2.42 2.25 2.36 2.40 2.63 2.40 2.36 2.45 2.30
[10:28:11.063] <TB2> INFO: ----------------------------------------------------------------------
[10:28:11.063] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 10, vtrims = 254 126 63 32
[10:28:11.063] <TB2> INFO: ----------------------------------------------------------------------
[10:28:11.065] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 10 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[10:28:11.074] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:28:11.074] <TB2> INFO: run 1 of 1
[10:28:11.379] <TB2> INFO: Expecting 8320000 events.
[10:28:51.300] <TB2> INFO: 1351820 events read in total (39206ms).
[10:29:35.599] <TB2> INFO: 2689570 events read in total (83505ms).
[10:30:18.439] <TB2> INFO: 4016470 events read in total (126346ms).
[10:31:00.826] <TB2> INFO: 5321700 events read in total (168732ms).
[10:31:43.264] <TB2> INFO: 6621870 events read in total (211170ms).
[10:32:25.091] <TB2> INFO: 7918910 events read in total (252997ms).
[10:32:37.365] <TB2> INFO: 8320000 events read in total (265271ms).
[10:32:37.407] <TB2> INFO: Test took 266333ms.
[10:32:37.475] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:33:03.060] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 10 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[10:33:03.069] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:33:03.069] <TB2> INFO: run 1 of 1
[10:33:03.375] <TB2> INFO: Expecting 8528000 events.
[10:33:44.135] <TB2> INFO: 1255950 events read in total (40046ms).
[10:34:28.217] <TB2> INFO: 2500600 events read in total (84128ms).
[10:35:07.020] <TB2> INFO: 3737440 events read in total (122931ms).
[10:35:51.203] <TB2> INFO: 4960670 events read in total (167114ms).
[10:36:30.691] <TB2> INFO: 6174390 events read in total (206602ms).
[10:37:09.262] <TB2> INFO: 7385660 events read in total (245173ms).
[10:37:49.934] <TB2> INFO: 8528000 events read in total (285845ms).
[10:37:49.973] <TB2> INFO: Test took 286904ms.
[10:37:50.065] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:38:17.869] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 10 dacrange: 0 .. 208 (-1/-1) hits flags = 528 (plus default)
[10:38:17.878] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:38:17.878] <TB2> INFO: run 1 of 1
[10:38:18.181] <TB2> INFO: Expecting 8694400 events.
[10:38:58.592] <TB2> INFO: 1240880 events read in total (39696ms).
[10:39:41.806] <TB2> INFO: 2469960 events read in total (82910ms).
[10:40:24.833] <TB2> INFO: 3693810 events read in total (125937ms).
[10:41:07.982] <TB2> INFO: 4903880 events read in total (169086ms).
[10:41:44.254] <TB2> INFO: 6104780 events read in total (205358ms).
[10:42:27.087] <TB2> INFO: 7302630 events read in total (248191ms).
[10:43:10.205] <TB2> INFO: 8500430 events read in total (291309ms).
[10:43:17.197] <TB2> INFO: 8694400 events read in total (298301ms).
[10:43:17.234] <TB2> INFO: Test took 299356ms.
[10:43:17.325] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:43:45.340] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 10 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[10:43:45.348] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:43:45.348] <TB2> INFO: run 1 of 1
[10:43:45.653] <TB2> INFO: Expecting 8528000 events.
[10:44:31.522] <TB2> INFO: 1256030 events read in total (45154ms).
[10:45:15.373] <TB2> INFO: 2500380 events read in total (89005ms).
[10:45:59.108] <TB2> INFO: 3736880 events read in total (132740ms).
[10:46:36.629] <TB2> INFO: 4959650 events read in total (170261ms).
[10:47:20.238] <TB2> INFO: 6173300 events read in total (213870ms).
[10:48:04.463] <TB2> INFO: 7384420 events read in total (258095ms).
[10:48:46.268] <TB2> INFO: 8528000 events read in total (299900ms).
[10:48:46.326] <TB2> INFO: Test took 300978ms.
[10:48:46.421] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:49:11.403] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 10 dacrange: 0 .. 202 (-1/-1) hits flags = 528 (plus default)
[10:49:11.411] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[10:49:11.411] <TB2> INFO: run 1 of 1
[10:49:11.717] <TB2> INFO: Expecting 8444800 events.
[10:49:55.889] <TB2> INFO: 1262640 events read in total (43453ms).
[10:50:38.926] <TB2> INFO: 2514570 events read in total (86490ms).
[10:51:21.363] <TB2> INFO: 3759040 events read in total (128927ms).
[10:52:00.194] <TB2> INFO: 4987400 events read in total (167758ms).
[10:52:43.866] <TB2> INFO: 6207750 events read in total (211430ms).
[10:53:27.482] <TB2> INFO: 7425550 events read in total (255046ms).
[10:54:04.242] <TB2> INFO: 8444800 events read in total (291806ms).
[10:54:04.280] <TB2> INFO: Test took 292869ms.
[10:54:04.366] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:54:29.650] <TB2> INFO: PixTestTrim::trimBitTest() done
[10:54:29.651] <TB2> INFO: PixTestTrim::doTest() done, duration: 3415 seconds
[10:54:29.651] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:54:29.651] <TB2> INFO: Decoding statistics:
[10:54:29.651] <TB2> INFO: General information:
[10:54:29.651] <TB2> INFO: 16bit words read: 0
[10:54:29.651] <TB2> INFO: valid events total: 0
[10:54:29.651] <TB2> INFO: empty events: 0
[10:54:29.651] <TB2> INFO: valid events with pixels: 0
[10:54:29.651] <TB2> INFO: valid pixel hits: 0
[10:54:29.651] <TB2> INFO: Event errors: 0
[10:54:29.651] <TB2> INFO: start marker: 0
[10:54:29.651] <TB2> INFO: stop marker: 0
[10:54:29.651] <TB2> INFO: overflow: 0
[10:54:29.651] <TB2> INFO: invalid 5bit words: 0
[10:54:29.651] <TB2> INFO: invalid XOR eye diagram: 0
[10:54:29.651] <TB2> INFO: TBM errors: 0
[10:54:29.651] <TB2> INFO: flawed TBM headers: 0
[10:54:29.651] <TB2> INFO: flawed TBM trailers: 0
[10:54:29.651] <TB2> INFO: event ID mismatches: 0
[10:54:29.651] <TB2> INFO: ROC errors: 0
[10:54:29.651] <TB2> INFO: missing ROC header(s): 0
[10:54:29.651] <TB2> INFO: misplaced readback start: 0
[10:54:29.651] <TB2> INFO: Pixel decoding errors: 0
[10:54:29.651] <TB2> INFO: pixel data incomplete: 0
[10:54:29.651] <TB2> INFO: pixel address: 0
[10:54:29.651] <TB2> INFO: pulse height fill bit: 0
[10:54:29.651] <TB2> INFO: buffer corruption: 0
[10:54:30.323] <TB2> INFO: ######################################################################
[10:54:30.323] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[10:54:30.323] <TB2> INFO: ######################################################################
[10:54:30.627] <TB2> INFO: Expecting 41600 events.
[10:54:34.919] <TB2> INFO: 41600 events read in total (3577ms).
[10:54:34.920] <TB2> INFO: Test took 4596ms.
[10:54:34.927] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:54:35.592] <TB2> INFO: Expecting 41600 events.
[10:54:39.592] <TB2> INFO: 41600 events read in total (3285ms).
[10:54:39.593] <TB2> INFO: Test took 4319ms.
[10:54:39.599] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:54:40.044] <TB2> INFO: Expecting 41600 events.
[10:54:44.069] <TB2> INFO: 41600 events read in total (3310ms).
[10:54:44.069] <TB2> INFO: Test took 4347ms.
[10:54:44.076] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[10:54:44.519] <TB2> INFO: Expecting 2560 events.
[10:54:45.489] <TB2> INFO: 2560 events read in total (255ms).
[10:54:45.489] <TB2> INFO: Test took 1407ms.
[10:54:45.996] <TB2> INFO: Expecting 2560 events.
[10:54:46.952] <TB2> INFO: 2560 events read in total (241ms).
[10:54:46.952] <TB2> INFO: Test took 1463ms.
[10:54:47.460] <TB2> INFO: Expecting 2560 events.
[10:54:48.415] <TB2> INFO: 2560 events read in total (241ms).
[10:54:48.415] <TB2> INFO: Test took 1463ms.
[10:54:48.923] <TB2> INFO: Expecting 2560 events.
[10:54:49.878] <TB2> INFO: 2560 events read in total (241ms).
[10:54:49.878] <TB2> INFO: Test took 1462ms.
[10:54:50.386] <TB2> INFO: Expecting 2560 events.
[10:54:51.341] <TB2> INFO: 2560 events read in total (241ms).
[10:54:51.342] <TB2> INFO: Test took 1464ms.
[10:54:51.849] <TB2> INFO: Expecting 2560 events.
[10:54:52.805] <TB2> INFO: 2560 events read in total (241ms).
[10:54:52.805] <TB2> INFO: Test took 1463ms.
[10:54:53.313] <TB2> INFO: Expecting 2560 events.
[10:54:54.311] <TB2> INFO: 2560 events read in total (284ms).
[10:54:54.311] <TB2> INFO: Test took 1505ms.
[10:54:54.819] <TB2> INFO: Expecting 2560 events.
[10:54:55.789] <TB2> INFO: 2560 events read in total (255ms).
[10:54:55.789] <TB2> INFO: Test took 1477ms.
[10:54:56.297] <TB2> INFO: Expecting 2560 events.
[10:54:57.267] <TB2> INFO: 2560 events read in total (255ms).
[10:54:57.267] <TB2> INFO: Test took 1478ms.
[10:54:57.774] <TB2> INFO: Expecting 2560 events.
[10:54:58.730] <TB2> INFO: 2560 events read in total (241ms).
[10:54:58.730] <TB2> INFO: Test took 1463ms.
[10:54:59.239] <TB2> INFO: Expecting 2560 events.
[10:55:00.238] <TB2> INFO: 2560 events read in total (284ms).
[10:55:00.238] <TB2> INFO: Test took 1508ms.
[10:55:00.745] <TB2> INFO: Expecting 2560 events.
[10:55:01.721] <TB2> INFO: 2560 events read in total (261ms).
[10:55:01.721] <TB2> INFO: Test took 1483ms.
[10:55:02.229] <TB2> INFO: Expecting 2560 events.
[10:55:03.190] <TB2> INFO: 2560 events read in total (246ms).
[10:55:03.190] <TB2> INFO: Test took 1469ms.
[10:55:03.698] <TB2> INFO: Expecting 2560 events.
[10:55:04.670] <TB2> INFO: 2560 events read in total (257ms).
[10:55:04.670] <TB2> INFO: Test took 1479ms.
[10:55:05.179] <TB2> INFO: Expecting 2560 events.
[10:55:06.169] <TB2> INFO: 2560 events read in total (275ms).
[10:55:06.169] <TB2> INFO: Test took 1498ms.
[10:55:06.677] <TB2> INFO: Expecting 2560 events.
[10:55:07.654] <TB2> INFO: 2560 events read in total (262ms).
[10:55:07.654] <TB2> INFO: Test took 1484ms.
[10:55:07.658] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:55:08.164] <TB2> INFO: Expecting 655360 events.
[10:55:21.727] <TB2> INFO: 655360 events read in total (12848ms).
[10:55:21.738] <TB2> INFO: Expecting 655360 events.
[10:55:34.187] <TB2> INFO: 655360 events read in total (11867ms).
[10:55:34.200] <TB2> INFO: Expecting 655360 events.
[10:55:47.919] <TB2> INFO: 655360 events read in total (13147ms).
[10:55:47.938] <TB2> INFO: Expecting 655360 events.
[10:56:01.527] <TB2> INFO: 655360 events read in total (13027ms).
[10:56:01.545] <TB2> INFO: Expecting 655360 events.
[10:56:14.042] <TB2> INFO: 655360 events read in total (11901ms).
[10:56:14.068] <TB2> INFO: Expecting 655360 events.
[10:56:27.508] <TB2> INFO: 655360 events read in total (12855ms).
[10:56:27.537] <TB2> INFO: Expecting 655360 events.
[10:56:38.894] <TB2> INFO: 655360 events read in total (10781ms).
[10:56:38.925] <TB2> INFO: Expecting 655360 events.
[10:56:50.392] <TB2> INFO: 655360 events read in total (10891ms).
[10:56:50.428] <TB2> INFO: Expecting 655360 events.
[10:57:02.993] <TB2> INFO: 655360 events read in total (11994ms).
[10:57:03.035] <TB2> INFO: Expecting 655360 events.
[10:57:16.493] <TB2> INFO: 655360 events read in total (12905ms).
[10:57:16.540] <TB2> INFO: Expecting 655360 events.
[10:57:30.220] <TB2> INFO: 655360 events read in total (13143ms).
[10:57:30.263] <TB2> INFO: Expecting 655360 events.
[10:57:43.115] <TB2> INFO: 655360 events read in total (12290ms).
[10:57:43.161] <TB2> INFO: Expecting 655360 events.
[10:57:55.769] <TB2> INFO: 655360 events read in total (12041ms).
[10:57:55.824] <TB2> INFO: Expecting 655360 events.
[10:58:09.545] <TB2> INFO: 655360 events read in total (13185ms).
[10:58:09.610] <TB2> INFO: Expecting 655360 events.
[10:58:23.119] <TB2> INFO: 655360 events read in total (12976ms).
[10:58:23.179] <TB2> INFO: Expecting 655360 events.
[10:58:35.697] <TB2> INFO: 655360 events read in total (11978ms).
[10:58:35.756] <TB2> INFO: Test took 208098ms.
[10:58:35.835] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:58:36.144] <TB2> INFO: Expecting 655360 events.
[10:58:49.341] <TB2> INFO: 655360 events read in total (12482ms).
[10:58:49.353] <TB2> INFO: Expecting 655360 events.
[10:59:02.812] <TB2> INFO: 655360 events read in total (12891ms).
[10:59:02.828] <TB2> INFO: Expecting 655360 events.
[10:59:16.195] <TB2> INFO: 655360 events read in total (12779ms).
[10:59:16.211] <TB2> INFO: Expecting 655360 events.
[10:59:28.437] <TB2> INFO: 655360 events read in total (11617ms).
[10:59:28.456] <TB2> INFO: Expecting 655360 events.
[10:59:42.148] <TB2> INFO: 655360 events read in total (13076ms).
[10:59:42.171] <TB2> INFO: Expecting 655360 events.
[10:59:55.962] <TB2> INFO: 655360 events read in total (13195ms).
[10:59:55.988] <TB2> INFO: Expecting 655360 events.
[11:00:08.811] <TB2> INFO: 655360 events read in total (12229ms).
[11:00:08.841] <TB2> INFO: Expecting 655360 events.
[11:00:21.322] <TB2> INFO: 655360 events read in total (11903ms).
[11:00:21.363] <TB2> INFO: Expecting 655360 events.
[11:00:34.579] <TB2> INFO: 655360 events read in total (12640ms).
[11:00:34.615] <TB2> INFO: Expecting 655360 events.
[11:00:48.142] <TB2> INFO: 655360 events read in total (12941ms).
[11:00:48.197] <TB2> INFO: Expecting 655360 events.
[11:01:00.788] <TB2> INFO: 655360 events read in total (12064ms).
[11:01:00.837] <TB2> INFO: Expecting 655360 events.
[11:01:14.355] <TB2> INFO: 655360 events read in total (12979ms).
[11:01:14.401] <TB2> INFO: Expecting 655360 events.
[11:01:27.875] <TB2> INFO: 655360 events read in total (12916ms).
[11:01:27.924] <TB2> INFO: Expecting 655360 events.
[11:01:40.708] <TB2> INFO: 655360 events read in total (12214ms).
[11:01:40.768] <TB2> INFO: Expecting 655360 events.
[11:01:54.035] <TB2> INFO: 655360 events read in total (12704ms).
[11:01:54.096] <TB2> INFO: Expecting 655360 events.
[11:02:05.265] <TB2> INFO: 655360 events read in total (10616ms).
[11:02:05.326] <TB2> INFO: Test took 209491ms.
[11:02:05.510] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:02:05.517] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:02:05.524] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:02:05.531] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:02:05.538] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:02:05.548] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:02:05.557] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:02:05.567] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:02:05.576] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:02:05.586] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:02:05.593] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[11:02:05.600] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[11:02:05.610] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:02:05.616] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:02:05.623] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:02:05.630] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:02:05.637] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:02:05.643] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[11:02:05.685] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C0.dat
[11:02:05.685] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C1.dat
[11:02:05.685] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C2.dat
[11:02:05.685] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C3.dat
[11:02:05.685] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C4.dat
[11:02:05.685] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C5.dat
[11:02:05.685] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C6.dat
[11:02:05.685] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C7.dat
[11:02:05.685] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C8.dat
[11:02:05.685] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C9.dat
[11:02:05.686] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C10.dat
[11:02:05.686] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C11.dat
[11:02:05.686] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C12.dat
[11:02:05.686] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C13.dat
[11:02:05.686] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C14.dat
[11:02:05.686] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//dacParameters35_C15.dat
[11:02:05.993] <TB2> INFO: Expecting 41600 events.
[11:02:09.786] <TB2> INFO: 41600 events read in total (3078ms).
[11:02:09.787] <TB2> INFO: Test took 4099ms.
[11:02:10.426] <TB2> INFO: Expecting 41600 events.
[11:02:14.168] <TB2> INFO: 41600 events read in total (3027ms).
[11:02:14.169] <TB2> INFO: Test took 4048ms.
[11:02:14.806] <TB2> INFO: Expecting 41600 events.
[11:02:18.580] <TB2> INFO: 41600 events read in total (3059ms).
[11:02:18.581] <TB2> INFO: Test took 4105ms.
[11:02:18.915] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:19.046] <TB2> INFO: Expecting 2560 events.
[11:02:20.002] <TB2> INFO: 2560 events read in total (241ms).
[11:02:20.002] <TB2> INFO: Test took 1087ms.
[11:02:20.005] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:20.511] <TB2> INFO: Expecting 2560 events.
[11:02:21.468] <TB2> INFO: 2560 events read in total (243ms).
[11:02:21.468] <TB2> INFO: Test took 1463ms.
[11:02:21.471] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:21.976] <TB2> INFO: Expecting 2560 events.
[11:02:22.933] <TB2> INFO: 2560 events read in total (242ms).
[11:02:22.934] <TB2> INFO: Test took 1463ms.
[11:02:22.936] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:23.441] <TB2> INFO: Expecting 2560 events.
[11:02:24.398] <TB2> INFO: 2560 events read in total (242ms).
[11:02:24.398] <TB2> INFO: Test took 1462ms.
[11:02:24.400] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:24.906] <TB2> INFO: Expecting 2560 events.
[11:02:25.862] <TB2> INFO: 2560 events read in total (241ms).
[11:02:25.862] <TB2> INFO: Test took 1462ms.
[11:02:25.865] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:26.371] <TB2> INFO: Expecting 2560 events.
[11:02:27.341] <TB2> INFO: 2560 events read in total (256ms).
[11:02:27.341] <TB2> INFO: Test took 1476ms.
[11:02:27.343] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:27.849] <TB2> INFO: Expecting 2560 events.
[11:02:28.805] <TB2> INFO: 2560 events read in total (241ms).
[11:02:28.805] <TB2> INFO: Test took 1462ms.
[11:02:28.807] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:29.313] <TB2> INFO: Expecting 2560 events.
[11:02:30.270] <TB2> INFO: 2560 events read in total (242ms).
[11:02:30.270] <TB2> INFO: Test took 1463ms.
[11:02:30.273] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:30.778] <TB2> INFO: Expecting 2560 events.
[11:02:31.749] <TB2> INFO: 2560 events read in total (256ms).
[11:02:31.749] <TB2> INFO: Test took 1476ms.
[11:02:31.752] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:32.257] <TB2> INFO: Expecting 2560 events.
[11:02:33.213] <TB2> INFO: 2560 events read in total (241ms).
[11:02:33.213] <TB2> INFO: Test took 1461ms.
[11:02:33.215] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:33.721] <TB2> INFO: Expecting 2560 events.
[11:02:34.679] <TB2> INFO: 2560 events read in total (243ms).
[11:02:34.679] <TB2> INFO: Test took 1464ms.
[11:02:34.681] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:35.187] <TB2> INFO: Expecting 2560 events.
[11:02:36.144] <TB2> INFO: 2560 events read in total (242ms).
[11:02:36.144] <TB2> INFO: Test took 1464ms.
[11:02:36.146] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:36.652] <TB2> INFO: Expecting 2560 events.
[11:02:37.609] <TB2> INFO: 2560 events read in total (242ms).
[11:02:37.609] <TB2> INFO: Test took 1463ms.
[11:02:37.611] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:38.118] <TB2> INFO: Expecting 2560 events.
[11:02:39.075] <TB2> INFO: 2560 events read in total (243ms).
[11:02:39.075] <TB2> INFO: Test took 1464ms.
[11:02:39.078] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:39.583] <TB2> INFO: Expecting 2560 events.
[11:02:40.541] <TB2> INFO: 2560 events read in total (243ms).
[11:02:40.541] <TB2> INFO: Test took 1463ms.
[11:02:40.543] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:41.049] <TB2> INFO: Expecting 2560 events.
[11:02:42.005] <TB2> INFO: 2560 events read in total (241ms).
[11:02:42.006] <TB2> INFO: Test took 1463ms.
[11:02:42.008] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:42.514] <TB2> INFO: Expecting 2560 events.
[11:02:43.470] <TB2> INFO: 2560 events read in total (241ms).
[11:02:43.471] <TB2> INFO: Test took 1463ms.
[11:02:43.473] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:43.979] <TB2> INFO: Expecting 2560 events.
[11:02:44.935] <TB2> INFO: 2560 events read in total (242ms).
[11:02:44.935] <TB2> INFO: Test took 1463ms.
[11:02:44.937] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:45.444] <TB2> INFO: Expecting 2560 events.
[11:02:46.401] <TB2> INFO: 2560 events read in total (244ms).
[11:02:46.402] <TB2> INFO: Test took 1465ms.
[11:02:46.403] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:46.910] <TB2> INFO: Expecting 2560 events.
[11:02:47.866] <TB2> INFO: 2560 events read in total (241ms).
[11:02:47.866] <TB2> INFO: Test took 1463ms.
[11:02:47.869] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:48.375] <TB2> INFO: Expecting 2560 events.
[11:02:49.333] <TB2> INFO: 2560 events read in total (243ms).
[11:02:49.333] <TB2> INFO: Test took 1464ms.
[11:02:49.336] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:49.841] <TB2> INFO: Expecting 2560 events.
[11:02:50.797] <TB2> INFO: 2560 events read in total (241ms).
[11:02:50.797] <TB2> INFO: Test took 1461ms.
[11:02:50.799] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:51.305] <TB2> INFO: Expecting 2560 events.
[11:02:52.262] <TB2> INFO: 2560 events read in total (242ms).
[11:02:52.262] <TB2> INFO: Test took 1463ms.
[11:02:52.265] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:52.771] <TB2> INFO: Expecting 2560 events.
[11:02:53.732] <TB2> INFO: 2560 events read in total (246ms).
[11:02:53.732] <TB2> INFO: Test took 1467ms.
[11:02:53.735] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:54.241] <TB2> INFO: Expecting 2560 events.
[11:02:55.203] <TB2> INFO: 2560 events read in total (247ms).
[11:02:55.203] <TB2> INFO: Test took 1468ms.
[11:02:55.206] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:55.712] <TB2> INFO: Expecting 2560 events.
[11:02:56.673] <TB2> INFO: 2560 events read in total (246ms).
[11:02:56.673] <TB2> INFO: Test took 1468ms.
[11:02:56.676] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:57.183] <TB2> INFO: Expecting 2560 events.
[11:02:58.146] <TB2> INFO: 2560 events read in total (248ms).
[11:02:58.146] <TB2> INFO: Test took 1470ms.
[11:02:58.150] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:02:58.655] <TB2> INFO: Expecting 2560 events.
[11:02:59.619] <TB2> INFO: 2560 events read in total (249ms).
[11:02:59.619] <TB2> INFO: Test took 1470ms.
[11:02:59.621] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:03:00.128] <TB2> INFO: Expecting 2560 events.
[11:03:01.093] <TB2> INFO: 2560 events read in total (250ms).
[11:03:01.093] <TB2> INFO: Test took 1472ms.
[11:03:01.096] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:03:01.601] <TB2> INFO: Expecting 2560 events.
[11:03:02.577] <TB2> INFO: 2560 events read in total (261ms).
[11:03:02.578] <TB2> INFO: Test took 1483ms.
[11:03:02.581] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:03:03.086] <TB2> INFO: Expecting 2560 events.
[11:03:04.064] <TB2> INFO: 2560 events read in total (263ms).
[11:03:04.064] <TB2> INFO: Test took 1483ms.
[11:03:04.067] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[11:03:04.572] <TB2> INFO: Expecting 2560 events.
[11:03:05.537] <TB2> INFO: 2560 events read in total (250ms).
[11:03:05.537] <TB2> INFO: Test took 1471ms.
[11:03:06.250] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 515 seconds
[11:03:06.250] <TB2> INFO: PH scale (per ROC): 72 72 61 65 62 77 69 67 66 66 62 63 61 63 54 60
[11:03:06.250] <TB2> INFO: PH offset (per ROC): 176 180 197 195 177 187 186 174 192 176 184 206 196 184 189 187
[11:03:06.257] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:03:06.257] <TB2> INFO: Decoding statistics:
[11:03:06.257] <TB2> INFO: General information:
[11:03:06.257] <TB2> INFO: 16bit words read: 66440
[11:03:06.257] <TB2> INFO: valid events total: 5120
[11:03:06.257] <TB2> INFO: empty events: 2620
[11:03:06.257] <TB2> INFO: valid events with pixels: 2500
[11:03:06.257] <TB2> INFO: valid pixel hits: 2500
[11:03:06.257] <TB2> INFO: Event errors: 0
[11:03:06.258] <TB2> INFO: start marker: 0
[11:03:06.258] <TB2> INFO: stop marker: 0
[11:03:06.258] <TB2> INFO: overflow: 0
[11:03:06.258] <TB2> INFO: invalid 5bit words: 0
[11:03:06.258] <TB2> INFO: invalid XOR eye diagram: 0
[11:03:06.258] <TB2> INFO: TBM errors: 0
[11:03:06.258] <TB2> INFO: flawed TBM headers: 0
[11:03:06.258] <TB2> INFO: flawed TBM trailers: 0
[11:03:06.258] <TB2> INFO: event ID mismatches: 0
[11:03:06.258] <TB2> INFO: ROC errors: 0
[11:03:06.258] <TB2> INFO: missing ROC header(s): 0
[11:03:06.258] <TB2> INFO: misplaced readback start: 0
[11:03:06.258] <TB2> INFO: Pixel decoding errors: 0
[11:03:06.258] <TB2> INFO: pixel data incomplete: 0
[11:03:06.258] <TB2> INFO: pixel address: 0
[11:03:06.258] <TB2> INFO: pulse height fill bit: 0
[11:03:06.258] <TB2> INFO: buffer corruption: 0
[11:03:06.446] <TB2> INFO: ######################################################################
[11:03:06.446] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[11:03:06.446] <TB2> INFO: ######################################################################
[11:03:06.459] <TB2> INFO: scanning low vcal = 10
[11:03:06.764] <TB2> INFO: Expecting 41600 events.
[11:03:10.535] <TB2> INFO: 41600 events read in total (3056ms).
[11:03:10.536] <TB2> INFO: Test took 4077ms.
[11:03:10.538] <TB2> INFO: scanning low vcal = 20
[11:03:11.044] <TB2> INFO: Expecting 41600 events.
[11:03:14.884] <TB2> INFO: 41600 events read in total (3125ms).
[11:03:14.885] <TB2> INFO: Test took 4347ms.
[11:03:14.887] <TB2> INFO: scanning low vcal = 30
[11:03:15.393] <TB2> INFO: Expecting 41600 events.
[11:03:19.264] <TB2> INFO: 41600 events read in total (3156ms).
[11:03:19.265] <TB2> INFO: Test took 4378ms.
[11:03:19.267] <TB2> INFO: scanning low vcal = 40
[11:03:19.763] <TB2> INFO: Expecting 41600 events.
[11:03:24.058] <TB2> INFO: 41600 events read in total (3580ms).
[11:03:24.059] <TB2> INFO: Test took 4792ms.
[11:03:24.062] <TB2> INFO: scanning low vcal = 50
[11:03:24.477] <TB2> INFO: Expecting 41600 events.
[11:03:29.065] <TB2> INFO: 41600 events read in total (3873ms).
[11:03:29.065] <TB2> INFO: Test took 5003ms.
[11:03:29.068] <TB2> INFO: scanning low vcal = 60
[11:03:29.505] <TB2> INFO: Expecting 41600 events.
[11:03:33.949] <TB2> INFO: 41600 events read in total (3730ms).
[11:03:33.949] <TB2> INFO: Test took 4880ms.
[11:03:33.952] <TB2> INFO: scanning low vcal = 70
[11:03:34.399] <TB2> INFO: Expecting 41600 events.
[11:03:38.717] <TB2> INFO: 41600 events read in total (3603ms).
[11:03:38.718] <TB2> INFO: Test took 4766ms.
[11:03:38.720] <TB2> INFO: scanning low vcal = 80
[11:03:39.163] <TB2> INFO: Expecting 41600 events.
[11:03:43.680] <TB2> INFO: 41600 events read in total (3802ms).
[11:03:43.681] <TB2> INFO: Test took 4961ms.
[11:03:43.684] <TB2> INFO: scanning low vcal = 90
[11:03:44.126] <TB2> INFO: Expecting 41600 events.
[11:03:48.488] <TB2> INFO: 41600 events read in total (3647ms).
[11:03:48.489] <TB2> INFO: Test took 4805ms.
[11:03:48.492] <TB2> INFO: scanning low vcal = 100
[11:03:48.939] <TB2> INFO: Expecting 41600 events.
[11:03:53.498] <TB2> INFO: 41600 events read in total (3844ms).
[11:03:53.499] <TB2> INFO: Test took 5007ms.
[11:03:53.502] <TB2> INFO: scanning low vcal = 110
[11:03:53.949] <TB2> INFO: Expecting 41600 events.
[11:03:58.356] <TB2> INFO: 41600 events read in total (3692ms).
[11:03:58.357] <TB2> INFO: Test took 4855ms.
[11:03:58.360] <TB2> INFO: scanning low vcal = 120
[11:03:58.805] <TB2> INFO: Expecting 41600 events.
[11:04:03.147] <TB2> INFO: 41600 events read in total (3628ms).
[11:04:03.148] <TB2> INFO: Test took 4788ms.
[11:04:03.152] <TB2> INFO: scanning low vcal = 130
[11:04:03.590] <TB2> INFO: Expecting 41600 events.
[11:04:08.078] <TB2> INFO: 41600 events read in total (3773ms).
[11:04:08.079] <TB2> INFO: Test took 4927ms.
[11:04:08.081] <TB2> INFO: scanning low vcal = 140
[11:04:08.518] <TB2> INFO: Expecting 41600 events.
[11:04:12.864] <TB2> INFO: 41600 events read in total (3631ms).
[11:04:12.864] <TB2> INFO: Test took 4782ms.
[11:04:12.867] <TB2> INFO: scanning low vcal = 150
[11:04:13.297] <TB2> INFO: Expecting 41600 events.
[11:04:17.650] <TB2> INFO: 41600 events read in total (3638ms).
[11:04:17.650] <TB2> INFO: Test took 4783ms.
[11:04:17.653] <TB2> INFO: scanning low vcal = 160
[11:04:18.096] <TB2> INFO: Expecting 41600 events.
[11:04:22.583] <TB2> INFO: 41600 events read in total (3772ms).
[11:04:22.584] <TB2> INFO: Test took 4931ms.
[11:04:22.587] <TB2> INFO: scanning low vcal = 170
[11:04:23.026] <TB2> INFO: Expecting 41600 events.
[11:04:27.422] <TB2> INFO: 41600 events read in total (3681ms).
[11:04:27.423] <TB2> INFO: Test took 4836ms.
[11:04:27.427] <TB2> INFO: scanning low vcal = 180
[11:04:27.845] <TB2> INFO: Expecting 41600 events.
[11:04:32.358] <TB2> INFO: 41600 events read in total (3799ms).
[11:04:32.359] <TB2> INFO: Test took 4932ms.
[11:04:32.362] <TB2> INFO: scanning low vcal = 190
[11:04:32.806] <TB2> INFO: Expecting 41600 events.
[11:04:37.269] <TB2> INFO: 41600 events read in total (3748ms).
[11:04:37.270] <TB2> INFO: Test took 4908ms.
[11:04:37.272] <TB2> INFO: scanning low vcal = 200
[11:04:37.720] <TB2> INFO: Expecting 41600 events.
[11:04:42.105] <TB2> INFO: 41600 events read in total (3670ms).
[11:04:42.105] <TB2> INFO: Test took 4833ms.
[11:04:42.108] <TB2> INFO: scanning low vcal = 210
[11:04:42.533] <TB2> INFO: Expecting 41600 events.
[11:04:47.031] <TB2> INFO: 41600 events read in total (3783ms).
[11:04:47.032] <TB2> INFO: Test took 4924ms.
[11:04:47.035] <TB2> INFO: scanning low vcal = 220
[11:04:47.470] <TB2> INFO: Expecting 41600 events.
[11:04:51.861] <TB2> INFO: 41600 events read in total (3676ms).
[11:04:51.862] <TB2> INFO: Test took 4827ms.
[11:04:51.864] <TB2> INFO: scanning low vcal = 230
[11:04:52.282] <TB2> INFO: Expecting 41600 events.
[11:04:56.686] <TB2> INFO: 41600 events read in total (3689ms).
[11:04:56.686] <TB2> INFO: Test took 4822ms.
[11:04:56.689] <TB2> INFO: scanning low vcal = 240
[11:04:57.124] <TB2> INFO: Expecting 41600 events.
[11:05:01.619] <TB2> INFO: 41600 events read in total (3780ms).
[11:05:01.620] <TB2> INFO: Test took 4931ms.
[11:05:01.623] <TB2> INFO: scanning low vcal = 250
[11:05:02.067] <TB2> INFO: Expecting 41600 events.
[11:05:06.435] <TB2> INFO: 41600 events read in total (3653ms).
[11:05:06.436] <TB2> INFO: Test took 4813ms.
[11:05:06.440] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[11:05:06.876] <TB2> INFO: Expecting 41600 events.
[11:05:11.320] <TB2> INFO: 41600 events read in total (3729ms).
[11:05:11.321] <TB2> INFO: Test took 4881ms.
[11:05:11.323] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[11:05:11.773] <TB2> INFO: Expecting 41600 events.
[11:05:16.121] <TB2> INFO: 41600 events read in total (3632ms).
[11:05:16.121] <TB2> INFO: Test took 4798ms.
[11:05:16.124] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[11:05:16.549] <TB2> INFO: Expecting 41600 events.
[11:05:20.912] <TB2> INFO: 41600 events read in total (3648ms).
[11:05:20.913] <TB2> INFO: Test took 4789ms.
[11:05:20.916] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[11:05:21.358] <TB2> INFO: Expecting 41600 events.
[11:05:25.759] <TB2> INFO: 41600 events read in total (3686ms).
[11:05:25.760] <TB2> INFO: Test took 4844ms.
[11:05:25.762] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[11:05:26.211] <TB2> INFO: Expecting 41600 events.
[11:05:30.584] <TB2> INFO: 41600 events read in total (3658ms).
[11:05:30.585] <TB2> INFO: Test took 4823ms.
[11:05:31.057] <TB2> INFO: PixTestGainPedestal::measure() done
[11:06:09.195] <TB2> INFO: PixTestGainPedestal::fit() done
[11:06:09.195] <TB2> INFO: non-linearity mean: 0.959 0.956 0.950 0.957 0.956 0.958 0.962 0.961 0.957 0.957 0.958 0.954 0.955 0.961 0.953 0.961
[11:06:09.195] <TB2> INFO: non-linearity RMS: 0.007 0.007 0.009 0.007 0.007 0.007 0.007 0.007 0.007 0.006 0.008 0.008 0.008 0.008 0.009 0.007
[11:06:09.195] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//phCalibrationFitErr35_C0.dat
[11:06:09.214] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//phCalibrationFitErr35_C1.dat
[11:06:09.244] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//phCalibrationFitErr35_C2.dat
[11:06:09.269] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//phCalibrationFitErr35_C3.dat
[11:06:09.297] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//phCalibrationFitErr35_C4.dat
[11:06:09.319] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//phCalibrationFitErr35_C5.dat
[11:06:09.349] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//phCalibrationFitErr35_C6.dat
[11:06:09.375] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//phCalibrationFitErr35_C7.dat
[11:06:09.394] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//phCalibrationFitErr35_C8.dat
[11:06:09.413] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//phCalibrationFitErr35_C9.dat
[11:06:09.431] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//phCalibrationFitErr35_C10.dat
[11:06:09.450] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//phCalibrationFitErr35_C11.dat
[11:06:09.469] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//phCalibrationFitErr35_C12.dat
[11:06:09.488] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//phCalibrationFitErr35_C13.dat
[11:06:09.506] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//phCalibrationFitErr35_C14.dat
[11:06:09.524] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//phCalibrationFitErr35_C15.dat
[11:06:09.542] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 183 seconds
[11:06:09.542] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:06:09.542] <TB2> INFO: Decoding statistics:
[11:06:09.542] <TB2> INFO: General information:
[11:06:09.543] <TB2> INFO: 16bit words read: 2329020
[11:06:09.543] <TB2> INFO: valid events total: 83200
[11:06:09.543] <TB2> INFO: empty events: 0
[11:06:09.543] <TB2> INFO: valid events with pixels: 83200
[11:06:09.543] <TB2> INFO: valid pixel hits: 665310
[11:06:09.543] <TB2> INFO: Event errors: 0
[11:06:09.543] <TB2> INFO: start marker: 0
[11:06:09.543] <TB2> INFO: stop marker: 0
[11:06:09.543] <TB2> INFO: overflow: 0
[11:06:09.543] <TB2> INFO: invalid 5bit words: 0
[11:06:09.543] <TB2> INFO: invalid XOR eye diagram: 0
[11:06:09.543] <TB2> INFO: TBM errors: 0
[11:06:09.543] <TB2> INFO: flawed TBM headers: 0
[11:06:09.543] <TB2> INFO: flawed TBM trailers: 0
[11:06:09.543] <TB2> INFO: event ID mismatches: 0
[11:06:09.543] <TB2> INFO: ROC errors: 0
[11:06:09.543] <TB2> INFO: missing ROC header(s): 0
[11:06:09.543] <TB2> INFO: misplaced readback start: 0
[11:06:09.543] <TB2> INFO: Pixel decoding errors: 0
[11:06:09.543] <TB2> INFO: pixel data incomplete: 0
[11:06:09.543] <TB2> INFO: pixel address: 0
[11:06:09.543] <TB2> INFO: pulse height fill bit: 0
[11:06:09.543] <TB2> INFO: buffer corruption: 0
[11:06:09.550] <TB2> INFO: readReadbackCal: /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C0.dat .. /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C15.dat
[11:06:09.551] <TB2> INFO: ######################################################################
[11:06:09.551] <TB2> INFO: PixTestReadback::doTest()
[11:06:09.551] <TB2> INFO: ######################################################################
[11:06:09.552] <TB2> INFO: PixTestReadback::RES sent once
[11:06:20.756] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C0.dat
[11:06:20.756] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C1.dat
[11:06:20.757] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C2.dat
[11:06:20.757] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C3.dat
[11:06:20.757] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C4.dat
[11:06:20.757] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C5.dat
[11:06:20.757] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C6.dat
[11:06:20.757] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C7.dat
[11:06:20.757] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C8.dat
[11:06:20.758] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C9.dat
[11:06:20.758] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C10.dat
[11:06:20.758] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C11.dat
[11:06:20.758] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C12.dat
[11:06:20.758] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C13.dat
[11:06:20.758] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C14.dat
[11:06:20.758] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C15.dat
[11:06:20.785] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:06:20.785] <TB2> INFO: PixTestReadback::RES sent once
[11:06:31.934] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C0.dat
[11:06:31.934] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C1.dat
[11:06:31.934] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C2.dat
[11:06:31.934] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C3.dat
[11:06:31.934] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C4.dat
[11:06:31.935] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C5.dat
[11:06:31.935] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C6.dat
[11:06:31.935] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C7.dat
[11:06:31.935] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C8.dat
[11:06:31.935] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C9.dat
[11:06:31.935] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C10.dat
[11:06:31.936] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C11.dat
[11:06:31.936] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C12.dat
[11:06:31.936] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C13.dat
[11:06:31.936] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C14.dat
[11:06:31.936] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C15.dat
[11:06:31.965] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:06:31.965] <TB2> INFO: PixTestReadback::RES sent once
[11:06:40.544] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:06:40.544] <TB2> INFO: Vbg will be calibrated using Vd calibration
[11:06:40.544] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 154.7calibrated Vbg = 1.20964 :::*/*/*/*/
[11:06:40.544] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 160.5calibrated Vbg = 1.20236 :::*/*/*/*/
[11:06:40.544] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 152calibrated Vbg = 1.21496 :::*/*/*/*/
[11:06:40.544] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 162calibrated Vbg = 1.21978 :::*/*/*/*/
[11:06:40.544] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 146calibrated Vbg = 1.22271 :::*/*/*/*/
[11:06:40.544] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 166.3calibrated Vbg = 1.22602 :::*/*/*/*/
[11:06:40.544] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 152.4calibrated Vbg = 1.21973 :::*/*/*/*/
[11:06:40.544] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 147.2calibrated Vbg = 1.22548 :::*/*/*/*/
[11:06:40.544] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 151.9calibrated Vbg = 1.22499 :::*/*/*/*/
[11:06:40.544] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 152.7calibrated Vbg = 1.22382 :::*/*/*/*/
[11:06:40.544] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 149.9calibrated Vbg = 1.22521 :::*/*/*/*/
[11:06:40.544] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 154.9calibrated Vbg = 1.213 :::*/*/*/*/
[11:06:40.544] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 148.4calibrated Vbg = 1.21059 :::*/*/*/*/
[11:06:40.544] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 146.8calibrated Vbg = 1.2101 :::*/*/*/*/
[11:06:40.544] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 156.3calibrated Vbg = 1.21218 :::*/*/*/*/
[11:06:40.544] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 168.5calibrated Vbg = 1.21671 :::*/*/*/*/
[11:06:40.548] <TB2> INFO: PixTestReadback::RES sent once
[11:09:34.568] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C0.dat
[11:09:34.568] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C1.dat
[11:09:34.568] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C2.dat
[11:09:34.569] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C3.dat
[11:09:34.569] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C4.dat
[11:09:34.569] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C5.dat
[11:09:34.569] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C6.dat
[11:09:34.569] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C7.dat
[11:09:34.569] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C8.dat
[11:09:34.569] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C9.dat
[11:09:34.569] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C10.dat
[11:09:34.569] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C11.dat
[11:09:34.569] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C12.dat
[11:09:34.569] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C13.dat
[11:09:34.569] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C14.dat
[11:09:34.569] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//000_FulltestPxar_p17//readbackCal_C15.dat
[11:09:34.598] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[11:09:34.599] <TB2> INFO: PixTestReadback::doTest() done
[11:09:34.599] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:09:34.599] <TB2> INFO: Decoding statistics:
[11:09:34.599] <TB2> INFO: General information:
[11:09:34.599] <TB2> INFO: 16bit words read: 768
[11:09:34.599] <TB2> INFO: valid events total: 64
[11:09:34.599] <TB2> INFO: empty events: 64
[11:09:34.599] <TB2> INFO: valid events with pixels: 0
[11:09:34.599] <TB2> INFO: valid pixel hits: 0
[11:09:34.599] <TB2> INFO: Event errors: 0
[11:09:34.599] <TB2> INFO: start marker: 0
[11:09:34.599] <TB2> INFO: stop marker: 0
[11:09:34.599] <TB2> INFO: overflow: 0
[11:09:34.599] <TB2> INFO: invalid 5bit words: 0
[11:09:34.599] <TB2> INFO: invalid XOR eye diagram: 0
[11:09:34.599] <TB2> INFO: TBM errors: 0
[11:09:34.599] <TB2> INFO: flawed TBM headers: 0
[11:09:34.599] <TB2> INFO: flawed TBM trailers: 0
[11:09:34.599] <TB2> INFO: event ID mismatches: 0
[11:09:34.599] <TB2> INFO: ROC errors: 0
[11:09:34.599] <TB2> INFO: missing ROC header(s): 0
[11:09:34.599] <TB2> INFO: misplaced readback start: 0
[11:09:34.599] <TB2> INFO: Pixel decoding errors: 0
[11:09:34.599] <TB2> INFO: pixel data incomplete: 0
[11:09:34.599] <TB2> INFO: pixel address: 0
[11:09:34.599] <TB2> INFO: pulse height fill bit: 0
[11:09:34.599] <TB2> INFO: buffer corruption: 0
[11:09:34.612] <TB2> INFO: Decoding statistics:
[11:09:34.612] <TB2> INFO: General information:
[11:09:34.612] <TB2> INFO: 16bit words read: 2396228
[11:09:34.612] <TB2> INFO: valid events total: 88384
[11:09:34.612] <TB2> INFO: empty events: 2684
[11:09:34.612] <TB2> INFO: valid events with pixels: 85700
[11:09:34.612] <TB2> INFO: valid pixel hits: 667810
[11:09:34.612] <TB2> INFO: Event errors: 0
[11:09:34.612] <TB2> INFO: start marker: 0
[11:09:34.612] <TB2> INFO: stop marker: 0
[11:09:34.612] <TB2> INFO: overflow: 0
[11:09:34.612] <TB2> INFO: invalid 5bit words: 0
[11:09:34.612] <TB2> INFO: invalid XOR eye diagram: 0
[11:09:34.612] <TB2> INFO: TBM errors: 0
[11:09:34.612] <TB2> INFO: flawed TBM headers: 0
[11:09:34.612] <TB2> INFO: flawed TBM trailers: 0
[11:09:34.612] <TB2> INFO: event ID mismatches: 0
[11:09:34.612] <TB2> INFO: ROC errors: 0
[11:09:34.612] <TB2> INFO: missing ROC header(s): 0
[11:09:34.612] <TB2> INFO: misplaced readback start: 0
[11:09:34.612] <TB2> INFO: Pixel decoding errors: 0
[11:09:34.612] <TB2> INFO: pixel data incomplete: 0
[11:09:34.612] <TB2> INFO: pixel address: 0
[11:09:34.612] <TB2> INFO: pulse height fill bit: 0
[11:09:34.612] <TB2> INFO: buffer corruption: 0
[11:09:34.612] <TB2> INFO: enter test to run
[11:09:34.612] <TB2> INFO: test: exit no parameter change
[11:09:34.802] <TB2> QUIET: Connection to board 156 closed.
[11:09:34.882] <TB2> INFO: pXar: this is the end, my friend