[11:43:11.131] <TB2> INFO: *** Welcome to pxar ***
[11:43:11.131] <TB2> INFO: *** Today: 2015/11/03
[11:43:11.197] <TB2> INFO: *** Version: 9da6
[11:43:11.198] <TB2> INFO: readRocDacs: /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C0.dat .. /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C15.dat
[11:43:11.198] <TB2> INFO: readTbmDacs: /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//tbmParameters_C0a.dat .. /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//tbmParameters_C0b.dat
[11:43:11.198] <TB2> INFO: readMaskFile: /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//defaultMaskFile.dat
[11:43:11.198] <TB2> INFO: readTrimFile: /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters_C0.dat .. /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters_C15.dat
[11:43:11.277] <TB2> INFO: clk: 4
[11:43:11.277] <TB2> INFO: ctr: 4
[11:43:11.277] <TB2> INFO: sda: 19
[11:43:11.277] <TB2> INFO: tin: 9
[11:43:11.277] <TB2> INFO: level: 15
[11:43:11.277] <TB2> INFO: triggerdelay: 0
[11:43:11.277] <TB2> QUIET: Instanciating API for pxar v2.6.0+26~g89693ff
[11:43:11.277] <TB2> INFO: Log level: INFO
[11:43:11.284] <TB2> INFO: Found DTB DTB_WXC55Z
[11:43:11.294] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[11:43:11.297] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.2
SW version: 4.5
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[11:43:11.300] <TB2> INFO: RPC call hashes of host and DTB match: 398089610
[11:43:12.863] <TB2> INFO: DUT info:
[11:43:12.863] <TB2> INFO: The DUT currently contains the following objects:
[11:43:12.863] <TB2> INFO: 2 TBM Cores tbm08c (2 ON)
[11:43:12.863] <TB2> INFO: TBM Core alpha (0): 7 registers set
[11:43:12.863] <TB2> INFO: TBM Core beta (1): 7 registers set
[11:43:12.863] <TB2> INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[11:43:12.863] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:43:12.863] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:43:12.863] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:43:12.863] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:43:12.863] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:43:12.863] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:43:12.863] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:43:12.863] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:43:12.863] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:43:12.863] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:43:12.863] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:43:12.863] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:43:12.863] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:43:12.864] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:43:12.864] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:43:12.864] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:43:13.265] <TB2> INFO: enter 'restricted' command line mode
[11:43:13.265] <TB2> INFO: enter test to run
[11:43:13.265] <TB2> INFO: test: pretest no parameter change
[11:43:13.265] <TB2> INFO: running: pretest
[11:43:13.274] <TB2> INFO: ######################################################################
[11:43:13.274] <TB2> INFO: PixTestPretest::doTest()
[11:43:13.274] <TB2> INFO: ######################################################################
[11:43:13.276] <TB2> INFO: ----------------------------------------------------------------------
[11:43:13.276] <TB2> INFO: PixTestPretest::programROC()
[11:43:13.276] <TB2> INFO: ----------------------------------------------------------------------
[11:43:31.294] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:43:31.294] <TB2> INFO: IA differences per ROC: 16.9 16.1 18.5 17.7 16.1 15.3 16.1 15.3 19.3 15.3 17.7 16.9 18.5 17.7 16.9 16.1
[11:43:31.376] <TB2> INFO: ----------------------------------------------------------------------
[11:43:31.376] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:43:31.376] <TB2> INFO: ----------------------------------------------------------------------
[11:43:52.679] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 389.9 mA = 24.3688 mA/ROC
[11:43:52.679] <TB2> INFO: i(loss) [mA/ROC]: 21.7 20.9 21.7 20.9 19.3 20.9 20.9 20.1 20.1 21.7 20.9 20.1 20.1 20.1 20.1 20.9
[11:43:52.708] <TB2> INFO: ----------------------------------------------------------------------
[11:43:52.708] <TB2> INFO: PixTestPretest::findTiming()
[11:43:52.708] <TB2> INFO: ----------------------------------------------------------------------
[11:43:52.708] <TB2> INFO: PixTestCmd::init()
[11:43:53.302] <TB2> WARNING: Not unmasking DUT, not setting Calibrate bits!
[11:45:29.906] <TB2> INFO: TBM phases: 160MHz: 7, 400MHz: 6, TBM delays: ROC(0/1):4, header/trailer: 1, token: 1
[11:45:29.906] <TB2> INFO: (success/tries = 100/100), width = 5
[11:45:29.908] <TB2> INFO: ----------------------------------------------------------------------
[11:45:29.908] <TB2> INFO: PixTestPretest::findWorkingPixel()
[11:45:29.908] <TB2> INFO: ----------------------------------------------------------------------
[11:45:30.044] <TB2> INFO: Expecting 231680 events.
[11:45:34.656] <TB2> ERROR: <datapipe.cc/CheckEventValidity:L488> Channel 0 Number of ROCs (1) != Token Chain Length (8)
[11:45:34.659] <TB2> ERROR: <datapipe.cc/CheckEventID:L461> Channel 0 Event ID mismatch: local ID (21) != TBM ID (2)
[11:45:37.836] <TB2> INFO: 231680 events read in total (7077ms).
[11:45:37.840] <TB2> INFO: Test took 7930ms.
[11:45:38.245] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[11:45:38.283] <TB2> INFO: ----------------------------------------------------------------------
[11:45:38.283] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[11:45:38.283] <TB2> INFO: ----------------------------------------------------------------------
[11:45:38.419] <TB2> INFO: Expecting 231680 events.
[11:45:46.968] <TB2> INFO: 231680 events read in total (7834ms).
[11:45:46.976] <TB2> INFO: Test took 8689ms.
[11:45:47.387] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[11:45:47.387] <TB2> INFO: CalDel: 101 125 153 130 123 87 117 118 125 143 123 123 135 137 131 110
[11:45:47.387] <TB2> INFO: VthrComp: 52 51 58 52 51 52 51 51 51 53 51 52 54 52 51 62
[11:45:47.390] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C0.dat
[11:45:47.391] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C1.dat
[11:45:47.391] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C2.dat
[11:45:47.391] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C3.dat
[11:45:47.391] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C4.dat
[11:45:47.392] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C5.dat
[11:45:47.392] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C6.dat
[11:45:47.392] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C7.dat
[11:45:47.392] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C8.dat
[11:45:47.393] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C9.dat
[11:45:47.393] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C10.dat
[11:45:47.393] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C11.dat
[11:45:47.393] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C12.dat
[11:45:47.393] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C13.dat
[11:45:47.394] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C14.dat
[11:45:47.394] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters_C15.dat
[11:45:47.394] <TB2> INFO: write tbm parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//tbmParameters_C0a.dat
[11:45:47.394] <TB2> INFO: write tbm parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//tbmParameters_C0b.dat
[11:45:47.394] <TB2> INFO: PixTestPretest::doTest() done, duration: 154 seconds
[11:45:47.461] <TB2> INFO: enter test to run
[11:45:47.461] <TB2> INFO: test: fulltest no parameter change
[11:45:47.461] <TB2> INFO: running: fulltest
[11:45:47.461] <TB2> INFO: ######################################################################
[11:45:47.461] <TB2> INFO: PixTestFullTest::doTest()
[11:45:47.461] <TB2> INFO: ######################################################################
[11:45:47.462] <TB2> INFO: ######################################################################
[11:45:47.462] <TB2> INFO: PixTestAlive::doTest()
[11:45:47.462] <TB2> INFO: ######################################################################
[11:45:47.464] <TB2> INFO: ----------------------------------------------------------------------
[11:45:47.464] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:45:47.464] <TB2> INFO: ----------------------------------------------------------------------
[11:45:47.773] <TB2> INFO: Expecting 41600 events.
[11:45:52.165] <TB2> INFO: 41600 events read in total (3677ms).
[11:45:52.166] <TB2> INFO: Test took 4701ms.
[11:45:52.172] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:45:52.548] <TB2> INFO: PixTestAlive::aliveTest() done
[11:45:52.548] <TB2> INFO: number of dead pixels (per ROC): 2 3 0 3 0 0 3 0 0 1 0 0 1 0 1 2
[11:45:52.550] <TB2> INFO: ----------------------------------------------------------------------
[11:45:52.550] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:45:52.550] <TB2> INFO: ----------------------------------------------------------------------
[11:45:52.881] <TB2> INFO: Expecting 41600 events.
[11:45:56.015] <TB2> INFO: 41600 events read in total (2419ms).
[11:45:56.015] <TB2> INFO: Test took 3463ms.
[11:45:56.015] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:45:56.015] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:45:56.425] <TB2> INFO: PixTestAlive::maskTest() done
[11:45:56.425] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:45:56.427] <TB2> INFO: ----------------------------------------------------------------------
[11:45:56.427] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:45:56.427] <TB2> INFO: ----------------------------------------------------------------------
[11:45:56.736] <TB2> INFO: Expecting 41600 events.
[11:46:01.027] <TB2> INFO: 41600 events read in total (3577ms).
[11:46:01.027] <TB2> INFO: Test took 4598ms.
[11:46:01.033] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:46:01.411] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[11:46:01.411] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:46:01.411] <TB2> INFO: PixTestAlive::doTest() done, duration: 13 seconds
[11:46:01.411] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:46:01.411] <TB2> INFO: Decoding statistics:
[11:46:01.411] <TB2> INFO: General information:
[11:46:01.411] <TB2> INFO: 16bit words read: 0
[11:46:01.411] <TB2> INFO: valid events total: 0
[11:46:01.411] <TB2> INFO: empty events: 0
[11:46:01.411] <TB2> INFO: valid events with pixels: 0
[11:46:01.411] <TB2> INFO: valid pixel hits: 0
[11:46:01.411] <TB2> INFO: Event errors: 0
[11:46:01.411] <TB2> INFO: start marker: 0
[11:46:01.411] <TB2> INFO: stop marker: 0
[11:46:01.411] <TB2> INFO: overflow: 0
[11:46:01.411] <TB2> INFO: invalid 5bit words: 0
[11:46:01.411] <TB2> INFO: invalid XOR eye diagram: 0
[11:46:01.411] <TB2> INFO: TBM errors: 0
[11:46:01.411] <TB2> INFO: flawed TBM headers: 0
[11:46:01.411] <TB2> INFO: flawed TBM trailers: 0
[11:46:01.411] <TB2> INFO: event ID mismatches: 0
[11:46:01.412] <TB2> INFO: ROC errors: 0
[11:46:01.412] <TB2> INFO: missing ROC header(s): 0
[11:46:01.412] <TB2> INFO: misplaced readback start: 0
[11:46:01.412] <TB2> INFO: Pixel decoding errors: 0
[11:46:01.412] <TB2> INFO: pixel data incomplete: 0
[11:46:01.412] <TB2> INFO: pixel address: 0
[11:46:01.412] <TB2> INFO: pulse height fill bit: 0
[11:46:01.412] <TB2> INFO: buffer corruption: 0
[11:46:01.427] <TB2> INFO: ######################################################################
[11:46:01.427] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[11:46:01.427] <TB2> INFO: ######################################################################
[11:46:01.429] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[11:46:01.440] <TB2> INFO: dacScan split into 1 runs with ntrig = 5
[11:46:01.440] <TB2> INFO: run 1 of 1
[11:46:01.749] <TB2> INFO: Expecting 3120000 events.
[11:46:56.482] <TB2> INFO: 1288570 events read in total (54018ms).
[11:47:51.074] <TB2> INFO: 2555740 events read in total (108610ms).
[11:48:13.533] <TB2> INFO: 3120000 events read in total (131070ms).
[11:48:13.583] <TB2> INFO: Test took 132143ms.
[11:48:13.675] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:48:38.146] <TB2> INFO: PixTestBBMap::doTest() done, duration: 156 seconds
[11:48:38.146] <TB2> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:48:38.146] <TB2> INFO: separation cut (per ROC): 152 146 151 144 128 151 141 142 145 146 141 149 144 146 134 167
[11:48:38.146] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[11:48:38.146] <TB2> INFO: Decoding statistics:
[11:48:38.146] <TB2> INFO: General information:
[11:48:38.146] <TB2> INFO: 16bit words read: 0
[11:48:38.146] <TB2> INFO: valid events total: 0
[11:48:38.146] <TB2> INFO: empty events: 0
[11:48:38.146] <TB2> INFO: valid events with pixels: 0
[11:48:38.146] <TB2> INFO: valid pixel hits: 0
[11:48:38.146] <TB2> INFO: Event errors: 0
[11:48:38.146] <TB2> INFO: start marker: 0
[11:48:38.146] <TB2> INFO: stop marker: 0
[11:48:38.146] <TB2> INFO: overflow: 0
[11:48:38.146] <TB2> INFO: invalid 5bit words: 0
[11:48:38.146] <TB2> INFO: invalid XOR eye diagram: 0
[11:48:38.146] <TB2> INFO: TBM errors: 0
[11:48:38.146] <TB2> INFO: flawed TBM headers: 0
[11:48:38.146] <TB2> INFO: flawed TBM trailers: 0
[11:48:38.146] <TB2> INFO: event ID mismatches: 0
[11:48:38.146] <TB2> INFO: ROC errors: 0
[11:48:38.146] <TB2> INFO: missing ROC header(s): 0
[11:48:38.146] <TB2> INFO: misplaced readback start: 0
[11:48:38.146] <TB2> INFO: Pixel decoding errors: 0
[11:48:38.146] <TB2> INFO: pixel data incomplete: 0
[11:48:38.146] <TB2> INFO: pixel address: 0
[11:48:38.146] <TB2> INFO: pulse height fill bit: 0
[11:48:38.147] <TB2> INFO: buffer corruption: 0
[11:48:38.219] <TB2> INFO: ######################################################################
[11:48:38.227] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:48:38.227] <TB2> INFO: ######################################################################
[11:48:38.227] <TB2> INFO: ----------------------------------------------------------------------
[11:48:38.227] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:48:38.227] <TB2> INFO: ----------------------------------------------------------------------
[11:48:38.227] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 150 (-1/-1) hits flags = 528 (plus default)
[11:48:38.236] <TB2> INFO: dacScan split into 1 runs with ntrig = 50
[11:48:38.236] <TB2> INFO: run 1 of 1
[11:48:38.541] <TB2> INFO: Expecting 26208000 events.
[11:49:15.899] <TB2> INFO: 1338200 events read in total (36644ms).
[11:49:52.077] <TB2> INFO: 2643500 events read in total (72822ms).
[11:50:27.843] <TB2> INFO: 3939250 events read in total (108588ms).
[11:51:04.712] <TB2> INFO: 5236400 events read in total (145457ms).
[11:51:42.312] <TB2> INFO: 6530800 events read in total (183057ms).
[11:52:18.710] <TB2> INFO: 7822850 events read in total (219455ms).
[11:52:55.032] <TB2> INFO: 9113000 events read in total (255777ms).
[11:53:30.891] <TB2> INFO: 10397600 events read in total (291636ms).
[11:54:07.608] <TB2> INFO: 11681600 events read in total (328353ms).
[11:54:44.754] <TB2> INFO: 12959850 events read in total (365499ms).
[11:55:21.901] <TB2> INFO: 14223750 events read in total (402646ms).
[11:55:58.329] <TB2> INFO: 15476100 events read in total (439074ms).
[11:56:33.898] <TB2> INFO: 16729750 events read in total (474643ms).
[11:57:09.939] <TB2> INFO: 17978600 events read in total (510684ms).
[11:57:45.367] <TB2> INFO: 19229700 events read in total (546112ms).
[11:58:20.835] <TB2> INFO: 20475000 events read in total (581580ms).
[11:58:57.315] <TB2> INFO: 21723450 events read in total (618060ms).
[11:59:33.786] <TB2> INFO: 22967700 events read in total (654531ms).
[12:00:09.061] <TB2> INFO: 24215700 events read in total (689806ms).
[12:00:44.170] <TB2> INFO: 25461550 events read in total (724915ms).
[12:01:05.298] <TB2> INFO: 26208000 events read in total (746043ms).
[12:01:05.334] <TB2> INFO: Test took 747098ms.
[12:01:05.395] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:01:05.516] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:07.084] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:08.387] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:09.870] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:11.516] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:13.219] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:14.668] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:16.088] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:17.484] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:18.843] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:20.157] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:21.471] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:22.771] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:24.109] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:25.395] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:26.734] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[12:01:28.037] <TB2> INFO: PixTestScurves::scurves() done
[12:01:28.037] <TB2> INFO: Vcal mean: 114.47 115.56 120.15 112.20 103.54 119.51 108.46 110.20 105.64 114.29 113.76 115.08 118.77 118.34 104.94 128.69
[12:01:28.037] <TB2> INFO: Vcal RMS: 5.97 6.75 9.13 6.57 5.40 5.91 6.06 5.52 5.44 5.87 5.44 5.74 6.15 6.46 5.50 8.93
[12:01:28.038] <TB2> INFO: PixTestScurves::fullTest() done, duration: 769 seconds
[12:01:28.038] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:01:28.038] <TB2> INFO: Decoding statistics:
[12:01:28.038] <TB2> INFO: General information:
[12:01:28.038] <TB2> INFO: 16bit words read: 0
[12:01:28.038] <TB2> INFO: valid events total: 0
[12:01:28.038] <TB2> INFO: empty events: 0
[12:01:28.038] <TB2> INFO: valid events with pixels: 0
[12:01:28.038] <TB2> INFO: valid pixel hits: 0
[12:01:28.038] <TB2> INFO: Event errors: 0
[12:01:28.038] <TB2> INFO: start marker: 0
[12:01:28.038] <TB2> INFO: stop marker: 0
[12:01:28.038] <TB2> INFO: overflow: 0
[12:01:28.038] <TB2> INFO: invalid 5bit words: 0
[12:01:28.038] <TB2> INFO: invalid XOR eye diagram: 0
[12:01:28.038] <TB2> INFO: TBM errors: 0
[12:01:28.038] <TB2> INFO: flawed TBM headers: 0
[12:01:28.038] <TB2> INFO: flawed TBM trailers: 0
[12:01:28.038] <TB2> INFO: event ID mismatches: 0
[12:01:28.038] <TB2> INFO: ROC errors: 0
[12:01:28.038] <TB2> INFO: missing ROC header(s): 0
[12:01:28.038] <TB2> INFO: misplaced readback start: 0
[12:01:28.038] <TB2> INFO: Pixel decoding errors: 0
[12:01:28.038] <TB2> INFO: pixel data incomplete: 0
[12:01:28.038] <TB2> INFO: pixel address: 0
[12:01:28.038] <TB2> INFO: pulse height fill bit: 0
[12:01:28.038] <TB2> INFO: buffer corruption: 0
[12:01:28.110] <TB2> INFO: ######################################################################
[12:01:28.110] <TB2> INFO: PixTestTrim::doTest()
[12:01:28.110] <TB2> INFO: ######################################################################
[12:01:28.111] <TB2> INFO: ----------------------------------------------------------------------
[12:01:28.111] <TB2> INFO: PixTestTrim::trimTest() ntrig = 10, vcal = 35
[12:01:28.111] <TB2> INFO: ----------------------------------------------------------------------
[12:01:28.198] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[12:01:28.198] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 10 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:01:28.209] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[12:01:28.209] <TB2> INFO: run 1 of 1
[12:01:28.520] <TB2> INFO: Expecting 6281600 events.
[12:02:14.864] <TB2> INFO: 1468650 events read in total (45629ms).
[12:03:02.653] <TB2> INFO: 2931640 events read in total (93418ms).
[12:03:45.377] <TB2> INFO: 4375800 events read in total (136143ms).
[12:04:32.315] <TB2> INFO: 5812190 events read in total (183080ms).
[12:04:47.712] <TB2> INFO: 6281600 events read in total (198477ms).
[12:04:47.741] <TB2> INFO: Test took 199532ms.
[12:04:47.786] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:05:09.423] <TB2> INFO: ROC 0 VthrComp = 113
[12:05:09.423] <TB2> INFO: ROC 1 VthrComp = 110
[12:05:09.423] <TB2> INFO: ROC 2 VthrComp = 117
[12:05:09.423] <TB2> INFO: ROC 3 VthrComp = 107
[12:05:09.423] <TB2> INFO: ROC 4 VthrComp = 102
[12:05:09.423] <TB2> INFO: ROC 5 VthrComp = 111
[12:05:09.423] <TB2> INFO: ROC 6 VthrComp = 108
[12:05:09.423] <TB2> INFO: ROC 7 VthrComp = 107
[12:05:09.424] <TB2> INFO: ROC 8 VthrComp = 108
[12:05:09.424] <TB2> INFO: ROC 9 VthrComp = 111
[12:05:09.424] <TB2> INFO: ROC 10 VthrComp = 109
[12:05:09.424] <TB2> INFO: ROC 11 VthrComp = 113
[12:05:09.424] <TB2> INFO: ROC 12 VthrComp = 110
[12:05:09.424] <TB2> INFO: ROC 13 VthrComp = 111
[12:05:09.424] <TB2> INFO: ROC 14 VthrComp = 104
[12:05:09.424] <TB2> INFO: ROC 15 VthrComp = 68
[12:05:09.425] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[12:05:09.425] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 10 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[12:05:09.434] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[12:05:09.434] <TB2> INFO: run 1 of 1
[12:05:09.768] <TB2> INFO: Expecting 6281600 events.
[12:05:44.133] <TB2> INFO: 914610 events read in total (33650ms).
[12:06:22.123] <TB2> INFO: 1826330 events read in total (71640ms).
[12:07:01.133] <TB2> INFO: 2737510 events read in total (110650ms).
[12:07:38.649] <TB2> INFO: 3642760 events read in total (148166ms).
[12:08:13.864] <TB2> INFO: 4538750 events read in total (183381ms).
[12:08:49.462] <TB2> INFO: 5430900 events read in total (218979ms).
[12:09:26.821] <TB2> INFO: 6281600 events read in total (256338ms).
[12:09:26.880] <TB2> INFO: Test took 257446ms.
[12:09:27.008] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:09:52.216] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 66.1341 for pixel 27/3 mean/min/max = 51.1014/35.9674/66.2354
[12:09:52.216] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 67.1774 for pixel 51/74 mean/min/max = 51.2135/35.1415/67.2855
[12:09:52.217] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 71.5575 for pixel 26/3 mean/min/max = 52.6857/33.2573/72.1142
[12:09:52.217] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 67.8546 for pixel 12/6 mean/min/max = 51.4691/34.9264/68.0118
[12:09:52.217] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 59.9584 for pixel 24/14 mean/min/max = 46.2707/32.4823/60.059
[12:09:52.217] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 74.1335 for pixel 0/77 mean/min/max = 57.0864/39.7297/74.443
[12:09:52.218] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 64.9796 for pixel 0/73 mean/min/max = 49.7261/34.4695/64.9827
[12:09:52.218] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 65.4716 for pixel 26/64 mean/min/max = 50.103/34.7064/65.4996
[12:09:52.218] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 64.249 for pixel 30/4 mean/min/max = 49.6548/35.0008/64.3088
[12:09:52.218] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 68.7284 for pixel 21/46 mean/min/max = 52.2544/35.7761/68.7328
[12:09:52.219] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 67.7539 for pixel 4/3 mean/min/max = 51.6551/35.541/67.7691
[12:09:52.219] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 65.2728 for pixel 10/21 mean/min/max = 49.5984/33.8836/65.3133
[12:09:52.219] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 71.8112 for pixel 0/20 mean/min/max = 55.0276/37.7021/72.3532
[12:09:52.219] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 71.3772 for pixel 1/25 mean/min/max = 54.2155/36.9971/71.4339
[12:09:52.220] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 61.5678 for pixel 20/9 mean/min/max = 47.7065/33.7283/61.6846
[12:09:52.220] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 140.065 for pixel 0/52 mean/min/max = 120.181/100.256/140.107
[12:09:52.220] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:09:52.352] <TB2> INFO: Expecting 514560 events.
[12:10:02.384] <TB2> INFO: 514560 events read in total (9313ms).
[12:10:02.390] <TB2> INFO: Expecting 514560 events.
[12:10:11.377] <TB2> INFO: 514560 events read in total (8321ms).
[12:10:11.384] <TB2> INFO: Expecting 514560 events.
[12:10:20.271] <TB2> INFO: 514560 events read in total (8217ms).
[12:10:20.280] <TB2> INFO: Expecting 514560 events.
[12:10:30.016] <TB2> INFO: 514560 events read in total (9066ms).
[12:10:30.029] <TB2> INFO: Expecting 514560 events.
[12:10:39.781] <TB2> INFO: 514560 events read in total (9095ms).
[12:10:39.795] <TB2> INFO: Expecting 514560 events.
[12:10:49.837] <TB2> INFO: 514560 events read in total (9380ms).
[12:10:49.854] <TB2> INFO: Expecting 514560 events.
[12:10:59.476] <TB2> INFO: 514560 events read in total (8972ms).
[12:10:59.497] <TB2> INFO: Expecting 514560 events.
[12:11:09.412] <TB2> INFO: 514560 events read in total (9268ms).
[12:11:09.436] <TB2> INFO: Expecting 514560 events.
[12:11:19.074] <TB2> INFO: 514560 events read in total (9002ms).
[12:11:19.097] <TB2> INFO: Expecting 514560 events.
[12:11:28.961] <TB2> INFO: 514560 events read in total (9220ms).
[12:11:28.991] <TB2> INFO: Expecting 514560 events.
[12:11:38.781] <TB2> INFO: 514560 events read in total (9161ms).
[12:11:38.807] <TB2> INFO: Expecting 514560 events.
[12:11:48.701] <TB2> INFO: 514560 events read in total (9252ms).
[12:11:48.734] <TB2> INFO: Expecting 514560 events.
[12:11:58.517] <TB2> INFO: 514560 events read in total (9155ms).
[12:11:58.552] <TB2> INFO: Expecting 514560 events.
[12:12:08.291] <TB2> INFO: 514560 events read in total (9110ms).
[12:12:08.329] <TB2> INFO: Expecting 514560 events.
[12:12:18.083] <TB2> INFO: 514560 events read in total (9130ms).
[12:12:18.119] <TB2> INFO: Expecting 514560 events.
[12:12:27.963] <TB2> INFO: 514560 events read in total (9214ms).
[12:12:27.999] <TB2> INFO: Test took 155779ms.
[12:12:29.112] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 10 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[12:12:29.121] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[12:12:29.121] <TB2> INFO: run 1 of 1
[12:12:29.424] <TB2> INFO: Expecting 6281600 events.
[12:13:09.489] <TB2> INFO: 881420 events read in total (39350ms).
[12:13:47.322] <TB2> INFO: 1760380 events read in total (77183ms).
[12:14:26.388] <TB2> INFO: 2640020 events read in total (116249ms).
[12:15:05.320] <TB2> INFO: 3514900 events read in total (155181ms).
[12:15:41.435] <TB2> INFO: 4380950 events read in total (191296ms).
[12:16:17.888] <TB2> INFO: 5242920 events read in total (227749ms).
[12:16:55.422] <TB2> INFO: 6103320 events read in total (265283ms).
[12:17:03.512] <TB2> INFO: 6281600 events read in total (273373ms).
[12:17:03.582] <TB2> INFO: Test took 274461ms.
[12:17:03.729] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:17:28.606] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 0.199002 .. 255.000000
[12:17:28.687] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 10 dacrange: 0 .. 255 (-1/-1) hits flags = 528 (plus default)
[12:17:28.696] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[12:17:28.696] <TB2> INFO: run 1 of 1
[12:17:29.006] <TB2> INFO: Expecting 10649600 events.
[12:18:00.341] <TB2> INFO: 825720 events read in total (30611ms).
[12:18:37.213] <TB2> INFO: 1652010 events read in total (67483ms).
[12:19:14.386] <TB2> INFO: 2477970 events read in total (104656ms).
[12:19:52.699] <TB2> INFO: 3304340 events read in total (142969ms).
[12:20:29.905] <TB2> INFO: 4130750 events read in total (180175ms).
[12:21:07.952] <TB2> INFO: 4957190 events read in total (218222ms).
[12:21:45.278] <TB2> INFO: 5784000 events read in total (255548ms).
[12:22:23.142] <TB2> INFO: 6611740 events read in total (293412ms).
[12:23:02.060] <TB2> INFO: 7439580 events read in total (332330ms).
[12:23:36.675] <TB2> INFO: 8267380 events read in total (366946ms).
[12:24:13.843] <TB2> INFO: 9094850 events read in total (404113ms).
[12:24:51.307] <TB2> INFO: 9922370 events read in total (441577ms).
[12:25:24.425] <TB2> INFO: 10649600 events read in total (474695ms).
[12:25:24.582] <TB2> INFO: Test took 475886ms.
[12:25:24.886] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:25:54.126] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 17.064494 .. 78.869154
[12:25:54.208] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 10 dacrange: 7 .. 88 (-1/-1) hits flags = 528 (plus default)
[12:25:54.216] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[12:25:54.216] <TB2> INFO: run 1 of 1
[12:25:54.534] <TB2> INFO: Expecting 3411200 events.
[12:26:29.132] <TB2> INFO: 953310 events read in total (33884ms).
[12:27:09.643] <TB2> INFO: 1906240 events read in total (74395ms).
[12:27:48.424] <TB2> INFO: 2858760 events read in total (113177ms).
[12:28:10.149] <TB2> INFO: 3411200 events read in total (134900ms).
[12:28:10.191] <TB2> INFO: Test took 135976ms.
[12:28:10.270] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:28:27.149] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 3.703023 .. 67.565054
[12:28:27.244] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 10 dacrange: 3 .. 77 (-1/-1) hits flags = 528 (plus default)
[12:28:27.253] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[12:28:27.253] <TB2> INFO: run 1 of 1
[12:28:27.587] <TB2> INFO: Expecting 3120000 events.
[12:29:09.123] <TB2> INFO: 1015820 events read in total (40821ms).
[12:29:48.891] <TB2> INFO: 2031330 events read in total (80590ms).
[12:30:28.918] <TB2> INFO: 3046210 events read in total (120616ms).
[12:30:32.291] <TB2> INFO: 3120000 events read in total (123989ms).
[12:30:32.328] <TB2> INFO: Test took 125074ms.
[12:30:32.390] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:30:48.310] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 0.339999 .. 67.565054
[12:30:48.393] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 10 dacrange: 0 .. 77 (-1/-1) hits flags = 528 (plus default)
[12:30:48.401] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[12:30:48.401] <TB2> INFO: run 1 of 1
[12:30:48.709] <TB2> INFO: Expecting 3244800 events.
[12:31:27.168] <TB2> INFO: 1033210 events read in total (37744ms).
[12:32:06.702] <TB2> INFO: 2066520 events read in total (77281ms).
[12:32:48.092] <TB2> INFO: 3099500 events read in total (118668ms).
[12:32:54.347] <TB2> INFO: 3244800 events read in total (124923ms).
[12:32:54.374] <TB2> INFO: Test took 125974ms.
[12:32:54.437] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:33:10.926] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:33:10.926] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 10 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[12:33:10.936] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[12:33:10.936] <TB2> INFO: run 1 of 1
[12:33:11.260] <TB2> INFO: Expecting 1705600 events.
[12:33:51.925] <TB2> INFO: 1076540 events read in total (39950ms).
[12:34:17.491] <TB2> INFO: 1705600 events read in total (65516ms).
[12:34:17.511] <TB2> INFO: Test took 66576ms.
[12:34:17.545] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:34:31.228] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C0.dat
[12:34:31.228] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C1.dat
[12:34:31.228] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C2.dat
[12:34:31.228] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C3.dat
[12:34:31.229] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C4.dat
[12:34:31.229] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C5.dat
[12:34:31.229] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C6.dat
[12:34:31.229] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C7.dat
[12:34:31.229] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C8.dat
[12:34:31.230] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C9.dat
[12:34:31.230] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C10.dat
[12:34:31.230] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C11.dat
[12:34:31.231] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C12.dat
[12:34:31.231] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C13.dat
[12:34:31.231] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C14.dat
[12:34:31.232] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C15.dat
[12:34:31.232] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters35_C0.dat
[12:34:31.242] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters35_C1.dat
[12:34:31.250] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters35_C2.dat
[12:34:31.258] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters35_C3.dat
[12:34:31.265] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters35_C4.dat
[12:34:31.274] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters35_C5.dat
[12:34:31.282] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters35_C6.dat
[12:34:31.290] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters35_C7.dat
[12:34:31.298] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters35_C8.dat
[12:34:31.306] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters35_C9.dat
[12:34:31.314] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters35_C10.dat
[12:34:31.322] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters35_C11.dat
[12:34:31.330] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters35_C12.dat
[12:34:31.338] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters35_C13.dat
[12:34:31.346] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters35_C14.dat
[12:34:31.354] <TB2> INFO: write trim parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//trimParameters35_C15.dat
[12:34:31.362] <TB2> INFO: PixTestTrim::trimTest() done
[12:34:31.362] <TB2> INFO: vtrim: 135 125 125 133 111 149 116 132 127 130 142 129 140 154 119 236
[12:34:31.362] <TB2> INFO: vthrcomp: 113 110 117 107 102 111 108 107 108 111 109 113 110 111 104 68
[12:34:31.362] <TB2> INFO: vcal mean: 35.02 34.94 34.88 34.94 34.99 35.04 35.04 34.98 34.98 34.99 35.02 34.99 35.02 35.05 35.00 39.33
[12:34:31.362] <TB2> INFO: vcal RMS: 1.20 1.55 1.00 1.29 0.92 1.05 1.20 0.94 0.86 1.09 1.17 0.91 1.11 1.02 1.06 11.30
[12:34:31.362] <TB2> INFO: bits mean: 8.15 7.99 7.84 8.13 9.46 5.97 8.16 8.31 8.22 7.87 8.60 8.38 6.96 7.89 8.87 1.02
[12:34:31.362] <TB2> INFO: bits RMS: 2.30 2.48 2.64 2.46 2.59 2.26 2.54 2.46 2.50 2.38 2.22 2.59 2.36 2.20 2.59 0.34
[12:34:31.370] <TB2> INFO: ----------------------------------------------------------------------
[12:34:31.370] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 10, vtrims = 254 126 63 32
[12:34:31.370] <TB2> INFO: ----------------------------------------------------------------------
[12:34:31.373] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 10 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[12:34:31.382] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[12:34:31.382] <TB2> INFO: run 1 of 1
[12:34:31.711] <TB2> INFO: Expecting 8320000 events.
[12:35:10.456] <TB2> INFO: 1320460 events read in total (38030ms).
[12:35:51.845] <TB2> INFO: 2624990 events read in total (79419ms).
[12:36:37.080] <TB2> INFO: 3921950 events read in total (124654ms).
[12:37:20.784] <TB2> INFO: 5201680 events read in total (168358ms).
[12:38:02.001] <TB2> INFO: 6475750 events read in total (209576ms).
[12:38:43.450] <TB2> INFO: 7748710 events read in total (251024ms).
[12:39:03.462] <TB2> INFO: 8320000 events read in total (271036ms).
[12:39:03.522] <TB2> INFO: Test took 272140ms.
[12:39:03.603] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:39:29.508] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 10 dacrange: 0 .. 208 (-1/-1) hits flags = 528 (plus default)
[12:39:29.516] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[12:39:29.520] <TB2> INFO: run 1 of 1
[12:39:29.838] <TB2> INFO: Expecting 8694400 events.
[12:40:14.028] <TB2> INFO: 1220740 events read in total (43475ms).
[12:40:54.660] <TB2> INFO: 2427940 events read in total (84107ms).
[12:41:37.765] <TB2> INFO: 3630140 events read in total (127212ms).
[12:42:19.198] <TB2> INFO: 4822630 events read in total (168645ms).
[12:43:00.875] <TB2> INFO: 6004620 events read in total (210322ms).
[12:43:43.150] <TB2> INFO: 7185350 events read in total (252597ms).
[12:44:22.494] <TB2> INFO: 8365850 events read in total (291941ms).
[12:44:35.117] <TB2> INFO: 8694400 events read in total (304564ms).
[12:44:35.157] <TB2> INFO: Test took 305637ms.
[12:44:35.252] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:45:02.698] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 10 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[12:45:02.707] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[12:45:02.710] <TB2> INFO: run 1 of 1
[12:45:03.013] <TB2> INFO: Expecting 8569600 events.
[12:45:46.755] <TB2> INFO: 1230970 events read in total (43027ms).
[12:46:30.929] <TB2> INFO: 2447840 events read in total (87201ms).
[12:47:09.793] <TB2> INFO: 3660340 events read in total (126065ms).
[12:47:55.067] <TB2> INFO: 4860760 events read in total (171339ms).
[12:48:39.232] <TB2> INFO: 6052100 events read in total (215504ms).
[12:49:15.619] <TB2> INFO: 7241460 events read in total (251891ms).
[12:49:56.986] <TB2> INFO: 8433710 events read in total (293258ms).
[12:50:01.743] <TB2> INFO: 8569600 events read in total (298015ms).
[12:50:01.783] <TB2> INFO: Test took 299073ms.
[12:50:01.875] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:50:30.884] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 10 dacrange: 0 .. 210 (-1/-1) hits flags = 528 (plus default)
[12:50:30.893] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[12:50:30.893] <TB2> INFO: run 1 of 1
[12:50:31.209] <TB2> INFO: Expecting 8777600 events.
[12:51:16.230] <TB2> INFO: 1212810 events read in total (44305ms).
[12:52:00.278] <TB2> INFO: 2411890 events read in total (88353ms).
[12:52:44.130] <TB2> INFO: 3607380 events read in total (132205ms).
[12:53:27.400] <TB2> INFO: 4793150 events read in total (175475ms).
[12:54:07.167] <TB2> INFO: 5968180 events read in total (215242ms).
[12:54:47.061] <TB2> INFO: 7141660 events read in total (255136ms).
[12:55:29.752] <TB2> INFO: 8315130 events read in total (297827ms).
[12:55:47.153] <TB2> INFO: 8777600 events read in total (315228ms).
[12:55:47.192] <TB2> INFO: Test took 316299ms.
[12:55:47.304] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[12:56:14.488] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 10 dacrange: 0 .. 209 (-1/-1) hits flags = 528 (plus default)
[12:56:14.497] <TB2> INFO: dacScan split into 1 runs with ntrig = 10
[12:56:14.497] <TB2> INFO: run 1 of 1
[12:56:14.799] <TB2> INFO: Expecting 8736000 events.
[12:56:59.872] <TB2> INFO: 1215640 events read in total (44357ms).
[12:57:43.436] <TB2> INFO: 2417950 events read in total (87921ms).
[12:58:23.749] <TB2> INFO: 3615700 events read in total (128234ms).
[12:59:03.463] <TB2> INFO: 4803700 events read in total (167948ms).
[12:59:47.328] <TB2> INFO: 5981150 events read in total (211813ms).
[13:00:30.844] <TB2> INFO: 7157400 events read in total (255329ms).
[13:01:15.453] <TB2> INFO: 8333510 events read in total (299938ms).
[13:01:31.174] <TB2> INFO: 8736000 events read in total (315659ms).
[13:01:31.214] <TB2> INFO: Test took 316717ms.
[13:01:31.311] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:01:58.376] <TB2> INFO: PixTestTrim::trimBitTest() done
[13:01:58.377] <TB2> INFO: PixTestTrim::doTest() done, duration: 3630 seconds
[13:01:58.377] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:01:58.377] <TB2> INFO: Decoding statistics:
[13:01:58.377] <TB2> INFO: General information:
[13:01:58.377] <TB2> INFO: 16bit words read: 0
[13:01:58.377] <TB2> INFO: valid events total: 0
[13:01:58.377] <TB2> INFO: empty events: 0
[13:01:58.377] <TB2> INFO: valid events with pixels: 0
[13:01:58.377] <TB2> INFO: valid pixel hits: 0
[13:01:58.377] <TB2> INFO: Event errors: 0
[13:01:58.377] <TB2> INFO: start marker: 0
[13:01:58.377] <TB2> INFO: stop marker: 0
[13:01:58.377] <TB2> INFO: overflow: 0
[13:01:58.377] <TB2> INFO: invalid 5bit words: 0
[13:01:58.377] <TB2> INFO: invalid XOR eye diagram: 0
[13:01:58.377] <TB2> INFO: TBM errors: 0
[13:01:58.377] <TB2> INFO: flawed TBM headers: 0
[13:01:58.377] <TB2> INFO: flawed TBM trailers: 0
[13:01:58.377] <TB2> INFO: event ID mismatches: 0
[13:01:58.377] <TB2> INFO: ROC errors: 0
[13:01:58.377] <TB2> INFO: missing ROC header(s): 0
[13:01:58.377] <TB2> INFO: misplaced readback start: 0
[13:01:58.377] <TB2> INFO: Pixel decoding errors: 0
[13:01:58.377] <TB2> INFO: pixel data incomplete: 0
[13:01:58.377] <TB2> INFO: pixel address: 0
[13:01:58.377] <TB2> INFO: pulse height fill bit: 0
[13:01:58.377] <TB2> INFO: buffer corruption: 0
[13:01:59.065] <TB2> INFO: ######################################################################
[13:01:59.065] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:01:59.065] <TB2> INFO: ######################################################################
[13:01:59.371] <TB2> INFO: Expecting 41600 events.
[13:02:03.789] <TB2> INFO: 41600 events read in total (3701ms).
[13:02:03.789] <TB2> INFO: Test took 4723ms.
[13:02:03.795] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:02:04.489] <TB2> INFO: Expecting 41600 events.
[13:02:09.095] <TB2> INFO: 41600 events read in total (3891ms).
[13:02:09.096] <TB2> INFO: Test took 4945ms.
[13:02:09.103] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:02:09.525] <TB2> INFO: Expecting 41600 events.
[13:02:13.938] <TB2> INFO: 41600 events read in total (3698ms).
[13:02:13.939] <TB2> INFO: Test took 4746ms.
[13:02:13.945] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:02:14.386] <TB2> INFO: Expecting 41600 events.
[13:02:18.855] <TB2> INFO: 41600 events read in total (3754ms).
[13:02:18.856] <TB2> INFO: Test took 4794ms.
[13:02:18.863] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:02:19.274] <TB2> INFO: Expecting 41600 events.
[13:02:23.792] <TB2> INFO: 41600 events read in total (3803ms).
[13:02:23.793] <TB2> INFO: Test took 4842ms.
[13:02:23.799] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:02:24.238] <TB2> INFO: Expecting 41600 events.
[13:02:28.799] <TB2> INFO: 41600 events read in total (3846ms).
[13:02:28.799] <TB2> INFO: Test took 4903ms.
[13:02:28.806] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:02:29.251] <TB2> INFO: Expecting 2560 events.
[13:02:30.227] <TB2> INFO: 2560 events read in total (261ms).
[13:02:30.227] <TB2> INFO: Test took 1411ms.
[13:02:30.735] <TB2> INFO: Expecting 2560 events.
[13:02:31.696] <TB2> INFO: 2560 events read in total (246ms).
[13:02:31.696] <TB2> INFO: Test took 1468ms.
[13:02:32.204] <TB2> INFO: Expecting 2560 events.
[13:02:33.194] <TB2> INFO: 2560 events read in total (275ms).
[13:02:33.194] <TB2> INFO: Test took 1498ms.
[13:02:33.702] <TB2> INFO: Expecting 2560 events.
[13:02:34.664] <TB2> INFO: 2560 events read in total (247ms).
[13:02:34.664] <TB2> INFO: Test took 1469ms.
[13:02:35.171] <TB2> INFO: Expecting 2560 events.
[13:02:36.138] <TB2> INFO: 2560 events read in total (252ms).
[13:02:36.138] <TB2> INFO: Test took 1473ms.
[13:02:36.646] <TB2> INFO: Expecting 2560 events.
[13:02:37.610] <TB2> INFO: 2560 events read in total (249ms).
[13:02:37.610] <TB2> INFO: Test took 1471ms.
[13:02:38.118] <TB2> INFO: Expecting 2560 events.
[13:02:39.094] <TB2> INFO: 2560 events read in total (261ms).
[13:02:39.095] <TB2> INFO: Test took 1484ms.
[13:02:39.602] <TB2> INFO: Expecting 2560 events.
[13:02:40.564] <TB2> INFO: 2560 events read in total (247ms).
[13:02:40.564] <TB2> INFO: Test took 1469ms.
[13:02:41.072] <TB2> INFO: Expecting 2560 events.
[13:02:42.030] <TB2> INFO: 2560 events read in total (243ms).
[13:02:42.030] <TB2> INFO: Test took 1466ms.
[13:02:42.538] <TB2> INFO: Expecting 2560 events.
[13:02:43.499] <TB2> INFO: 2560 events read in total (246ms).
[13:02:43.499] <TB2> INFO: Test took 1469ms.
[13:02:44.007] <TB2> INFO: Expecting 2560 events.
[13:02:44.969] <TB2> INFO: 2560 events read in total (247ms).
[13:02:44.969] <TB2> INFO: Test took 1469ms.
[13:02:45.477] <TB2> INFO: Expecting 2560 events.
[13:02:46.453] <TB2> INFO: 2560 events read in total (261ms).
[13:02:46.453] <TB2> INFO: Test took 1483ms.
[13:02:46.961] <TB2> INFO: Expecting 2560 events.
[13:02:47.937] <TB2> INFO: 2560 events read in total (261ms).
[13:02:47.937] <TB2> INFO: Test took 1483ms.
[13:02:48.445] <TB2> INFO: Expecting 2560 events.
[13:02:49.405] <TB2> INFO: 2560 events read in total (245ms).
[13:02:49.405] <TB2> INFO: Test took 1467ms.
[13:02:49.913] <TB2> INFO: Expecting 2560 events.
[13:02:50.874] <TB2> INFO: 2560 events read in total (246ms).
[13:02:50.874] <TB2> INFO: Test took 1469ms.
[13:02:51.382] <TB2> INFO: Expecting 2560 events.
[13:02:52.344] <TB2> INFO: 2560 events read in total (247ms).
[13:02:52.345] <TB2> INFO: Test took 1470ms.
[13:02:52.349] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:02:52.853] <TB2> INFO: Expecting 655360 events.
[13:03:05.442] <TB2> INFO: 655360 events read in total (11874ms).
[13:03:05.451] <TB2> INFO: Expecting 655360 events.
[13:03:19.323] <TB2> INFO: 655360 events read in total (13273ms).
[13:03:19.335] <TB2> INFO: Expecting 655360 events.
[13:03:30.761] <TB2> INFO: 655360 events read in total (10825ms).
[13:03:30.776] <TB2> INFO: Expecting 655360 events.
[13:03:42.133] <TB2> INFO: 655360 events read in total (10768ms).
[13:03:42.153] <TB2> INFO: Expecting 655360 events.
[13:03:54.016] <TB2> INFO: 655360 events read in total (11275ms).
[13:03:54.045] <TB2> INFO: Expecting 655360 events.
[13:04:06.763] <TB2> INFO: 655360 events read in total (12167ms).
[13:04:06.788] <TB2> INFO: Expecting 655360 events.
[13:04:19.229] <TB2> INFO: 655360 events read in total (11857ms).
[13:04:19.258] <TB2> INFO: Expecting 655360 events.
[13:04:31.623] <TB2> INFO: 655360 events read in total (11792ms).
[13:04:31.655] <TB2> INFO: Expecting 655360 events.
[13:04:44.781] <TB2> INFO: 655360 events read in total (12543ms).
[13:04:44.831] <TB2> INFO: Expecting 655360 events.
[13:04:58.059] <TB2> INFO: 655360 events read in total (12692ms).
[13:04:58.100] <TB2> INFO: Expecting 655360 events.
[13:05:11.328] <TB2> INFO: 655360 events read in total (12667ms).
[13:05:11.371] <TB2> INFO: Expecting 655360 events.
[13:05:24.152] <TB2> INFO: 655360 events read in total (12219ms).
[13:05:24.197] <TB2> INFO: Expecting 655360 events.
[13:05:36.145] <TB2> INFO: 655360 events read in total (11397ms).
[13:05:36.194] <TB2> INFO: Expecting 655360 events.
[13:05:48.093] <TB2> INFO: 655360 events read in total (11333ms).
[13:05:48.158] <TB2> INFO: Expecting 655360 events.
[13:05:59.980] <TB2> INFO: 655360 events read in total (11286ms).
[13:06:00.041] <TB2> INFO: Expecting 655360 events.
[13:06:13.190] <TB2> INFO: 655360 events read in total (12617ms).
[13:06:13.248] <TB2> INFO: Test took 200899ms.
[13:06:13.344] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:06:13.650] <TB2> INFO: Expecting 655360 events.
[13:06:26.732] <TB2> INFO: 655360 events read in total (12367ms).
[13:06:26.741] <TB2> INFO: Expecting 655360 events.
[13:06:39.650] <TB2> INFO: 655360 events read in total (12311ms).
[13:06:39.662] <TB2> INFO: Expecting 655360 events.
[13:06:52.433] <TB2> INFO: 655360 events read in total (12166ms).
[13:06:52.448] <TB2> INFO: Expecting 655360 events.
[13:07:05.586] <TB2> INFO: 655360 events read in total (12532ms).
[13:07:05.604] <TB2> INFO: Expecting 655360 events.
[13:07:18.835] <TB2> INFO: 655360 events read in total (12634ms).
[13:07:18.858] <TB2> INFO: Expecting 655360 events.
[13:07:32.041] <TB2> INFO: 655360 events read in total (12591ms).
[13:07:32.067] <TB2> INFO: Expecting 655360 events.
[13:07:44.983] <TB2> INFO: 655360 events read in total (12328ms).
[13:07:45.015] <TB2> INFO: Expecting 655360 events.
[13:07:57.718] <TB2> INFO: 655360 events read in total (12122ms).
[13:07:57.750] <TB2> INFO: Expecting 655360 events.
[13:08:10.829] <TB2> INFO: 655360 events read in total (12507ms).
[13:08:10.864] <TB2> INFO: Expecting 655360 events.
[13:08:24.541] <TB2> INFO: 655360 events read in total (13100ms).
[13:08:24.583] <TB2> INFO: Expecting 655360 events.
[13:08:38.097] <TB2> INFO: 655360 events read in total (12944ms).
[13:08:38.138] <TB2> INFO: Expecting 655360 events.
[13:08:51.517] <TB2> INFO: 655360 events read in total (12800ms).
[13:08:51.564] <TB2> INFO: Expecting 655360 events.
[13:09:04.537] <TB2> INFO: 655360 events read in total (12426ms).
[13:09:04.587] <TB2> INFO: Expecting 655360 events.
[13:09:17.949] <TB2> INFO: 655360 events read in total (12803ms).
[13:09:18.002] <TB2> INFO: Expecting 655360 events.
[13:09:31.214] <TB2> INFO: 655360 events read in total (12686ms).
[13:09:31.269] <TB2> INFO: Expecting 655360 events.
[13:09:44.979] <TB2> INFO: 655360 events read in total (13159ms).
[13:09:45.039] <TB2> INFO: Test took 211695ms.
[13:09:45.236] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:45.243] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:45.250] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:45.256] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:09:45.263] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:45.270] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:45.276] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:45.287] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:45.297] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:45.306] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:45.312] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:45.319] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:45.326] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:45.333] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:45.339] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[13:09:45.346] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[13:09:45.352] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[13:09:45.359] <TB2> INFO: safety margin for low PH: adding 4, margin is now 24
[13:09:45.366] <TB2> INFO: safety margin for low PH: adding 5, margin is now 25
[13:09:45.372] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:45.381] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:45.390] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[13:09:45.435] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C0.dat
[13:09:45.435] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C1.dat
[13:09:45.435] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C2.dat
[13:09:45.435] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C3.dat
[13:09:45.435] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C4.dat
[13:09:45.435] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C5.dat
[13:09:45.436] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C6.dat
[13:09:45.436] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C7.dat
[13:09:45.436] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C8.dat
[13:09:45.436] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C9.dat
[13:09:45.436] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C10.dat
[13:09:45.437] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C11.dat
[13:09:45.437] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C12.dat
[13:09:45.437] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C13.dat
[13:09:45.437] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C14.dat
[13:09:45.437] <TB2> INFO: write dac parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//dacParameters35_C15.dat
[13:09:45.755] <TB2> INFO: Expecting 41600 events.
[13:09:49.956] <TB2> INFO: 41600 events read in total (3486ms).
[13:09:49.956] <TB2> INFO: Test took 4516ms.
[13:09:50.621] <TB2> INFO: Expecting 41600 events.
[13:09:54.578] <TB2> INFO: 41600 events read in total (3242ms).
[13:09:54.578] <TB2> INFO: Test took 4323ms.
[13:09:55.216] <TB2> INFO: Expecting 41600 events.
[13:09:59.206] <TB2> INFO: 41600 events read in total (3275ms).
[13:09:59.206] <TB2> INFO: Test took 4296ms.
[13:09:59.539] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:09:59.671] <TB2> INFO: Expecting 2560 events.
[13:10:00.636] <TB2> INFO: 2560 events read in total (250ms).
[13:10:00.636] <TB2> INFO: Test took 1098ms.
[13:10:00.639] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:01.144] <TB2> INFO: Expecting 2560 events.
[13:10:02.107] <TB2> INFO: 2560 events read in total (248ms).
[13:10:02.107] <TB2> INFO: Test took 1468ms.
[13:10:02.110] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:02.615] <TB2> INFO: Expecting 2560 events.
[13:10:03.594] <TB2> INFO: 2560 events read in total (264ms).
[13:10:03.595] <TB2> INFO: Test took 1485ms.
[13:10:03.597] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:04.104] <TB2> INFO: Expecting 2560 events.
[13:10:05.065] <TB2> INFO: 2560 events read in total (246ms).
[13:10:05.065] <TB2> INFO: Test took 1468ms.
[13:10:05.067] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:05.574] <TB2> INFO: Expecting 2560 events.
[13:10:06.564] <TB2> INFO: 2560 events read in total (275ms).
[13:10:06.565] <TB2> INFO: Test took 1498ms.
[13:10:06.566] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:07.074] <TB2> INFO: Expecting 2560 events.
[13:10:08.050] <TB2> INFO: 2560 events read in total (261ms).
[13:10:08.050] <TB2> INFO: Test took 1484ms.
[13:10:08.052] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:08.558] <TB2> INFO: Expecting 2560 events.
[13:10:09.519] <TB2> INFO: 2560 events read in total (245ms).
[13:10:09.520] <TB2> INFO: Test took 1468ms.
[13:10:09.523] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:10.029] <TB2> INFO: Expecting 2560 events.
[13:10:10.990] <TB2> INFO: 2560 events read in total (246ms).
[13:10:10.990] <TB2> INFO: Test took 1467ms.
[13:10:10.993] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:11.499] <TB2> INFO: Expecting 2560 events.
[13:10:12.460] <TB2> INFO: 2560 events read in total (246ms).
[13:10:12.460] <TB2> INFO: Test took 1468ms.
[13:10:12.463] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:12.970] <TB2> INFO: Expecting 2560 events.
[13:10:13.948] <TB2> INFO: 2560 events read in total (263ms).
[13:10:13.948] <TB2> INFO: Test took 1485ms.
[13:10:13.951] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:14.456] <TB2> INFO: Expecting 2560 events.
[13:10:15.418] <TB2> INFO: 2560 events read in total (247ms).
[13:10:15.418] <TB2> INFO: Test took 1467ms.
[13:10:15.421] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:15.927] <TB2> INFO: Expecting 2560 events.
[13:10:16.889] <TB2> INFO: 2560 events read in total (247ms).
[13:10:16.890] <TB2> INFO: Test took 1470ms.
[13:10:16.893] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:17.398] <TB2> INFO: Expecting 2560 events.
[13:10:18.364] <TB2> INFO: 2560 events read in total (251ms).
[13:10:18.365] <TB2> INFO: Test took 1473ms.
[13:10:18.367] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:18.873] <TB2> INFO: Expecting 2560 events.
[13:10:19.839] <TB2> INFO: 2560 events read in total (251ms).
[13:10:19.839] <TB2> INFO: Test took 1472ms.
[13:10:19.842] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:20.347] <TB2> INFO: Expecting 2560 events.
[13:10:21.305] <TB2> INFO: 2560 events read in total (243ms).
[13:10:21.305] <TB2> INFO: Test took 1463ms.
[13:10:21.307] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:21.814] <TB2> INFO: Expecting 2560 events.
[13:10:22.775] <TB2> INFO: 2560 events read in total (246ms).
[13:10:22.775] <TB2> INFO: Test took 1468ms.
[13:10:22.778] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:23.283] <TB2> INFO: Expecting 2560 events.
[13:10:24.240] <TB2> INFO: 2560 events read in total (242ms).
[13:10:24.241] <TB2> INFO: Test took 1464ms.
[13:10:24.243] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:24.750] <TB2> INFO: Expecting 2560 events.
[13:10:25.711] <TB2> INFO: 2560 events read in total (246ms).
[13:10:25.711] <TB2> INFO: Test took 1468ms.
[13:10:25.713] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:26.220] <TB2> INFO: Expecting 2560 events.
[13:10:27.178] <TB2> INFO: 2560 events read in total (243ms).
[13:10:27.178] <TB2> INFO: Test took 1465ms.
[13:10:27.181] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:27.686] <TB2> INFO: Expecting 2560 events.
[13:10:28.647] <TB2> INFO: 2560 events read in total (246ms).
[13:10:28.647] <TB2> INFO: Test took 1466ms.
[13:10:28.649] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:29.156] <TB2> INFO: Expecting 2560 events.
[13:10:30.132] <TB2> INFO: 2560 events read in total (261ms).
[13:10:30.132] <TB2> INFO: Test took 1483ms.
[13:10:30.135] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:30.641] <TB2> INFO: Expecting 2560 events.
[13:10:31.617] <TB2> INFO: 2560 events read in total (261ms).
[13:10:31.617] <TB2> INFO: Test took 1482ms.
[13:10:31.619] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:32.125] <TB2> INFO: Expecting 2560 events.
[13:10:33.100] <TB2> INFO: 2560 events read in total (260ms).
[13:10:33.101] <TB2> INFO: Test took 1482ms.
[13:10:33.103] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:33.610] <TB2> INFO: Expecting 2560 events.
[13:10:34.571] <TB2> INFO: 2560 events read in total (246ms).
[13:10:34.571] <TB2> INFO: Test took 1468ms.
[13:10:34.573] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:35.080] <TB2> INFO: Expecting 2560 events.
[13:10:36.041] <TB2> INFO: 2560 events read in total (246ms).
[13:10:36.042] <TB2> INFO: Test took 1469ms.
[13:10:36.044] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:36.551] <TB2> INFO: Expecting 2560 events.
[13:10:37.513] <TB2> INFO: 2560 events read in total (247ms).
[13:10:37.513] <TB2> INFO: Test took 1469ms.
[13:10:37.516] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:38.022] <TB2> INFO: Expecting 2560 events.
[13:10:38.983] <TB2> INFO: 2560 events read in total (246ms).
[13:10:38.984] <TB2> INFO: Test took 1468ms.
[13:10:38.986] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:39.492] <TB2> INFO: Expecting 2560 events.
[13:10:40.454] <TB2> INFO: 2560 events read in total (247ms).
[13:10:40.455] <TB2> INFO: Test took 1469ms.
[13:10:40.457] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:40.963] <TB2> INFO: Expecting 2560 events.
[13:10:41.923] <TB2> INFO: 2560 events read in total (245ms).
[13:10:41.923] <TB2> INFO: Test took 1467ms.
[13:10:41.926] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:42.432] <TB2> INFO: Expecting 2560 events.
[13:10:43.408] <TB2> INFO: 2560 events read in total (261ms).
[13:10:43.408] <TB2> INFO: Test took 1483ms.
[13:10:43.411] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:43.917] <TB2> INFO: Expecting 2560 events.
[13:10:44.875] <TB2> INFO: 2560 events read in total (243ms).
[13:10:44.875] <TB2> INFO: Test took 1465ms.
[13:10:44.877] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:10:45.384] <TB2> INFO: Expecting 2560 events.
[13:10:46.342] <TB2> INFO: 2560 events read in total (243ms).
[13:10:46.342] <TB2> INFO: Test took 1465ms.
[13:10:47.058] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 527 seconds
[13:10:47.058] <TB2> INFO: PH scale (per ROC): 83 80 74 74 69 89 81 79 76 75 74 76 70 74 67 69
[13:10:47.058] <TB2> INFO: PH offset (per ROC): 157 161 176 175 159 165 163 153 174 156 164 183 176 163 167 165
[13:10:47.065] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:10:47.065] <TB2> INFO: Decoding statistics:
[13:10:47.065] <TB2> INFO: General information:
[13:10:47.065] <TB2> INFO: 16bit words read: 66356
[13:10:47.065] <TB2> INFO: valid events total: 5120
[13:10:47.065] <TB2> INFO: empty events: 2662
[13:10:47.065] <TB2> INFO: valid events with pixels: 2458
[13:10:47.065] <TB2> INFO: valid pixel hits: 2458
[13:10:47.065] <TB2> INFO: Event errors: 0
[13:10:47.065] <TB2> INFO: start marker: 0
[13:10:47.065] <TB2> INFO: stop marker: 0
[13:10:47.065] <TB2> INFO: overflow: 0
[13:10:47.065] <TB2> INFO: invalid 5bit words: 0
[13:10:47.065] <TB2> INFO: invalid XOR eye diagram: 0
[13:10:47.065] <TB2> INFO: TBM errors: 0
[13:10:47.065] <TB2> INFO: flawed TBM headers: 0
[13:10:47.065] <TB2> INFO: flawed TBM trailers: 0
[13:10:47.065] <TB2> INFO: event ID mismatches: 0
[13:10:47.065] <TB2> INFO: ROC errors: 0
[13:10:47.065] <TB2> INFO: missing ROC header(s): 0
[13:10:47.065] <TB2> INFO: misplaced readback start: 0
[13:10:47.065] <TB2> INFO: Pixel decoding errors: 0
[13:10:47.065] <TB2> INFO: pixel data incomplete: 0
[13:10:47.065] <TB2> INFO: pixel address: 0
[13:10:47.065] <TB2> INFO: pulse height fill bit: 0
[13:10:47.065] <TB2> INFO: buffer corruption: 0
[13:10:47.234] <TB2> INFO: ######################################################################
[13:10:47.234] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:10:47.234] <TB2> INFO: ######################################################################
[13:10:47.243] <TB2> INFO: scanning low vcal = 10
[13:10:47.543] <TB2> INFO: Expecting 41600 events.
[13:10:51.328] <TB2> INFO: 41600 events read in total (3070ms).
[13:10:51.328] <TB2> INFO: Test took 4085ms.
[13:10:51.331] <TB2> INFO: scanning low vcal = 20
[13:10:51.836] <TB2> INFO: Expecting 41600 events.
[13:10:55.714] <TB2> INFO: 41600 events read in total (3163ms).
[13:10:55.714] <TB2> INFO: Test took 4383ms.
[13:10:55.717] <TB2> INFO: scanning low vcal = 30
[13:10:56.222] <TB2> INFO: Expecting 41600 events.
[13:11:00.040] <TB2> INFO: 41600 events read in total (3103ms).
[13:11:00.040] <TB2> INFO: Test took 4323ms.
[13:11:00.042] <TB2> INFO: scanning low vcal = 40
[13:11:00.539] <TB2> INFO: Expecting 41600 events.
[13:11:05.011] <TB2> INFO: 41600 events read in total (3757ms).
[13:11:05.012] <TB2> INFO: Test took 4969ms.
[13:11:05.014] <TB2> INFO: scanning low vcal = 50
[13:11:05.436] <TB2> INFO: Expecting 41600 events.
[13:11:09.980] <TB2> INFO: 41600 events read in total (3829ms).
[13:11:09.980] <TB2> INFO: Test took 4966ms.
[13:11:09.984] <TB2> INFO: scanning low vcal = 60
[13:11:10.432] <TB2> INFO: Expecting 41600 events.
[13:11:14.728] <TB2> INFO: 41600 events read in total (3582ms).
[13:11:14.729] <TB2> INFO: Test took 4745ms.
[13:11:14.732] <TB2> INFO: scanning low vcal = 70
[13:11:15.181] <TB2> INFO: Expecting 41600 events.
[13:11:19.711] <TB2> INFO: 41600 events read in total (3815ms).
[13:11:19.711] <TB2> INFO: Test took 4979ms.
[13:11:19.714] <TB2> INFO: scanning low vcal = 80
[13:11:20.130] <TB2> INFO: Expecting 41600 events.
[13:11:24.680] <TB2> INFO: 41600 events read in total (3836ms).
[13:11:24.681] <TB2> INFO: Test took 4967ms.
[13:11:24.684] <TB2> INFO: scanning low vcal = 90
[13:11:25.132] <TB2> INFO: Expecting 41600 events.
[13:11:29.663] <TB2> INFO: 41600 events read in total (3816ms).
[13:11:29.663] <TB2> INFO: Test took 4979ms.
[13:11:29.666] <TB2> INFO: scanning low vcal = 100
[13:11:30.105] <TB2> INFO: Expecting 41600 events.
[13:11:34.605] <TB2> INFO: 41600 events read in total (3785ms).
[13:11:34.606] <TB2> INFO: Test took 4940ms.
[13:11:34.609] <TB2> INFO: scanning low vcal = 110
[13:11:35.051] <TB2> INFO: Expecting 41600 events.
[13:11:39.453] <TB2> INFO: 41600 events read in total (3688ms).
[13:11:39.454] <TB2> INFO: Test took 4845ms.
[13:11:39.460] <TB2> INFO: scanning low vcal = 120
[13:11:39.888] <TB2> INFO: Expecting 41600 events.
[13:11:44.195] <TB2> INFO: 41600 events read in total (3592ms).
[13:11:44.196] <TB2> INFO: Test took 4736ms.
[13:11:44.198] <TB2> INFO: scanning low vcal = 130
[13:11:44.644] <TB2> INFO: Expecting 41600 events.
[13:11:48.956] <TB2> INFO: 41600 events read in total (3597ms).
[13:11:48.956] <TB2> INFO: Test took 4758ms.
[13:11:48.959] <TB2> INFO: scanning low vcal = 140
[13:11:49.407] <TB2> INFO: Expecting 41600 events.
[13:11:53.778] <TB2> INFO: 41600 events read in total (3656ms).
[13:11:53.778] <TB2> INFO: Test took 4819ms.
[13:11:53.781] <TB2> INFO: scanning low vcal = 150
[13:11:54.230] <TB2> INFO: Expecting 41600 events.
[13:11:58.612] <TB2> INFO: 41600 events read in total (3667ms).
[13:11:58.613] <TB2> INFO: Test took 4832ms.
[13:11:58.615] <TB2> INFO: scanning low vcal = 160
[13:11:59.046] <TB2> INFO: Expecting 41600 events.
[13:12:03.465] <TB2> INFO: 41600 events read in total (3704ms).
[13:12:03.465] <TB2> INFO: Test took 4850ms.
[13:12:03.468] <TB2> INFO: scanning low vcal = 170
[13:12:03.900] <TB2> INFO: Expecting 41600 events.
[13:12:08.318] <TB2> INFO: 41600 events read in total (3703ms).
[13:12:08.318] <TB2> INFO: Test took 4850ms.
[13:12:08.322] <TB2> INFO: scanning low vcal = 180
[13:12:08.757] <TB2> INFO: Expecting 41600 events.
[13:12:13.085] <TB2> INFO: 41600 events read in total (3613ms).
[13:12:13.086] <TB2> INFO: Test took 4763ms.
[13:12:13.088] <TB2> INFO: scanning low vcal = 190
[13:12:13.536] <TB2> INFO: Expecting 41600 events.
[13:12:17.986] <TB2> INFO: 41600 events read in total (3735ms).
[13:12:17.987] <TB2> INFO: Test took 4899ms.
[13:12:17.989] <TB2> INFO: scanning low vcal = 200
[13:12:18.403] <TB2> INFO: Expecting 41600 events.
[13:12:22.844] <TB2> INFO: 41600 events read in total (3726ms).
[13:12:22.844] <TB2> INFO: Test took 4855ms.
[13:12:22.847] <TB2> INFO: scanning low vcal = 210
[13:12:23.260] <TB2> INFO: Expecting 41600 events.
[13:12:27.663] <TB2> INFO: 41600 events read in total (3688ms).
[13:12:27.663] <TB2> INFO: Test took 4816ms.
[13:12:27.669] <TB2> INFO: scanning low vcal = 220
[13:12:28.097] <TB2> INFO: Expecting 41600 events.
[13:12:32.516] <TB2> INFO: 41600 events read in total (3704ms).
[13:12:32.517] <TB2> INFO: Test took 4848ms.
[13:12:32.520] <TB2> INFO: scanning low vcal = 230
[13:12:32.962] <TB2> INFO: Expecting 41600 events.
[13:12:37.235] <TB2> INFO: 41600 events read in total (3558ms).
[13:12:37.236] <TB2> INFO: Test took 4716ms.
[13:12:37.238] <TB2> INFO: scanning low vcal = 240
[13:12:37.689] <TB2> INFO: Expecting 41600 events.
[13:12:41.998] <TB2> INFO: 41600 events read in total (3594ms).
[13:12:41.998] <TB2> INFO: Test took 4760ms.
[13:12:42.001] <TB2> INFO: scanning low vcal = 250
[13:12:42.450] <TB2> INFO: Expecting 41600 events.
[13:12:46.776] <TB2> INFO: 41600 events read in total (3611ms).
[13:12:46.776] <TB2> INFO: Test took 4775ms.
[13:12:46.780] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[13:12:47.225] <TB2> INFO: Expecting 41600 events.
[13:12:51.618] <TB2> INFO: 41600 events read in total (3678ms).
[13:12:51.619] <TB2> INFO: Test took 4839ms.
[13:12:51.622] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[13:12:52.066] <TB2> INFO: Expecting 41600 events.
[13:12:56.389] <TB2> INFO: 41600 events read in total (3608ms).
[13:12:56.389] <TB2> INFO: Test took 4767ms.
[13:12:56.392] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[13:12:56.841] <TB2> INFO: Expecting 41600 events.
[13:13:01.158] <TB2> INFO: 41600 events read in total (3602ms).
[13:13:01.159] <TB2> INFO: Test took 4767ms.
[13:13:01.161] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[13:13:01.606] <TB2> INFO: Expecting 41600 events.
[13:13:05.918] <TB2> INFO: 41600 events read in total (3597ms).
[13:13:05.918] <TB2> INFO: Test took 4756ms.
[13:13:05.921] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[13:13:06.371] <TB2> INFO: Expecting 41600 events.
[13:13:10.760] <TB2> INFO: 41600 events read in total (3675ms).
[13:13:10.761] <TB2> INFO: Test took 4840ms.
[13:13:11.271] <TB2> INFO: PixTestGainPedestal::measure() done
[13:13:44.225] <TB2> INFO: PixTestGainPedestal::fit() done
[13:13:44.225] <TB2> INFO: non-linearity mean: 0.961 0.958 0.957 0.952 0.954 0.955 0.963 0.958 0.953 0.951 0.958 0.956 0.960 0.960 0.955 0.959
[13:13:44.225] <TB2> INFO: non-linearity RMS: 0.006 0.005 0.006 0.007 0.007 0.006 0.006 0.007 0.007 0.006 0.006 0.006 0.005 0.007 0.007 0.007
[13:13:44.225] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//phCalibrationFitErr35_C0.dat
[13:13:44.243] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//phCalibrationFitErr35_C1.dat
[13:13:44.261] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//phCalibrationFitErr35_C2.dat
[13:13:44.279] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//phCalibrationFitErr35_C3.dat
[13:13:44.296] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//phCalibrationFitErr35_C4.dat
[13:13:44.314] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//phCalibrationFitErr35_C5.dat
[13:13:44.332] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//phCalibrationFitErr35_C6.dat
[13:13:44.350] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//phCalibrationFitErr35_C7.dat
[13:13:44.368] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//phCalibrationFitErr35_C8.dat
[13:13:44.385] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//phCalibrationFitErr35_C9.dat
[13:13:44.403] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//phCalibrationFitErr35_C10.dat
[13:13:44.420] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//phCalibrationFitErr35_C11.dat
[13:13:44.438] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//phCalibrationFitErr35_C12.dat
[13:13:44.456] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//phCalibrationFitErr35_C13.dat
[13:13:44.474] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//phCalibrationFitErr35_C14.dat
[13:13:44.491] <TB2> INFO: write gain/ped parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//phCalibrationFitErr35_C15.dat
[13:13:44.509] <TB2> INFO: PixTestGainPedestal::fullTest() done, duration: 177 seconds
[13:13:44.509] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:13:44.509] <TB2> INFO: Decoding statistics:
[13:13:44.509] <TB2> INFO: General information:
[13:13:44.509] <TB2> INFO: 16bit words read: 2329286
[13:13:44.509] <TB2> INFO: valid events total: 83200
[13:13:44.509] <TB2> INFO: empty events: 0
[13:13:44.509] <TB2> INFO: valid events with pixels: 83200
[13:13:44.509] <TB2> INFO: valid pixel hits: 665443
[13:13:44.509] <TB2> INFO: Event errors: 0
[13:13:44.509] <TB2> INFO: start marker: 0
[13:13:44.509] <TB2> INFO: stop marker: 0
[13:13:44.509] <TB2> INFO: overflow: 0
[13:13:44.509] <TB2> INFO: invalid 5bit words: 0
[13:13:44.509] <TB2> INFO: invalid XOR eye diagram: 0
[13:13:44.509] <TB2> INFO: TBM errors: 0
[13:13:44.509] <TB2> INFO: flawed TBM headers: 0
[13:13:44.509] <TB2> INFO: flawed TBM trailers: 0
[13:13:44.509] <TB2> INFO: event ID mismatches: 0
[13:13:44.509] <TB2> INFO: ROC errors: 0
[13:13:44.509] <TB2> INFO: missing ROC header(s): 0
[13:13:44.509] <TB2> INFO: misplaced readback start: 0
[13:13:44.509] <TB2> INFO: Pixel decoding errors: 0
[13:13:44.509] <TB2> INFO: pixel data incomplete: 0
[13:13:44.509] <TB2> INFO: pixel address: 0
[13:13:44.509] <TB2> INFO: pulse height fill bit: 0
[13:13:44.509] <TB2> INFO: buffer corruption: 0
[13:13:44.515] <TB2> INFO: readReadbackCal: /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C0.dat .. /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C15.dat
[13:13:44.516] <TB2> INFO: ######################################################################
[13:13:44.516] <TB2> INFO: PixTestReadback::doTest()
[13:13:44.516] <TB2> INFO: ######################################################################
[13:13:44.517] <TB2> INFO: PixTestReadback::RES sent once
[13:13:55.714] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C0.dat
[13:13:55.714] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C1.dat
[13:13:55.715] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C2.dat
[13:13:55.715] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C3.dat
[13:13:55.716] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C4.dat
[13:13:55.716] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C5.dat
[13:13:55.716] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C6.dat
[13:13:55.716] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C7.dat
[13:13:55.716] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C8.dat
[13:13:55.716] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C9.dat
[13:13:55.717] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C10.dat
[13:13:55.717] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C11.dat
[13:13:55.717] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C12.dat
[13:13:55.717] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C13.dat
[13:13:55.717] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C14.dat
[13:13:55.717] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C15.dat
[13:13:55.748] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:13:55.748] <TB2> INFO: PixTestReadback::RES sent once
[13:14:06.902] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C0.dat
[13:14:06.902] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C1.dat
[13:14:06.903] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C2.dat
[13:14:06.903] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C3.dat
[13:14:06.903] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C4.dat
[13:14:06.903] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C5.dat
[13:14:06.903] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C6.dat
[13:14:06.903] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C7.dat
[13:14:06.904] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C8.dat
[13:14:06.904] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C9.dat
[13:14:06.904] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C10.dat
[13:14:06.904] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C11.dat
[13:14:06.904] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C12.dat
[13:14:06.904] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C13.dat
[13:14:06.905] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C14.dat
[13:14:06.905] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C15.dat
[13:14:06.938] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:14:06.938] <TB2> INFO: PixTestReadback::RES sent once
[13:14:15.514] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:14:15.514] <TB2> INFO: Vbg will be calibrated using Vd calibration
[13:14:15.514] <TB2> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 153.8calibrated Vbg = 1.19051 :::*/*/*/*/
[13:14:15.514] <TB2> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 160calibrated Vbg = 1.18838 :::*/*/*/*/
[13:14:15.514] <TB2> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 150.7calibrated Vbg = 1.19453 :::*/*/*/*/
[13:14:15.514] <TB2> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 161.4calibrated Vbg = 1.20397 :::*/*/*/*/
[13:14:15.514] <TB2> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 144.5calibrated Vbg = 1.20326 :::*/*/*/*/
[13:14:15.514] <TB2> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 165.9calibrated Vbg = 1.2057 :::*/*/*/*/
[13:14:15.514] <TB2> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 151.7calibrated Vbg = 1.20555 :::*/*/*/*/
[13:14:15.514] <TB2> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 145.3calibrated Vbg = 1.20729 :::*/*/*/*/
[13:14:15.514] <TB2> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 151.3calibrated Vbg = 1.20906 :::*/*/*/*/
[13:14:15.514] <TB2> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 151.4calibrated Vbg = 1.20382 :::*/*/*/*/
[13:14:15.514] <TB2> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 149.2calibrated Vbg = 1.21398 :::*/*/*/*/
[13:14:15.514] <TB2> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 154.7calibrated Vbg = 1.19936 :::*/*/*/*/
[13:14:15.514] <TB2> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 147.6calibrated Vbg = 1.19827 :::*/*/*/*/
[13:14:15.514] <TB2> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 146.2calibrated Vbg = 1.19696 :::*/*/*/*/
[13:14:15.514] <TB2> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 156calibrated Vbg = 1.19183 :::*/*/*/*/
[13:14:15.514] <TB2> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 168.6calibrated Vbg = 1.19051 :::*/*/*/*/
[13:14:15.518] <TB2> INFO: PixTestReadback::RES sent once
[13:17:09.503] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C0.dat
[13:17:09.504] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C1.dat
[13:17:09.504] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C2.dat
[13:17:09.504] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C3.dat
[13:17:09.504] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C4.dat
[13:17:09.504] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C5.dat
[13:17:09.504] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C6.dat
[13:17:09.504] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C7.dat
[13:17:09.504] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C8.dat
[13:17:09.504] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C9.dat
[13:17:09.505] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C10.dat
[13:17:09.505] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C11.dat
[13:17:09.505] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C12.dat
[13:17:09.505] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C13.dat
[13:17:09.505] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C14.dat
[13:17:09.505] <TB2> INFO: write readback calibration parameters into /usr/local/receptionDATA/M3512_ModuleQualificationINFN_2015-11-03_10h35m_1446543354//002_FulltestPxar_m20//readbackCal_C15.dat
[13:17:09.536] <TB2> INFO: PixTestPattern:: pg_setup set to default.
[13:17:09.537] <TB2> INFO: PixTestReadback::doTest() done
[13:17:09.537] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:17:09.537] <TB2> INFO: Decoding statistics:
[13:17:09.537] <TB2> INFO: General information:
[13:17:09.537] <TB2> INFO: 16bit words read: 768
[13:17:09.537] <TB2> INFO: valid events total: 64
[13:17:09.537] <TB2> INFO: empty events: 64
[13:17:09.537] <TB2> INFO: valid events with pixels: 0
[13:17:09.537] <TB2> INFO: valid pixel hits: 0
[13:17:09.537] <TB2> INFO: Event errors: 0
[13:17:09.537] <TB2> INFO: start marker: 0
[13:17:09.537] <TB2> INFO: stop marker: 0
[13:17:09.537] <TB2> INFO: overflow: 0
[13:17:09.537] <TB2> INFO: invalid 5bit words: 0
[13:17:09.537] <TB2> INFO: invalid XOR eye diagram: 0
[13:17:09.537] <TB2> INFO: TBM errors: 0
[13:17:09.537] <TB2> INFO: flawed TBM headers: 0
[13:17:09.537] <TB2> INFO: flawed TBM trailers: 0
[13:17:09.537] <TB2> INFO: event ID mismatches: 0
[13:17:09.537] <TB2> INFO: ROC errors: 0
[13:17:09.537] <TB2> INFO: missing ROC header(s): 0
[13:17:09.537] <TB2> INFO: misplaced readback start: 0
[13:17:09.537] <TB2> INFO: Pixel decoding errors: 0
[13:17:09.537] <TB2> INFO: pixel data incomplete: 0
[13:17:09.537] <TB2> INFO: pixel address: 0
[13:17:09.537] <TB2> INFO: pulse height fill bit: 0
[13:17:09.537] <TB2> INFO: buffer corruption: 0
[13:17:09.553] <TB2> INFO: Decoding statistics:
[13:17:09.553] <TB2> INFO: General information:
[13:17:09.553] <TB2> INFO: 16bit words read: 2396410
[13:17:09.553] <TB2> INFO: valid events total: 88384
[13:17:09.553] <TB2> INFO: empty events: 2726
[13:17:09.553] <TB2> INFO: valid events with pixels: 85658
[13:17:09.553] <TB2> INFO: valid pixel hits: 667901
[13:17:09.553] <TB2> INFO: Event errors: 0
[13:17:09.553] <TB2> INFO: start marker: 0
[13:17:09.553] <TB2> INFO: stop marker: 0
[13:17:09.553] <TB2> INFO: overflow: 0
[13:17:09.553] <TB2> INFO: invalid 5bit words: 0
[13:17:09.553] <TB2> INFO: invalid XOR eye diagram: 0
[13:17:09.553] <TB2> INFO: TBM errors: 0
[13:17:09.554] <TB2> INFO: flawed TBM headers: 0
[13:17:09.554] <TB2> INFO: flawed TBM trailers: 0
[13:17:09.554] <TB2> INFO: event ID mismatches: 0
[13:17:09.554] <TB2> INFO: ROC errors: 0
[13:17:09.554] <TB2> INFO: missing ROC header(s): 0
[13:17:09.554] <TB2> INFO: misplaced readback start: 0
[13:17:09.554] <TB2> INFO: Pixel decoding errors: 0
[13:17:09.554] <TB2> INFO: pixel data incomplete: 0
[13:17:09.554] <TB2> INFO: pixel address: 0
[13:17:09.554] <TB2> INFO: pulse height fill bit: 0
[13:17:09.554] <TB2> INFO: buffer corruption: 0
[13:17:09.554] <TB2> INFO: enter test to run
[13:17:09.554] <TB2> INFO: test: exit no parameter change
[13:17:09.768] <TB2> QUIET: Connection to board 156 closed.
[13:17:09.855] <TB2> INFO: pXar: this is the end, my friend